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mlx4_core: Fix meaning of dev->caps.reserved_mtts
[linux-2.6-block.git] / drivers / net / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
41
42#include <linux/mlx4/device.h>
43#include <linux/mlx4/doorbell.h>
44
45#include "mlx4.h"
46#include "fw.h"
47#include "icm.h"
48
49MODULE_AUTHOR("Roland Dreier");
50MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51MODULE_LICENSE("Dual BSD/GPL");
52MODULE_VERSION(DRV_VERSION);
53
54#ifdef CONFIG_MLX4_DEBUG
55
56int mlx4_debug_level = 0;
57module_param_named(debug_level, mlx4_debug_level, int, 0644);
58MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
59
60#endif /* CONFIG_MLX4_DEBUG */
61
62#ifdef CONFIG_PCI_MSI
63
08fb1055 64static int msi_x = 1;
225c7b1f
RD		 65module_param(msi_x, int, 0444);
66MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
67
68#else /* CONFIG_PCI_MSI */
69
70#define msi_x (0)
71
72#endif /* CONFIG_PCI_MSI */
73
74static const char mlx4_version[] __devinitdata =
75 DRV_NAME ": Mellanox ConnectX core driver v"
76 DRV_VERSION " (" DRV_RELDATE ")\n";
77
78static struct mlx4_profile default_profile = {
79 .num_qp = 1 << 16,
80 .num_srq = 1 << 16,
c9f2ba5e 81 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 82 .num_cq = 1 << 16,
83 .num_mcg = 1 << 13,
84 .num_mpt = 1 << 17,
85 .num_mtt = 1 << 20,
86};
87
88static int __devinit mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
89{
90 int err;
5ae2a7a8 91 int i;
225c7b1f
RD		 92
93 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
94 if (err) {
95 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
96 return err;
97 }
98
99 if (dev_cap->min_page_sz > PAGE_SIZE) {
100 mlx4_err(dev, "HCA minimum page size of %d bigger than "
101 "kernel PAGE_SIZE of %ld, aborting.\n",
102 dev_cap->min_page_sz, PAGE_SIZE);
103 return -ENODEV;
104 }
105 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
106 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
107 "aborting.\n",
108 dev_cap->num_ports, MLX4_MAX_PORTS);
109 return -ENODEV;
110 }
111
112 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
113 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
114 "PCI resource 2 size of 0x%llx, aborting.\n",
115 dev_cap->uar_size,
116 (unsigned long long) pci_resource_len(dev->pdev, 2));
117 return -ENODEV;
118 }
119
120 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 121 for (i = 1; i <= dev->caps.num_ports; ++i) {
122 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
123 dev->caps.mtu_cap[i] = dev_cap->max_mtu[i];
124 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
125 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
126 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
127 }
128
225c7b1f 129 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 130 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
131 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
132 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
133 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
134 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
135 dev->caps.max_wqes = dev_cap->max_qp_sz;
136 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
137 dev->caps.reserved_qps = dev_cap->reserved_qps;
138 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
139 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
140 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
141 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
142 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
143 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
144 /*
145 * Subtract 1 from the limit because we need to allocate a
146 * spare CQE so the HCA HW can tell the difference between an
147 * empty CQ and a full CQ.
148 */
149 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
150 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
151 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
121964ec
RD		 152 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
153 MLX4_MTT_ENTRY_PER_SEG);
225c7b1f
RD		 154 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
155 dev->caps.reserved_uars = dev_cap->reserved_uars;
156 dev->caps.reserved_pds = dev_cap->reserved_pds;
225c7b1f 157 dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
149983af 158 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 159 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
160 dev->caps.flags = dev_cap->flags;
161 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
162
163 return 0;
164}
165
166static int __devinit mlx4_load_fw(struct mlx4_dev *dev)
167{
168 struct mlx4_priv *priv = mlx4_priv(dev);
169 int err;
170
171 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 172 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 173 if (!priv->fw.fw_icm) {
174 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
175 return -ENOMEM;
176 }
177
178 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
179 if (err) {
180 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
181 goto err_free;
182 }
183
184 err = mlx4_RUN_FW(dev);
185 if (err) {
186 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
187 goto err_unmap_fa;
188 }
189
190 return 0;
191
192err_unmap_fa:
193 mlx4_UNMAP_FA(dev);
194
195err_free:
5b0bf5e2 196 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 197 return err;
198}
199
200static int __devinit mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
201 int cmpt_entry_sz)
202{
203 struct mlx4_priv *priv = mlx4_priv(dev);
204 int err;
205
206 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
207 cmpt_base +
208 ((u64) (MLX4_CMPT_TYPE_QP *
209 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
210 cmpt_entry_sz, dev->caps.num_qps,
5b0bf5e2 211 dev->caps.reserved_qps, 0, 0);
225c7b1f
RD		 212 if (err)
213 goto err;
214
215 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
216 cmpt_base +
217 ((u64) (MLX4_CMPT_TYPE_SRQ *
218 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
219 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 220 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 221 if (err)
222 goto err_qp;
223
224 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
225 cmpt_base +
226 ((u64) (MLX4_CMPT_TYPE_CQ *
227 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
228 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 229 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 230 if (err)
231 goto err_srq;
232
233 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
234 cmpt_base +
235 ((u64) (MLX4_CMPT_TYPE_EQ *
236 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
237 cmpt_entry_sz,
238 roundup_pow_of_two(MLX4_NUM_EQ +
239 dev->caps.reserved_eqs),
5b0bf5e2 240 MLX4_NUM_EQ + dev->caps.reserved_eqs, 0, 0);
225c7b1f
RD		 241 if (err)
242 goto err_cq;
243
244 return 0;
245
246err_cq:
247 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
248
249err_srq:
250 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
251
252err_qp:
253 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
254
255err:
256 return err;
257}
258
259static int __devinit mlx4_init_icm(struct mlx4_dev *dev,
260 struct mlx4_dev_cap *dev_cap,
261 struct mlx4_init_hca_param *init_hca,
262 u64 icm_size)
263{
264 struct mlx4_priv *priv = mlx4_priv(dev);
265 u64 aux_pages;
266 int err;
267
268 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
269 if (err) {
270 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
271 return err;
272 }
273
274 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
275 (unsigned long long) icm_size >> 10,
276 (unsigned long long) aux_pages << 2);
277
278 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 279 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 280 if (!priv->fw.aux_icm) {
281 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
282 return -ENOMEM;
283 }
284
285 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
286 if (err) {
287 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
288 goto err_free_aux;
289 }
290
291 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
292 if (err) {
293 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
294 goto err_unmap_aux;
295 }
296
297 err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
298 if (err) {
299 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
300 goto err_unmap_cmpt;
301 }
302
303 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
304 init_hca->mtt_base,
305 dev->caps.mtt_entry_sz,
306 dev->caps.num_mtt_segs,
5b0bf5e2 307 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 308 if (err) {
309 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
310 goto err_unmap_eq;
311 }
312
313 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
314 init_hca->dmpt_base,
315 dev_cap->dmpt_entry_sz,
316 dev->caps.num_mpts,
5b0bf5e2 317 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 318 if (err) {
319 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
320 goto err_unmap_mtt;
321 }
322
323 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
324 init_hca->qpc_base,
325 dev_cap->qpc_entry_sz,
326 dev->caps.num_qps,
5b0bf5e2 327 dev->caps.reserved_qps, 0, 0);
225c7b1f
RD		 328 if (err) {
329 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
330 goto err_unmap_dmpt;
331 }
332
333 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
334 init_hca->auxc_base,
335 dev_cap->aux_entry_sz,
336 dev->caps.num_qps,
5b0bf5e2 337 dev->caps.reserved_qps, 0, 0);
225c7b1f
RD		 338 if (err) {
339 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
340 goto err_unmap_qp;
341 }
342
343 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
344 init_hca->altc_base,
345 dev_cap->altc_entry_sz,
346 dev->caps.num_qps,
5b0bf5e2 347 dev->caps.reserved_qps, 0, 0);
225c7b1f
RD		 348 if (err) {
349 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
350 goto err_unmap_auxc;
351 }
352
353 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
354 init_hca->rdmarc_base,
355 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
356 dev->caps.num_qps,
5b0bf5e2 357 dev->caps.reserved_qps, 0, 0);
225c7b1f
RD		 358 if (err) {
359 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
360 goto err_unmap_altc;
361 }
362
363 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
364 init_hca->cqc_base,
365 dev_cap->cqc_entry_sz,
366 dev->caps.num_cqs,
5b0bf5e2 367 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 368 if (err) {
369 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
370 goto err_unmap_rdmarc;
371 }
372
373 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
374 init_hca->srqc_base,
375 dev_cap->srq_entry_sz,
376 dev->caps.num_srqs,
5b0bf5e2 377 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 378 if (err) {
379 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
380 goto err_unmap_cq;
381 }
382
383 /*
384 * It's not strictly required, but for simplicity just map the
385 * whole multicast group table now. The table isn't very big
386 * and it's a lot easier than trying to track ref counts.
387 */
388 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
389 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
390 dev->caps.num_mgms + dev->caps.num_amgms,
391 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 392 0, 0);
225c7b1f
RD		 393 if (err) {
394 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
395 goto err_unmap_srq;
396 }
397
398 return 0;
399
400err_unmap_srq:
401 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
402
403err_unmap_cq:
404 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
405
406err_unmap_rdmarc:
407 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
408
409err_unmap_altc:
410 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
411
412err_unmap_auxc:
413 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
414
415err_unmap_qp:
416 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
417
418err_unmap_dmpt:
419 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
420
421err_unmap_mtt:
422 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
423
424err_unmap_eq:
425 mlx4_unmap_eq_icm(dev);
426
427err_unmap_cmpt:
428 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
429 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
430 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
431 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
432
433err_unmap_aux:
434 mlx4_UNMAP_ICM_AUX(dev);
435
436err_free_aux:
5b0bf5e2 437 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 438
439 return err;
440}
441
442static void mlx4_free_icms(struct mlx4_dev *dev)
443{
444 struct mlx4_priv *priv = mlx4_priv(dev);
445
446 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
447 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
448 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
449 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
450 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
451 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
452 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
453 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
454 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
455 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
456 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
457 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
458 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
459 mlx4_unmap_eq_icm(dev);
460
461 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 462 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 463}
464
465static void mlx4_close_hca(struct mlx4_dev *dev)
466{
467 mlx4_CLOSE_HCA(dev, 0);
468 mlx4_free_icms(dev);
469 mlx4_UNMAP_FA(dev);
5b0bf5e2 470 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
225c7b1f
RD		 471}
472
473static int __devinit mlx4_init_hca(struct mlx4_dev *dev)
474{
475 struct mlx4_priv *priv = mlx4_priv(dev);
476 struct mlx4_adapter adapter;
477 struct mlx4_dev_cap dev_cap;
478 struct mlx4_profile profile;
479 struct mlx4_init_hca_param init_hca;
480 u64 icm_size;
481 int err;
482
483 err = mlx4_QUERY_FW(dev);
484 if (err) {
485 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
486 return err;
487 }
488
489 err = mlx4_load_fw(dev);
490 if (err) {
491 mlx4_err(dev, "Failed to start FW, aborting.\n");
492 return err;
493 }
494
495 err = mlx4_dev_cap(dev, &dev_cap);
496 if (err) {
497 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
498 goto err_stop_fw;
499 }
500
501 profile = default_profile;
502
503 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
504 if ((long long) icm_size < 0) {
505 err = icm_size;
506 goto err_stop_fw;
507 }
508
509 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
510
511 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
512 if (err)
513 goto err_stop_fw;
514
515 err = mlx4_INIT_HCA(dev, &init_hca);
516 if (err) {
517 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
518 goto err_free_icm;
519 }
520
521 err = mlx4_QUERY_ADAPTER(dev, &adapter);
522 if (err) {
523 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
524 goto err_close;
525 }
526
527 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8
JM		 528 dev->rev_id = adapter.revision_id;
529 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 530
531 return 0;
532
533err_close:
534 mlx4_close_hca(dev);
535
536err_free_icm:
537 mlx4_free_icms(dev);
538
539err_stop_fw:
540 mlx4_UNMAP_FA(dev);
5b0bf5e2 541 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 542
543 return err;
544}
545
546static int __devinit mlx4_setup_hca(struct mlx4_dev *dev)
547{
548 struct mlx4_priv *priv = mlx4_priv(dev);
549 int err;
550
225c7b1f
RD		 551 err = mlx4_init_uar_table(dev);
552 if (err) {
553 mlx4_err(dev, "Failed to initialize "
554 "user access region table, aborting.\n");
555 return err;
556 }
557
558 err = mlx4_uar_alloc(dev, &priv->driver_uar);
559 if (err) {
560 mlx4_err(dev, "Failed to allocate driver access region, "
561 "aborting.\n");
562 goto err_uar_table_free;
563 }
564
565 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
566 if (!priv->kar) {
567 mlx4_err(dev, "Couldn't map kernel access region, "
568 "aborting.\n");
569 err = -ENOMEM;
570 goto err_uar_free;
571 }
572
573 err = mlx4_init_pd_table(dev);
574 if (err) {
575 mlx4_err(dev, "Failed to initialize "
576 "protection domain table, aborting.\n");
577 goto err_kar_unmap;
578 }
579
580 err = mlx4_init_mr_table(dev);
581 if (err) {
582 mlx4_err(dev, "Failed to initialize "
583 "memory region table, aborting.\n");
584 goto err_pd_table_free;
585 }
586
225c7b1f
RD		 587 err = mlx4_init_eq_table(dev);
588 if (err) {
589 mlx4_err(dev, "Failed to initialize "
590 "event queue table, aborting.\n");
ee49bd93 591 goto err_mr_table_free;
225c7b1f
RD		 592 }
593
594 err = mlx4_cmd_use_events(dev);
595 if (err) {
596 mlx4_err(dev, "Failed to switch to event-driven "
597 "firmware commands, aborting.\n");
598 goto err_eq_table_free;
599 }
600
601 err = mlx4_NOP(dev);
602 if (err) {
08fb1055
MT		 603 if (dev->flags & MLX4_FLAG_MSI_X) {
604 mlx4_warn(dev, "NOP command failed to generate MSI-X "
605 "interrupt IRQ %d).\n",
606 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
607 mlx4_warn(dev, "Trying again without MSI-X.\n");
608 } else {
609 mlx4_err(dev, "NOP command failed to generate interrupt "
610 "(IRQ %d), aborting.\n",
611 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 612 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 613 }
225c7b1f
RD		 614
615 goto err_cmd_poll;
616 }
617
618 mlx4_dbg(dev, "NOP command IRQ test passed\n");
619
620 err = mlx4_init_cq_table(dev);
621 if (err) {
622 mlx4_err(dev, "Failed to initialize "
623 "completion queue table, aborting.\n");
624 goto err_cmd_poll;
625 }
626
627 err = mlx4_init_srq_table(dev);
628 if (err) {
629 mlx4_err(dev, "Failed to initialize "
630 "shared receive queue table, aborting.\n");
631 goto err_cq_table_free;
632 }
633
634 err = mlx4_init_qp_table(dev);
635 if (err) {
636 mlx4_err(dev, "Failed to initialize "
637 "queue pair table, aborting.\n");
638 goto err_srq_table_free;
639 }
640
641 err = mlx4_init_mcg_table(dev);
642 if (err) {
643 mlx4_err(dev, "Failed to initialize "
644 "multicast group table, aborting.\n");
645 goto err_qp_table_free;
646 }
647
648 return 0;
649
650err_qp_table_free:
651 mlx4_cleanup_qp_table(dev);
652
653err_srq_table_free:
654 mlx4_cleanup_srq_table(dev);
655
656err_cq_table_free:
657 mlx4_cleanup_cq_table(dev);
658
659err_cmd_poll:
660 mlx4_cmd_use_polling(dev);
661
662err_eq_table_free:
663 mlx4_cleanup_eq_table(dev);
664
ee49bd93 665err_mr_table_free:
225c7b1f
RD		 666 mlx4_cleanup_mr_table(dev);
667
668err_pd_table_free:
669 mlx4_cleanup_pd_table(dev);
670
671err_kar_unmap:
672 iounmap(priv->kar);
673
674err_uar_free:
675 mlx4_uar_free(dev, &priv->driver_uar);
676
677err_uar_table_free:
678 mlx4_cleanup_uar_table(dev);
679 return err;
680}
681
682static void __devinit mlx4_enable_msi_x(struct mlx4_dev *dev)
683{
684 struct mlx4_priv *priv = mlx4_priv(dev);
685 struct msix_entry entries[MLX4_NUM_EQ];
686 int err;
687 int i;
688
689 if (msi_x) {
690 for (i = 0; i < MLX4_NUM_EQ; ++i)
691 entries[i].entry = i;
692
693 err = pci_enable_msix(dev->pdev, entries, ARRAY_SIZE(entries));
694 if (err) {
695 if (err > 0)
696 mlx4_info(dev, "Only %d MSI-X vectors available, "
697 "not using MSI-X\n", err);
698 goto no_msi;
699 }
700
701 for (i = 0; i < MLX4_NUM_EQ; ++i)
702 priv->eq_table.eq[i].irq = entries[i].vector;
703
704 dev->flags |= MLX4_FLAG_MSI_X;
705 return;
706 }
707
708no_msi:
709 for (i = 0; i < MLX4_NUM_EQ; ++i)
710 priv->eq_table.eq[i].irq = dev->pdev->irq;
711}
712
713static int __devinit mlx4_init_one(struct pci_dev *pdev,
714 const struct pci_device_id *id)
715{
716 static int mlx4_version_printed;
717 struct mlx4_priv *priv;
718 struct mlx4_dev *dev;
719 int err;
720
721 if (!mlx4_version_printed) {
722 printk(KERN_INFO "%s", mlx4_version);
723 ++mlx4_version_printed;
724 }
725
726 printk(KERN_INFO PFX "Initializing %s\n",
727 pci_name(pdev));
728
729 err = pci_enable_device(pdev);
730 if (err) {
731 dev_err(&pdev->dev, "Cannot enable PCI device, "
732 "aborting.\n");
733 return err;
734 }
735
736 /*
737 * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
738 * be present)
739 */
740 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
741 pci_resource_len(pdev, 0) != 1 << 20) {
742 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
743 err = -ENODEV;
744 goto err_disable_pdev;
745 }
746 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
747 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
748 err = -ENODEV;
749 goto err_disable_pdev;
750 }
751
752 err = pci_request_region(pdev, 0, DRV_NAME);
753 if (err) {
754 dev_err(&pdev->dev, "Cannot request control region, aborting.\n");
755 goto err_disable_pdev;
756 }
757
758 err = pci_request_region(pdev, 2, DRV_NAME);
759 if (err) {
760 dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n");
761 goto err_release_bar0;
762 }
763
764 pci_set_master(pdev);
765
766 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
767 if (err) {
768 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
769 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
770 if (err) {
771 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
772 goto err_release_bar2;
773 }
774 }
775 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
776 if (err) {
777 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
778 "consistent PCI DMA mask.\n");
779 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
780 if (err) {
781 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
782 "aborting.\n");
783 goto err_release_bar2;
784 }
785 }
786
787 priv = kzalloc(sizeof *priv, GFP_KERNEL);
788 if (!priv) {
789 dev_err(&pdev->dev, "Device struct alloc failed, "
790 "aborting.\n");
791 err = -ENOMEM;
792 goto err_release_bar2;
793 }
794
795 dev = &priv->dev;
796 dev->pdev = pdev;
b581401e
RD		 797 INIT_LIST_HEAD(&priv->ctx_list);
798 spin_lock_init(&priv->ctx_lock);
225c7b1f
RD		 799
800 /*
801 * Now reset the HCA before we touch the PCI capabilities or
802 * attempt a firmware command, since a boot ROM may have left
803 * the HCA in an undefined state.
804 */
805 err = mlx4_reset(dev);
806 if (err) {
807 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
808 goto err_free_dev;
809 }
810
225c7b1f
RD		 811 if (mlx4_cmd_init(dev)) {
812 mlx4_err(dev, "Failed to init command interface, aborting.\n");
813 goto err_free_dev;
814 }
815
816 err = mlx4_init_hca(dev);
817 if (err)
818 goto err_cmd;
819
08fb1055
MT		 820 mlx4_enable_msi_x(dev);
821
225c7b1f 822 err = mlx4_setup_hca(dev);
08fb1055
MT		 823 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
824 dev->flags &= ~MLX4_FLAG_MSI_X;
825 pci_disable_msix(pdev);
826 err = mlx4_setup_hca(dev);
827 }
828
225c7b1f
RD		 829 if (err)
830 goto err_close;
831
832 err = mlx4_register_device(dev);
833 if (err)
834 goto err_cleanup;
835
836 pci_set_drvdata(pdev, dev);
837
838 return 0;
839
840err_cleanup:
841 mlx4_cleanup_mcg_table(dev);
842 mlx4_cleanup_qp_table(dev);
843 mlx4_cleanup_srq_table(dev);
844 mlx4_cleanup_cq_table(dev);
845 mlx4_cmd_use_polling(dev);
846 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 847 mlx4_cleanup_mr_table(dev);
848 mlx4_cleanup_pd_table(dev);
849 mlx4_cleanup_uar_table(dev);
850
851err_close:
08fb1055
MT		 852 if (dev->flags & MLX4_FLAG_MSI_X)
853 pci_disable_msix(pdev);
854
225c7b1f
RD		 855 mlx4_close_hca(dev);
856
857err_cmd:
858 mlx4_cmd_cleanup(dev);
859
860err_free_dev:
225c7b1f
RD		 861 kfree(priv);
862
863err_release_bar2:
864 pci_release_region(pdev, 2);
865
866err_release_bar0:
867 pci_release_region(pdev, 0);
868
869err_disable_pdev:
870 pci_disable_device(pdev);
871 pci_set_drvdata(pdev, NULL);
872 return err;
873}
874
875static void __devexit mlx4_remove_one(struct pci_dev *pdev)
876{
877 struct mlx4_dev *dev = pci_get_drvdata(pdev);
878 struct mlx4_priv *priv = mlx4_priv(dev);
879 int p;
880
881 if (dev) {
882 mlx4_unregister_device(dev);
883
884 for (p = 1; p <= dev->caps.num_ports; ++p)
885 mlx4_CLOSE_PORT(dev, p);
886
887 mlx4_cleanup_mcg_table(dev);
888 mlx4_cleanup_qp_table(dev);
889 mlx4_cleanup_srq_table(dev);
890 mlx4_cleanup_cq_table(dev);
891 mlx4_cmd_use_polling(dev);
892 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 893 mlx4_cleanup_mr_table(dev);
894 mlx4_cleanup_pd_table(dev);
895
896 iounmap(priv->kar);
897 mlx4_uar_free(dev, &priv->driver_uar);
898 mlx4_cleanup_uar_table(dev);
899 mlx4_close_hca(dev);
900 mlx4_cmd_cleanup(dev);
901
902 if (dev->flags & MLX4_FLAG_MSI_X)
903 pci_disable_msix(pdev);
904
905 kfree(priv);
906 pci_release_region(pdev, 2);
907 pci_release_region(pdev, 0);
908 pci_disable_device(pdev);
909 pci_set_drvdata(pdev, NULL);
910 }
911}
912
ee49bd93
JM		 913int mlx4_restart_one(struct pci_dev *pdev)
914{
915 mlx4_remove_one(pdev);
916 return mlx4_init_one(pdev, NULL);
917}
918
225c7b1f
RD		 919static struct pci_device_id mlx4_pci_table[] = {
920 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
921 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
922 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
786f238e
JM		 923 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
924 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
225c7b1f
RD		 925 { 0, }
926};
927
928MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
929
930static struct pci_driver mlx4_driver = {
931 .name = DRV_NAME,
932 .id_table = mlx4_pci_table,
933 .probe = mlx4_init_one,
934 .remove = __devexit_p(mlx4_remove_one)
935};
936
937static int __init mlx4_init(void)
938{
939 int ret;
940
ee49bd93
JM		 941 ret = mlx4_catas_init();
942 if (ret)
943 return ret;
944
225c7b1f
RD		 945 ret = pci_register_driver(&mlx4_driver);
946 return ret < 0 ? ret : 0;
947}
948
949static void __exit mlx4_cleanup(void)
950{
951 pci_unregister_driver(&mlx4_driver);
ee49bd93 952 mlx4_catas_cleanup();
225c7b1f
RD		 953}
954
955module_init(mlx4_init);
956module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)