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Merge git://git.linux-nfs.org/projects/trondmy/nfs-2.6
[linux-2.6-block.git] / drivers / net / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/mlx4/cmd.h>
36
37#include "fw.h"
38#include "icm.h"
39
fe40900f 40enum {
5ae2a7a8
RD		 41 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
42 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
43 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 44};
45
225c7b1f
RD		 46extern void __buggy_use_of_MLX4_GET(void);
47extern void __buggy_use_of_MLX4_PUT(void);
48
51f5f0ee
JM		 49static int enable_qos;
50module_param(enable_qos, bool, 0444);
51MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
52
225c7b1f
RD		 53#define MLX4_GET(dest, source, offset) \
54 do { \
55 void *__p = (char *) (source) + (offset); \
56 switch (sizeof (dest)) { \
57 case 1: (dest) = *(u8 *) __p; break; \
58 case 2: (dest) = be16_to_cpup(__p); break; \
59 case 4: (dest) = be32_to_cpup(__p); break; \
60 case 8: (dest) = be64_to_cpup(__p); break; \
61 default: __buggy_use_of_MLX4_GET(); \
62 } \
63 } while (0)
64
65#define MLX4_PUT(dest, source, offset) \
66 do { \
67 void *__d = ((char *) (dest) + (offset)); \
68 switch (sizeof(source)) { \
69 case 1: *(u8 *) __d = (source); break; \
70 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
71 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
72 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
73 default: __buggy_use_of_MLX4_PUT(); \
74 } \
75 } while (0)
76
77static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
78{
79 static const char *fname[] = {
80 [ 0] = "RC transport",
81 [ 1] = "UC transport",
82 [ 2] = "UD transport",
ea98054f 83 [ 3] = "XRC transport",
225c7b1f
RD		 84 [ 4] = "reliable multicast",
85 [ 5] = "FCoIB support",
86 [ 6] = "SRQ support",
87 [ 7] = "IPoIB checksum offload",
88 [ 8] = "P_Key violation counter",
89 [ 9] = "Q_Key violation counter",
90 [10] = "VMM",
7ff93f8b 91 [12] = "DPDP",
225c7b1f
RD		 92 [16] = "MW support",
93 [17] = "APM support",
94 [18] = "Atomic ops support",
95 [19] = "Raw multicast support",
96 [20] = "Address vector port checking support",
97 [21] = "UD multicast support",
98 [24] = "Demand paging support",
99 [25] = "Router support"
100 };
101 int i;
102
103 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 104 for (i = 0; i < ARRAY_SIZE(fname); ++i)
225c7b1f
RD		 105 if (fname[i] && (flags & (1 << i)))
106 mlx4_dbg(dev, " %s\n", fname[i]);
107}
108
2d928651
VS		 109int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
110{
111 struct mlx4_cmd_mailbox *mailbox;
112 u32 *inbox;
113 int err = 0;
114
115#define MOD_STAT_CFG_IN_SIZE 0x100
116
117#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
118#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
119
120 mailbox = mlx4_alloc_cmd_mailbox(dev);
121 if (IS_ERR(mailbox))
122 return PTR_ERR(mailbox);
123 inbox = mailbox->buf;
124
125 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
126
127 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
128 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
129
130 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
131 MLX4_CMD_TIME_CLASS_A);
132
133 mlx4_free_cmd_mailbox(dev, mailbox);
134 return err;
135}
136
225c7b1f
RD		 137int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
138{
139 struct mlx4_cmd_mailbox *mailbox;
140 u32 *outbox;
141 u8 field;
142 u16 size;
143 u16 stat_rate;
144 int err;
5ae2a7a8 145 int i;
225c7b1f
RD		 146
147#define QUERY_DEV_CAP_OUT_SIZE 0x100
148#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
149#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
150#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
151#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
152#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
153#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
154#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
155#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
156#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
157#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
158#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
159#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
160#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
161#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
162#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
163#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
164#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
165#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
166#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
167#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
168#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 169#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
225c7b1f
RD		 170#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
171#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
172#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
173#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
174#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 175#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 176#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
177#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
178#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
179#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
180#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
181#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
182#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
183#define QUERY_DEV_CAP_BF_OFFSET 0x4c
184#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
185#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
186#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
187#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
188#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
189#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
190#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
191#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
192#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
193#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
194#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
195#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
196#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
197#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
198#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
199#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
200#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
201#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
202#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
203#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
204#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
205#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 206#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 207#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
208#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
209
210 mailbox = mlx4_alloc_cmd_mailbox(dev);
211 if (IS_ERR(mailbox))
212 return PTR_ERR(mailbox);
213 outbox = mailbox->buf;
214
215 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
216 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 217 if (err)
218 goto out;
219
220 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
221 dev_cap->reserved_qps = 1 << (field & 0xf);
222 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
223 dev_cap->max_qps = 1 << (field & 0x1f);
224 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
225 dev_cap->reserved_srqs = 1 << (field >> 4);
226 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
227 dev_cap->max_srqs = 1 << (field & 0x1f);
228 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
229 dev_cap->max_cq_sz = 1 << field;
230 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
231 dev_cap->reserved_cqs = 1 << (field & 0xf);
232 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
233 dev_cap->max_cqs = 1 << (field & 0x1f);
234 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
235 dev_cap->max_mpts = 1 << (field & 0x3f);
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
237 dev_cap->reserved_eqs = 1 << (field & 0xf);
238 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 239 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 240 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
241 dev_cap->reserved_mtts = 1 << (field >> 4);
242 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
243 dev_cap->max_mrw_sz = 1 << field;
244 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
245 dev_cap->reserved_mrws = 1 << (field & 0xf);
246 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
247 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
248 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
249 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
250 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
251 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 252 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
253 field &= 0x1f;
254 if (!field)
255 dev_cap->max_gso_sz = 0;
256 else
257 dev_cap->max_gso_sz = 1 << field;
258
225c7b1f
RD		 259 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
260 dev_cap->max_rdma_global = 1 << (field & 0x3f);
261 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
262 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 263 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 264 dev_cap->num_ports = field & 0xf;
149983af
DB		 265 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
266 dev_cap->max_msg_sz = 1 << (field & 0x1f);
225c7b1f
RD		 267 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
268 dev_cap->stat_rate_support = stat_rate;
225c7b1f
RD		 269 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
270 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
271 dev_cap->reserved_uars = field >> 4;
272 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
273 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
274 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
275 dev_cap->min_page_sz = 1 << field;
276
277 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
278 if (field & 0x80) {
279 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
280 dev_cap->bf_reg_size = 1 << (field & 0x1f);
281 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
282 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
283 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
284 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
285 } else {
286 dev_cap->bf_reg_size = 0;
287 mlx4_dbg(dev, "BlueFlame not available\n");
288 }
289
290 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
291 dev_cap->max_sq_sg = field;
292 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
293 dev_cap->max_sq_desc_sz = size;
294
295 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
296 dev_cap->max_qp_per_mcg = 1 << field;
297 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
298 dev_cap->reserved_mgms = field & 0xf;
299 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
300 dev_cap->max_mcgs = 1 << field;
301 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
302 dev_cap->reserved_pds = field >> 4;
303 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
304 dev_cap->max_pds = 1 << (field & 0x3f);
305
306 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
307 dev_cap->rdmarc_entry_sz = size;
308 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
309 dev_cap->qpc_entry_sz = size;
310 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
311 dev_cap->aux_entry_sz = size;
312 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
313 dev_cap->altc_entry_sz = size;
314 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
315 dev_cap->eqc_entry_sz = size;
316 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
317 dev_cap->cqc_entry_sz = size;
318 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
319 dev_cap->srq_entry_sz = size;
320 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
321 dev_cap->cmpt_entry_sz = size;
322 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
323 dev_cap->mtt_entry_sz = size;
324 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
325 dev_cap->dmpt_entry_sz = size;
326
327 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
328 dev_cap->max_srq_sz = 1 << field;
329 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
330 dev_cap->max_qp_sz = 1 << field;
331 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
332 dev_cap->resize_srq = field & 1;
333 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
334 dev_cap->max_rq_sg = field;
335 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
336 dev_cap->max_rq_desc_sz = size;
337
338 MLX4_GET(dev_cap->bmme_flags, outbox,
339 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
340 MLX4_GET(dev_cap->reserved_lkey, outbox,
341 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
342 MLX4_GET(dev_cap->max_icm_sz, outbox,
343 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
344
5ae2a7a8
RD		 345 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
346 for (i = 1; i <= dev_cap->num_ports; ++i) {
347 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
348 dev_cap->max_vl[i] = field >> 4;
349 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 350 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 351 dev_cap->max_port_width[i] = field & 0xf;
352 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
353 dev_cap->max_gids[i] = 1 << (field & 0xf);
354 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
355 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
356 }
357 } else {
7ff93f8b 358#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 359#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 360#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 361#define QUERY_PORT_WIDTH_OFFSET 0x06
362#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 363#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 364#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 365#define QUERY_PORT_MAC_OFFSET 0x10
5ae2a7a8
RD		 366
367 for (i = 1; i <= dev_cap->num_ports; ++i) {
368 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
369 MLX4_CMD_TIME_CLASS_B);
370 if (err)
371 goto out;
372
7ff93f8b
YP		 373 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
374 dev_cap->supported_port_types[i] = field & 3;
5ae2a7a8 375 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 376 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 377 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
378 dev_cap->max_port_width[i] = field & 0xf;
379 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
380 dev_cap->max_gids[i] = 1 << (field >> 4);
381 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
382 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
383 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 384 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
385 dev_cap->log_max_macs[i] = field & 0xf;
386 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 387 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
388 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
5ae2a7a8
RD		 389 }
390 }
391
95d04f07
RD		 392 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
393 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 394
395 /*
396 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
397 * we can't use any EQs whose doorbell falls on that page,
398 * even if the EQ itself isn't reserved.
399 */
400 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
401 dev_cap->reserved_eqs);
402
403 mlx4_dbg(dev, "Max ICM size %lld MB\n",
404 (unsigned long long) dev_cap->max_icm_sz >> 20);
405 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
406 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
407 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
408 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
409 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
410 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
411 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
412 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
413 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
414 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
415 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
416 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
417 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
418 dev_cap->max_pds, dev_cap->reserved_mgms);
419 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
420 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
421 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 422 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 423 dev_cap->max_port_width[1]);
225c7b1f
RD		 424 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
425 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
426 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
427 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 428 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
225c7b1f
RD		 429
430 dump_dev_cap_flags(dev, dev_cap->flags);
431
432out:
433 mlx4_free_cmd_mailbox(dev, mailbox);
434 return err;
435}
436
437int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
438{
439 struct mlx4_cmd_mailbox *mailbox;
440 struct mlx4_icm_iter iter;
441 __be64 *pages;
442 int lg;
443 int nent = 0;
444 int i;
445 int err = 0;
446 int ts = 0, tc = 0;
447
448 mailbox = mlx4_alloc_cmd_mailbox(dev);
449 if (IS_ERR(mailbox))
450 return PTR_ERR(mailbox);
451 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
452 pages = mailbox->buf;
453
454 for (mlx4_icm_first(icm, &iter);
455 !mlx4_icm_last(&iter);
456 mlx4_icm_next(&iter)) {
457 /*
458 * We have to pass pages that are aligned to their
459 * size, so find the least significant 1 in the
460 * address or size and use that as our log2 size.
461 */
462 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
463 if (lg < MLX4_ICM_PAGE_SHIFT) {
464 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
465 MLX4_ICM_PAGE_SIZE,
466 (unsigned long long) mlx4_icm_addr(&iter),
467 mlx4_icm_size(&iter));
468 err = -EINVAL;
469 goto out;
470 }
471
472 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
473 if (virt != -1) {
474 pages[nent * 2] = cpu_to_be64(virt);
475 virt += 1 << lg;
476 }
477
478 pages[nent * 2 + 1] =
479 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
480 (lg - MLX4_ICM_PAGE_SHIFT));
481 ts += 1 << (lg - 10);
482 ++tc;
483
484 if (++nent == MLX4_MAILBOX_SIZE / 16) {
485 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
486 MLX4_CMD_TIME_CLASS_B);
487 if (err)
488 goto out;
489 nent = 0;
490 }
491 }
492 }
493
494 if (nent)
495 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
496 if (err)
497 goto out;
498
499 switch (op) {
500 case MLX4_CMD_MAP_FA:
501 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
502 break;
503 case MLX4_CMD_MAP_ICM_AUX:
504 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
505 break;
506 case MLX4_CMD_MAP_ICM:
507 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
508 tc, ts, (unsigned long long) virt - (ts << 10));
509 break;
510 }
511
512out:
513 mlx4_free_cmd_mailbox(dev, mailbox);
514 return err;
515}
516
517int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
518{
519 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
520}
521
522int mlx4_UNMAP_FA(struct mlx4_dev *dev)
523{
524 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
525}
526
527
528int mlx4_RUN_FW(struct mlx4_dev *dev)
529{
530 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
531}
532
533int mlx4_QUERY_FW(struct mlx4_dev *dev)
534{
535 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
536 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
537 struct mlx4_cmd_mailbox *mailbox;
538 u32 *outbox;
539 int err = 0;
540 u64 fw_ver;
fe40900f 541 u16 cmd_if_rev;
225c7b1f
RD		 542 u8 lg;
543
544#define QUERY_FW_OUT_SIZE 0x100
545#define QUERY_FW_VER_OFFSET 0x00
fe40900f 546#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 547#define QUERY_FW_MAX_CMD_OFFSET 0x0f
548#define QUERY_FW_ERR_START_OFFSET 0x30
549#define QUERY_FW_ERR_SIZE_OFFSET 0x38
550#define QUERY_FW_ERR_BAR_OFFSET 0x3c
551
552#define QUERY_FW_SIZE_OFFSET 0x00
553#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
554#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
555
556 mailbox = mlx4_alloc_cmd_mailbox(dev);
557 if (IS_ERR(mailbox))
558 return PTR_ERR(mailbox);
559 outbox = mailbox->buf;
560
561 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
562 MLX4_CMD_TIME_CLASS_A);
563 if (err)
564 goto out;
565
566 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
567 /*
3e1db334 568 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 569 * version, so swap here.
570 */
571 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
572 ((fw_ver & 0xffff0000ull) >> 16) |
573 ((fw_ver & 0x0000ffffull) << 16);
574
fe40900f 575 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 576 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
577 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 578 mlx4_err(dev, "Installed FW has unsupported "
579 "command interface revision %d.\n",
580 cmd_if_rev);
581 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
582 (int) (dev->caps.fw_ver >> 32),
583 (int) (dev->caps.fw_ver >> 16) & 0xffff,
584 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 585 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
586 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 587 err = -ENODEV;
588 goto out;
589 }
590
5ae2a7a8
RD		 591 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
592 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
593
225c7b1f
RD		 594 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
595 cmd->max_cmds = 1 << lg;
596
fe40900f 597 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 598 (int) (dev->caps.fw_ver >> 32),
599 (int) (dev->caps.fw_ver >> 16) & 0xffff,
600 (int) dev->caps.fw_ver & 0xffff,
fe40900f 601 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 602
603 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
604 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
605 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
606 fw->catas_bar = (fw->catas_bar >> 6) * 2;
607
608 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
609 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
610
611 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
612 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
613 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
614 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
615
616 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
617
618 /*
619 * Round up number of system pages needed in case
620 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
621 */
622 fw->fw_pages =
623 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
624 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
625
626 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
627 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
628
629out:
630 mlx4_free_cmd_mailbox(dev, mailbox);
631 return err;
632}
633
634static void get_board_id(void *vsd, char *board_id)
635{
636 int i;
637
638#define VSD_OFFSET_SIG1 0x00
639#define VSD_OFFSET_SIG2 0xde
640#define VSD_OFFSET_MLX_BOARD_ID 0xd0
641#define VSD_OFFSET_TS_BOARD_ID 0x20
642
643#define VSD_SIGNATURE_TOPSPIN 0x5ad
644
645 memset(board_id, 0, MLX4_BOARD_ID_LEN);
646
647 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
648 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
649 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
650 } else {
651 /*
652 * The board ID is a string but the firmware byte
653 * swaps each 4-byte word before passing it back to
654 * us. Therefore we need to swab it before printing.
655 */
656 for (i = 0; i < 4; ++i)
657 ((u32 *) board_id)[i] =
658 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
659 }
660}
661
662int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
663{
664 struct mlx4_cmd_mailbox *mailbox;
665 u32 *outbox;
666 int err;
667
668#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 669#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
670#define QUERY_ADAPTER_VSD_OFFSET 0x20
671
672 mailbox = mlx4_alloc_cmd_mailbox(dev);
673 if (IS_ERR(mailbox))
674 return PTR_ERR(mailbox);
675 outbox = mailbox->buf;
676
677 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
678 MLX4_CMD_TIME_CLASS_A);
679 if (err)
680 goto out;
681
225c7b1f
RD		 682 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
683
684 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
685 adapter->board_id);
686
687out:
688 mlx4_free_cmd_mailbox(dev, mailbox);
689 return err;
690}
691
692int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
693{
694 struct mlx4_cmd_mailbox *mailbox;
695 __be32 *inbox;
696 int err;
697
698#define INIT_HCA_IN_SIZE 0x200
699#define INIT_HCA_VERSION_OFFSET 0x000
700#define INIT_HCA_VERSION 2
701#define INIT_HCA_FLAGS_OFFSET 0x014
702#define INIT_HCA_QPC_OFFSET 0x020
703#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
704#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
705#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
706#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
707#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
708#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
709#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
710#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
711#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
712#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
713#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
714#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
715#define INIT_HCA_MCAST_OFFSET 0x0c0
716#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
717#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
718#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
719#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
720#define INIT_HCA_TPT_OFFSET 0x0f0
721#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
722#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
723#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
724#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
725#define INIT_HCA_UAR_OFFSET 0x120
726#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
727#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
728
729 mailbox = mlx4_alloc_cmd_mailbox(dev);
730 if (IS_ERR(mailbox))
731 return PTR_ERR(mailbox);
732 inbox = mailbox->buf;
733
734 memset(inbox, 0, INIT_HCA_IN_SIZE);
735
736 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
737
738#if defined(__LITTLE_ENDIAN)
739 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
740#elif defined(__BIG_ENDIAN)
741 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
742#else
743#error Host endianness not defined
744#endif
745 /* Check port for UD address vector: */
746 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
747
8ff095ec
EC		 748 /* Enable IPoIB checksumming if we can: */
749 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
750 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
751
51f5f0ee
JM		 752 /* Enable QoS support if module parameter set */
753 if (enable_qos)
754 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
755
225c7b1f
RD		 756 /* QPC/EEC/CQC/EQC/RDMARC attributes */
757
758 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
759 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
760 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
761 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
762 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
763 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
764 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
765 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
766 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
767 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
768 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
769 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
770
771 /* multicast attributes */
772
773 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
774 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
775 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
776 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
777
778 /* TPT attributes */
779
780 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
781 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
782 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
783 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
784
785 /* UAR attributes */
786
787 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
788 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
789
77109cc2 790 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
225c7b1f
RD		 791
792 if (err)
793 mlx4_err(dev, "INIT_HCA returns %d\n", err);
794
795 mlx4_free_cmd_mailbox(dev, mailbox);
796 return err;
797}
798
5ae2a7a8 799int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 800{
801 struct mlx4_cmd_mailbox *mailbox;
802 u32 *inbox;
803 int err;
804 u32 flags;
5ae2a7a8 805 u16 field;
225c7b1f 806
5ae2a7a8 807 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 808#define INIT_PORT_IN_SIZE 256
809#define INIT_PORT_FLAGS_OFFSET 0x00
810#define INIT_PORT_FLAG_SIG (1 << 18)
811#define INIT_PORT_FLAG_NG (1 << 17)
812#define INIT_PORT_FLAG_G0 (1 << 16)
813#define INIT_PORT_VL_SHIFT 4
814#define INIT_PORT_PORT_WIDTH_SHIFT 8
815#define INIT_PORT_MTU_OFFSET 0x04
816#define INIT_PORT_MAX_GID_OFFSET 0x06
817#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
818#define INIT_PORT_GUID0_OFFSET 0x10
819#define INIT_PORT_NODE_GUID_OFFSET 0x18
820#define INIT_PORT_SI_GUID_OFFSET 0x20
821
5ae2a7a8
RD		 822 mailbox = mlx4_alloc_cmd_mailbox(dev);
823 if (IS_ERR(mailbox))
824 return PTR_ERR(mailbox);
825 inbox = mailbox->buf;
225c7b1f 826
5ae2a7a8 827 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 828
5ae2a7a8
RD		 829 flags = 0;
830 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
831 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
832 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 833
b79acb49 834 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 835 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
836 field = dev->caps.gid_table_len[port];
837 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
838 field = dev->caps.pkey_table_len[port];
839 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 840
5ae2a7a8
RD		 841 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
842 MLX4_CMD_TIME_CLASS_A);
225c7b1f 843
5ae2a7a8
RD		 844 mlx4_free_cmd_mailbox(dev, mailbox);
845 } else
846 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
847 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 848
849 return err;
850}
851EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
852
853int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
854{
855 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
856}
857EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
858
859int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
860{
861 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
862}
863
864int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
865{
866 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
867 MLX4_CMD_SET_ICM_SIZE,
868 MLX4_CMD_TIME_CLASS_A);
869 if (ret)
870 return ret;
871
872 /*
873 * Round up number of system pages needed in case
874 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
875 */
876 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
877 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
878
879 return 0;
880}
881
882int mlx4_NOP(struct mlx4_dev *dev)
883{
884 /* Input modifier of 0x1f means "finish as soon as possible." */
885 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
886}
Linux 6.x block layer and io_uring tree(s)