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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/mlx4/cq.h> | |
35 | #include <linux/mlx4/qp.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/if_ether.h> | |
38 | #include <linux/if_vlan.h> | |
39 | #include <linux/vmalloc.h> | |
40 | ||
41 | #include "mlx4_en.h" | |
42 | ||
43 | static void *get_wqe(struct mlx4_en_rx_ring *ring, int n) | |
44 | { | |
45 | int offset = n << ring->srq.wqe_shift; | |
46 | return ring->buf + offset; | |
47 | } | |
48 | ||
49 | static void mlx4_en_srq_event(struct mlx4_srq *srq, enum mlx4_event type) | |
50 | { | |
51 | return; | |
52 | } | |
53 | ||
54 | static int mlx4_en_get_frag_header(struct skb_frag_struct *frags, void **mac_hdr, | |
55 | void **ip_hdr, void **tcpudp_hdr, | |
56 | u64 *hdr_flags, void *priv) | |
57 | { | |
58 | *mac_hdr = page_address(frags->page) + frags->page_offset; | |
59 | *ip_hdr = *mac_hdr + ETH_HLEN; | |
60 | *tcpudp_hdr = (struct tcphdr *)(*ip_hdr + sizeof(struct iphdr)); | |
61 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
62 | ||
63 | return 0; | |
64 | } | |
65 | ||
66 | static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv, | |
67 | struct mlx4_en_rx_desc *rx_desc, | |
68 | struct skb_frag_struct *skb_frags, | |
69 | struct mlx4_en_rx_alloc *ring_alloc, | |
70 | int i) | |
71 | { | |
72 | struct mlx4_en_dev *mdev = priv->mdev; | |
73 | struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; | |
74 | struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i]; | |
75 | struct page *page; | |
76 | dma_addr_t dma; | |
77 | ||
78 | if (page_alloc->offset == frag_info->last_offset) { | |
79 | /* Allocate new page */ | |
80 | page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER); | |
81 | if (!page) | |
82 | return -ENOMEM; | |
83 | ||
84 | skb_frags[i].page = page_alloc->page; | |
85 | skb_frags[i].page_offset = page_alloc->offset; | |
86 | page_alloc->page = page; | |
87 | page_alloc->offset = frag_info->frag_align; | |
88 | } else { | |
89 | page = page_alloc->page; | |
90 | get_page(page); | |
91 | ||
92 | skb_frags[i].page = page; | |
93 | skb_frags[i].page_offset = page_alloc->offset; | |
94 | page_alloc->offset += frag_info->frag_stride; | |
95 | } | |
96 | dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) + | |
97 | skb_frags[i].page_offset, frag_info->frag_size, | |
98 | PCI_DMA_FROMDEVICE); | |
99 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
100 | return 0; | |
101 | } | |
102 | ||
103 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
104 | struct mlx4_en_rx_ring *ring) | |
105 | { | |
106 | struct mlx4_en_rx_alloc *page_alloc; | |
107 | int i; | |
108 | ||
109 | for (i = 0; i < priv->num_frags; i++) { | |
110 | page_alloc = &ring->page_alloc[i]; | |
111 | page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP, | |
112 | MLX4_EN_ALLOC_ORDER); | |
113 | if (!page_alloc->page) | |
114 | goto out; | |
115 | ||
116 | page_alloc->offset = priv->frag_info[i].frag_align; | |
117 | mlx4_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n", | |
118 | i, page_alloc->page); | |
119 | } | |
120 | return 0; | |
121 | ||
122 | out: | |
123 | while (i--) { | |
124 | page_alloc = &ring->page_alloc[i]; | |
125 | put_page(page_alloc->page); | |
126 | page_alloc->page = NULL; | |
127 | } | |
128 | return -ENOMEM; | |
129 | } | |
130 | ||
131 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
132 | struct mlx4_en_rx_ring *ring) | |
133 | { | |
134 | struct mlx4_en_rx_alloc *page_alloc; | |
135 | int i; | |
136 | ||
137 | for (i = 0; i < priv->num_frags; i++) { | |
138 | page_alloc = &ring->page_alloc[i]; | |
139 | mlx4_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", | |
140 | i, page_count(page_alloc->page)); | |
141 | ||
142 | put_page(page_alloc->page); | |
143 | page_alloc->page = NULL; | |
144 | } | |
145 | } | |
146 | ||
147 | ||
148 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, | |
149 | struct mlx4_en_rx_ring *ring, int index) | |
150 | { | |
151 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
152 | struct skb_frag_struct *skb_frags = ring->rx_info + | |
153 | (index << priv->log_rx_info); | |
154 | int possible_frags; | |
155 | int i; | |
156 | ||
157 | /* Pre-link descriptor */ | |
158 | rx_desc->next.next_wqe_index = cpu_to_be16((index + 1) & ring->size_mask); | |
159 | ||
160 | /* Set size and memtype fields */ | |
161 | for (i = 0; i < priv->num_frags; i++) { | |
162 | skb_frags[i].size = priv->frag_info[i].frag_size; | |
163 | rx_desc->data[i].byte_count = | |
164 | cpu_to_be32(priv->frag_info[i].frag_size); | |
165 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
166 | } | |
167 | ||
168 | /* If the number of used fragments does not fill up the ring stride, | |
169 | * remaining (unused) fragments must be padded with null address/size | |
170 | * and a special memory key */ | |
171 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
172 | for (i = priv->num_frags; i < possible_frags; i++) { | |
173 | rx_desc->data[i].byte_count = 0; | |
174 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
175 | rx_desc->data[i].addr = 0; | |
176 | } | |
177 | } | |
178 | ||
179 | ||
180 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, | |
181 | struct mlx4_en_rx_ring *ring, int index) | |
182 | { | |
183 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
184 | struct skb_frag_struct *skb_frags = ring->rx_info + | |
185 | (index << priv->log_rx_info); | |
186 | int i; | |
187 | ||
188 | for (i = 0; i < priv->num_frags; i++) | |
189 | if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i)) | |
190 | goto err; | |
191 | ||
192 | return 0; | |
193 | ||
194 | err: | |
195 | while (i--) | |
196 | put_page(skb_frags[i].page); | |
197 | return -ENOMEM; | |
198 | } | |
199 | ||
200 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) | |
201 | { | |
202 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
203 | } | |
204 | ||
38aab07c YP |
205 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
206 | struct mlx4_en_rx_ring *ring, | |
207 | int index) | |
208 | { | |
209 | struct mlx4_en_dev *mdev = priv->mdev; | |
210 | struct skb_frag_struct *skb_frags; | |
211 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride); | |
212 | dma_addr_t dma; | |
213 | int nr; | |
214 | ||
215 | skb_frags = ring->rx_info + (index << priv->log_rx_info); | |
216 | for (nr = 0; nr < priv->num_frags; nr++) { | |
217 | mlx4_dbg(DRV, priv, "Freeing fragment:%d\n", nr); | |
218 | dma = be64_to_cpu(rx_desc->data[nr].addr); | |
219 | ||
220 | mlx4_dbg(DRV, priv, "Unmaping buffer at dma:0x%llx\n", (u64) dma); | |
221 | pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size, | |
222 | PCI_DMA_FROMDEVICE); | |
223 | put_page(skb_frags[nr].page); | |
224 | } | |
225 | } | |
226 | ||
c27a02cd YP |
227 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
228 | { | |
229 | struct mlx4_en_dev *mdev = priv->mdev; | |
230 | struct mlx4_en_rx_ring *ring; | |
231 | int ring_ind; | |
232 | int buf_ind; | |
38aab07c | 233 | int new_size; |
c27a02cd YP |
234 | |
235 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
236 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
237 | ring = &priv->rx_ring[ring_ind]; | |
238 | ||
239 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
240 | ring->actual_size)) { | |
241 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { | |
242 | mlx4_err(mdev, "Failed to allocate " | |
243 | "enough rx buffers\n"); | |
244 | return -ENOMEM; | |
245 | } else { | |
38aab07c YP |
246 | new_size = rounddown_pow_of_two(ring->actual_size); |
247 | mlx4_warn(mdev, "Only %d buffers allocated " | |
248 | "reducing ring size to %d", | |
249 | ring->actual_size, new_size); | |
250 | goto reduce_rings; | |
c27a02cd YP |
251 | } |
252 | } | |
253 | ring->actual_size++; | |
254 | ring->prod++; | |
255 | } | |
256 | } | |
38aab07c YP |
257 | return 0; |
258 | ||
259 | reduce_rings: | |
260 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
261 | ring = &priv->rx_ring[ring_ind]; | |
262 | while (ring->actual_size > new_size) { | |
263 | ring->actual_size--; | |
264 | ring->prod--; | |
265 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
266 | } | |
267 | ring->size_mask = ring->actual_size - 1; | |
268 | } | |
269 | ||
c27a02cd YP |
270 | return 0; |
271 | } | |
272 | ||
273 | static int mlx4_en_fill_rx_buf(struct net_device *dev, | |
274 | struct mlx4_en_rx_ring *ring) | |
275 | { | |
276 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
277 | int num = 0; | |
278 | int err; | |
279 | ||
280 | while ((u32) (ring->prod - ring->cons) < ring->actual_size) { | |
281 | err = mlx4_en_prepare_rx_desc(priv, ring, ring->prod & | |
282 | ring->size_mask); | |
283 | if (err) { | |
284 | if (netif_msg_rx_err(priv)) | |
285 | mlx4_warn(priv->mdev, | |
286 | "Failed preparing rx descriptor\n"); | |
287 | priv->port_stats.rx_alloc_failed++; | |
288 | break; | |
289 | } | |
290 | ++num; | |
291 | ++ring->prod; | |
292 | } | |
38aab07c | 293 | if ((u32) (ring->prod - ring->cons) == ring->actual_size) |
c27a02cd YP |
294 | ring->full = 1; |
295 | ||
296 | return num; | |
297 | } | |
298 | ||
299 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, | |
300 | struct mlx4_en_rx_ring *ring) | |
301 | { | |
c27a02cd | 302 | int index; |
c27a02cd YP |
303 | |
304 | mlx4_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", | |
305 | ring->cons, ring->prod); | |
306 | ||
307 | /* Unmap and free Rx buffers */ | |
38aab07c | 308 | BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); |
c27a02cd YP |
309 | while (ring->cons != ring->prod) { |
310 | index = ring->cons & ring->size_mask; | |
c27a02cd | 311 | mlx4_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 312 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
313 | ++ring->cons; |
314 | } | |
315 | } | |
316 | ||
317 | ||
318 | void mlx4_en_rx_refill(struct work_struct *work) | |
319 | { | |
bf6aede7 | 320 | struct delayed_work *delay = to_delayed_work(work); |
c27a02cd YP |
321 | struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv, |
322 | refill_task); | |
323 | struct mlx4_en_dev *mdev = priv->mdev; | |
324 | struct net_device *dev = priv->dev; | |
325 | struct mlx4_en_rx_ring *ring; | |
326 | int need_refill = 0; | |
327 | int i; | |
328 | ||
329 | mutex_lock(&mdev->state_lock); | |
330 | if (!mdev->device_up || !priv->port_up) | |
331 | goto out; | |
332 | ||
333 | /* We only get here if there are no receive buffers, so we can't race | |
334 | * with Rx interrupts while filling buffers */ | |
335 | for (i = 0; i < priv->rx_ring_num; i++) { | |
336 | ring = &priv->rx_ring[i]; | |
337 | if (ring->need_refill) { | |
338 | if (mlx4_en_fill_rx_buf(dev, ring)) { | |
339 | ring->need_refill = 0; | |
340 | mlx4_en_update_rx_prod_db(ring); | |
341 | } else | |
342 | need_refill = 1; | |
343 | } | |
344 | } | |
345 | if (need_refill) | |
346 | queue_delayed_work(mdev->workqueue, &priv->refill_task, HZ); | |
347 | ||
348 | out: | |
349 | mutex_unlock(&mdev->state_lock); | |
350 | } | |
351 | ||
352 | ||
353 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, | |
354 | struct mlx4_en_rx_ring *ring, u32 size, u16 stride) | |
355 | { | |
356 | struct mlx4_en_dev *mdev = priv->mdev; | |
357 | int err; | |
358 | int tmp; | |
359 | ||
360 | /* Sanity check SRQ size before proceeding */ | |
361 | if (size >= mdev->dev->caps.max_srq_wqes) | |
362 | return -EINVAL; | |
363 | ||
364 | ring->prod = 0; | |
365 | ring->cons = 0; | |
366 | ring->size = size; | |
367 | ring->size_mask = size - 1; | |
368 | ring->stride = stride; | |
369 | ring->log_stride = ffs(ring->stride) - 1; | |
370 | ring->buf_size = ring->size * ring->stride; | |
371 | ||
372 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
373 | sizeof(struct skb_frag_struct)); | |
374 | ring->rx_info = vmalloc(tmp); | |
375 | if (!ring->rx_info) { | |
376 | mlx4_err(mdev, "Failed allocating rx_info ring\n"); | |
377 | return -ENOMEM; | |
378 | } | |
379 | mlx4_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", | |
380 | ring->rx_info, tmp); | |
381 | ||
382 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, | |
383 | ring->buf_size, 2 * PAGE_SIZE); | |
384 | if (err) | |
385 | goto err_ring; | |
386 | ||
387 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
388 | if (err) { | |
389 | mlx4_err(mdev, "Failed to map RX buffer\n"); | |
390 | goto err_hwq; | |
391 | } | |
392 | ring->buf = ring->wqres.buf.direct.buf; | |
393 | ||
394 | /* Configure lro mngr */ | |
395 | memset(&ring->lro, 0, sizeof(struct net_lro_mgr)); | |
396 | ring->lro.dev = priv->dev; | |
397 | ring->lro.features = LRO_F_NAPI; | |
398 | ring->lro.frag_align_pad = NET_IP_ALIGN; | |
399 | ring->lro.ip_summed = CHECKSUM_UNNECESSARY; | |
400 | ring->lro.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
401 | ring->lro.max_desc = mdev->profile.num_lro; | |
402 | ring->lro.max_aggr = MAX_SKB_FRAGS; | |
403 | ring->lro.lro_arr = kzalloc(mdev->profile.num_lro * | |
404 | sizeof(struct net_lro_desc), | |
405 | GFP_KERNEL); | |
406 | if (!ring->lro.lro_arr) { | |
407 | mlx4_err(mdev, "Failed to allocate lro array\n"); | |
408 | goto err_map; | |
409 | } | |
410 | ring->lro.get_frag_header = mlx4_en_get_frag_header; | |
411 | ||
412 | return 0; | |
413 | ||
414 | err_map: | |
415 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
416 | err_hwq: | |
417 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
418 | err_ring: | |
419 | vfree(ring->rx_info); | |
420 | ring->rx_info = NULL; | |
421 | return err; | |
422 | } | |
423 | ||
424 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
425 | { | |
426 | struct mlx4_en_dev *mdev = priv->mdev; | |
427 | struct mlx4_wqe_srq_next_seg *next; | |
428 | struct mlx4_en_rx_ring *ring; | |
429 | int i; | |
430 | int ring_ind; | |
431 | int err; | |
432 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
433 | DS_SIZE * priv->num_frags); | |
434 | int max_gs = (stride - sizeof(struct mlx4_wqe_srq_next_seg)) / DS_SIZE; | |
435 | ||
436 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
437 | ring = &priv->rx_ring[ring_ind]; | |
438 | ||
439 | ring->prod = 0; | |
440 | ring->cons = 0; | |
441 | ring->actual_size = 0; | |
442 | ring->cqn = priv->rx_cq[ring_ind].mcq.cqn; | |
443 | ||
444 | ring->stride = stride; | |
445 | ring->log_stride = ffs(ring->stride) - 1; | |
446 | ring->buf_size = ring->size * ring->stride; | |
447 | ||
448 | memset(ring->buf, 0, ring->buf_size); | |
449 | mlx4_en_update_rx_prod_db(ring); | |
450 | ||
451 | /* Initailize all descriptors */ | |
452 | for (i = 0; i < ring->size; i++) | |
453 | mlx4_en_init_rx_desc(priv, ring, i); | |
454 | ||
455 | /* Initialize page allocators */ | |
456 | err = mlx4_en_init_allocator(priv, ring); | |
457 | if (err) { | |
9a4f92a6 YP |
458 | mlx4_err(mdev, "Failed initializing ring allocator\n"); |
459 | ring_ind--; | |
460 | goto err_allocator; | |
c27a02cd YP |
461 | } |
462 | ||
463 | /* Fill Rx buffers */ | |
464 | ring->full = 0; | |
465 | } | |
b58515be IM |
466 | err = mlx4_en_fill_rx_buffers(priv); |
467 | if (err) | |
c27a02cd YP |
468 | goto err_buffers; |
469 | ||
470 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
471 | ring = &priv->rx_ring[ring_ind]; | |
472 | ||
473 | mlx4_en_update_rx_prod_db(ring); | |
474 | ||
475 | /* Configure SRQ representing the ring */ | |
38aab07c | 476 | ring->srq.max = ring->actual_size; |
c27a02cd YP |
477 | ring->srq.max_gs = max_gs; |
478 | ring->srq.wqe_shift = ilog2(ring->stride); | |
479 | ||
480 | for (i = 0; i < ring->srq.max; ++i) { | |
481 | next = get_wqe(ring, i); | |
482 | next->next_wqe_index = | |
483 | cpu_to_be16((i + 1) & (ring->srq.max - 1)); | |
484 | } | |
485 | ||
486 | err = mlx4_srq_alloc(mdev->dev, mdev->priv_pdn, &ring->wqres.mtt, | |
487 | ring->wqres.db.dma, &ring->srq); | |
488 | if (err){ | |
489 | mlx4_err(mdev, "Failed to allocate srq\n"); | |
9a4f92a6 | 490 | ring_ind--; |
c27a02cd YP |
491 | goto err_srq; |
492 | } | |
493 | ring->srq.event = mlx4_en_srq_event; | |
494 | } | |
495 | ||
496 | return 0; | |
497 | ||
498 | err_srq: | |
499 | while (ring_ind >= 0) { | |
500 | ring = &priv->rx_ring[ring_ind]; | |
501 | mlx4_srq_free(mdev->dev, &ring->srq); | |
502 | ring_ind--; | |
503 | } | |
504 | ||
505 | err_buffers: | |
506 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
507 | mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]); | |
508 | ||
509 | ring_ind = priv->rx_ring_num - 1; | |
510 | err_allocator: | |
511 | while (ring_ind >= 0) { | |
512 | mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]); | |
513 | ring_ind--; | |
514 | } | |
515 | return err; | |
516 | } | |
517 | ||
518 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, | |
519 | struct mlx4_en_rx_ring *ring) | |
520 | { | |
521 | struct mlx4_en_dev *mdev = priv->mdev; | |
522 | ||
523 | kfree(ring->lro.lro_arr); | |
524 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
525 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
526 | vfree(ring->rx_info); | |
527 | ring->rx_info = NULL; | |
528 | } | |
529 | ||
530 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
531 | struct mlx4_en_rx_ring *ring) | |
532 | { | |
533 | struct mlx4_en_dev *mdev = priv->mdev; | |
534 | ||
535 | mlx4_srq_free(mdev->dev, &ring->srq); | |
536 | mlx4_en_free_rx_buf(priv, ring); | |
537 | mlx4_en_destroy_allocator(priv, ring); | |
538 | } | |
539 | ||
540 | ||
541 | /* Unmap a completed descriptor and free unused pages */ | |
542 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, | |
543 | struct mlx4_en_rx_desc *rx_desc, | |
544 | struct skb_frag_struct *skb_frags, | |
545 | struct skb_frag_struct *skb_frags_rx, | |
546 | struct mlx4_en_rx_alloc *page_alloc, | |
547 | int length) | |
548 | { | |
549 | struct mlx4_en_dev *mdev = priv->mdev; | |
550 | struct mlx4_en_frag_info *frag_info; | |
551 | int nr; | |
552 | dma_addr_t dma; | |
553 | ||
554 | /* Collect used fragments while replacing them in the HW descirptors */ | |
555 | for (nr = 0; nr < priv->num_frags; nr++) { | |
556 | frag_info = &priv->frag_info[nr]; | |
557 | if (length <= frag_info->frag_prefix_size) | |
558 | break; | |
559 | ||
560 | /* Save page reference in skb */ | |
561 | skb_frags_rx[nr].page = skb_frags[nr].page; | |
562 | skb_frags_rx[nr].size = skb_frags[nr].size; | |
563 | skb_frags_rx[nr].page_offset = skb_frags[nr].page_offset; | |
564 | dma = be64_to_cpu(rx_desc->data[nr].addr); | |
565 | ||
566 | /* Allocate a replacement page */ | |
567 | if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr)) | |
568 | goto fail; | |
569 | ||
570 | /* Unmap buffer */ | |
571 | pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size, | |
572 | PCI_DMA_FROMDEVICE); | |
573 | } | |
574 | /* Adjust size of last fragment to match actual length */ | |
575 | skb_frags_rx[nr - 1].size = length - | |
576 | priv->frag_info[nr - 1].frag_prefix_size; | |
577 | return nr; | |
578 | ||
579 | fail: | |
580 | /* Drop all accumulated fragments (which have already been replaced in | |
581 | * the descriptor) of this packet; remaining fragments are reused... */ | |
582 | while (nr > 0) { | |
583 | nr--; | |
584 | put_page(skb_frags_rx[nr].page); | |
585 | } | |
586 | return 0; | |
587 | } | |
588 | ||
589 | ||
590 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
591 | struct mlx4_en_rx_desc *rx_desc, | |
592 | struct skb_frag_struct *skb_frags, | |
593 | struct mlx4_en_rx_alloc *page_alloc, | |
594 | unsigned int length) | |
595 | { | |
596 | struct mlx4_en_dev *mdev = priv->mdev; | |
597 | struct sk_buff *skb; | |
598 | void *va; | |
599 | int used_frags; | |
600 | dma_addr_t dma; | |
601 | ||
602 | skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN); | |
603 | if (!skb) { | |
604 | mlx4_dbg(RX_ERR, priv, "Failed allocating skb\n"); | |
605 | return NULL; | |
606 | } | |
607 | skb->dev = priv->dev; | |
608 | skb_reserve(skb, NET_IP_ALIGN); | |
609 | skb->len = length; | |
610 | skb->truesize = length + sizeof(struct sk_buff); | |
611 | ||
612 | /* Get pointer to first fragment so we could copy the headers into the | |
613 | * (linear part of the) skb */ | |
614 | va = page_address(skb_frags[0].page) + skb_frags[0].page_offset; | |
615 | ||
616 | if (length <= SMALL_PACKET_SIZE) { | |
617 | /* We are copying all relevant data to the skb - temporarily | |
618 | * synch buffers for the copy */ | |
619 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
620 | dma_sync_single_range_for_cpu(&mdev->pdev->dev, dma, 0, | |
621 | length, DMA_FROM_DEVICE); | |
622 | skb_copy_to_linear_data(skb, va, length); | |
623 | dma_sync_single_range_for_device(&mdev->pdev->dev, dma, 0, | |
624 | length, DMA_FROM_DEVICE); | |
625 | skb->tail += length; | |
626 | } else { | |
627 | ||
628 | /* Move relevant fragments to skb */ | |
629 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags, | |
630 | skb_shinfo(skb)->frags, | |
631 | page_alloc, length); | |
785a0982 YP |
632 | if (unlikely(!used_frags)) { |
633 | kfree_skb(skb); | |
634 | return NULL; | |
635 | } | |
c27a02cd YP |
636 | skb_shinfo(skb)->nr_frags = used_frags; |
637 | ||
638 | /* Copy headers into the skb linear buffer */ | |
639 | memcpy(skb->data, va, HEADER_COPY_SIZE); | |
640 | skb->tail += HEADER_COPY_SIZE; | |
641 | ||
642 | /* Skip headers in first fragment */ | |
643 | skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE; | |
644 | ||
645 | /* Adjust size of first fragment */ | |
646 | skb_shinfo(skb)->frags[0].size -= HEADER_COPY_SIZE; | |
647 | skb->data_len = length - HEADER_COPY_SIZE; | |
648 | } | |
649 | return skb; | |
650 | } | |
651 | ||
652 | static void mlx4_en_copy_desc(struct mlx4_en_priv *priv, | |
653 | struct mlx4_en_rx_ring *ring, | |
654 | int from, int to, int num) | |
655 | { | |
656 | struct skb_frag_struct *skb_frags_from; | |
657 | struct skb_frag_struct *skb_frags_to; | |
658 | struct mlx4_en_rx_desc *rx_desc_from; | |
659 | struct mlx4_en_rx_desc *rx_desc_to; | |
660 | int from_index, to_index; | |
661 | int nr, i; | |
662 | ||
663 | for (i = 0; i < num; i++) { | |
664 | from_index = (from + i) & ring->size_mask; | |
665 | to_index = (to + i) & ring->size_mask; | |
666 | skb_frags_from = ring->rx_info + (from_index << priv->log_rx_info); | |
667 | skb_frags_to = ring->rx_info + (to_index << priv->log_rx_info); | |
668 | rx_desc_from = ring->buf + (from_index << ring->log_stride); | |
669 | rx_desc_to = ring->buf + (to_index << ring->log_stride); | |
670 | ||
671 | for (nr = 0; nr < priv->num_frags; nr++) { | |
672 | skb_frags_to[nr].page = skb_frags_from[nr].page; | |
673 | skb_frags_to[nr].page_offset = skb_frags_from[nr].page_offset; | |
674 | rx_desc_to->data[nr].addr = rx_desc_from->data[nr].addr; | |
675 | } | |
676 | } | |
677 | } | |
678 | ||
679 | ||
680 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) | |
681 | { | |
682 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
683 | struct mlx4_en_dev *mdev = priv->mdev; | |
684 | struct mlx4_cqe *cqe; | |
685 | struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring]; | |
686 | struct skb_frag_struct *skb_frags; | |
687 | struct skb_frag_struct lro_frags[MLX4_EN_MAX_RX_FRAGS]; | |
688 | struct mlx4_en_rx_desc *rx_desc; | |
689 | struct sk_buff *skb; | |
690 | int index; | |
691 | int nr; | |
692 | unsigned int length; | |
693 | int polled = 0; | |
694 | int ip_summed; | |
695 | ||
696 | if (!priv->port_up) | |
697 | return 0; | |
698 | ||
699 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx | |
700 | * descriptor offset can be deduced from the CQE index instead of | |
701 | * reading 'cqe->index' */ | |
702 | index = cq->mcq.cons_index & ring->size_mask; | |
703 | cqe = &cq->buf[index]; | |
704 | ||
705 | /* Process all completed CQEs */ | |
706 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
707 | cq->mcq.cons_index & cq->size)) { | |
708 | ||
709 | skb_frags = ring->rx_info + (index << priv->log_rx_info); | |
710 | rx_desc = ring->buf + (index << ring->log_stride); | |
711 | ||
712 | /* | |
713 | * make sure we read the CQE after we read the ownership bit | |
714 | */ | |
715 | rmb(); | |
716 | ||
717 | /* Drop packet on bad receive or bad checksum */ | |
718 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
719 | MLX4_CQE_OPCODE_ERROR)) { | |
720 | mlx4_err(mdev, "CQE completed in error - vendor " | |
721 | "syndrom:%d syndrom:%d\n", | |
722 | ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome, | |
723 | ((struct mlx4_err_cqe *) cqe)->syndrome); | |
724 | goto next; | |
725 | } | |
726 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
727 | mlx4_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); | |
728 | goto next; | |
729 | } | |
730 | ||
731 | /* | |
732 | * Packet is OK - process it. | |
733 | */ | |
734 | length = be32_to_cpu(cqe->byte_cnt); | |
735 | ring->bytes += length; | |
736 | ring->packets++; | |
737 | ||
738 | if (likely(priv->rx_csum)) { | |
739 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && | |
740 | (cqe->checksum == cpu_to_be16(0xffff))) { | |
741 | priv->port_stats.rx_chksum_good++; | |
742 | /* This packet is eligible for LRO if it is: | |
743 | * - DIX Ethernet (type interpretation) | |
744 | * - TCP/IP (v4) | |
745 | * - without IP options | |
746 | * - not an IP fragment */ | |
747 | if (mlx4_en_can_lro(cqe->status) && | |
748 | dev->features & NETIF_F_LRO) { | |
749 | ||
750 | nr = mlx4_en_complete_rx_desc( | |
751 | priv, rx_desc, | |
752 | skb_frags, lro_frags, | |
753 | ring->page_alloc, length); | |
754 | if (!nr) | |
755 | goto next; | |
756 | ||
757 | if (priv->vlgrp && (cqe->vlan_my_qpn & | |
758 | cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK))) { | |
759 | lro_vlan_hwaccel_receive_frags( | |
760 | &ring->lro, lro_frags, | |
761 | length, length, | |
762 | priv->vlgrp, | |
763 | be16_to_cpu(cqe->sl_vid), | |
764 | NULL, 0); | |
765 | } else | |
766 | lro_receive_frags(&ring->lro, | |
767 | lro_frags, | |
768 | length, | |
769 | length, | |
770 | NULL, 0); | |
771 | ||
772 | goto next; | |
773 | } | |
774 | ||
775 | /* LRO not possible, complete processing here */ | |
776 | ip_summed = CHECKSUM_UNNECESSARY; | |
777 | INC_PERF_COUNTER(priv->pstats.lro_misses); | |
778 | } else { | |
779 | ip_summed = CHECKSUM_NONE; | |
780 | priv->port_stats.rx_chksum_none++; | |
781 | } | |
782 | } else { | |
783 | ip_summed = CHECKSUM_NONE; | |
784 | priv->port_stats.rx_chksum_none++; | |
785 | } | |
786 | ||
787 | skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags, | |
788 | ring->page_alloc, length); | |
789 | if (!skb) { | |
790 | priv->stats.rx_dropped++; | |
791 | goto next; | |
792 | } | |
793 | ||
794 | skb->ip_summed = ip_summed; | |
795 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 796 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd YP |
797 | |
798 | /* Push it up the stack */ | |
799 | if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) & | |
800 | MLX4_CQE_VLAN_PRESENT_MASK)) { | |
801 | vlan_hwaccel_receive_skb(skb, priv->vlgrp, | |
802 | be16_to_cpu(cqe->sl_vid)); | |
803 | } else | |
804 | netif_receive_skb(skb); | |
805 | ||
c27a02cd YP |
806 | next: |
807 | ++cq->mcq.cons_index; | |
808 | index = (cq->mcq.cons_index) & ring->size_mask; | |
809 | cqe = &cq->buf[index]; | |
810 | if (++polled == budget) { | |
811 | /* We are here because we reached the NAPI budget - | |
812 | * flush only pending LRO sessions */ | |
813 | lro_flush_all(&ring->lro); | |
814 | goto out; | |
815 | } | |
816 | } | |
817 | ||
818 | /* If CQ is empty flush all LRO sessions unconditionally */ | |
819 | lro_flush_all(&ring->lro); | |
820 | ||
821 | out: | |
822 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
823 | mlx4_cq_set_ci(&cq->mcq); | |
824 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
825 | ring->cons = cq->mcq.cons_index; | |
826 | ring->prod += polled; /* Polled descriptors were realocated in place */ | |
827 | if (unlikely(!ring->full)) { | |
828 | mlx4_en_copy_desc(priv, ring, ring->cons - polled, | |
829 | ring->prod - polled, polled); | |
830 | mlx4_en_fill_rx_buf(dev, ring); | |
831 | } | |
832 | mlx4_en_update_rx_prod_db(ring); | |
833 | return polled; | |
834 | } | |
835 | ||
836 | ||
837 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
838 | { | |
839 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
840 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
841 | ||
842 | if (priv->port_up) | |
288379f0 | 843 | napi_schedule(&cq->napi); |
c27a02cd YP |
844 | else |
845 | mlx4_en_arm_cq(priv, cq); | |
846 | } | |
847 | ||
848 | /* Rx CQ polling - called by NAPI */ | |
849 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
850 | { | |
851 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
852 | struct net_device *dev = cq->dev; | |
853 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
854 | int done; | |
855 | ||
856 | done = mlx4_en_process_rx_cq(dev, cq, budget); | |
857 | ||
858 | /* If we used up all the quota - we're probably not done yet... */ | |
859 | if (done == budget) | |
860 | INC_PERF_COUNTER(priv->pstats.napi_quota); | |
861 | else { | |
862 | /* Done for now */ | |
288379f0 | 863 | napi_complete(napi); |
c27a02cd YP |
864 | mlx4_en_arm_cq(priv, cq); |
865 | } | |
866 | return done; | |
867 | } | |
868 | ||
869 | ||
870 | /* Calculate the last offset position that accomodates a full fragment | |
871 | * (assuming fagment size = stride-align) */ | |
872 | static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align) | |
873 | { | |
874 | u16 res = MLX4_EN_ALLOC_SIZE % stride; | |
875 | u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align; | |
876 | ||
877 | mlx4_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d " | |
878 | "res:%d offset:%d\n", stride, align, res, offset); | |
879 | return offset; | |
880 | } | |
881 | ||
882 | ||
883 | static int frag_sizes[] = { | |
884 | FRAG_SZ0, | |
885 | FRAG_SZ1, | |
886 | FRAG_SZ2, | |
887 | FRAG_SZ3 | |
888 | }; | |
889 | ||
890 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
891 | { | |
892 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
893 | int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE; | |
894 | int buf_size = 0; | |
895 | int i = 0; | |
896 | ||
897 | while (buf_size < eff_mtu) { | |
898 | priv->frag_info[i].frag_size = | |
899 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
900 | frag_sizes[i] : eff_mtu - buf_size; | |
901 | priv->frag_info[i].frag_prefix_size = buf_size; | |
902 | if (!i) { | |
903 | priv->frag_info[i].frag_align = NET_IP_ALIGN; | |
904 | priv->frag_info[i].frag_stride = | |
905 | ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); | |
906 | } else { | |
907 | priv->frag_info[i].frag_align = 0; | |
908 | priv->frag_info[i].frag_stride = | |
909 | ALIGN(frag_sizes[i], SMP_CACHE_BYTES); | |
910 | } | |
911 | priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset( | |
912 | priv, priv->frag_info[i].frag_stride, | |
913 | priv->frag_info[i].frag_align); | |
914 | buf_size += priv->frag_info[i].frag_size; | |
915 | i++; | |
916 | } | |
917 | ||
918 | priv->num_frags = i; | |
919 | priv->rx_skb_size = eff_mtu; | |
920 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct)); | |
921 | ||
922 | mlx4_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d " | |
923 | "num_frags:%d):\n", eff_mtu, priv->num_frags); | |
924 | for (i = 0; i < priv->num_frags; i++) { | |
925 | mlx4_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d " | |
926 | "stride:%d last_offset:%d\n", i, | |
927 | priv->frag_info[i].frag_size, | |
928 | priv->frag_info[i].frag_prefix_size, | |
929 | priv->frag_info[i].frag_align, | |
930 | priv->frag_info[i].frag_stride, | |
931 | priv->frag_info[i].last_offset); | |
932 | } | |
933 | } | |
934 | ||
935 | /* RSS related functions */ | |
936 | ||
937 | /* Calculate rss size and map each entry in rss table to rx ring */ | |
938 | void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv, | |
939 | struct mlx4_en_rss_map *rss_map, | |
940 | int num_entries, int num_rings) | |
941 | { | |
942 | int i; | |
943 | ||
944 | rss_map->size = roundup_pow_of_two(num_entries); | |
945 | mlx4_dbg(DRV, priv, "Setting default RSS map of %d entires\n", | |
946 | rss_map->size); | |
947 | ||
948 | for (i = 0; i < rss_map->size; i++) { | |
949 | rss_map->map[i] = i % num_rings; | |
950 | mlx4_dbg(DRV, priv, "Entry %d ---> ring %d\n", i, rss_map->map[i]); | |
951 | } | |
952 | } | |
953 | ||
c27a02cd YP |
954 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, |
955 | int qpn, int srqn, int cqn, | |
956 | enum mlx4_qp_state *state, | |
957 | struct mlx4_qp *qp) | |
958 | { | |
959 | struct mlx4_en_dev *mdev = priv->mdev; | |
960 | struct mlx4_qp_context *context; | |
961 | int err = 0; | |
962 | ||
963 | context = kmalloc(sizeof *context , GFP_KERNEL); | |
964 | if (!context) { | |
965 | mlx4_err(mdev, "Failed to allocate qp context\n"); | |
966 | return -ENOMEM; | |
967 | } | |
968 | ||
969 | err = mlx4_qp_alloc(mdev->dev, qpn, qp); | |
970 | if (err) { | |
971 | mlx4_err(mdev, "Failed to allocate qp #%d\n", qpn); | |
972 | goto out; | |
c27a02cd YP |
973 | } |
974 | qp->event = mlx4_en_sqp_event; | |
975 | ||
976 | memset(context, 0, sizeof *context); | |
977 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 0, qpn, cqn, srqn, context); | |
978 | ||
979 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, context, qp, state); | |
980 | if (err) { | |
981 | mlx4_qp_remove(mdev->dev, qp); | |
982 | mlx4_qp_free(mdev->dev, qp); | |
983 | } | |
984 | out: | |
985 | kfree(context); | |
986 | return err; | |
987 | } | |
988 | ||
989 | /* Allocate rx qp's and configure them according to rss map */ | |
990 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
991 | { | |
992 | struct mlx4_en_dev *mdev = priv->mdev; | |
993 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
994 | struct mlx4_qp_context context; | |
995 | struct mlx4_en_rss_context *rss_context; | |
996 | void *ptr; | |
997 | int rss_xor = mdev->profile.rss_xor; | |
998 | u8 rss_mask = mdev->profile.rss_mask; | |
999 | int i, srqn, qpn, cqn; | |
1000 | int err = 0; | |
1001 | int good_qps = 0; | |
1002 | ||
1003 | mlx4_dbg(DRV, priv, "Configuring rss steering for port %u\n", priv->port); | |
1004 | err = mlx4_qp_reserve_range(mdev->dev, rss_map->size, | |
1005 | rss_map->size, &rss_map->base_qpn); | |
1006 | if (err) { | |
1007 | mlx4_err(mdev, "Failed reserving %d qps for port %u\n", | |
1008 | rss_map->size, priv->port); | |
1009 | return err; | |
1010 | } | |
1011 | ||
1012 | for (i = 0; i < rss_map->size; i++) { | |
1013 | cqn = priv->rx_ring[rss_map->map[i]].cqn; | |
1014 | srqn = priv->rx_ring[rss_map->map[i]].srq.srqn; | |
1015 | qpn = rss_map->base_qpn + i; | |
1016 | err = mlx4_en_config_rss_qp(priv, qpn, srqn, cqn, | |
1017 | &rss_map->state[i], | |
1018 | &rss_map->qps[i]); | |
1019 | if (err) | |
1020 | goto rss_err; | |
1021 | ||
1022 | ++good_qps; | |
1023 | } | |
1024 | ||
1025 | /* Configure RSS indirection qp */ | |
1026 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &priv->base_qpn); | |
1027 | if (err) { | |
1028 | mlx4_err(mdev, "Failed to reserve range for RSS " | |
1029 | "indirection qp\n"); | |
1030 | goto rss_err; | |
1031 | } | |
1032 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp); | |
1033 | if (err) { | |
1034 | mlx4_err(mdev, "Failed to allocate RSS indirection QP\n"); | |
1035 | goto reserve_err; | |
1036 | } | |
1037 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
1038 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
1039 | priv->rx_ring[0].cqn, 0, &context); | |
1040 | ||
1041 | ptr = ((void *) &context) + 0x3c; | |
1042 | rss_context = (struct mlx4_en_rss_context *) ptr; | |
1043 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_map->size) << 24 | | |
1044 | (rss_map->base_qpn)); | |
1045 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); | |
1046 | rss_context->hash_fn = rss_xor & 0x3; | |
1047 | rss_context->flags = rss_mask << 2; | |
1048 | ||
1049 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, | |
1050 | &rss_map->indir_qp, &rss_map->indir_state); | |
1051 | if (err) | |
1052 | goto indir_err; | |
1053 | ||
1054 | return 0; | |
1055 | ||
1056 | indir_err: | |
1057 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1058 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1059 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1060 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
1061 | reserve_err: | |
1062 | mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1); | |
1063 | rss_err: | |
1064 | for (i = 0; i < good_qps; i++) { | |
1065 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1066 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1067 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1068 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1069 | } | |
1070 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size); | |
1071 | return err; | |
1072 | } | |
1073 | ||
1074 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
1075 | { | |
1076 | struct mlx4_en_dev *mdev = priv->mdev; | |
1077 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1078 | int i; | |
1079 | ||
1080 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1081 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1082 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1083 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
1084 | mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1); | |
1085 | ||
1086 | for (i = 0; i < rss_map->size; i++) { | |
1087 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1088 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1089 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1090 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1091 | } | |
1092 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size); | |
1093 | } | |
1094 | ||
1095 | ||
1096 | ||
1097 | ||
1098 |