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ixgbe: setup per CPU PCI pool for FCoE DDP
[linux-2.6-block.git] / drivers / net / mlx4 / en_rx.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/mlx4/cq.h>
5a0e3ad6 35#include <linux/slab.h>
c27a02cd
YP		 36#include <linux/mlx4/qp.h>
37#include <linux/skbuff.h>
38#include <linux/if_ether.h>
39#include <linux/if_vlan.h>
40#include <linux/vmalloc.h>
41
42#include "mlx4_en.h"
43
c27a02cd 44
c27a02cd
YP		 45static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
46 struct mlx4_en_rx_desc *rx_desc,
47 struct skb_frag_struct *skb_frags,
48 struct mlx4_en_rx_alloc *ring_alloc,
49 int i)
50{
51 struct mlx4_en_dev *mdev = priv->mdev;
52 struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
53 struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
54 struct page *page;
55 dma_addr_t dma;
56
57 if (page_alloc->offset == frag_info->last_offset) {
58 /* Allocate new page */
59 page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
60 if (!page)
61 return -ENOMEM;
62
63 skb_frags[i].page = page_alloc->page;
64 skb_frags[i].page_offset = page_alloc->offset;
65 page_alloc->page = page;
66 page_alloc->offset = frag_info->frag_align;
67 } else {
68 page = page_alloc->page;
69 get_page(page);
70
71 skb_frags[i].page = page;
72 skb_frags[i].page_offset = page_alloc->offset;
73 page_alloc->offset += frag_info->frag_stride;
74 }
75 dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) +
76 skb_frags[i].page_offset, frag_info->frag_size,
77 PCI_DMA_FROMDEVICE);
78 rx_desc->data[i].addr = cpu_to_be64(dma);
79 return 0;
80}
81
82static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
83 struct mlx4_en_rx_ring *ring)
84{
85 struct mlx4_en_rx_alloc *page_alloc;
86 int i;
87
88 for (i = 0; i < priv->num_frags; i++) {
89 page_alloc = &ring->page_alloc[i];
90 page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
91 MLX4_EN_ALLOC_ORDER);
92 if (!page_alloc->page)
93 goto out;
94
95 page_alloc->offset = priv->frag_info[i].frag_align;
453a6082
YP		 96 en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
97 i, page_alloc->page);
c27a02cd
YP		 98 }
99 return 0;
100
101out:
102 while (i--) {
103 page_alloc = &ring->page_alloc[i];
104 put_page(page_alloc->page);
105 page_alloc->page = NULL;
106 }
107 return -ENOMEM;
108}
109
110static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
111 struct mlx4_en_rx_ring *ring)
112{
113 struct mlx4_en_rx_alloc *page_alloc;
114 int i;
115
116 for (i = 0; i < priv->num_frags; i++) {
117 page_alloc = &ring->page_alloc[i];
453a6082
YP		 118 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
119 i, page_count(page_alloc->page));
c27a02cd
YP		 120
121 put_page(page_alloc->page);
122 page_alloc->page = NULL;
123 }
124}
125
126
127static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
128 struct mlx4_en_rx_ring *ring, int index)
129{
130 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
131 struct skb_frag_struct *skb_frags = ring->rx_info +
132 (index << priv->log_rx_info);
133 int possible_frags;
134 int i;
135
c27a02cd
YP		 136 /* Set size and memtype fields */
137 for (i = 0; i < priv->num_frags; i++) {
138 skb_frags[i].size = priv->frag_info[i].frag_size;
139 rx_desc->data[i].byte_count =
140 cpu_to_be32(priv->frag_info[i].frag_size);
141 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
142 }
143
144 /* If the number of used fragments does not fill up the ring stride,
145 * remaining (unused) fragments must be padded with null address/size
146 * and a special memory key */
147 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
148 for (i = priv->num_frags; i < possible_frags; i++) {
149 rx_desc->data[i].byte_count = 0;
150 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
151 rx_desc->data[i].addr = 0;
152 }
153}
154
155
156static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
157 struct mlx4_en_rx_ring *ring, int index)
158{
159 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
160 struct skb_frag_struct *skb_frags = ring->rx_info +
161 (index << priv->log_rx_info);
162 int i;
163
164 for (i = 0; i < priv->num_frags; i++)
165 if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
166 goto err;
167
168 return 0;
169
170err:
171 while (i--)
172 put_page(skb_frags[i].page);
173 return -ENOMEM;
174}
175
176static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
177{
178 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
179}
180
38aab07c
YP		 181static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
182 struct mlx4_en_rx_ring *ring,
183 int index)
184{
185 struct mlx4_en_dev *mdev = priv->mdev;
186 struct skb_frag_struct *skb_frags;
187 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
188 dma_addr_t dma;
189 int nr;
190
191 skb_frags = ring->rx_info + (index << priv->log_rx_info);
192 for (nr = 0; nr < priv->num_frags; nr++) {
453a6082 193 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
38aab07c
YP		 194 dma = be64_to_cpu(rx_desc->data[nr].addr);
195
af901ca1 196 en_dbg(DRV, priv, "Unmapping buffer at dma:0x%llx\n", (u64) dma);
38aab07c
YP		 197 pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
198 PCI_DMA_FROMDEVICE);
199 put_page(skb_frags[nr].page);
200 }
201}
202
c27a02cd
YP		 203static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
204{
c27a02cd
YP		 205 struct mlx4_en_rx_ring *ring;
206 int ring_ind;
207 int buf_ind;
38aab07c 208 int new_size;
c27a02cd
YP		 209
210 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
211 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
212 ring = &priv->rx_ring[ring_ind];
213
214 if (mlx4_en_prepare_rx_desc(priv, ring,
215 ring->actual_size)) {
216 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
453a6082
YP		 217 en_err(priv, "Failed to allocate "
218 "enough rx buffers\n");
c27a02cd
YP		 219 return -ENOMEM;
220 } else {
38aab07c 221 new_size = rounddown_pow_of_two(ring->actual_size);
453a6082
YP		 222 en_warn(priv, "Only %d buffers allocated "
223 "reducing ring size to %d",
224 ring->actual_size, new_size);
38aab07c 225 goto reduce_rings;
c27a02cd
YP		 226 }
227 }
228 ring->actual_size++;
229 ring->prod++;
230 }
231 }
38aab07c
YP		 232 return 0;
233
234reduce_rings:
235 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
236 ring = &priv->rx_ring[ring_ind];
237 while (ring->actual_size > new_size) {
238 ring->actual_size--;
239 ring->prod--;
240 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
241 }
38aab07c
YP		 242 }
243
c27a02cd
YP		 244 return 0;
245}
246
c27a02cd
YP		 247static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
248 struct mlx4_en_rx_ring *ring)
249{
c27a02cd 250 int index;
c27a02cd 251
453a6082
YP		 252 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
253 ring->cons, ring->prod);
c27a02cd
YP		 254
255 /* Unmap and free Rx buffers */
38aab07c 256 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
c27a02cd
YP		 257 while (ring->cons != ring->prod) {
258 index = ring->cons & ring->size_mask;
453a6082 259 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
38aab07c 260 mlx4_en_free_rx_desc(priv, ring, index);
c27a02cd
YP		 261 ++ring->cons;
262 }
263}
264
c27a02cd
YP		 265int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
266 struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
267{
268 struct mlx4_en_dev *mdev = priv->mdev;
269 int err;
270 int tmp;
271
c27a02cd
YP		 272
273 ring->prod = 0;
274 ring->cons = 0;
275 ring->size = size;
276 ring->size_mask = size - 1;
277 ring->stride = stride;
278 ring->log_stride = ffs(ring->stride) - 1;
9f519f68 279 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
c27a02cd
YP		 280
281 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
282 sizeof(struct skb_frag_struct));
283 ring->rx_info = vmalloc(tmp);
284 if (!ring->rx_info) {
453a6082 285 en_err(priv, "Failed allocating rx_info ring\n");
c27a02cd
YP		 286 return -ENOMEM;
287 }
453a6082 288 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
c27a02cd
YP		 289 ring->rx_info, tmp);
290
291 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
292 ring->buf_size, 2 * PAGE_SIZE);
293 if (err)
294 goto err_ring;
295
296 err = mlx4_en_map_buffer(&ring->wqres.buf);
297 if (err) {
453a6082 298 en_err(priv, "Failed to map RX buffer\n");
c27a02cd
YP		 299 goto err_hwq;
300 }
301 ring->buf = ring->wqres.buf.direct.buf;
302
c27a02cd
YP		 303 return 0;
304
c27a02cd
YP		 305err_hwq:
306 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
307err_ring:
308 vfree(ring->rx_info);
309 ring->rx_info = NULL;
310 return err;
311}
312
313int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
314{
c27a02cd
YP		 315 struct mlx4_en_rx_ring *ring;
316 int i;
317 int ring_ind;
318 int err;
319 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
320 DS_SIZE * priv->num_frags);
c27a02cd
YP		 321
322 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
323 ring = &priv->rx_ring[ring_ind];
324
325 ring->prod = 0;
326 ring->cons = 0;
327 ring->actual_size = 0;
328 ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
329
330 ring->stride = stride;
9f519f68
YP		 331 if (ring->stride <= TXBB_SIZE)
332 ring->buf += TXBB_SIZE;
333
c27a02cd
YP		 334 ring->log_stride = ffs(ring->stride) - 1;
335 ring->buf_size = ring->size * ring->stride;
336
337 memset(ring->buf, 0, ring->buf_size);
338 mlx4_en_update_rx_prod_db(ring);
339
340 /* Initailize all descriptors */
341 for (i = 0; i < ring->size; i++)
342 mlx4_en_init_rx_desc(priv, ring, i);
343
344 /* Initialize page allocators */
345 err = mlx4_en_init_allocator(priv, ring);
346 if (err) {
453a6082 347 en_err(priv, "Failed initializing ring allocator\n");
60b1809f
YP		 348 if (ring->stride <= TXBB_SIZE)
349 ring->buf -= TXBB_SIZE;
9a4f92a6
YP		 350 ring_ind--;
351 goto err_allocator;
c27a02cd 352 }
c27a02cd 353 }
b58515be
IM		 354 err = mlx4_en_fill_rx_buffers(priv);
355 if (err)
c27a02cd
YP		 356 goto err_buffers;
357
358 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
359 ring = &priv->rx_ring[ring_ind];
360
00d7d7bc 361 ring->size_mask = ring->actual_size - 1;
c27a02cd 362 mlx4_en_update_rx_prod_db(ring);
c27a02cd
YP		 363 }
364
365 return 0;
366
c27a02cd
YP		 367err_buffers:
368 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
369 mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
370
371 ring_ind = priv->rx_ring_num - 1;
372err_allocator:
373 while (ring_ind >= 0) {
60b1809f
YP		 374 if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE)
375 priv->rx_ring[ring_ind].buf -= TXBB_SIZE;
c27a02cd
YP		 376 mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
377 ring_ind--;
378 }
379 return err;
380}
381
382void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
383 struct mlx4_en_rx_ring *ring)
384{
385 struct mlx4_en_dev *mdev = priv->mdev;
386
c27a02cd 387 mlx4_en_unmap_buffer(&ring->wqres.buf);
9f519f68 388 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size + TXBB_SIZE);
c27a02cd
YP		 389 vfree(ring->rx_info);
390 ring->rx_info = NULL;
391}
392
393void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
394 struct mlx4_en_rx_ring *ring)
395{
c27a02cd 396 mlx4_en_free_rx_buf(priv, ring);
9f519f68
YP		 397 if (ring->stride <= TXBB_SIZE)
398 ring->buf -= TXBB_SIZE;
c27a02cd
YP		 399 mlx4_en_destroy_allocator(priv, ring);
400}
401
402
403/* Unmap a completed descriptor and free unused pages */
404static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
405 struct mlx4_en_rx_desc *rx_desc,
406 struct skb_frag_struct *skb_frags,
407 struct skb_frag_struct *skb_frags_rx,
408 struct mlx4_en_rx_alloc *page_alloc,
409 int length)
410{
411 struct mlx4_en_dev *mdev = priv->mdev;
412 struct mlx4_en_frag_info *frag_info;
413 int nr;
414 dma_addr_t dma;
415
416 /* Collect used fragments while replacing them in the HW descirptors */
417 for (nr = 0; nr < priv->num_frags; nr++) {
418 frag_info = &priv->frag_info[nr];
419 if (length <= frag_info->frag_prefix_size)
420 break;
421
422 /* Save page reference in skb */
423 skb_frags_rx[nr].page = skb_frags[nr].page;
424 skb_frags_rx[nr].size = skb_frags[nr].size;
425 skb_frags_rx[nr].page_offset = skb_frags[nr].page_offset;
426 dma = be64_to_cpu(rx_desc->data[nr].addr);
427
428 /* Allocate a replacement page */
429 if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
430 goto fail;
431
432 /* Unmap buffer */
69351a29 433 pci_unmap_single(mdev->pdev, dma, skb_frags_rx[nr].size,
c27a02cd
YP		 434 PCI_DMA_FROMDEVICE);
435 }
436 /* Adjust size of last fragment to match actual length */
973507cb 437 if (nr > 0)
438 skb_frags_rx[nr - 1].size = length -
439 priv->frag_info[nr - 1].frag_prefix_size;
c27a02cd
YP		 440 return nr;
441
442fail:
443 /* Drop all accumulated fragments (which have already been replaced in
444 * the descriptor) of this packet; remaining fragments are reused... */
445 while (nr > 0) {
446 nr--;
447 put_page(skb_frags_rx[nr].page);
448 }
449 return 0;
450}
451
452
453static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
454 struct mlx4_en_rx_desc *rx_desc,
455 struct skb_frag_struct *skb_frags,
456 struct mlx4_en_rx_alloc *page_alloc,
457 unsigned int length)
458{
459 struct mlx4_en_dev *mdev = priv->mdev;
460 struct sk_buff *skb;
461 void *va;
462 int used_frags;
463 dma_addr_t dma;
464
465 skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN);
466 if (!skb) {
453a6082 467 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
c27a02cd
YP		 468 return NULL;
469 }
470 skb->dev = priv->dev;
471 skb_reserve(skb, NET_IP_ALIGN);
472 skb->len = length;
473 skb->truesize = length + sizeof(struct sk_buff);
474
475 /* Get pointer to first fragment so we could copy the headers into the
476 * (linear part of the) skb */
477 va = page_address(skb_frags[0].page) + skb_frags[0].page_offset;
478
479 if (length <= SMALL_PACKET_SIZE) {
480 /* We are copying all relevant data to the skb - temporarily
481 * synch buffers for the copy */
482 dma = be64_to_cpu(rx_desc->data[0].addr);
e4fc8560
FT		 483 dma_sync_single_for_cpu(&mdev->pdev->dev, dma, length,
484 DMA_FROM_DEVICE);
c27a02cd 485 skb_copy_to_linear_data(skb, va, length);
e4fc8560
FT		 486 dma_sync_single_for_device(&mdev->pdev->dev, dma, length,
487 DMA_FROM_DEVICE);
c27a02cd
YP		 488 skb->tail += length;
489 } else {
490
491 /* Move relevant fragments to skb */
492 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
493 skb_shinfo(skb)->frags,
494 page_alloc, length);
785a0982
YP		 495 if (unlikely(!used_frags)) {
496 kfree_skb(skb);
497 return NULL;
498 }
c27a02cd
YP		 499 skb_shinfo(skb)->nr_frags = used_frags;
500
501 /* Copy headers into the skb linear buffer */
502 memcpy(skb->data, va, HEADER_COPY_SIZE);
503 skb->tail += HEADER_COPY_SIZE;
504
505 /* Skip headers in first fragment */
506 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
507
508 /* Adjust size of first fragment */
509 skb_shinfo(skb)->frags[0].size -= HEADER_COPY_SIZE;
510 skb->data_len = length - HEADER_COPY_SIZE;
511 }
512 return skb;
513}
514
e7c1c2c4
YP		 515static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
516{
517 int i;
518 int offset = ETH_HLEN;
519
520 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
521 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
522 goto out_loopback;
523 }
524 /* Loopback found */
525 priv->loopback_ok = 1;
526
527out_loopback:
528 dev_kfree_skb_any(skb);
529}
c27a02cd
YP		 530
531int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
532{
533 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd
YP		 534 struct mlx4_cqe *cqe;
535 struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
536 struct skb_frag_struct *skb_frags;
c27a02cd
YP		 537 struct mlx4_en_rx_desc *rx_desc;
538 struct sk_buff *skb;
539 int index;
540 int nr;
541 unsigned int length;
542 int polled = 0;
543 int ip_summed;
544
545 if (!priv->port_up)
546 return 0;
547
548 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
549 * descriptor offset can be deduced from the CQE index instead of
550 * reading 'cqe->index' */
551 index = cq->mcq.cons_index & ring->size_mask;
552 cqe = &cq->buf[index];
553
554 /* Process all completed CQEs */
555 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
556 cq->mcq.cons_index & cq->size)) {
557
558 skb_frags = ring->rx_info + (index << priv->log_rx_info);
559 rx_desc = ring->buf + (index << ring->log_stride);
560
561 /*
562 * make sure we read the CQE after we read the ownership bit
563 */
564 rmb();
565
566 /* Drop packet on bad receive or bad checksum */
567 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
568 MLX4_CQE_OPCODE_ERROR)) {
453a6082 569 en_err(priv, "CQE completed in error - vendor "
c27a02cd
YP		 570 "syndrom:%d syndrom:%d\n",
571 ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
572 ((struct mlx4_err_cqe *) cqe)->syndrome);
573 goto next;
574 }
575 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
453a6082 576 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
c27a02cd
YP		 577 goto next;
578 }
579
580 /*
581 * Packet is OK - process it.
582 */
583 length = be32_to_cpu(cqe->byte_cnt);
584 ring->bytes += length;
585 ring->packets++;
586
c8c64cff 587 if (likely(dev->features & NETIF_F_RXCSUM)) {
c27a02cd
YP		 588 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
589 (cqe->checksum == cpu_to_be16(0xffff))) {
590 priv->port_stats.rx_chksum_good++;
591 /* This packet is eligible for LRO if it is:
592 * - DIX Ethernet (type interpretation)
593 * - TCP/IP (v4)
594 * - without IP options
595 * - not an IP fragment */
fa37a958
YP		 596 if (dev->features & NETIF_F_GRO) {
597 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
ebc872c7
YP		 598 if (!gro_skb)
599 goto next;
c27a02cd
YP		 600
601 nr = mlx4_en_complete_rx_desc(
602 priv, rx_desc,
fa37a958 603 skb_frags, skb_shinfo(gro_skb)->frags,
c27a02cd
YP		 604 ring->page_alloc, length);
605 if (!nr)
606 goto next;
607
fa37a958
YP		 608 skb_shinfo(gro_skb)->nr_frags = nr;
609 gro_skb->len = length;
610 gro_skb->data_len = length;
611 gro_skb->truesize += length;
612 gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
613
c27a02cd 614 if (priv->vlgrp && (cqe->vlan_my_qpn &
fa37a958
YP		 615 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)))
616 vlan_gro_frags(&cq->napi, priv->vlgrp, be16_to_cpu(cqe->sl_vid));
617 else
618 napi_gro_frags(&cq->napi);
c27a02cd
YP		 619
620 goto next;
621 }
622
623 /* LRO not possible, complete processing here */
624 ip_summed = CHECKSUM_UNNECESSARY;
c27a02cd
YP		 625 } else {
626 ip_summed = CHECKSUM_NONE;
627 priv->port_stats.rx_chksum_none++;
628 }
629 } else {
630 ip_summed = CHECKSUM_NONE;
631 priv->port_stats.rx_chksum_none++;
632 }
633
634 skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
635 ring->page_alloc, length);
636 if (!skb) {
637 priv->stats.rx_dropped++;
638 goto next;
639 }
640
e7c1c2c4
YP		 641 if (unlikely(priv->validate_loopback)) {
642 validate_loopback(priv, skb);
643 goto next;
644 }
645
c27a02cd
YP		 646 skb->ip_summed = ip_summed;
647 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 648 skb_record_rx_queue(skb, cq->ring);
c27a02cd
YP		 649
650 /* Push it up the stack */
651 if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) &
652 MLX4_CQE_VLAN_PRESENT_MASK)) {
653 vlan_hwaccel_receive_skb(skb, priv->vlgrp,
654 be16_to_cpu(cqe->sl_vid));
655 } else
656 netif_receive_skb(skb);
657
c27a02cd
YP		 658next:
659 ++cq->mcq.cons_index;
660 index = (cq->mcq.cons_index) & ring->size_mask;
661 cqe = &cq->buf[index];
662 if (++polled == budget) {
663 /* We are here because we reached the NAPI budget -
664 * flush only pending LRO sessions */
c27a02cd
YP		 665 goto out;
666 }
667 }
668
c27a02cd
YP		 669out:
670 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
671 mlx4_cq_set_ci(&cq->mcq);
672 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
673 ring->cons = cq->mcq.cons_index;
674 ring->prod += polled; /* Polled descriptors were realocated in place */
c27a02cd
YP		 675 mlx4_en_update_rx_prod_db(ring);
676 return polled;
677}
678
679
680void mlx4_en_rx_irq(struct mlx4_cq *mcq)
681{
682 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
683 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
684
685 if (priv->port_up)
288379f0 686 napi_schedule(&cq->napi);
c27a02cd
YP		 687 else
688 mlx4_en_arm_cq(priv, cq);
689}
690
691/* Rx CQ polling - called by NAPI */
692int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
693{
694 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
695 struct net_device *dev = cq->dev;
696 struct mlx4_en_priv *priv = netdev_priv(dev);
697 int done;
698
699 done = mlx4_en_process_rx_cq(dev, cq, budget);
700
701 /* If we used up all the quota - we're probably not done yet... */
702 if (done == budget)
703 INC_PERF_COUNTER(priv->pstats.napi_quota);
704 else {
705 /* Done for now */
288379f0 706 napi_complete(napi);
c27a02cd
YP		 707 mlx4_en_arm_cq(priv, cq);
708 }
709 return done;
710}
711
712
25985edc 713/* Calculate the last offset position that accommodates a full fragment
c27a02cd
YP		 714 * (assuming fagment size = stride-align) */
715static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
716{
717 u16 res = MLX4_EN_ALLOC_SIZE % stride;
718 u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
719
453a6082 720 en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
c27a02cd
YP		 721 "res:%d offset:%d\n", stride, align, res, offset);
722 return offset;
723}
724
725
726static int frag_sizes[] = {
727 FRAG_SZ0,
728 FRAG_SZ1,
729 FRAG_SZ2,
730 FRAG_SZ3
731};
732
733void mlx4_en_calc_rx_buf(struct net_device *dev)
734{
735 struct mlx4_en_priv *priv = netdev_priv(dev);
736 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
737 int buf_size = 0;
738 int i = 0;
739
740 while (buf_size < eff_mtu) {
741 priv->frag_info[i].frag_size =
742 (eff_mtu > buf_size + frag_sizes[i]) ?
743 frag_sizes[i] : eff_mtu - buf_size;
744 priv->frag_info[i].frag_prefix_size = buf_size;
745 if (!i) {
746 priv->frag_info[i].frag_align = NET_IP_ALIGN;
747 priv->frag_info[i].frag_stride =
748 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
749 } else {
750 priv->frag_info[i].frag_align = 0;
751 priv->frag_info[i].frag_stride =
752 ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
753 }
754 priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
755 priv, priv->frag_info[i].frag_stride,
756 priv->frag_info[i].frag_align);
757 buf_size += priv->frag_info[i].frag_size;
758 i++;
759 }
760
761 priv->num_frags = i;
762 priv->rx_skb_size = eff_mtu;
763 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
764
453a6082 765 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
c27a02cd
YP		 766 "num_frags:%d):\n", eff_mtu, priv->num_frags);
767 for (i = 0; i < priv->num_frags; i++) {
453a6082 768 en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
c27a02cd
YP		 769 "stride:%d last_offset:%d\n", i,
770 priv->frag_info[i].frag_size,
771 priv->frag_info[i].frag_prefix_size,
772 priv->frag_info[i].frag_align,
773 priv->frag_info[i].frag_stride,
774 priv->frag_info[i].last_offset);
775 }
776}
777
778/* RSS related functions */
779
9f519f68
YP		 780static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
781 struct mlx4_en_rx_ring *ring,
c27a02cd
YP		 782 enum mlx4_qp_state *state,
783 struct mlx4_qp *qp)
784{
785 struct mlx4_en_dev *mdev = priv->mdev;
786 struct mlx4_qp_context *context;
787 int err = 0;
788
789 context = kmalloc(sizeof *context , GFP_KERNEL);
790 if (!context) {
453a6082 791 en_err(priv, "Failed to allocate qp context\n");
c27a02cd
YP		 792 return -ENOMEM;
793 }
794
795 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
796 if (err) {
453a6082 797 en_err(priv, "Failed to allocate qp #%x\n", qpn);
c27a02cd 798 goto out;
c27a02cd
YP		 799 }
800 qp->event = mlx4_en_sqp_event;
801
802 memset(context, 0, sizeof *context);
00d7d7bc 803 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
9f519f68
YP		 804 qpn, ring->cqn, context);
805 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
c27a02cd 806
9f519f68 807 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
c27a02cd
YP		 808 if (err) {
809 mlx4_qp_remove(mdev->dev, qp);
810 mlx4_qp_free(mdev->dev, qp);
811 }
9f519f68 812 mlx4_en_update_rx_prod_db(ring);
c27a02cd
YP		 813out:
814 kfree(context);
815 return err;
816}
817
818/* Allocate rx qp's and configure them according to rss map */
819int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
820{
821 struct mlx4_en_dev *mdev = priv->mdev;
822 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
823 struct mlx4_qp_context context;
824 struct mlx4_en_rss_context *rss_context;
825 void *ptr;
0533943c 826 u8 rss_mask = 0x3f;
9f519f68 827 int i, qpn;
c27a02cd
YP		 828 int err = 0;
829 int good_qps = 0;
830
453a6082 831 en_dbg(DRV, priv, "Configuring rss steering\n");
b6b912e0
YP		 832 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
833 priv->rx_ring_num,
834 &rss_map->base_qpn);
c27a02cd 835 if (err) {
b6b912e0 836 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
c27a02cd
YP		 837 return err;
838 }
839
b6b912e0 840 for (i = 0; i < priv->rx_ring_num; i++) {
c27a02cd 841 qpn = rss_map->base_qpn + i;
9f519f68 842 err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i],
c27a02cd
YP		 843 &rss_map->state[i],
844 &rss_map->qps[i]);
845 if (err)
846 goto rss_err;
847
848 ++good_qps;
849 }
850
851 /* Configure RSS indirection qp */
c27a02cd
YP		 852 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
853 if (err) {
453a6082 854 en_err(priv, "Failed to allocate RSS indirection QP\n");
1679200f 855 goto rss_err;
c27a02cd
YP		 856 }
857 rss_map->indir_qp.event = mlx4_en_sqp_event;
858 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
9f519f68 859 priv->rx_ring[0].cqn, &context);
c27a02cd
YP		 860
861 ptr = ((void *) &context) + 0x3c;
862 rss_context = (struct mlx4_en_rss_context *) ptr;
b6b912e0 863 rss_context->base_qpn = cpu_to_be32(ilog2(priv->rx_ring_num) << 24 |
c27a02cd
YP		 864 (rss_map->base_qpn));
865 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
0533943c 866 rss_context->flags = rss_mask;
c27a02cd 867
0533943c
YP		 868 if (priv->mdev->profile.udp_rss)
869 rss_context->base_qpn_udp = rss_context->default_qpn;
c27a02cd
YP		 870 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
871 &rss_map->indir_qp, &rss_map->indir_state);
872 if (err)
873 goto indir_err;
874
875 return 0;
876
877indir_err:
878 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
879 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
880 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
881 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
c27a02cd
YP		 882rss_err:
883 for (i = 0; i < good_qps; i++) {
884 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
885 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
886 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
887 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
888 }
b6b912e0 889 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
c27a02cd
YP		 890 return err;
891}
892
893void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
894{
895 struct mlx4_en_dev *mdev = priv->mdev;
896 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
897 int i;
898
899 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
900 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
901 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
902 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
c27a02cd 903
b6b912e0 904 for (i = 0; i < priv->rx_ring_num; i++) {
c27a02cd
YP		 905 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
906 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
907 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
908 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
909 }
b6b912e0 910 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
c27a02cd
YP		 911}
912
913
914
915
916
Linux 6.x block layer and io_uring tree(s)