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ixgbe: update dca to new interface, fix CONFIG_DCA_MODULE
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720
SH		 48static const char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 50
8d792cd9 51#define DRV_VERSION "1.3.18-k4"
9c8eb720
SH		 52const char ixgbe_driver_version[] = DRV_VERSION;
53static const char ixgbe_copyright[] =
54 "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
3957d63d 57 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 74 board_82598 },
8d792cd9
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
76 board_82598 },
9a799d71
AK		 77
78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
82
96b0e0f6 83#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 84static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
85 void *p);
86static struct notifier_block dca_notifier = {
87 .notifier_call = ixgbe_notify_dca,
88 .next = NULL,
89 .priority = 0
90};
91#endif
92
9a799d71
AK		 93MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
94MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
95MODULE_LICENSE("GPL");
96MODULE_VERSION(DRV_VERSION);
97
98#define DEFAULT_DEBUG_LEVEL_SHIFT 3
99
5eba3699
AV		 100static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
101{
102 u32 ctrl_ext;
103
104 /* Let firmware take over control of h/w */
105 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
107 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
108}
109
110static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
111{
112 u32 ctrl_ext;
113
114 /* Let firmware know the driver has taken over */
115 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
117 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
118}
9a799d71
AK		 119
120#ifdef DEBUG
121/**
122 * ixgbe_get_hw_dev_name - return device name string
123 * used by hardware layer to print debugging information
124 **/
125char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
126{
127 struct ixgbe_adapter *adapter = hw->back;
128 struct net_device *netdev = adapter->netdev;
129 return netdev->name;
130}
131#endif
132
133static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
134 u8 msix_vector)
135{
136 u32 ivar, index;
137
138 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
139 index = (int_alloc_entry >> 2) & 0x1F;
140 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
141 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
142 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
144}
145
146static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
147 struct ixgbe_tx_buffer
148 *tx_buffer_info)
149{
150 if (tx_buffer_info->dma) {
e01c31a5 151 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
9a799d71
AK		 152 tx_buffer_info->length, PCI_DMA_TODEVICE);
153 tx_buffer_info->dma = 0;
154 }
155 if (tx_buffer_info->skb) {
156 dev_kfree_skb_any(tx_buffer_info->skb);
157 tx_buffer_info->skb = NULL;
158 }
159 /* tx_buffer_info must be completely set up in the transmit path */
160}
161
162static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
163 struct ixgbe_ring *tx_ring,
e01c31a5 164 unsigned int eop)
9a799d71 165{
e01c31a5
JB		 166 struct ixgbe_hw *hw = &adapter->hw;
167 u32 head, tail;
168
9a799d71 169 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 170 * check with the clearing of time_stamp and movement of eop */
171 head = IXGBE_READ_REG(hw, tx_ring->head);
172 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 173 adapter->detect_tx_hung = false;
e01c31a5
JB		 174 if ((head != tail) &&
175 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 176 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
177 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
178 /* detected Tx unit hang */
e01c31a5
JB		 179 union ixgbe_adv_tx_desc *tx_desc;
180 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 181 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 182 " Tx Queue <%d>\n"
183 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 184 " next_to_use <%x>\n"
185 " next_to_clean <%x>\n"
186 "tx_buffer_info[next_to_clean]\n"
187 " time_stamp <%lx>\n"
e01c31a5
JB		 188 " jiffies <%lx>\n",
189 tx_ring->queue_index,
190 head, tail,
191 tx_ring->next_to_use, eop,
192 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 193 return true;
194 }
195
196 return false;
197}
198
e092be60
AV		 199#define IXGBE_MAX_TXD_PWR 14
200#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
201
202/* Tx Descriptors needed, worst case */
203#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
204 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
205#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
206 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
207
e01c31a5
JB		 208#define GET_TX_HEAD_FROM_RING(ring) (\
209 *(volatile u32 *) \
210 ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
211static void ixgbe_tx_timeout(struct net_device *netdev);
212
9a799d71
AK		 213/**
214 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
215 * @adapter: board private structure
e01c31a5 216 * @tx_ring: tx ring to clean
9a799d71
AK		 217 **/
218static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 219 struct ixgbe_ring *tx_ring)
9a799d71 220{
e01c31a5 221 union ixgbe_adv_tx_desc *tx_desc;
9a799d71 222 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5
JB		 223 struct net_device *netdev = adapter->netdev;
224 struct sk_buff *skb;
225 unsigned int i;
226 u32 head, oldhead;
227 unsigned int count = 0;
228 unsigned int total_bytes = 0, total_packets = 0;
9a799d71 229
e01c31a5
JB		 230 rmb();
231 head = GET_TX_HEAD_FROM_RING(tx_ring);
232 head = le32_to_cpu(head);
9a799d71 233 i = tx_ring->next_to_clean;
e01c31a5
JB		 234 while (1) {
235 while (i != head) {
9a799d71
AK		 236 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
237 tx_buffer_info = &tx_ring->tx_buffer_info[i];
e01c31a5 238 skb = tx_buffer_info->skb;
9a799d71 239
e01c31a5 240 if (skb) {
e092be60 241 unsigned int segs, bytecount;
e01c31a5
JB		 242
243 /* gso_segs is currently only valid for tcp */
e092be60
AV		 244 segs = skb_shinfo(skb)->gso_segs ?: 1;
245 /* multiply data chunks by size of headers */
246 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 247 skb->len;
248 total_packets += segs;
249 total_bytes += bytecount;
e092be60 250 }
e01c31a5 251
9a799d71 252 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 253 tx_buffer_info);
9a799d71
AK		 254
255 i++;
256 if (i == tx_ring->count)
257 i = 0;
9a799d71 258
e01c31a5
JB		 259 count++;
260 if (count == tx_ring->count)
261 goto done_cleaning;
262 }
263 oldhead = head;
264 rmb();
265 head = GET_TX_HEAD_FROM_RING(tx_ring);
266 head = le32_to_cpu(head);
267 if (head == oldhead)
268 goto done_cleaning;
269 } /* while (1) */
270
271done_cleaning:
9a799d71
AK		 272 tx_ring->next_to_clean = i;
273
e092be60 274#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 275 if (unlikely(count && netif_carrier_ok(netdev) &&
276 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 277 /* Make sure that anybody stopping the queue after this
278 * sees the new next_to_clean.
279 */
280 smp_mb();
30eba97a
AV		 281 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
282 !test_bit(__IXGBE_DOWN, &adapter->state)) {
283 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 284 ++adapter->restart_queue;
30eba97a 285 }
e092be60 286 }
9a799d71 287
e01c31a5
JB		 288 if (adapter->detect_tx_hung) {
289 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
290 /* schedule immediate reset if we believe we hung */
291 DPRINTK(PROBE, INFO,
292 "tx hang %d detected, resetting adapter\n",
293 adapter->tx_timeout_count + 1);
294 ixgbe_tx_timeout(adapter->netdev);
295 }
296 }
9a799d71 297
e01c31a5
JB		 298 /* re-arm the interrupt */
299 if ((total_packets >= tx_ring->work_limit) ||
300 (count == tx_ring->count))
301 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 302
e01c31a5
JB		 303 tx_ring->total_bytes += total_bytes;
304 tx_ring->total_packets += total_packets;
305 tx_ring->stats.bytes += total_bytes;
306 tx_ring->stats.packets += total_packets;
307 adapter->net_stats.tx_bytes += total_bytes;
308 adapter->net_stats.tx_packets += total_packets;
309 return (total_packets ? true : false);
9a799d71
AK		 310}
311
96b0e0f6 312#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd 313static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
3a581073 314 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 315{
316 u32 rxctrl;
317 int cpu = get_cpu();
3a581073 318 int q = rx_ring - adapter->rx_ring;
bd0362dd 319
3a581073 320 if (rx_ring->cpu != cpu) {
bd0362dd
JC		 321 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
322 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
96b0e0f6 323 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 324 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
325 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
326 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 327 rx_ring->cpu = cpu;
bd0362dd
JC		 328 }
329 put_cpu();
330}
331
332static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
3a581073 333 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 334{
335 u32 txctrl;
336 int cpu = get_cpu();
3a581073 337 int q = tx_ring - adapter->tx_ring;
bd0362dd 338
3a581073 339 if (tx_ring->cpu != cpu) {
bd0362dd
JC		 340 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
341 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
96b0e0f6 342 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 343 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
344 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 345 tx_ring->cpu = cpu;
bd0362dd
JC		 346 }
347 put_cpu();
348}
349
350static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
351{
352 int i;
353
354 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
355 return;
356
357 for (i = 0; i < adapter->num_tx_queues; i++) {
358 adapter->tx_ring[i].cpu = -1;
359 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
360 }
361 for (i = 0; i < adapter->num_rx_queues; i++) {
362 adapter->rx_ring[i].cpu = -1;
363 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
364 }
365}
366
367static int __ixgbe_notify_dca(struct device *dev, void *data)
368{
369 struct net_device *netdev = dev_get_drvdata(dev);
370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
371 unsigned long event = *(unsigned long *)data;
372
373 switch (event) {
374 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 375 /* if we're already enabled, don't do it again */
376 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
377 break;
bd0362dd
JC		 378 /* Always use CB2 mode, difference is masked
379 * in the CB driver. */
380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 381 if (dca_add_requester(dev) == 0) {
96b0e0f6 382 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 383 ixgbe_setup_dca(adapter);
384 break;
385 }
386 /* Fall Through since DCA is disabled. */
387 case DCA_PROVIDER_REMOVE:
388 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
389 dca_remove_requester(dev);
390 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
392 }
393 break;
394 }
395
652f093f 396 return 0;
bd0362dd
JC		 397}
398
96b0e0f6 399#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
9a799d71
AK		 400/**
401 * ixgbe_receive_skb - Send a completed packet up the stack
402 * @adapter: board private structure
403 * @skb: packet to send up
177db6ff
MC		 404 * @status: hardware indication of status of receive
405 * @rx_ring: rx descriptor ring (for a specific queue) to setup
406 * @rx_desc: rx descriptor
9a799d71
AK		 407 **/
408static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
177db6ff
MC		 409 struct sk_buff *skb, u8 status,
410 struct ixgbe_ring *ring,
411 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 412{
177db6ff
MC		 413 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
414 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 415
177db6ff
MC		 416 if (adapter->netdev->features & NETIF_F_LRO &&
417 skb->ip_summed == CHECKSUM_UNNECESSARY) {
9a799d71 418 if (adapter->vlgrp && is_vlan)
177db6ff
MC		 419 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
420 adapter->vlgrp, tag,
421 rx_desc);
9a799d71 422 else
177db6ff
MC		 423 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
424 ring->lro_used = true;
425 } else {
426 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
427 if (adapter->vlgrp && is_vlan)
428 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
429 else
430 netif_receive_skb(skb);
431 } else {
432 if (adapter->vlgrp && is_vlan)
433 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
434 else
435 netif_rx(skb);
436 }
9a799d71
AK		 437 }
438}
439
e59bd25d
AV		 440/**
441 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
442 * @adapter: address of board private structure
443 * @status_err: hardware indication of status of receive
444 * @skb: skb currently being received and modified
445 **/
9a799d71 446static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 447 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 448{
449 skb->ip_summed = CHECKSUM_NONE;
450
712744be
JB		 451 /* Rx csum disabled */
452 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 453 return;
e59bd25d
AV		 454
455 /* if IP and error */
456 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
457 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 458 adapter->hw_csum_rx_error++;
459 return;
460 }
e59bd25d
AV		 461
462 if (!(status_err & IXGBE_RXD_STAT_L4CS))
463 return;
464
465 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
466 adapter->hw_csum_rx_error++;
467 return;
468 }
469
9a799d71 470 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 471 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 472 adapter->hw_csum_rx_good++;
473}
474
475/**
476 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
477 * @adapter: address of board private structure
478 **/
479static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 480 struct ixgbe_ring *rx_ring,
481 int cleaned_count)
9a799d71
AK		 482{
483 struct net_device *netdev = adapter->netdev;
484 struct pci_dev *pdev = adapter->pdev;
485 union ixgbe_adv_rx_desc *rx_desc;
3a581073 486 struct ixgbe_rx_buffer *bi;
9a799d71 487 unsigned int i;
7c6e0a43 488 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 489
490 i = rx_ring->next_to_use;
3a581073 491 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 492
493 while (cleaned_count--) {
494 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
495
3a581073
JB		 496 if (!bi->page &&
497 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
498 bi->page = alloc_page(GFP_ATOMIC);
499 if (!bi->page) {
9a799d71
AK		 500 adapter->alloc_rx_page_failed++;
501 goto no_buffers;
502 }
3a581073 503 bi->page_dma = pci_map_page(pdev, bi->page, 0,
7c6e0a43
JB		 504 PAGE_SIZE,
505 PCI_DMA_FROMDEVICE);
9a799d71
AK		 506 }
507
3a581073
JB		 508 if (!bi->skb) {
509 struct sk_buff *skb = netdev_alloc_skb(netdev, bufsz);
9a799d71
AK		 510
511 if (!skb) {
512 adapter->alloc_rx_buff_failed++;
513 goto no_buffers;
514 }
515
516 /*
517 * Make buffer alignment 2 beyond a 16 byte boundary
518 * this will result in a 16 byte aligned IP header after
519 * the 14 byte MAC header is removed
520 */
521 skb_reserve(skb, NET_IP_ALIGN);
522
3a581073
JB		 523 bi->skb = skb;
524 bi->dma = pci_map_single(pdev, skb->data, bufsz,
525 PCI_DMA_FROMDEVICE);
9a799d71
AK		 526 }
527 /* Refresh the desc even if buffer_addrs didn't change because
528 * each write-back erases this info. */
529 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 530 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
531 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 532 } else {
3a581073 533 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 534 }
535
536 i++;
537 if (i == rx_ring->count)
538 i = 0;
3a581073 539 bi = &rx_ring->rx_buffer_info[i];
9a799d71 540 }
7c6e0a43 541
9a799d71
AK		 542no_buffers:
543 if (rx_ring->next_to_use != i) {
544 rx_ring->next_to_use = i;
545 if (i-- == 0)
546 i = (rx_ring->count - 1);
547
548 /*
549 * Force memory writes to complete before letting h/w
550 * know there are new descriptors to fetch. (Only
551 * applicable for weak-ordered memory model archs,
552 * such as IA-64).
553 */
554 wmb();
555 writel(i, adapter->hw.hw_addr + rx_ring->tail);
556 }
557}
558
7c6e0a43
JB		 559static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
560{
561 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
562}
563
564static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
565{
566 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
567}
568
9a799d71 569static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 570 struct ixgbe_ring *rx_ring,
571 int *work_done, int work_to_do)
9a799d71
AK		 572{
573 struct net_device *netdev = adapter->netdev;
574 struct pci_dev *pdev = adapter->pdev;
575 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
576 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
577 struct sk_buff *skb;
578 unsigned int i;
7c6e0a43 579 u32 len, staterr;
177db6ff
MC		 580 u16 hdr_info;
581 bool cleaned = false;
9a799d71 582 int cleaned_count = 0;
d2f4fbe2 583 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 584
585 i = rx_ring->next_to_clean;
9a799d71
AK		 586 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
587 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
588 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 589
590 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 591 u32 upper_len = 0;
9a799d71
AK		 592 if (*work_done >= work_to_do)
593 break;
594 (*work_done)++;
595
596 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 597 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
598 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
599 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 600 if (hdr_info & IXGBE_RXDADV_SPH)
601 adapter->rx_hdr_split++;
602 if (len > IXGBE_RX_HDR_SIZE)
603 len = IXGBE_RX_HDR_SIZE;
604 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 605 } else {
9a799d71 606 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 607 }
9a799d71
AK		 608
609 cleaned = true;
610 skb = rx_buffer_info->skb;
611 prefetch(skb->data - NET_IP_ALIGN);
612 rx_buffer_info->skb = NULL;
613
614 if (len && !skb_shinfo(skb)->nr_frags) {
615 pci_unmap_single(pdev, rx_buffer_info->dma,
7c6e0a43
JB		 616 rx_ring->rx_buf_len + NET_IP_ALIGN,
617 PCI_DMA_FROMDEVICE);
9a799d71
AK		 618 skb_put(skb, len);
619 }
620
621 if (upper_len) {
622 pci_unmap_page(pdev, rx_buffer_info->page_dma,
623 PAGE_SIZE, PCI_DMA_FROMDEVICE);
624 rx_buffer_info->page_dma = 0;
625 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
626 rx_buffer_info->page, 0, upper_len);
627 rx_buffer_info->page = NULL;
628
629 skb->len += upper_len;
630 skb->data_len += upper_len;
631 skb->truesize += upper_len;
632 }
633
634 i++;
635 if (i == rx_ring->count)
636 i = 0;
637 next_buffer = &rx_ring->rx_buffer_info[i];
638
639 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
640 prefetch(next_rxd);
641
642 cleaned_count++;
643 if (staterr & IXGBE_RXD_STAT_EOP) {
644 rx_ring->stats.packets++;
645 rx_ring->stats.bytes += skb->len;
646 } else {
647 rx_buffer_info->skb = next_buffer->skb;
648 rx_buffer_info->dma = next_buffer->dma;
649 next_buffer->skb = skb;
650 adapter->non_eop_descs++;
651 goto next_desc;
652 }
653
654 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
655 dev_kfree_skb_irq(skb);
656 goto next_desc;
657 }
658
659 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 660
661 /* probably a little skewed due to removing CRC */
662 total_rx_bytes += skb->len;
663 total_rx_packets++;
664
9a799d71 665 skb->protocol = eth_type_trans(skb, netdev);
177db6ff 666 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 667 netdev->last_rx = jiffies;
668
669next_desc:
670 rx_desc->wb.upper.status_error = 0;
671
672 /* return some buffers to hardware, one at a time is too slow */
673 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
674 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
675 cleaned_count = 0;
676 }
677
678 /* use prefetched values */
679 rx_desc = next_rxd;
680 rx_buffer_info = next_buffer;
681
682 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 683 }
684
685 if (rx_ring->lro_used) {
686 lro_flush_all(&rx_ring->lro_mgr);
687 rx_ring->lro_used = false;
9a799d71
AK		 688 }
689
690 rx_ring->next_to_clean = i;
691 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
692
693 if (cleaned_count)
694 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
695
f494e8fa
AV		 696 rx_ring->total_packets += total_rx_packets;
697 rx_ring->total_bytes += total_rx_bytes;
698 adapter->net_stats.rx_bytes += total_rx_bytes;
699 adapter->net_stats.rx_packets += total_rx_packets;
700
9a799d71
AK		 701 return cleaned;
702}
703
021230d4 704static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 705/**
706 * ixgbe_configure_msix - Configure MSI-X hardware
707 * @adapter: board private structure
708 *
709 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
710 * interrupts.
711 **/
712static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
713{
021230d4
AV		 714 struct ixgbe_q_vector *q_vector;
715 int i, j, q_vectors, v_idx, r_idx;
716 u32 mask;
9a799d71 717
021230d4 718 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 719
021230d4
AV		 720 /* Populate the IVAR table and set the ITR values to the
721 * corresponding register.
722 */
723 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
724 q_vector = &adapter->q_vector[v_idx];
725 /* XXX for_each_bit(...) */
726 r_idx = find_first_bit(q_vector->rxr_idx,
727 adapter->num_rx_queues);
728
729 for (i = 0; i < q_vector->rxr_count; i++) {
730 j = adapter->rx_ring[r_idx].reg_idx;
731 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
732 r_idx = find_next_bit(q_vector->rxr_idx,
733 adapter->num_rx_queues,
734 r_idx + 1);
735 }
736 r_idx = find_first_bit(q_vector->txr_idx,
737 adapter->num_tx_queues);
738
739 for (i = 0; i < q_vector->txr_count; i++) {
740 j = adapter->tx_ring[r_idx].reg_idx;
741 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
742 r_idx = find_next_bit(q_vector->txr_idx,
743 adapter->num_tx_queues,
744 r_idx + 1);
745 }
746
747 /* if this is a tx only vector use half the irq (tx) rate */
748 if (q_vector->txr_count && !q_vector->rxr_count)
749 q_vector->eitr = adapter->tx_eitr;
750 else
751 /* rx only or mixed */
752 q_vector->eitr = adapter->rx_eitr;
753
754 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
755 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 756 }
757
021230d4
AV		 758 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
759 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
760
761 /* set up to autoclear timer, lsc, and the vectors */
762 mask = IXGBE_EIMS_ENABLE_MASK;
763 mask &= ~IXGBE_EIMS_OTHER;
764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 765}
766
f494e8fa
AV		 767enum latency_range {
768 lowest_latency = 0,
769 low_latency = 1,
770 bulk_latency = 2,
771 latency_invalid = 255
772};
773
774/**
775 * ixgbe_update_itr - update the dynamic ITR value based on statistics
776 * @adapter: pointer to adapter
777 * @eitr: eitr setting (ints per sec) to give last timeslice
778 * @itr_setting: current throttle rate in ints/second
779 * @packets: the number of packets during this measurement interval
780 * @bytes: the number of bytes during this measurement interval
781 *
782 * Stores a new ITR value based on packets and byte
783 * counts during the last interrupt. The advantage of per interrupt
784 * computation is faster updates and more accurate ITR for the current
785 * traffic pattern. Constants in this function were computed
786 * based on theoretical maximum wire speed and thresholds were set based
787 * on testing data as well as attempting to minimize response time
788 * while increasing bulk throughput.
789 * this functionality is controlled by the InterruptThrottleRate module
790 * parameter (see ixgbe_param.c)
791 **/
792static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
793 u32 eitr, u8 itr_setting,
794 int packets, int bytes)
795{
796 unsigned int retval = itr_setting;
797 u32 timepassed_us;
798 u64 bytes_perint;
799
800 if (packets == 0)
801 goto update_itr_done;
802
803
804 /* simple throttlerate management
805 * 0-20MB/s lowest (100000 ints/s)
806 * 20-100MB/s low (20000 ints/s)
807 * 100-1249MB/s bulk (8000 ints/s)
808 */
809 /* what was last interrupt timeslice? */
810 timepassed_us = 1000000/eitr;
811 bytes_perint = bytes / timepassed_us; /* bytes/usec */
812
813 switch (itr_setting) {
814 case lowest_latency:
815 if (bytes_perint > adapter->eitr_low)
816 retval = low_latency;
817 break;
818 case low_latency:
819 if (bytes_perint > adapter->eitr_high)
820 retval = bulk_latency;
821 else if (bytes_perint <= adapter->eitr_low)
822 retval = lowest_latency;
823 break;
824 case bulk_latency:
825 if (bytes_perint <= adapter->eitr_high)
826 retval = low_latency;
827 break;
828 }
829
830update_itr_done:
831 return retval;
832}
833
834static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
835{
836 struct ixgbe_adapter *adapter = q_vector->adapter;
837 struct ixgbe_hw *hw = &adapter->hw;
838 u32 new_itr;
839 u8 current_itr, ret_itr;
840 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
841 sizeof(struct ixgbe_q_vector);
842 struct ixgbe_ring *rx_ring, *tx_ring;
843
844 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
845 for (i = 0; i < q_vector->txr_count; i++) {
846 tx_ring = &(adapter->tx_ring[r_idx]);
847 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
848 q_vector->tx_eitr,
849 tx_ring->total_packets,
850 tx_ring->total_bytes);
851 /* if the result for this queue would decrease interrupt
852 * rate for this vector then use that result */
853 q_vector->tx_eitr = ((q_vector->tx_eitr > ret_itr) ?
854 q_vector->tx_eitr - 1 : ret_itr);
855 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
856 r_idx + 1);
857 }
858
859 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
860 for (i = 0; i < q_vector->rxr_count; i++) {
861 rx_ring = &(adapter->rx_ring[r_idx]);
862 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
863 q_vector->rx_eitr,
864 rx_ring->total_packets,
865 rx_ring->total_bytes);
866 /* if the result for this queue would decrease interrupt
867 * rate for this vector then use that result */
868 q_vector->rx_eitr = ((q_vector->rx_eitr > ret_itr) ?
869 q_vector->rx_eitr - 1 : ret_itr);
870 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
871 r_idx + 1);
872 }
873
874 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
875
876 switch (current_itr) {
877 /* counts and packets in update_itr are dependent on these numbers */
878 case lowest_latency:
879 new_itr = 100000;
880 break;
881 case low_latency:
882 new_itr = 20000; /* aka hwitr = ~200 */
883 break;
884 case bulk_latency:
885 default:
886 new_itr = 8000;
887 break;
888 }
889
890 if (new_itr != q_vector->eitr) {
891 u32 itr_reg;
892 /* do an exponential smoothing */
893 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
894 q_vector->eitr = new_itr;
895 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
896 /* must write high and low 16 bits to reset counter */
897 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
898 itr_reg);
899 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
900 }
901
902 return;
903}
904
9a799d71
AK		 905static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
906{
907 struct net_device *netdev = data;
908 struct ixgbe_adapter *adapter = netdev_priv(netdev);
909 struct ixgbe_hw *hw = &adapter->hw;
910 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
911
912 if (eicr & IXGBE_EICR_LSC) {
913 adapter->lsc_int++;
914 if (!test_bit(__IXGBE_DOWN, &adapter->state))
915 mod_timer(&adapter->watchdog_timer, jiffies);
916 }
d4f80882
AV		 917
918 if (!test_bit(__IXGBE_DOWN, &adapter->state))
919 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 920
921 return IRQ_HANDLED;
922}
923
924static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
925{
021230d4
AV		 926 struct ixgbe_q_vector *q_vector = data;
927 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 928 struct ixgbe_ring *tx_ring;
021230d4
AV		 929 int i, r_idx;
930
931 if (!q_vector->txr_count)
932 return IRQ_HANDLED;
933
934 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
935 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 936 tx_ring = &(adapter->tx_ring[r_idx]);
96b0e0f6 937#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd 938 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 939 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 940#endif
3a581073
JB		 941 tx_ring->total_bytes = 0;
942 tx_ring->total_packets = 0;
943 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4
AV		 944 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
945 r_idx + 1);
946 }
9a799d71 947
9a799d71
AK		 948 return IRQ_HANDLED;
949}
950
021230d4
AV		 951/**
952 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
953 * @irq: unused
954 * @data: pointer to our q_vector struct for this interrupt vector
955 **/
9a799d71
AK		 956static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
957{
021230d4
AV		 958 struct ixgbe_q_vector *q_vector = data;
959 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 960 struct ixgbe_ring *rx_ring;
021230d4
AV		 961 int r_idx;
962
963 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
964 if (!q_vector->rxr_count)
965 return IRQ_HANDLED;
966
3a581073 967 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 968 /* disable interrupts on this vector only */
3a581073
JB		 969 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
970 rx_ring->total_bytes = 0;
971 rx_ring->total_packets = 0;
021230d4
AV		 972 netif_rx_schedule(adapter->netdev, &q_vector->napi);
973
974 return IRQ_HANDLED;
975}
976
977static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
978{
979 ixgbe_msix_clean_rx(irq, data);
980 ixgbe_msix_clean_tx(irq, data);
9a799d71 981
9a799d71
AK		 982 return IRQ_HANDLED;
983}
984
021230d4
AV		 985/**
986 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
987 * @napi: napi struct with our devices info in it
988 * @budget: amount of work driver is allowed to do this pass, in packets
989 *
990 **/
9a799d71
AK		 991static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
992{
021230d4
AV		 993 struct ixgbe_q_vector *q_vector =
994 container_of(napi, struct ixgbe_q_vector, napi);
995 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 996 struct ixgbe_ring *rx_ring;
9a799d71 997 int work_done = 0;
021230d4 998 long r_idx;
9a799d71 999
021230d4 1000 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1001 rx_ring = &(adapter->rx_ring[r_idx]);
96b0e0f6 1002#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd 1003 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1004 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1005#endif
9a799d71 1006
3a581073 1007 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
9a799d71 1008
021230d4
AV		 1009 /* If all Rx work done, exit the polling mode */
1010 if (work_done < budget) {
1011 netif_rx_complete(adapter->netdev, napi);
f494e8fa
AV		 1012 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
1013 ixgbe_set_itr_msix(q_vector);
9a799d71 1014 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1015 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1016 }
1017
1018 return work_done;
1019}
1020
021230d4
AV		 1021static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1022 int r_idx)
1023{
1024 a->q_vector[v_idx].adapter = a;
1025 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1026 a->q_vector[v_idx].rxr_count++;
1027 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1028}
1029
1030static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1031 int r_idx)
1032{
1033 a->q_vector[v_idx].adapter = a;
1034 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1035 a->q_vector[v_idx].txr_count++;
1036 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1037}
1038
9a799d71 1039/**
021230d4
AV		 1040 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1041 * @adapter: board private structure to initialize
1042 * @vectors: allotted vector count for descriptor rings
9a799d71 1043 *
021230d4
AV		 1044 * This function maps descriptor rings to the queue-specific vectors
1045 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1046 * one vector per ring/queue, but on a constrained vector budget, we
1047 * group the rings as "efficiently" as possible. You would add new
1048 * mapping configurations in here.
9a799d71 1049 **/
021230d4
AV		 1050static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1051 int vectors)
1052{
1053 int v_start = 0;
1054 int rxr_idx = 0, txr_idx = 0;
1055 int rxr_remaining = adapter->num_rx_queues;
1056 int txr_remaining = adapter->num_tx_queues;
1057 int i, j;
1058 int rqpv, tqpv;
1059 int err = 0;
1060
1061 /* No mapping required if MSI-X is disabled. */
1062 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1063 goto out;
9a799d71 1064
021230d4
AV		 1065 /*
1066 * The ideal configuration...
1067 * We have enough vectors to map one per queue.
1068 */
1069 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1070 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1071 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1072
021230d4
AV		 1073 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1074 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1075
9a799d71 1076 goto out;
021230d4 1077 }
9a799d71 1078
021230d4
AV		 1079 /*
1080 * If we don't have enough vectors for a 1-to-1
1081 * mapping, we'll have to group them so there are
1082 * multiple queues per vector.
1083 */
1084 /* Re-adjusting *qpv takes care of the remainder. */
1085 for (i = v_start; i < vectors; i++) {
1086 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1087 for (j = 0; j < rqpv; j++) {
1088 map_vector_to_rxq(adapter, i, rxr_idx);
1089 rxr_idx++;
1090 rxr_remaining--;
1091 }
1092 }
1093 for (i = v_start; i < vectors; i++) {
1094 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1095 for (j = 0; j < tqpv; j++) {
1096 map_vector_to_txq(adapter, i, txr_idx);
1097 txr_idx++;
1098 txr_remaining--;
9a799d71 1099 }
9a799d71
AK		 1100 }
1101
021230d4
AV		 1102out:
1103 return err;
1104}
1105
1106/**
1107 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1108 * @adapter: board private structure
1109 *
1110 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1111 * interrupts from the kernel.
1112 **/
1113static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1114{
1115 struct net_device *netdev = adapter->netdev;
1116 irqreturn_t (*handler)(int, void *);
1117 int i, vector, q_vectors, err;
1118
1119 /* Decrement for Other and TCP Timer vectors */
1120 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1121
1122 /* Map the Tx/Rx rings to the vectors we were allotted. */
1123 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1124 if (err)
1125 goto out;
1126
1127#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1128 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1129 &ixgbe_msix_clean_many)
1130 for (vector = 0; vector < q_vectors; vector++) {
1131 handler = SET_HANDLER(&adapter->q_vector[vector]);
1132 sprintf(adapter->name[vector], "%s:v%d-%s",
1133 netdev->name, vector,
1134 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1135 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
1136 err = request_irq(adapter->msix_entries[vector].vector,
1137 handler, 0, adapter->name[vector],
1138 &(adapter->q_vector[vector]));
9a799d71
AK		 1139 if (err) {
1140 DPRINTK(PROBE, ERR,
1141 "request_irq failed for MSIX interrupt "
1142 "Error: %d\n", err);
021230d4 1143 goto free_queue_irqs;
9a799d71 1144 }
9a799d71
AK		 1145 }
1146
021230d4
AV		 1147 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1148 err = request_irq(adapter->msix_entries[vector].vector,
1149 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1150 if (err) {
1151 DPRINTK(PROBE, ERR,
1152 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1153 goto free_queue_irqs;
9a799d71
AK		 1154 }
1155
9a799d71
AK		 1156 return 0;
1157
021230d4
AV		 1158free_queue_irqs:
1159 for (i = vector - 1; i >= 0; i--)
1160 free_irq(adapter->msix_entries[--vector].vector,
1161 &(adapter->q_vector[i]));
1162 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1163 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1164 kfree(adapter->msix_entries);
1165 adapter->msix_entries = NULL;
021230d4 1166out:
9a799d71
AK		 1167 return err;
1168}
1169
f494e8fa
AV		 1170static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1171{
1172 struct ixgbe_hw *hw = &adapter->hw;
1173 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1174 u8 current_itr;
1175 u32 new_itr = q_vector->eitr;
1176 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1177 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1178
1179 q_vector->tx_eitr = ixgbe_update_itr(adapter, new_itr,
1180 q_vector->tx_eitr,
1181 tx_ring->total_packets,
1182 tx_ring->total_bytes);
1183 q_vector->rx_eitr = ixgbe_update_itr(adapter, new_itr,
1184 q_vector->rx_eitr,
1185 rx_ring->total_packets,
1186 rx_ring->total_bytes);
1187
1188 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
1189
1190 switch (current_itr) {
1191 /* counts and packets in update_itr are dependent on these numbers */
1192 case lowest_latency:
1193 new_itr = 100000;
1194 break;
1195 case low_latency:
1196 new_itr = 20000; /* aka hwitr = ~200 */
1197 break;
1198 case bulk_latency:
1199 new_itr = 8000;
1200 break;
1201 default:
1202 break;
1203 }
1204
1205 if (new_itr != q_vector->eitr) {
1206 u32 itr_reg;
1207 /* do an exponential smoothing */
1208 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1209 q_vector->eitr = new_itr;
1210 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1211 /* must write high and low 16 bits to reset counter */
1212 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1213 }
1214
1215 return;
1216}
1217
021230d4
AV		 1218static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1219
9a799d71 1220/**
021230d4 1221 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1222 * @irq: interrupt number
1223 * @data: pointer to a network interface device structure
1224 * @pt_regs: CPU registers structure
1225 **/
1226static irqreturn_t ixgbe_intr(int irq, void *data)
1227{
1228 struct net_device *netdev = data;
1229 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1230 struct ixgbe_hw *hw = &adapter->hw;
1231 u32 eicr;
1232
9a799d71 1233
021230d4
AV		 1234 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1235 * therefore no explict interrupt disable is necessary */
1236 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
9a799d71
AK		 1237 if (!eicr)
1238 return IRQ_NONE; /* Not our interrupt */
1239
1240 if (eicr & IXGBE_EICR_LSC) {
1241 adapter->lsc_int++;
1242 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1243 mod_timer(&adapter->watchdog_timer, jiffies);
1244 }
021230d4
AV		 1245
1246
1247 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
f494e8fa
AV		 1248 adapter->tx_ring[0].total_packets = 0;
1249 adapter->tx_ring[0].total_bytes = 0;
1250 adapter->rx_ring[0].total_packets = 0;
1251 adapter->rx_ring[0].total_bytes = 0;
021230d4
AV		 1252 /* would disable interrupts here but EIAM disabled it */
1253 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 1254 }
1255
1256 return IRQ_HANDLED;
1257}
1258
021230d4
AV		 1259static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1260{
1261 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1262
1263 for (i = 0; i < q_vectors; i++) {
1264 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1265 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1266 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1267 q_vector->rxr_count = 0;
1268 q_vector->txr_count = 0;
1269 }
1270}
1271
9a799d71
AK		 1272/**
1273 * ixgbe_request_irq - initialize interrupts
1274 * @adapter: board private structure
1275 *
1276 * Attempts to configure interrupts using the best available
1277 * capabilities of the hardware and kernel.
1278 **/
021230d4 1279static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1280{
1281 struct net_device *netdev = adapter->netdev;
021230d4 1282 int err;
9a799d71 1283
021230d4
AV		 1284 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1285 err = ixgbe_request_msix_irqs(adapter);
1286 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1287 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1288 netdev->name, netdev);
1289 } else {
1290 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1291 netdev->name, netdev);
9a799d71
AK		 1292 }
1293
9a799d71
AK		 1294 if (err)
1295 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1296
9a799d71
AK		 1297 return err;
1298}
1299
1300static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1301{
1302 struct net_device *netdev = adapter->netdev;
1303
1304 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1305 int i, q_vectors;
9a799d71 1306
021230d4
AV		 1307 q_vectors = adapter->num_msix_vectors;
1308
1309 i = q_vectors - 1;
9a799d71 1310 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1311
021230d4
AV		 1312 i--;
1313 for (; i >= 0; i--) {
1314 free_irq(adapter->msix_entries[i].vector,
1315 &(adapter->q_vector[i]));
1316 }
1317
1318 ixgbe_reset_q_vectors(adapter);
1319 } else {
1320 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1321 }
1322}
1323
1324/**
1325 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1326 * @adapter: board private structure
1327 **/
1328static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1329{
9a799d71
AK		 1330 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1331 IXGBE_WRITE_FLUSH(&adapter->hw);
021230d4
AV		 1332 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1333 int i;
1334 for (i = 0; i < adapter->num_msix_vectors; i++)
1335 synchronize_irq(adapter->msix_entries[i].vector);
1336 } else {
1337 synchronize_irq(adapter->pdev->irq);
1338 }
9a799d71
AK		 1339}
1340
1341/**
1342 * ixgbe_irq_enable - Enable default interrupt generation settings
1343 * @adapter: board private structure
1344 **/
1345static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1346{
021230d4
AV		 1347 u32 mask;
1348 mask = IXGBE_EIMS_ENABLE_MASK;
1349 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
d4f80882 1350 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1351}
1352
1353/**
1354 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1355 *
1356 **/
1357static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1358{
9a799d71
AK		 1359 struct ixgbe_hw *hw = &adapter->hw;
1360
021230d4
AV		 1361 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1362 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr));
9a799d71
AK		 1363
1364 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1365 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1366
1367 map_vector_to_rxq(adapter, 0, 0);
1368 map_vector_to_txq(adapter, 0, 0);
1369
1370 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1371}
1372
1373/**
3a581073 1374 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1375 * @adapter: board private structure
1376 *
1377 * Configure the Tx unit of the MAC after a reset.
1378 **/
1379static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1380{
e01c31a5 1381 u64 tdba, tdwba;
9a799d71 1382 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1383 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1384
1385 /* Setup the HW Tx Head and Tail descriptor pointers */
1386 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1387 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1388 j = ring->reg_idx;
1389 tdba = ring->dma;
1390 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1391 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1392 (tdba & DMA_32BIT_MASK));
021230d4 1393 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
e01c31a5
JB		 1394 tdwba = ring->dma +
1395 (ring->count * sizeof(union ixgbe_adv_tx_desc));
1396 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1397 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1398 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
021230d4
AV		 1399 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1400 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1401 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1402 adapter->tx_ring[i].head = IXGBE_TDH(j);
1403 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1404 /* Disable Tx Head Writeback RO bit, since this hoses
1405 * bookkeeping if things aren't delivered in order.
1406 */
e01c31a5 1407 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1408 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1409 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1410 }
9a799d71
AK		 1411}
1412
1413#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1414 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1415
1416#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
177db6ff
MC		 1417/**
1418 * ixgbe_get_skb_hdr - helper function for LRO header processing
1419 * @skb: pointer to sk_buff to be added to LRO packet
1420 * @iphdr: pointer to tcp header structure
1421 * @tcph: pointer to tcp header structure
1422 * @hdr_flags: pointer to header flags
1423 * @priv: private data
1424 **/
1425static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1426 u64 *hdr_flags, void *priv)
1427{
1428 union ixgbe_adv_rx_desc *rx_desc = priv;
1429
1430 /* Verify that this is a valid IPv4 TCP packet */
7c6e0a43 1431 if (!(ixgbe_get_pkt_info(rx_desc) &
177db6ff
MC		 1432 (IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP)))
1433 return -1;
1434
1435 /* Set network headers */
1436 skb_reset_network_header(skb);
1437 skb_set_transport_header(skb, ip_hdrlen(skb));
1438 *iphdr = ip_hdr(skb);
1439 *tcph = tcp_hdr(skb);
1440 *hdr_flags = LRO_IPV4 | LRO_TCP;
1441 return 0;
1442}
1443
9a799d71 1444/**
3a581073 1445 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1446 * @adapter: board private structure
1447 *
1448 * Configure the Rx unit of the MAC after a reset.
1449 **/
1450static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1451{
1452 u64 rdba;
1453 struct ixgbe_hw *hw = &adapter->hw;
1454 struct net_device *netdev = adapter->netdev;
1455 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1456 int i, j;
9a799d71 1457 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1458 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1459 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1460 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1461 u32 fctrl, hlreg0;
9a799d71 1462 u32 pages;
021230d4 1463 u32 reta = 0, mrqc, srrctl;
7c6e0a43 1464 int rx_buf_len;
9a799d71
AK		 1465
1466 /* Decide whether to use packet split mode or not */
1467 if (netdev->mtu > ETH_DATA_LEN)
1468 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1469 else
1470 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1471
1472 /* Set the RX buffer length according to the mode */
1473 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1474 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71
AK		 1475 } else {
1476 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1477 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1478 else
7c6e0a43 1479 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1480 }
1481
1482 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1483 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1484 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1485 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1486
1487 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1488 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1489 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1490 else
1491 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1492 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1493
1494 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1495
1496 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(0));
1497 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1498 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1499
1500 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1501 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1502 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1503 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1504 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1505 IXGBE_SRRCTL_BSIZEHDR_MASK);
1506 } else {
1507 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1508
7c6e0a43 1509 if (rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
9a799d71
AK		 1510 srrctl |=
1511 IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1512 else
7c6e0a43 1513 srrctl |= rx_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
9a799d71
AK		 1514 }
1515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(0), srrctl);
1516
1517 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1518 /* disable receives while setting up the descriptors */
1519 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1520 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1521
1522 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1523 * the Base and Length of the Rx Descriptor Ring */
1524 for (i = 0; i < adapter->num_rx_queues; i++) {
1525 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1526 j = adapter->rx_ring[i].reg_idx;
1527 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1528 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1529 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1530 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1531 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1532 adapter->rx_ring[i].head = IXGBE_RDH(j);
1533 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1534 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
9a799d71
AK		 1535 }
1536
177db6ff
MC		 1537 /* Intitial LRO Settings */
1538 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1539 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1540 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1541 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1542 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1543 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1544 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1545 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1546 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1547
021230d4 1548 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1549 /* Fill out redirection table */
021230d4
AV		 1550 for (i = 0, j = 0; i < 128; i++, j++) {
1551 if (j == adapter->ring_feature[RING_F_RSS].indices)
1552 j = 0;
1553 /* reta = 4-byte sliding window of
1554 * 0x00..(indices-1)(indices-1)00..etc. */
1555 reta = (reta << 8) | (j * 0x11);
1556 if ((i & 3) == 3)
1557 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1558 }
1559
1560 /* Fill out hash function seeds */
1561 for (i = 0; i < 10; i++)
7c6e0a43 1562 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1563
1564 mrqc = IXGBE_MRQC_RSSEN
1565 /* Perform hash on these packet types */
7c6e0a43
JB		 1566 | IXGBE_MRQC_RSS_FIELD_IPV4
1567 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1568 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1569 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1570 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1571 | IXGBE_MRQC_RSS_FIELD_IPV6
1572 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1573 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1574 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
9a799d71 1575 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1576 }
9a799d71 1577
021230d4
AV		 1578 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1579
1580 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1581 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1582 /* Disable indicating checksum in descriptor, enables
1583 * RSS hash */
9a799d71 1584 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1585 }
021230d4
AV		 1586 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1587 /* Enable IPv4 payload checksum for UDP fragments
1588 * if PCSD is not set */
1589 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1590 }
1591
1592 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1593}
1594
1595static void ixgbe_vlan_rx_register(struct net_device *netdev,
1596 struct vlan_group *grp)
1597{
1598 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1599 u32 ctrl;
1600
d4f80882
AV		 1601 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1602 ixgbe_irq_disable(adapter);
9a799d71
AK		 1603 adapter->vlgrp = grp;
1604
1605 if (grp) {
1606 /* enable VLAN tag insert/strip */
1607 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1608 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1609 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1611 }
1612
d4f80882
AV		 1613 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1614 ixgbe_irq_enable(adapter);
9a799d71
AK		 1615}
1616
1617static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1618{
1619 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1620
1621 /* add VID to filter table */
1622 ixgbe_set_vfta(&adapter->hw, vid, 0, true);
1623}
1624
1625static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1626{
1627 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1628
d4f80882
AV		 1629 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1630 ixgbe_irq_disable(adapter);
1631
9a799d71 1632 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1633
1634 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1635 ixgbe_irq_enable(adapter);
9a799d71
AK		 1636
1637 /* remove VID from filter table */
1638 ixgbe_set_vfta(&adapter->hw, vid, 0, false);
1639}
1640
1641static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1642{
1643 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1644
1645 if (adapter->vlgrp) {
1646 u16 vid;
1647 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1648 if (!vlan_group_get_device(adapter->vlgrp, vid))
1649 continue;
1650 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1651 }
1652 }
1653}
1654
2c5645cf
CL		 1655static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1656{
1657 struct dev_mc_list *mc_ptr;
1658 u8 *addr = *mc_addr_ptr;
1659 *vmdq = 0;
1660
1661 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1662 if (mc_ptr->next)
1663 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1664 else
1665 *mc_addr_ptr = NULL;
1666
1667 return addr;
1668}
1669
9a799d71 1670/**
2c5645cf 1671 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1672 * @netdev: network interface device structure
1673 *
2c5645cf
CL		 1674 * The set_rx_method entry point is called whenever the unicast/multicast
1675 * address list or the network interface flags are updated. This routine is
1676 * responsible for configuring the hardware for proper unicast, multicast and
1677 * promiscuous mode.
9a799d71 1678 **/
2c5645cf 1679static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1680{
1681 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1682 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1683 u32 fctrl, vlnctrl;
2c5645cf
CL		 1684 u8 *addr_list = NULL;
1685 int addr_count = 0;
9a799d71
AK		 1686
1687 /* Check for Promiscuous and All Multicast modes */
1688
1689 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1690 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1691
1692 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1693 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1694 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1695 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1696 } else {
746b9f02
PM		 1697 if (netdev->flags & IFF_ALLMULTI) {
1698 fctrl |= IXGBE_FCTRL_MPE;
1699 fctrl &= ~IXGBE_FCTRL_UPE;
1700 } else {
1701 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1702 }
3d01625a 1703 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 1704 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 1705 }
1706
1707 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1708 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 1709
2c5645cf
CL		 1710 /* reprogram secondary unicast list */
1711 addr_count = netdev->uc_count;
1712 if (addr_count)
1713 addr_list = netdev->uc_list->dmi_addr;
1714 ixgbe_update_uc_addr_list(hw, addr_list, addr_count,
1715 ixgbe_addr_list_itr);
9a799d71 1716
2c5645cf
CL		 1717 /* reprogram multicast list */
1718 addr_count = netdev->mc_count;
1719 if (addr_count)
1720 addr_list = netdev->mc_list->dmi_addr;
1721 ixgbe_update_mc_addr_list(hw, addr_list, addr_count,
1722 ixgbe_addr_list_itr);
9a799d71
AK		 1723}
1724
021230d4
AV		 1725static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1726{
1727 int q_idx;
1728 struct ixgbe_q_vector *q_vector;
1729 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1730
1731 /* legacy and MSI only use one vector */
1732 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1733 q_vectors = 1;
1734
1735 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1736 q_vector = &adapter->q_vector[q_idx];
1737 if (!q_vector->rxr_count)
1738 continue;
1739 napi_enable(&q_vector->napi);
1740 }
1741}
1742
1743static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1744{
1745 int q_idx;
1746 struct ixgbe_q_vector *q_vector;
1747 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1748
1749 /* legacy and MSI only use one vector */
1750 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1751 q_vectors = 1;
1752
1753 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1754 q_vector = &adapter->q_vector[q_idx];
1755 if (!q_vector->rxr_count)
1756 continue;
1757 napi_disable(&q_vector->napi);
1758 }
1759}
1760
9a799d71
AK		 1761static void ixgbe_configure(struct ixgbe_adapter *adapter)
1762{
1763 struct net_device *netdev = adapter->netdev;
1764 int i;
1765
2c5645cf 1766 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 1767
1768 ixgbe_restore_vlan(adapter);
1769
1770 ixgbe_configure_tx(adapter);
1771 ixgbe_configure_rx(adapter);
1772 for (i = 0; i < adapter->num_rx_queues; i++)
1773 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1774 (adapter->rx_ring[i].count - 1));
1775}
1776
1777static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1778{
1779 struct net_device *netdev = adapter->netdev;
9a799d71 1780 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1781 int i, j = 0;
9a799d71 1782 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1783 u32 txdctl, rxdctl, mhadd;
1784 u32 gpie;
9a799d71 1785
5eba3699
AV		 1786 ixgbe_get_hw_control(adapter);
1787
021230d4
AV		 1788 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1789 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1790 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1791 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1792 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1793 } else {
1794 /* MSI only */
021230d4 1795 gpie = 0;
9a799d71 1796 }
021230d4
AV		 1797 /* XXX: to interrupt immediately for EICS writes, enable this */
1798 /* gpie |= IXGBE_GPIE_EIMEN; */
1799 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1800 }
1801
021230d4
AV		 1802 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1803 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1804 * specifically only auto mask tx and rx interrupts */
1805 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1806 }
9a799d71 1807
021230d4 1808 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1809 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1810 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1811 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1812
1813 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1814 }
1815
1816 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 1817 j = adapter->tx_ring[i].reg_idx;
1818 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 1819 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1820 txdctl |= (8 << 16);
9a799d71 1821 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 1822 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 1823 }
1824
1825 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 1826 j = adapter->rx_ring[i].reg_idx;
1827 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1828 /* enable PTHRESH=32 descriptors (half the internal cache)
1829 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1830 * this also removes a pesky rx_no_buffer_count increment */
1831 rxdctl |= 0x0020;
9a799d71 1832 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 1833 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 1834 }
1835 /* enable all receives */
1836 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1837 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1838 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1839
1840 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1841 ixgbe_configure_msix(adapter);
1842 else
1843 ixgbe_configure_msi_and_legacy(adapter);
1844
1845 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 1846 ixgbe_napi_enable_all(adapter);
1847
1848 /* clear any pending interrupts, may auto mask */
1849 IXGBE_READ_REG(hw, IXGBE_EICR);
1850
9a799d71
AK		 1851 ixgbe_irq_enable(adapter);
1852
1853 /* bring the link up in the watchdog, this could race with our first
1854 * link up interrupt but shouldn't be a problem */
1855 mod_timer(&adapter->watchdog_timer, jiffies);
1856 return 0;
1857}
1858
d4f80882
AV		 1859void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1860{
1861 WARN_ON(in_interrupt());
1862 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1863 msleep(1);
1864 ixgbe_down(adapter);
1865 ixgbe_up(adapter);
1866 clear_bit(__IXGBE_RESETTING, &adapter->state);
1867}
1868
9a799d71
AK		 1869int ixgbe_up(struct ixgbe_adapter *adapter)
1870{
1871 /* hardware has been reset, we need to reload some things */
1872 ixgbe_configure(adapter);
1873
1874 return ixgbe_up_complete(adapter);
1875}
1876
1877void ixgbe_reset(struct ixgbe_adapter *adapter)
1878{
1879 if (ixgbe_init_hw(&adapter->hw))
1880 DPRINTK(PROBE, ERR, "Hardware Error\n");
1881
1882 /* reprogram the RAR[0] in case user changed it. */
1883 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
1884
1885}
1886
1887#ifdef CONFIG_PM
1888static int ixgbe_resume(struct pci_dev *pdev)
1889{
1890 struct net_device *netdev = pci_get_drvdata(pdev);
1891 struct ixgbe_adapter *adapter = netdev_priv(netdev);
021230d4 1892 u32 err;
9a799d71
AK		 1893
1894 pci_set_power_state(pdev, PCI_D0);
1895 pci_restore_state(pdev);
1896 err = pci_enable_device(pdev);
1897 if (err) {
1898 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
1899 "suspend\n");
1900 return err;
1901 }
1902 pci_set_master(pdev);
1903
1904 pci_enable_wake(pdev, PCI_D3hot, 0);
1905 pci_enable_wake(pdev, PCI_D3cold, 0);
1906
1907 if (netif_running(netdev)) {
021230d4 1908 err = ixgbe_request_irq(adapter);
9a799d71
AK		 1909 if (err)
1910 return err;
1911 }
1912
1913 ixgbe_reset(adapter);
1914
1915 if (netif_running(netdev))
1916 ixgbe_up(adapter);
1917
1918 netif_device_attach(netdev);
1919
1920 return 0;
1921}
1922#endif
1923
1924/**
1925 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
1926 * @adapter: board private structure
1927 * @rx_ring: ring to free buffers from
1928 **/
1929static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
1930 struct ixgbe_ring *rx_ring)
1931{
1932 struct pci_dev *pdev = adapter->pdev;
1933 unsigned long size;
1934 unsigned int i;
1935
1936 /* Free all the Rx ring sk_buffs */
1937
1938 for (i = 0; i < rx_ring->count; i++) {
1939 struct ixgbe_rx_buffer *rx_buffer_info;
1940
1941 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1942 if (rx_buffer_info->dma) {
1943 pci_unmap_single(pdev, rx_buffer_info->dma,
7c6e0a43 1944 rx_ring->rx_buf_len,
9a799d71
AK		 1945 PCI_DMA_FROMDEVICE);
1946 rx_buffer_info->dma = 0;
1947 }
1948 if (rx_buffer_info->skb) {
1949 dev_kfree_skb(rx_buffer_info->skb);
1950 rx_buffer_info->skb = NULL;
1951 }
1952 if (!rx_buffer_info->page)
1953 continue;
1954 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE,
1955 PCI_DMA_FROMDEVICE);
1956 rx_buffer_info->page_dma = 0;
1957
1958 put_page(rx_buffer_info->page);
1959 rx_buffer_info->page = NULL;
1960 }
1961
1962 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1963 memset(rx_ring->rx_buffer_info, 0, size);
1964
1965 /* Zero out the descriptor ring */
1966 memset(rx_ring->desc, 0, rx_ring->size);
1967
1968 rx_ring->next_to_clean = 0;
1969 rx_ring->next_to_use = 0;
1970
1971 writel(0, adapter->hw.hw_addr + rx_ring->head);
1972 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1973}
1974
1975/**
1976 * ixgbe_clean_tx_ring - Free Tx Buffers
1977 * @adapter: board private structure
1978 * @tx_ring: ring to be cleaned
1979 **/
1980static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
1981 struct ixgbe_ring *tx_ring)
1982{
1983 struct ixgbe_tx_buffer *tx_buffer_info;
1984 unsigned long size;
1985 unsigned int i;
1986
1987 /* Free all the Tx ring sk_buffs */
1988
1989 for (i = 0; i < tx_ring->count; i++) {
1990 tx_buffer_info = &tx_ring->tx_buffer_info[i];
1991 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1992 }
1993
1994 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
1995 memset(tx_ring->tx_buffer_info, 0, size);
1996
1997 /* Zero out the descriptor ring */
1998 memset(tx_ring->desc, 0, tx_ring->size);
1999
2000 tx_ring->next_to_use = 0;
2001 tx_ring->next_to_clean = 0;
2002
2003 writel(0, adapter->hw.hw_addr + tx_ring->head);
2004 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2005}
2006
2007/**
021230d4 2008 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2009 * @adapter: board private structure
2010 **/
021230d4 2011static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2012{
2013 int i;
2014
021230d4
AV		 2015 for (i = 0; i < adapter->num_rx_queues; i++)
2016 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2017}
2018
2019/**
021230d4 2020 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2021 * @adapter: board private structure
2022 **/
021230d4 2023static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2024{
2025 int i;
2026
021230d4
AV		 2027 for (i = 0; i < adapter->num_tx_queues; i++)
2028 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2029}
2030
2031void ixgbe_down(struct ixgbe_adapter *adapter)
2032{
2033 struct net_device *netdev = adapter->netdev;
2034 u32 rxctrl;
2035
2036 /* signal that we are down to the interrupt handler */
2037 set_bit(__IXGBE_DOWN, &adapter->state);
2038
2039 /* disable receives */
2040 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
2041 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL,
2042 rxctrl & ~IXGBE_RXCTRL_RXEN);
2043
2044 netif_tx_disable(netdev);
2045
2046 /* disable transmits in the hardware */
2047
2048 /* flush both disables */
2049 IXGBE_WRITE_FLUSH(&adapter->hw);
2050 msleep(10);
2051
2052 ixgbe_irq_disable(adapter);
2053
021230d4 2054 ixgbe_napi_disable_all(adapter);
9a799d71
AK		 2055 del_timer_sync(&adapter->watchdog_timer);
2056
2057 netif_carrier_off(netdev);
fd2ea0a7 2058 netif_tx_stop_all_queues(netdev);
9a799d71 2059
96b0e0f6
JB		 2060#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
2061 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2062 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2063 dca_remove_requester(&adapter->pdev->dev);
2064 }
2065
2066#endif
6f4a0e45
PL		 2067 if (!pci_channel_offline(adapter->pdev))
2068 ixgbe_reset(adapter);
9a799d71
AK		 2069 ixgbe_clean_all_tx_rings(adapter);
2070 ixgbe_clean_all_rx_rings(adapter);
2071
96b0e0f6
JB		 2072#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
2073 /* since we reset the hardware DCA settings were cleared */
2074 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2075 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2076 /* always use CB2 mode, difference is masked
2077 * in the CB driver */
2078 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
2079 ixgbe_setup_dca(adapter);
2080 }
2081#endif
9a799d71
AK		 2082}
2083
2084static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
2085{
2086 struct net_device *netdev = pci_get_drvdata(pdev);
2087 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2088#ifdef CONFIG_PM
2089 int retval = 0;
2090#endif
2091
2092 netif_device_detach(netdev);
2093
2094 if (netif_running(netdev)) {
2095 ixgbe_down(adapter);
2096 ixgbe_free_irq(adapter);
2097 }
2098
2099#ifdef CONFIG_PM
2100 retval = pci_save_state(pdev);
2101 if (retval)
2102 return retval;
2103#endif
2104
2105 pci_enable_wake(pdev, PCI_D3hot, 0);
2106 pci_enable_wake(pdev, PCI_D3cold, 0);
2107
5eba3699
AV		 2108 ixgbe_release_hw_control(adapter);
2109
9a799d71
AK		 2110 pci_disable_device(pdev);
2111
2112 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2113
2114 return 0;
2115}
2116
2117static void ixgbe_shutdown(struct pci_dev *pdev)
2118{
2119 ixgbe_suspend(pdev, PMSG_SUSPEND);
2120}
2121
2122/**
021230d4
AV		 2123 * ixgbe_poll - NAPI Rx polling callback
2124 * @napi: structure for representing this polling device
2125 * @budget: how many packets driver is allowed to clean
2126 *
2127 * This function is used for legacy and MSI, NAPI mode
9a799d71 2128 **/
021230d4 2129static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2130{
021230d4
AV		 2131 struct ixgbe_q_vector *q_vector = container_of(napi,
2132 struct ixgbe_q_vector, napi);
2133 struct ixgbe_adapter *adapter = q_vector->adapter;
d2c7ddd6 2134 int tx_cleaned = 0, work_done = 0;
9a799d71 2135
96b0e0f6 2136#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 2137 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2138 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2139 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2140 }
2141#endif
2142
d2c7ddd6 2143 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 2144 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 2145
d2c7ddd6
DM		 2146 if (tx_cleaned)
2147 work_done = budget;
2148
53e52c72
DM		 2149 /* If budget not fully consumed, exit the polling mode */
2150 if (work_done < budget) {
021230d4 2151 netif_rx_complete(adapter->netdev, napi);
f494e8fa
AV		 2152 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
2153 ixgbe_set_itr(adapter);
d4f80882
AV		 2154 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2155 ixgbe_irq_enable(adapter);
9a799d71
AK		 2156 }
2157
2158 return work_done;
2159}
2160
2161/**
2162 * ixgbe_tx_timeout - Respond to a Tx Hang
2163 * @netdev: network interface device structure
2164 **/
2165static void ixgbe_tx_timeout(struct net_device *netdev)
2166{
2167 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2168
2169 /* Do the reset outside of interrupt context */
2170 schedule_work(&adapter->reset_task);
2171}
2172
2173static void ixgbe_reset_task(struct work_struct *work)
2174{
2175 struct ixgbe_adapter *adapter;
2176 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2177
2178 adapter->tx_timeout_count++;
2179
d4f80882 2180 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2181}
2182
021230d4
AV		 2183static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2184 int vectors)
2185{
2186 int err, vector_threshold;
2187
2188 /* We'll want at least 3 (vector_threshold):
2189 * 1) TxQ[0] Cleanup
2190 * 2) RxQ[0] Cleanup
2191 * 3) Other (Link Status Change, etc.)
2192 * 4) TCP Timer (optional)
2193 */
2194 vector_threshold = MIN_MSIX_COUNT;
2195
2196 /* The more we get, the more we will assign to Tx/Rx Cleanup
2197 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2198 * Right now, we simply care about how many we'll get; we'll
2199 * set them up later while requesting irq's.
2200 */
2201 while (vectors >= vector_threshold) {
2202 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2203 vectors);
2204 if (!err) /* Success in acquiring all requested vectors. */
2205 break;
2206 else if (err < 0)
2207 vectors = 0; /* Nasty failure, quit now */
2208 else /* err == number of vectors we should try again with */
2209 vectors = err;
2210 }
2211
2212 if (vectors < vector_threshold) {
2213 /* Can't allocate enough MSI-X interrupts? Oh well.
2214 * This just means we'll go with either a single MSI
2215 * vector or fall back to legacy interrupts.
2216 */
2217 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2218 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2219 kfree(adapter->msix_entries);
2220 adapter->msix_entries = NULL;
2221 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2222 adapter->num_tx_queues = 1;
2223 adapter->num_rx_queues = 1;
2224 } else {
2225 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2226 adapter->num_msix_vectors = vectors;
2227 }
2228}
2229
2230static void __devinit ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2231{
2232 int nrq, ntq;
2233 int feature_mask = 0, rss_i, rss_m;
2234
2235 /* Number of supported queues */
2236 switch (adapter->hw.mac.type) {
2237 case ixgbe_mac_82598EB:
2238 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2239 rss_m = 0;
2240 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2241
2242 switch (adapter->flags & feature_mask) {
2243 case (IXGBE_FLAG_RSS_ENABLED):
2244 rss_m = 0xF;
2245 nrq = rss_i;
30eba97a 2246 ntq = rss_i;
021230d4
AV		 2247 break;
2248 case 0:
2249 default:
2250 rss_i = 0;
2251 rss_m = 0;
2252 nrq = 1;
2253 ntq = 1;
2254 break;
2255 }
2256
2257 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2258 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2259 break;
2260 default:
2261 nrq = 1;
2262 ntq = 1;
2263 break;
2264 }
2265
2266 adapter->num_rx_queues = nrq;
2267 adapter->num_tx_queues = ntq;
2268}
2269
2270/**
2271 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2272 * @adapter: board private structure to initialize
2273 *
2274 * Once we know the feature-set enabled for the device, we'll cache
2275 * the register offset the descriptor ring is assigned to.
2276 **/
2277static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2278{
2279 /* TODO: Remove all uses of the indices in the cases where multiple
2280 * features are OR'd together, if the feature set makes sense.
2281 */
2282 int feature_mask = 0, rss_i;
2283 int i, txr_idx, rxr_idx;
2284
2285 /* Number of supported queues */
2286 switch (adapter->hw.mac.type) {
2287 case ixgbe_mac_82598EB:
2288 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2289 txr_idx = 0;
2290 rxr_idx = 0;
2291 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2292 switch (adapter->flags & feature_mask) {
2293 case (IXGBE_FLAG_RSS_ENABLED):
2294 for (i = 0; i < adapter->num_rx_queues; i++)
2295 adapter->rx_ring[i].reg_idx = i;
2296 for (i = 0; i < adapter->num_tx_queues; i++)
2297 adapter->tx_ring[i].reg_idx = i;
2298 break;
2299 case 0:
2300 default:
2301 break;
2302 }
2303 break;
2304 default:
2305 break;
2306 }
2307}
2308
9a799d71
AK		 2309/**
2310 * ixgbe_alloc_queues - Allocate memory for all rings
2311 * @adapter: board private structure to initialize
2312 *
2313 * We allocate one ring per queue at run-time since we don't know the
2314 * number of queues at compile-time. The polling_netdev array is
2315 * intended for Multiqueue, but should work fine with a single queue.
2316 **/
2317static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2318{
2319 int i;
2320
2321 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2322 sizeof(struct ixgbe_ring), GFP_KERNEL);
2323 if (!adapter->tx_ring)
021230d4 2324 goto err_tx_ring_allocation;
9a799d71
AK		 2325
2326 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2327 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2328 if (!adapter->rx_ring)
2329 goto err_rx_ring_allocation;
9a799d71 2330
021230d4
AV		 2331 for (i = 0; i < adapter->num_tx_queues; i++) {
2332 adapter->tx_ring[i].count = IXGBE_DEFAULT_TXD;
2333 adapter->tx_ring[i].queue_index = i;
2334 }
9a799d71 2335 for (i = 0; i < adapter->num_rx_queues; i++) {
9a799d71 2336 adapter->rx_ring[i].count = IXGBE_DEFAULT_RXD;
021230d4
AV		 2337 adapter->rx_ring[i].queue_index = i;
2338 }
2339
2340 ixgbe_cache_ring_register(adapter);
2341
2342 return 0;
2343
2344err_rx_ring_allocation:
2345 kfree(adapter->tx_ring);
2346err_tx_ring_allocation:
2347 return -ENOMEM;
2348}
2349
2350/**
2351 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2352 * @adapter: board private structure to initialize
2353 *
2354 * Attempt to configure the interrupts using the best available
2355 * capabilities of the hardware and the kernel.
2356 **/
2357static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
2358 *adapter)
2359{
2360 int err = 0;
2361 int vector, v_budget;
2362
2363 /*
2364 * It's easy to be greedy for MSI-X vectors, but it really
2365 * doesn't do us much good if we have a lot more vectors
2366 * than CPU's. So let's be conservative and only ask for
2367 * (roughly) twice the number of vectors as there are CPU's.
2368 */
2369 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2370 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2371
2372 /*
2373 * At the same time, hardware can only support a maximum of
2374 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2375 * we can easily reach upwards of 64 Rx descriptor queues and
2376 * 32 Tx queues. Thus, we cap it off in those rare cases where
2377 * the cpu count also exceeds our vector limit.
2378 */
2379 v_budget = min(v_budget, MAX_MSIX_COUNT);
2380
2381 /* A failure in MSI-X entry allocation isn't fatal, but it does
2382 * mean we disable MSI-X capabilities of the adapter. */
2383 adapter->msix_entries = kcalloc(v_budget,
2384 sizeof(struct msix_entry), GFP_KERNEL);
2385 if (!adapter->msix_entries) {
2386 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2387 ixgbe_set_num_queues(adapter);
2388 kfree(adapter->tx_ring);
2389 kfree(adapter->rx_ring);
2390 err = ixgbe_alloc_queues(adapter);
2391 if (err) {
2392 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2393 "for queues\n");
2394 goto out;
2395 }
2396
2397 goto try_msi;
2398 }
2399
2400 for (vector = 0; vector < v_budget; vector++)
2401 adapter->msix_entries[vector].entry = vector;
2402
2403 ixgbe_acquire_msix_vectors(adapter, v_budget);
2404
2405 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2406 goto out;
2407
2408try_msi:
2409 err = pci_enable_msi(adapter->pdev);
2410 if (!err) {
2411 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2412 } else {
2413 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2414 "falling back to legacy. Error: %d\n", err);
2415 /* reset err */
2416 err = 0;
2417 }
2418
2419out:
30eba97a 2420 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2421 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2422
2423 return err;
2424}
2425
2426static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2427{
2428 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2429 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2430 pci_disable_msix(adapter->pdev);
2431 kfree(adapter->msix_entries);
2432 adapter->msix_entries = NULL;
2433 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2434 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2435 pci_disable_msi(adapter->pdev);
2436 }
2437 return;
2438}
2439
2440/**
2441 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2442 * @adapter: board private structure to initialize
2443 *
2444 * We determine which interrupt scheme to use based on...
2445 * - Kernel support (MSI, MSI-X)
2446 * - which can be user-defined (via MODULE_PARAM)
2447 * - Hardware queue count (num_*_queues)
2448 * - defined by miscellaneous hardware support/features (RSS, etc.)
2449 **/
2450static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2451{
2452 int err;
2453
2454 /* Number of supported queues */
2455 ixgbe_set_num_queues(adapter);
2456
2457 err = ixgbe_alloc_queues(adapter);
2458 if (err) {
2459 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2460 goto err_alloc_queues;
2461 }
2462
2463 err = ixgbe_set_interrupt_capability(adapter);
2464 if (err) {
2465 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2466 goto err_set_interrupt;
9a799d71
AK		 2467 }
2468
021230d4
AV		 2469 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2470 "Tx Queue count = %u\n",
2471 (adapter->num_rx_queues > 1) ? "Enabled" :
2472 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2473
2474 set_bit(__IXGBE_DOWN, &adapter->state);
2475
9a799d71 2476 return 0;
021230d4
AV		 2477
2478err_set_interrupt:
2479 kfree(adapter->tx_ring);
2480 kfree(adapter->rx_ring);
2481err_alloc_queues:
2482 return err;
9a799d71
AK		 2483}
2484
2485/**
2486 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2487 * @adapter: board private structure to initialize
2488 *
2489 * ixgbe_sw_init initializes the Adapter private data structure.
2490 * Fields are initialized based on PCI device information and
2491 * OS network device settings (MTU size).
2492 **/
2493static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2494{
2495 struct ixgbe_hw *hw = &adapter->hw;
2496 struct pci_dev *pdev = adapter->pdev;
021230d4
AV		 2497 unsigned int rss;
2498
2499 /* Set capability flags */
2500 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2501 adapter->ring_feature[RING_F_RSS].indices = rss;
2502 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
9a799d71 2503
f494e8fa
AV		 2504 /* Enable Dynamic interrupt throttling by default */
2505 adapter->rx_eitr = 1;
2506 adapter->tx_eitr = 1;
2507
9a799d71 2508 /* default flow control settings */
2b9ade93
JB		 2509 hw->fc.original_type = ixgbe_fc_none;
2510 hw->fc.type = ixgbe_fc_none;
2511 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2512 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2513 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2514 hw->fc.send_xon = true;
9a799d71 2515
021230d4 2516 /* select 10G link by default */
9a799d71
AK		 2517 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2518 if (hw->mac.ops.reset(hw)) {
2519 dev_err(&pdev->dev, "HW Init failed\n");
2520 return -EIO;
2521 }
3957d63d
AK		 2522 if (hw->mac.ops.setup_link_speed(hw, IXGBE_LINK_SPEED_10GB_FULL, true,
2523 false)) {
9a799d71
AK		 2524 dev_err(&pdev->dev, "Link Speed setup failed\n");
2525 return -EIO;
2526 }
2527
2528 /* initialize eeprom parameters */
2529 if (ixgbe_init_eeprom(hw)) {
2530 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2531 return -EIO;
2532 }
2533
021230d4 2534 /* enable rx csum by default */
9a799d71
AK		 2535 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2536
9a799d71
AK		 2537 set_bit(__IXGBE_DOWN, &adapter->state);
2538
2539 return 0;
2540}
2541
2542/**
2543 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2544 * @adapter: board private structure
3a581073 2545 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2546 *
2547 * Return 0 on success, negative on failure
2548 **/
2549int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2550 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2551{
2552 struct pci_dev *pdev = adapter->pdev;
2553 int size;
2554
3a581073
JB		 2555 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2556 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 2557 if (!tx_ring->tx_buffer_info)
2558 goto err;
3a581073 2559 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 2560
2561 /* round up to nearest 4K */
e01c31a5
JB		 2562 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2563 sizeof(u32);
3a581073 2564 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 2565
3a581073
JB		 2566 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2567 &tx_ring->dma);
e01c31a5
JB		 2568 if (!tx_ring->desc)
2569 goto err;
9a799d71 2570
3a581073
JB		 2571 tx_ring->next_to_use = 0;
2572 tx_ring->next_to_clean = 0;
2573 tx_ring->work_limit = tx_ring->count;
9a799d71 2574 return 0;
e01c31a5
JB		 2575
2576err:
2577 vfree(tx_ring->tx_buffer_info);
2578 tx_ring->tx_buffer_info = NULL;
2579 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2580 "descriptor ring\n");
2581 return -ENOMEM;
9a799d71
AK		 2582}
2583
2584/**
2585 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2586 * @adapter: board private structure
3a581073 2587 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2588 *
2589 * Returns 0 on success, negative on failure
2590 **/
2591int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3a581073 2592 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2593{
2594 struct pci_dev *pdev = adapter->pdev;
021230d4 2595 int size;
9a799d71 2596
177db6ff 2597 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
3a581073
JB		 2598 rx_ring->lro_mgr.lro_arr = vmalloc(size);
2599 if (!rx_ring->lro_mgr.lro_arr)
177db6ff 2600 return -ENOMEM;
3a581073 2601 memset(rx_ring->lro_mgr.lro_arr, 0, size);
177db6ff 2602
3a581073
JB		 2603 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2604 rx_ring->rx_buffer_info = vmalloc(size);
2605 if (!rx_ring->rx_buffer_info) {
9a799d71
AK		 2606 DPRINTK(PROBE, ERR,
2607 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2608 goto alloc_failed;
9a799d71 2609 }
3a581073 2610 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 2611
9a799d71 2612 /* Round up to nearest 4K */
3a581073
JB		 2613 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2614 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 2615
3a581073 2616 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 2617
3a581073 2618 if (!rx_ring->desc) {
9a799d71
AK		 2619 DPRINTK(PROBE, ERR,
2620 "Memory allocation failed for the rx desc ring\n");
3a581073 2621 vfree(rx_ring->rx_buffer_info);
177db6ff 2622 goto alloc_failed;
9a799d71
AK		 2623 }
2624
3a581073
JB		 2625 rx_ring->next_to_clean = 0;
2626 rx_ring->next_to_use = 0;
9a799d71
AK		 2627
2628 return 0;
177db6ff
MC		 2629
2630alloc_failed:
3a581073
JB		 2631 vfree(rx_ring->lro_mgr.lro_arr);
2632 rx_ring->lro_mgr.lro_arr = NULL;
177db6ff 2633 return -ENOMEM;
9a799d71
AK		 2634}
2635
2636/**
2637 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2638 * @adapter: board private structure
2639 * @tx_ring: Tx descriptor ring for a specific queue
2640 *
2641 * Free all transmit software resources
2642 **/
2643static void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2644 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2645{
2646 struct pci_dev *pdev = adapter->pdev;
2647
2648 ixgbe_clean_tx_ring(adapter, tx_ring);
2649
2650 vfree(tx_ring->tx_buffer_info);
2651 tx_ring->tx_buffer_info = NULL;
2652
2653 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2654
2655 tx_ring->desc = NULL;
2656}
2657
2658/**
2659 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2660 * @adapter: board private structure
2661 *
2662 * Free all transmit software resources
2663 **/
2664static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2665{
2666 int i;
2667
2668 for (i = 0; i < adapter->num_tx_queues; i++)
2669 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2670}
2671
2672/**
2673 * ixgbe_free_rx_resources - Free Rx Resources
2674 * @adapter: board private structure
2675 * @rx_ring: ring to clean the resources from
2676 *
2677 * Free all receive software resources
2678 **/
2679static void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2680 struct ixgbe_ring *rx_ring)
2681{
2682 struct pci_dev *pdev = adapter->pdev;
2683
177db6ff
MC		 2684 vfree(rx_ring->lro_mgr.lro_arr);
2685 rx_ring->lro_mgr.lro_arr = NULL;
2686
9a799d71
AK		 2687 ixgbe_clean_rx_ring(adapter, rx_ring);
2688
2689 vfree(rx_ring->rx_buffer_info);
2690 rx_ring->rx_buffer_info = NULL;
2691
2692 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2693
2694 rx_ring->desc = NULL;
2695}
2696
2697/**
2698 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2699 * @adapter: board private structure
2700 *
2701 * Free all receive software resources
2702 **/
2703static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2704{
2705 int i;
2706
2707 for (i = 0; i < adapter->num_rx_queues; i++)
2708 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2709}
2710
2711/**
021230d4 2712 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
9a799d71
AK		 2713 * @adapter: board private structure
2714 *
2715 * If this function returns with an error, then it's possible one or
2716 * more of the rings is populated (while the rest are not). It is the
2717 * callers duty to clean those orphaned rings.
2718 *
2719 * Return 0 on success, negative on failure
2720 **/
2721static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2722{
2723 int i, err = 0;
2724
2725 for (i = 0; i < adapter->num_tx_queues; i++) {
2726 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2727 if (err) {
2728 DPRINTK(PROBE, ERR,
2729 "Allocation for Tx Queue %u failed\n", i);
2730 break;
2731 }
2732 }
2733
2734 return err;
2735}
2736
2737/**
021230d4 2738 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
9a799d71
AK		 2739 * @adapter: board private structure
2740 *
2741 * If this function returns with an error, then it's possible one or
2742 * more of the rings is populated (while the rest are not). It is the
2743 * callers duty to clean those orphaned rings.
2744 *
2745 * Return 0 on success, negative on failure
2746 **/
2747
2748static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2749{
2750 int i, err = 0;
2751
2752 for (i = 0; i < adapter->num_rx_queues; i++) {
2753 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2754 if (err) {
2755 DPRINTK(PROBE, ERR,
2756 "Allocation for Rx Queue %u failed\n", i);
2757 break;
2758 }
2759 }
2760
2761 return err;
2762}
2763
2764/**
2765 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2766 * @netdev: network interface device structure
2767 * @new_mtu: new value for maximum frame size
2768 *
2769 * Returns 0 on success, negative on failure
2770 **/
2771static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2772{
2773 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2774 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2775
2776 if ((max_frame < (ETH_ZLEN + ETH_FCS_LEN)) ||
2777 (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
2778 return -EINVAL;
2779
021230d4
AV		 2780 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
2781 netdev->mtu, new_mtu);
2782 /* must set new MTU before calling down or up */
9a799d71
AK		 2783 netdev->mtu = new_mtu;
2784
d4f80882
AV		 2785 if (netif_running(netdev))
2786 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2787
2788 return 0;
2789}
2790
2791/**
2792 * ixgbe_open - Called when a network interface is made active
2793 * @netdev: network interface device structure
2794 *
2795 * Returns 0 on success, negative value on failure
2796 *
2797 * The open entry point is called when a network interface is made
2798 * active by the system (IFF_UP). At this point all resources needed
2799 * for transmit and receive operations are allocated, the interrupt
2800 * handler is registered with the OS, the watchdog timer is started,
2801 * and the stack is notified that the interface is ready.
2802 **/
2803static int ixgbe_open(struct net_device *netdev)
2804{
2805 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2806 int err;
4bebfaa5
AK		 2807
2808 /* disallow open during test */
2809 if (test_bit(__IXGBE_TESTING, &adapter->state))
2810 return -EBUSY;
9a799d71 2811
9a799d71
AK		 2812 /* allocate transmit descriptors */
2813 err = ixgbe_setup_all_tx_resources(adapter);
2814 if (err)
2815 goto err_setup_tx;
2816
9a799d71
AK		 2817 /* allocate receive descriptors */
2818 err = ixgbe_setup_all_rx_resources(adapter);
2819 if (err)
2820 goto err_setup_rx;
2821
2822 ixgbe_configure(adapter);
2823
021230d4 2824 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2825 if (err)
2826 goto err_req_irq;
2827
9a799d71
AK		 2828 err = ixgbe_up_complete(adapter);
2829 if (err)
2830 goto err_up;
2831
d55b53ff
JK		 2832 netif_tx_start_all_queues(netdev);
2833
9a799d71
AK		 2834 return 0;
2835
2836err_up:
5eba3699 2837 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2838 ixgbe_free_irq(adapter);
2839err_req_irq:
2840 ixgbe_free_all_rx_resources(adapter);
2841err_setup_rx:
2842 ixgbe_free_all_tx_resources(adapter);
2843err_setup_tx:
2844 ixgbe_reset(adapter);
2845
2846 return err;
2847}
2848
2849/**
2850 * ixgbe_close - Disables a network interface
2851 * @netdev: network interface device structure
2852 *
2853 * Returns 0, this is not allowed to fail
2854 *
2855 * The close entry point is called when an interface is de-activated
2856 * by the OS. The hardware is still under the drivers control, but
2857 * needs to be disabled. A global MAC reset is issued to stop the
2858 * hardware, and all transmit and receive resources are freed.
2859 **/
2860static int ixgbe_close(struct net_device *netdev)
2861{
2862 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 2863
2864 ixgbe_down(adapter);
2865 ixgbe_free_irq(adapter);
2866
2867 ixgbe_free_all_tx_resources(adapter);
2868 ixgbe_free_all_rx_resources(adapter);
2869
5eba3699 2870 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2871
2872 return 0;
2873}
2874
2875/**
2876 * ixgbe_update_stats - Update the board statistics counters.
2877 * @adapter: board private structure
2878 **/
2879void ixgbe_update_stats(struct ixgbe_adapter *adapter)
2880{
2881 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 2882 u64 total_mpc = 0;
2883 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 2884
2885 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 2886 for (i = 0; i < 8; i++) {
2887 /* for packet buffers not used, the register should read 0 */
2888 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2889 missed_rx += mpc;
2890 adapter->stats.mpc[i] += mpc;
2891 total_mpc += adapter->stats.mpc[i];
2892 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2893 }
2894 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2895 /* work around hardware counting issue */
2896 adapter->stats.gprc -= missed_rx;
2897
2898 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 2899 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 2900 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2901 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 2902 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2903 adapter->stats.bprc += bprc;
2904 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2905 adapter->stats.mprc -= bprc;
2906 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2907 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2908 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2909 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2910 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2911 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2912 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 2913 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2914 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 2915 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 2916 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2917 adapter->stats.lxontxc += lxon;
2918 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2919 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 2920 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2921 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 2922 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2923 /*
2924 * 82598 errata - tx of flow control packets is included in tx counters
2925 */
2926 xon_off_tot = lxon + lxoff;
2927 adapter->stats.gptc -= xon_off_tot;
2928 adapter->stats.mptc -= xon_off_tot;
2929 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 2930 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2931 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2932 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 2933 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2934 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 2935 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 2936 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2937 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2938 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2939 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2940 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 2941 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2942
2943 /* Fill out the OS statistics structure */
9a799d71
AK		 2944 adapter->net_stats.multicast = adapter->stats.mprc;
2945
2946 /* Rx Errors */
2947 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
2948 adapter->stats.rlec;
2949 adapter->net_stats.rx_dropped = 0;
2950 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2951 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 2952 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 2953}
2954
2955/**
2956 * ixgbe_watchdog - Timer Call-back
2957 * @data: pointer to adapter cast into an unsigned long
2958 **/
2959static void ixgbe_watchdog(unsigned long data)
2960{
2961 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2962 struct net_device *netdev = adapter->netdev;
2963 bool link_up;
2964 u32 link_speed = 0;
2965
3957d63d 2966 adapter->hw.mac.ops.check_link(&adapter->hw, &(link_speed), &link_up);
9a799d71
AK		 2967
2968 if (link_up) {
2969 if (!netif_carrier_ok(netdev)) {
2970 u32 frctl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2971 u32 rmcs = IXGBE_READ_REG(&adapter->hw, IXGBE_RMCS);
2972#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
2973#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
2974 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
2975 "Flow Control: %s\n",
2976 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
2977 "10 Gbps" :
2978 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5a059e9d 2979 "1 Gbps" : "unknown speed")),
9a799d71
AK		 2980 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
2981 (FLOW_RX ? "RX" :
2982 (FLOW_TX ? "TX" : "None"))));
2983
2984 netif_carrier_on(netdev);
fd2ea0a7 2985 netif_tx_wake_all_queues(netdev);
9a799d71
AK		 2986 } else {
2987 /* Force detection of hung controller */
2988 adapter->detect_tx_hung = true;
2989 }
2990 } else {
2991 if (netif_carrier_ok(netdev)) {
2992 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2993 netif_carrier_off(netdev);
fd2ea0a7 2994 netif_tx_stop_all_queues(netdev);
9a799d71
AK		 2995 }
2996 }
2997
2998 ixgbe_update_stats(adapter);
2999
021230d4
AV		 3000 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3001 /* Cause software interrupt to ensure rx rings are cleaned */
3002 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3003 u32 eics =
3004 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, eics);
3006 } else {
3007 /* for legacy and MSI interrupts don't set any bits that
3008 * are enabled for EIAM, because this operation would
3009 * set *both* EIMS and EICS for any bit in EIAM */
3010 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
3011 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3012 }
3013 /* Reset the timer */
9a799d71
AK		 3014 mod_timer(&adapter->watchdog_timer,
3015 round_jiffies(jiffies + 2 * HZ));
021230d4 3016 }
9a799d71
AK		 3017}
3018
9a799d71
AK		 3019static int ixgbe_tso(struct ixgbe_adapter *adapter,
3020 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3021 u32 tx_flags, u8 *hdr_len)
3022{
3023 struct ixgbe_adv_tx_context_desc *context_desc;
3024 unsigned int i;
3025 int err;
3026 struct ixgbe_tx_buffer *tx_buffer_info;
3027 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3028 u32 mss_l4len_idx = 0, l4len;
9a799d71
AK		 3029
3030 if (skb_is_gso(skb)) {
3031 if (skb_header_cloned(skb)) {
3032 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3033 if (err)
3034 return err;
3035 }
3036 l4len = tcp_hdrlen(skb);
3037 *hdr_len += l4len;
3038
8327d000 3039 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3040 struct iphdr *iph = ip_hdr(skb);
3041 iph->tot_len = 0;
3042 iph->check = 0;
3043 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3044 iph->daddr, 0,
3045 IPPROTO_TCP,
3046 0);
3047 adapter->hw_tso_ctxt++;
3048 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3049 ipv6_hdr(skb)->payload_len = 0;
3050 tcp_hdr(skb)->check =
3051 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3052 &ipv6_hdr(skb)->daddr,
3053 0, IPPROTO_TCP, 0);
3054 adapter->hw_tso6_ctxt++;
3055 }
3056
3057 i = tx_ring->next_to_use;
3058
3059 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3060 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3061
3062 /* VLAN MACLEN IPLEN */
3063 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3064 vlan_macip_lens |=
3065 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3066 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3067 IXGBE_ADVTXD_MACLEN_SHIFT);
3068 *hdr_len += skb_network_offset(skb);
3069 vlan_macip_lens |=
3070 (skb_transport_header(skb) - skb_network_header(skb));
3071 *hdr_len +=
3072 (skb_transport_header(skb) - skb_network_header(skb));
3073 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3074 context_desc->seqnum_seed = 0;
3075
3076 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3077 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3078 IXGBE_ADVTXD_DTYP_CTXT);
3079
8327d000 3080 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3081 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3082 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3083 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3084
3085 /* MSS L4LEN IDX */
3086 mss_l4len_idx |=
3087 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3088 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3089 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3090
3091 tx_buffer_info->time_stamp = jiffies;
3092 tx_buffer_info->next_to_watch = i;
3093
3094 i++;
3095 if (i == tx_ring->count)
3096 i = 0;
3097 tx_ring->next_to_use = i;
3098
3099 return true;
3100 }
3101 return false;
3102}
3103
3104static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3105 struct ixgbe_ring *tx_ring,
3106 struct sk_buff *skb, u32 tx_flags)
3107{
3108 struct ixgbe_adv_tx_context_desc *context_desc;
3109 unsigned int i;
3110 struct ixgbe_tx_buffer *tx_buffer_info;
3111 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3112
3113 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3114 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3115 i = tx_ring->next_to_use;
3116 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3117 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3118
3119 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3120 vlan_macip_lens |=
3121 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3122 vlan_macip_lens |= (skb_network_offset(skb) <<
3123 IXGBE_ADVTXD_MACLEN_SHIFT);
3124 if (skb->ip_summed == CHECKSUM_PARTIAL)
3125 vlan_macip_lens |= (skb_transport_header(skb) -
3126 skb_network_header(skb));
3127
3128 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3129 context_desc->seqnum_seed = 0;
3130
3131 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3132 IXGBE_ADVTXD_DTYP_CTXT);
3133
3134 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 3135 switch (skb->protocol) {
3136 case __constant_htons(ETH_P_IP):
9a799d71 3137 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3138 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3139 type_tucmd_mlhl |=
3140 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3141 break;
3142
3143 case __constant_htons(ETH_P_IPV6):
3144 /* XXX what about other V6 headers?? */
3145 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3146 type_tucmd_mlhl |=
3147 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3148 break;
9a799d71 3149
41825d71
AK		 3150 default:
3151 if (unlikely(net_ratelimit())) {
3152 DPRINTK(PROBE, WARNING,
3153 "partial checksum but proto=%x!\n",
3154 skb->protocol);
3155 }
3156 break;
3157 }
9a799d71
AK		 3158 }
3159
3160 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3161 context_desc->mss_l4len_idx = 0;
3162
3163 tx_buffer_info->time_stamp = jiffies;
3164 tx_buffer_info->next_to_watch = i;
3165 adapter->hw_csum_tx_good++;
3166 i++;
3167 if (i == tx_ring->count)
3168 i = 0;
3169 tx_ring->next_to_use = i;
3170
3171 return true;
3172 }
3173 return false;
3174}
3175
3176static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3177 struct ixgbe_ring *tx_ring,
3178 struct sk_buff *skb, unsigned int first)
3179{
3180 struct ixgbe_tx_buffer *tx_buffer_info;
3181 unsigned int len = skb->len;
3182 unsigned int offset = 0, size, count = 0, i;
3183 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3184 unsigned int f;
3185
3186 len -= skb->data_len;
3187
3188 i = tx_ring->next_to_use;
3189
3190 while (len) {
3191 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3192 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3193
3194 tx_buffer_info->length = size;
3195 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3196 skb->data + offset,
3197 size, PCI_DMA_TODEVICE);
3198 tx_buffer_info->time_stamp = jiffies;
3199 tx_buffer_info->next_to_watch = i;
3200
3201 len -= size;
3202 offset += size;
3203 count++;
3204 i++;
3205 if (i == tx_ring->count)
3206 i = 0;
3207 }
3208
3209 for (f = 0; f < nr_frags; f++) {
3210 struct skb_frag_struct *frag;
3211
3212 frag = &skb_shinfo(skb)->frags[f];
3213 len = frag->size;
3214 offset = frag->page_offset;
3215
3216 while (len) {
3217 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3218 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3219
3220 tx_buffer_info->length = size;
3221 tx_buffer_info->dma = pci_map_page(adapter->pdev,
3222 frag->page,
3223 offset,
3224 size, PCI_DMA_TODEVICE);
3225 tx_buffer_info->time_stamp = jiffies;
3226 tx_buffer_info->next_to_watch = i;
3227
3228 len -= size;
3229 offset += size;
3230 count++;
3231 i++;
3232 if (i == tx_ring->count)
3233 i = 0;
3234 }
3235 }
3236 if (i == 0)
3237 i = tx_ring->count - 1;
3238 else
3239 i = i - 1;
3240 tx_ring->tx_buffer_info[i].skb = skb;
3241 tx_ring->tx_buffer_info[first].next_to_watch = i;
3242
3243 return count;
3244}
3245
3246static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3247 struct ixgbe_ring *tx_ring,
3248 int tx_flags, int count, u32 paylen, u8 hdr_len)
3249{
3250 union ixgbe_adv_tx_desc *tx_desc = NULL;
3251 struct ixgbe_tx_buffer *tx_buffer_info;
3252 u32 olinfo_status = 0, cmd_type_len = 0;
3253 unsigned int i;
3254 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3255
3256 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3257
3258 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3259
3260 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3261 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3262
3263 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3264 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3265
3266 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3267 IXGBE_ADVTXD_POPTS_SHIFT;
3268
3269 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3270 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3271 IXGBE_ADVTXD_POPTS_SHIFT;
3272
3273 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3274 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3275 IXGBE_ADVTXD_POPTS_SHIFT;
3276
3277 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3278
3279 i = tx_ring->next_to_use;
3280 while (count--) {
3281 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3282 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3283 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3284 tx_desc->read.cmd_type_len =
3285 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3286 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3287
3288 i++;
3289 if (i == tx_ring->count)
3290 i = 0;
3291 }
3292
3293 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3294
3295 /*
3296 * Force memory writes to complete before letting h/w
3297 * know there are new descriptors to fetch. (Only
3298 * applicable for weak-ordered memory model archs,
3299 * such as IA-64).
3300 */
3301 wmb();
3302
3303 tx_ring->next_to_use = i;
3304 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3305}
3306
e092be60
AV		 3307static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3308 struct ixgbe_ring *tx_ring, int size)
3309{
3310 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3311
30eba97a 3312 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3313 /* Herbert's original patch had:
3314 * smp_mb__after_netif_stop_queue();
3315 * but since that doesn't exist yet, just open code it. */
3316 smp_mb();
3317
3318 /* We need to check again in a case another CPU has just
3319 * made room available. */
3320 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3321 return -EBUSY;
3322
3323 /* A reprieve! - use start_queue because it doesn't call schedule */
30eba97a 3324 netif_wake_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3325 ++adapter->restart_queue;
3326 return 0;
3327}
3328
3329static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3330 struct ixgbe_ring *tx_ring, int size)
3331{
3332 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3333 return 0;
3334 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3335}
3336
3337
9a799d71
AK		 3338static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3339{
3340 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3341 struct ixgbe_ring *tx_ring;
3342 unsigned int len = skb->len;
3343 unsigned int first;
3344 unsigned int tx_flags = 0;
30eba97a
AV		 3345 u8 hdr_len = 0;
3346 int r_idx = 0, tso;
9a799d71
AK		 3347 unsigned int mss = 0;
3348 int count = 0;
3349 unsigned int f;
3350 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3351 len -= skb->data_len;
30eba97a 3352 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3353 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3354
9a799d71
AK		 3355
3356 if (skb->len <= 0) {
3357 dev_kfree_skb(skb);
3358 return NETDEV_TX_OK;
3359 }
3360 mss = skb_shinfo(skb)->gso_size;
3361
3362 if (mss)
3363 count++;
3364 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3365 count++;
3366
3367 count += TXD_USE_COUNT(len);
3368 for (f = 0; f < nr_frags; f++)
3369 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3370
e092be60 3371 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3372 adapter->tx_busy++;
9a799d71
AK		 3373 return NETDEV_TX_BUSY;
3374 }
9a799d71
AK		 3375 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3376 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3377 tx_flags |= (vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT);
3378 }
3379
8327d000 3380 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3381 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3382 first = tx_ring->next_to_use;
3383 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3384 if (tso < 0) {
3385 dev_kfree_skb_any(skb);
3386 return NETDEV_TX_OK;
3387 }
3388
3389 if (tso)
3390 tx_flags |= IXGBE_TX_FLAGS_TSO;
3391 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3392 (skb->ip_summed == CHECKSUM_PARTIAL))
3393 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3394
3395 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3396 ixgbe_tx_map(adapter, tx_ring, skb, first),
3397 skb->len, hdr_len);
3398
3399 netdev->trans_start = jiffies;
3400
e092be60 3401 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3402
3403 return NETDEV_TX_OK;
3404}
3405
3406/**
3407 * ixgbe_get_stats - Get System Network Statistics
3408 * @netdev: network interface device structure
3409 *
3410 * Returns the address of the device statistics structure.
3411 * The statistics are actually updated from the timer callback.
3412 **/
3413static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3414{
3415 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3416
3417 /* only return the current stats */
3418 return &adapter->net_stats;
3419}
3420
3421/**
3422 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3423 * @netdev: network interface device structure
3424 * @p: pointer to an address structure
3425 *
3426 * Returns 0 on success, negative on failure
3427 **/
3428static int ixgbe_set_mac(struct net_device *netdev, void *p)
3429{
3430 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3431 struct sockaddr *addr = p;
3432
3433 if (!is_valid_ether_addr(addr->sa_data))
3434 return -EADDRNOTAVAIL;
3435
3436 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3437 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3438
3439 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
3440
3441 return 0;
3442}
3443
3444#ifdef CONFIG_NET_POLL_CONTROLLER
3445/*
3446 * Polling 'interrupt' - used by things like netconsole to send skbs
3447 * without having to re-enable interrupts. It's not called while
3448 * the interrupt routine is executing.
3449 */
3450static void ixgbe_netpoll(struct net_device *netdev)
3451{
3452 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3453
3454 disable_irq(adapter->pdev->irq);
3455 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3456 ixgbe_intr(adapter->pdev->irq, netdev);
3457 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3458 enable_irq(adapter->pdev->irq);
3459}
3460#endif
3461
021230d4
AV		 3462/**
3463 * ixgbe_napi_add_all - prep napi structs for use
3464 * @adapter: private struct
3465 * helper function to napi_add each possible q_vector->napi
3466 */
3467static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3468{
3469 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3470 int (*poll)(struct napi_struct *, int);
3471
3472 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3473 poll = &ixgbe_clean_rxonly;
3474 } else {
3475 poll = &ixgbe_poll;
3476 /* only one q_vector for legacy modes */
3477 q_vectors = 1;
3478 }
3479
3480 for (i = 0; i < q_vectors; i++) {
3481 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
3482 netif_napi_add(adapter->netdev, &q_vector->napi,
3483 (*poll), 64);
3484 }
3485}
3486
9a799d71
AK		 3487/**
3488 * ixgbe_probe - Device Initialization Routine
3489 * @pdev: PCI device information struct
3490 * @ent: entry in ixgbe_pci_tbl
3491 *
3492 * Returns 0 on success, negative on failure
3493 *
3494 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3495 * The OS initialization, configuring of the adapter private structure,
3496 * and a hardware reset occur.
3497 **/
3498static int __devinit ixgbe_probe(struct pci_dev *pdev,
3499 const struct pci_device_id *ent)
3500{
3501 struct net_device *netdev;
3502 struct ixgbe_adapter *adapter = NULL;
3503 struct ixgbe_hw *hw;
3504 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3505 unsigned long mmio_start, mmio_len;
3506 static int cards_found;
3507 int i, err, pci_using_dac;
3508 u16 link_status, link_speed, link_width;
3509 u32 part_num;
3510
3511 err = pci_enable_device(pdev);
3512 if (err)
3513 return err;
3514
3515 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3516 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3517 pci_using_dac = 1;
3518 } else {
3519 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3520 if (err) {
3521 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3522 if (err) {
3523 dev_err(&pdev->dev, "No usable DMA "
3524 "configuration, aborting\n");
3525 goto err_dma;
3526 }
3527 }
3528 pci_using_dac = 0;
3529 }
3530
3531 err = pci_request_regions(pdev, ixgbe_driver_name);
3532 if (err) {
3533 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3534 goto err_pci_reg;
3535 }
3536
3537 pci_set_master(pdev);
fb3b27bc 3538 pci_save_state(pdev);
9a799d71 3539
30eba97a 3540 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 3541 if (!netdev) {
3542 err = -ENOMEM;
3543 goto err_alloc_etherdev;
3544 }
3545
9a799d71
AK		 3546 SET_NETDEV_DEV(netdev, &pdev->dev);
3547
3548 pci_set_drvdata(pdev, netdev);
3549 adapter = netdev_priv(netdev);
3550
3551 adapter->netdev = netdev;
3552 adapter->pdev = pdev;
3553 hw = &adapter->hw;
3554 hw->back = adapter;
3555 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3556
3557 mmio_start = pci_resource_start(pdev, 0);
3558 mmio_len = pci_resource_len(pdev, 0);
3559
3560 hw->hw_addr = ioremap(mmio_start, mmio_len);
3561 if (!hw->hw_addr) {
3562 err = -EIO;
3563 goto err_ioremap;
3564 }
3565
3566 for (i = 1; i <= 5; i++) {
3567 if (pci_resource_len(pdev, i) == 0)
3568 continue;
3569 }
3570
3571 netdev->open = &ixgbe_open;
3572 netdev->stop = &ixgbe_close;
3573 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3574 netdev->get_stats = &ixgbe_get_stats;
2c5645cf
CL		 3575 netdev->set_rx_mode = &ixgbe_set_rx_mode;
3576 netdev->set_multicast_list = &ixgbe_set_rx_mode;
9a799d71
AK		 3577 netdev->set_mac_address = &ixgbe_set_mac;
3578 netdev->change_mtu = &ixgbe_change_mtu;
3579 ixgbe_set_ethtool_ops(netdev);
3580 netdev->tx_timeout = &ixgbe_tx_timeout;
3581 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3582 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3583 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3584 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3585#ifdef CONFIG_NET_POLL_CONTROLLER
3586 netdev->poll_controller = ixgbe_netpoll;
3587#endif
3588 strcpy(netdev->name, pci_name(pdev));
3589
3590 netdev->mem_start = mmio_start;
3591 netdev->mem_end = mmio_start + mmio_len;
3592
3593 adapter->bd_number = cards_found;
3594
3595 /* PCI config space info */
3596 hw->vendor_id = pdev->vendor;
3597 hw->device_id = pdev->device;
3598 hw->revision_id = pdev->revision;
3599 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3600 hw->subsystem_device_id = pdev->subsystem_device;
3601
3602 /* Setup hw api */
3603 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3604 hw->mac.type = ii->mac;
9a799d71
AK		 3605
3606 err = ii->get_invariants(hw);
3607 if (err)
3608 goto err_hw_init;
3609
3610 /* setup the private structure */
3611 err = ixgbe_sw_init(adapter);
3612 if (err)
3613 goto err_sw_init;
3614
3615 netdev->features = NETIF_F_SG |
22f32b7a 3616 NETIF_F_IP_CSUM |
9a799d71
AK		 3617 NETIF_F_HW_VLAN_TX |
3618 NETIF_F_HW_VLAN_RX |
3619 NETIF_F_HW_VLAN_FILTER;
3620
177db6ff 3621 netdev->features |= NETIF_F_LRO;
9a799d71 3622 netdev->features |= NETIF_F_TSO;
9a799d71 3623 netdev->features |= NETIF_F_TSO6;
ad31c402
JK		 3624
3625 netdev->vlan_features |= NETIF_F_TSO;
3626 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 3627 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 3628 netdev->vlan_features |= NETIF_F_SG;
3629
9a799d71
AK		 3630 if (pci_using_dac)
3631 netdev->features |= NETIF_F_HIGHDMA;
3632
9a799d71
AK		 3633 /* make sure the EEPROM is good */
3634 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
3635 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3636 err = -EIO;
3637 goto err_eeprom;
3638 }
3639
3640 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3641 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3642
3643 if (ixgbe_validate_mac_addr(netdev->dev_addr)) {
3644 err = -EIO;
3645 goto err_eeprom;
3646 }
3647
3648 init_timer(&adapter->watchdog_timer);
3649 adapter->watchdog_timer.function = &ixgbe_watchdog;
3650 adapter->watchdog_timer.data = (unsigned long)adapter;
3651
3652 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
3653
021230d4
AV		 3654 err = ixgbe_init_interrupt_scheme(adapter);
3655 if (err)
3656 goto err_sw_init;
9a799d71
AK		 3657
3658 /* print bus type/speed/width info */
3659 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3660 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3661 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3662 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
3663 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3664 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3665 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3666 "Unknown"),
3667 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3668 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3669 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3670 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3671 "Unknown"),
3672 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3673 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
3674 ixgbe_read_part_num(hw, &part_num);
3675 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
3676 hw->mac.type, hw->phy.type,
3677 (part_num >> 8), (part_num & 0xff));
3678
0c254d86
AK		 3679 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3680 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
3681 "this card is not sufficient for optimal "
3682 "performance.\n");
3683 dev_warn(&pdev->dev, "For optimal performance a x8 "
3684 "PCI-Express slot is required.\n");
3685 }
3686
9a799d71
AK		 3687 /* reset the hardware with the new settings */
3688 ixgbe_start_hw(hw);
3689
3690 netif_carrier_off(netdev);
fd2ea0a7 3691 netif_tx_stop_all_queues(netdev);
9a799d71 3692
021230d4
AV		 3693 ixgbe_napi_add_all(adapter);
3694
9a799d71
AK		 3695 strcpy(netdev->name, "eth%d");
3696 err = register_netdev(netdev);
3697 if (err)
3698 goto err_register;
3699
96b0e0f6 3700#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
652f093f 3701 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 3702 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3703 /* always use CB2 mode, difference is masked
3704 * in the CB driver */
3705 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3706 ixgbe_setup_dca(adapter);
3707 }
3708#endif
9a799d71
AK		 3709
3710 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3711 cards_found++;
3712 return 0;
3713
3714err_register:
5eba3699 3715 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3716err_hw_init:
3717err_sw_init:
021230d4 3718 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3719err_eeprom:
3720 iounmap(hw->hw_addr);
3721err_ioremap:
3722 free_netdev(netdev);
3723err_alloc_etherdev:
3724 pci_release_regions(pdev);
3725err_pci_reg:
3726err_dma:
3727 pci_disable_device(pdev);
3728 return err;
3729}
3730
3731/**
3732 * ixgbe_remove - Device Removal Routine
3733 * @pdev: PCI device information struct
3734 *
3735 * ixgbe_remove is called by the PCI subsystem to alert the driver
3736 * that it should release a PCI device. The could be caused by a
3737 * Hot-Plug event, or because the driver is going to be removed from
3738 * memory.
3739 **/
3740static void __devexit ixgbe_remove(struct pci_dev *pdev)
3741{
3742 struct net_device *netdev = pci_get_drvdata(pdev);
3743 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3744
3745 set_bit(__IXGBE_DOWN, &adapter->state);
3746 del_timer_sync(&adapter->watchdog_timer);
3747
3748 flush_scheduled_work();
3749
96b0e0f6 3750#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 3751 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3752 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
3753 dca_remove_requester(&pdev->dev);
3754 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
3755 }
3756
3757#endif
9a799d71
AK		 3758 unregister_netdev(netdev);
3759
021230d4 3760 ixgbe_reset_interrupt_capability(adapter);
5eba3699 3761
021230d4 3762 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3763
3764 iounmap(adapter->hw.hw_addr);
3765 pci_release_regions(pdev);
3766
021230d4
AV		 3767 DPRINTK(PROBE, INFO, "complete\n");
3768 kfree(adapter->tx_ring);
3769 kfree(adapter->rx_ring);
3770
9a799d71
AK		 3771 free_netdev(netdev);
3772
3773 pci_disable_device(pdev);
3774}
3775
3776/**
3777 * ixgbe_io_error_detected - called when PCI error is detected
3778 * @pdev: Pointer to PCI device
3779 * @state: The current pci connection state
3780 *
3781 * This function is called after a PCI bus error affecting
3782 * this device has been detected.
3783 */
3784static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
3785 pci_channel_state_t state)
3786{
3787 struct net_device *netdev = pci_get_drvdata(pdev);
3788 struct ixgbe_adapter *adapter = netdev->priv;
3789
3790 netif_device_detach(netdev);
3791
3792 if (netif_running(netdev))
3793 ixgbe_down(adapter);
3794 pci_disable_device(pdev);
3795
3796 /* Request a slot slot reset. */
3797 return PCI_ERS_RESULT_NEED_RESET;
3798}
3799
3800/**
3801 * ixgbe_io_slot_reset - called after the pci bus has been reset.
3802 * @pdev: Pointer to PCI device
3803 *
3804 * Restart the card from scratch, as if from a cold-boot.
3805 */
3806static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
3807{
3808 struct net_device *netdev = pci_get_drvdata(pdev);
3809 struct ixgbe_adapter *adapter = netdev->priv;
3810
3811 if (pci_enable_device(pdev)) {
3812 DPRINTK(PROBE, ERR,
3813 "Cannot re-enable PCI device after reset.\n");
3814 return PCI_ERS_RESULT_DISCONNECT;
3815 }
3816 pci_set_master(pdev);
fb3b27bc 3817 pci_restore_state(pdev);
9a799d71
AK		 3818
3819 pci_enable_wake(pdev, PCI_D3hot, 0);
3820 pci_enable_wake(pdev, PCI_D3cold, 0);
3821
3822 ixgbe_reset(adapter);
3823
3824 return PCI_ERS_RESULT_RECOVERED;
3825}
3826
3827/**
3828 * ixgbe_io_resume - called when traffic can start flowing again.
3829 * @pdev: Pointer to PCI device
3830 *
3831 * This callback is called when the error recovery driver tells us that
3832 * its OK to resume normal operation.
3833 */
3834static void ixgbe_io_resume(struct pci_dev *pdev)
3835{
3836 struct net_device *netdev = pci_get_drvdata(pdev);
3837 struct ixgbe_adapter *adapter = netdev->priv;
3838
3839 if (netif_running(netdev)) {
3840 if (ixgbe_up(adapter)) {
3841 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
3842 return;
3843 }
3844 }
3845
3846 netif_device_attach(netdev);
3847
3848}
3849
3850static struct pci_error_handlers ixgbe_err_handler = {
3851 .error_detected = ixgbe_io_error_detected,
3852 .slot_reset = ixgbe_io_slot_reset,
3853 .resume = ixgbe_io_resume,
3854};
3855
3856static struct pci_driver ixgbe_driver = {
3857 .name = ixgbe_driver_name,
3858 .id_table = ixgbe_pci_tbl,
3859 .probe = ixgbe_probe,
3860 .remove = __devexit_p(ixgbe_remove),
3861#ifdef CONFIG_PM
3862 .suspend = ixgbe_suspend,
3863 .resume = ixgbe_resume,
3864#endif
3865 .shutdown = ixgbe_shutdown,
3866 .err_handler = &ixgbe_err_handler
3867};
3868
3869/**
3870 * ixgbe_init_module - Driver Registration Routine
3871 *
3872 * ixgbe_init_module is the first routine called when the driver is
3873 * loaded. All it does is register with the PCI subsystem.
3874 **/
3875static int __init ixgbe_init_module(void)
3876{
3877 int ret;
3878 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
3879 ixgbe_driver_string, ixgbe_driver_version);
3880
3881 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
3882
96b0e0f6 3883#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 3884 dca_register_notify(&dca_notifier);
3885
3886#endif
9a799d71
AK		 3887 ret = pci_register_driver(&ixgbe_driver);
3888 return ret;
3889}
3890module_init(ixgbe_init_module);
3891
3892/**
3893 * ixgbe_exit_module - Driver Exit Cleanup Routine
3894 *
3895 * ixgbe_exit_module is called just before the driver is removed
3896 * from memory.
3897 **/
3898static void __exit ixgbe_exit_module(void)
3899{
96b0e0f6 3900#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 3901 dca_unregister_notify(&dca_notifier);
3902#endif
9a799d71
AK		 3903 pci_unregister_driver(&ixgbe_driver);
3904}
bd0362dd 3905
96b0e0f6 3906#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 3907static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
3908 void *p)
3909{
3910 int ret_val;
3911
3912 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
3913 __ixgbe_notify_dca);
3914
3915 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3916}
96b0e0f6 3917#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
bd0362dd 3918
9a799d71
AK		 3919module_exit(ixgbe_exit_module);
3920
3921/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)