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ixgbe: only enable WoL for magic packet by default
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
45#include <linux/if_vlan.h>
70c71606 46#include <linux/prefetch.h>
eacd73f7 47#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 48
49#include "ixgbe.h"
50#include "ixgbe_common.h"
ee5f784a 51#include "ixgbe_dcb_82599.h"
1cdd1ec8 52#include "ixgbe_sriov.h"
9a799d71
AK		 53
54char ixgbe_driver_name[] = "ixgbe";
9c8eb720 55static const char ixgbe_driver_string[] =
e8e9f696 56 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 57#define MAJ 3
a38a104d 58#define MIN 4
c89c7112 59#define BUILD 8
75e3d3c6 60#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 61 __stringify(BUILD) "-k"
9c8eb720 62const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 63static const char ixgbe_copyright[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 65
66static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 67 [board_82598] = &ixgbe_82598_info,
e8e26350 68 [board_82599] = &ixgbe_82599_info,
fe15e8e1 69 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 70};
71
72/* ixgbe_pci_tbl - PCI Device ID Table
73 *
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
76 *
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
79 */
a3aa1884 80static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 84 board_82598 },
9a799d71 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 86 board_82598 },
0befdb3e
JB		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
88 board_82598 },
3845bec0
PWJ		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
90 board_82598 },
9a799d71 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 92 board_82598 },
8d792cd9
JB		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
94 board_82598 },
c4900be0
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
98 board_82598 },
b95f5fcb
JB		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
100 board_82598 },
c4900be0
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
102 board_82598 },
2f21bdd3
DS		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
104 board_82598 },
e8e26350
PW		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
106 board_82599 },
1fcf03e6
PWJ		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
108 board_82599 },
74757d49
DS		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
110 board_82599 },
e8e26350
PW		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
112 board_82599 },
38ad1c8e
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
114 board_82599 },
dbfec662
DS		 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
116 board_82599 },
8911184f
PWJ		 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
118 board_82599 },
dbffcb21
DS		 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
120 board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
122 board_82599 },
119fc60a
MC		 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
124 board_82599 },
312eb931
DS		 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
126 board_82599 },
b93a2226 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 128 board_X540 },
4c40ef02
ET		 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
130 board_82599 },
4f6290cf
DS		 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
132 board_82599 },
9a799d71
AK		 133
134 /* required last entry */
135 {0, }
136};
137MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138
5dd2d332 139#ifdef CONFIG_IXGBE_DCA
bd0362dd 140static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 141 void *p);
bd0362dd
JC		 142static struct notifier_block dca_notifier = {
143 .notifier_call = ixgbe_notify_dca,
144 .next = NULL,
145 .priority = 0
146};
147#endif
148
1cdd1ec8
GR		 149#ifdef CONFIG_PCI_IOV
150static unsigned int max_vfs;
151module_param(max_vfs, uint, 0);
e8e9f696
JP		 152MODULE_PARM_DESC(max_vfs,
153 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 154#endif /* CONFIG_PCI_IOV */
155
9a799d71
AK		 156MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158MODULE_LICENSE("GPL");
159MODULE_VERSION(DRV_VERSION);
160
161#define DEFAULT_DEBUG_LEVEL_SHIFT 3
162
1cdd1ec8
GR		 163static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
164{
165 struct ixgbe_hw *hw = &adapter->hw;
166 u32 gcr;
167 u32 gpie;
168 u32 vmdctl;
169
170#ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter->pdev);
173#endif
174
175 /* turn off device IOV mode */
176 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
177 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
178 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
179 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
180 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
181 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
182
183 /* set default pool back to 0 */
184 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
185 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
186 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
187
188 /* take a breather then clean up driver data */
189 msleep(100);
e8e9f696
JP		 190
191 kfree(adapter->vfinfo);
1cdd1ec8
GR		 192 adapter->vfinfo = NULL;
193
194 adapter->num_vfs = 0;
195 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
196}
197
7086400d
AD		 198static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199{
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203}
204
205static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206{
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212}
213
dcd79aeb
TI		 214struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217};
218
219static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249};
250
251
252/*
253 * ixgbe_regdump - register printout routine
254 */
255static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256{
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
c7689578 319 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 326 pr_err("%-15s", rname);
dcd79aeb 327 for (j = 0; j < 8; j++)
c7689578
JP		 328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
dcd79aeb
TI		 330 }
331
332}
333
334/*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337static void ixgbe_dump(struct ixgbe_adapter *adapter)
338{
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer_info;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 359 pr_info("Device Name state "
dcd79aeb 360 "trans_start last_rx\n");
c7689578
JP		 361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
dcd79aeb
TI		 366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 370 pr_info(" Register Name Value\n");
dcd79aeb
TI		 371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 382 for (n = 0; n < adapter->num_tx_queues; n++) {
383 tx_ring = adapter->tx_ring[n];
384 tx_buffer_info =
385 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 387 n, tx_ring->next_to_use, tx_ring->next_to_clean,
388 (u64)tx_buffer_info->dma,
389 tx_buffer_info->length,
390 tx_buffer_info->next_to_watch,
391 (u64)tx_buffer_info->time_stamp);
392 }
393
394 /* Print TX Rings */
395 if (!netif_msg_tx_done(adapter))
396 goto rx_ring_summary;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
399
400 /* Transmit Descriptor Formats
401 *
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
409 */
410
411 for (n = 0; n < adapter->num_tx_queues; n++) {
412 tx_ring = adapter->tx_ring[n];
c7689578
JP		 413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
419
420 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 421 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 422 tx_buffer_info = &tx_ring->tx_buffer_info[i];
423 u0 = (struct my_u0 *)tx_desc;
c7689578 424 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 425 " %04X %3X %016llX %p", i,
426 le64_to_cpu(u0->a),
427 le64_to_cpu(u0->b),
428 (u64)tx_buffer_info->dma,
429 tx_buffer_info->length,
430 tx_buffer_info->next_to_watch,
431 (u64)tx_buffer_info->time_stamp,
432 tx_buffer_info->skb);
433 if (i == tx_ring->next_to_use &&
434 i == tx_ring->next_to_clean)
c7689578 435 pr_cont(" NTC/U\n");
dcd79aeb 436 else if (i == tx_ring->next_to_use)
c7689578 437 pr_cont(" NTU\n");
dcd79aeb 438 else if (i == tx_ring->next_to_clean)
c7689578 439 pr_cont(" NTC\n");
dcd79aeb 440 else
c7689578 441 pr_cont("\n");
dcd79aeb
TI		 442
443 if (netif_msg_pktdata(adapter) &&
444 tx_buffer_info->dma != 0)
445 print_hex_dump(KERN_INFO, "",
446 DUMP_PREFIX_ADDRESS, 16, 1,
447 phys_to_virt(tx_buffer_info->dma),
448 tx_buffer_info->length, true);
449 }
450 }
451
452 /* Print RX Rings Summary */
453rx_ring_summary:
454 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 455 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 456 for (n = 0; n < adapter->num_rx_queues; n++) {
457 rx_ring = adapter->rx_ring[n];
c7689578
JP		 458 pr_info("%5d %5X %5X\n",
459 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 460 }
461
462 /* Print RX Rings */
463 if (!netif_msg_rx_status(adapter))
464 goto exit;
465
466 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
467
468 /* Advanced Receive Descriptor (Read) Format
469 * 63 1 0
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
475 *
476 *
477 * Advanced Receive Descriptor (Write-Back) Format
478 *
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
487 */
488 for (n = 0; n < adapter->num_rx_queues; n++) {
489 rx_ring = adapter->rx_ring[n];
c7689578
JP		 490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
c7689578 496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
499
500 for (i = 0; i < rx_ring->count; i++) {
501 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 502 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 503 u0 = (struct my_u0 *)rx_desc;
504 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
505 if (staterr & IXGBE_RXD_STAT_DD) {
506 /* Descriptor Done */
c7689578 507 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 508 "%016llX ---------------- %p", i,
509 le64_to_cpu(u0->a),
510 le64_to_cpu(u0->b),
511 rx_buffer_info->skb);
512 } else {
c7689578 513 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 514 "%016llX %016llX %p", i,
515 le64_to_cpu(u0->a),
516 le64_to_cpu(u0->b),
517 (u64)rx_buffer_info->dma,
518 rx_buffer_info->skb);
519
520 if (netif_msg_pktdata(adapter)) {
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS, 16, 1,
523 phys_to_virt(rx_buffer_info->dma),
524 rx_ring->rx_buf_len, true);
525
526 if (rx_ring->rx_buf_len
527 < IXGBE_RXBUFFER_2048)
528 print_hex_dump(KERN_INFO, "",
529 DUMP_PREFIX_ADDRESS, 16, 1,
530 phys_to_virt(
531 rx_buffer_info->page_dma +
532 rx_buffer_info->page_offset
533 ),
534 PAGE_SIZE/2, true);
535 }
536 }
537
538 if (i == rx_ring->next_to_use)
c7689578 539 pr_cont(" NTU\n");
dcd79aeb 540 else if (i == rx_ring->next_to_clean)
c7689578 541 pr_cont(" NTC\n");
dcd79aeb 542 else
c7689578 543 pr_cont("\n");
dcd79aeb
TI		 544
545 }
546 }
547
548exit:
549 return;
550}
551
5eba3699
AV		 552static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
553{
554 u32 ctrl_ext;
555
556 /* Let firmware take over control of h/w */
557 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
558 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 559 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 560}
561
562static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
563{
564 u32 ctrl_ext;
565
566 /* Let firmware know the driver has taken over */
567 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 569 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 570}
9a799d71 571
e8e26350
PW		 572/*
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
578 *
579 */
580static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 581 u8 queue, u8 msix_vector)
9a799d71
AK		 582{
583 u32 ivar, index;
e8e26350
PW		 584 struct ixgbe_hw *hw = &adapter->hw;
585 switch (hw->mac.type) {
586 case ixgbe_mac_82598EB:
587 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
588 if (direction == -1)
589 direction = 0;
590 index = (((direction * 64) + queue) >> 2) & 0x1F;
591 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
592 ivar &= ~(0xFF << (8 * (queue & 0x3)));
593 ivar |= (msix_vector << (8 * (queue & 0x3)));
594 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
595 break;
596 case ixgbe_mac_82599EB:
b93a2226 597 case ixgbe_mac_X540:
e8e26350
PW		 598 if (direction == -1) {
599 /* other causes */
600 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
601 index = ((queue & 1) * 8);
602 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
603 ivar &= ~(0xFF << index);
604 ivar |= (msix_vector << index);
605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
606 break;
607 } else {
608 /* tx or rx causes */
609 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
610 index = ((16 * (queue & 1)) + (8 * direction));
611 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
612 ivar &= ~(0xFF << index);
613 ivar |= (msix_vector << index);
614 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
615 break;
616 }
617 default:
618 break;
619 }
9a799d71
AK		 620}
621
fe49f04a 622static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 623 u64 qmask)
fe49f04a
AD		 624{
625 u32 mask;
626
bd508178
AD		 627 switch (adapter->hw.mac.type) {
628 case ixgbe_mac_82598EB:
fe49f04a
AD		 629 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 631 break;
632 case ixgbe_mac_82599EB:
b93a2226 633 case ixgbe_mac_X540:
fe49f04a
AD		 634 mask = (qmask & 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
636 mask = (qmask >> 32);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 638 break;
639 default:
640 break;
fe49f04a
AD		 641 }
642}
643
b6ec895e
AD		 644void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
645 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 646{
e5a43549
AD		 647 if (tx_buffer_info->dma) {
648 if (tx_buffer_info->mapped_as_page)
b6ec895e 649 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 650 tx_buffer_info->dma,
651 tx_buffer_info->length,
1b507730 652 DMA_TO_DEVICE);
e5a43549 653 else
b6ec895e 654 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 655 tx_buffer_info->dma,
656 tx_buffer_info->length,
1b507730 657 DMA_TO_DEVICE);
e5a43549
AD		 658 tx_buffer_info->dma = 0;
659 }
9a799d71
AK		 660 if (tx_buffer_info->skb) {
661 dev_kfree_skb_any(tx_buffer_info->skb);
662 tx_buffer_info->skb = NULL;
663 }
44df32c5 664 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 665 /* tx_buffer_info must be completely set up in the transmit path */
666}
667
c84d324c
JF		 668static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
669{
670 struct ixgbe_hw *hw = &adapter->hw;
671 struct ixgbe_hw_stats *hwstats = &adapter->stats;
672 u32 data = 0;
673 u32 xoff[8] = {0};
674 int i;
675
676 if ((hw->fc.current_mode == ixgbe_fc_full) ||
677 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
678 switch (hw->mac.type) {
679 case ixgbe_mac_82598EB:
680 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 681 break;
682 default:
c84d324c
JF		 683 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
684 }
685 hwstats->lxoffrxc += data;
686
687 /* refill credits (no tx hang) if we received xoff */
688 if (!data)
689 return;
690
691 for (i = 0; i < adapter->num_tx_queues; i++)
692 clear_bit(__IXGBE_HANG_CHECK_ARMED,
693 &adapter->tx_ring[i]->state);
694 return;
695 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
696 return;
697
698 /* update stats for each tc, only valid with PFC enabled */
699 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
700 switch (hw->mac.type) {
701 case ixgbe_mac_82598EB:
702 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 703 break;
c84d324c
JF		 704 default:
705 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 706 }
c84d324c
JF		 707 hwstats->pxoffrxc[i] += xoff[i];
708 }
709
710 /* disarm tx queues that have received xoff frames */
711 for (i = 0; i < adapter->num_tx_queues; i++) {
712 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 713 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 714
715 if (xoff[tc])
716 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 717 }
26f23d82
YZ		 718}
719
c84d324c 720static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 721{
c84d324c
JF		 722 return ring->tx_stats.completed;
723}
724
725static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
726{
727 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 728 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 729
c84d324c
JF		 730 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
731 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
732
733 if (head != tail)
734 return (head < tail) ?
735 tail - head : (tail + ring->count - head);
736
737 return 0;
738}
739
740static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
741{
742 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
743 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
744 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
745 bool ret = false;
746
7d637bcc 747 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 748
749 /*
750 * Check for a hung queue, but be thorough. This verifies
751 * that a transmit has been completed since the previous
752 * check AND there is at least one packet pending. The
753 * ARMED bit is set to indicate a potential hang. The
754 * bit is cleared if a pause frame is received to remove
755 * false hang detection due to PFC or 802.3x frames. By
756 * requiring this to fail twice we avoid races with
757 * pfc clearing the ARMED bit and conditions where we
758 * run the check_tx_hang logic with a transmit completion
759 * pending but without time to complete it yet.
760 */
761 if ((tx_done_old == tx_done) && tx_pending) {
762 /* make sure it is true for two checks in a row */
763 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
764 &tx_ring->state);
765 } else {
766 /* update completed stats and continue */
767 tx_ring->tx_stats.tx_done_old = tx_done;
768 /* reset the countdown */
769 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 770 }
771
c84d324c 772 return ret;
9a799d71
AK		 773}
774
c83c6cbd
AD		 775/**
776 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
777 * @adapter: driver private struct
778 **/
779static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
780{
781
782 /* Do the reset outside of interrupt context */
783 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
784 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
785 ixgbe_service_event_schedule(adapter);
786 }
787}
e01c31a5 788
9a799d71
AK		 789/**
790 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 791 * @q_vector: structure containing interrupt and ring information
e01c31a5 792 * @tx_ring: tx ring to clean
9a799d71 793 **/
fe49f04a 794static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 795 struct ixgbe_ring *tx_ring)
9a799d71 796{
fe49f04a 797 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 798 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
799 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 800 unsigned int total_bytes = 0, total_packets = 0;
b953799e 801 u16 i, eop, count = 0;
9a799d71
AK		 802
803 i = tx_ring->next_to_clean;
12207e49 804 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 805 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 806
807 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
bd198058 808 (count < q_vector->tx.work_limit)) {
12207e49 809 bool cleaned = false;
2d0bb1c1 810 rmb(); /* read buffer_info after eop_desc */
12207e49 811 for ( ; !cleaned; count++) {
31f05a2d 812 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 813 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 814
815 tx_desc->wb.status = 0;
12207e49 816 cleaned = (i == eop);
9a799d71 817
8ad494b0
AD		 818 i++;
819 if (i == tx_ring->count)
820 i = 0;
e01c31a5 821
8ad494b0
AD		 822 if (cleaned && tx_buffer_info->skb) {
823 total_bytes += tx_buffer_info->bytecount;
824 total_packets += tx_buffer_info->gso_segs;
e092be60 825 }
e01c31a5 826
b6ec895e 827 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 828 tx_buffer_info);
e01c31a5 829 }
12207e49 830
c84d324c 831 tx_ring->tx_stats.completed++;
12207e49 832 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 833 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 834 }
835
9a799d71 836 tx_ring->next_to_clean = i;
b953799e 837 tx_ring->stats.bytes += total_bytes;
bd198058
AD		 838 tx_ring->stats.packets += total_packets;
839 u64_stats_update_begin(&tx_ring->syncp);
840 q_vector->tx.total_bytes += total_bytes;
841 q_vector->tx.total_packets += total_packets;
b953799e
AD		 842 u64_stats_update_end(&tx_ring->syncp);
843
c84d324c
JF		 844 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
845 /* schedule immediate reset if we believe we hung */
846 struct ixgbe_hw *hw = &adapter->hw;
847 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
848 e_err(drv, "Detected Tx Unit Hang\n"
849 " Tx Queue <%d>\n"
850 " TDH, TDT <%x>, <%x>\n"
851 " next_to_use <%x>\n"
852 " next_to_clean <%x>\n"
853 "tx_buffer_info[next_to_clean]\n"
854 " time_stamp <%lx>\n"
855 " jiffies <%lx>\n",
856 tx_ring->queue_index,
857 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
858 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
859 tx_ring->next_to_use, eop,
860 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
861
862 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
863
864 e_info(probe,
865 "tx hang %d detected on queue %d, resetting adapter\n",
866 adapter->tx_timeout_count + 1, tx_ring->queue_index);
867
b953799e 868 /* schedule immediate reset if we believe we hung */
c83c6cbd 869 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 870
871 /* the adapter is about to reset, no point in enabling stuff */
872 return true;
873 }
9a799d71 874
e092be60 875#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 876 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 877 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 878 /* Make sure that anybody stopping the queue after this
879 * sees the new next_to_clean.
880 */
881 smp_mb();
fc77dc3c 882 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 883 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 884 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 885 ++tx_ring->tx_stats.restart_queue;
30eba97a 886 }
e092be60 887 }
9a799d71 888
bd198058 889 return count < q_vector->tx.work_limit;
9a799d71
AK		 890}
891
5dd2d332 892#ifdef CONFIG_IXGBE_DCA
bd0362dd 893static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 894 struct ixgbe_ring *rx_ring,
895 int cpu)
bd0362dd 896{
33cf09c9 897 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 898 u32 rxctrl;
33cf09c9
AD		 899 u8 reg_idx = rx_ring->reg_idx;
900
901 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
902 switch (hw->mac.type) {
903 case ixgbe_mac_82598EB:
904 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
905 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
906 break;
907 case ixgbe_mac_82599EB:
b93a2226 908 case ixgbe_mac_X540:
33cf09c9
AD		 909 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
910 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
911 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
912 break;
913 default:
914 break;
bd0362dd 915 }
33cf09c9
AD		 916 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
917 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
918 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 919 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 920}
921
922static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 923 struct ixgbe_ring *tx_ring,
924 int cpu)
bd0362dd 925{
33cf09c9 926 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 927 u32 txctrl;
33cf09c9
AD		 928 u8 reg_idx = tx_ring->reg_idx;
929
930 switch (hw->mac.type) {
931 case ixgbe_mac_82598EB:
932 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
933 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
934 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
935 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 936 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
937 break;
938 case ixgbe_mac_82599EB:
b93a2226 939 case ixgbe_mac_X540:
33cf09c9
AD		 940 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
941 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
942 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
943 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
944 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 945 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
946 break;
947 default:
948 break;
949 }
950}
951
952static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
953{
954 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 955 int cpu = get_cpu();
33cf09c9
AD		 956 long r_idx;
957 int i;
bd0362dd 958
33cf09c9
AD		 959 if (q_vector->cpu == cpu)
960 goto out_no_update;
961
08c8833b
AD		 962 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
963 for (i = 0; i < q_vector->tx.count; i++) {
33cf09c9 964 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
08c8833b 965 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
33cf09c9 966 r_idx + 1);
bd0362dd 967 }
33cf09c9 968
08c8833b
AD		 969 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
970 for (i = 0; i < q_vector->rx.count; i++) {
33cf09c9 971 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
08c8833b 972 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
33cf09c9
AD		 973 r_idx + 1);
974 }
975
976 q_vector->cpu = cpu;
977out_no_update:
bd0362dd
JC		 978 put_cpu();
979}
980
981static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
982{
33cf09c9 983 int num_q_vectors;
bd0362dd
JC		 984 int i;
985
986 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
987 return;
988
e35ec126
AD		 989 /* always use CB2 mode, difference is masked in the CB driver */
990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
991
33cf09c9
AD		 992 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
993 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
994 else
995 num_q_vectors = 1;
996
997 for (i = 0; i < num_q_vectors; i++) {
998 adapter->q_vector[i]->cpu = -1;
999 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1000 }
1001}
1002
1003static int __ixgbe_notify_dca(struct device *dev, void *data)
1004{
c60fbb00 1005 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1006 unsigned long event = *(unsigned long *)data;
1007
33cf09c9
AD		 1008 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1009 return 0;
1010
bd0362dd
JC		 1011 switch (event) {
1012 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1013 /* if we're already enabled, don't do it again */
1014 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1015 break;
652f093f 1016 if (dca_add_requester(dev) == 0) {
96b0e0f6 1017 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1018 ixgbe_setup_dca(adapter);
1019 break;
1020 }
1021 /* Fall Through since DCA is disabled. */
1022 case DCA_PROVIDER_REMOVE:
1023 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1024 dca_remove_requester(dev);
1025 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1026 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1027 }
1028 break;
1029 }
1030
652f093f 1031 return 0;
bd0362dd 1032}
5dd2d332 1033#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 1034
1035static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1036 struct sk_buff *skb)
1037{
1038 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1039}
1040
ff886dfc
AD		 1041/**
1042 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1043 * @adapter: address of board private structure
1044 * @rx_desc: advanced rx descriptor
1045 *
1046 * Returns : true if it is FCoE pkt
1047 */
1048static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1049 union ixgbe_adv_rx_desc *rx_desc)
1050{
1051 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1052
1053 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1054 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1055 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1056 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1057}
1058
9a799d71
AK		 1059/**
1060 * ixgbe_receive_skb - Send a completed packet up the stack
1061 * @adapter: board private structure
1062 * @skb: packet to send up
177db6ff
MC		 1063 * @status: hardware indication of status of receive
1064 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1065 * @rx_desc: rx descriptor
9a799d71 1066 **/
78b6f4ce 1067static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1068 struct sk_buff *skb, u8 status,
1069 struct ixgbe_ring *ring,
1070 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1071{
78b6f4ce
HX		 1072 struct ixgbe_adapter *adapter = q_vector->adapter;
1073 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1074 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1075 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1076
f62bbb5e
JG		 1077 if (is_vlan && (tag & VLAN_VID_MASK))
1078 __vlan_hwaccel_put_tag(skb, tag);
1079
1080 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1081 napi_gro_receive(napi, skb);
1082 else
1083 netif_rx(skb);
9a799d71
AK		 1084}
1085
e59bd25d
AV		 1086/**
1087 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1088 * @adapter: address of board private structure
1089 * @status_err: hardware indication of status of receive
1090 * @skb: skb currently being received and modified
ff886dfc 1091 * @status_err: status error value of last descriptor in packet
e59bd25d 1092 **/
9a799d71 1093static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1094 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1095 struct sk_buff *skb,
1096 u32 status_err)
9a799d71 1097{
ff886dfc 1098 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1099
712744be
JB		 1100 /* Rx csum disabled */
1101 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1102 return;
e59bd25d
AV		 1103
1104 /* if IP and error */
1105 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1106 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1107 adapter->hw_csum_rx_error++;
1108 return;
1109 }
e59bd25d
AV		 1110
1111 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1112 return;
1113
1114 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1115 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1116
1117 /*
1118 * 82599 errata, UDP frames with a 0 checksum can be marked as
1119 * checksum errors.
1120 */
1121 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1122 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1123 return;
1124
e59bd25d
AV		 1125 adapter->hw_csum_rx_error++;
1126 return;
1127 }
1128
9a799d71 1129 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1130 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1131}
1132
84ea2591 1133static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1134{
1135 /*
1136 * Force memory writes to complete before letting h/w
1137 * know there are new descriptors to fetch. (Only
1138 * applicable for weak-ordered memory model archs,
1139 * such as IA-64).
1140 */
1141 wmb();
84ea2591 1142 writel(val, rx_ring->tail);
e8e26350
PW		 1143}
1144
9a799d71
AK		 1145/**
1146 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1147 * @rx_ring: ring to place buffers on
1148 * @cleaned_count: number of buffers to replace
9a799d71 1149 **/
fc77dc3c 1150void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1151{
9a799d71 1152 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1153 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1154 struct sk_buff *skb;
1155 u16 i = rx_ring->next_to_use;
9a799d71 1156
fc77dc3c
AD		 1157 /* do nothing if no valid netdev defined */
1158 if (!rx_ring->netdev)
1159 return;
1160
9a799d71 1161 while (cleaned_count--) {
31f05a2d 1162 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1163 bi = &rx_ring->rx_buffer_info[i];
1164 skb = bi->skb;
9a799d71 1165
d5f398ed 1166 if (!skb) {
fc77dc3c 1167 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1168 rx_ring->rx_buf_len);
9a799d71 1169 if (!skb) {
5b7da515 1170 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1171 goto no_buffers;
1172 }
d716a7d8
AD		 1173 /* initialize queue mapping */
1174 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1175 bi->skb = skb;
d716a7d8 1176 }
9a799d71 1177
d716a7d8 1178 if (!bi->dma) {
b6ec895e 1179 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1180 skb->data,
e8e9f696 1181 rx_ring->rx_buf_len,
1b507730 1182 DMA_FROM_DEVICE);
b6ec895e 1183 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1184 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1185 bi->dma = 0;
1186 goto no_buffers;
1187 }
9a799d71 1188 }
d5f398ed 1189
7d637bcc 1190 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1191 if (!bi->page) {
fc77dc3c 1192 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1193 if (!bi->page) {
5b7da515 1194 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1195 goto no_buffers;
1196 }
1197 }
1198
1199 if (!bi->page_dma) {
1200 /* use a half page if we're re-using */
1201 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1202 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1203 bi->page,
1204 bi->page_offset,
1205 PAGE_SIZE / 2,
1206 DMA_FROM_DEVICE);
b6ec895e 1207 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1208 bi->page_dma)) {
5b7da515 1209 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1210 bi->page_dma = 0;
1211 goto no_buffers;
1212 }
1213 }
1214
1215 /* Refresh the desc even if buffer_addrs didn't change
1216 * because each write-back erases this info. */
3a581073
JB		 1217 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1218 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1219 } else {
3a581073 1220 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1221 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1222 }
1223
1224 i++;
1225 if (i == rx_ring->count)
1226 i = 0;
9a799d71 1227 }
7c6e0a43 1228
9a799d71
AK		 1229no_buffers:
1230 if (rx_ring->next_to_use != i) {
1231 rx_ring->next_to_use = i;
84ea2591 1232 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1233 }
1234}
1235
c267fc16 1236static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1237{
c267fc16
AD		 1238 /* HW will not DMA in data larger than the given buffer, even if it
1239 * parses the (NFS, of course) header to be larger. In that case, it
1240 * fills the header buffer and spills the rest into the page.
1241 */
1242 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1243 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1244 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1245 if (hlen > IXGBE_RX_HDR_SIZE)
1246 hlen = IXGBE_RX_HDR_SIZE;
1247 return hlen;
7c6e0a43
JB		 1248}
1249
f8212f97
AD		 1250/**
1251 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1252 * @skb: pointer to the last skb in the rsc queue
1253 *
1254 * This function changes a queue full of hw rsc buffers into a completed
1255 * packet. It uses the ->prev pointers to find the first packet and then
1256 * turns it into the frag list owner.
1257 **/
aa80175a 1258static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1259{
1260 unsigned int frag_list_size = 0;
aa80175a 1261 unsigned int skb_cnt = 1;
f8212f97
AD		 1262
1263 while (skb->prev) {
1264 struct sk_buff *prev = skb->prev;
1265 frag_list_size += skb->len;
1266 skb->prev = NULL;
1267 skb = prev;
aa80175a 1268 skb_cnt++;
f8212f97
AD		 1269 }
1270
1271 skb_shinfo(skb)->frag_list = skb->next;
1272 skb->next = NULL;
1273 skb->len += frag_list_size;
1274 skb->data_len += frag_list_size;
1275 skb->truesize += frag_list_size;
aa80175a
AD		 1276 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1277
f8212f97
AD		 1278 return skb;
1279}
1280
aa80175a
AD		 1281static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1282{
1283 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1284 IXGBE_RXDADV_RSCCNT_MASK);
1285}
43634e82 1286
c267fc16 1287static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1288 struct ixgbe_ring *rx_ring,
1289 int *work_done, int work_to_do)
9a799d71 1290{
78b6f4ce 1291 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1292 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1293 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1294 struct sk_buff *skb;
d2f4fbe2 1295 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1296 const int current_node = numa_node_id();
3d8fd385
YZ		 1297#ifdef IXGBE_FCOE
1298 int ddp_bytes = 0;
1299#endif /* IXGBE_FCOE */
c267fc16
AD		 1300 u32 staterr;
1301 u16 i;
1302 u16 cleaned_count = 0;
aa80175a 1303 bool pkt_is_rsc = false;
9a799d71
AK		 1304
1305 i = rx_ring->next_to_clean;
31f05a2d 1306 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1307 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1308
1309 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1310 u32 upper_len = 0;
9a799d71 1311
3c945e5b 1312 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1313
c267fc16
AD		 1314 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1315
9a799d71 1316 skb = rx_buffer_info->skb;
9a799d71 1317 rx_buffer_info->skb = NULL;
c267fc16 1318 prefetch(skb->data);
9a799d71 1319
c267fc16 1320 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1321 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1322
1323 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1324 if (rx_buffer_info->dma) {
c267fc16 1325 u16 hlen;
aa80175a 1326 if (pkt_is_rsc &&
c267fc16
AD		 1327 !(staterr & IXGBE_RXD_STAT_EOP) &&
1328 !skb->prev) {
43634e82
MC		 1329 /*
1330 * When HWRSC is enabled, delay unmapping
1331 * of the first packet. It carries the
1332 * header information, HW may still
1333 * access the header after the writeback.
1334 * Only unmap it when EOP is reached
1335 */
e8171aaa 1336 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1337 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1338 } else {
b6ec895e 1339 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1340 rx_buffer_info->dma,
1341 rx_ring->rx_buf_len,
1342 DMA_FROM_DEVICE);
e8171aaa 1343 }
4f57ca6e 1344 rx_buffer_info->dma = 0;
c267fc16
AD		 1345
1346 if (ring_is_ps_enabled(rx_ring)) {
1347 hlen = ixgbe_get_hlen(rx_desc);
1348 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1349 } else {
1350 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1351 }
1352
1353 skb_put(skb, hlen);
1354 } else {
1355 /* assume packet split since header is unmapped */
1356 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1357 }
1358
1359 if (upper_len) {
b6ec895e
AD		 1360 dma_unmap_page(rx_ring->dev,
1361 rx_buffer_info->page_dma,
1362 PAGE_SIZE / 2,
1363 DMA_FROM_DEVICE);
9a799d71
AK		 1364 rx_buffer_info->page_dma = 0;
1365 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1366 rx_buffer_info->page,
1367 rx_buffer_info->page_offset,
1368 upper_len);
762f4c57 1369
c267fc16
AD		 1370 if ((page_count(rx_buffer_info->page) == 1) &&
1371 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1372 get_page(rx_buffer_info->page);
c267fc16
AD		 1373 else
1374 rx_buffer_info->page = NULL;
9a799d71
AK		 1375
1376 skb->len += upper_len;
1377 skb->data_len += upper_len;
1378 skb->truesize += upper_len;
1379 }
1380
1381 i++;
1382 if (i == rx_ring->count)
1383 i = 0;
9a799d71 1384
31f05a2d 1385 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1386 prefetch(next_rxd);
9a799d71 1387 cleaned_count++;
f8212f97 1388
aa80175a 1389 if (pkt_is_rsc) {
f8212f97
AD		 1390 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1391 IXGBE_RXDADV_NEXTP_SHIFT;
1392 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1393 } else {
1394 next_buffer = &rx_ring->rx_buffer_info[i];
1395 }
1396
c267fc16 1397 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1398 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1399 rx_buffer_info->skb = next_buffer->skb;
1400 rx_buffer_info->dma = next_buffer->dma;
1401 next_buffer->skb = skb;
1402 next_buffer->dma = 0;
1403 } else {
1404 skb->next = next_buffer->skb;
1405 skb->next->prev = skb;
1406 }
5b7da515 1407 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1408 goto next_desc;
1409 }
1410
aa80175a
AD		 1411 if (skb->prev) {
1412 skb = ixgbe_transform_rsc_queue(skb);
1413 /* if we got here without RSC the packet is invalid */
1414 if (!pkt_is_rsc) {
1415 __pskb_trim(skb, 0);
1416 rx_buffer_info->skb = skb;
1417 goto next_desc;
1418 }
1419 }
c267fc16
AD		 1420
1421 if (ring_is_rsc_enabled(rx_ring)) {
1422 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1423 dma_unmap_single(rx_ring->dev,
1424 IXGBE_RSC_CB(skb)->dma,
1425 rx_ring->rx_buf_len,
1426 DMA_FROM_DEVICE);
1427 IXGBE_RSC_CB(skb)->dma = 0;
1428 IXGBE_RSC_CB(skb)->delay_unmap = false;
1429 }
aa80175a
AD		 1430 }
1431 if (pkt_is_rsc) {
c267fc16
AD		 1432 if (ring_is_ps_enabled(rx_ring))
1433 rx_ring->rx_stats.rsc_count +=
aa80175a 1434 skb_shinfo(skb)->nr_frags;
c267fc16 1435 else
aa80175a
AD		 1436 rx_ring->rx_stats.rsc_count +=
1437 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1438 rx_ring->rx_stats.rsc_flush++;
1439 }
1440
1441 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1442 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1443 dev_kfree_skb_any(skb);
9a799d71
AK		 1444 goto next_desc;
1445 }
1446
ff886dfc 1447 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1448 if (adapter->netdev->features & NETIF_F_RXHASH)
1449 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1450
1451 /* probably a little skewed due to removing CRC */
1452 total_rx_bytes += skb->len;
1453 total_rx_packets++;
1454
fc77dc3c 1455 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1456#ifdef IXGBE_FCOE
1457 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1458 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1459 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1460 staterr);
3d8fd385 1461 if (!ddp_bytes)
332d4a7d 1462 goto next_desc;
3d8fd385 1463 }
332d4a7d 1464#endif /* IXGBE_FCOE */
fdaff1ce 1465 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1466
1467next_desc:
1468 rx_desc->wb.upper.status_error = 0;
1469
c267fc16
AD		 1470 (*work_done)++;
1471 if (*work_done >= work_to_do)
1472 break;
1473
9a799d71
AK		 1474 /* return some buffers to hardware, one at a time is too slow */
1475 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1476 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1477 cleaned_count = 0;
1478 }
1479
1480 /* use prefetched values */
1481 rx_desc = next_rxd;
9a799d71 1482 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1483 }
1484
9a799d71 1485 rx_ring->next_to_clean = i;
7d4987de 1486 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1487
1488 if (cleaned_count)
fc77dc3c 1489 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1490
3d8fd385
YZ		 1491#ifdef IXGBE_FCOE
1492 /* include DDPed FCoE data */
1493 if (ddp_bytes > 0) {
1494 unsigned int mss;
1495
fc77dc3c 1496 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1497 sizeof(struct fc_frame_header) -
1498 sizeof(struct fcoe_crc_eof);
1499 if (mss > 512)
1500 mss &= ~511;
1501 total_rx_bytes += ddp_bytes;
1502 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1503 }
1504#endif /* IXGBE_FCOE */
1505
c267fc16
AD		 1506 u64_stats_update_begin(&rx_ring->syncp);
1507 rx_ring->stats.packets += total_rx_packets;
1508 rx_ring->stats.bytes += total_rx_bytes;
1509 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1510 q_vector->rx.total_packets += total_rx_packets;
1511 q_vector->rx.total_bytes += total_rx_bytes;
9a799d71
AK		 1512}
1513
021230d4 1514static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1515/**
1516 * ixgbe_configure_msix - Configure MSI-X hardware
1517 * @adapter: board private structure
1518 *
1519 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1520 * interrupts.
1521 **/
1522static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1523{
021230d4 1524 struct ixgbe_q_vector *q_vector;
bf29ee6c 1525 int i, q_vectors, v_idx, r_idx;
021230d4 1526 u32 mask;
9a799d71 1527
021230d4 1528 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1529
4df10466
JB		 1530 /*
1531 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1532 * corresponding register.
1533 */
1534 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1535 q_vector = adapter->q_vector[v_idx];
984b3f57 1536 /* XXX for_each_set_bit(...) */
08c8833b 1537 r_idx = find_first_bit(q_vector->rx.idx,
e8e9f696 1538 adapter->num_rx_queues);
021230d4 1539
08c8833b 1540 for (i = 0; i < q_vector->rx.count; i++) {
bf29ee6c
AD		 1541 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1542 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
08c8833b 1543 r_idx = find_next_bit(q_vector->rx.idx,
e8e9f696
JP		 1544 adapter->num_rx_queues,
1545 r_idx + 1);
021230d4 1546 }
08c8833b 1547 r_idx = find_first_bit(q_vector->tx.idx,
e8e9f696 1548 adapter->num_tx_queues);
021230d4 1549
08c8833b 1550 for (i = 0; i < q_vector->tx.count; i++) {
bf29ee6c
AD		 1551 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1552 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
08c8833b 1553 r_idx = find_next_bit(q_vector->tx.idx,
e8e9f696
JP		 1554 adapter->num_tx_queues,
1555 r_idx + 1);
021230d4
AV		 1556 }
1557
08c8833b 1558 if (q_vector->tx.count && !q_vector->rx.count)
f7554a2b
NS		 1559 /* tx only */
1560 q_vector->eitr = adapter->tx_eitr_param;
08c8833b 1561 else if (q_vector->rx.count)
f7554a2b
NS		 1562 /* rx or mixed */
1563 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1564
fe49f04a 1565 ixgbe_write_eitr(q_vector);
03ecf91a
AD		 1566 /* If ATR is enabled, set interrupt affinity */
1567 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
b25ebfd2
PW		 1568 /*
1569 * Allocate the affinity_hint cpumask, assign the mask
1570 * for this vector, and set our affinity_hint for
1571 * this irq.
1572 */
1573 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1574 GFP_KERNEL))
1575 return;
1576 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1577 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1578 q_vector->affinity_mask);
1579 }
9a799d71
AK		 1580 }
1581
bd508178
AD		 1582 switch (adapter->hw.mac.type) {
1583 case ixgbe_mac_82598EB:
e8e26350 1584 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1585 v_idx);
bd508178
AD		 1586 break;
1587 case ixgbe_mac_82599EB:
b93a2226 1588 case ixgbe_mac_X540:
e8e26350 1589 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1590 break;
1591
1592 default:
1593 break;
1594 }
021230d4
AV		 1595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1596
41fb9248 1597 /* set up to autoclear timer, and the vectors */
021230d4 1598 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1599 if (adapter->num_vfs)
1600 mask &= ~(IXGBE_EIMS_OTHER |
1601 IXGBE_EIMS_MAILBOX |
1602 IXGBE_EIMS_LSC);
1603 else
1604 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1606}
1607
f494e8fa
AV		 1608enum latency_range {
1609 lowest_latency = 0,
1610 low_latency = 1,
1611 bulk_latency = 2,
1612 latency_invalid = 255
1613};
1614
1615/**
1616 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1617 * @q_vector: structure containing interrupt and ring information
1618 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1619 *
1620 * Stores a new ITR value based on packets and byte
1621 * counts during the last interrupt. The advantage of per interrupt
1622 * computation is faster updates and more accurate ITR for the current
1623 * traffic pattern. Constants in this function were computed
1624 * based on theoretical maximum wire speed and thresholds were set based
1625 * on testing data as well as attempting to minimize response time
1626 * while increasing bulk throughput.
1627 * this functionality is controlled by the InterruptThrottleRate module
1628 * parameter (see ixgbe_param.c)
1629 **/
bd198058
AD		 1630static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1631 struct ixgbe_ring_container *ring_container)
f494e8fa 1632{
f494e8fa 1633 u64 bytes_perint;
bd198058
AD		 1634 struct ixgbe_adapter *adapter = q_vector->adapter;
1635 int bytes = ring_container->total_bytes;
1636 int packets = ring_container->total_packets;
1637 u32 timepassed_us;
1638 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1639
1640 if (packets == 0)
bd198058 1641 return;
f494e8fa
AV		 1642
1643 /* simple throttlerate management
1644 * 0-20MB/s lowest (100000 ints/s)
1645 * 20-100MB/s low (20000 ints/s)
1646 * 100-1249MB/s bulk (8000 ints/s)
1647 */
1648 /* what was last interrupt timeslice? */
bd198058 1649 timepassed_us = 1000000/q_vector->eitr;
f494e8fa
AV		 1650 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1651
1652 switch (itr_setting) {
1653 case lowest_latency:
1654 if (bytes_perint > adapter->eitr_low)
bd198058 1655 itr_setting = low_latency;
f494e8fa
AV		 1656 break;
1657 case low_latency:
1658 if (bytes_perint > adapter->eitr_high)
bd198058 1659 itr_setting = bulk_latency;
f494e8fa 1660 else if (bytes_perint <= adapter->eitr_low)
bd198058 1661 itr_setting = lowest_latency;
f494e8fa
AV		 1662 break;
1663 case bulk_latency:
1664 if (bytes_perint <= adapter->eitr_high)
bd198058 1665 itr_setting = low_latency;
f494e8fa
AV		 1666 break;
1667 }
1668
bd198058
AD		 1669 /* clear work counters since we have the values we need */
1670 ring_container->total_bytes = 0;
1671 ring_container->total_packets = 0;
1672
1673 /* write updated itr to ring container */
1674 ring_container->itr = itr_setting;
f494e8fa
AV		 1675}
1676
509ee935
JB		 1677/**
1678 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1679 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1680 *
1681 * This function is made to be called by ethtool and by the driver
1682 * when it needs to update EITR registers at runtime. Hardware
1683 * specific quirks/differences are taken care of here.
1684 */
fe49f04a 1685void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1686{
fe49f04a 1687 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1688 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1689 int v_idx = q_vector->v_idx;
1690 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1691
bd508178
AD		 1692 switch (adapter->hw.mac.type) {
1693 case ixgbe_mac_82598EB:
509ee935
JB		 1694 /* must write high and low 16 bits to reset counter */
1695 itr_reg |= (itr_reg << 16);
bd508178
AD		 1696 break;
1697 case ixgbe_mac_82599EB:
b93a2226 1698 case ixgbe_mac_X540:
f8d1dcaf 1699 /*
b93a2226 1700 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1701 * max interrupt rate, but there is an errata where it can
1702 * not be zero with RSC
1703 */
1704 if (itr_reg == 8 &&
1705 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1706 itr_reg = 0;
1707
509ee935
JB		 1708 /*
1709 * set the WDIS bit to not clear the timer bits and cause an
1710 * immediate assertion of the interrupt
1711 */
1712 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1713 break;
1714 default:
1715 break;
509ee935
JB		 1716 }
1717 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1718}
1719
bd198058 1720static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1721{
bd198058
AD		 1722 u32 new_itr = q_vector->eitr;
1723 u8 current_itr;
f494e8fa 1724
bd198058
AD		 1725 ixgbe_update_itr(q_vector, &q_vector->tx);
1726 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1727
08c8833b 1728 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1729
1730 switch (current_itr) {
1731 /* counts and packets in update_itr are dependent on these numbers */
1732 case lowest_latency:
1733 new_itr = 100000;
1734 break;
1735 case low_latency:
1736 new_itr = 20000; /* aka hwitr = ~200 */
1737 break;
1738 case bulk_latency:
f494e8fa
AV		 1739 new_itr = 8000;
1740 break;
bd198058
AD		 1741 default:
1742 break;
f494e8fa
AV		 1743 }
1744
1745 if (new_itr != q_vector->eitr) {
fe49f04a 1746 /* do an exponential smoothing */
125601bf 1747 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 1748
bd198058 1749 /* save the algorithm value here */
509ee935 1750 q_vector->eitr = new_itr;
fe49f04a
AD		 1751
1752 ixgbe_write_eitr(q_vector);
f494e8fa 1753 }
f494e8fa
AV		 1754}
1755
119fc60a 1756/**
f0f9778d
AD		 1757 * ixgbe_check_overtemp_subtask - check for over tempurature
1758 * @adapter: pointer to adapter
119fc60a 1759 **/
f0f9778d 1760static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1761{
119fc60a
MC		 1762 struct ixgbe_hw *hw = &adapter->hw;
1763 u32 eicr = adapter->interrupt_event;
1764
f0f9778d 1765 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1766 return;
1767
f0f9778d
AD		 1768 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1769 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1770 return;
1771
1772 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1773
7ca647bd 1774 switch (hw->device_id) {
f0f9778d
AD		 1775 case IXGBE_DEV_ID_82599_T3_LOM:
1776 /*
1777 * Since the warning interrupt is for both ports
1778 * we don't have to check if:
1779 * - This interrupt wasn't for our port.
1780 * - We may have missed the interrupt so always have to
1781 * check if we got a LSC
1782 */
1783 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1784 !(eicr & IXGBE_EICR_LSC))
1785 return;
1786
1787 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1788 u32 autoneg;
1789 bool link_up = false;
7ca647bd 1790
7ca647bd
JP		 1791 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1792
f0f9778d
AD		 1793 if (link_up)
1794 return;
1795 }
1796
1797 /* Check if this is not due to overtemp */
1798 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1799 return;
1800
1801 break;
7ca647bd
JP		 1802 default:
1803 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1804 return;
7ca647bd 1805 break;
119fc60a 1806 }
7ca647bd
JP		 1807 e_crit(drv,
1808 "Network adapter has been stopped because it has over heated. "
1809 "Restart the computer. If the problem persists, "
1810 "power off the system and replace the adapter\n");
f0f9778d
AD		 1811
1812 adapter->interrupt_event = 0;
119fc60a
MC		 1813}
1814
0befdb3e
JB		 1815static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1816{
1817 struct ixgbe_hw *hw = &adapter->hw;
1818
1819 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1820 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1821 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1822 /* write to clear the interrupt */
1823 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1824 }
1825}
cf8280ee 1826
e8e26350
PW		 1827static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1828{
1829 struct ixgbe_hw *hw = &adapter->hw;
1830
73c4b7cd
AD		 1831 if (eicr & IXGBE_EICR_GPI_SDP2) {
1832 /* Clear the interrupt */
1833 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1834 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1835 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1836 ixgbe_service_event_schedule(adapter);
1837 }
73c4b7cd
AD		 1838 }
1839
e8e26350
PW		 1840 if (eicr & IXGBE_EICR_GPI_SDP1) {
1841 /* Clear the interrupt */
1842 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1843 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1844 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1845 ixgbe_service_event_schedule(adapter);
1846 }
e8e26350
PW		 1847 }
1848}
1849
cf8280ee
JB		 1850static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1851{
1852 struct ixgbe_hw *hw = &adapter->hw;
1853
1854 adapter->lsc_int++;
1855 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1856 adapter->link_check_timeout = jiffies;
1857 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1858 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1859 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1860 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1861 }
1862}
1863
9a799d71
AK		 1864static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1865{
a65151ba 1866 struct ixgbe_adapter *adapter = data;
9a799d71 1867 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1868 u32 eicr;
1869
1870 /*
1871 * Workaround for Silicon errata. Use clear-by-write instead
1872 * of clear-by-read. Reading with EICS will return the
1873 * interrupt causes without clearing, which later be done
1874 * with the write to EICR.
1875 */
1876 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1877 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1878
cf8280ee
JB		 1879 if (eicr & IXGBE_EICR_LSC)
1880 ixgbe_check_lsc(adapter);
d4f80882 1881
1cdd1ec8
GR		 1882 if (eicr & IXGBE_EICR_MAILBOX)
1883 ixgbe_msg_task(adapter);
1884
bd508178
AD		 1885 switch (hw->mac.type) {
1886 case ixgbe_mac_82599EB:
b93a2226 1887 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1888 /* Handle Flow Director Full threshold interrupt */
1889 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1890 int reinit_count = 0;
c4cf55e5 1891 int i;
c4cf55e5 1892 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1893 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1894 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1895 &ring->state))
1896 reinit_count++;
1897 }
1898 if (reinit_count) {
1899 /* no more flow director interrupts until after init */
1900 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1901 eicr &= ~IXGBE_EICR_FLOW_DIR;
1902 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1903 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1904 }
1905 }
f0f9778d
AD		 1906 ixgbe_check_sfp_event(adapter, eicr);
1907 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1908 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1909 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1910 adapter->interrupt_event = eicr;
1911 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1912 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1913 }
1914 }
bd508178
AD		 1915 break;
1916 default:
1917 break;
c4cf55e5 1918 }
bd508178
AD		 1919
1920 ixgbe_check_fan_failure(adapter, eicr);
1921
7086400d 1922 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1923 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7086400d
AD		 1924 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1925 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
9a799d71
AK		 1926
1927 return IRQ_HANDLED;
1928}
1929
fe49f04a
AD		 1930static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1931 u64 qmask)
1932{
1933 u32 mask;
bd508178 1934 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1935
bd508178
AD		 1936 switch (hw->mac.type) {
1937 case ixgbe_mac_82598EB:
fe49f04a 1938 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1939 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1940 break;
1941 case ixgbe_mac_82599EB:
b93a2226 1942 case ixgbe_mac_X540:
fe49f04a 1943 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1944 if (mask)
1945 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1946 mask = (qmask >> 32);
bd508178
AD		 1947 if (mask)
1948 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1949 break;
1950 default:
1951 break;
fe49f04a
AD		 1952 }
1953 /* skip the flush */
1954}
1955
1956static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1957 u64 qmask)
fe49f04a
AD		 1958{
1959 u32 mask;
bd508178 1960 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1961
bd508178
AD		 1962 switch (hw->mac.type) {
1963 case ixgbe_mac_82598EB:
fe49f04a 1964 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1965 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1966 break;
1967 case ixgbe_mac_82599EB:
b93a2226 1968 case ixgbe_mac_X540:
fe49f04a 1969 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1970 if (mask)
1971 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1972 mask = (qmask >> 32);
bd508178
AD		 1973 if (mask)
1974 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1975 break;
1976 default:
1977 break;
fe49f04a
AD		 1978 }
1979 /* skip the flush */
1980}
1981
9a799d71
AK		 1982static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1983{
021230d4
AV		 1984 struct ixgbe_q_vector *q_vector = data;
1985 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1986 struct ixgbe_ring *tx_ring;
021230d4
AV		 1987 int i, r_idx;
1988
08c8833b 1989 if (!q_vector->tx.count)
021230d4
AV		 1990 return IRQ_HANDLED;
1991
08c8833b
AD		 1992 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
1993 for (i = 0; i < q_vector->tx.count; i++) {
4a0b9ca0 1994 tx_ring = adapter->tx_ring[r_idx];
08c8833b 1995 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
e8e9f696 1996 r_idx + 1);
021230d4 1997 }
9a799d71 1998
9b471446 1999 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2000 napi_schedule(&q_vector->napi);
2001
9a799d71
AK		 2002 return IRQ_HANDLED;
2003}
2004
021230d4
AV		 2005/**
2006 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2007 * @irq: unused
2008 * @data: pointer to our q_vector struct for this interrupt vector
2009 **/
9a799d71
AK		 2010static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2011{
021230d4
AV		 2012 struct ixgbe_q_vector *q_vector = data;
2013 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2014 struct ixgbe_ring *rx_ring;
021230d4 2015 int r_idx;
30efa5a3 2016 int i;
021230d4 2017
33cf09c9
AD		 2018#ifdef CONFIG_IXGBE_DCA
2019 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2020 ixgbe_update_dca(q_vector);
2021#endif
2022
08c8833b
AD		 2023 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2024 for (i = 0; i < q_vector->rx.count; i++) {
4a0b9ca0 2025 rx_ring = adapter->rx_ring[r_idx];
08c8833b 2026 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
e8e9f696 2027 r_idx + 1);
30efa5a3
JB		 2028 }
2029
08c8833b 2030 if (!q_vector->rx.count)
021230d4
AV		 2031 return IRQ_HANDLED;
2032
9b471446 2033 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2034 napi_schedule(&q_vector->napi);
021230d4
AV		 2035
2036 return IRQ_HANDLED;
2037}
2038
2039static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2040{
91281fd3
AD		 2041 struct ixgbe_q_vector *q_vector = data;
2042 struct ixgbe_adapter *adapter = q_vector->adapter;
2043 struct ixgbe_ring *ring;
2044 int r_idx;
2045 int i;
2046
08c8833b 2047 if (!q_vector->tx.count && !q_vector->rx.count)
91281fd3
AD		 2048 return IRQ_HANDLED;
2049
08c8833b
AD		 2050 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2051 for (i = 0; i < q_vector->tx.count; i++) {
4a0b9ca0 2052 ring = adapter->tx_ring[r_idx];
08c8833b 2053 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
e8e9f696 2054 r_idx + 1);
91281fd3
AD		 2055 }
2056
08c8833b
AD		 2057 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2058 for (i = 0; i < q_vector->rx.count; i++) {
4a0b9ca0 2059 ring = adapter->rx_ring[r_idx];
08c8833b 2060 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
e8e9f696 2061 r_idx + 1);
91281fd3
AD		 2062 }
2063
9b471446 2064 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2065 napi_schedule(&q_vector->napi);
9a799d71 2066
9a799d71
AK		 2067 return IRQ_HANDLED;
2068}
2069
021230d4
AV		 2070/**
2071 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2072 * @napi: napi struct with our devices info in it
2073 * @budget: amount of work driver is allowed to do this pass, in packets
2074 *
f0848276
JB		 2075 * This function is optimized for cleaning one queue only on a single
2076 * q_vector!!!
021230d4 2077 **/
9a799d71
AK		 2078static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2079{
021230d4 2080 struct ixgbe_q_vector *q_vector =
e8e9f696 2081 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2082 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2083 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2084 int work_done = 0;
021230d4 2085 long r_idx;
9a799d71 2086
5dd2d332 2087#ifdef CONFIG_IXGBE_DCA
bd0362dd 2088 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2089 ixgbe_update_dca(q_vector);
bd0362dd 2090#endif
9a799d71 2091
08c8833b 2092 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
33cf09c9
AD		 2093 rx_ring = adapter->rx_ring[r_idx];
2094
78b6f4ce 2095 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2096
021230d4
AV		 2097 /* If all Rx work done, exit the polling mode */
2098 if (work_done < budget) {
288379f0 2099 napi_complete(napi);
f7554a2b 2100 if (adapter->rx_itr_setting & 1)
bd198058 2101 ixgbe_set_itr(q_vector);
9a799d71 2102 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2103 ixgbe_irq_enable_queues(adapter,
e8e9f696 2104 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2105 }
2106
2107 return work_done;
2108}
2109
f0848276 2110/**
91281fd3 2111 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2112 * @napi: napi struct with our devices info in it
2113 * @budget: amount of work driver is allowed to do this pass, in packets
2114 *
2115 * This function will clean more than one rx queue associated with a
2116 * q_vector.
2117 **/
91281fd3 2118static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2119{
2120 struct ixgbe_q_vector *q_vector =
e8e9f696 2121 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2122 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2123 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2124 int work_done = 0, i;
2125 long r_idx;
91281fd3
AD		 2126 bool tx_clean_complete = true;
2127
33cf09c9
AD		 2128#ifdef CONFIG_IXGBE_DCA
2129 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2130 ixgbe_update_dca(q_vector);
2131#endif
2132
08c8833b
AD		 2133 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2134 for (i = 0; i < q_vector->tx.count; i++) {
4a0b9ca0 2135 ring = adapter->tx_ring[r_idx];
91281fd3 2136 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
08c8833b 2137 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
e8e9f696 2138 r_idx + 1);
91281fd3 2139 }
f0848276
JB		 2140
2141 /* attempt to distribute budget to each queue fairly, but don't allow
2142 * the budget to go below 1 because we'll exit polling */
08c8833b 2143 budget /= (q_vector->rx.count ?: 1);
f0848276 2144 budget = max(budget, 1);
08c8833b
AD		 2145 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2146 for (i = 0; i < q_vector->rx.count; i++) {
4a0b9ca0 2147 ring = adapter->rx_ring[r_idx];
91281fd3 2148 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
08c8833b 2149 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
e8e9f696 2150 r_idx + 1);
f0848276
JB		 2151 }
2152
08c8833b 2153 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
4a0b9ca0 2154 ring = adapter->rx_ring[r_idx];
f0848276 2155 /* If all Rx work done, exit the polling mode */
7f821875 2156 if (work_done < budget) {
288379f0 2157 napi_complete(napi);
f7554a2b 2158 if (adapter->rx_itr_setting & 1)
bd198058 2159 ixgbe_set_itr(q_vector);
f0848276 2160 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2161 ixgbe_irq_enable_queues(adapter,
e8e9f696 2162 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2163 return 0;
2164 }
2165
2166 return work_done;
2167}
91281fd3
AD		 2168
2169/**
2170 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2171 * @napi: napi struct with our devices info in it
2172 * @budget: amount of work driver is allowed to do this pass, in packets
2173 *
2174 * This function is optimized for cleaning one queue only on a single
2175 * q_vector!!!
2176 **/
2177static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2178{
2179 struct ixgbe_q_vector *q_vector =
e8e9f696 2180 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2181 struct ixgbe_adapter *adapter = q_vector->adapter;
2182 struct ixgbe_ring *tx_ring = NULL;
2183 int work_done = 0;
2184 long r_idx;
2185
91281fd3
AD		 2186#ifdef CONFIG_IXGBE_DCA
2187 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2188 ixgbe_update_dca(q_vector);
91281fd3
AD		 2189#endif
2190
08c8833b 2191 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
33cf09c9
AD		 2192 tx_ring = adapter->tx_ring[r_idx];
2193
91281fd3
AD		 2194 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2195 work_done = budget;
2196
f7554a2b 2197 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2198 if (work_done < budget) {
2199 napi_complete(napi);
f7554a2b 2200 if (adapter->tx_itr_setting & 1)
bd198058 2201 ixgbe_set_itr(q_vector);
91281fd3 2202 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2203 ixgbe_irq_enable_queues(adapter,
2204 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2205 }
2206
2207 return work_done;
2208}
2209
021230d4 2210static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2211 int r_idx)
021230d4 2212{
7a921c93 2213 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2214 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2215
08c8833b
AD		 2216 set_bit(r_idx, q_vector->rx.idx);
2217 q_vector->rx.count++;
2274543f 2218 rx_ring->q_vector = q_vector;
021230d4
AV		 2219}
2220
2221static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2222 int t_idx)
021230d4 2223{
7a921c93 2224 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2225 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2226
08c8833b
AD		 2227 set_bit(t_idx, q_vector->tx.idx);
2228 q_vector->tx.count++;
2274543f 2229 tx_ring->q_vector = q_vector;
bd198058 2230 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2231}
2232
9a799d71 2233/**
021230d4
AV		 2234 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2235 * @adapter: board private structure to initialize
9a799d71 2236 *
021230d4
AV		 2237 * This function maps descriptor rings to the queue-specific vectors
2238 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2239 * one vector per ring/queue, but on a constrained vector budget, we
2240 * group the rings as "efficiently" as possible. You would add new
2241 * mapping configurations in here.
9a799d71 2242 **/
d0759ebb 2243static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2244{
d0759ebb 2245 int q_vectors;
021230d4
AV		 2246 int v_start = 0;
2247 int rxr_idx = 0, txr_idx = 0;
2248 int rxr_remaining = adapter->num_rx_queues;
2249 int txr_remaining = adapter->num_tx_queues;
2250 int i, j;
2251 int rqpv, tqpv;
2252 int err = 0;
2253
2254 /* No mapping required if MSI-X is disabled. */
2255 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2256 goto out;
9a799d71 2257
d0759ebb
AD		 2258 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2259
021230d4
AV		 2260 /*
2261 * The ideal configuration...
2262 * We have enough vectors to map one per queue.
2263 */
d0759ebb 2264 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2265 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2266 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2267
021230d4
AV		 2268 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2269 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2270
9a799d71 2271 goto out;
021230d4 2272 }
9a799d71 2273
021230d4
AV		 2274 /*
2275 * If we don't have enough vectors for a 1-to-1
2276 * mapping, we'll have to group them so there are
2277 * multiple queues per vector.
2278 */
2279 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2280 for (i = v_start; i < q_vectors; i++) {
2281 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2282 for (j = 0; j < rqpv; j++) {
2283 map_vector_to_rxq(adapter, i, rxr_idx);
2284 rxr_idx++;
2285 rxr_remaining--;
2286 }
d0759ebb 2287 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2288 for (j = 0; j < tqpv; j++) {
2289 map_vector_to_txq(adapter, i, txr_idx);
2290 txr_idx++;
2291 txr_remaining--;
9a799d71 2292 }
9a799d71 2293 }
021230d4
AV		 2294out:
2295 return err;
2296}
2297
2298/**
2299 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2300 * @adapter: board private structure
2301 *
2302 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2303 * interrupts from the kernel.
2304 **/
2305static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2306{
2307 struct net_device *netdev = adapter->netdev;
2308 irqreturn_t (*handler)(int, void *);
2309 int i, vector, q_vectors, err;
e8e9f696 2310 int ri = 0, ti = 0;
021230d4
AV		 2311
2312 /* Decrement for Other and TCP Timer vectors */
2313 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2314
d0759ebb 2315 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2316 if (err)
d0759ebb 2317 return err;
021230d4 2318
08c8833b 2319#define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count) \
d0759ebb 2320 ? &ixgbe_msix_clean_many : \
08c8833b
AD		 2321 (_v)->rx.count ? &ixgbe_msix_clean_rx : \
2322 (_v)->tx.count ? &ixgbe_msix_clean_tx : \
d0759ebb 2323 NULL)
021230d4 2324 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2325 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2326 handler = SET_HANDLER(q_vector);
cb13fc20 2327
e8e9f696 2328 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2329 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2330 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2331 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2332 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2333 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2334 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2335 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2336 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2337 ti++;
d0759ebb
AD		 2338 } else {
2339 /* skip this unused q_vector */
2340 continue;
32aa77a4 2341 }
021230d4 2342 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2343 handler, 0, q_vector->name,
2344 q_vector);
9a799d71 2345 if (err) {
396e799c 2346 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2347 "Error: %d\n", err);
021230d4 2348 goto free_queue_irqs;
9a799d71 2349 }
9a799d71
AK		 2350 }
2351
d0759ebb 2352 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2353 err = request_irq(adapter->msix_entries[vector].vector,
a65151ba 2354 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
9a799d71 2355 if (err) {
396e799c 2356 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2357 goto free_queue_irqs;
9a799d71
AK		 2358 }
2359
9a799d71
AK		 2360 return 0;
2361
021230d4
AV		 2362free_queue_irqs:
2363 for (i = vector - 1; i >= 0; i--)
2364 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2365 adapter->q_vector[i]);
021230d4
AV		 2366 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2367 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2368 kfree(adapter->msix_entries);
2369 adapter->msix_entries = NULL;
9a799d71
AK		 2370 return err;
2371}
2372
79aefa45
AD		 2373/**
2374 * ixgbe_irq_enable - Enable default interrupt generation settings
2375 * @adapter: board private structure
2376 **/
6af3b9eb
ET		 2377static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2378 bool flush)
79aefa45
AD		 2379{
2380 u32 mask;
835462fc
NS		 2381
2382 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2383 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2384 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2385 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2386 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2387 switch (adapter->hw.mac.type) {
2388 case ixgbe_mac_82599EB:
b93a2226 2389 case ixgbe_mac_X540:
2a41ff81 2390 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2391 mask |= IXGBE_EIMS_GPI_SDP1;
2392 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2393 if (adapter->num_vfs)
2394 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2395 break;
2396 default:
2397 break;
e8e26350 2398 }
03ecf91a 2399 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
c4cf55e5 2400 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2401
79aefa45 2402 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2403 if (queues)
2404 ixgbe_irq_enable_queues(adapter, ~0);
2405 if (flush)
2406 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2407
2408 if (adapter->num_vfs > 32) {
2409 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2410 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2411 }
79aefa45 2412}
021230d4 2413
9a799d71 2414/**
021230d4 2415 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2416 * @irq: interrupt number
2417 * @data: pointer to a network interface device structure
9a799d71
AK		 2418 **/
2419static irqreturn_t ixgbe_intr(int irq, void *data)
2420{
a65151ba 2421 struct ixgbe_adapter *adapter = data;
9a799d71 2422 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2423 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2424 u32 eicr;
2425
54037505 2426 /*
6af3b9eb 2427 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2428 * before the read of EICR.
2429 */
2430 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2431
021230d4
AV		 2432 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2433 * therefore no explict interrupt disable is necessary */
2434 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2435 if (!eicr) {
6af3b9eb
ET		 2436 /*
2437 * shared interrupt alert!
f47cf66e 2438 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2439 * have disabled interrupts due to EIAM
2440 * finish the workaround of silicon errata on 82598. Unmask
2441 * the interrupt that we masked before the EICR read.
2442 */
2443 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2444 ixgbe_irq_enable(adapter, true, true);
9a799d71 2445 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2446 }
9a799d71 2447
cf8280ee
JB		 2448 if (eicr & IXGBE_EICR_LSC)
2449 ixgbe_check_lsc(adapter);
021230d4 2450
bd508178
AD		 2451 switch (hw->mac.type) {
2452 case ixgbe_mac_82599EB:
e8e26350 2453 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2454 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2455 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
f0f9778d
AD		 2456 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2457 adapter->interrupt_event = eicr;
2458 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2459 ixgbe_service_event_schedule(adapter);
2460 }
bd508178
AD		 2461 }
2462 break;
2463 default:
2464 break;
2465 }
e8e26350 2466
0befdb3e
JB		 2467 ixgbe_check_fan_failure(adapter, eicr);
2468
7a921c93 2469 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2470 /* would disable interrupts here but EIAM disabled it */
7a921c93 2471 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2472 }
2473
6af3b9eb
ET		 2474 /*
2475 * re-enable link(maybe) and non-queue interrupts, no flush.
2476 * ixgbe_poll will re-enable the queue interrupts
2477 */
2478
2479 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2480 ixgbe_irq_enable(adapter, false, false);
2481
9a799d71
AK		 2482 return IRQ_HANDLED;
2483}
2484
021230d4
AV		 2485static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2486{
2487 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2488
2489 for (i = 0; i < q_vectors; i++) {
7a921c93 2490 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
08c8833b
AD		 2491 bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
2492 bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
2493 q_vector->rx.count = 0;
2494 q_vector->tx.count = 0;
021230d4
AV		 2495 }
2496}
2497
9a799d71
AK		 2498/**
2499 * ixgbe_request_irq - initialize interrupts
2500 * @adapter: board private structure
2501 *
2502 * Attempts to configure interrupts using the best available
2503 * capabilities of the hardware and kernel.
2504 **/
021230d4 2505static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2506{
2507 struct net_device *netdev = adapter->netdev;
021230d4 2508 int err;
9a799d71 2509
021230d4
AV		 2510 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2511 err = ixgbe_request_msix_irqs(adapter);
2512 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2513 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2514 netdev->name, adapter);
021230d4 2515 } else {
a0607fd3 2516 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2517 netdev->name, adapter);
9a799d71
AK		 2518 }
2519
9a799d71 2520 if (err)
396e799c 2521 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2522
9a799d71
AK		 2523 return err;
2524}
2525
2526static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2527{
9a799d71 2528 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2529 int i, q_vectors;
9a799d71 2530
021230d4
AV		 2531 q_vectors = adapter->num_msix_vectors;
2532
2533 i = q_vectors - 1;
a65151ba 2534 free_irq(adapter->msix_entries[i].vector, adapter);
9a799d71 2535
021230d4
AV		 2536 i--;
2537 for (; i >= 0; i--) {
894ff7cf 2538 /* free only the irqs that were actually requested */
08c8833b
AD		 2539 if (!adapter->q_vector[i]->rx.count &&
2540 !adapter->q_vector[i]->tx.count)
894ff7cf
AD		 2541 continue;
2542
021230d4 2543 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2544 adapter->q_vector[i]);
021230d4
AV		 2545 }
2546
2547 ixgbe_reset_q_vectors(adapter);
2548 } else {
a65151ba 2549 free_irq(adapter->pdev->irq, adapter);
9a799d71
AK		 2550 }
2551}
2552
22d5a71b
JB		 2553/**
2554 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2555 * @adapter: board private structure
2556 **/
2557static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2558{
bd508178
AD		 2559 switch (adapter->hw.mac.type) {
2560 case ixgbe_mac_82598EB:
835462fc 2561 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2562 break;
2563 case ixgbe_mac_82599EB:
b93a2226 2564 case ixgbe_mac_X540:
835462fc
NS		 2565 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2566 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2568 if (adapter->num_vfs > 32)
2569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2570 break;
2571 default:
2572 break;
22d5a71b
JB		 2573 }
2574 IXGBE_WRITE_FLUSH(&adapter->hw);
2575 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2576 int i;
2577 for (i = 0; i < adapter->num_msix_vectors; i++)
2578 synchronize_irq(adapter->msix_entries[i].vector);
2579 } else {
2580 synchronize_irq(adapter->pdev->irq);
2581 }
2582}
2583
9a799d71
AK		 2584/**
2585 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2586 *
2587 **/
2588static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2589{
9a799d71
AK		 2590 struct ixgbe_hw *hw = &adapter->hw;
2591
021230d4 2592 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2593 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2594
e8e26350
PW		 2595 ixgbe_set_ivar(adapter, 0, 0, 0);
2596 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2597
2598 map_vector_to_rxq(adapter, 0, 0);
2599 map_vector_to_txq(adapter, 0, 0);
2600
396e799c 2601 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2602}
2603
43e69bf0
AD		 2604/**
2605 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2606 * @adapter: board private structure
2607 * @ring: structure containing ring specific data
2608 *
2609 * Configure the Tx descriptor ring after a reset.
2610 **/
84418e3b
AD		 2611void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2612 struct ixgbe_ring *ring)
43e69bf0
AD		 2613{
2614 struct ixgbe_hw *hw = &adapter->hw;
2615 u64 tdba = ring->dma;
2f1860b8
AD		 2616 int wait_loop = 10;
2617 u32 txdctl;
bf29ee6c 2618 u8 reg_idx = ring->reg_idx;
43e69bf0 2619
2f1860b8
AD		 2620 /* disable queue to avoid issues while updating state */
2621 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2622 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2623 txdctl & ~IXGBE_TXDCTL_ENABLE);
2624 IXGBE_WRITE_FLUSH(hw);
2625
43e69bf0 2626 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2627 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2628 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2629 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2630 ring->count * sizeof(union ixgbe_adv_tx_desc));
2631 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2632 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2633 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2634
2f1860b8
AD		 2635 /* configure fetching thresholds */
2636 if (adapter->rx_itr_setting == 0) {
2637 /* cannot set wthresh when itr==0 */
2638 txdctl &= ~0x007F0000;
2639 } else {
2640 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2641 txdctl |= (8 << 16);
2642 }
2643 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2644 /* PThresh workaround for Tx hang with DFP enabled. */
2645 txdctl |= 32;
2646 }
2647
2648 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2649 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2650 adapter->atr_sample_rate) {
2651 ring->atr_sample_rate = adapter->atr_sample_rate;
2652 ring->atr_count = 0;
2653 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2654 } else {
2655 ring->atr_sample_rate = 0;
2656 }
2f1860b8 2657
c84d324c
JF		 2658 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2659
2f1860b8
AD		 2660 /* enable queue */
2661 txdctl |= IXGBE_TXDCTL_ENABLE;
2662 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2663
2664 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2665 if (hw->mac.type == ixgbe_mac_82598EB &&
2666 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2667 return;
2668
2669 /* poll to verify queue is enabled */
2670 do {
032b4325 2671 usleep_range(1000, 2000);
2f1860b8
AD		 2672 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2673 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2674 if (!wait_loop)
2675 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2676}
2677
120ff942
AD		 2678static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2679{
2680 struct ixgbe_hw *hw = &adapter->hw;
2681 u32 rttdcs;
72a32f1f 2682 u32 reg;
8b1c0b24 2683 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2684
2685 if (hw->mac.type == ixgbe_mac_82598EB)
2686 return;
2687
2688 /* disable the arbiter while setting MTQC */
2689 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2690 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2691 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2692
2693 /* set transmit pool layout */
8b1c0b24 2694 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2695 case (IXGBE_FLAG_SRIOV_ENABLED):
2696 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2697 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2698 break;
8b1c0b24
JF		 2699 default:
2700 if (!tcs)
2701 reg = IXGBE_MTQC_64Q_1PB;
2702 else if (tcs <= 4)
2703 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2704 else
2705 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2706
8b1c0b24 2707 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2708
8b1c0b24
JF		 2709 /* Enable Security TX Buffer IFG for multiple pb */
2710 if (tcs) {
2711 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2712 reg |= IXGBE_SECTX_DCB;
2713 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2714 }
120ff942
AD		 2715 break;
2716 }
2717
2718 /* re-enable the arbiter */
2719 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2720 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2721}
2722
9a799d71 2723/**
3a581073 2724 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2725 * @adapter: board private structure
2726 *
2727 * Configure the Tx unit of the MAC after a reset.
2728 **/
2729static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2730{
2f1860b8
AD		 2731 struct ixgbe_hw *hw = &adapter->hw;
2732 u32 dmatxctl;
43e69bf0 2733 u32 i;
9a799d71 2734
2f1860b8
AD		 2735 ixgbe_setup_mtqc(adapter);
2736
2737 if (hw->mac.type != ixgbe_mac_82598EB) {
2738 /* DMATXCTL.EN must be before Tx queues are enabled */
2739 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2740 dmatxctl |= IXGBE_DMATXCTL_TE;
2741 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2742 }
2743
9a799d71 2744 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2745 for (i = 0; i < adapter->num_tx_queues; i++)
2746 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2747}
2748
e8e26350 2749#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2750
a6616b42 2751static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2752 struct ixgbe_ring *rx_ring)
cc41ac7c 2753{
cc41ac7c 2754 u32 srrctl;
bf29ee6c 2755 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2756
bd508178
AD		 2757 switch (adapter->hw.mac.type) {
2758 case ixgbe_mac_82598EB: {
2759 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2760 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2761 reg_idx = reg_idx & mask;
cc41ac7c 2762 }
bd508178
AD		 2763 break;
2764 case ixgbe_mac_82599EB:
b93a2226 2765 case ixgbe_mac_X540:
bd508178
AD		 2766 default:
2767 break;
2768 }
2769
bf29ee6c 2770 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2771
2772 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2773 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2774 if (adapter->num_vfs)
2775 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2776
afafd5b0
AD		 2777 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2778 IXGBE_SRRCTL_BSIZEHDR_MASK;
2779
7d637bcc 2780 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2781#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2782 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2783#else
2784 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2785#endif
cc41ac7c 2786 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2787 } else {
afafd5b0
AD		 2788 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2789 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2790 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2791 }
e8e26350 2792
bf29ee6c 2793 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2794}
9a799d71 2795
05abb126 2796static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2797{
05abb126
AD		 2798 struct ixgbe_hw *hw = &adapter->hw;
2799 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2800 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2801 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2802 u32 mrqc = 0, reta = 0;
2803 u32 rxcsum;
2804 int i, j;
8b1c0b24 2805 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2806 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2807
2808 if (tcs)
2809 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2810
05abb126
AD		 2811 /* Fill out hash function seeds */
2812 for (i = 0; i < 10; i++)
2813 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2814
2815 /* Fill out redirection table */
2816 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2817 if (j == maxq)
05abb126
AD		 2818 j = 0;
2819 /* reta = 4-byte sliding window of
2820 * 0x00..(indices-1)(indices-1)00..etc. */
2821 reta = (reta << 8) | (j * 0x11);
2822 if ((i & 3) == 3)
2823 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2824 }
0cefafad 2825
05abb126
AD		 2826 /* Disable indicating checksum in descriptor, enables RSS hash */
2827 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2828 rxcsum |= IXGBE_RXCSUM_PCSD;
2829 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2830
8b1c0b24
JF		 2831 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2832 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2833 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2834 } else {
2835 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2836 | IXGBE_FLAG_SRIOV_ENABLED);
2837
2838 switch (mask) {
2839 case (IXGBE_FLAG_RSS_ENABLED):
2840 if (!tcs)
2841 mrqc = IXGBE_MRQC_RSSEN;
2842 else if (tcs <= 4)
2843 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2844 else
2845 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2846 break;
2847 case (IXGBE_FLAG_SRIOV_ENABLED):
2848 mrqc = IXGBE_MRQC_VMDQEN;
2849 break;
2850 default:
2851 break;
2852 }
0cefafad
JB		 2853 }
2854
05abb126
AD		 2855 /* Perform hash on these packet types */
2856 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2857 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2858 | IXGBE_MRQC_RSS_FIELD_IPV6
2859 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2860
2861 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2862}
2863
b93a2226
DS		 2864/**
2865 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2866 * @adapter: address of board private structure
2867 * @ring: structure containing ring specific data
2868 **/
2869void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2870 struct ixgbe_ring *ring)
2871{
2872 struct ixgbe_hw *hw = &adapter->hw;
2873 u32 rscctrl;
2874 u8 reg_idx = ring->reg_idx;
2875
2876 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2877 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2878 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2879}
2880
bb5a9ad2
NS		 2881/**
2882 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2883 * @adapter: address of board private structure
2884 * @index: index of ring to set
bb5a9ad2 2885 **/
b93a2226 2886void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2887 struct ixgbe_ring *ring)
bb5a9ad2 2888{
bb5a9ad2 2889 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2890 u32 rscctrl;
edd2ea55 2891 int rx_buf_len;
bf29ee6c 2892 u8 reg_idx = ring->reg_idx;
7367096a 2893
7d637bcc 2894 if (!ring_is_rsc_enabled(ring))
7367096a 2895 return;
bb5a9ad2 2896
7367096a
AD		 2897 rx_buf_len = ring->rx_buf_len;
2898 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2899 rscctrl |= IXGBE_RSCCTL_RSCEN;
2900 /*
2901 * we must limit the number of descriptors so that the
2902 * total size of max desc * buf_len is not greater
2903 * than 65535
2904 */
7d637bcc 2905 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2906#if (MAX_SKB_FRAGS > 16)
2907 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2908#elif (MAX_SKB_FRAGS > 8)
2909 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2910#elif (MAX_SKB_FRAGS > 4)
2911 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2912#else
2913 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2914#endif
2915 } else {
2916 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2917 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2918 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2919 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2920 else
2921 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2922 }
7367096a 2923 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2924}
2925
9e10e045
AD		 2926/**
2927 * ixgbe_set_uta - Set unicast filter table address
2928 * @adapter: board private structure
2929 *
2930 * The unicast table address is a register array of 32-bit registers.
2931 * The table is meant to be used in a way similar to how the MTA is used
2932 * however due to certain limitations in the hardware it is necessary to
2933 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2934 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2935 **/
2936static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2937{
2938 struct ixgbe_hw *hw = &adapter->hw;
2939 int i;
2940
2941 /* The UTA table only exists on 82599 hardware and newer */
2942 if (hw->mac.type < ixgbe_mac_82599EB)
2943 return;
2944
2945 /* we only need to do this if VMDq is enabled */
2946 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2947 return;
2948
2949 for (i = 0; i < 128; i++)
2950 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2951}
2952
2953#define IXGBE_MAX_RX_DESC_POLL 10
2954static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2955 struct ixgbe_ring *ring)
2956{
2957 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2958 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2959 u32 rxdctl;
bf29ee6c 2960 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2961
2962 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2963 if (hw->mac.type == ixgbe_mac_82598EB &&
2964 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2965 return;
2966
2967 do {
032b4325 2968 usleep_range(1000, 2000);
9e10e045
AD		 2969 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2970 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2971
2972 if (!wait_loop) {
2973 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2974 "the polling period\n", reg_idx);
2975 }
2976}
2977
2d39d576
YZ		 2978void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2979 struct ixgbe_ring *ring)
2980{
2981 struct ixgbe_hw *hw = &adapter->hw;
2982 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2983 u32 rxdctl;
2984 u8 reg_idx = ring->reg_idx;
2985
2986 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2987 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2988
2989 /* write value back with RXDCTL.ENABLE bit cleared */
2990 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2991
2992 if (hw->mac.type == ixgbe_mac_82598EB &&
2993 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2994 return;
2995
2996 /* the hardware may take up to 100us to really disable the rx queue */
2997 do {
2998 udelay(10);
2999 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3000 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3001
3002 if (!wait_loop) {
3003 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3004 "the polling period\n", reg_idx);
3005 }
3006}
3007
84418e3b
AD		 3008void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3009 struct ixgbe_ring *ring)
acd37177
AD		 3010{
3011 struct ixgbe_hw *hw = &adapter->hw;
3012 u64 rdba = ring->dma;
9e10e045 3013 u32 rxdctl;
bf29ee6c 3014 u8 reg_idx = ring->reg_idx;
acd37177 3015
9e10e045
AD		 3016 /* disable queue to avoid issues while updating state */
3017 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3018 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3019
acd37177
AD		 3020 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3021 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3022 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3023 ring->count * sizeof(union ixgbe_adv_rx_desc));
3024 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3025 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3026 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3027
3028 ixgbe_configure_srrctl(adapter, ring);
3029 ixgbe_configure_rscctl(adapter, ring);
3030
e9f98072
GR		 3031 /* If operating in IOV mode set RLPML for X540 */
3032 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3033 hw->mac.type == ixgbe_mac_X540) {
3034 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3035 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3036 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3037 }
3038
9e10e045
AD		 3039 if (hw->mac.type == ixgbe_mac_82598EB) {
3040 /*
3041 * enable cache line friendly hardware writes:
3042 * PTHRESH=32 descriptors (half the internal cache),
3043 * this also removes ugly rx_no_buffer_count increment
3044 * HTHRESH=4 descriptors (to minimize latency on fetch)
3045 * WTHRESH=8 burst writeback up to two cache lines
3046 */
3047 rxdctl &= ~0x3FFFFF;
3048 rxdctl |= 0x080420;
3049 }
3050
3051 /* enable receive descriptor ring */
3052 rxdctl |= IXGBE_RXDCTL_ENABLE;
3053 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3054
3055 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3056 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3057}
3058
48654521
AD		 3059static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3060{
3061 struct ixgbe_hw *hw = &adapter->hw;
3062 int p;
3063
3064 /* PSRTYPE must be initialized in non 82598 adapters */
3065 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3066 IXGBE_PSRTYPE_UDPHDR |
3067 IXGBE_PSRTYPE_IPV4HDR |
48654521 3068 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3069 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3070
3071 if (hw->mac.type == ixgbe_mac_82598EB)
3072 return;
3073
3074 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3075 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3076
3077 for (p = 0; p < adapter->num_rx_pools; p++)
3078 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3079 psrtype);
3080}
3081
f5b4a52e
AD		 3082static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3083{
3084 struct ixgbe_hw *hw = &adapter->hw;
3085 u32 gcr_ext;
3086 u32 vt_reg_bits;
3087 u32 reg_offset, vf_shift;
3088 u32 vmdctl;
3089
3090 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3091 return;
3092
3093 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3094 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3095 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3096 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3097
3098 vf_shift = adapter->num_vfs % 32;
3099 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3100
3101 /* Enable only the PF's pool for Tx/Rx */
3102 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3103 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3104 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3105 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3106 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3107
3108 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3109 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3110
3111 /*
3112 * Set up VF register offsets for selected VT Mode,
3113 * i.e. 32 or 64 VFs for SR-IOV
3114 */
3115 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3116 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3117 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3118 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3119
3120 /* enable Tx loopback for VF/PF communication */
3121 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3122 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 3123 hw->mac.ops.set_mac_anti_spoofing(hw,
3124 (adapter->antispoofing_enabled =
3125 (adapter->num_vfs != 0)),
a985b6c3 3126 adapter->num_vfs);
f5b4a52e
AD		 3127}
3128
477de6ed 3129static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3130{
9a799d71
AK		 3131 struct ixgbe_hw *hw = &adapter->hw;
3132 struct net_device *netdev = adapter->netdev;
3133 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3134 int rx_buf_len;
477de6ed
AD		 3135 struct ixgbe_ring *rx_ring;
3136 int i;
3137 u32 mhadd, hlreg0;
48654521 3138
9a799d71 3139 /* Decide whether to use packet split mode or not */
a124339a
DS		 3140 /* On by default */
3141 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3142
1cdd1ec8 3143 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3144 if (adapter->num_vfs)
3145 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3146
3147 /* Disable packet split due to 82599 erratum #45 */
3148 if (hw->mac.type == ixgbe_mac_82599EB)
3149 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3150
3151 /* Set the RX buffer length according to the mode */
3152 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3153 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3154 } else {
0c19d6af 3155 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3156 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3157 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3158 else
477de6ed 3159 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3160 }
3161
63f39bd1 3162#ifdef IXGBE_FCOE
477de6ed
AD		 3163 /* adjust max frame to be able to do baby jumbo for FCoE */
3164 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3165 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3166 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3167
477de6ed
AD		 3168#endif /* IXGBE_FCOE */
3169 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3170 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3171 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3172 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3173
3174 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3175 }
3176
3177 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3178 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3179 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3180 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3181
0cefafad
JB		 3182 /*
3183 * Setup the HW Rx Head and Tail Descriptor Pointers and
3184 * the Base and Length of the Rx Descriptor Ring
3185 */
9a799d71 3186 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3187 rx_ring = adapter->rx_ring[i];
a6616b42 3188 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3189
6e455b89 3190 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3191 set_ring_ps_enabled(rx_ring);
3192 else
3193 clear_ring_ps_enabled(rx_ring);
3194
3195 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3196 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3197 else
7d637bcc 3198 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3199
63f39bd1 3200#ifdef IXGBE_FCOE
e8e9f696 3201 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3202 struct ixgbe_ring_feature *f;
3203 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3204 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3205 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3206 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3207 rx_ring->rx_buf_len =
e8e9f696 3208 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3209 } else if (!ring_is_rsc_enabled(rx_ring) &&
3210 !ring_is_ps_enabled(rx_ring)) {
3211 rx_ring->rx_buf_len =
3212 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3213 }
63f39bd1 3214 }
63f39bd1 3215#endif /* IXGBE_FCOE */
477de6ed 3216 }
477de6ed
AD		 3217}
3218
7367096a
AD		 3219static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3220{
3221 struct ixgbe_hw *hw = &adapter->hw;
3222 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3223
3224 switch (hw->mac.type) {
3225 case ixgbe_mac_82598EB:
3226 /*
3227 * For VMDq support of different descriptor types or
3228 * buffer sizes through the use of multiple SRRCTL
3229 * registers, RDRXCTL.MVMEN must be set to 1
3230 *
3231 * also, the manual doesn't mention it clearly but DCA hints
3232 * will only use queue 0's tags unless this bit is set. Side
3233 * effects of setting this bit are only that SRRCTL must be
3234 * fully programmed [0..15]
3235 */
3236 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3237 break;
3238 case ixgbe_mac_82599EB:
b93a2226 3239 case ixgbe_mac_X540:
7367096a
AD		 3240 /* Disable RSC for ACK packets */
3241 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3242 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3243 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3244 /* hardware requires some bits to be set by default */
3245 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3246 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3247 break;
3248 default:
3249 /* We should do nothing since we don't know this hardware */
3250 return;
3251 }
3252
3253 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3254}
3255
477de6ed
AD		 3256/**
3257 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3258 * @adapter: board private structure
3259 *
3260 * Configure the Rx unit of the MAC after a reset.
3261 **/
3262static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3263{
3264 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3265 int i;
3266 u32 rxctrl;
477de6ed
AD		 3267
3268 /* disable receives while setting up the descriptors */
3269 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3270 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3271
3272 ixgbe_setup_psrtype(adapter);
7367096a 3273 ixgbe_setup_rdrxctl(adapter);
477de6ed 3274
9e10e045 3275 /* Program registers for the distribution of queues */
f5b4a52e 3276 ixgbe_setup_mrqc(adapter);
f5b4a52e 3277
9e10e045
AD		 3278 ixgbe_set_uta(adapter);
3279
477de6ed
AD		 3280 /* set_rx_buffer_len must be called before ring initialization */
3281 ixgbe_set_rx_buffer_len(adapter);
3282
3283 /*
3284 * Setup the HW Rx Head and Tail Descriptor Pointers and
3285 * the Base and Length of the Rx Descriptor Ring
3286 */
9e10e045
AD		 3287 for (i = 0; i < adapter->num_rx_queues; i++)
3288 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3289
9e10e045
AD		 3290 /* disable drop enable for 82598 parts */
3291 if (hw->mac.type == ixgbe_mac_82598EB)
3292 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3293
3294 /* enable all receives */
3295 rxctrl |= IXGBE_RXCTRL_RXEN;
3296 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3297}
3298
068c89b0
DS		 3299static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3300{
3301 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3302 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3303 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3304
3305 /* add VID to filter table */
1ada1b1b 3306 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3307 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3308}
3309
3310static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3311{
3312 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3313 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3314 int pool_ndx = adapter->num_vfs;
068c89b0 3315
068c89b0 3316 /* remove VID from filter table */
1ada1b1b 3317 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3318 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3319}
3320
5f6c0181
JB		 3321/**
3322 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3323 * @adapter: driver data
3324 */
3325static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3326{
3327 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3328 u32 vlnctrl;
3329
3330 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3331 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3332 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3333}
3334
3335/**
3336 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3337 * @adapter: driver data
3338 */
3339static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3340{
3341 struct ixgbe_hw *hw = &adapter->hw;
3342 u32 vlnctrl;
3343
3344 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3345 vlnctrl |= IXGBE_VLNCTRL_VFE;
3346 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3347 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3348}
3349
3350/**
3351 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3352 * @adapter: driver data
3353 */
3354static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3355{
3356 struct ixgbe_hw *hw = &adapter->hw;
3357 u32 vlnctrl;
5f6c0181
JB		 3358 int i, j;
3359
3360 switch (hw->mac.type) {
3361 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3362 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3363 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3364 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3365 break;
3366 case ixgbe_mac_82599EB:
b93a2226 3367 case ixgbe_mac_X540:
5f6c0181
JB		 3368 for (i = 0; i < adapter->num_rx_queues; i++) {
3369 j = adapter->rx_ring[i]->reg_idx;
3370 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3371 vlnctrl &= ~IXGBE_RXDCTL_VME;
3372 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3373 }
3374 break;
3375 default:
3376 break;
3377 }
3378}
3379
3380/**
f62bbb5e 3381 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3382 * @adapter: driver data
3383 */
f62bbb5e 3384static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3385{
3386 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3387 u32 vlnctrl;
5f6c0181
JB		 3388 int i, j;
3389
3390 switch (hw->mac.type) {
3391 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3392 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3393 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3394 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3395 break;
3396 case ixgbe_mac_82599EB:
b93a2226 3397 case ixgbe_mac_X540:
5f6c0181
JB		 3398 for (i = 0; i < adapter->num_rx_queues; i++) {
3399 j = adapter->rx_ring[i]->reg_idx;
3400 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3401 vlnctrl |= IXGBE_RXDCTL_VME;
3402 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3403 }
3404 break;
3405 default:
3406 break;
3407 }
3408}
3409
9a799d71
AK		 3410static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3411{
f62bbb5e 3412 u16 vid;
9a799d71 3413
f62bbb5e
JG		 3414 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3415
3416 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3417 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3418}
3419
2850062a
AD		 3420/**
3421 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3422 * @netdev: network interface device structure
3423 *
3424 * Writes unicast address list to the RAR table.
3425 * Returns: -ENOMEM on failure/insufficient address space
3426 * 0 on no addresses written
3427 * X on writing X addresses to the RAR table
3428 **/
3429static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3430{
3431 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3432 struct ixgbe_hw *hw = &adapter->hw;
3433 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3434 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3435 int count = 0;
3436
3437 /* return ENOMEM indicating insufficient memory for addresses */
3438 if (netdev_uc_count(netdev) > rar_entries)
3439 return -ENOMEM;
3440
3441 if (!netdev_uc_empty(netdev) && rar_entries) {
3442 struct netdev_hw_addr *ha;
3443 /* return error if we do not support writing to RAR table */
3444 if (!hw->mac.ops.set_rar)
3445 return -ENOMEM;
3446
3447 netdev_for_each_uc_addr(ha, netdev) {
3448 if (!rar_entries)
3449 break;
3450 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3451 vfn, IXGBE_RAH_AV);
3452 count++;
3453 }
3454 }
3455 /* write the addresses in reverse order to avoid write combining */
3456 for (; rar_entries > 0 ; rar_entries--)
3457 hw->mac.ops.clear_rar(hw, rar_entries);
3458
3459 return count;
3460}
3461
9a799d71 3462/**
2c5645cf 3463 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3464 * @netdev: network interface device structure
3465 *
2c5645cf
CL		 3466 * The set_rx_method entry point is called whenever the unicast/multicast
3467 * address list or the network interface flags are updated. This routine is
3468 * responsible for configuring the hardware for proper unicast, multicast and
3469 * promiscuous mode.
9a799d71 3470 **/
7f870475 3471void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3472{
3473 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3474 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3475 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3476 int count;
9a799d71
AK		 3477
3478 /* Check for Promiscuous and All Multicast modes */
3479
3480 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3481
f5dc442b
AD		 3482 /* set all bits that we expect to always be set */
3483 fctrl |= IXGBE_FCTRL_BAM;
3484 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3485 fctrl |= IXGBE_FCTRL_PMCF;
3486
2850062a
AD		 3487 /* clear the bits we are changing the status of */
3488 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3489
9a799d71 3490 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3491 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3492 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3493 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3494 /* don't hardware filter vlans in promisc mode */
3495 ixgbe_vlan_filter_disable(adapter);
9a799d71 3496 } else {
746b9f02
PM		 3497 if (netdev->flags & IFF_ALLMULTI) {
3498 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3499 vmolr |= IXGBE_VMOLR_MPE;
3500 } else {
3501 /*
3502 * Write addresses to the MTA, if the attempt fails
25985edc 3503 * then we should just turn on promiscuous mode so
2850062a
AD		 3504 * that we can at least receive multicast traffic
3505 */
3506 hw->mac.ops.update_mc_addr_list(hw, netdev);
3507 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3508 }
5f6c0181 3509 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3510 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3511 /*
3512 * Write addresses to available RAR registers, if there is not
3513 * sufficient space to store all the addresses then enable
25985edc 3514 * unicast promiscuous mode
2850062a
AD		 3515 */
3516 count = ixgbe_write_uc_addr_list(netdev);
3517 if (count < 0) {
3518 fctrl |= IXGBE_FCTRL_UPE;
3519 vmolr |= IXGBE_VMOLR_ROPE;
3520 }
9a799d71
AK		 3521 }
3522
2850062a 3523 if (adapter->num_vfs) {
1cdd1ec8 3524 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3525 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3526 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3527 IXGBE_VMOLR_ROPE);
3528 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3529 }
3530
3531 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3532
3533 if (netdev->features & NETIF_F_HW_VLAN_RX)
3534 ixgbe_vlan_strip_enable(adapter);
3535 else
3536 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3537}
3538
021230d4
AV		 3539static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3540{
3541 int q_idx;
3542 struct ixgbe_q_vector *q_vector;
3543 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3544
3545 /* legacy and MSI only use one vector */
3546 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3547 q_vectors = 1;
3548
3549 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3550 struct napi_struct *napi;
7a921c93 3551 q_vector = adapter->q_vector[q_idx];
f0848276 3552 napi = &q_vector->napi;
91281fd3 3553 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
08c8833b
AD		 3554 if (!q_vector->rx.count || !q_vector->tx.count) {
3555 if (q_vector->tx.count == 1)
91281fd3 3556 napi->poll = &ixgbe_clean_txonly;
08c8833b 3557 else if (q_vector->rx.count == 1)
91281fd3
AD		 3558 napi->poll = &ixgbe_clean_rxonly;
3559 }
3560 }
f0848276
JB		 3561
3562 napi_enable(napi);
021230d4
AV		 3563 }
3564}
3565
3566static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3567{
3568 int q_idx;
3569 struct ixgbe_q_vector *q_vector;
3570 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3571
3572 /* legacy and MSI only use one vector */
3573 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3574 q_vectors = 1;
3575
3576 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3577 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3578 napi_disable(&q_vector->napi);
3579 }
3580}
3581
7a6b6f51 3582#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3583/*
3584 * ixgbe_configure_dcb - Configure DCB hardware
3585 * @adapter: ixgbe adapter struct
3586 *
3587 * This is called by the driver on open to configure the DCB hardware.
3588 * This is also called by the gennetlink interface when reconfiguring
3589 * the DCB state.
3590 */
3591static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3592{
3593 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3594 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3595
67ebd791
AD		 3596 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3597 if (hw->mac.type == ixgbe_mac_82598EB)
3598 netif_set_gso_max_size(adapter->netdev, 65536);
3599 return;
3600 }
3601
3602 if (hw->mac.type == ixgbe_mac_82598EB)
3603 netif_set_gso_max_size(adapter->netdev, 32768);
3604
2f90b865 3605
2f90b865 3606 /* Enable VLAN tag insert/strip */
f62bbb5e 3607 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3608
2f90b865 3609 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3610
3611 /* reconfigure the hardware */
6f70f6ac 3612 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3613#ifdef CONFIG_FCOE
3614 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3615 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3616#endif
3617 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3618 DCB_TX_CONFIG);
3619 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3620 DCB_RX_CONFIG);
3621 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3622 } else {
3623 struct net_device *dev = adapter->netdev;
3624
3625 if (adapter->ixgbe_ieee_ets)
3626 dev->dcbnl_ops->ieee_setets(dev,
3627 adapter->ixgbe_ieee_ets);
3628 if (adapter->ixgbe_ieee_pfc)
3629 dev->dcbnl_ops->ieee_setpfc(dev,
3630 adapter->ixgbe_ieee_pfc);
3631 }
8187cd48
JF		 3632
3633 /* Enable RSS Hash per TC */
3634 if (hw->mac.type != ixgbe_mac_82598EB) {
3635 int i;
3636 u32 reg = 0;
3637
3638 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3639 u8 msb = 0;
3640 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3641
3642 while (cnt >>= 1)
3643 msb++;
3644
3645 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3646 }
3647 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3648 }
2f90b865
AD		 3649}
3650
3651#endif
80605c65
JF		 3652
3653static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3654{
3655 int hdrm = 0;
3656 int num_tc = netdev_get_num_tc(adapter->netdev);
3657 struct ixgbe_hw *hw = &adapter->hw;
3658
3659 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3660 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3661 hdrm = 64 << adapter->fdir_pballoc;
3662
3663 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3664}
3665
e4911d57
AD		 3666static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3667{
3668 struct ixgbe_hw *hw = &adapter->hw;
3669 struct hlist_node *node, *node2;
3670 struct ixgbe_fdir_filter *filter;
3671
3672 spin_lock(&adapter->fdir_perfect_lock);
3673
3674 if (!hlist_empty(&adapter->fdir_filter_list))
3675 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3676
3677 hlist_for_each_entry_safe(filter, node, node2,
3678 &adapter->fdir_filter_list, fdir_node) {
3679 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3680 &filter->filter,
3681 filter->sw_idx,
3682 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3683 IXGBE_FDIR_DROP_QUEUE :
3684 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3685 }
3686
3687 spin_unlock(&adapter->fdir_perfect_lock);
3688}
3689
9a799d71
AK		 3690static void ixgbe_configure(struct ixgbe_adapter *adapter)
3691{
3692 struct net_device *netdev = adapter->netdev;
c4cf55e5 3693 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3694 int i;
3695
80605c65 3696 ixgbe_configure_pb(adapter);
7a6b6f51 3697#ifdef CONFIG_IXGBE_DCB
67ebd791 3698 ixgbe_configure_dcb(adapter);
2f90b865 3699#endif
9a799d71 3700
f62bbb5e
JG		 3701 ixgbe_set_rx_mode(netdev);
3702 ixgbe_restore_vlan(adapter);
3703
eacd73f7
YZ		 3704#ifdef IXGBE_FCOE
3705 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3706 ixgbe_configure_fcoe(adapter);
3707
3708#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3709 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3710 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3711 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3712 adapter->atr_sample_rate;
c4cf55e5 3713 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
e4911d57
AD		 3714 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3715 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3716 adapter->fdir_pballoc);
3717 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3718 }
933d41f1 3719 ixgbe_configure_virtualization(adapter);
c4cf55e5 3720
9a799d71
AK		 3721 ixgbe_configure_tx(adapter);
3722 ixgbe_configure_rx(adapter);
9a799d71
AK		 3723}
3724
e8e26350
PW		 3725static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3726{
3727 switch (hw->phy.type) {
3728 case ixgbe_phy_sfp_avago:
3729 case ixgbe_phy_sfp_ftl:
3730 case ixgbe_phy_sfp_intel:
3731 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3732 case ixgbe_phy_sfp_passive_tyco:
3733 case ixgbe_phy_sfp_passive_unknown:
3734 case ixgbe_phy_sfp_active_unknown:
3735 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3736 return true;
3737 default:
3738 return false;
3739 }
3740}
3741
0ecc061d 3742/**
e8e26350
PW		 3743 * ixgbe_sfp_link_config - set up SFP+ link
3744 * @adapter: pointer to private adapter struct
3745 **/
3746static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3747{
7086400d
AD		 3748 /*
3749 * We are assuming the worst case scenerio here, and that
3750 * is that an SFP was inserted/removed after the reset
3751 * but before SFP detection was enabled. As such the best
3752 * solution is to just start searching as soon as we start
3753 */
3754 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3755 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3756
7086400d 3757 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3758}
3759
3760/**
3761 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3762 * @hw: pointer to private hardware struct
3763 *
3764 * Returns 0 on success, negative on failure
3765 **/
e8e26350 3766static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3767{
3768 u32 autoneg;
8620a103 3769 bool negotiation, link_up = false;
0ecc061d
PWJ		 3770 u32 ret = IXGBE_ERR_LINK_SETUP;
3771
3772 if (hw->mac.ops.check_link)
3773 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3774
3775 if (ret)
3776 goto link_cfg_out;
3777
0b0c2b31
ET		 3778 autoneg = hw->phy.autoneg_advertised;
3779 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3780 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3781 &negotiation);
0ecc061d
PWJ		 3782 if (ret)
3783 goto link_cfg_out;
3784
8620a103
MC		 3785 if (hw->mac.ops.setup_link)
3786 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3787link_cfg_out:
3788 return ret;
3789}
3790
a34bcfff 3791static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3792{
9a799d71 3793 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3794 u32 gpie = 0;
9a799d71 3795
9b471446 3796 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3797 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3798 IXGBE_GPIE_OCD;
3799 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3800 /*
3801 * use EIAM to auto-mask when MSI-X interrupt is asserted
3802 * this saves a register write for every interrupt
3803 */
3804 switch (hw->mac.type) {
3805 case ixgbe_mac_82598EB:
3806 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3807 break;
9b471446 3808 case ixgbe_mac_82599EB:
b93a2226
DS		 3809 case ixgbe_mac_X540:
3810 default:
9b471446
JB		 3811 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3812 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3813 break;
3814 }
3815 } else {
021230d4
AV		 3816 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3817 * specifically only auto mask tx and rx interrupts */
3818 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3819 }
9a799d71 3820
a34bcfff
AD		 3821 /* XXX: to interrupt immediately for EICS writes, enable this */
3822 /* gpie |= IXGBE_GPIE_EIMEN; */
3823
3824 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3825 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3826 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3827 }
3828
a34bcfff
AD		 3829 /* Enable fan failure interrupt */
3830 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3831 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3832
2698b208 3833 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3834 gpie |= IXGBE_SDP1_GPIEN;
3835 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3836 }
a34bcfff
AD		 3837
3838 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3839}
3840
3841static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3842{
3843 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3844 int err;
a34bcfff
AD		 3845 u32 ctrl_ext;
3846
3847 ixgbe_get_hw_control(adapter);
3848 ixgbe_setup_gpie(adapter);
e8e26350 3849
9a799d71
AK		 3850 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3851 ixgbe_configure_msix(adapter);
3852 else
3853 ixgbe_configure_msi_and_legacy(adapter);
3854
c6ecf39a
DS		 3855 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3856 if (hw->mac.ops.enable_tx_laser &&
3857 ((hw->phy.multispeed_fiber) ||
9f911707 3858 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3859 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3860 hw->mac.ops.enable_tx_laser(hw);
3861
9a799d71 3862 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3863 ixgbe_napi_enable_all(adapter);
3864
73c4b7cd
AD		 3865 if (ixgbe_is_sfp(hw)) {
3866 ixgbe_sfp_link_config(adapter);
3867 } else {
3868 err = ixgbe_non_sfp_link_config(hw);
3869 if (err)
3870 e_err(probe, "link_config FAILED %d\n", err);
3871 }
3872
021230d4
AV		 3873 /* clear any pending interrupts, may auto mask */
3874 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3875 ixgbe_irq_enable(adapter, true, true);
9a799d71 3876
bf069c97
DS		 3877 /*
3878 * If this adapter has a fan, check to see if we had a failure
3879 * before we enabled the interrupt.
3880 */
3881 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3882 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3883 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3884 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3885 }
3886
1da100bb 3887 /* enable transmits */
477de6ed 3888 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3889
9a799d71
AK		 3890 /* bring the link up in the watchdog, this could race with our first
3891 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3892 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3893 adapter->link_check_timeout = jiffies;
7086400d 3894 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3895
3896 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3897 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3898 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3899 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3900
9a799d71
AK		 3901 return 0;
3902}
3903
d4f80882
AV		 3904void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3905{
3906 WARN_ON(in_interrupt());
7086400d
AD		 3907 /* put off any impending NetWatchDogTimeout */
3908 adapter->netdev->trans_start = jiffies;
3909
d4f80882 3910 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3911 usleep_range(1000, 2000);
d4f80882 3912 ixgbe_down(adapter);
5809a1ae
GR		 3913 /*
3914 * If SR-IOV enabled then wait a bit before bringing the adapter
3915 * back up to give the VFs time to respond to the reset. The
3916 * two second wait is based upon the watchdog timer cycle in
3917 * the VF driver.
3918 */
3919 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3920 msleep(2000);
d4f80882
AV		 3921 ixgbe_up(adapter);
3922 clear_bit(__IXGBE_RESETTING, &adapter->state);
3923}
3924
9a799d71
AK		 3925int ixgbe_up(struct ixgbe_adapter *adapter)
3926{
3927 /* hardware has been reset, we need to reload some things */
3928 ixgbe_configure(adapter);
3929
3930 return ixgbe_up_complete(adapter);
3931}
3932
3933void ixgbe_reset(struct ixgbe_adapter *adapter)
3934{
c44ade9e 3935 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3936 int err;
3937
7086400d
AD		 3938 /* lock SFP init bit to prevent race conditions with the watchdog */
3939 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3940 usleep_range(1000, 2000);
3941
3942 /* clear all SFP and link config related flags while holding SFP_INIT */
3943 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3944 IXGBE_FLAG2_SFP_NEEDS_RESET);
3945 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3946
8ca783ab 3947 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3948 switch (err) {
3949 case 0:
3950 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3951 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3952 break;
3953 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3954 e_dev_err("master disable timed out\n");
da4dd0f7 3955 break;
794caeb2
PWJ		 3956 case IXGBE_ERR_EEPROM_VERSION:
3957 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3958 e_dev_warn("This device is a pre-production adapter/LOM. "
3959 "Please be aware there may be issuesassociated with "
3960 "your hardware. If you are experiencing problems "
3961 "please contact your Intel or hardware "
3962 "representative who provided you with this "
3963 "hardware.\n");
794caeb2 3964 break;
da4dd0f7 3965 default:
849c4542 3966 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3967 }
9a799d71 3968
7086400d
AD		 3969 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3970
9a799d71 3971 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3972 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3973 IXGBE_RAH_AV);
9a799d71
AK		 3974}
3975
9a799d71
AK		 3976/**
3977 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3978 * @rx_ring: ring to free buffers from
3979 **/
b6ec895e 3980static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3981{
b6ec895e 3982 struct device *dev = rx_ring->dev;
9a799d71 3983 unsigned long size;
b6ec895e 3984 u16 i;
9a799d71 3985
84418e3b
AD		 3986 /* ring already cleared, nothing to do */
3987 if (!rx_ring->rx_buffer_info)
3988 return;
9a799d71 3989
84418e3b 3990 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3991 for (i = 0; i < rx_ring->count; i++) {
3992 struct ixgbe_rx_buffer *rx_buffer_info;
3993
3994 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3995 if (rx_buffer_info->dma) {
b6ec895e 3996 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3997 rx_ring->rx_buf_len,
1b507730 3998 DMA_FROM_DEVICE);
9a799d71
AK		 3999 rx_buffer_info->dma = 0;
4000 }
4001 if (rx_buffer_info->skb) {
f8212f97 4002 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4003 rx_buffer_info->skb = NULL;
f8212f97
AD		 4004 do {
4005 struct sk_buff *this = skb;
e8171aaa 4006 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 4007 dma_unmap_single(dev,
1b507730 4008 IXGBE_RSC_CB(this)->dma,
e8e9f696 4009 rx_ring->rx_buf_len,
1b507730 4010 DMA_FROM_DEVICE);
fd3686a8 4011 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 4012 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 4013 }
f8212f97
AD		 4014 skb = skb->prev;
4015 dev_kfree_skb(this);
4016 } while (skb);
9a799d71
AK		 4017 }
4018 if (!rx_buffer_info->page)
4019 continue;
4f57ca6e 4020 if (rx_buffer_info->page_dma) {
b6ec895e 4021 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4022 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4023 rx_buffer_info->page_dma = 0;
4024 }
9a799d71
AK		 4025 put_page(rx_buffer_info->page);
4026 rx_buffer_info->page = NULL;
762f4c57 4027 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4028 }
4029
4030 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4031 memset(rx_ring->rx_buffer_info, 0, size);
4032
4033 /* Zero out the descriptor ring */
4034 memset(rx_ring->desc, 0, rx_ring->size);
4035
4036 rx_ring->next_to_clean = 0;
4037 rx_ring->next_to_use = 0;
9a799d71
AK		 4038}
4039
4040/**
4041 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4042 * @tx_ring: ring to be cleaned
4043 **/
b6ec895e 4044static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4045{
4046 struct ixgbe_tx_buffer *tx_buffer_info;
4047 unsigned long size;
b6ec895e 4048 u16 i;
9a799d71 4049
84418e3b
AD		 4050 /* ring already cleared, nothing to do */
4051 if (!tx_ring->tx_buffer_info)
4052 return;
9a799d71 4053
84418e3b 4054 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4055 for (i = 0; i < tx_ring->count; i++) {
4056 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4057 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4058 }
4059
4060 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4061 memset(tx_ring->tx_buffer_info, 0, size);
4062
4063 /* Zero out the descriptor ring */
4064 memset(tx_ring->desc, 0, tx_ring->size);
4065
4066 tx_ring->next_to_use = 0;
4067 tx_ring->next_to_clean = 0;
9a799d71
AK		 4068}
4069
4070/**
021230d4 4071 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4072 * @adapter: board private structure
4073 **/
021230d4 4074static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4075{
4076 int i;
4077
021230d4 4078 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4079 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4080}
4081
4082/**
021230d4 4083 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4084 * @adapter: board private structure
4085 **/
021230d4 4086static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4087{
4088 int i;
4089
021230d4 4090 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4091 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4092}
4093
e4911d57
AD		 4094static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4095{
4096 struct hlist_node *node, *node2;
4097 struct ixgbe_fdir_filter *filter;
4098
4099 spin_lock(&adapter->fdir_perfect_lock);
4100
4101 hlist_for_each_entry_safe(filter, node, node2,
4102 &adapter->fdir_filter_list, fdir_node) {
4103 hlist_del(&filter->fdir_node);
4104 kfree(filter);
4105 }
4106 adapter->fdir_filter_count = 0;
4107
4108 spin_unlock(&adapter->fdir_perfect_lock);
4109}
4110
9a799d71
AK		 4111void ixgbe_down(struct ixgbe_adapter *adapter)
4112{
4113 struct net_device *netdev = adapter->netdev;
7f821875 4114 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4115 u32 rxctrl;
bf29ee6c 4116 int i;
b25ebfd2 4117 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4118
4119 /* signal that we are down to the interrupt handler */
4120 set_bit(__IXGBE_DOWN, &adapter->state);
4121
4122 /* disable receives */
7f821875
JB		 4123 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4124 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4125
2d39d576
YZ		 4126 /* disable all enabled rx queues */
4127 for (i = 0; i < adapter->num_rx_queues; i++)
4128 /* this call also flushes the previous write */
4129 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4130
032b4325 4131 usleep_range(10000, 20000);
9a799d71 4132
7f821875
JB		 4133 netif_tx_stop_all_queues(netdev);
4134
7086400d 4135 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4136 netif_carrier_off(netdev);
4137 netif_tx_disable(netdev);
4138
4139 ixgbe_irq_disable(adapter);
4140
4141 ixgbe_napi_disable_all(adapter);
4142
d034acf1
AD		 4143 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4144 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4145 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4146
4147 del_timer_sync(&adapter->service_timer);
4148
34cecbbf
AD		 4149 /* disable receive for all VFs and wait one second */
4150 if (adapter->num_vfs) {
4151 /* ping all the active vfs to let them know we are going down */
4152 ixgbe_ping_all_vfs(adapter);
4153
4154 /* Disable all VFTE/VFRE TX/RX */
4155 ixgbe_disable_tx_rx(adapter);
4156
4157 /* Mark all the VFs as inactive */
4158 for (i = 0 ; i < adapter->num_vfs; i++)
4159 adapter->vfinfo[i].clear_to_send = 0;
4160 }
4161
b25ebfd2
PW		 4162 /* Cleanup the affinity_hint CPU mask memory and callback */
4163 for (i = 0; i < num_q_vectors; i++) {
4164 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4165 /* clear the affinity_mask in the IRQ descriptor */
4166 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4167 /* release the CPU mask memory */
4168 free_cpumask_var(q_vector->affinity_mask);
4169 }
4170
7f821875
JB		 4171 /* disable transmits in the hardware now that interrupts are off */
4172 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4173 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4174 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4175 }
34cecbbf
AD		 4176
4177 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4178 switch (hw->mac.type) {
4179 case ixgbe_mac_82599EB:
b93a2226 4180 case ixgbe_mac_X540:
88512539 4181 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4182 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4183 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4184 break;
4185 default:
4186 break;
4187 }
7f821875 4188
6f4a0e45
PL		 4189 if (!pci_channel_offline(adapter->pdev))
4190 ixgbe_reset(adapter);
c6ecf39a
DS		 4191
4192 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4193 if (hw->mac.ops.disable_tx_laser &&
4194 ((hw->phy.multispeed_fiber) ||
9f911707 4195 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4196 (hw->mac.type == ixgbe_mac_82599EB))))
4197 hw->mac.ops.disable_tx_laser(hw);
4198
9a799d71
AK		 4199 ixgbe_clean_all_tx_rings(adapter);
4200 ixgbe_clean_all_rx_rings(adapter);
4201
5dd2d332 4202#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4203 /* since we reset the hardware DCA settings were cleared */
e35ec126 4204 ixgbe_setup_dca(adapter);
96b0e0f6 4205#endif
9a799d71
AK		 4206}
4207
9a799d71 4208/**
021230d4
AV		 4209 * ixgbe_poll - NAPI Rx polling callback
4210 * @napi: structure for representing this polling device
4211 * @budget: how many packets driver is allowed to clean
4212 *
4213 * This function is used for legacy and MSI, NAPI mode
9a799d71 4214 **/
021230d4 4215static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4216{
9a1a69ad 4217 struct ixgbe_q_vector *q_vector =
e8e9f696 4218 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4219 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4220 int tx_clean_complete, work_done = 0;
9a799d71 4221
5dd2d332 4222#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4223 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4224 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4225#endif
4226
4a0b9ca0
PW		 4227 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4228 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4229
9a1a69ad 4230 if (!tx_clean_complete)
d2c7ddd6
DM		 4231 work_done = budget;
4232
53e52c72
DM		 4233 /* If budget not fully consumed, exit the polling mode */
4234 if (work_done < budget) {
288379f0 4235 napi_complete(napi);
f7554a2b 4236 if (adapter->rx_itr_setting & 1)
bd198058 4237 ixgbe_set_itr(q_vector);
d4f80882 4238 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4239 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4240 }
9a799d71
AK		 4241 return work_done;
4242}
4243
4244/**
4245 * ixgbe_tx_timeout - Respond to a Tx Hang
4246 * @netdev: network interface device structure
4247 **/
4248static void ixgbe_tx_timeout(struct net_device *netdev)
4249{
4250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4251
4252 /* Do the reset outside of interrupt context */
c83c6cbd 4253 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4254}
4255
4df10466
JB		 4256/**
4257 * ixgbe_set_rss_queues: Allocate queues for RSS
4258 * @adapter: board private structure to initialize
4259 *
4260 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4261 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4262 *
4263 **/
bc97114d
PWJ		 4264static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4265{
4266 bool ret = false;
0cefafad 4267 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4268
4269 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4270 f->mask = 0xF;
4271 adapter->num_rx_queues = f->indices;
4272 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4273 ret = true;
4274 } else {
bc97114d 4275 ret = false;
b9804972
JB		 4276 }
4277
bc97114d
PWJ		 4278 return ret;
4279}
4280
c4cf55e5
PWJ		 4281/**
4282 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4283 * @adapter: board private structure to initialize
4284 *
4285 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4286 * to the original CPU that initiated the Tx session. This runs in addition
4287 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4288 * Rx load across CPUs using RSS.
4289 *
4290 **/
e8e9f696 4291static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4292{
4293 bool ret = false;
4294 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4295
4296 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4297 f_fdir->mask = 0;
4298
4299 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4300 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4301 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4302 adapter->num_tx_queues = f_fdir->indices;
4303 adapter->num_rx_queues = f_fdir->indices;
4304 ret = true;
4305 } else {
4306 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4307 }
4308 return ret;
4309}
4310
0331a832
YZ		 4311#ifdef IXGBE_FCOE
4312/**
4313 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4314 * @adapter: board private structure to initialize
4315 *
4316 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4317 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4318 * rx queues out of the max number of rx queues, instead, it is used as the
4319 * index of the first rx queue used by FCoE.
4320 *
4321 **/
4322static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4323{
0331a832
YZ		 4324 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4325
e5b64635
JF		 4326 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4327 return false;
4328
e901acd6 4329 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4330
e901acd6
JF		 4331 adapter->num_rx_queues = 1;
4332 adapter->num_tx_queues = 1;
e5b64635 4333
e901acd6
JF		 4334 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4335 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4336 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4337 ixgbe_set_fdir_queues(adapter);
4338 else
4339 ixgbe_set_rss_queues(adapter);
e5b64635 4340 }
03ecf91a 4341
e901acd6
JF		 4342 /* adding FCoE rx rings to the end */
4343 f->mask = adapter->num_rx_queues;
4344 adapter->num_rx_queues += f->indices;
4345 adapter->num_tx_queues += f->indices;
0331a832 4346
e5b64635
JF		 4347 return true;
4348}
4349#endif /* IXGBE_FCOE */
4350
e901acd6
JF		 4351/* Artificial max queue cap per traffic class in DCB mode */
4352#define DCB_QUEUE_CAP 8
4353
e5b64635
JF		 4354#ifdef CONFIG_IXGBE_DCB
4355static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4356{
e901acd6
JF		 4357 int per_tc_q, q, i, offset = 0;
4358 struct net_device *dev = adapter->netdev;
4359 int tcs = netdev_get_num_tc(dev);
e5b64635 4360
e901acd6
JF		 4361 if (!tcs)
4362 return false;
e5b64635 4363
e901acd6
JF		 4364 /* Map queue offset and counts onto allocated tx queues */
4365 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4366 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4367
8b1c0b24 4368 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4369 netdev_set_prio_tc_map(dev, i, i);
4370 netdev_set_tc_queue(dev, i, q, offset);
4371 offset += q;
0331a832
YZ		 4372 }
4373
e901acd6
JF		 4374 adapter->num_tx_queues = q * tcs;
4375 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4376
4377#ifdef IXGBE_FCOE
e901acd6
JF		 4378 /* FCoE enabled queues require special configuration indexed
4379 * by feature specific indices and mask. Here we map FCoE
4380 * indices onto the DCB queue pairs allowing FCoE to own
4381 * configuration later.
e5b64635 4382 */
e901acd6
JF		 4383 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4384 int tc;
4385 struct ixgbe_ring_feature *f =
4386 &adapter->ring_feature[RING_F_FCOE];
4387
4388 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4389 f->indices = dev->tc_to_txq[tc].count;
4390 f->mask = dev->tc_to_txq[tc].offset;
4391 }
e5b64635
JF		 4392#endif
4393
e901acd6 4394 return true;
0331a832 4395}
e5b64635 4396#endif
0331a832 4397
1cdd1ec8
GR		 4398/**
4399 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4400 * @adapter: board private structure to initialize
4401 *
4402 * IOV doesn't actually use anything, so just NAK the
4403 * request for now and let the other queue routines
4404 * figure out what to do.
4405 */
4406static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4407{
4408 return false;
4409}
4410
4df10466 4411/*
25985edc 4412 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4413 * @adapter: board private structure to initialize
4414 *
4415 * This is the top level queue allocation routine. The order here is very
4416 * important, starting with the "most" number of features turned on at once,
4417 * and ending with the smallest set of features. This way large combinations
4418 * can be allocated if they're turned on, and smaller combinations are the
4419 * fallthrough conditions.
4420 *
4421 **/
847f53ff 4422static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4423{
1cdd1ec8
GR		 4424 /* Start with base case */
4425 adapter->num_rx_queues = 1;
4426 adapter->num_tx_queues = 1;
4427 adapter->num_rx_pools = adapter->num_rx_queues;
4428 adapter->num_rx_queues_per_pool = 1;
4429
4430 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4431 goto done;
1cdd1ec8 4432
bc97114d
PWJ		 4433#ifdef CONFIG_IXGBE_DCB
4434 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4435 goto done;
bc97114d
PWJ		 4436
4437#endif
e5b64635
JF		 4438#ifdef IXGBE_FCOE
4439 if (ixgbe_set_fcoe_queues(adapter))
4440 goto done;
4441
4442#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4443 if (ixgbe_set_fdir_queues(adapter))
4444 goto done;
4445
bc97114d 4446 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4447 goto done;
4448
4449 /* fallback to base case */
4450 adapter->num_rx_queues = 1;
4451 adapter->num_tx_queues = 1;
4452
4453done:
847f53ff 4454 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4455 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4456 return netif_set_real_num_rx_queues(adapter->netdev,
4457 adapter->num_rx_queues);
b9804972
JB		 4458}
4459
021230d4 4460static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4461 int vectors)
021230d4
AV		 4462{
4463 int err, vector_threshold;
4464
4465 /* We'll want at least 3 (vector_threshold):
4466 * 1) TxQ[0] Cleanup
4467 * 2) RxQ[0] Cleanup
4468 * 3) Other (Link Status Change, etc.)
4469 * 4) TCP Timer (optional)
4470 */
4471 vector_threshold = MIN_MSIX_COUNT;
4472
4473 /* The more we get, the more we will assign to Tx/Rx Cleanup
4474 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4475 * Right now, we simply care about how many we'll get; we'll
4476 * set them up later while requesting irq's.
4477 */
4478 while (vectors >= vector_threshold) {
4479 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4480 vectors);
021230d4
AV		 4481 if (!err) /* Success in acquiring all requested vectors. */
4482 break;
4483 else if (err < 0)
4484 vectors = 0; /* Nasty failure, quit now */
4485 else /* err == number of vectors we should try again with */
4486 vectors = err;
4487 }
4488
4489 if (vectors < vector_threshold) {
4490 /* Can't allocate enough MSI-X interrupts? Oh well.
4491 * This just means we'll go with either a single MSI
4492 * vector or fall back to legacy interrupts.
4493 */
849c4542
ET		 4494 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4495 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4496 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4497 kfree(adapter->msix_entries);
4498 adapter->msix_entries = NULL;
021230d4
AV		 4499 } else {
4500 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4501 /*
4502 * Adjust for only the vectors we'll use, which is minimum
4503 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4504 * vectors we were allocated.
4505 */
4506 adapter->num_msix_vectors = min(vectors,
e8e9f696 4507 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4508 }
4509}
4510
021230d4 4511/**
bc97114d 4512 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4513 * @adapter: board private structure to initialize
4514 *
bc97114d
PWJ		 4515 * Cache the descriptor ring offsets for RSS to the assigned rings.
4516 *
021230d4 4517 **/
bc97114d 4518static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4519{
bc97114d 4520 int i;
bc97114d 4521
9d6b758f
AD		 4522 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4523 return false;
bc97114d 4524
9d6b758f
AD		 4525 for (i = 0; i < adapter->num_rx_queues; i++)
4526 adapter->rx_ring[i]->reg_idx = i;
4527 for (i = 0; i < adapter->num_tx_queues; i++)
4528 adapter->tx_ring[i]->reg_idx = i;
4529
4530 return true;
bc97114d
PWJ		 4531}
4532
4533#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4534
4535/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4536static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4537 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4538{
4539 struct net_device *dev = adapter->netdev;
4540 struct ixgbe_hw *hw = &adapter->hw;
4541 u8 num_tcs = netdev_get_num_tc(dev);
4542
4543 *tx = 0;
4544 *rx = 0;
4545
4546 switch (hw->mac.type) {
4547 case ixgbe_mac_82598EB:
aba70d5e
JF		 4548 *tx = tc << 2;
4549 *rx = tc << 3;
e5b64635
JF		 4550 break;
4551 case ixgbe_mac_82599EB:
4552 case ixgbe_mac_X540:
4553 if (num_tcs == 8) {
4554 if (tc < 3) {
4555 *tx = tc << 5;
4556 *rx = tc << 4;
4557 } else if (tc < 5) {
4558 *tx = ((tc + 2) << 4);
4559 *rx = tc << 4;
4560 } else if (tc < num_tcs) {
4561 *tx = ((tc + 8) << 3);
4562 *rx = tc << 4;
4563 }
4564 } else if (num_tcs == 4) {
4565 *rx = tc << 5;
4566 switch (tc) {
4567 case 0:
4568 *tx = 0;
4569 break;
4570 case 1:
4571 *tx = 64;
4572 break;
4573 case 2:
4574 *tx = 96;
4575 break;
4576 case 3:
4577 *tx = 112;
4578 break;
4579 default:
4580 break;
4581 }
4582 }
4583 break;
4584 default:
4585 break;
4586 }
4587}
4588
bc97114d
PWJ		 4589/**
4590 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4591 * @adapter: board private structure to initialize
4592 *
4593 * Cache the descriptor ring offsets for DCB to the assigned rings.
4594 *
4595 **/
4596static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4597{
e5b64635
JF		 4598 struct net_device *dev = adapter->netdev;
4599 int i, j, k;
4600 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4601
8b1c0b24 4602 if (!num_tcs)
bd508178 4603 return false;
f92ef202 4604
e5b64635
JF		 4605 for (i = 0, k = 0; i < num_tcs; i++) {
4606 unsigned int tx_s, rx_s;
4607 u16 count = dev->tc_to_txq[i].count;
4608
4609 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4610 for (j = 0; j < count; j++, k++) {
4611 adapter->tx_ring[k]->reg_idx = tx_s + j;
4612 adapter->rx_ring[k]->reg_idx = rx_s + j;
4613 adapter->tx_ring[k]->dcb_tc = i;
4614 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4615 }
021230d4 4616 }
e5b64635
JF		 4617
4618 return true;
bc97114d
PWJ		 4619}
4620#endif
4621
c4cf55e5
PWJ		 4622/**
4623 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4624 * @adapter: board private structure to initialize
4625 *
4626 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4627 *
4628 **/
e8e9f696 4629static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4630{
4631 int i;
4632 bool ret = false;
4633
03ecf91a
AD		 4634 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4635 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4636 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4637 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4638 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4639 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4640 ret = true;
4641 }
4642
4643 return ret;
4644}
4645
0331a832
YZ		 4646#ifdef IXGBE_FCOE
4647/**
4648 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4649 * @adapter: board private structure to initialize
4650 *
4651 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4652 *
4653 */
4654static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4655{
0331a832 4656 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4657 int i;
4658 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4659
4660 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4661 return false;
0331a832 4662
bf29ee6c 4663 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4664 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4665 ixgbe_cache_ring_fdir(adapter);
4666 else
4667 ixgbe_cache_ring_rss(adapter);
8faa2a78 4668
bf29ee6c
AD		 4669 fcoe_rx_i = f->mask;
4670 fcoe_tx_i = f->mask;
0331a832 4671 }
bf29ee6c
AD		 4672 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4673 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4674 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4675 }
4676 return true;
0331a832
YZ		 4677}
4678
4679#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4680/**
4681 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4682 * @adapter: board private structure to initialize
4683 *
4684 * SR-IOV doesn't use any descriptor rings but changes the default if
4685 * no other mapping is used.
4686 *
4687 */
4688static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4689{
4a0b9ca0
PW		 4690 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4691 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4692 if (adapter->num_vfs)
4693 return true;
4694 else
4695 return false;
4696}
4697
bc97114d
PWJ		 4698/**
4699 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4700 * @adapter: board private structure to initialize
4701 *
4702 * Once we know the feature-set enabled for the device, we'll cache
4703 * the register offset the descriptor ring is assigned to.
4704 *
4705 * Note, the order the various feature calls is important. It must start with
4706 * the "most" features enabled at the same time, then trickle down to the
4707 * least amount of features turned on at once.
4708 **/
4709static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4710{
4711 /* start with default case */
4a0b9ca0
PW		 4712 adapter->rx_ring[0]->reg_idx = 0;
4713 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4714
1cdd1ec8
GR		 4715 if (ixgbe_cache_ring_sriov(adapter))
4716 return;
4717
e5b64635
JF		 4718#ifdef CONFIG_IXGBE_DCB
4719 if (ixgbe_cache_ring_dcb(adapter))
4720 return;
4721#endif
4722
0331a832
YZ		 4723#ifdef IXGBE_FCOE
4724 if (ixgbe_cache_ring_fcoe(adapter))
4725 return;
0331a832 4726#endif /* IXGBE_FCOE */
bc97114d 4727
c4cf55e5
PWJ		 4728 if (ixgbe_cache_ring_fdir(adapter))
4729 return;
4730
bc97114d
PWJ		 4731 if (ixgbe_cache_ring_rss(adapter))
4732 return;
021230d4
AV		 4733}
4734
9a799d71
AK		 4735/**
4736 * ixgbe_alloc_queues - Allocate memory for all rings
4737 * @adapter: board private structure to initialize
4738 *
4739 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4740 * number of queues at compile-time. The polling_netdev array is
4741 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4742 **/
2f90b865 4743static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4744{
e2ddeba9 4745 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4746
e2ddeba9
ED		 4747 if (nid < 0 || !node_online(nid))
4748 nid = first_online_node;
4749
4750 for (; tx < adapter->num_tx_queues; tx++) {
4751 struct ixgbe_ring *ring;
4752
4753 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4754 if (!ring)
e2ddeba9 4755 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4756 if (!ring)
e2ddeba9 4757 goto err_allocation;
4a0b9ca0 4758 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4759 ring->queue_index = tx;
4760 ring->numa_node = nid;
b6ec895e 4761 ring->dev = &adapter->pdev->dev;
fc77dc3c 4762 ring->netdev = adapter->netdev;
4a0b9ca0 4763
e2ddeba9 4764 adapter->tx_ring[tx] = ring;
021230d4 4765 }
b9804972 4766
e2ddeba9
ED		 4767 for (; rx < adapter->num_rx_queues; rx++) {
4768 struct ixgbe_ring *ring;
4a0b9ca0 4769
e2ddeba9 4770 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4771 if (!ring)
e2ddeba9 4772 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4773 if (!ring)
e2ddeba9
ED		 4774 goto err_allocation;
4775 ring->count = adapter->rx_ring_count;
4776 ring->queue_index = rx;
4777 ring->numa_node = nid;
b6ec895e 4778 ring->dev = &adapter->pdev->dev;
fc77dc3c 4779 ring->netdev = adapter->netdev;
4a0b9ca0 4780
e2ddeba9 4781 adapter->rx_ring[rx] = ring;
021230d4
AV		 4782 }
4783
4784 ixgbe_cache_ring_register(adapter);
4785
4786 return 0;
4787
e2ddeba9
ED		 4788err_allocation:
4789 while (tx)
4790 kfree(adapter->tx_ring[--tx]);
4791
4792 while (rx)
4793 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4794 return -ENOMEM;
4795}
4796
4797/**
4798 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4799 * @adapter: board private structure to initialize
4800 *
4801 * Attempt to configure the interrupts using the best available
4802 * capabilities of the hardware and the kernel.
4803 **/
feea6a57 4804static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4805{
8be0e467 4806 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4807 int err = 0;
4808 int vector, v_budget;
4809
4810 /*
4811 * It's easy to be greedy for MSI-X vectors, but it really
4812 * doesn't do us much good if we have a lot more vectors
4813 * than CPU's. So let's be conservative and only ask for
342bde1b 4814 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4815 */
4816 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4817 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4818
4819 /*
4820 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4821 * hw.mac->max_msix_vectors vectors. With features
4822 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4823 * descriptor queues supported by our device. Thus, we cap it off in
4824 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4825 */
8be0e467 4826 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4827
4828 /* A failure in MSI-X entry allocation isn't fatal, but it does
4829 * mean we disable MSI-X capabilities of the adapter. */
4830 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4831 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4832 if (adapter->msix_entries) {
4833 for (vector = 0; vector < v_budget; vector++)
4834 adapter->msix_entries[vector].entry = vector;
021230d4 4835
7a921c93 4836 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4837
7a921c93
AD		 4838 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4839 goto out;
4840 }
26d27844 4841
7a921c93
AD		 4842 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4843 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4844 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4845 e_err(probe,
03ecf91a 4846 "ATR is not supported while multiple "
45b9f509
AD		 4847 "queues are disabled. Disabling Flow Director\n");
4848 }
c4cf55e5 4849 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4850 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4851 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4852 ixgbe_disable_sriov(adapter);
4853
847f53ff
BH		 4854 err = ixgbe_set_num_queues(adapter);
4855 if (err)
4856 return err;
021230d4 4857
021230d4
AV		 4858 err = pci_enable_msi(adapter->pdev);
4859 if (!err) {
4860 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4861 } else {
849c4542
ET		 4862 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4863 "Unable to allocate MSI interrupt, "
4864 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4865 /* reset err */
4866 err = 0;
4867 }
4868
4869out:
021230d4
AV		 4870 return err;
4871}
4872
7a921c93
AD		 4873/**
4874 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4875 * @adapter: board private structure to initialize
4876 *
4877 * We allocate one q_vector per queue interrupt. If allocation fails we
4878 * return -ENOMEM.
4879 **/
4880static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4881{
4882 int q_idx, num_q_vectors;
4883 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4884 int (*poll)(struct napi_struct *, int);
4885
4886 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4887 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4888 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4889 } else {
4890 num_q_vectors = 1;
7a921c93
AD		 4891 poll = &ixgbe_poll;
4892 }
4893
4894 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4895 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4896 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4897 if (!q_vector)
4898 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4899 GFP_KERNEL);
7a921c93
AD		 4900 if (!q_vector)
4901 goto err_out;
4902 q_vector->adapter = adapter;
08c8833b 4903 if (q_vector->tx.count && !q_vector->rx.count)
f7554a2b
NS		 4904 q_vector->eitr = adapter->tx_eitr_param;
4905 else
4906 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4907 q_vector->v_idx = q_idx;
91281fd3 4908 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4909 adapter->q_vector[q_idx] = q_vector;
4910 }
4911
4912 return 0;
4913
4914err_out:
4915 while (q_idx) {
4916 q_idx--;
4917 q_vector = adapter->q_vector[q_idx];
4918 netif_napi_del(&q_vector->napi);
4919 kfree(q_vector);
4920 adapter->q_vector[q_idx] = NULL;
4921 }
4922 return -ENOMEM;
4923}
4924
4925/**
4926 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4927 * @adapter: board private structure to initialize
4928 *
4929 * This function frees the memory allocated to the q_vectors. In addition if
4930 * NAPI is enabled it will delete any references to the NAPI struct prior
4931 * to freeing the q_vector.
4932 **/
4933static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4934{
4935 int q_idx, num_q_vectors;
7a921c93 4936
91281fd3 4937 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4938 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4939 else
7a921c93 4940 num_q_vectors = 1;
7a921c93
AD		 4941
4942 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4943 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4944 adapter->q_vector[q_idx] = NULL;
91281fd3 4945 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4946 kfree(q_vector);
4947 }
4948}
4949
7b25cdba 4950static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4951{
4952 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4953 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4954 pci_disable_msix(adapter->pdev);
4955 kfree(adapter->msix_entries);
4956 adapter->msix_entries = NULL;
4957 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4958 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4959 pci_disable_msi(adapter->pdev);
4960 }
021230d4
AV		 4961}
4962
4963/**
4964 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4965 * @adapter: board private structure to initialize
4966 *
4967 * We determine which interrupt scheme to use based on...
4968 * - Kernel support (MSI, MSI-X)
4969 * - which can be user-defined (via MODULE_PARAM)
4970 * - Hardware queue count (num_*_queues)
4971 * - defined by miscellaneous hardware support/features (RSS, etc.)
4972 **/
2f90b865 4973int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4974{
4975 int err;
4976
4977 /* Number of supported queues */
847f53ff
BH		 4978 err = ixgbe_set_num_queues(adapter);
4979 if (err)
4980 return err;
021230d4 4981
021230d4
AV		 4982 err = ixgbe_set_interrupt_capability(adapter);
4983 if (err) {
849c4542 4984 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4985 goto err_set_interrupt;
9a799d71
AK		 4986 }
4987
7a921c93
AD		 4988 err = ixgbe_alloc_q_vectors(adapter);
4989 if (err) {
849c4542 4990 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4991 goto err_alloc_q_vectors;
4992 }
4993
4994 err = ixgbe_alloc_queues(adapter);
4995 if (err) {
849c4542 4996 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4997 goto err_alloc_queues;
4998 }
4999
849c4542 5000 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5001 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5002 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5003
5004 set_bit(__IXGBE_DOWN, &adapter->state);
5005
9a799d71 5006 return 0;
021230d4 5007
7a921c93
AD		 5008err_alloc_queues:
5009 ixgbe_free_q_vectors(adapter);
5010err_alloc_q_vectors:
5011 ixgbe_reset_interrupt_capability(adapter);
021230d4 5012err_set_interrupt:
7a921c93
AD		 5013 return err;
5014}
5015
5016/**
5017 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5018 * @adapter: board private structure to clear interrupt scheme on
5019 *
5020 * We go through and clear interrupt specific resources and reset the structure
5021 * to pre-load conditions
5022 **/
5023void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5024{
4a0b9ca0
PW		 5025 int i;
5026
5027 for (i = 0; i < adapter->num_tx_queues; i++) {
5028 kfree(adapter->tx_ring[i]);
5029 adapter->tx_ring[i] = NULL;
5030 }
5031 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5032 struct ixgbe_ring *ring = adapter->rx_ring[i];
5033
5034 /* ixgbe_get_stats64() might access this ring, we must wait
5035 * a grace period before freeing it.
5036 */
bcec8b65 5037 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 5038 adapter->rx_ring[i] = NULL;
5039 }
7a921c93 5040
b8eb3a10
DS		 5041 adapter->num_tx_queues = 0;
5042 adapter->num_rx_queues = 0;
5043
7a921c93
AD		 5044 ixgbe_free_q_vectors(adapter);
5045 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5046}
5047
5048/**
5049 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5050 * @adapter: board private structure to initialize
5051 *
5052 * ixgbe_sw_init initializes the Adapter private data structure.
5053 * Fields are initialized based on PCI device information and
5054 * OS network device settings (MTU size).
5055 **/
5056static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5057{
5058 struct ixgbe_hw *hw = &adapter->hw;
5059 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5060 struct net_device *dev = adapter->netdev;
021230d4 5061 unsigned int rss;
7a6b6f51 5062#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5063 int j;
5064 struct tc_configuration *tc;
5065#endif
16b61beb 5066 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5067
c44ade9e
JB		 5068 /* PCI config space info */
5069
5070 hw->vendor_id = pdev->vendor;
5071 hw->device_id = pdev->device;
5072 hw->revision_id = pdev->revision;
5073 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5074 hw->subsystem_device_id = pdev->subsystem_device;
5075
021230d4
AV		 5076 /* Set capability flags */
5077 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5078 adapter->ring_feature[RING_F_RSS].indices = rss;
5079 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5080 switch (hw->mac.type) {
5081 case ixgbe_mac_82598EB:
bf069c97
DS		 5082 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5083 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5084 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5085 break;
5086 case ixgbe_mac_82599EB:
b93a2226 5087 case ixgbe_mac_X540:
e8e26350 5088 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5089 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5090 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5091 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5092 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5093 /* Flow Director hash filters enabled */
5094 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5095 adapter->atr_sample_rate = 20;
c4cf55e5 5096 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5097 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5098 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5099#ifdef IXGBE_FCOE
0d551589
YZ		 5100 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5101 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5102 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5103#ifdef CONFIG_IXGBE_DCB
6ee16520 5104 /* Default traffic class to use for FCoE */
56075a98 5105 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5106#endif
eacd73f7 5107#endif /* IXGBE_FCOE */
bd508178
AD		 5108 break;
5109 default:
5110 break;
f8212f97 5111 }
2f90b865 5112
1fc5f038
AD		 5113 /* n-tuple support exists, always init our spinlock */
5114 spin_lock_init(&adapter->fdir_perfect_lock);
5115
7a6b6f51 5116#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5117 /* Configure DCB traffic classes */
5118 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5119 tc = &adapter->dcb_cfg.tc_config[j];
5120 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5121 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5122 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5123 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5124 tc->dcb_pfc = pfc_disabled;
5125 }
5126 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5127 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5128 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5129 adapter->dcb_set_bitmap = 0x00;
3032309b 5130 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5131 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5132 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5133
5134#endif
9a799d71
AK		 5135
5136 /* default flow control settings */
cd7664f6 5137 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5138 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5139#ifdef CONFIG_DCB
5140 adapter->last_lfc_mode = hw->fc.current_mode;
5141#endif
16b61beb
JF		 5142 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5143 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5144 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5145 hw->fc.send_xon = true;
71fd570b 5146 hw->fc.disable_fc_autoneg = false;
9a799d71 5147
30efa5a3 5148 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5149 adapter->rx_itr_setting = 1;
5150 adapter->rx_eitr_param = 20000;
5151 adapter->tx_itr_setting = 1;
5152 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5153
5154 /* set defaults for eitr in MegaBytes */
5155 adapter->eitr_low = 10;
5156 adapter->eitr_high = 20;
5157
5158 /* set default ring sizes */
5159 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5160 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5161
bd198058
AD		 5162 /* set default work limits */
5163 adapter->tx_work_limit = adapter->tx_ring_count;
5164
9a799d71 5165 /* initialize eeprom parameters */
c44ade9e 5166 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5167 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5168 return -EIO;
5169 }
5170
021230d4 5171 /* enable rx csum by default */
9a799d71
AK		 5172 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5173
1a6c14a2
JB		 5174 /* get assigned NUMA node */
5175 adapter->node = dev_to_node(&pdev->dev);
5176
9a799d71
AK		 5177 set_bit(__IXGBE_DOWN, &adapter->state);
5178
5179 return 0;
5180}
5181
5182/**
5183 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5184 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5185 *
5186 * Return 0 on success, negative on failure
5187 **/
b6ec895e 5188int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5189{
b6ec895e 5190 struct device *dev = tx_ring->dev;
9a799d71
AK		 5191 int size;
5192
3a581073 5193 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5194 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5195 if (!tx_ring->tx_buffer_info)
89bf67f1 5196 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5197 if (!tx_ring->tx_buffer_info)
5198 goto err;
9a799d71
AK		 5199
5200 /* round up to nearest 4K */
12207e49 5201 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5202 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5203
b6ec895e 5204 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5205 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5206 if (!tx_ring->desc)
5207 goto err;
9a799d71 5208
3a581073
JB		 5209 tx_ring->next_to_use = 0;
5210 tx_ring->next_to_clean = 0;
9a799d71 5211 return 0;
e01c31a5
JB		 5212
5213err:
5214 vfree(tx_ring->tx_buffer_info);
5215 tx_ring->tx_buffer_info = NULL;
b6ec895e 5216 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5217 return -ENOMEM;
9a799d71
AK		 5218}
5219
69888674
AD		 5220/**
5221 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5222 * @adapter: board private structure
5223 *
5224 * If this function returns with an error, then it's possible one or
5225 * more of the rings is populated (while the rest are not). It is the
5226 * callers duty to clean those orphaned rings.
5227 *
5228 * Return 0 on success, negative on failure
5229 **/
5230static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5231{
5232 int i, err = 0;
5233
5234 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5235 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5236 if (!err)
5237 continue;
396e799c 5238 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5239 break;
5240 }
5241
5242 return err;
5243}
5244
9a799d71
AK		 5245/**
5246 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5247 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5248 *
5249 * Returns 0 on success, negative on failure
5250 **/
b6ec895e 5251int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5252{
b6ec895e 5253 struct device *dev = rx_ring->dev;
021230d4 5254 int size;
9a799d71 5255
3a581073 5256 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5257 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5258 if (!rx_ring->rx_buffer_info)
89bf67f1 5259 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5260 if (!rx_ring->rx_buffer_info)
5261 goto err;
9a799d71 5262
9a799d71 5263 /* Round up to nearest 4K */
3a581073
JB		 5264 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5265 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5266
b6ec895e 5267 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5268 &rx_ring->dma, GFP_KERNEL);
9a799d71 5269
b6ec895e
AD		 5270 if (!rx_ring->desc)
5271 goto err;
9a799d71 5272
3a581073
JB		 5273 rx_ring->next_to_clean = 0;
5274 rx_ring->next_to_use = 0;
9a799d71
AK		 5275
5276 return 0;
b6ec895e
AD		 5277err:
5278 vfree(rx_ring->rx_buffer_info);
5279 rx_ring->rx_buffer_info = NULL;
5280 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5281 return -ENOMEM;
9a799d71
AK		 5282}
5283
69888674
AD		 5284/**
5285 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5286 * @adapter: board private structure
5287 *
5288 * If this function returns with an error, then it's possible one or
5289 * more of the rings is populated (while the rest are not). It is the
5290 * callers duty to clean those orphaned rings.
5291 *
5292 * Return 0 on success, negative on failure
5293 **/
69888674
AD		 5294static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5295{
5296 int i, err = 0;
5297
5298 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5299 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5300 if (!err)
5301 continue;
396e799c 5302 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5303 break;
5304 }
5305
5306 return err;
5307}
5308
9a799d71
AK		 5309/**
5310 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5311 * @tx_ring: Tx descriptor ring for a specific queue
5312 *
5313 * Free all transmit software resources
5314 **/
b6ec895e 5315void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5316{
b6ec895e 5317 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5318
5319 vfree(tx_ring->tx_buffer_info);
5320 tx_ring->tx_buffer_info = NULL;
5321
b6ec895e
AD		 5322 /* if not set, then don't free */
5323 if (!tx_ring->desc)
5324 return;
5325
5326 dma_free_coherent(tx_ring->dev, tx_ring->size,
5327 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5328
5329 tx_ring->desc = NULL;
5330}
5331
5332/**
5333 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5334 * @adapter: board private structure
5335 *
5336 * Free all transmit software resources
5337 **/
5338static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5339{
5340 int i;
5341
5342 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5343 if (adapter->tx_ring[i]->desc)
b6ec895e 5344 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5345}
5346
5347/**
b4617240 5348 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5349 * @rx_ring: ring to clean the resources from
5350 *
5351 * Free all receive software resources
5352 **/
b6ec895e 5353void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5354{
b6ec895e 5355 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5356
5357 vfree(rx_ring->rx_buffer_info);
5358 rx_ring->rx_buffer_info = NULL;
5359
b6ec895e
AD		 5360 /* if not set, then don't free */
5361 if (!rx_ring->desc)
5362 return;
5363
5364 dma_free_coherent(rx_ring->dev, rx_ring->size,
5365 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5366
5367 rx_ring->desc = NULL;
5368}
5369
5370/**
5371 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5372 * @adapter: board private structure
5373 *
5374 * Free all receive software resources
5375 **/
5376static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5377{
5378 int i;
5379
5380 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5381 if (adapter->rx_ring[i]->desc)
b6ec895e 5382 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5383}
5384
9a799d71
AK		 5385/**
5386 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5387 * @netdev: network interface device structure
5388 * @new_mtu: new value for maximum frame size
5389 *
5390 * Returns 0 on success, negative on failure
5391 **/
5392static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5393{
5394 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5395 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5396 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5397
42c783c5 5398 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5399 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5400 hw->mac.type != ixgbe_mac_X540) {
5401 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5402 return -EINVAL;
5403 } else {
5404 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5405 return -EINVAL;
5406 }
9a799d71 5407
396e799c 5408 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5409 /* must set new MTU before calling down or up */
9a799d71
AK		 5410 netdev->mtu = new_mtu;
5411
16b61beb
JF		 5412 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5413 hw->fc.low_water = FC_LOW_WATER(max_frame);
5414
d4f80882
AV		 5415 if (netif_running(netdev))
5416 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5417
5418 return 0;
5419}
5420
5421/**
5422 * ixgbe_open - Called when a network interface is made active
5423 * @netdev: network interface device structure
5424 *
5425 * Returns 0 on success, negative value on failure
5426 *
5427 * The open entry point is called when a network interface is made
5428 * active by the system (IFF_UP). At this point all resources needed
5429 * for transmit and receive operations are allocated, the interrupt
5430 * handler is registered with the OS, the watchdog timer is started,
5431 * and the stack is notified that the interface is ready.
5432 **/
5433static int ixgbe_open(struct net_device *netdev)
5434{
5435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5436 int err;
4bebfaa5
AK		 5437
5438 /* disallow open during test */
5439 if (test_bit(__IXGBE_TESTING, &adapter->state))
5440 return -EBUSY;
9a799d71 5441
54386467
JB		 5442 netif_carrier_off(netdev);
5443
9a799d71
AK		 5444 /* allocate transmit descriptors */
5445 err = ixgbe_setup_all_tx_resources(adapter);
5446 if (err)
5447 goto err_setup_tx;
5448
9a799d71
AK		 5449 /* allocate receive descriptors */
5450 err = ixgbe_setup_all_rx_resources(adapter);
5451 if (err)
5452 goto err_setup_rx;
5453
5454 ixgbe_configure(adapter);
5455
021230d4 5456 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5457 if (err)
5458 goto err_req_irq;
5459
9a799d71
AK		 5460 err = ixgbe_up_complete(adapter);
5461 if (err)
5462 goto err_up;
5463
d55b53ff
JK		 5464 netif_tx_start_all_queues(netdev);
5465
9a799d71
AK		 5466 return 0;
5467
5468err_up:
5eba3699 5469 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5470 ixgbe_free_irq(adapter);
5471err_req_irq:
9a799d71 5472err_setup_rx:
a20a1199 5473 ixgbe_free_all_rx_resources(adapter);
9a799d71 5474err_setup_tx:
a20a1199 5475 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5476 ixgbe_reset(adapter);
5477
5478 return err;
5479}
5480
5481/**
5482 * ixgbe_close - Disables a network interface
5483 * @netdev: network interface device structure
5484 *
5485 * Returns 0, this is not allowed to fail
5486 *
5487 * The close entry point is called when an interface is de-activated
5488 * by the OS. The hardware is still under the drivers control, but
5489 * needs to be disabled. A global MAC reset is issued to stop the
5490 * hardware, and all transmit and receive resources are freed.
5491 **/
5492static int ixgbe_close(struct net_device *netdev)
5493{
5494 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5495
5496 ixgbe_down(adapter);
5497 ixgbe_free_irq(adapter);
5498
e4911d57
AD		 5499 ixgbe_fdir_filter_exit(adapter);
5500
9a799d71
AK		 5501 ixgbe_free_all_tx_resources(adapter);
5502 ixgbe_free_all_rx_resources(adapter);
5503
5eba3699 5504 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5505
5506 return 0;
5507}
5508
b3c8b4ba
AD		 5509#ifdef CONFIG_PM
5510static int ixgbe_resume(struct pci_dev *pdev)
5511{
c60fbb00
AD		 5512 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5513 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5514 u32 err;
5515
5516 pci_set_power_state(pdev, PCI_D0);
5517 pci_restore_state(pdev);
656ab817
DS		 5518 /*
5519 * pci_restore_state clears dev->state_saved so call
5520 * pci_save_state to restore it.
5521 */
5522 pci_save_state(pdev);
9ce77666 5523
5524 err = pci_enable_device_mem(pdev);
b3c8b4ba 5525 if (err) {
849c4542 5526 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5527 return err;
5528 }
5529 pci_set_master(pdev);
5530
dd4d8ca6 5531 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5532
5533 err = ixgbe_init_interrupt_scheme(adapter);
5534 if (err) {
849c4542 5535 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5536 return err;
5537 }
5538
b3c8b4ba
AD		 5539 ixgbe_reset(adapter);
5540
495dce12
WJP		 5541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5542
b3c8b4ba 5543 if (netif_running(netdev)) {
c60fbb00 5544 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5545 if (err)
5546 return err;
5547 }
5548
5549 netif_device_attach(netdev);
5550
5551 return 0;
5552}
b3c8b4ba 5553#endif /* CONFIG_PM */
9d8d05ae
RW		 5554
5555static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5556{
c60fbb00
AD		 5557 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5558 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5559 struct ixgbe_hw *hw = &adapter->hw;
5560 u32 ctrl, fctrl;
5561 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5562#ifdef CONFIG_PM
5563 int retval = 0;
5564#endif
5565
5566 netif_device_detach(netdev);
5567
5568 if (netif_running(netdev)) {
5569 ixgbe_down(adapter);
5570 ixgbe_free_irq(adapter);
5571 ixgbe_free_all_tx_resources(adapter);
5572 ixgbe_free_all_rx_resources(adapter);
5573 }
b3c8b4ba 5574
5f5ae6fc 5575 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5576#ifdef CONFIG_DCB
5577 kfree(adapter->ixgbe_ieee_pfc);
5578 kfree(adapter->ixgbe_ieee_ets);
5579#endif
5f5ae6fc 5580
b3c8b4ba
AD		 5581#ifdef CONFIG_PM
5582 retval = pci_save_state(pdev);
5583 if (retval)
5584 return retval;
4df10466 5585
b3c8b4ba 5586#endif
e8e26350
PW		 5587 if (wufc) {
5588 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5589
e8e26350
PW		 5590 /* turn on all-multi mode if wake on multicast is enabled */
5591 if (wufc & IXGBE_WUFC_MC) {
5592 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5593 fctrl |= IXGBE_FCTRL_MPE;
5594 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5595 }
5596
5597 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5598 ctrl |= IXGBE_CTRL_GIO_DIS;
5599 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5600
5601 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5602 } else {
5603 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5604 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5605 }
5606
bd508178
AD		 5607 switch (hw->mac.type) {
5608 case ixgbe_mac_82598EB:
dd4d8ca6 5609 pci_wake_from_d3(pdev, false);
bd508178
AD		 5610 break;
5611 case ixgbe_mac_82599EB:
b93a2226 5612 case ixgbe_mac_X540:
bd508178
AD		 5613 pci_wake_from_d3(pdev, !!wufc);
5614 break;
5615 default:
5616 break;
5617 }
b3c8b4ba 5618
9d8d05ae
RW		 5619 *enable_wake = !!wufc;
5620
b3c8b4ba
AD		 5621 ixgbe_release_hw_control(adapter);
5622
5623 pci_disable_device(pdev);
5624
9d8d05ae
RW		 5625 return 0;
5626}
5627
5628#ifdef CONFIG_PM
5629static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5630{
5631 int retval;
5632 bool wake;
5633
5634 retval = __ixgbe_shutdown(pdev, &wake);
5635 if (retval)
5636 return retval;
5637
5638 if (wake) {
5639 pci_prepare_to_sleep(pdev);
5640 } else {
5641 pci_wake_from_d3(pdev, false);
5642 pci_set_power_state(pdev, PCI_D3hot);
5643 }
b3c8b4ba
AD		 5644
5645 return 0;
5646}
9d8d05ae 5647#endif /* CONFIG_PM */
b3c8b4ba
AD		 5648
5649static void ixgbe_shutdown(struct pci_dev *pdev)
5650{
9d8d05ae
RW		 5651 bool wake;
5652
5653 __ixgbe_shutdown(pdev, &wake);
5654
5655 if (system_state == SYSTEM_POWER_OFF) {
5656 pci_wake_from_d3(pdev, wake);
5657 pci_set_power_state(pdev, PCI_D3hot);
5658 }
b3c8b4ba
AD		 5659}
5660
9a799d71
AK		 5661/**
5662 * ixgbe_update_stats - Update the board statistics counters.
5663 * @adapter: board private structure
5664 **/
5665void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5666{
2d86f139 5667 struct net_device *netdev = adapter->netdev;
9a799d71 5668 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5669 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5670 u64 total_mpc = 0;
5671 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5672 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5673 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5674 u64 bytes = 0, packets = 0;
9a799d71 5675
d08935c2
DS		 5676 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5677 test_bit(__IXGBE_RESETTING, &adapter->state))
5678 return;
5679
94b982b2 5680 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5681 u64 rsc_count = 0;
94b982b2 5682 u64 rsc_flush = 0;
d51019a4
PW		 5683 for (i = 0; i < 16; i++)
5684 adapter->hw_rx_no_dma_resources +=
7ca647bd 5685 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5686 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5687 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5688 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5689 }
5690 adapter->rsc_total_count = rsc_count;
5691 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5692 }
5693
5b7da515
AD		 5694 for (i = 0; i < adapter->num_rx_queues; i++) {
5695 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5696 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5697 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5698 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5699 bytes += rx_ring->stats.bytes;
5700 packets += rx_ring->stats.packets;
5701 }
5702 adapter->non_eop_descs = non_eop_descs;
5703 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5704 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5705 netdev->stats.rx_bytes = bytes;
5706 netdev->stats.rx_packets = packets;
5707
5708 bytes = 0;
5709 packets = 0;
7ca3bc58 5710 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5711 for (i = 0; i < adapter->num_tx_queues; i++) {
5712 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5713 restart_queue += tx_ring->tx_stats.restart_queue;
5714 tx_busy += tx_ring->tx_stats.tx_busy;
5715 bytes += tx_ring->stats.bytes;
5716 packets += tx_ring->stats.packets;
5717 }
eb985f09 5718 adapter->restart_queue = restart_queue;
5b7da515
AD		 5719 adapter->tx_busy = tx_busy;
5720 netdev->stats.tx_bytes = bytes;
5721 netdev->stats.tx_packets = packets;
7ca3bc58 5722
7ca647bd 5723 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5724 for (i = 0; i < 8; i++) {
5725 /* for packet buffers not used, the register should read 0 */
5726 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5727 missed_rx += mpc;
7ca647bd
JP		 5728 hwstats->mpc[i] += mpc;
5729 total_mpc += hwstats->mpc[i];
e8e26350 5730 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5731 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5732 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5733 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5734 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5735 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5736 switch (hw->mac.type) {
5737 case ixgbe_mac_82598EB:
7ca647bd
JP		 5738 hwstats->pxonrxc[i] +=
5739 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5740 break;
5741 case ixgbe_mac_82599EB:
b93a2226 5742 case ixgbe_mac_X540:
bd508178
AD		 5743 hwstats->pxonrxc[i] +=
5744 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5745 break;
5746 default:
5747 break;
e8e26350 5748 }
7ca647bd
JP		 5749 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5750 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5751 }
7ca647bd 5752 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5753 /* work around hardware counting issue */
7ca647bd 5754 hwstats->gprc -= missed_rx;
6f11eef7 5755
c84d324c
JF		 5756 ixgbe_update_xoff_received(adapter);
5757
6f11eef7 5758 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5759 switch (hw->mac.type) {
5760 case ixgbe_mac_82598EB:
5761 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5762 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5763 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5764 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5765 break;
b93a2226 5766 case ixgbe_mac_X540:
58f6bcf9
ET		 5767 /* OS2BMC stats are X540 only*/
5768 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5769 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5770 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5771 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5772 case ixgbe_mac_82599EB:
7ca647bd 5773 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5774 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5775 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5776 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5777 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5778 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5779 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5780 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5781 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5782#ifdef IXGBE_FCOE
7ca647bd
JP		 5783 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5784 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5785 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5786 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5787 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5788 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5789#endif /* IXGBE_FCOE */
bd508178
AD		 5790 break;
5791 default:
5792 break;
e8e26350 5793 }
9a799d71 5794 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5795 hwstats->bprc += bprc;
5796 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5797 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5798 hwstats->mprc -= bprc;
5799 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5800 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5801 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5802 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5803 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5804 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5805 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5806 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5807 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5808 hwstats->lxontxc += lxon;
6f11eef7 5809 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5810 hwstats->lxofftxc += lxoff;
5811 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5812 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5813 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5814 /*
5815 * 82598 errata - tx of flow control packets is included in tx counters
5816 */
5817 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5818 hwstats->gptc -= xon_off_tot;
5819 hwstats->mptc -= xon_off_tot;
5820 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5821 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5822 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5823 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5824 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5825 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5826 hwstats->ptc64 -= xon_off_tot;
5827 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5828 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5829 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5830 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5831 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5832 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5833
5834 /* Fill out the OS statistics structure */
7ca647bd 5835 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5836
5837 /* Rx Errors */
7ca647bd 5838 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5839 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5840 netdev->stats.rx_length_errors = hwstats->rlec;
5841 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5842 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5843}
5844
5845/**
d034acf1
AD		 5846 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5847 * @adapter - pointer to the device adapter structure
9a799d71 5848 **/
d034acf1 5849static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5850{
cf8280ee 5851 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5852 int i;
cf8280ee 5853
d034acf1
AD		 5854 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5855 return;
5856
5857 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5858
d034acf1 5859 /* if interface is down do nothing */
fe49f04a 5860 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5861 return;
5862
5863 /* do nothing if we are not using signature filters */
5864 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5865 return;
5866
5867 adapter->fdir_overflow++;
5868
93c52dd0
AD		 5869 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5870 for (i = 0; i < adapter->num_tx_queues; i++)
5871 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5872 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5873 /* re-enable flow director interrupts */
5874 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5875 } else {
5876 e_err(probe, "failed to finish FDIR re-initialization, "
5877 "ignored adding FDIR ATR filters\n");
5878 }
93c52dd0
AD		 5879}
5880
5881/**
5882 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5883 * @adapter - pointer to the device adapter structure
5884 *
5885 * This function serves two purposes. First it strobes the interrupt lines
5886 * in order to make certain interrupts are occuring. Secondly it sets the
5887 * bits needed to check for TX hangs. As a result we should immediately
5888 * determine if a hang has occured.
5889 */
5890static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5891{
cf8280ee 5892 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5893 u64 eics = 0;
5894 int i;
cf8280ee 5895
93c52dd0
AD		 5896 /* If we're down or resetting, just bail */
5897 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5898 test_bit(__IXGBE_RESETTING, &adapter->state))
5899 return;
22d5a71b 5900
93c52dd0
AD		 5901 /* Force detection of hung controller */
5902 if (netif_carrier_ok(adapter->netdev)) {
5903 for (i = 0; i < adapter->num_tx_queues; i++)
5904 set_check_for_tx_hang(adapter->tx_ring[i]);
5905 }
22d5a71b 5906
fe49f04a
AD		 5907 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5908 /*
5909 * for legacy and MSI interrupts don't set any bits
5910 * that are enabled for EIAM, because this operation
5911 * would set *both* EIMS and EICS for any bit in EIAM
5912 */
5913 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5914 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5915 } else {
5916 /* get one bit for every active tx/rx interrupt vector */
5917 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5918 struct ixgbe_q_vector *qv = adapter->q_vector[i];
08c8833b 5919 if (qv->rx.count || qv->tx.count)
93c52dd0
AD		 5920 eics |= ((u64)1 << i);
5921 }
cf8280ee 5922 }
9a799d71 5923
93c52dd0 5924 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5925 ixgbe_irq_rearm_queues(adapter, eics);
5926
cf8280ee
JB		 5927}
5928
e8e26350 5929/**
93c52dd0
AD		 5930 * ixgbe_watchdog_update_link - update the link status
5931 * @adapter - pointer to the device adapter structure
5932 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5933 **/
93c52dd0 5934static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5935{
e8e26350 5936 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5937 u32 link_speed = adapter->link_speed;
5938 bool link_up = adapter->link_up;
c4cf55e5 5939 int i;
e8e26350 5940
93c52dd0
AD		 5941 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5942 return;
5943
5944 if (hw->mac.ops.check_link) {
5945 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5946 } else {
93c52dd0
AD		 5947 /* always assume link is up, if no check link function */
5948 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5949 link_up = true;
c4cf55e5 5950 }
93c52dd0
AD		 5951 if (link_up) {
5952 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5953 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5954 hw->mac.ops.fc_enable(hw, i);
5955 } else {
5956 hw->mac.ops.fc_enable(hw, 0);
5957 }
5958 }
5959
5960 if (link_up ||
5961 time_after(jiffies, (adapter->link_check_timeout +
5962 IXGBE_TRY_LINK_TIMEOUT))) {
5963 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5964 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5965 IXGBE_WRITE_FLUSH(hw);
5966 }
5967
5968 adapter->link_up = link_up;
5969 adapter->link_speed = link_speed;
e8e26350
PW		 5970}
5971
5972/**
93c52dd0
AD		 5973 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5974 * print link up message
5975 * @adapter - pointer to the device adapter structure
e8e26350 5976 **/
93c52dd0 5977static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5978{
93c52dd0 5979 struct net_device *netdev = adapter->netdev;
e8e26350 5980 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5981 u32 link_speed = adapter->link_speed;
5982 bool flow_rx, flow_tx;
e8e26350 5983
93c52dd0
AD		 5984 /* only continue if link was previously down */
5985 if (netif_carrier_ok(netdev))
a985b6c3 5986 return;
63d6e1d8 5987
93c52dd0 5988 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5989
93c52dd0
AD		 5990 switch (hw->mac.type) {
5991 case ixgbe_mac_82598EB: {
5992 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5993 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5994 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5995 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5996 }
5997 break;
5998 case ixgbe_mac_X540:
5999 case ixgbe_mac_82599EB: {
6000 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6001 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6002 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6003 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6004 }
6005 break;
6006 default:
6007 flow_tx = false;
6008 flow_rx = false;
6009 break;
e8e26350 6010 }
93c52dd0
AD		 6011 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6012 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6013 "10 Gbps" :
6014 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6015 "1 Gbps" :
6016 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6017 "100 Mbps" :
6018 "unknown speed"))),
6019 ((flow_rx && flow_tx) ? "RX/TX" :
6020 (flow_rx ? "RX" :
6021 (flow_tx ? "TX" : "None"))));
e8e26350 6022
93c52dd0 6023 netif_carrier_on(netdev);
93c52dd0 6024 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 6025}
6026
c4cf55e5 6027/**
93c52dd0
AD		 6028 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6029 * print link down message
6030 * @adapter - pointer to the adapter structure
c4cf55e5 6031 **/
93c52dd0 6032static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6033{
cf8280ee 6034 struct net_device *netdev = adapter->netdev;
c4cf55e5 6035 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6036
93c52dd0
AD		 6037 adapter->link_up = false;
6038 adapter->link_speed = 0;
cf8280ee 6039
93c52dd0
AD		 6040 /* only continue if link was up previously */
6041 if (!netif_carrier_ok(netdev))
6042 return;
264857b8 6043
93c52dd0
AD		 6044 /* poll for SFP+ cable when link is down */
6045 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6046 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6047
93c52dd0
AD		 6048 e_info(drv, "NIC Link is Down\n");
6049 netif_carrier_off(netdev);
6050}
e8e26350 6051
93c52dd0
AD		 6052/**
6053 * ixgbe_watchdog_flush_tx - flush queues on link down
6054 * @adapter - pointer to the device adapter structure
6055 **/
6056static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6057{
c4cf55e5 6058 int i;
93c52dd0 6059 int some_tx_pending = 0;
c4cf55e5 6060
93c52dd0 6061 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6062 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6063 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6064 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6065 some_tx_pending = 1;
6066 break;
6067 }
6068 }
6069
6070 if (some_tx_pending) {
6071 /* We've lost link, so the controller stops DMA,
6072 * but we've got queued Tx work that's never going
6073 * to get done, so reset controller to flush Tx.
6074 * (Do the reset outside of interrupt context).
6075 */
c83c6cbd 6076 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6077 }
c4cf55e5 6078 }
c4cf55e5
PWJ		 6079}
6080
a985b6c3
GR		 6081static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6082{
6083 u32 ssvpc;
6084
6085 /* Do not perform spoof check for 82598 */
6086 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6087 return;
6088
6089 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6090
6091 /*
6092 * ssvpc register is cleared on read, if zero then no
6093 * spoofed packets in the last interval.
6094 */
6095 if (!ssvpc)
6096 return;
6097
6098 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6099}
6100
93c52dd0
AD		 6101/**
6102 * ixgbe_watchdog_subtask - check and bring link up
6103 * @adapter - pointer to the device adapter structure
6104 **/
6105static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6106{
6107 /* if interface is down do nothing */
6108 if (test_bit(__IXGBE_DOWN, &adapter->state))
6109 return;
6110
6111 ixgbe_watchdog_update_link(adapter);
6112
6113 if (adapter->link_up)
6114 ixgbe_watchdog_link_is_up(adapter);
6115 else
6116 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6117
a985b6c3 6118 ixgbe_spoof_check(adapter);
9a799d71 6119 ixgbe_update_stats(adapter);
93c52dd0
AD		 6120
6121 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6122}
10eec955 6123
cf8280ee 6124/**
7086400d
AD		 6125 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6126 * @adapter - the ixgbe adapter structure
cf8280ee 6127 **/
7086400d 6128static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6129{
cf8280ee 6130 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6131 s32 err;
cf8280ee 6132
7086400d
AD		 6133 /* not searching for SFP so there is nothing to do here */
6134 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6135 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6136 return;
10eec955 6137
7086400d
AD		 6138 /* someone else is in init, wait until next service event */
6139 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6140 return;
cf8280ee 6141
7086400d
AD		 6142 err = hw->phy.ops.identify_sfp(hw);
6143 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6144 goto sfp_out;
264857b8 6145
7086400d
AD		 6146 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6147 /* If no cable is present, then we need to reset
6148 * the next time we find a good cable. */
6149 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6150 }
9a799d71 6151
7086400d
AD		 6152 /* exit on error */
6153 if (err)
6154 goto sfp_out;
e8e26350 6155
7086400d
AD		 6156 /* exit if reset not needed */
6157 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6158 goto sfp_out;
9a799d71 6159
7086400d 6160 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6161
7086400d
AD		 6162 /*
6163 * A module may be identified correctly, but the EEPROM may not have
6164 * support for that module. setup_sfp() will fail in that case, so
6165 * we should not allow that module to load.
6166 */
6167 if (hw->mac.type == ixgbe_mac_82598EB)
6168 err = hw->phy.ops.reset(hw);
6169 else
6170 err = hw->mac.ops.setup_sfp(hw);
6171
6172 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6173 goto sfp_out;
6174
6175 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6176 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6177
6178sfp_out:
6179 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6180
6181 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6182 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6183 e_dev_err("failed to initialize because an unsupported "
6184 "SFP+ module type was detected.\n");
6185 e_dev_err("Reload the driver after installing a "
6186 "supported module.\n");
6187 unregister_netdev(adapter->netdev);
bc59fcda 6188 }
7086400d 6189}
bc59fcda 6190
7086400d
AD		 6191/**
6192 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6193 * @adapter - the ixgbe adapter structure
6194 **/
6195static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6196{
6197 struct ixgbe_hw *hw = &adapter->hw;
6198 u32 autoneg;
6199 bool negotiation;
6200
6201 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6202 return;
6203
6204 /* someone else is in init, wait until next service event */
6205 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6206 return;
6207
6208 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6209
6210 autoneg = hw->phy.autoneg_advertised;
6211 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6212 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6213 hw->mac.autotry_restart = false;
6214 if (hw->mac.ops.setup_link)
6215 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6216
6217 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6218 adapter->link_check_timeout = jiffies;
6219 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6220}
6221
6222/**
6223 * ixgbe_service_timer - Timer Call-back
6224 * @data: pointer to adapter cast into an unsigned long
6225 **/
6226static void ixgbe_service_timer(unsigned long data)
6227{
6228 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6229 unsigned long next_event_offset;
6230
6231 /* poll faster when waiting for link */
6232 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6233 next_event_offset = HZ / 10;
6234 else
6235 next_event_offset = HZ * 2;
6236
6237 /* Reset the timer */
6238 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6239
6240 ixgbe_service_event_schedule(adapter);
6241}
6242
c83c6cbd
AD		 6243static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6244{
6245 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6246 return;
6247
6248 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6249
6250 /* If we're already down or resetting, just bail */
6251 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6252 test_bit(__IXGBE_RESETTING, &adapter->state))
6253 return;
6254
6255 ixgbe_dump(adapter);
6256 netdev_err(adapter->netdev, "Reset adapter\n");
6257 adapter->tx_timeout_count++;
6258
6259 ixgbe_reinit_locked(adapter);
6260}
6261
7086400d
AD		 6262/**
6263 * ixgbe_service_task - manages and runs subtasks
6264 * @work: pointer to work_struct containing our data
6265 **/
6266static void ixgbe_service_task(struct work_struct *work)
6267{
6268 struct ixgbe_adapter *adapter = container_of(work,
6269 struct ixgbe_adapter,
6270 service_task);
6271
c83c6cbd 6272 ixgbe_reset_subtask(adapter);
7086400d
AD		 6273 ixgbe_sfp_detection_subtask(adapter);
6274 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6275 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6276 ixgbe_watchdog_subtask(adapter);
d034acf1 6277 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6278 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6279
6280 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6281}
6282
897ab156
AD		 6283void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6284 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6285{
6286 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6287 u16 i = tx_ring->next_to_use;
9a799d71 6288
897ab156 6289 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6290
897ab156
AD		 6291 i++;
6292 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6293
897ab156
AD		 6294 /* set bits to identify this as an advanced context descriptor */
6295 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6296
897ab156
AD		 6297 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6298 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6299 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6300 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6301}
9a799d71 6302
897ab156
AD		 6303static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6304 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6305{
6306 int err;
6307 u32 vlan_macip_lens, type_tucmd;
6308 u32 mss_l4len_idx, l4len;
9a799d71 6309
897ab156
AD		 6310 if (!skb_is_gso(skb))
6311 return 0;
9a799d71 6312
897ab156
AD		 6313 if (skb_header_cloned(skb)) {
6314 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6315 if (err)
6316 return err;
9a799d71 6317 }
9a799d71 6318
897ab156
AD		 6319 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6320 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6321
6322 if (protocol == __constant_htons(ETH_P_IP)) {
6323 struct iphdr *iph = ip_hdr(skb);
6324 iph->tot_len = 0;
6325 iph->check = 0;
6326 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6327 iph->daddr, 0,
6328 IPPROTO_TCP,
6329 0);
6330 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6331 } else if (skb_is_gso_v6(skb)) {
6332 ipv6_hdr(skb)->payload_len = 0;
6333 tcp_hdr(skb)->check =
6334 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6335 &ipv6_hdr(skb)->daddr,
6336 0, IPPROTO_TCP, 0);
6337 }
6338
6339 l4len = tcp_hdrlen(skb);
6340 *hdr_len = skb_transport_offset(skb) + l4len;
6341
6342 /* mss_l4len_id: use 1 as index for TSO */
6343 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6344 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6345 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6346
6347 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6348 vlan_macip_lens = skb_network_header_len(skb);
6349 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6350 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6351
6352 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6353 mss_l4len_idx);
6354
6355 return 1;
6356}
6357
6358static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6359 struct sk_buff *skb, u32 tx_flags,
6360 __be16 protocol)
7ca647bd 6361{
897ab156
AD		 6362 u32 vlan_macip_lens = 0;
6363 u32 mss_l4len_idx = 0;
6364 u32 type_tucmd = 0;
7ca647bd 6365
897ab156
AD		 6366 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6367 if (!(tx_flags & IXGBE_TX_FLAGS_VLAN))
6368 return false;
6369 } else {
6370 u8 l4_hdr = 0;
6371 switch (protocol) {
6372 case __constant_htons(ETH_P_IP):
6373 vlan_macip_lens |= skb_network_header_len(skb);
6374 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6375 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6376 break;
897ab156
AD		 6377 case __constant_htons(ETH_P_IPV6):
6378 vlan_macip_lens |= skb_network_header_len(skb);
6379 l4_hdr = ipv6_hdr(skb)->nexthdr;
6380 break;
6381 default:
6382 if (unlikely(net_ratelimit())) {
6383 dev_warn(tx_ring->dev,
6384 "partial checksum but proto=%x!\n",
6385 skb->protocol);
6386 }
7ca647bd
JP		 6387 break;
6388 }
897ab156
AD		 6389
6390 switch (l4_hdr) {
7ca647bd 6391 case IPPROTO_TCP:
897ab156
AD		 6392 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6393 mss_l4len_idx = tcp_hdrlen(skb) <<
6394 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6395 break;
6396 case IPPROTO_SCTP:
897ab156
AD		 6397 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6398 mss_l4len_idx = sizeof(struct sctphdr) <<
6399 IXGBE_ADVTXD_L4LEN_SHIFT;
6400 break;
6401 case IPPROTO_UDP:
6402 mss_l4len_idx = sizeof(struct udphdr) <<
6403 IXGBE_ADVTXD_L4LEN_SHIFT;
6404 break;
6405 default:
6406 if (unlikely(net_ratelimit())) {
6407 dev_warn(tx_ring->dev,
6408 "partial checksum but l4 proto=%x!\n",
6409 skb->protocol);
6410 }
7ca647bd
JP		 6411 break;
6412 }
7ca647bd
JP		 6413 }
6414
897ab156
AD		 6415 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6416 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6417
897ab156
AD		 6418 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6419 type_tucmd, mss_l4len_idx);
9a799d71 6420
897ab156 6421 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6422}
6423
6424static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6425 struct ixgbe_ring *tx_ring,
6426 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6427 unsigned int first, const u8 hdr_len)
9a799d71 6428{
b6ec895e 6429 struct device *dev = tx_ring->dev;
9a799d71 6430 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6431 unsigned int len;
6432 unsigned int total = skb->len;
63544e9c 6433 unsigned int offset = 0, size, count = 0;
9a799d71
AK		 6434 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6435 unsigned int f;
8ad494b0
AD		 6436 unsigned int bytecount = skb->len;
6437 u16 gso_segs = 1;
63544e9c 6438 u16 i;
9a799d71
AK		 6439
6440 i = tx_ring->next_to_use;
6441
eacd73f7
YZ		 6442 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6443 /* excluding fcoe_crc_eof for FCoE */
6444 total -= sizeof(struct fcoe_crc_eof);
6445
6446 len = min(skb_headlen(skb), total);
9a799d71
AK		 6447 while (len) {
6448 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6449 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6450
6451 tx_buffer_info->length = size;
e5a43549 6452 tx_buffer_info->mapped_as_page = false;
b6ec895e 6453 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6454 skb->data + offset,
1b507730 6455 size, DMA_TO_DEVICE);
b6ec895e 6456 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6457 goto dma_error;
9a799d71
AK		 6458 tx_buffer_info->time_stamp = jiffies;
6459 tx_buffer_info->next_to_watch = i;
6460
6461 len -= size;
eacd73f7 6462 total -= size;
9a799d71
AK		 6463 offset += size;
6464 count++;
44df32c5
AD		 6465
6466 if (len) {
6467 i++;
6468 if (i == tx_ring->count)
6469 i = 0;
6470 }
9a799d71
AK		 6471 }
6472
6473 for (f = 0; f < nr_frags; f++) {
6474 struct skb_frag_struct *frag;
6475
6476 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6477 len = min((unsigned int)frag->size, total);
e5a43549 6478 offset = frag->page_offset;
9a799d71
AK		 6479
6480 while (len) {
44df32c5
AD		 6481 i++;
6482 if (i == tx_ring->count)
6483 i = 0;
6484
9a799d71
AK		 6485 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6486 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6487
6488 tx_buffer_info->length = size;
b6ec895e 6489 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6490 frag->page,
6491 offset, size,
1b507730 6492 DMA_TO_DEVICE);
e5a43549 6493 tx_buffer_info->mapped_as_page = true;
b6ec895e 6494 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6495 goto dma_error;
9a799d71
AK		 6496 tx_buffer_info->time_stamp = jiffies;
6497 tx_buffer_info->next_to_watch = i;
6498
6499 len -= size;
eacd73f7 6500 total -= size;
9a799d71
AK		 6501 offset += size;
6502 count++;
9a799d71 6503 }
eacd73f7
YZ		 6504 if (total == 0)
6505 break;
9a799d71 6506 }
44df32c5 6507
8ad494b0
AD		 6508 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6509 gso_segs = skb_shinfo(skb)->gso_segs;
6510#ifdef IXGBE_FCOE
6511 /* adjust for FCoE Sequence Offload */
6512 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6513 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6514 skb_shinfo(skb)->gso_size);
6515#endif /* IXGBE_FCOE */
6516 bytecount += (gso_segs - 1) * hdr_len;
6517
6518 /* multiply data chunks by size of headers */
6519 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6520 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6521 tx_ring->tx_buffer_info[i].skb = skb;
6522 tx_ring->tx_buffer_info[first].next_to_watch = i;
6523
e5a43549
AD		 6524 return count;
6525
6526dma_error:
849c4542 6527 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6528
6529 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6530 tx_buffer_info->dma = 0;
6531 tx_buffer_info->time_stamp = 0;
6532 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6533 if (count)
6534 count--;
e5a43549
AD		 6535
6536 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6537 while (count--) {
e8e9f696 6538 if (i == 0)
e5a43549 6539 i += tx_ring->count;
c1fa347f 6540 i--;
e5a43549 6541 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6542 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6543 }
6544
e44d38e1 6545 return 0;
9a799d71
AK		 6546}
6547
84ea2591 6548static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6549 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6550{
6551 union ixgbe_adv_tx_desc *tx_desc = NULL;
6552 struct ixgbe_tx_buffer *tx_buffer_info;
6553 u32 olinfo_status = 0, cmd_type_len = 0;
6554 unsigned int i;
6555 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6556
6557 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6558
6559 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6560
6561 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6562 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6563
6564 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6565 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6566
6567 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6568 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6569
4eeae6fd
PW		 6570 /* use index 1 context for tso */
6571 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6572 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6573 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6574 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6575
6576 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6577 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6578 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6579
eacd73f7
YZ		 6580 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6581 olinfo_status |= IXGBE_ADVTXD_CC;
6582 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6583 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6584 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6585 }
6586
9a799d71
AK		 6587 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6588
6589 i = tx_ring->next_to_use;
6590 while (count--) {
6591 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6592 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6593 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6594 tx_desc->read.cmd_type_len =
e8e9f696 6595 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6596 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6597 i++;
6598 if (i == tx_ring->count)
6599 i = 0;
6600 }
6601
6602 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6603
6604 /*
6605 * Force memory writes to complete before letting h/w
6606 * know there are new descriptors to fetch. (Only
6607 * applicable for weak-ordered memory model archs,
6608 * such as IA-64).
6609 */
6610 wmb();
6611
6612 tx_ring->next_to_use = i;
84ea2591 6613 writel(i, tx_ring->tail);
9a799d71
AK		 6614}
6615
69830529
AD		 6616static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6617 u32 tx_flags, __be16 protocol)
6618{
6619 struct ixgbe_q_vector *q_vector = ring->q_vector;
6620 union ixgbe_atr_hash_dword input = { .dword = 0 };
6621 union ixgbe_atr_hash_dword common = { .dword = 0 };
6622 union {
6623 unsigned char *network;
6624 struct iphdr *ipv4;
6625 struct ipv6hdr *ipv6;
6626 } hdr;
ee9e0f0b 6627 struct tcphdr *th;
905e4a41 6628 __be16 vlan_id;
c4cf55e5 6629
69830529
AD		 6630 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6631 if (!q_vector)
6632 return;
6633
6634 /* do nothing if sampling is disabled */
6635 if (!ring->atr_sample_rate)
d3ead241 6636 return;
c4cf55e5 6637
69830529 6638 ring->atr_count++;
c4cf55e5 6639
69830529
AD		 6640 /* snag network header to get L4 type and address */
6641 hdr.network = skb_network_header(skb);
6642
6643 /* Currently only IPv4/IPv6 with TCP is supported */
6644 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6645 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6646 (protocol != __constant_htons(ETH_P_IP) ||
6647 hdr.ipv4->protocol != IPPROTO_TCP))
6648 return;
ee9e0f0b
AD		 6649
6650 th = tcp_hdr(skb);
c4cf55e5 6651
69830529
AD		 6652 /* skip this packet since the socket is closing */
6653 if (th->fin)
6654 return;
6655
6656 /* sample on all syn packets or once every atr sample count */
6657 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6658 return;
6659
6660 /* reset sample count */
6661 ring->atr_count = 0;
6662
6663 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6664
6665 /*
6666 * src and dst are inverted, think how the receiver sees them
6667 *
6668 * The input is broken into two sections, a non-compressed section
6669 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6670 * is XORed together and stored in the compressed dword.
6671 */
6672 input.formatted.vlan_id = vlan_id;
6673
6674 /*
6675 * since src port and flex bytes occupy the same word XOR them together
6676 * and write the value to source port portion of compressed dword
6677 */
6678 if (vlan_id)
6679 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6680 else
6681 common.port.src ^= th->dest ^ protocol;
6682 common.port.dst ^= th->source;
6683
6684 if (protocol == __constant_htons(ETH_P_IP)) {
6685 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6686 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6687 } else {
6688 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6689 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6690 hdr.ipv6->saddr.s6_addr32[1] ^
6691 hdr.ipv6->saddr.s6_addr32[2] ^
6692 hdr.ipv6->saddr.s6_addr32[3] ^
6693 hdr.ipv6->daddr.s6_addr32[0] ^
6694 hdr.ipv6->daddr.s6_addr32[1] ^
6695 hdr.ipv6->daddr.s6_addr32[2] ^
6696 hdr.ipv6->daddr.s6_addr32[3];
6697 }
c4cf55e5
PWJ		 6698
6699 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6700 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6701 input, common, ring->queue_index);
c4cf55e5
PWJ		 6702}
6703
63544e9c 6704static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6705{
fc77dc3c 6706 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6707 /* Herbert's original patch had:
6708 * smp_mb__after_netif_stop_queue();
6709 * but since that doesn't exist yet, just open code it. */
6710 smp_mb();
6711
6712 /* We need to check again in a case another CPU has just
6713 * made room available. */
7d4987de 6714 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6715 return -EBUSY;
6716
6717 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6718 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6719 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6720 return 0;
6721}
6722
82d4e46e 6723static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6724{
7d4987de 6725 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6726 return 0;
fc77dc3c 6727 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6728}
6729
09a3b1f8
SH		 6730static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6731{
6732 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6733 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6734 smp_processor_id();
56075a98 6735#ifdef IXGBE_FCOE
6440752c 6736 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6737
e5b64635
JF		 6738 if (((protocol == htons(ETH_P_FCOE)) ||
6739 (protocol == htons(ETH_P_FIP))) &&
6740 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6741 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6742 txq += adapter->ring_feature[RING_F_FCOE].mask;
6743 return txq;
56075a98
JF		 6744 }
6745#endif
6746
fdd3d631
KK		 6747 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6748 while (unlikely(txq >= dev->real_num_tx_queues))
6749 txq -= dev->real_num_tx_queues;
5f715823 6750 return txq;
fdd3d631 6751 }
c4cf55e5 6752
09a3b1f8
SH		 6753 return skb_tx_hash(dev, skb);
6754}
6755
fc77dc3c 6756netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6757 struct ixgbe_adapter *adapter,
6758 struct ixgbe_ring *tx_ring)
9a799d71 6759{
5f715823 6760 int tso;
a535c30e
AD		 6761 u32 tx_flags = 0;
6762#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6763 unsigned short f;
6764#endif
63544e9c 6765 u16 first;
a535c30e 6766 u16 count = TXD_USE_COUNT(skb_headlen(skb));
5e09a105 6767 __be16 protocol;
63544e9c 6768 u8 hdr_len = 0;
5e09a105 6769
a535c30e
AD		 6770 /*
6771 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6772 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6773 * + 2 desc gap to keep tail from touching head,
6774 * + 1 desc for context descriptor,
6775 * otherwise try next time
6776 */
6777#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6778 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6779 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6780#else
6781 count += skb_shinfo(skb)->nr_frags;
6782#endif
6783 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6784 tx_ring->tx_stats.tx_busy++;
6785 return NETDEV_TX_BUSY;
6786 }
6787
5e09a105 6788 protocol = vlan_get_protocol(skb);
9f8cdf4f 6789
eab6d18d 6790 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6791 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6792 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6793 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
e5b64635 6794 tx_flags |= tx_ring->dcb_tc << 13;
2f90b865
AD		 6795 }
6796 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6797 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6798 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6799 skb->priority != TC_PRIO_CONTROL) {
e5b64635 6800 tx_flags |= tx_ring->dcb_tc << 13;
2ea186ae
JF		 6801 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6802 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6803 }
eacd73f7 6804
09ad1cc0 6805#ifdef IXGBE_FCOE
56075a98
JF		 6806 /* for FCoE with DCB, we force the priority to what
6807 * was specified by the switch */
6808 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
e5b64635
JF		 6809 (protocol == htons(ETH_P_FCOE)))
6810 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6811
a535c30e
AD		 6812#endif
6813 /* record the location of the first descriptor for this packet */
9a799d71 6814 first = tx_ring->next_to_use;
a535c30e 6815
eacd73f7
YZ		 6816 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6817#ifdef IXGBE_FCOE
6818 /* setup tx offload for FCoE */
897ab156
AD		 6819 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6820 if (tso < 0)
6821 goto out_drop;
6822 else if (tso)
eacd73f7
YZ		 6823 tx_flags |= IXGBE_TX_FLAGS_FSO;
6824#endif /* IXGBE_FCOE */
6825 } else {
5e09a105 6826 if (protocol == htons(ETH_P_IP))
eacd73f7 6827 tx_flags |= IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6828 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6829 if (tso < 0)
6830 goto out_drop;
6831 else if (tso)
eacd73f7 6832 tx_flags |= IXGBE_TX_FLAGS_TSO;
897ab156 6833 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
eacd73f7
YZ		 6834 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6835 }
9a799d71 6836
8ad494b0 6837 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6838 if (count) {
c4cf55e5 6839 /* add the ATR filter if ATR is on */
69830529
AD		 6840 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6841 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
84ea2591 6842 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6843 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6844
44df32c5 6845 } else {
44df32c5
AD		 6846 tx_ring->tx_buffer_info[first].time_stamp = 0;
6847 tx_ring->next_to_use = first;
897ab156 6848 goto out_drop;
44df32c5 6849 }
9a799d71
AK		 6850
6851 return NETDEV_TX_OK;
897ab156
AD		 6852
6853out_drop:
6854 dev_kfree_skb_any(skb);
6855 return NETDEV_TX_OK;
9a799d71
AK		 6856}
6857
84418e3b
AD		 6858static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6859{
6860 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6861 struct ixgbe_ring *tx_ring;
6862
6863 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6864 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6865}
6866
9a799d71
AK		 6867/**
6868 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6869 * @netdev: network interface device structure
6870 * @p: pointer to an address structure
6871 *
6872 * Returns 0 on success, negative on failure
6873 **/
6874static int ixgbe_set_mac(struct net_device *netdev, void *p)
6875{
6876 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6877 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6878 struct sockaddr *addr = p;
6879
6880 if (!is_valid_ether_addr(addr->sa_data))
6881 return -EADDRNOTAVAIL;
6882
6883 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6884 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6885
1cdd1ec8
GR		 6886 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6887 IXGBE_RAH_AV);
9a799d71
AK		 6888
6889 return 0;
6890}
6891
6b73e10d
BH		 6892static int
6893ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6894{
6895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6896 struct ixgbe_hw *hw = &adapter->hw;
6897 u16 value;
6898 int rc;
6899
6900 if (prtad != hw->phy.mdio.prtad)
6901 return -EINVAL;
6902 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6903 if (!rc)
6904 rc = value;
6905 return rc;
6906}
6907
6908static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6909 u16 addr, u16 value)
6910{
6911 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6912 struct ixgbe_hw *hw = &adapter->hw;
6913
6914 if (prtad != hw->phy.mdio.prtad)
6915 return -EINVAL;
6916 return hw->phy.ops.write_reg(hw, addr, devad, value);
6917}
6918
6919static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6920{
6921 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6922
6923 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6924}
6925
0365e6e4
PW		 6926/**
6927 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6928 * netdev->dev_addrs
0365e6e4
PW		 6929 * @netdev: network interface device structure
6930 *
6931 * Returns non-zero on failure
6932 **/
6933static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6934{
6935 int err = 0;
6936 struct ixgbe_adapter *adapter = netdev_priv(dev);
6937 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6938
6939 if (is_valid_ether_addr(mac->san_addr)) {
6940 rtnl_lock();
6941 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6942 rtnl_unlock();
6943 }
6944 return err;
6945}
6946
6947/**
6948 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6949 * netdev->dev_addrs
0365e6e4
PW		 6950 * @netdev: network interface device structure
6951 *
6952 * Returns non-zero on failure
6953 **/
6954static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6955{
6956 int err = 0;
6957 struct ixgbe_adapter *adapter = netdev_priv(dev);
6958 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6959
6960 if (is_valid_ether_addr(mac->san_addr)) {
6961 rtnl_lock();
6962 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6963 rtnl_unlock();
6964 }
6965 return err;
6966}
6967
9a799d71
AK		 6968#ifdef CONFIG_NET_POLL_CONTROLLER
6969/*
6970 * Polling 'interrupt' - used by things like netconsole to send skbs
6971 * without having to re-enable interrupts. It's not called while
6972 * the interrupt routine is executing.
6973 */
6974static void ixgbe_netpoll(struct net_device *netdev)
6975{
6976 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6977 int i;
9a799d71 6978
1a647bd2
AD		 6979 /* if interface is down do nothing */
6980 if (test_bit(__IXGBE_DOWN, &adapter->state))
6981 return;
6982
9a799d71 6983 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6984 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6985 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6986 for (i = 0; i < num_q_vectors; i++) {
6987 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6988 ixgbe_msix_clean_many(0, q_vector);
6989 }
6990 } else {
6991 ixgbe_intr(adapter->pdev->irq, netdev);
6992 }
9a799d71 6993 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6994}
6995#endif
6996
de1036b1
ED		 6997static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6998 struct rtnl_link_stats64 *stats)
6999{
7000 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7001 int i;
7002
1a51502b 7003 rcu_read_lock();
de1036b1 7004 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7005 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7006 u64 bytes, packets;
7007 unsigned int start;
7008
1a51502b
ED		 7009 if (ring) {
7010 do {
7011 start = u64_stats_fetch_begin_bh(&ring->syncp);
7012 packets = ring->stats.packets;
7013 bytes = ring->stats.bytes;
7014 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7015 stats->rx_packets += packets;
7016 stats->rx_bytes += bytes;
7017 }
de1036b1 7018 }
1ac9ad13
ED		 7019
7020 for (i = 0; i < adapter->num_tx_queues; i++) {
7021 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7022 u64 bytes, packets;
7023 unsigned int start;
7024
7025 if (ring) {
7026 do {
7027 start = u64_stats_fetch_begin_bh(&ring->syncp);
7028 packets = ring->stats.packets;
7029 bytes = ring->stats.bytes;
7030 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7031 stats->tx_packets += packets;
7032 stats->tx_bytes += bytes;
7033 }
7034 }
1a51502b 7035 rcu_read_unlock();
de1036b1
ED		 7036 /* following stats updated by ixgbe_watchdog_task() */
7037 stats->multicast = netdev->stats.multicast;
7038 stats->rx_errors = netdev->stats.rx_errors;
7039 stats->rx_length_errors = netdev->stats.rx_length_errors;
7040 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7041 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7042 return stats;
7043}
7044
8b1c0b24
JF		 7045/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7046 * #adapter: pointer to ixgbe_adapter
7047 * @tc: number of traffic classes currently enabled
7048 *
7049 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7050 * 802.1Q priority maps to a packet buffer that exists.
7051 */
7052static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7053{
7054 struct ixgbe_hw *hw = &adapter->hw;
7055 u32 reg, rsave;
7056 int i;
7057
7058 /* 82598 have a static priority to TC mapping that can not
7059 * be changed so no validation is needed.
7060 */
7061 if (hw->mac.type == ixgbe_mac_82598EB)
7062 return;
7063
7064 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7065 rsave = reg;
7066
7067 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7068 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7069
7070 /* If up2tc is out of bounds default to zero */
7071 if (up2tc > tc)
7072 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7073 }
7074
7075 if (reg != rsave)
7076 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7077
7078 return;
7079}
7080
7081
7082/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7083 * classes.
7084 *
7085 * @netdev: net device to configure
7086 * @tc: number of traffic classes to enable
7087 */
7088int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7089{
8b1c0b24
JF		 7090 struct ixgbe_adapter *adapter = netdev_priv(dev);
7091 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24
JF		 7092
7093 /* If DCB is anabled do not remove traffic classes, multiple
7094 * traffic classes are required to implement DCB
7095 */
7096 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7097 return 0;
7098
7099 /* Hardware supports up to 8 traffic classes */
7100 if (tc > MAX_TRAFFIC_CLASS ||
7101 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7102 return -EINVAL;
7103
7104 /* Hardware has to reinitialize queues and interrupts to
7105 * match packet buffer alignment. Unfortunantly, the
7106 * hardware is not flexible enough to do this dynamically.
7107 */
7108 if (netif_running(dev))
7109 ixgbe_close(dev);
7110 ixgbe_clear_interrupt_scheme(adapter);
7111
7112 if (tc)
7113 netdev_set_num_tc(dev, tc);
7114 else
7115 netdev_reset_tc(dev);
7116
8b1c0b24
JF		 7117 ixgbe_init_interrupt_scheme(adapter);
7118 ixgbe_validate_rtr(adapter, tc);
7119 if (netif_running(dev))
7120 ixgbe_open(dev);
7121
7122 return 0;
7123}
de1036b1 7124
0edc3527 7125static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7126 .ndo_open = ixgbe_open,
0edc3527 7127 .ndo_stop = ixgbe_close,
00829823 7128 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7129 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7130 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7131 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7132 .ndo_validate_addr = eth_validate_addr,
7133 .ndo_set_mac_address = ixgbe_set_mac,
7134 .ndo_change_mtu = ixgbe_change_mtu,
7135 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7136 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7137 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7138 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7139 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7140 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7141 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7142 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7143 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7144 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7145#ifdef CONFIG_NET_POLL_CONTROLLER
7146 .ndo_poll_controller = ixgbe_netpoll,
7147#endif
332d4a7d
YZ		 7148#ifdef IXGBE_FCOE
7149 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7150 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7151 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7152 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7153 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7154 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7155#endif /* IXGBE_FCOE */
0edc3527
SH		 7156};
7157
1cdd1ec8
GR		 7158static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7159 const struct ixgbe_info *ii)
7160{
7161#ifdef CONFIG_PCI_IOV
7162 struct ixgbe_hw *hw = &adapter->hw;
7163 int err;
a1cbb15c
GR		 7164 int num_vf_macvlans, i;
7165 struct vf_macvlans *mv_list;
1cdd1ec8 7166
3377eba7 7167 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7168 return;
7169
7170 /* The 82599 supports up to 64 VFs per physical function
7171 * but this implementation limits allocation to 63 so that
7172 * basic networking resources are still available to the
7173 * physical function
7174 */
7175 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7176 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7177 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7178 if (err) {
396e799c 7179 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7180 goto err_novfs;
7181 }
a1cbb15c
GR		 7182
7183 num_vf_macvlans = hw->mac.num_rar_entries -
7184 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7185
7186 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7187 sizeof(struct vf_macvlans),
7188 GFP_KERNEL);
7189 if (mv_list) {
7190 /* Initialize list of VF macvlans */
7191 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7192 for (i = 0; i < num_vf_macvlans; i++) {
7193 mv_list->vf = -1;
7194 mv_list->free = true;
7195 mv_list->rar_entry = hw->mac.num_rar_entries -
7196 (i + adapter->num_vfs + 1);
7197 list_add(&mv_list->l, &adapter->vf_mvs.l);
7198 mv_list++;
7199 }
7200 }
7201
1cdd1ec8
GR		 7202 /* If call to enable VFs succeeded then allocate memory
7203 * for per VF control structures.
7204 */
7205 adapter->vfinfo =
7206 kcalloc(adapter->num_vfs,
7207 sizeof(struct vf_data_storage), GFP_KERNEL);
7208 if (adapter->vfinfo) {
7209 /* Now that we're sure SR-IOV is enabled
7210 * and memory allocated set up the mailbox parameters
7211 */
7212 ixgbe_init_mbx_params_pf(hw);
7213 memcpy(&hw->mbx.ops, ii->mbx_ops,
7214 sizeof(hw->mbx.ops));
7215
7216 /* Disable RSC when in SR-IOV mode */
7217 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7218 IXGBE_FLAG2_RSC_ENABLED);
7219 return;
7220 }
7221
7222 /* Oh oh */
396e799c
ET		 7223 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7224 "SRIOV disabled\n");
1cdd1ec8
GR		 7225 pci_disable_sriov(adapter->pdev);
7226
7227err_novfs:
7228 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7229 adapter->num_vfs = 0;
7230#endif /* CONFIG_PCI_IOV */
7231}
7232
9a799d71
AK		 7233/**
7234 * ixgbe_probe - Device Initialization Routine
7235 * @pdev: PCI device information struct
7236 * @ent: entry in ixgbe_pci_tbl
7237 *
7238 * Returns 0 on success, negative on failure
7239 *
7240 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7241 * The OS initialization, configuring of the adapter private structure,
7242 * and a hardware reset occur.
7243 **/
7244static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7245 const struct pci_device_id *ent)
9a799d71
AK		 7246{
7247 struct net_device *netdev;
7248 struct ixgbe_adapter *adapter = NULL;
7249 struct ixgbe_hw *hw;
7250 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7251 static int cards_found;
7252 int i, err, pci_using_dac;
289700db 7253 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7254 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7255#ifdef IXGBE_FCOE
7256 u16 device_caps;
7257#endif
289700db 7258 u32 eec;
9a799d71 7259
bded64a7
AG		 7260 /* Catch broken hardware that put the wrong VF device ID in
7261 * the PCIe SR-IOV capability.
7262 */
7263 if (pdev->is_virtfn) {
7264 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7265 pci_name(pdev), pdev->vendor, pdev->device);
7266 return -EINVAL;
7267 }
7268
9ce77666 7269 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7270 if (err)
7271 return err;
7272
1b507730
NN		 7273 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7274 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7275 pci_using_dac = 1;
7276 } else {
1b507730 7277 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7278 if (err) {
1b507730
NN		 7279 err = dma_set_coherent_mask(&pdev->dev,
7280 DMA_BIT_MASK(32));
9a799d71 7281 if (err) {
b8bc0421
DC		 7282 dev_err(&pdev->dev,
7283 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7284 goto err_dma;
7285 }
7286 }
7287 pci_using_dac = 0;
7288 }
7289
9ce77666 7290 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7291 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7292 if (err) {
b8bc0421
DC		 7293 dev_err(&pdev->dev,
7294 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7295 goto err_pci_reg;
7296 }
7297
19d5afd4 7298 pci_enable_pcie_error_reporting(pdev);
6fabd715 7299
9a799d71 7300 pci_set_master(pdev);
fb3b27bc 7301 pci_save_state(pdev);
9a799d71 7302
e901acd6
JF		 7303#ifdef CONFIG_IXGBE_DCB
7304 indices *= MAX_TRAFFIC_CLASS;
7305#endif
7306
c85a2618
JF		 7307 if (ii->mac == ixgbe_mac_82598EB)
7308 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7309 else
7310 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7311
e901acd6 7312#ifdef IXGBE_FCOE
c85a2618
JF		 7313 indices += min_t(unsigned int, num_possible_cpus(),
7314 IXGBE_MAX_FCOE_INDICES);
7315#endif
c85a2618 7316 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7317 if (!netdev) {
7318 err = -ENOMEM;
7319 goto err_alloc_etherdev;
7320 }
7321
9a799d71
AK		 7322 SET_NETDEV_DEV(netdev, &pdev->dev);
7323
9a799d71 7324 adapter = netdev_priv(netdev);
c60fbb00 7325 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7326
7327 adapter->netdev = netdev;
7328 adapter->pdev = pdev;
7329 hw = &adapter->hw;
7330 hw->back = adapter;
7331 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7332
05857980 7333 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7334 pci_resource_len(pdev, 0));
9a799d71
AK		 7335 if (!hw->hw_addr) {
7336 err = -EIO;
7337 goto err_ioremap;
7338 }
7339
7340 for (i = 1; i <= 5; i++) {
7341 if (pci_resource_len(pdev, i) == 0)
7342 continue;
7343 }
7344
0edc3527 7345 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7346 ixgbe_set_ethtool_ops(netdev);
9a799d71 7347 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7348 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7349
9a799d71
AK		 7350 adapter->bd_number = cards_found;
7351
9a799d71
AK		 7352 /* Setup hw api */
7353 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7354 hw->mac.type = ii->mac;
9a799d71 7355
c44ade9e
JB		 7356 /* EEPROM */
7357 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7358 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7359 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7360 if (!(eec & (1 << 8)))
7361 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7362
7363 /* PHY */
7364 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7365 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7366 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7367 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7368 hw->phy.mdio.mmds = 0;
7369 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7370 hw->phy.mdio.dev = netdev;
7371 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7372 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7373
8ca783ab 7374 ii->get_invariants(hw);
9a799d71
AK		 7375
7376 /* setup the private structure */
7377 err = ixgbe_sw_init(adapter);
7378 if (err)
7379 goto err_sw_init;
7380
e86bff0e 7381 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7382 switch (adapter->hw.mac.type) {
7383 case ixgbe_mac_82599EB:
7384 case ixgbe_mac_X540:
e86bff0e 7385 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7386 break;
7387 default:
7388 break;
7389 }
e86bff0e 7390
bf069c97
DS		 7391 /*
7392 * If there is a fan on this device and it has failed log the
7393 * failure.
7394 */
7395 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7396 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7397 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7398 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7399 }
7400
c44ade9e 7401 /* reset_hw fills in the perm_addr as well */
119fc60a 7402 hw->phy.reset_if_overtemp = true;
c44ade9e 7403 err = hw->mac.ops.reset_hw(hw);
119fc60a 7404 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7405 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7406 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7407 err = 0;
7408 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7409 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7410 "module type was detected.\n");
7411 e_dev_err("Reload the driver after installing a supported "
7412 "module.\n");
04f165ef
PW		 7413 goto err_sw_init;
7414 } else if (err) {
849c4542 7415 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7416 goto err_sw_init;
7417 }
7418
1cdd1ec8
GR		 7419 ixgbe_probe_vf(adapter, ii);
7420
396e799c 7421 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7422 NETIF_F_IP_CSUM |
7423 NETIF_F_HW_VLAN_TX |
7424 NETIF_F_HW_VLAN_RX |
7425 NETIF_F_HW_VLAN_FILTER;
9a799d71 7426
e9990a9c 7427 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7428 netdev->features |= NETIF_F_TSO;
9a799d71 7429 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7430 netdev->features |= NETIF_F_GRO;
67a74ee2 7431 netdev->features |= NETIF_F_RXHASH;
ad31c402 7432
58be7666
DS		 7433 switch (adapter->hw.mac.type) {
7434 case ixgbe_mac_82599EB:
7435 case ixgbe_mac_X540:
45a5ead0 7436 netdev->features |= NETIF_F_SCTP_CSUM;
58be7666
DS		 7437 break;
7438 default:
7439 break;
7440 }
45a5ead0 7441
ad31c402
JK		 7442 netdev->vlan_features |= NETIF_F_TSO;
7443 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7444 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7445 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7446 netdev->vlan_features |= NETIF_F_SG;
7447
1cdd1ec8
GR		 7448 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7449 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7450 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7451
7a6b6f51 7452#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7453 netdev->dcbnl_ops = &dcbnl_ops;
7454#endif
7455
eacd73f7 7456#ifdef IXGBE_FCOE
0d551589 7457 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7458 if (hw->mac.ops.get_device_caps) {
7459 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7460 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7461 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7462 }
7463 }
5e09d7f6
YZ		 7464 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7465 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7466 netdev->vlan_features |= NETIF_F_FSO;
7467 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7468 }
eacd73f7 7469#endif /* IXGBE_FCOE */
7b872a55 7470 if (pci_using_dac) {
9a799d71 7471 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7472 netdev->vlan_features |= NETIF_F_HIGHDMA;
7473 }
9a799d71 7474
0c19d6af 7475 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7476 netdev->features |= NETIF_F_LRO;
7477
9a799d71 7478 /* make sure the EEPROM is good */
c44ade9e 7479 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7480 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7481 err = -EIO;
7482 goto err_eeprom;
7483 }
7484
7485 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7486 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7487
c44ade9e 7488 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7489 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7490 err = -EIO;
7491 goto err_eeprom;
7492 }
7493
c6ecf39a
DS		 7494 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7495 if (hw->mac.ops.disable_tx_laser &&
7496 ((hw->phy.multispeed_fiber) ||
9f911707 7497 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7498 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7499 hw->mac.ops.disable_tx_laser(hw);
7500
7086400d
AD		 7501 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7502 (unsigned long) adapter);
9a799d71 7503
7086400d
AD		 7504 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7505 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7506
021230d4
AV		 7507 err = ixgbe_init_interrupt_scheme(adapter);
7508 if (err)
7509 goto err_sw_init;
9a799d71 7510
67a74ee2
ET		 7511 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7512 netdev->features &= ~NETIF_F_RXHASH;
7513
e8e26350 7514 switch (pdev->device) {
0b077fea
DS		 7515 case IXGBE_DEV_ID_82599_SFP:
7516 /* Only this subdevice supports WOL */
7517 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
9417c464 7518 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7519 break;
50d6c681
AD		 7520 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7521 /* All except this subdevice support WOL */
0b077fea 7522 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7523 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7524 break;
e8e26350 7525 case IXGBE_DEV_ID_82599_KX4:
9417c464 7526 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7527 break;
7528 default:
7529 adapter->wol = 0;
7530 break;
7531 }
e8e26350
PW		 7532 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7533
04f165ef
PW		 7534 /* pick up the PCI bus settings for reporting later */
7535 hw->mac.ops.get_bus_info(hw);
7536
9a799d71 7537 /* print bus type/speed/width info */
849c4542 7538 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7539 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7540 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7541 "Unknown"),
7542 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7543 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7544 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7545 "Unknown"),
7546 netdev->dev_addr);
289700db
DS		 7547
7548 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7549 if (err)
9fe93afd 7550 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7551 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7552 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7553 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7554 part_str);
e8e26350 7555 else
289700db
DS		 7556 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7557 hw->mac.type, hw->phy.type, part_str);
9a799d71 7558
e8e26350 7559 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7560 e_dev_warn("PCI-Express bandwidth available for this card is "
7561 "not sufficient for optimal performance.\n");
7562 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7563 "is required.\n");
0c254d86
AK		 7564 }
7565
34b0368c
PWJ		 7566 /* save off EEPROM version number */
7567 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7568
9a799d71 7569 /* reset the hardware with the new settings */
794caeb2 7570 err = hw->mac.ops.start_hw(hw);
c44ade9e 7571
794caeb2
PWJ		 7572 if (err == IXGBE_ERR_EEPROM_VERSION) {
7573 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7574 e_dev_warn("This device is a pre-production adapter/LOM. "
7575 "Please be aware there may be issues associated "
7576 "with your hardware. If you are experiencing "
7577 "problems please contact your Intel or hardware "
7578 "representative who provided you with this "
7579 "hardware.\n");
794caeb2 7580 }
9a799d71
AK		 7581 strcpy(netdev->name, "eth%d");
7582 err = register_netdev(netdev);
7583 if (err)
7584 goto err_register;
7585
54386467
JB		 7586 /* carrier off reporting is important to ethtool even BEFORE open */
7587 netif_carrier_off(netdev);
7588
5dd2d332 7589#ifdef CONFIG_IXGBE_DCA
652f093f 7590 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7591 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7592 ixgbe_setup_dca(adapter);
7593 }
7594#endif
1cdd1ec8 7595 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7596 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7597 for (i = 0; i < adapter->num_vfs; i++)
7598 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7599 }
7600
9612de92
ET		 7601 /* Inform firmware of driver version */
7602 if (hw->mac.ops.set_fw_drv_ver)
a38a104d
DS		 7603 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7604 FW_CEM_UNUSED_VER);
9612de92 7605
0365e6e4
PW		 7606 /* add san mac addr to netdev */
7607 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7608
849c4542 7609 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7610 cards_found++;
7611 return 0;
7612
7613err_register:
5eba3699 7614 ixgbe_release_hw_control(adapter);
7a921c93 7615 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7616err_sw_init:
7617err_eeprom:
1cdd1ec8
GR		 7618 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7619 ixgbe_disable_sriov(adapter);
7086400d 7620 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7621 iounmap(hw->hw_addr);
7622err_ioremap:
7623 free_netdev(netdev);
7624err_alloc_etherdev:
e8e9f696
JP		 7625 pci_release_selected_regions(pdev,
7626 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7627err_pci_reg:
7628err_dma:
7629 pci_disable_device(pdev);
7630 return err;
7631}
7632
7633/**
7634 * ixgbe_remove - Device Removal Routine
7635 * @pdev: PCI device information struct
7636 *
7637 * ixgbe_remove is called by the PCI subsystem to alert the driver
7638 * that it should release a PCI device. The could be caused by a
7639 * Hot-Plug event, or because the driver is going to be removed from
7640 * memory.
7641 **/
7642static void __devexit ixgbe_remove(struct pci_dev *pdev)
7643{
c60fbb00
AD		 7644 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7645 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7646
7647 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7648 cancel_work_sync(&adapter->service_task);
9a799d71 7649
5dd2d332 7650#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7651 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7652 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7653 dca_remove_requester(&pdev->dev);
7654 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7655 }
7656
7657#endif
332d4a7d
YZ		 7658#ifdef IXGBE_FCOE
7659 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7660 ixgbe_cleanup_fcoe(adapter);
7661
7662#endif /* IXGBE_FCOE */
0365e6e4
PW		 7663
7664 /* remove the added san mac */
7665 ixgbe_del_sanmac_netdev(netdev);
7666
c4900be0
DS		 7667 if (netdev->reg_state == NETREG_REGISTERED)
7668 unregister_netdev(netdev);
9a799d71 7669
1cdd1ec8
GR		 7670 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7671 ixgbe_disable_sriov(adapter);
7672
7a921c93 7673 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7674
021230d4 7675 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7676
7677 iounmap(adapter->hw.hw_addr);
9ce77666 7678 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7679 IORESOURCE_MEM));
9a799d71 7680
849c4542 7681 e_dev_info("complete\n");
021230d4 7682
9a799d71
AK		 7683 free_netdev(netdev);
7684
19d5afd4 7685 pci_disable_pcie_error_reporting(pdev);
6fabd715 7686
9a799d71
AK		 7687 pci_disable_device(pdev);
7688}
7689
7690/**
7691 * ixgbe_io_error_detected - called when PCI error is detected
7692 * @pdev: Pointer to PCI device
7693 * @state: The current pci connection state
7694 *
7695 * This function is called after a PCI bus error affecting
7696 * this device has been detected.
7697 */
7698static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7699 pci_channel_state_t state)
9a799d71 7700{
c60fbb00
AD		 7701 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7702 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7703
7704 netif_device_detach(netdev);
7705
3044b8d1
BL		 7706 if (state == pci_channel_io_perm_failure)
7707 return PCI_ERS_RESULT_DISCONNECT;
7708
9a799d71
AK		 7709 if (netif_running(netdev))
7710 ixgbe_down(adapter);
7711 pci_disable_device(pdev);
7712
b4617240 7713 /* Request a slot reset. */
9a799d71
AK		 7714 return PCI_ERS_RESULT_NEED_RESET;
7715}
7716
7717/**
7718 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7719 * @pdev: Pointer to PCI device
7720 *
7721 * Restart the card from scratch, as if from a cold-boot.
7722 */
7723static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7724{
c60fbb00 7725 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7726 pci_ers_result_t result;
7727 int err;
9a799d71 7728
9ce77666 7729 if (pci_enable_device_mem(pdev)) {
396e799c 7730 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7731 result = PCI_ERS_RESULT_DISCONNECT;
7732 } else {
7733 pci_set_master(pdev);
7734 pci_restore_state(pdev);
c0e1f68b 7735 pci_save_state(pdev);
9a799d71 7736
dd4d8ca6 7737 pci_wake_from_d3(pdev, false);
9a799d71 7738
6fabd715 7739 ixgbe_reset(adapter);
88512539 7740 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7741 result = PCI_ERS_RESULT_RECOVERED;
7742 }
7743
7744 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7745 if (err) {
849c4542
ET		 7746 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7747 "failed 0x%0x\n", err);
6fabd715
PWJ		 7748 /* non-fatal, continue */
7749 }
9a799d71 7750
6fabd715 7751 return result;
9a799d71
AK		 7752}
7753
7754/**
7755 * ixgbe_io_resume - called when traffic can start flowing again.
7756 * @pdev: Pointer to PCI device
7757 *
7758 * This callback is called when the error recovery driver tells us that
7759 * its OK to resume normal operation.
7760 */
7761static void ixgbe_io_resume(struct pci_dev *pdev)
7762{
c60fbb00
AD		 7763 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7764 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7765
7766 if (netif_running(netdev)) {
7767 if (ixgbe_up(adapter)) {
396e799c 7768 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7769 return;
7770 }
7771 }
7772
7773 netif_device_attach(netdev);
9a799d71
AK		 7774}
7775
7776static struct pci_error_handlers ixgbe_err_handler = {
7777 .error_detected = ixgbe_io_error_detected,
7778 .slot_reset = ixgbe_io_slot_reset,
7779 .resume = ixgbe_io_resume,
7780};
7781
7782static struct pci_driver ixgbe_driver = {
7783 .name = ixgbe_driver_name,
7784 .id_table = ixgbe_pci_tbl,
7785 .probe = ixgbe_probe,
7786 .remove = __devexit_p(ixgbe_remove),
7787#ifdef CONFIG_PM
7788 .suspend = ixgbe_suspend,
7789 .resume = ixgbe_resume,
7790#endif
7791 .shutdown = ixgbe_shutdown,
7792 .err_handler = &ixgbe_err_handler
7793};
7794
7795/**
7796 * ixgbe_init_module - Driver Registration Routine
7797 *
7798 * ixgbe_init_module is the first routine called when the driver is
7799 * loaded. All it does is register with the PCI subsystem.
7800 **/
7801static int __init ixgbe_init_module(void)
7802{
7803 int ret;
c7689578 7804 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7805 pr_info("%s\n", ixgbe_copyright);
9a799d71 7806
5dd2d332 7807#ifdef CONFIG_IXGBE_DCA
bd0362dd 7808 dca_register_notify(&dca_notifier);
bd0362dd 7809#endif
5dd2d332 7810
9a799d71
AK		 7811 ret = pci_register_driver(&ixgbe_driver);
7812 return ret;
7813}
b4617240 7814
9a799d71
AK		 7815module_init(ixgbe_init_module);
7816
7817/**
7818 * ixgbe_exit_module - Driver Exit Cleanup Routine
7819 *
7820 * ixgbe_exit_module is called just before the driver is removed
7821 * from memory.
7822 **/
7823static void __exit ixgbe_exit_module(void)
7824{
5dd2d332 7825#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7826 dca_unregister_notify(&dca_notifier);
7827#endif
9a799d71 7828 pci_unregister_driver(&ixgbe_driver);
1a51502b 7829 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7830}
bd0362dd 7831
5dd2d332 7832#ifdef CONFIG_IXGBE_DCA
bd0362dd 7833static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7834 void *p)
bd0362dd
JC		 7835{
7836 int ret_val;
7837
7838 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7839 __ixgbe_notify_dca);
bd0362dd
JC		 7840
7841 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7842}
b453368d 7843
5dd2d332 7844#endif /* CONFIG_IXGBE_DCA */
849c4542 7845
9a799d71
AK		 7846module_exit(ixgbe_exit_module);
7847
7848/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)