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ixgbe: cleanup flow director hash computation to improve performance
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
9a2d09cf 55#define DRV_VERSION "3.0.12-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
fe15e8e1 62 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 63};
64
65/* ixgbe_pci_tbl - PCI Device ID Table
66 *
67 * Wildcard entries (PCI_ANY_ID) should come last
68 * Last entry must be all 0s
69 *
70 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
71 * Class, Class Mask, private data (not used) }
72 */
a3aa1884 73static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 77 board_82598 },
9a799d71 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 79 board_82598 },
0befdb3e
JB		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
81 board_82598 },
3845bec0
PWJ		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
83 board_82598 },
9a799d71 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 85 board_82598 },
8d792cd9
JB		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
87 board_82598 },
c4900be0
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
91 board_82598 },
b95f5fcb
JB		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
93 board_82598 },
c4900be0
DS		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
95 board_82598 },
2f21bdd3
DS		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
97 board_82598 },
e8e26350
PW		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
99 board_82599 },
1fcf03e6
PWJ		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
101 board_82599 },
74757d49
DS		 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
103 board_82599 },
e8e26350
PW		 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
105 board_82599 },
38ad1c8e
DS		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
107 board_82599 },
dbfec662
DS		 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
109 board_82599 },
8911184f
PWJ		 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
111 board_82599 },
dbffcb21
DS		 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
113 board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
115 board_82599 },
119fc60a
MC		 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
117 board_82599 },
312eb931
DS		 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
119 board_82599 },
b93a2226 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 121 board_X540 },
9a799d71
AK		 122
123 /* required last entry */
124 {0, }
125};
126MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
127
5dd2d332 128#ifdef CONFIG_IXGBE_DCA
bd0362dd 129static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 130 void *p);
bd0362dd
JC		 131static struct notifier_block dca_notifier = {
132 .notifier_call = ixgbe_notify_dca,
133 .next = NULL,
134 .priority = 0
135};
136#endif
137
1cdd1ec8
GR		 138#ifdef CONFIG_PCI_IOV
139static unsigned int max_vfs;
140module_param(max_vfs, uint, 0);
e8e9f696
JP		 141MODULE_PARM_DESC(max_vfs,
142 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 143#endif /* CONFIG_PCI_IOV */
144
9a799d71
AK		 145MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
146MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
147MODULE_LICENSE("GPL");
148MODULE_VERSION(DRV_VERSION);
149
150#define DEFAULT_DEBUG_LEVEL_SHIFT 3
151
1cdd1ec8
GR		 152static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
153{
154 struct ixgbe_hw *hw = &adapter->hw;
155 u32 gcr;
156 u32 gpie;
157 u32 vmdctl;
158
159#ifdef CONFIG_PCI_IOV
160 /* disable iov and allow time for transactions to clear */
161 pci_disable_sriov(adapter->pdev);
162#endif
163
164 /* turn off device IOV mode */
165 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
166 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
167 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
168 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
169 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
170 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
171
172 /* set default pool back to 0 */
173 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
174 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
175 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
176
177 /* take a breather then clean up driver data */
178 msleep(100);
e8e9f696
JP		 179
180 kfree(adapter->vfinfo);
1cdd1ec8
GR		 181 adapter->vfinfo = NULL;
182
183 adapter->num_vfs = 0;
184 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
185}
186
dcd79aeb
TI		 187struct ixgbe_reg_info {
188 u32 ofs;
189 char *name;
190};
191
192static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
193
194 /* General Registers */
195 {IXGBE_CTRL, "CTRL"},
196 {IXGBE_STATUS, "STATUS"},
197 {IXGBE_CTRL_EXT, "CTRL_EXT"},
198
199 /* Interrupt Registers */
200 {IXGBE_EICR, "EICR"},
201
202 /* RX Registers */
203 {IXGBE_SRRCTL(0), "SRRCTL"},
204 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
205 {IXGBE_RDLEN(0), "RDLEN"},
206 {IXGBE_RDH(0), "RDH"},
207 {IXGBE_RDT(0), "RDT"},
208 {IXGBE_RXDCTL(0), "RXDCTL"},
209 {IXGBE_RDBAL(0), "RDBAL"},
210 {IXGBE_RDBAH(0), "RDBAH"},
211
212 /* TX Registers */
213 {IXGBE_TDBAL(0), "TDBAL"},
214 {IXGBE_TDBAH(0), "TDBAH"},
215 {IXGBE_TDLEN(0), "TDLEN"},
216 {IXGBE_TDH(0), "TDH"},
217 {IXGBE_TDT(0), "TDT"},
218 {IXGBE_TXDCTL(0), "TXDCTL"},
219
220 /* List Terminator */
221 {}
222};
223
224
225/*
226 * ixgbe_regdump - register printout routine
227 */
228static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
229{
230 int i = 0, j = 0;
231 char rname[16];
232 u32 regs[64];
233
234 switch (reginfo->ofs) {
235 case IXGBE_SRRCTL(0):
236 for (i = 0; i < 64; i++)
237 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
238 break;
239 case IXGBE_DCA_RXCTRL(0):
240 for (i = 0; i < 64; i++)
241 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
242 break;
243 case IXGBE_RDLEN(0):
244 for (i = 0; i < 64; i++)
245 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
246 break;
247 case IXGBE_RDH(0):
248 for (i = 0; i < 64; i++)
249 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
250 break;
251 case IXGBE_RDT(0):
252 for (i = 0; i < 64; i++)
253 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
254 break;
255 case IXGBE_RXDCTL(0):
256 for (i = 0; i < 64; i++)
257 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
258 break;
259 case IXGBE_RDBAL(0):
260 for (i = 0; i < 64; i++)
261 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
262 break;
263 case IXGBE_RDBAH(0):
264 for (i = 0; i < 64; i++)
265 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
266 break;
267 case IXGBE_TDBAL(0):
268 for (i = 0; i < 64; i++)
269 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
270 break;
271 case IXGBE_TDBAH(0):
272 for (i = 0; i < 64; i++)
273 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
274 break;
275 case IXGBE_TDLEN(0):
276 for (i = 0; i < 64; i++)
277 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
278 break;
279 case IXGBE_TDH(0):
280 for (i = 0; i < 64; i++)
281 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
282 break;
283 case IXGBE_TDT(0):
284 for (i = 0; i < 64; i++)
285 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
286 break;
287 case IXGBE_TXDCTL(0):
288 for (i = 0; i < 64; i++)
289 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
290 break;
291 default:
c7689578 292 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 293 IXGBE_READ_REG(hw, reginfo->ofs));
294 return;
295 }
296
297 for (i = 0; i < 8; i++) {
298 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 299 pr_err("%-15s", rname);
dcd79aeb 300 for (j = 0; j < 8; j++)
c7689578
JP		 301 pr_cont(" %08x", regs[i*8+j]);
302 pr_cont("\n");
dcd79aeb
TI		 303 }
304
305}
306
307/*
308 * ixgbe_dump - Print registers, tx-rings and rx-rings
309 */
310static void ixgbe_dump(struct ixgbe_adapter *adapter)
311{
312 struct net_device *netdev = adapter->netdev;
313 struct ixgbe_hw *hw = &adapter->hw;
314 struct ixgbe_reg_info *reginfo;
315 int n = 0;
316 struct ixgbe_ring *tx_ring;
317 struct ixgbe_tx_buffer *tx_buffer_info;
318 union ixgbe_adv_tx_desc *tx_desc;
319 struct my_u0 { u64 a; u64 b; } *u0;
320 struct ixgbe_ring *rx_ring;
321 union ixgbe_adv_rx_desc *rx_desc;
322 struct ixgbe_rx_buffer *rx_buffer_info;
323 u32 staterr;
324 int i = 0;
325
326 if (!netif_msg_hw(adapter))
327 return;
328
329 /* Print netdevice Info */
330 if (netdev) {
331 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 332 pr_info("Device Name state "
dcd79aeb 333 "trans_start last_rx\n");
c7689578
JP		 334 pr_info("%-15s %016lX %016lX %016lX\n",
335 netdev->name,
336 netdev->state,
337 netdev->trans_start,
338 netdev->last_rx);
dcd79aeb
TI		 339 }
340
341 /* Print Registers */
342 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 343 pr_info(" Register Name Value\n");
dcd79aeb
TI		 344 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
345 reginfo->name; reginfo++) {
346 ixgbe_regdump(hw, reginfo);
347 }
348
349 /* Print TX Ring Summary */
350 if (!netdev || !netif_running(netdev))
351 goto exit;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 354 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 355 for (n = 0; n < adapter->num_tx_queues; n++) {
356 tx_ring = adapter->tx_ring[n];
357 tx_buffer_info =
358 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 359 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 360 n, tx_ring->next_to_use, tx_ring->next_to_clean,
361 (u64)tx_buffer_info->dma,
362 tx_buffer_info->length,
363 tx_buffer_info->next_to_watch,
364 (u64)tx_buffer_info->time_stamp);
365 }
366
367 /* Print TX Rings */
368 if (!netif_msg_tx_done(adapter))
369 goto rx_ring_summary;
370
371 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
372
373 /* Transmit Descriptor Formats
374 *
375 * Advanced Transmit Descriptor
376 * +--------------------------------------------------------------+
377 * 0 | Buffer Address [63:0] |
378 * +--------------------------------------------------------------+
379 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
380 * +--------------------------------------------------------------+
381 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
382 */
383
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
c7689578
JP		 386 pr_info("------------------------------------\n");
387 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
388 pr_info("------------------------------------\n");
389 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 390 "[PlPOIdStDDt Ln] [bi->dma ] "
391 "leng ntw timestamp bi->skb\n");
392
393 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 394 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 395 tx_buffer_info = &tx_ring->tx_buffer_info[i];
396 u0 = (struct my_u0 *)tx_desc;
c7689578 397 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 398 " %04X %3X %016llX %p", i,
399 le64_to_cpu(u0->a),
400 le64_to_cpu(u0->b),
401 (u64)tx_buffer_info->dma,
402 tx_buffer_info->length,
403 tx_buffer_info->next_to_watch,
404 (u64)tx_buffer_info->time_stamp,
405 tx_buffer_info->skb);
406 if (i == tx_ring->next_to_use &&
407 i == tx_ring->next_to_clean)
c7689578 408 pr_cont(" NTC/U\n");
dcd79aeb 409 else if (i == tx_ring->next_to_use)
c7689578 410 pr_cont(" NTU\n");
dcd79aeb 411 else if (i == tx_ring->next_to_clean)
c7689578 412 pr_cont(" NTC\n");
dcd79aeb 413 else
c7689578 414 pr_cont("\n");
dcd79aeb
TI		 415
416 if (netif_msg_pktdata(adapter) &&
417 tx_buffer_info->dma != 0)
418 print_hex_dump(KERN_INFO, "",
419 DUMP_PREFIX_ADDRESS, 16, 1,
420 phys_to_virt(tx_buffer_info->dma),
421 tx_buffer_info->length, true);
422 }
423 }
424
425 /* Print RX Rings Summary */
426rx_ring_summary:
427 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 428 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 429 for (n = 0; n < adapter->num_rx_queues; n++) {
430 rx_ring = adapter->rx_ring[n];
c7689578
JP		 431 pr_info("%5d %5X %5X\n",
432 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 433 }
434
435 /* Print RX Rings */
436 if (!netif_msg_rx_status(adapter))
437 goto exit;
438
439 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
440
441 /* Advanced Receive Descriptor (Read) Format
442 * 63 1 0
443 * +-----------------------------------------------------+
444 * 0 | Packet Buffer Address [63:1] |A0/NSE|
445 * +----------------------------------------------+------+
446 * 8 | Header Buffer Address [63:1] | DD |
447 * +-----------------------------------------------------+
448 *
449 *
450 * Advanced Receive Descriptor (Write-Back) Format
451 *
452 * 63 48 47 32 31 30 21 20 16 15 4 3 0
453 * +------------------------------------------------------+
454 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
455 * | Checksum Ident | | | | Type | Type |
456 * +------------------------------------------------------+
457 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
458 * +------------------------------------------------------+
459 * 63 48 47 32 31 20 19 0
460 */
461 for (n = 0; n < adapter->num_rx_queues; n++) {
462 rx_ring = adapter->rx_ring[n];
c7689578
JP		 463 pr_info("------------------------------------\n");
464 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
465 pr_info("------------------------------------\n");
466 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 467 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
468 "<-- Adv Rx Read format\n");
c7689578 469 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 470 "[vl er S cks ln] ---------------- [bi->skb] "
471 "<-- Adv Rx Write-Back format\n");
472
473 for (i = 0; i < rx_ring->count; i++) {
474 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 475 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 476 u0 = (struct my_u0 *)rx_desc;
477 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
478 if (staterr & IXGBE_RXD_STAT_DD) {
479 /* Descriptor Done */
c7689578 480 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 481 "%016llX ---------------- %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 rx_buffer_info->skb);
485 } else {
c7689578 486 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 487 "%016llX %016llX %p", i,
488 le64_to_cpu(u0->a),
489 le64_to_cpu(u0->b),
490 (u64)rx_buffer_info->dma,
491 rx_buffer_info->skb);
492
493 if (netif_msg_pktdata(adapter)) {
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(rx_buffer_info->dma),
497 rx_ring->rx_buf_len, true);
498
499 if (rx_ring->rx_buf_len
500 < IXGBE_RXBUFFER_2048)
501 print_hex_dump(KERN_INFO, "",
502 DUMP_PREFIX_ADDRESS, 16, 1,
503 phys_to_virt(
504 rx_buffer_info->page_dma +
505 rx_buffer_info->page_offset
506 ),
507 PAGE_SIZE/2, true);
508 }
509 }
510
511 if (i == rx_ring->next_to_use)
c7689578 512 pr_cont(" NTU\n");
dcd79aeb 513 else if (i == rx_ring->next_to_clean)
c7689578 514 pr_cont(" NTC\n");
dcd79aeb 515 else
c7689578 516 pr_cont("\n");
dcd79aeb
TI		 517
518 }
519 }
520
521exit:
522 return;
523}
524
5eba3699
AV		 525static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
526{
527 u32 ctrl_ext;
528
529 /* Let firmware take over control of h/w */
530 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 532 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 533}
534
535static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
536{
537 u32 ctrl_ext;
538
539 /* Let firmware know the driver has taken over */
540 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 542 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 543}
9a799d71 544
e8e26350
PW		 545/*
546 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
547 * @adapter: pointer to adapter struct
548 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
549 * @queue: queue to map the corresponding interrupt to
550 * @msix_vector: the vector to map to the corresponding queue
551 *
552 */
553static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 554 u8 queue, u8 msix_vector)
9a799d71
AK		 555{
556 u32 ivar, index;
e8e26350
PW		 557 struct ixgbe_hw *hw = &adapter->hw;
558 switch (hw->mac.type) {
559 case ixgbe_mac_82598EB:
560 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
561 if (direction == -1)
562 direction = 0;
563 index = (((direction * 64) + queue) >> 2) & 0x1F;
564 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
565 ivar &= ~(0xFF << (8 * (queue & 0x3)));
566 ivar |= (msix_vector << (8 * (queue & 0x3)));
567 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
568 break;
569 case ixgbe_mac_82599EB:
b93a2226 570 case ixgbe_mac_X540:
e8e26350
PW		 571 if (direction == -1) {
572 /* other causes */
573 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
574 index = ((queue & 1) * 8);
575 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
576 ivar &= ~(0xFF << index);
577 ivar |= (msix_vector << index);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
579 break;
580 } else {
581 /* tx or rx causes */
582 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
583 index = ((16 * (queue & 1)) + (8 * direction));
584 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
585 ivar &= ~(0xFF << index);
586 ivar |= (msix_vector << index);
587 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
588 break;
589 }
590 default:
591 break;
592 }
9a799d71
AK		 593}
594
fe49f04a 595static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 596 u64 qmask)
fe49f04a
AD		 597{
598 u32 mask;
599
bd508178
AD		 600 switch (adapter->hw.mac.type) {
601 case ixgbe_mac_82598EB:
fe49f04a
AD		 602 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 604 break;
605 case ixgbe_mac_82599EB:
b93a2226 606 case ixgbe_mac_X540:
fe49f04a
AD		 607 mask = (qmask & 0xFFFFFFFF);
608 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
609 mask = (qmask >> 32);
610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 611 break;
612 default:
613 break;
fe49f04a
AD		 614 }
615}
616
b6ec895e
AD		 617void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
618 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 619{
e5a43549
AD		 620 if (tx_buffer_info->dma) {
621 if (tx_buffer_info->mapped_as_page)
b6ec895e 622 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 623 tx_buffer_info->dma,
624 tx_buffer_info->length,
1b507730 625 DMA_TO_DEVICE);
e5a43549 626 else
b6ec895e 627 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 628 tx_buffer_info->dma,
629 tx_buffer_info->length,
1b507730 630 DMA_TO_DEVICE);
e5a43549
AD		 631 tx_buffer_info->dma = 0;
632 }
9a799d71
AK		 633 if (tx_buffer_info->skb) {
634 dev_kfree_skb_any(tx_buffer_info->skb);
635 tx_buffer_info->skb = NULL;
636 }
44df32c5 637 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 638 /* tx_buffer_info must be completely set up in the transmit path */
639}
640
26f23d82 641/**
c84d324c
JF		 642 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
643 * @adapter: driver private struct
644 * @index: reg idx of queue to query (0-127)
26f23d82 645 *
c84d324c
JF		 646 * Helper function to determine the traffic index for a paticular
647 * register index.
26f23d82 648 *
c84d324c 649 * Returns : a tc index for use in range 0-7, or 0-3
26f23d82 650 */
c84d324c 651u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
26f23d82 652{
c84d324c
JF		 653 int tc = -1;
654 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
26f23d82 655
c84d324c
JF		 656 /* if DCB is not enabled the queues have no TC */
657 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
658 return tc;
26f23d82 659
c84d324c
JF		 660 /* check valid range */
661 if (reg_idx >= adapter->hw.mac.max_tx_queues)
662 return tc;
663
664 switch (adapter->hw.mac.type) {
665 case ixgbe_mac_82598EB:
666 tc = reg_idx >> 2;
667 break;
668 default:
669 if (dcb_i != 4 && dcb_i != 8)
6837e895 670 break;
c84d324c
JF		 671
672 /* if VMDq is enabled the lowest order bits determine TC */
673 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
674 IXGBE_FLAG_VMDQ_ENABLED)) {
675 tc = reg_idx & (dcb_i - 1);
676 break;
677 }
678
679 /*
680 * Convert the reg_idx into the correct TC. This bitmask
681 * targets the last full 32 ring traffic class and assigns
682 * it a value of 1. From there the rest of the rings are
683 * based on shifting the mask further up to include the
684 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
685 * will only ever be 8 or 4 and that reg_idx will never
686 * be greater then 128. The code without the power of 2
687 * optimizations would be:
688 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
689 */
690 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
691 tc >>= 9 - (reg_idx >> 5);
692 }
693
694 return tc;
695}
696
697static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
698{
699 struct ixgbe_hw *hw = &adapter->hw;
700 struct ixgbe_hw_stats *hwstats = &adapter->stats;
701 u32 data = 0;
702 u32 xoff[8] = {0};
703 int i;
704
705 if ((hw->fc.current_mode == ixgbe_fc_full) ||
706 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
707 switch (hw->mac.type) {
708 case ixgbe_mac_82598EB:
709 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 710 break;
711 default:
c84d324c
JF		 712 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
713 }
714 hwstats->lxoffrxc += data;
715
716 /* refill credits (no tx hang) if we received xoff */
717 if (!data)
718 return;
719
720 for (i = 0; i < adapter->num_tx_queues; i++)
721 clear_bit(__IXGBE_HANG_CHECK_ARMED,
722 &adapter->tx_ring[i]->state);
723 return;
724 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
725 return;
726
727 /* update stats for each tc, only valid with PFC enabled */
728 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
729 switch (hw->mac.type) {
730 case ixgbe_mac_82598EB:
731 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 732 break;
c84d324c
JF		 733 default:
734 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 735 }
c84d324c
JF		 736 hwstats->pxoffrxc[i] += xoff[i];
737 }
738
739 /* disarm tx queues that have received xoff frames */
740 for (i = 0; i < adapter->num_tx_queues; i++) {
741 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
742 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
743
744 if (xoff[tc])
745 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 746 }
26f23d82
YZ		 747}
748
c84d324c 749static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 750{
c84d324c
JF		 751 return ring->tx_stats.completed;
752}
753
754static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
755{
756 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 757 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 758
c84d324c
JF		 759 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
760 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
761
762 if (head != tail)
763 return (head < tail) ?
764 tail - head : (tail + ring->count - head);
765
766 return 0;
767}
768
769static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
770{
771 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
772 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
773 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
774 bool ret = false;
775
7d637bcc 776 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 777
778 /*
779 * Check for a hung queue, but be thorough. This verifies
780 * that a transmit has been completed since the previous
781 * check AND there is at least one packet pending. The
782 * ARMED bit is set to indicate a potential hang. The
783 * bit is cleared if a pause frame is received to remove
784 * false hang detection due to PFC or 802.3x frames. By
785 * requiring this to fail twice we avoid races with
786 * pfc clearing the ARMED bit and conditions where we
787 * run the check_tx_hang logic with a transmit completion
788 * pending but without time to complete it yet.
789 */
790 if ((tx_done_old == tx_done) && tx_pending) {
791 /* make sure it is true for two checks in a row */
792 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
793 &tx_ring->state);
794 } else {
795 /* update completed stats and continue */
796 tx_ring->tx_stats.tx_done_old = tx_done;
797 /* reset the countdown */
798 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 799 }
800
c84d324c 801 return ret;
9a799d71
AK		 802}
803
b4617240
PW		 804#define IXGBE_MAX_TXD_PWR 14
805#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 806
807/* Tx Descriptors needed, worst case */
808#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
809 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
810#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 811 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 812
e01c31a5
JB		 813static void ixgbe_tx_timeout(struct net_device *netdev);
814
9a799d71
AK		 815/**
816 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 817 * @q_vector: structure containing interrupt and ring information
e01c31a5 818 * @tx_ring: tx ring to clean
9a799d71 819 **/
fe49f04a 820static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 821 struct ixgbe_ring *tx_ring)
9a799d71 822{
fe49f04a 823 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 824 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
825 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 826 unsigned int total_bytes = 0, total_packets = 0;
b953799e 827 u16 i, eop, count = 0;
9a799d71
AK		 828
829 i = tx_ring->next_to_clean;
12207e49 830 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 831 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 832
833 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 834 (count < tx_ring->work_limit)) {
12207e49 835 bool cleaned = false;
2d0bb1c1 836 rmb(); /* read buffer_info after eop_desc */
12207e49 837 for ( ; !cleaned; count++) {
31f05a2d 838 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 839 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 840
841 tx_desc->wb.status = 0;
12207e49 842 cleaned = (i == eop);
9a799d71 843
8ad494b0
AD		 844 i++;
845 if (i == tx_ring->count)
846 i = 0;
e01c31a5 847
8ad494b0
AD		 848 if (cleaned && tx_buffer_info->skb) {
849 total_bytes += tx_buffer_info->bytecount;
850 total_packets += tx_buffer_info->gso_segs;
e092be60 851 }
e01c31a5 852
b6ec895e 853 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 854 tx_buffer_info);
e01c31a5 855 }
12207e49 856
c84d324c 857 tx_ring->tx_stats.completed++;
12207e49 858 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 859 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 860 }
861
9a799d71 862 tx_ring->next_to_clean = i;
b953799e
AD		 863 tx_ring->total_bytes += total_bytes;
864 tx_ring->total_packets += total_packets;
865 u64_stats_update_begin(&tx_ring->syncp);
866 tx_ring->stats.packets += total_packets;
867 tx_ring->stats.bytes += total_bytes;
868 u64_stats_update_end(&tx_ring->syncp);
869
c84d324c
JF		 870 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
871 /* schedule immediate reset if we believe we hung */
872 struct ixgbe_hw *hw = &adapter->hw;
873 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
874 e_err(drv, "Detected Tx Unit Hang\n"
875 " Tx Queue <%d>\n"
876 " TDH, TDT <%x>, <%x>\n"
877 " next_to_use <%x>\n"
878 " next_to_clean <%x>\n"
879 "tx_buffer_info[next_to_clean]\n"
880 " time_stamp <%lx>\n"
881 " jiffies <%lx>\n",
882 tx_ring->queue_index,
883 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
884 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
885 tx_ring->next_to_use, eop,
886 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
887
888 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
889
890 e_info(probe,
891 "tx hang %d detected on queue %d, resetting adapter\n",
892 adapter->tx_timeout_count + 1, tx_ring->queue_index);
893
b953799e 894 /* schedule immediate reset if we believe we hung */
b953799e
AD		 895 ixgbe_tx_timeout(adapter->netdev);
896
897 /* the adapter is about to reset, no point in enabling stuff */
898 return true;
899 }
9a799d71 900
e092be60 901#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 902 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 903 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 904 /* Make sure that anybody stopping the queue after this
905 * sees the new next_to_clean.
906 */
907 smp_mb();
fc77dc3c 908 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 909 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 910 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 911 ++tx_ring->tx_stats.restart_queue;
30eba97a 912 }
e092be60 913 }
9a799d71 914
807540ba 915 return count < tx_ring->work_limit;
9a799d71
AK		 916}
917
5dd2d332 918#ifdef CONFIG_IXGBE_DCA
bd0362dd 919static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 920 struct ixgbe_ring *rx_ring,
921 int cpu)
bd0362dd 922{
33cf09c9 923 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 924 u32 rxctrl;
33cf09c9
AD		 925 u8 reg_idx = rx_ring->reg_idx;
926
927 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
928 switch (hw->mac.type) {
929 case ixgbe_mac_82598EB:
930 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
931 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
932 break;
933 case ixgbe_mac_82599EB:
b93a2226 934 case ixgbe_mac_X540:
33cf09c9
AD		 935 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
936 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
937 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
938 break;
939 default:
940 break;
bd0362dd 941 }
33cf09c9
AD		 942 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
943 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
944 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
945 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
946 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
947 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 948}
949
950static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 951 struct ixgbe_ring *tx_ring,
952 int cpu)
bd0362dd 953{
33cf09c9 954 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 955 u32 txctrl;
33cf09c9
AD		 956 u8 reg_idx = tx_ring->reg_idx;
957
958 switch (hw->mac.type) {
959 case ixgbe_mac_82598EB:
960 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
961 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
962 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
963 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
964 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
965 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
966 break;
967 case ixgbe_mac_82599EB:
b93a2226 968 case ixgbe_mac_X540:
33cf09c9
AD		 969 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
970 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
971 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
972 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
973 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
974 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
975 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
976 break;
977 default:
978 break;
979 }
980}
981
982static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
983{
984 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 985 int cpu = get_cpu();
33cf09c9
AD		 986 long r_idx;
987 int i;
bd0362dd 988
33cf09c9
AD		 989 if (q_vector->cpu == cpu)
990 goto out_no_update;
991
992 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
993 for (i = 0; i < q_vector->txr_count; i++) {
994 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
995 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
996 r_idx + 1);
bd0362dd 997 }
33cf09c9
AD		 998
999 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1000 for (i = 0; i < q_vector->rxr_count; i++) {
1001 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1002 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1003 r_idx + 1);
1004 }
1005
1006 q_vector->cpu = cpu;
1007out_no_update:
bd0362dd
JC		 1008 put_cpu();
1009}
1010
1011static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1012{
33cf09c9 1013 int num_q_vectors;
bd0362dd
JC		 1014 int i;
1015
1016 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1017 return;
1018
e35ec126
AD		 1019 /* always use CB2 mode, difference is masked in the CB driver */
1020 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1021
33cf09c9
AD		 1022 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1023 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1024 else
1025 num_q_vectors = 1;
1026
1027 for (i = 0; i < num_q_vectors; i++) {
1028 adapter->q_vector[i]->cpu = -1;
1029 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1030 }
1031}
1032
1033static int __ixgbe_notify_dca(struct device *dev, void *data)
1034{
c60fbb00 1035 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1036 unsigned long event = *(unsigned long *)data;
1037
33cf09c9
AD		 1038 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1039 return 0;
1040
bd0362dd
JC		 1041 switch (event) {
1042 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1043 /* if we're already enabled, don't do it again */
1044 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1045 break;
652f093f 1046 if (dca_add_requester(dev) == 0) {
96b0e0f6 1047 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1048 ixgbe_setup_dca(adapter);
1049 break;
1050 }
1051 /* Fall Through since DCA is disabled. */
1052 case DCA_PROVIDER_REMOVE:
1053 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1054 dca_remove_requester(dev);
1055 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1056 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1057 }
1058 break;
1059 }
1060
652f093f 1061 return 0;
bd0362dd
JC		 1062}
1063
5dd2d332 1064#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 1065/**
1066 * ixgbe_receive_skb - Send a completed packet up the stack
1067 * @adapter: board private structure
1068 * @skb: packet to send up
177db6ff
MC		 1069 * @status: hardware indication of status of receive
1070 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1071 * @rx_desc: rx descriptor
9a799d71 1072 **/
78b6f4ce 1073static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1074 struct sk_buff *skb, u8 status,
1075 struct ixgbe_ring *ring,
1076 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1077{
78b6f4ce
HX		 1078 struct ixgbe_adapter *adapter = q_vector->adapter;
1079 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1080 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1081 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1082
f62bbb5e
JG		 1083 if (is_vlan && (tag & VLAN_VID_MASK))
1084 __vlan_hwaccel_put_tag(skb, tag);
1085
1086 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1087 napi_gro_receive(napi, skb);
1088 else
1089 netif_rx(skb);
9a799d71
AK		 1090}
1091
e59bd25d
AV		 1092/**
1093 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1094 * @adapter: address of board private structure
1095 * @status_err: hardware indication of status of receive
1096 * @skb: skb currently being received and modified
1097 **/
9a799d71 1098static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1099 union ixgbe_adv_rx_desc *rx_desc,
1100 struct sk_buff *skb)
9a799d71 1101{
8bae1b2b
DS		 1102 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1103
bc8acf2c 1104 skb_checksum_none_assert(skb);
9a799d71 1105
712744be
JB		 1106 /* Rx csum disabled */
1107 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1108 return;
e59bd25d
AV		 1109
1110 /* if IP and error */
1111 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1112 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1113 adapter->hw_csum_rx_error++;
1114 return;
1115 }
e59bd25d
AV		 1116
1117 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1118 return;
1119
1120 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1121 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122
1123 /*
1124 * 82599 errata, UDP frames with a 0 checksum can be marked as
1125 * checksum errors.
1126 */
1127 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1128 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1129 return;
1130
e59bd25d
AV		 1131 adapter->hw_csum_rx_error++;
1132 return;
1133 }
1134
9a799d71 1135 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1136 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1137}
1138
84ea2591 1139static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1140{
1141 /*
1142 * Force memory writes to complete before letting h/w
1143 * know there are new descriptors to fetch. (Only
1144 * applicable for weak-ordered memory model archs,
1145 * such as IA-64).
1146 */
1147 wmb();
84ea2591 1148 writel(val, rx_ring->tail);
e8e26350
PW		 1149}
1150
9a799d71
AK		 1151/**
1152 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1153 * @rx_ring: ring to place buffers on
1154 * @cleaned_count: number of buffers to replace
9a799d71 1155 **/
fc77dc3c 1156void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1157{
9a799d71 1158 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1159 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1160 struct sk_buff *skb;
1161 u16 i = rx_ring->next_to_use;
9a799d71 1162
fc77dc3c
AD		 1163 /* do nothing if no valid netdev defined */
1164 if (!rx_ring->netdev)
1165 return;
1166
9a799d71 1167 while (cleaned_count--) {
31f05a2d 1168 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1169 bi = &rx_ring->rx_buffer_info[i];
1170 skb = bi->skb;
9a799d71 1171
d5f398ed 1172 if (!skb) {
fc77dc3c 1173 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1174 rx_ring->rx_buf_len);
9a799d71 1175 if (!skb) {
5b7da515 1176 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1177 goto no_buffers;
1178 }
d716a7d8
AD		 1179 /* initialize queue mapping */
1180 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1181 bi->skb = skb;
d716a7d8 1182 }
9a799d71 1183
d716a7d8 1184 if (!bi->dma) {
b6ec895e 1185 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1186 skb->data,
e8e9f696 1187 rx_ring->rx_buf_len,
1b507730 1188 DMA_FROM_DEVICE);
b6ec895e 1189 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1190 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1191 bi->dma = 0;
1192 goto no_buffers;
1193 }
9a799d71 1194 }
d5f398ed 1195
7d637bcc 1196 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1197 if (!bi->page) {
fc77dc3c 1198 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1199 if (!bi->page) {
5b7da515 1200 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1201 goto no_buffers;
1202 }
1203 }
1204
1205 if (!bi->page_dma) {
1206 /* use a half page if we're re-using */
1207 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1208 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1209 bi->page,
1210 bi->page_offset,
1211 PAGE_SIZE / 2,
1212 DMA_FROM_DEVICE);
b6ec895e 1213 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1214 bi->page_dma)) {
5b7da515 1215 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1216 bi->page_dma = 0;
1217 goto no_buffers;
1218 }
1219 }
1220
1221 /* Refresh the desc even if buffer_addrs didn't change
1222 * because each write-back erases this info. */
3a581073
JB		 1223 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1224 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1225 } else {
3a581073 1226 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1227 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1228 }
1229
1230 i++;
1231 if (i == rx_ring->count)
1232 i = 0;
9a799d71 1233 }
7c6e0a43 1234
9a799d71
AK		 1235no_buffers:
1236 if (rx_ring->next_to_use != i) {
1237 rx_ring->next_to_use = i;
84ea2591 1238 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1239 }
1240}
1241
c267fc16 1242static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1243{
c267fc16
AD		 1244 /* HW will not DMA in data larger than the given buffer, even if it
1245 * parses the (NFS, of course) header to be larger. In that case, it
1246 * fills the header buffer and spills the rest into the page.
1247 */
1248 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1249 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1250 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1251 if (hlen > IXGBE_RX_HDR_SIZE)
1252 hlen = IXGBE_RX_HDR_SIZE;
1253 return hlen;
7c6e0a43
JB		 1254}
1255
f8212f97
AD		 1256/**
1257 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1258 * @skb: pointer to the last skb in the rsc queue
1259 *
1260 * This function changes a queue full of hw rsc buffers into a completed
1261 * packet. It uses the ->prev pointers to find the first packet and then
1262 * turns it into the frag list owner.
1263 **/
aa80175a 1264static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1265{
1266 unsigned int frag_list_size = 0;
aa80175a 1267 unsigned int skb_cnt = 1;
f8212f97
AD		 1268
1269 while (skb->prev) {
1270 struct sk_buff *prev = skb->prev;
1271 frag_list_size += skb->len;
1272 skb->prev = NULL;
1273 skb = prev;
aa80175a 1274 skb_cnt++;
f8212f97
AD		 1275 }
1276
1277 skb_shinfo(skb)->frag_list = skb->next;
1278 skb->next = NULL;
1279 skb->len += frag_list_size;
1280 skb->data_len += frag_list_size;
1281 skb->truesize += frag_list_size;
aa80175a
AD		 1282 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1283
f8212f97
AD		 1284 return skb;
1285}
1286
aa80175a
AD		 1287static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1288{
1289 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1290 IXGBE_RXDADV_RSCCNT_MASK);
1291}
43634e82 1292
c267fc16 1293static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1294 struct ixgbe_ring *rx_ring,
1295 int *work_done, int work_to_do)
9a799d71 1296{
78b6f4ce 1297 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1298 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1299 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1300 struct sk_buff *skb;
d2f4fbe2 1301 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1302 const int current_node = numa_node_id();
3d8fd385
YZ		 1303#ifdef IXGBE_FCOE
1304 int ddp_bytes = 0;
1305#endif /* IXGBE_FCOE */
c267fc16
AD		 1306 u32 staterr;
1307 u16 i;
1308 u16 cleaned_count = 0;
aa80175a 1309 bool pkt_is_rsc = false;
9a799d71
AK		 1310
1311 i = rx_ring->next_to_clean;
31f05a2d 1312 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1313 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1314
1315 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1316 u32 upper_len = 0;
9a799d71 1317
3c945e5b 1318 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1319
c267fc16
AD		 1320 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1321
9a799d71 1322 skb = rx_buffer_info->skb;
9a799d71 1323 rx_buffer_info->skb = NULL;
c267fc16 1324 prefetch(skb->data);
9a799d71 1325
c267fc16 1326 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1327 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1328
1329 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1330 if (rx_buffer_info->dma) {
c267fc16 1331 u16 hlen;
aa80175a 1332 if (pkt_is_rsc &&
c267fc16
AD		 1333 !(staterr & IXGBE_RXD_STAT_EOP) &&
1334 !skb->prev) {
43634e82
MC		 1335 /*
1336 * When HWRSC is enabled, delay unmapping
1337 * of the first packet. It carries the
1338 * header information, HW may still
1339 * access the header after the writeback.
1340 * Only unmap it when EOP is reached
1341 */
e8171aaa 1342 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1343 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1344 } else {
b6ec895e 1345 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1346 rx_buffer_info->dma,
1347 rx_ring->rx_buf_len,
1348 DMA_FROM_DEVICE);
e8171aaa 1349 }
4f57ca6e 1350 rx_buffer_info->dma = 0;
c267fc16
AD		 1351
1352 if (ring_is_ps_enabled(rx_ring)) {
1353 hlen = ixgbe_get_hlen(rx_desc);
1354 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1355 } else {
1356 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1357 }
1358
1359 skb_put(skb, hlen);
1360 } else {
1361 /* assume packet split since header is unmapped */
1362 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1363 }
1364
1365 if (upper_len) {
b6ec895e
AD		 1366 dma_unmap_page(rx_ring->dev,
1367 rx_buffer_info->page_dma,
1368 PAGE_SIZE / 2,
1369 DMA_FROM_DEVICE);
9a799d71
AK		 1370 rx_buffer_info->page_dma = 0;
1371 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1372 rx_buffer_info->page,
1373 rx_buffer_info->page_offset,
1374 upper_len);
762f4c57 1375
c267fc16
AD		 1376 if ((page_count(rx_buffer_info->page) == 1) &&
1377 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1378 get_page(rx_buffer_info->page);
c267fc16
AD		 1379 else
1380 rx_buffer_info->page = NULL;
9a799d71
AK		 1381
1382 skb->len += upper_len;
1383 skb->data_len += upper_len;
1384 skb->truesize += upper_len;
1385 }
1386
1387 i++;
1388 if (i == rx_ring->count)
1389 i = 0;
9a799d71 1390
31f05a2d 1391 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1392 prefetch(next_rxd);
9a799d71 1393 cleaned_count++;
f8212f97 1394
aa80175a 1395 if (pkt_is_rsc) {
f8212f97
AD		 1396 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1397 IXGBE_RXDADV_NEXTP_SHIFT;
1398 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1399 } else {
1400 next_buffer = &rx_ring->rx_buffer_info[i];
1401 }
1402
c267fc16 1403 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1404 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1405 rx_buffer_info->skb = next_buffer->skb;
1406 rx_buffer_info->dma = next_buffer->dma;
1407 next_buffer->skb = skb;
1408 next_buffer->dma = 0;
1409 } else {
1410 skb->next = next_buffer->skb;
1411 skb->next->prev = skb;
1412 }
5b7da515 1413 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1414 goto next_desc;
1415 }
1416
aa80175a
AD		 1417 if (skb->prev) {
1418 skb = ixgbe_transform_rsc_queue(skb);
1419 /* if we got here without RSC the packet is invalid */
1420 if (!pkt_is_rsc) {
1421 __pskb_trim(skb, 0);
1422 rx_buffer_info->skb = skb;
1423 goto next_desc;
1424 }
1425 }
c267fc16
AD		 1426
1427 if (ring_is_rsc_enabled(rx_ring)) {
1428 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1429 dma_unmap_single(rx_ring->dev,
1430 IXGBE_RSC_CB(skb)->dma,
1431 rx_ring->rx_buf_len,
1432 DMA_FROM_DEVICE);
1433 IXGBE_RSC_CB(skb)->dma = 0;
1434 IXGBE_RSC_CB(skb)->delay_unmap = false;
1435 }
aa80175a
AD		 1436 }
1437 if (pkt_is_rsc) {
c267fc16
AD		 1438 if (ring_is_ps_enabled(rx_ring))
1439 rx_ring->rx_stats.rsc_count +=
aa80175a 1440 skb_shinfo(skb)->nr_frags;
c267fc16 1441 else
aa80175a
AD		 1442 rx_ring->rx_stats.rsc_count +=
1443 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1444 rx_ring->rx_stats.rsc_flush++;
1445 }
1446
1447 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1448 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1449 /* trim packet back to size 0 and recycle it */
1450 __pskb_trim(skb, 0);
1451 rx_buffer_info->skb = skb;
9a799d71
AK		 1452 goto next_desc;
1453 }
1454
8bae1b2b 1455 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1456
1457 /* probably a little skewed due to removing CRC */
1458 total_rx_bytes += skb->len;
1459 total_rx_packets++;
1460
fc77dc3c 1461 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1462#ifdef IXGBE_FCOE
1463 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1464 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1465 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1466 if (!ddp_bytes)
332d4a7d 1467 goto next_desc;
3d8fd385 1468 }
332d4a7d 1469#endif /* IXGBE_FCOE */
fdaff1ce 1470 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1471
1472next_desc:
1473 rx_desc->wb.upper.status_error = 0;
1474
c267fc16
AD		 1475 (*work_done)++;
1476 if (*work_done >= work_to_do)
1477 break;
1478
9a799d71
AK		 1479 /* return some buffers to hardware, one at a time is too slow */
1480 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1481 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1482 cleaned_count = 0;
1483 }
1484
1485 /* use prefetched values */
1486 rx_desc = next_rxd;
9a799d71 1487 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1488 }
1489
9a799d71
AK		 1490 rx_ring->next_to_clean = i;
1491 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1492
1493 if (cleaned_count)
fc77dc3c 1494 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1495
3d8fd385
YZ		 1496#ifdef IXGBE_FCOE
1497 /* include DDPed FCoE data */
1498 if (ddp_bytes > 0) {
1499 unsigned int mss;
1500
fc77dc3c 1501 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1502 sizeof(struct fc_frame_header) -
1503 sizeof(struct fcoe_crc_eof);
1504 if (mss > 512)
1505 mss &= ~511;
1506 total_rx_bytes += ddp_bytes;
1507 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1508 }
1509#endif /* IXGBE_FCOE */
1510
f494e8fa
AV		 1511 rx_ring->total_packets += total_rx_packets;
1512 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1513 u64_stats_update_begin(&rx_ring->syncp);
1514 rx_ring->stats.packets += total_rx_packets;
1515 rx_ring->stats.bytes += total_rx_bytes;
1516 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1517}
1518
021230d4 1519static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1520/**
1521 * ixgbe_configure_msix - Configure MSI-X hardware
1522 * @adapter: board private structure
1523 *
1524 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1525 * interrupts.
1526 **/
1527static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1528{
021230d4 1529 struct ixgbe_q_vector *q_vector;
bf29ee6c 1530 int i, q_vectors, v_idx, r_idx;
021230d4 1531 u32 mask;
9a799d71 1532
021230d4 1533 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1534
4df10466
JB		 1535 /*
1536 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1537 * corresponding register.
1538 */
1539 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1540 q_vector = adapter->q_vector[v_idx];
984b3f57 1541 /* XXX for_each_set_bit(...) */
021230d4 1542 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1543 adapter->num_rx_queues);
021230d4
AV		 1544
1545 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1546 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1547 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1548 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1549 adapter->num_rx_queues,
1550 r_idx + 1);
021230d4
AV		 1551 }
1552 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1553 adapter->num_tx_queues);
021230d4
AV		 1554
1555 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1556 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1557 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1558 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1559 adapter->num_tx_queues,
1560 r_idx + 1);
021230d4
AV		 1561 }
1562
021230d4 1563 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1564 /* tx only */
1565 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1566 else if (q_vector->rxr_count)
f7554a2b
NS		 1567 /* rx or mixed */
1568 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1569
fe49f04a 1570 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1571 /* If Flow Director is enabled, set interrupt affinity */
1572 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1573 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1574 /*
1575 * Allocate the affinity_hint cpumask, assign the mask
1576 * for this vector, and set our affinity_hint for
1577 * this irq.
1578 */
1579 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1580 GFP_KERNEL))
1581 return;
1582 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1583 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1584 q_vector->affinity_mask);
1585 }
9a799d71
AK		 1586 }
1587
bd508178
AD		 1588 switch (adapter->hw.mac.type) {
1589 case ixgbe_mac_82598EB:
e8e26350 1590 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1591 v_idx);
bd508178
AD		 1592 break;
1593 case ixgbe_mac_82599EB:
b93a2226 1594 case ixgbe_mac_X540:
e8e26350 1595 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1596 break;
1597
1598 default:
1599 break;
1600 }
021230d4
AV		 1601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1602
41fb9248 1603 /* set up to autoclear timer, and the vectors */
021230d4 1604 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1605 if (adapter->num_vfs)
1606 mask &= ~(IXGBE_EIMS_OTHER |
1607 IXGBE_EIMS_MAILBOX |
1608 IXGBE_EIMS_LSC);
1609 else
1610 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1612}
1613
f494e8fa
AV		 1614enum latency_range {
1615 lowest_latency = 0,
1616 low_latency = 1,
1617 bulk_latency = 2,
1618 latency_invalid = 255
1619};
1620
1621/**
1622 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1623 * @adapter: pointer to adapter
1624 * @eitr: eitr setting (ints per sec) to give last timeslice
1625 * @itr_setting: current throttle rate in ints/second
1626 * @packets: the number of packets during this measurement interval
1627 * @bytes: the number of bytes during this measurement interval
1628 *
1629 * Stores a new ITR value based on packets and byte
1630 * counts during the last interrupt. The advantage of per interrupt
1631 * computation is faster updates and more accurate ITR for the current
1632 * traffic pattern. Constants in this function were computed
1633 * based on theoretical maximum wire speed and thresholds were set based
1634 * on testing data as well as attempting to minimize response time
1635 * while increasing bulk throughput.
1636 * this functionality is controlled by the InterruptThrottleRate module
1637 * parameter (see ixgbe_param.c)
1638 **/
1639static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1640 u32 eitr, u8 itr_setting,
1641 int packets, int bytes)
f494e8fa
AV		 1642{
1643 unsigned int retval = itr_setting;
1644 u32 timepassed_us;
1645 u64 bytes_perint;
1646
1647 if (packets == 0)
1648 goto update_itr_done;
1649
1650
1651 /* simple throttlerate management
1652 * 0-20MB/s lowest (100000 ints/s)
1653 * 20-100MB/s low (20000 ints/s)
1654 * 100-1249MB/s bulk (8000 ints/s)
1655 */
1656 /* what was last interrupt timeslice? */
1657 timepassed_us = 1000000/eitr;
1658 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1659
1660 switch (itr_setting) {
1661 case lowest_latency:
1662 if (bytes_perint > adapter->eitr_low)
1663 retval = low_latency;
1664 break;
1665 case low_latency:
1666 if (bytes_perint > adapter->eitr_high)
1667 retval = bulk_latency;
1668 else if (bytes_perint <= adapter->eitr_low)
1669 retval = lowest_latency;
1670 break;
1671 case bulk_latency:
1672 if (bytes_perint <= adapter->eitr_high)
1673 retval = low_latency;
1674 break;
1675 }
1676
1677update_itr_done:
1678 return retval;
1679}
1680
509ee935
JB		 1681/**
1682 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1683 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1684 *
1685 * This function is made to be called by ethtool and by the driver
1686 * when it needs to update EITR registers at runtime. Hardware
1687 * specific quirks/differences are taken care of here.
1688 */
fe49f04a 1689void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1690{
fe49f04a 1691 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1692 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1693 int v_idx = q_vector->v_idx;
1694 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1695
bd508178
AD		 1696 switch (adapter->hw.mac.type) {
1697 case ixgbe_mac_82598EB:
509ee935
JB		 1698 /* must write high and low 16 bits to reset counter */
1699 itr_reg |= (itr_reg << 16);
bd508178
AD		 1700 break;
1701 case ixgbe_mac_82599EB:
b93a2226 1702 case ixgbe_mac_X540:
f8d1dcaf 1703 /*
b93a2226 1704 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1705 * max interrupt rate, but there is an errata where it can
1706 * not be zero with RSC
1707 */
1708 if (itr_reg == 8 &&
1709 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1710 itr_reg = 0;
1711
509ee935
JB		 1712 /*
1713 * set the WDIS bit to not clear the timer bits and cause an
1714 * immediate assertion of the interrupt
1715 */
1716 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1717 break;
1718 default:
1719 break;
509ee935
JB		 1720 }
1721 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1722}
1723
f494e8fa
AV		 1724static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1725{
1726 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1727 int i, r_idx;
f494e8fa
AV		 1728 u32 new_itr;
1729 u8 current_itr, ret_itr;
f494e8fa
AV		 1730
1731 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1732 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1733 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1734 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1735 q_vector->tx_itr,
1736 tx_ring->total_packets,
1737 tx_ring->total_bytes);
f494e8fa
AV		 1738 /* if the result for this queue would decrease interrupt
1739 * rate for this vector then use that result */
30efa5a3 1740 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1741 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1742 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1743 r_idx + 1);
f494e8fa
AV		 1744 }
1745
1746 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1747 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1748 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1749 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1750 q_vector->rx_itr,
1751 rx_ring->total_packets,
1752 rx_ring->total_bytes);
f494e8fa
AV		 1753 /* if the result for this queue would decrease interrupt
1754 * rate for this vector then use that result */
30efa5a3 1755 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1756 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1757 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1758 r_idx + 1);
f494e8fa
AV		 1759 }
1760
30efa5a3 1761 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1762
1763 switch (current_itr) {
1764 /* counts and packets in update_itr are dependent on these numbers */
1765 case lowest_latency:
1766 new_itr = 100000;
1767 break;
1768 case low_latency:
1769 new_itr = 20000; /* aka hwitr = ~200 */
1770 break;
1771 case bulk_latency:
1772 default:
1773 new_itr = 8000;
1774 break;
1775 }
1776
1777 if (new_itr != q_vector->eitr) {
fe49f04a 1778 /* do an exponential smoothing */
125601bf 1779 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1780
1781 /* save the algorithm value here, not the smoothed one */
1782 q_vector->eitr = new_itr;
fe49f04a
AD		 1783
1784 ixgbe_write_eitr(q_vector);
f494e8fa 1785 }
f494e8fa
AV		 1786}
1787
119fc60a
MC		 1788/**
1789 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1790 * @work: pointer to work_struct containing our data
1791 **/
1792static void ixgbe_check_overtemp_task(struct work_struct *work)
1793{
1794 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1795 struct ixgbe_adapter,
1796 check_overtemp_task);
119fc60a
MC		 1797 struct ixgbe_hw *hw = &adapter->hw;
1798 u32 eicr = adapter->interrupt_event;
1799
7ca647bd
JP		 1800 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1801 return;
1802
1803 switch (hw->device_id) {
1804 case IXGBE_DEV_ID_82599_T3_LOM: {
1805 u32 autoneg;
1806 bool link_up = false;
1807
1808 if (hw->mac.ops.check_link)
1809 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1810
1811 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1812 (eicr & IXGBE_EICR_LSC))
1813 /* Check if this is due to overtemp */
1814 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1815 break;
1816 return;
1817 }
1818 default:
1819 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1820 return;
7ca647bd 1821 break;
119fc60a 1822 }
7ca647bd
JP		 1823 e_crit(drv,
1824 "Network adapter has been stopped because it has over heated. "
1825 "Restart the computer. If the problem persists, "
1826 "power off the system and replace the adapter\n");
1827 /* write to clear the interrupt */
1828 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1829}
1830
0befdb3e
JB		 1831static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1832{
1833 struct ixgbe_hw *hw = &adapter->hw;
1834
1835 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1836 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1837 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1838 /* write to clear the interrupt */
1839 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1840 }
1841}
cf8280ee 1842
e8e26350
PW		 1843static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1844{
1845 struct ixgbe_hw *hw = &adapter->hw;
1846
73c4b7cd
AD		 1847 if (eicr & IXGBE_EICR_GPI_SDP2) {
1848 /* Clear the interrupt */
1849 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1850 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1851 schedule_work(&adapter->sfp_config_module_task);
1852 }
1853
e8e26350
PW		 1854 if (eicr & IXGBE_EICR_GPI_SDP1) {
1855 /* Clear the interrupt */
1856 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
73c4b7cd
AD		 1857 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1858 schedule_work(&adapter->multispeed_fiber_task);
e8e26350
PW		 1859 }
1860}
1861
cf8280ee
JB		 1862static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1863{
1864 struct ixgbe_hw *hw = &adapter->hw;
1865
1866 adapter->lsc_int++;
1867 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1868 adapter->link_check_timeout = jiffies;
1869 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1870 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1871 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1872 schedule_work(&adapter->watchdog_task);
1873 }
1874}
1875
9a799d71
AK		 1876static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1877{
1878 struct net_device *netdev = data;
1879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1880 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1881 u32 eicr;
1882
1883 /*
1884 * Workaround for Silicon errata. Use clear-by-write instead
1885 * of clear-by-read. Reading with EICS will return the
1886 * interrupt causes without clearing, which later be done
1887 * with the write to EICR.
1888 */
1889 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1890 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1891
cf8280ee
JB		 1892 if (eicr & IXGBE_EICR_LSC)
1893 ixgbe_check_lsc(adapter);
d4f80882 1894
1cdd1ec8
GR		 1895 if (eicr & IXGBE_EICR_MAILBOX)
1896 ixgbe_msg_task(adapter);
1897
bd508178
AD		 1898 switch (hw->mac.type) {
1899 case ixgbe_mac_82599EB:
d994653d
DS		 1900 ixgbe_check_sfp_event(adapter, eicr);
1901 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1902 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1903 adapter->interrupt_event = eicr;
1904 schedule_work(&adapter->check_overtemp_task);
1905 }
1906 /* now fallthrough to handle Flow Director */
b93a2226 1907 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1908 /* Handle Flow Director Full threshold interrupt */
1909 if (eicr & IXGBE_EICR_FLOW_DIR) {
1910 int i;
1911 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1912 /* Disable transmits before FDIR Re-initialization */
1913 netif_tx_stop_all_queues(netdev);
1914 for (i = 0; i < adapter->num_tx_queues; i++) {
1915 struct ixgbe_ring *tx_ring =
e8e9f696 1916 adapter->tx_ring[i];
7d637bcc
AD		 1917 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1918 &tx_ring->state))
c4cf55e5
PWJ		 1919 schedule_work(&adapter->fdir_reinit_task);
1920 }
1921 }
bd508178
AD		 1922 break;
1923 default:
1924 break;
c4cf55e5 1925 }
bd508178
AD		 1926
1927 ixgbe_check_fan_failure(adapter, eicr);
1928
d4f80882
AV		 1929 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1930 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1931
1932 return IRQ_HANDLED;
1933}
1934
fe49f04a
AD		 1935static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1936 u64 qmask)
1937{
1938 u32 mask;
bd508178 1939 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1940
bd508178
AD		 1941 switch (hw->mac.type) {
1942 case ixgbe_mac_82598EB:
fe49f04a 1943 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1944 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1945 break;
1946 case ixgbe_mac_82599EB:
b93a2226 1947 case ixgbe_mac_X540:
fe49f04a 1948 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1949 if (mask)
1950 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1951 mask = (qmask >> 32);
bd508178
AD		 1952 if (mask)
1953 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1954 break;
1955 default:
1956 break;
fe49f04a
AD		 1957 }
1958 /* skip the flush */
1959}
1960
1961static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1962 u64 qmask)
fe49f04a
AD		 1963{
1964 u32 mask;
bd508178 1965 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1966
bd508178
AD		 1967 switch (hw->mac.type) {
1968 case ixgbe_mac_82598EB:
fe49f04a 1969 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1970 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1971 break;
1972 case ixgbe_mac_82599EB:
b93a2226 1973 case ixgbe_mac_X540:
fe49f04a 1974 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1975 if (mask)
1976 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1977 mask = (qmask >> 32);
bd508178
AD		 1978 if (mask)
1979 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1980 break;
1981 default:
1982 break;
fe49f04a
AD		 1983 }
1984 /* skip the flush */
1985}
1986
9a799d71
AK		 1987static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1988{
021230d4
AV		 1989 struct ixgbe_q_vector *q_vector = data;
1990 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1991 struct ixgbe_ring *tx_ring;
021230d4
AV		 1992 int i, r_idx;
1993
1994 if (!q_vector->txr_count)
1995 return IRQ_HANDLED;
1996
1997 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1998 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1999 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 2000 tx_ring->total_bytes = 0;
2001 tx_ring->total_packets = 0;
021230d4 2002 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2003 r_idx + 1);
021230d4 2004 }
9a799d71 2005
9b471446 2006 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2007 napi_schedule(&q_vector->napi);
2008
9a799d71
AK		 2009 return IRQ_HANDLED;
2010}
2011
021230d4
AV		 2012/**
2013 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2014 * @irq: unused
2015 * @data: pointer to our q_vector struct for this interrupt vector
2016 **/
9a799d71
AK		 2017static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2018{
021230d4
AV		 2019 struct ixgbe_q_vector *q_vector = data;
2020 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2021 struct ixgbe_ring *rx_ring;
021230d4 2022 int r_idx;
30efa5a3 2023 int i;
021230d4 2024
33cf09c9
AD		 2025#ifdef CONFIG_IXGBE_DCA
2026 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2027 ixgbe_update_dca(q_vector);
2028#endif
2029
021230d4 2030 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2031 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2032 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2033 rx_ring->total_bytes = 0;
2034 rx_ring->total_packets = 0;
2035 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2036 r_idx + 1);
30efa5a3
JB		 2037 }
2038
021230d4
AV		 2039 if (!q_vector->rxr_count)
2040 return IRQ_HANDLED;
2041
9b471446 2042 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2043 napi_schedule(&q_vector->napi);
021230d4
AV		 2044
2045 return IRQ_HANDLED;
2046}
2047
2048static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2049{
91281fd3
AD		 2050 struct ixgbe_q_vector *q_vector = data;
2051 struct ixgbe_adapter *adapter = q_vector->adapter;
2052 struct ixgbe_ring *ring;
2053 int r_idx;
2054 int i;
2055
2056 if (!q_vector->txr_count && !q_vector->rxr_count)
2057 return IRQ_HANDLED;
2058
2059 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2060 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2061 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2062 ring->total_bytes = 0;
2063 ring->total_packets = 0;
2064 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2065 r_idx + 1);
91281fd3
AD		 2066 }
2067
2068 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2069 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2070 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2071 ring->total_bytes = 0;
2072 ring->total_packets = 0;
2073 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2074 r_idx + 1);
91281fd3
AD		 2075 }
2076
9b471446 2077 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2078 napi_schedule(&q_vector->napi);
9a799d71 2079
9a799d71
AK		 2080 return IRQ_HANDLED;
2081}
2082
021230d4
AV		 2083/**
2084 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2085 * @napi: napi struct with our devices info in it
2086 * @budget: amount of work driver is allowed to do this pass, in packets
2087 *
f0848276
JB		 2088 * This function is optimized for cleaning one queue only on a single
2089 * q_vector!!!
021230d4 2090 **/
9a799d71
AK		 2091static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2092{
021230d4 2093 struct ixgbe_q_vector *q_vector =
e8e9f696 2094 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2095 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2096 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2097 int work_done = 0;
021230d4 2098 long r_idx;
9a799d71 2099
5dd2d332 2100#ifdef CONFIG_IXGBE_DCA
bd0362dd 2101 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2102 ixgbe_update_dca(q_vector);
bd0362dd 2103#endif
9a799d71 2104
33cf09c9
AD		 2105 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2106 rx_ring = adapter->rx_ring[r_idx];
2107
78b6f4ce 2108 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2109
021230d4
AV		 2110 /* If all Rx work done, exit the polling mode */
2111 if (work_done < budget) {
288379f0 2112 napi_complete(napi);
f7554a2b 2113 if (adapter->rx_itr_setting & 1)
f494e8fa 2114 ixgbe_set_itr_msix(q_vector);
9a799d71 2115 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2116 ixgbe_irq_enable_queues(adapter,
e8e9f696 2117 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2118 }
2119
2120 return work_done;
2121}
2122
f0848276 2123/**
91281fd3 2124 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2125 * @napi: napi struct with our devices info in it
2126 * @budget: amount of work driver is allowed to do this pass, in packets
2127 *
2128 * This function will clean more than one rx queue associated with a
2129 * q_vector.
2130 **/
91281fd3 2131static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2132{
2133 struct ixgbe_q_vector *q_vector =
e8e9f696 2134 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2135 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2136 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2137 int work_done = 0, i;
2138 long r_idx;
91281fd3
AD		 2139 bool tx_clean_complete = true;
2140
33cf09c9
AD		 2141#ifdef CONFIG_IXGBE_DCA
2142 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2143 ixgbe_update_dca(q_vector);
2144#endif
2145
91281fd3
AD		 2146 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2147 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2148 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2149 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2150 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2151 r_idx + 1);
91281fd3 2152 }
f0848276
JB		 2153
2154 /* attempt to distribute budget to each queue fairly, but don't allow
2155 * the budget to go below 1 because we'll exit polling */
2156 budget /= (q_vector->rxr_count ?: 1);
2157 budget = max(budget, 1);
2158 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2159 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2160 ring = adapter->rx_ring[r_idx];
91281fd3 2161 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2162 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2163 r_idx + 1);
f0848276
JB		 2164 }
2165
2166 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2167 ring = adapter->rx_ring[r_idx];
f0848276 2168 /* If all Rx work done, exit the polling mode */
7f821875 2169 if (work_done < budget) {
288379f0 2170 napi_complete(napi);
f7554a2b 2171 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2172 ixgbe_set_itr_msix(q_vector);
2173 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2174 ixgbe_irq_enable_queues(adapter,
e8e9f696 2175 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2176 return 0;
2177 }
2178
2179 return work_done;
2180}
91281fd3
AD		 2181
2182/**
2183 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2184 * @napi: napi struct with our devices info in it
2185 * @budget: amount of work driver is allowed to do this pass, in packets
2186 *
2187 * This function is optimized for cleaning one queue only on a single
2188 * q_vector!!!
2189 **/
2190static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2191{
2192 struct ixgbe_q_vector *q_vector =
e8e9f696 2193 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2194 struct ixgbe_adapter *adapter = q_vector->adapter;
2195 struct ixgbe_ring *tx_ring = NULL;
2196 int work_done = 0;
2197 long r_idx;
2198
91281fd3
AD		 2199#ifdef CONFIG_IXGBE_DCA
2200 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2201 ixgbe_update_dca(q_vector);
91281fd3
AD		 2202#endif
2203
33cf09c9
AD		 2204 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2205 tx_ring = adapter->tx_ring[r_idx];
2206
91281fd3
AD		 2207 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2208 work_done = budget;
2209
f7554a2b 2210 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2211 if (work_done < budget) {
2212 napi_complete(napi);
f7554a2b 2213 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2214 ixgbe_set_itr_msix(q_vector);
2215 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2216 ixgbe_irq_enable_queues(adapter,
2217 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2218 }
2219
2220 return work_done;
2221}
2222
021230d4 2223static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2224 int r_idx)
021230d4 2225{
7a921c93 2226 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2227 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2228
2229 set_bit(r_idx, q_vector->rxr_idx);
2230 q_vector->rxr_count++;
2274543f 2231 rx_ring->q_vector = q_vector;
021230d4
AV		 2232}
2233
2234static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2235 int t_idx)
021230d4 2236{
7a921c93 2237 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2238 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2239
2240 set_bit(t_idx, q_vector->txr_idx);
2241 q_vector->txr_count++;
2274543f 2242 tx_ring->q_vector = q_vector;
021230d4
AV		 2243}
2244
9a799d71 2245/**
021230d4
AV		 2246 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2247 * @adapter: board private structure to initialize
9a799d71 2248 *
021230d4
AV		 2249 * This function maps descriptor rings to the queue-specific vectors
2250 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2251 * one vector per ring/queue, but on a constrained vector budget, we
2252 * group the rings as "efficiently" as possible. You would add new
2253 * mapping configurations in here.
9a799d71 2254 **/
d0759ebb 2255static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2256{
d0759ebb 2257 int q_vectors;
021230d4
AV		 2258 int v_start = 0;
2259 int rxr_idx = 0, txr_idx = 0;
2260 int rxr_remaining = adapter->num_rx_queues;
2261 int txr_remaining = adapter->num_tx_queues;
2262 int i, j;
2263 int rqpv, tqpv;
2264 int err = 0;
2265
2266 /* No mapping required if MSI-X is disabled. */
2267 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2268 goto out;
9a799d71 2269
d0759ebb
AD		 2270 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2271
021230d4
AV		 2272 /*
2273 * The ideal configuration...
2274 * We have enough vectors to map one per queue.
2275 */
d0759ebb 2276 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2277 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2278 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2279
021230d4
AV		 2280 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2281 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2282
9a799d71 2283 goto out;
021230d4 2284 }
9a799d71 2285
021230d4
AV		 2286 /*
2287 * If we don't have enough vectors for a 1-to-1
2288 * mapping, we'll have to group them so there are
2289 * multiple queues per vector.
2290 */
2291 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2292 for (i = v_start; i < q_vectors; i++) {
2293 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2294 for (j = 0; j < rqpv; j++) {
2295 map_vector_to_rxq(adapter, i, rxr_idx);
2296 rxr_idx++;
2297 rxr_remaining--;
2298 }
d0759ebb 2299 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2300 for (j = 0; j < tqpv; j++) {
2301 map_vector_to_txq(adapter, i, txr_idx);
2302 txr_idx++;
2303 txr_remaining--;
9a799d71 2304 }
9a799d71 2305 }
021230d4
AV		 2306out:
2307 return err;
2308}
2309
2310/**
2311 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2312 * @adapter: board private structure
2313 *
2314 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2315 * interrupts from the kernel.
2316 **/
2317static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2318{
2319 struct net_device *netdev = adapter->netdev;
2320 irqreturn_t (*handler)(int, void *);
2321 int i, vector, q_vectors, err;
e8e9f696 2322 int ri = 0, ti = 0;
021230d4
AV		 2323
2324 /* Decrement for Other and TCP Timer vectors */
2325 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2326
d0759ebb 2327 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2328 if (err)
d0759ebb 2329 return err;
021230d4 2330
d0759ebb
AD		 2331#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2332 ? &ixgbe_msix_clean_many : \
2333 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2334 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2335 NULL)
021230d4 2336 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2337 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2338 handler = SET_HANDLER(q_vector);
cb13fc20 2339
e8e9f696 2340 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2341 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2342 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2343 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2344 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2345 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2346 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2347 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2348 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2349 ti++;
d0759ebb
AD		 2350 } else {
2351 /* skip this unused q_vector */
2352 continue;
32aa77a4 2353 }
021230d4 2354 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2355 handler, 0, q_vector->name,
2356 q_vector);
9a799d71 2357 if (err) {
396e799c 2358 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2359 "Error: %d\n", err);
021230d4 2360 goto free_queue_irqs;
9a799d71 2361 }
9a799d71
AK		 2362 }
2363
d0759ebb 2364 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2365 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb 2366 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
9a799d71 2367 if (err) {
396e799c 2368 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2369 goto free_queue_irqs;
9a799d71
AK		 2370 }
2371
9a799d71
AK		 2372 return 0;
2373
021230d4
AV		 2374free_queue_irqs:
2375 for (i = vector - 1; i >= 0; i--)
2376 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2377 adapter->q_vector[i]);
021230d4
AV		 2378 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2379 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2380 kfree(adapter->msix_entries);
2381 adapter->msix_entries = NULL;
9a799d71
AK		 2382 return err;
2383}
2384
f494e8fa
AV		 2385static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2386{
7a921c93 2387 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2388 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2389 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2390 u32 new_itr = q_vector->eitr;
2391 u8 current_itr;
f494e8fa 2392
30efa5a3 2393 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2394 q_vector->tx_itr,
2395 tx_ring->total_packets,
2396 tx_ring->total_bytes);
30efa5a3 2397 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2398 q_vector->rx_itr,
2399 rx_ring->total_packets,
2400 rx_ring->total_bytes);
f494e8fa 2401
30efa5a3 2402 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2403
2404 switch (current_itr) {
2405 /* counts and packets in update_itr are dependent on these numbers */
2406 case lowest_latency:
2407 new_itr = 100000;
2408 break;
2409 case low_latency:
2410 new_itr = 20000; /* aka hwitr = ~200 */
2411 break;
2412 case bulk_latency:
2413 new_itr = 8000;
2414 break;
2415 default:
2416 break;
2417 }
2418
2419 if (new_itr != q_vector->eitr) {
fe49f04a 2420 /* do an exponential smoothing */
125601bf 2421 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2422
125601bf 2423 /* save the algorithm value here */
509ee935 2424 q_vector->eitr = new_itr;
fe49f04a
AD		 2425
2426 ixgbe_write_eitr(q_vector);
f494e8fa 2427 }
f494e8fa
AV		 2428}
2429
79aefa45
AD		 2430/**
2431 * ixgbe_irq_enable - Enable default interrupt generation settings
2432 * @adapter: board private structure
2433 **/
6af3b9eb
ET		 2434static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2435 bool flush)
79aefa45
AD		 2436{
2437 u32 mask;
835462fc
NS		 2438
2439 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2440 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2441 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2442 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2443 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2444 switch (adapter->hw.mac.type) {
2445 case ixgbe_mac_82599EB:
b93a2226 2446 case ixgbe_mac_X540:
2a41ff81 2447 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2448 mask |= IXGBE_EIMS_GPI_SDP1;
2449 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2450 if (adapter->num_vfs)
2451 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2452 break;
2453 default:
2454 break;
e8e26350 2455 }
c4cf55e5
PWJ		 2456 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2457 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2458 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2459
79aefa45 2460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2461 if (queues)
2462 ixgbe_irq_enable_queues(adapter, ~0);
2463 if (flush)
2464 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2465
2466 if (adapter->num_vfs > 32) {
2467 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2469 }
79aefa45 2470}
021230d4 2471
9a799d71 2472/**
021230d4 2473 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2474 * @irq: interrupt number
2475 * @data: pointer to a network interface device structure
9a799d71
AK		 2476 **/
2477static irqreturn_t ixgbe_intr(int irq, void *data)
2478{
2479 struct net_device *netdev = data;
2480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2481 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2482 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2483 u32 eicr;
2484
54037505 2485 /*
6af3b9eb 2486 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2487 * before the read of EICR.
2488 */
2489 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2490
021230d4
AV		 2491 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2492 * therefore no explict interrupt disable is necessary */
2493 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2494 if (!eicr) {
6af3b9eb
ET		 2495 /*
2496 * shared interrupt alert!
f47cf66e 2497 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2498 * have disabled interrupts due to EIAM
2499 * finish the workaround of silicon errata on 82598. Unmask
2500 * the interrupt that we masked before the EICR read.
2501 */
2502 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2503 ixgbe_irq_enable(adapter, true, true);
9a799d71 2504 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2505 }
9a799d71 2506
cf8280ee
JB		 2507 if (eicr & IXGBE_EICR_LSC)
2508 ixgbe_check_lsc(adapter);
021230d4 2509
bd508178
AD		 2510 switch (hw->mac.type) {
2511 case ixgbe_mac_82599EB:
e8e26350 2512 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2513 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2514 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2515 adapter->interrupt_event = eicr;
2516 schedule_work(&adapter->check_overtemp_task);
2517 }
2518 break;
2519 default:
2520 break;
2521 }
e8e26350 2522
0befdb3e
JB		 2523 ixgbe_check_fan_failure(adapter, eicr);
2524
7a921c93 2525 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2526 adapter->tx_ring[0]->total_packets = 0;
2527 adapter->tx_ring[0]->total_bytes = 0;
2528 adapter->rx_ring[0]->total_packets = 0;
2529 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2530 /* would disable interrupts here but EIAM disabled it */
7a921c93 2531 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2532 }
2533
6af3b9eb
ET		 2534 /*
2535 * re-enable link(maybe) and non-queue interrupts, no flush.
2536 * ixgbe_poll will re-enable the queue interrupts
2537 */
2538
2539 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2540 ixgbe_irq_enable(adapter, false, false);
2541
9a799d71
AK		 2542 return IRQ_HANDLED;
2543}
2544
021230d4
AV		 2545static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2546{
2547 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2548
2549 for (i = 0; i < q_vectors; i++) {
7a921c93 2550 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2551 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2552 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2553 q_vector->rxr_count = 0;
2554 q_vector->txr_count = 0;
2555 }
2556}
2557
9a799d71
AK		 2558/**
2559 * ixgbe_request_irq - initialize interrupts
2560 * @adapter: board private structure
2561 *
2562 * Attempts to configure interrupts using the best available
2563 * capabilities of the hardware and kernel.
2564 **/
021230d4 2565static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2566{
2567 struct net_device *netdev = adapter->netdev;
021230d4 2568 int err;
9a799d71 2569
021230d4
AV		 2570 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2571 err = ixgbe_request_msix_irqs(adapter);
2572 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2573 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2574 netdev->name, netdev);
021230d4 2575 } else {
a0607fd3 2576 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2577 netdev->name, netdev);
9a799d71
AK		 2578 }
2579
9a799d71 2580 if (err)
396e799c 2581 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2582
9a799d71
AK		 2583 return err;
2584}
2585
2586static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2587{
2588 struct net_device *netdev = adapter->netdev;
2589
2590 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2591 int i, q_vectors;
9a799d71 2592
021230d4
AV		 2593 q_vectors = adapter->num_msix_vectors;
2594
2595 i = q_vectors - 1;
9a799d71 2596 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2597
021230d4
AV		 2598 i--;
2599 for (; i >= 0; i--) {
2600 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2601 adapter->q_vector[i]);
021230d4
AV		 2602 }
2603
2604 ixgbe_reset_q_vectors(adapter);
2605 } else {
2606 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2607 }
2608}
2609
22d5a71b
JB		 2610/**
2611 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2612 * @adapter: board private structure
2613 **/
2614static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2615{
bd508178
AD		 2616 switch (adapter->hw.mac.type) {
2617 case ixgbe_mac_82598EB:
835462fc 2618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2619 break;
2620 case ixgbe_mac_82599EB:
b93a2226 2621 case ixgbe_mac_X540:
835462fc
NS		 2622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2623 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2625 if (adapter->num_vfs > 32)
2626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2627 break;
2628 default:
2629 break;
22d5a71b
JB		 2630 }
2631 IXGBE_WRITE_FLUSH(&adapter->hw);
2632 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2633 int i;
2634 for (i = 0; i < adapter->num_msix_vectors; i++)
2635 synchronize_irq(adapter->msix_entries[i].vector);
2636 } else {
2637 synchronize_irq(adapter->pdev->irq);
2638 }
2639}
2640
9a799d71
AK		 2641/**
2642 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2643 *
2644 **/
2645static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2646{
9a799d71
AK		 2647 struct ixgbe_hw *hw = &adapter->hw;
2648
021230d4 2649 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2650 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2651
e8e26350
PW		 2652 ixgbe_set_ivar(adapter, 0, 0, 0);
2653 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2654
2655 map_vector_to_rxq(adapter, 0, 0);
2656 map_vector_to_txq(adapter, 0, 0);
2657
396e799c 2658 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2659}
2660
43e69bf0
AD		 2661/**
2662 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2663 * @adapter: board private structure
2664 * @ring: structure containing ring specific data
2665 *
2666 * Configure the Tx descriptor ring after a reset.
2667 **/
84418e3b
AD		 2668void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2669 struct ixgbe_ring *ring)
43e69bf0
AD		 2670{
2671 struct ixgbe_hw *hw = &adapter->hw;
2672 u64 tdba = ring->dma;
2f1860b8
AD		 2673 int wait_loop = 10;
2674 u32 txdctl;
bf29ee6c 2675 u8 reg_idx = ring->reg_idx;
43e69bf0 2676
2f1860b8
AD		 2677 /* disable queue to avoid issues while updating state */
2678 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2679 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2680 txdctl & ~IXGBE_TXDCTL_ENABLE);
2681 IXGBE_WRITE_FLUSH(hw);
2682
43e69bf0 2683 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2684 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2685 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2686 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2687 ring->count * sizeof(union ixgbe_adv_tx_desc));
2688 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2689 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2690 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2691
2f1860b8
AD		 2692 /* configure fetching thresholds */
2693 if (adapter->rx_itr_setting == 0) {
2694 /* cannot set wthresh when itr==0 */
2695 txdctl &= ~0x007F0000;
2696 } else {
2697 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2698 txdctl |= (8 << 16);
2699 }
2700 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2701 /* PThresh workaround for Tx hang with DFP enabled. */
2702 txdctl |= 32;
2703 }
2704
2705 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2706 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2707 adapter->atr_sample_rate) {
2708 ring->atr_sample_rate = adapter->atr_sample_rate;
2709 ring->atr_count = 0;
2710 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2711 } else {
2712 ring->atr_sample_rate = 0;
2713 }
2f1860b8 2714
c84d324c
JF		 2715 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2716
2f1860b8
AD		 2717 /* enable queue */
2718 txdctl |= IXGBE_TXDCTL_ENABLE;
2719 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2720
2721 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2722 if (hw->mac.type == ixgbe_mac_82598EB &&
2723 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2724 return;
2725
2726 /* poll to verify queue is enabled */
2727 do {
2728 msleep(1);
2729 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2730 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2731 if (!wait_loop)
2732 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2733}
2734
120ff942
AD		 2735static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2736{
2737 struct ixgbe_hw *hw = &adapter->hw;
2738 u32 rttdcs;
2739 u32 mask;
2740
2741 if (hw->mac.type == ixgbe_mac_82598EB)
2742 return;
2743
2744 /* disable the arbiter while setting MTQC */
2745 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2746 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2747 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2748
2749 /* set transmit pool layout */
2750 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2751 switch (adapter->flags & mask) {
2752
2753 case (IXGBE_FLAG_SRIOV_ENABLED):
2754 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2755 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2756 break;
2757
2758 case (IXGBE_FLAG_DCB_ENABLED):
2759 /* We enable 8 traffic classes, DCB only */
2760 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2762 break;
2763
2764 default:
2765 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2766 break;
2767 }
2768
2769 /* re-enable the arbiter */
2770 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2771 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2772}
2773
9a799d71 2774/**
3a581073 2775 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2776 * @adapter: board private structure
2777 *
2778 * Configure the Tx unit of the MAC after a reset.
2779 **/
2780static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2781{
2f1860b8
AD		 2782 struct ixgbe_hw *hw = &adapter->hw;
2783 u32 dmatxctl;
43e69bf0 2784 u32 i;
9a799d71 2785
2f1860b8
AD		 2786 ixgbe_setup_mtqc(adapter);
2787
2788 if (hw->mac.type != ixgbe_mac_82598EB) {
2789 /* DMATXCTL.EN must be before Tx queues are enabled */
2790 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2791 dmatxctl |= IXGBE_DMATXCTL_TE;
2792 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2793 }
2794
9a799d71 2795 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2796 for (i = 0; i < adapter->num_tx_queues; i++)
2797 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2798}
2799
e8e26350 2800#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2801
a6616b42 2802static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2803 struct ixgbe_ring *rx_ring)
cc41ac7c 2804{
cc41ac7c 2805 u32 srrctl;
bf29ee6c 2806 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2807
bd508178
AD		 2808 switch (adapter->hw.mac.type) {
2809 case ixgbe_mac_82598EB: {
2810 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2811 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2812 reg_idx = reg_idx & mask;
cc41ac7c 2813 }
bd508178
AD		 2814 break;
2815 case ixgbe_mac_82599EB:
b93a2226 2816 case ixgbe_mac_X540:
bd508178
AD		 2817 default:
2818 break;
2819 }
2820
bf29ee6c 2821 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2822
2823 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2824 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2825 if (adapter->num_vfs)
2826 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2827
afafd5b0
AD		 2828 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2829 IXGBE_SRRCTL_BSIZEHDR_MASK;
2830
7d637bcc 2831 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2832#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2833 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2834#else
2835 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2836#endif
cc41ac7c 2837 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2838 } else {
afafd5b0
AD		 2839 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2840 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2841 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2842 }
e8e26350 2843
bf29ee6c 2844 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2845}
9a799d71 2846
05abb126 2847static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2848{
05abb126
AD		 2849 struct ixgbe_hw *hw = &adapter->hw;
2850 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2851 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2852 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2853 u32 mrqc = 0, reta = 0;
2854 u32 rxcsum;
2855 int i, j;
0cefafad
JB		 2856 int mask;
2857
05abb126
AD		 2858 /* Fill out hash function seeds */
2859 for (i = 0; i < 10; i++)
2860 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2861
2862 /* Fill out redirection table */
2863 for (i = 0, j = 0; i < 128; i++, j++) {
2864 if (j == adapter->ring_feature[RING_F_RSS].indices)
2865 j = 0;
2866 /* reta = 4-byte sliding window of
2867 * 0x00..(indices-1)(indices-1)00..etc. */
2868 reta = (reta << 8) | (j * 0x11);
2869 if ((i & 3) == 3)
2870 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2871 }
0cefafad 2872
05abb126
AD		 2873 /* Disable indicating checksum in descriptor, enables RSS hash */
2874 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2875 rxcsum |= IXGBE_RXCSUM_PCSD;
2876 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2877
2878 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2879 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2880 else
2881 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2882#ifdef CONFIG_IXGBE_DCB
05abb126 2883 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2884#endif
05abb126
AD		 2885 | IXGBE_FLAG_SRIOV_ENABLED
2886 );
0cefafad
JB		 2887
2888 switch (mask) {
2889 case (IXGBE_FLAG_RSS_ENABLED):
2890 mrqc = IXGBE_MRQC_RSSEN;
2891 break;
1cdd1ec8
GR		 2892 case (IXGBE_FLAG_SRIOV_ENABLED):
2893 mrqc = IXGBE_MRQC_VMDQEN;
2894 break;
0cefafad
JB		 2895#ifdef CONFIG_IXGBE_DCB
2896 case (IXGBE_FLAG_DCB_ENABLED):
2897 mrqc = IXGBE_MRQC_RT8TCEN;
2898 break;
2899#endif /* CONFIG_IXGBE_DCB */
2900 default:
2901 break;
2902 }
2903
05abb126
AD		 2904 /* Perform hash on these packet types */
2905 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2906 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2907 | IXGBE_MRQC_RSS_FIELD_IPV6
2908 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2909
2910 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2911}
2912
b93a2226
DS		 2913/**
2914 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2915 * @adapter: address of board private structure
2916 * @ring: structure containing ring specific data
2917 **/
2918void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2919 struct ixgbe_ring *ring)
2920{
2921 struct ixgbe_hw *hw = &adapter->hw;
2922 u32 rscctrl;
2923 u8 reg_idx = ring->reg_idx;
2924
2925 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2926 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2927 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2928}
2929
bb5a9ad2
NS		 2930/**
2931 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2932 * @adapter: address of board private structure
2933 * @index: index of ring to set
bb5a9ad2 2934 **/
b93a2226 2935void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2936 struct ixgbe_ring *ring)
bb5a9ad2 2937{
bb5a9ad2 2938 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2939 u32 rscctrl;
edd2ea55 2940 int rx_buf_len;
bf29ee6c 2941 u8 reg_idx = ring->reg_idx;
7367096a 2942
7d637bcc 2943 if (!ring_is_rsc_enabled(ring))
7367096a 2944 return;
bb5a9ad2 2945
7367096a
AD		 2946 rx_buf_len = ring->rx_buf_len;
2947 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2948 rscctrl |= IXGBE_RSCCTL_RSCEN;
2949 /*
2950 * we must limit the number of descriptors so that the
2951 * total size of max desc * buf_len is not greater
2952 * than 65535
2953 */
7d637bcc 2954 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2955#if (MAX_SKB_FRAGS > 16)
2956 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2957#elif (MAX_SKB_FRAGS > 8)
2958 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2959#elif (MAX_SKB_FRAGS > 4)
2960 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2961#else
2962 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2963#endif
2964 } else {
2965 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2966 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2967 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2968 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2969 else
2970 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2971 }
7367096a 2972 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2973}
2974
9e10e045
AD		 2975/**
2976 * ixgbe_set_uta - Set unicast filter table address
2977 * @adapter: board private structure
2978 *
2979 * The unicast table address is a register array of 32-bit registers.
2980 * The table is meant to be used in a way similar to how the MTA is used
2981 * however due to certain limitations in the hardware it is necessary to
2982 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2983 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2984 **/
2985static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2986{
2987 struct ixgbe_hw *hw = &adapter->hw;
2988 int i;
2989
2990 /* The UTA table only exists on 82599 hardware and newer */
2991 if (hw->mac.type < ixgbe_mac_82599EB)
2992 return;
2993
2994 /* we only need to do this if VMDq is enabled */
2995 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2996 return;
2997
2998 for (i = 0; i < 128; i++)
2999 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3000}
3001
3002#define IXGBE_MAX_RX_DESC_POLL 10
3003static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3004 struct ixgbe_ring *ring)
3005{
3006 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3007 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3008 u32 rxdctl;
bf29ee6c 3009 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3010
3011 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3012 if (hw->mac.type == ixgbe_mac_82598EB &&
3013 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3014 return;
3015
3016 do {
3017 msleep(1);
3018 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3019 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3020
3021 if (!wait_loop) {
3022 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3023 "the polling period\n", reg_idx);
3024 }
3025}
3026
2d39d576
YZ		 3027void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3028 struct ixgbe_ring *ring)
3029{
3030 struct ixgbe_hw *hw = &adapter->hw;
3031 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3032 u32 rxdctl;
3033 u8 reg_idx = ring->reg_idx;
3034
3035 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3036 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3037
3038 /* write value back with RXDCTL.ENABLE bit cleared */
3039 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3040
3041 if (hw->mac.type == ixgbe_mac_82598EB &&
3042 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3043 return;
3044
3045 /* the hardware may take up to 100us to really disable the rx queue */
3046 do {
3047 udelay(10);
3048 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3049 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3050
3051 if (!wait_loop) {
3052 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3053 "the polling period\n", reg_idx);
3054 }
3055}
3056
84418e3b
AD		 3057void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3058 struct ixgbe_ring *ring)
acd37177
AD		 3059{
3060 struct ixgbe_hw *hw = &adapter->hw;
3061 u64 rdba = ring->dma;
9e10e045 3062 u32 rxdctl;
bf29ee6c 3063 u8 reg_idx = ring->reg_idx;
acd37177 3064
9e10e045
AD		 3065 /* disable queue to avoid issues while updating state */
3066 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3067 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3068
acd37177
AD		 3069 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3070 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3071 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3072 ring->count * sizeof(union ixgbe_adv_rx_desc));
3073 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3074 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3075 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3076
3077 ixgbe_configure_srrctl(adapter, ring);
3078 ixgbe_configure_rscctl(adapter, ring);
3079
3080 if (hw->mac.type == ixgbe_mac_82598EB) {
3081 /*
3082 * enable cache line friendly hardware writes:
3083 * PTHRESH=32 descriptors (half the internal cache),
3084 * this also removes ugly rx_no_buffer_count increment
3085 * HTHRESH=4 descriptors (to minimize latency on fetch)
3086 * WTHRESH=8 burst writeback up to two cache lines
3087 */
3088 rxdctl &= ~0x3FFFFF;
3089 rxdctl |= 0x080420;
3090 }
3091
3092 /* enable receive descriptor ring */
3093 rxdctl |= IXGBE_RXDCTL_ENABLE;
3094 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3095
3096 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 3097 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 3098}
3099
48654521
AD		 3100static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3101{
3102 struct ixgbe_hw *hw = &adapter->hw;
3103 int p;
3104
3105 /* PSRTYPE must be initialized in non 82598 adapters */
3106 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3107 IXGBE_PSRTYPE_UDPHDR |
3108 IXGBE_PSRTYPE_IPV4HDR |
48654521 3109 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3110 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3111
3112 if (hw->mac.type == ixgbe_mac_82598EB)
3113 return;
3114
3115 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3116 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3117
3118 for (p = 0; p < adapter->num_rx_pools; p++)
3119 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3120 psrtype);
3121}
3122
f5b4a52e
AD		 3123static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3124{
3125 struct ixgbe_hw *hw = &adapter->hw;
3126 u32 gcr_ext;
3127 u32 vt_reg_bits;
3128 u32 reg_offset, vf_shift;
3129 u32 vmdctl;
3130
3131 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3132 return;
3133
3134 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3135 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3136 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3137 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3138
3139 vf_shift = adapter->num_vfs % 32;
3140 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3141
3142 /* Enable only the PF's pool for Tx/Rx */
3143 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3144 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3145 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3146 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3147 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3148
3149 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3150 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3151
3152 /*
3153 * Set up VF register offsets for selected VT Mode,
3154 * i.e. 32 or 64 VFs for SR-IOV
3155 */
3156 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3157 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3158 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3159 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3160
3161 /* enable Tx loopback for VF/PF communication */
3162 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3
GR		 3163 /* Enable MAC Anti-Spoofing */
3164 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3165 adapter->num_vfs);
f5b4a52e
AD		 3166}
3167
477de6ed 3168static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3169{
9a799d71
AK		 3170 struct ixgbe_hw *hw = &adapter->hw;
3171 struct net_device *netdev = adapter->netdev;
3172 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3173 int rx_buf_len;
477de6ed
AD		 3174 struct ixgbe_ring *rx_ring;
3175 int i;
3176 u32 mhadd, hlreg0;
48654521 3177
9a799d71 3178 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 3179 /* Do not use packet split if we're in SR-IOV Mode */
3180 if (!adapter->num_vfs)
3181 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3182
3183 /* Set the RX buffer length according to the mode */
3184 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3185 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3186 } else {
0c19d6af 3187 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3188 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3189 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3190 else
477de6ed 3191 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3192 }
3193
63f39bd1 3194#ifdef IXGBE_FCOE
477de6ed
AD		 3195 /* adjust max frame to be able to do baby jumbo for FCoE */
3196 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3197 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3198 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3199
477de6ed
AD		 3200#endif /* IXGBE_FCOE */
3201 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3202 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3203 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3204 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3205
3206 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3207 }
3208
3209 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3210 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3211 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3212 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3213
0cefafad
JB		 3214 /*
3215 * Setup the HW Rx Head and Tail Descriptor Pointers and
3216 * the Base and Length of the Rx Descriptor Ring
3217 */
9a799d71 3218 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3219 rx_ring = adapter->rx_ring[i];
a6616b42 3220 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3221
6e455b89 3222 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3223 set_ring_ps_enabled(rx_ring);
3224 else
3225 clear_ring_ps_enabled(rx_ring);
3226
3227 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3228 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3229 else
7d637bcc 3230 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3231
63f39bd1 3232#ifdef IXGBE_FCOE
e8e9f696 3233 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3234 struct ixgbe_ring_feature *f;
3235 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3236 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3237 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3238 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3239 rx_ring->rx_buf_len =
e8e9f696 3240 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3241 } else if (!ring_is_rsc_enabled(rx_ring) &&
3242 !ring_is_ps_enabled(rx_ring)) {
3243 rx_ring->rx_buf_len =
3244 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3245 }
63f39bd1 3246 }
63f39bd1 3247#endif /* IXGBE_FCOE */
477de6ed 3248 }
477de6ed
AD		 3249}
3250
7367096a
AD		 3251static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3252{
3253 struct ixgbe_hw *hw = &adapter->hw;
3254 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3255
3256 switch (hw->mac.type) {
3257 case ixgbe_mac_82598EB:
3258 /*
3259 * For VMDq support of different descriptor types or
3260 * buffer sizes through the use of multiple SRRCTL
3261 * registers, RDRXCTL.MVMEN must be set to 1
3262 *
3263 * also, the manual doesn't mention it clearly but DCA hints
3264 * will only use queue 0's tags unless this bit is set. Side
3265 * effects of setting this bit are only that SRRCTL must be
3266 * fully programmed [0..15]
3267 */
3268 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3269 break;
3270 case ixgbe_mac_82599EB:
b93a2226 3271 case ixgbe_mac_X540:
7367096a
AD		 3272 /* Disable RSC for ACK packets */
3273 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3274 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3275 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3276 /* hardware requires some bits to be set by default */
3277 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3278 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3279 break;
3280 default:
3281 /* We should do nothing since we don't know this hardware */
3282 return;
3283 }
3284
3285 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3286}
3287
477de6ed
AD		 3288/**
3289 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3290 * @adapter: board private structure
3291 *
3292 * Configure the Rx unit of the MAC after a reset.
3293 **/
3294static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3295{
3296 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3297 int i;
3298 u32 rxctrl;
477de6ed
AD		 3299
3300 /* disable receives while setting up the descriptors */
3301 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3302 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3303
3304 ixgbe_setup_psrtype(adapter);
7367096a 3305 ixgbe_setup_rdrxctl(adapter);
477de6ed 3306
9e10e045 3307 /* Program registers for the distribution of queues */
f5b4a52e 3308 ixgbe_setup_mrqc(adapter);
f5b4a52e 3309
9e10e045
AD		 3310 ixgbe_set_uta(adapter);
3311
477de6ed
AD		 3312 /* set_rx_buffer_len must be called before ring initialization */
3313 ixgbe_set_rx_buffer_len(adapter);
3314
3315 /*
3316 * Setup the HW Rx Head and Tail Descriptor Pointers and
3317 * the Base and Length of the Rx Descriptor Ring
3318 */
9e10e045
AD		 3319 for (i = 0; i < adapter->num_rx_queues; i++)
3320 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3321
9e10e045
AD		 3322 /* disable drop enable for 82598 parts */
3323 if (hw->mac.type == ixgbe_mac_82598EB)
3324 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3325
3326 /* enable all receives */
3327 rxctrl |= IXGBE_RXCTRL_RXEN;
3328 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3329}
3330
068c89b0
DS		 3331static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3332{
3333 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3334 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3335 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3336
3337 /* add VID to filter table */
1ada1b1b 3338 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3339 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3340}
3341
3342static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3343{
3344 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3345 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3346 int pool_ndx = adapter->num_vfs;
068c89b0 3347
068c89b0 3348 /* remove VID from filter table */
1ada1b1b 3349 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3350 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3351}
3352
5f6c0181
JB		 3353/**
3354 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3355 * @adapter: driver data
3356 */
3357static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3358{
3359 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3360 u32 vlnctrl;
3361
3362 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3363 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3364 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3365}
3366
3367/**
3368 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3369 * @adapter: driver data
3370 */
3371static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3372{
3373 struct ixgbe_hw *hw = &adapter->hw;
3374 u32 vlnctrl;
3375
3376 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3377 vlnctrl |= IXGBE_VLNCTRL_VFE;
3378 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3379 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3380}
3381
3382/**
3383 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3384 * @adapter: driver data
3385 */
3386static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3387{
3388 struct ixgbe_hw *hw = &adapter->hw;
3389 u32 vlnctrl;
5f6c0181
JB		 3390 int i, j;
3391
3392 switch (hw->mac.type) {
3393 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3394 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3395 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3396 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3397 break;
3398 case ixgbe_mac_82599EB:
b93a2226 3399 case ixgbe_mac_X540:
5f6c0181
JB		 3400 for (i = 0; i < adapter->num_rx_queues; i++) {
3401 j = adapter->rx_ring[i]->reg_idx;
3402 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3403 vlnctrl &= ~IXGBE_RXDCTL_VME;
3404 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3405 }
3406 break;
3407 default:
3408 break;
3409 }
3410}
3411
3412/**
f62bbb5e 3413 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3414 * @adapter: driver data
3415 */
f62bbb5e 3416static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3417{
3418 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3419 u32 vlnctrl;
5f6c0181
JB		 3420 int i, j;
3421
3422 switch (hw->mac.type) {
3423 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3424 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3425 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3426 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3427 break;
3428 case ixgbe_mac_82599EB:
b93a2226 3429 case ixgbe_mac_X540:
5f6c0181
JB		 3430 for (i = 0; i < adapter->num_rx_queues; i++) {
3431 j = adapter->rx_ring[i]->reg_idx;
3432 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3433 vlnctrl |= IXGBE_RXDCTL_VME;
3434 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3435 }
3436 break;
3437 default:
3438 break;
3439 }
3440}
3441
9a799d71
AK		 3442static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3443{
f62bbb5e 3444 u16 vid;
9a799d71 3445
f62bbb5e
JG		 3446 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3447
3448 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3449 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3450}
3451
2850062a
AD		 3452/**
3453 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3454 * @netdev: network interface device structure
3455 *
3456 * Writes unicast address list to the RAR table.
3457 * Returns: -ENOMEM on failure/insufficient address space
3458 * 0 on no addresses written
3459 * X on writing X addresses to the RAR table
3460 **/
3461static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3462{
3463 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3464 struct ixgbe_hw *hw = &adapter->hw;
3465 unsigned int vfn = adapter->num_vfs;
3466 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3467 int count = 0;
3468
3469 /* return ENOMEM indicating insufficient memory for addresses */
3470 if (netdev_uc_count(netdev) > rar_entries)
3471 return -ENOMEM;
3472
3473 if (!netdev_uc_empty(netdev) && rar_entries) {
3474 struct netdev_hw_addr *ha;
3475 /* return error if we do not support writing to RAR table */
3476 if (!hw->mac.ops.set_rar)
3477 return -ENOMEM;
3478
3479 netdev_for_each_uc_addr(ha, netdev) {
3480 if (!rar_entries)
3481 break;
3482 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3483 vfn, IXGBE_RAH_AV);
3484 count++;
3485 }
3486 }
3487 /* write the addresses in reverse order to avoid write combining */
3488 for (; rar_entries > 0 ; rar_entries--)
3489 hw->mac.ops.clear_rar(hw, rar_entries);
3490
3491 return count;
3492}
3493
9a799d71 3494/**
2c5645cf 3495 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3496 * @netdev: network interface device structure
3497 *
2c5645cf
CL		 3498 * The set_rx_method entry point is called whenever the unicast/multicast
3499 * address list or the network interface flags are updated. This routine is
3500 * responsible for configuring the hardware for proper unicast, multicast and
3501 * promiscuous mode.
9a799d71 3502 **/
7f870475 3503void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3504{
3505 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3506 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3507 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3508 int count;
9a799d71
AK		 3509
3510 /* Check for Promiscuous and All Multicast modes */
3511
3512 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3513
f5dc442b
AD		 3514 /* set all bits that we expect to always be set */
3515 fctrl |= IXGBE_FCTRL_BAM;
3516 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3517 fctrl |= IXGBE_FCTRL_PMCF;
3518
2850062a
AD		 3519 /* clear the bits we are changing the status of */
3520 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3521
9a799d71 3522 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3523 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3524 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3525 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3526 /* don't hardware filter vlans in promisc mode */
3527 ixgbe_vlan_filter_disable(adapter);
9a799d71 3528 } else {
746b9f02
PM		 3529 if (netdev->flags & IFF_ALLMULTI) {
3530 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3531 vmolr |= IXGBE_VMOLR_MPE;
3532 } else {
3533 /*
3534 * Write addresses to the MTA, if the attempt fails
3535 * then we should just turn on promiscous mode so
3536 * that we can at least receive multicast traffic
3537 */
3538 hw->mac.ops.update_mc_addr_list(hw, netdev);
3539 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3540 }
5f6c0181 3541 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3542 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3543 /*
3544 * Write addresses to available RAR registers, if there is not
3545 * sufficient space to store all the addresses then enable
3546 * unicast promiscous mode
3547 */
3548 count = ixgbe_write_uc_addr_list(netdev);
3549 if (count < 0) {
3550 fctrl |= IXGBE_FCTRL_UPE;
3551 vmolr |= IXGBE_VMOLR_ROPE;
3552 }
9a799d71
AK		 3553 }
3554
2850062a 3555 if (adapter->num_vfs) {
1cdd1ec8 3556 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3557 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3558 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3559 IXGBE_VMOLR_ROPE);
3560 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3561 }
3562
3563 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3564
3565 if (netdev->features & NETIF_F_HW_VLAN_RX)
3566 ixgbe_vlan_strip_enable(adapter);
3567 else
3568 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3569}
3570
021230d4
AV		 3571static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3572{
3573 int q_idx;
3574 struct ixgbe_q_vector *q_vector;
3575 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3576
3577 /* legacy and MSI only use one vector */
3578 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3579 q_vectors = 1;
3580
3581 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3582 struct napi_struct *napi;
7a921c93 3583 q_vector = adapter->q_vector[q_idx];
f0848276 3584 napi = &q_vector->napi;
91281fd3
AD		 3585 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3586 if (!q_vector->rxr_count || !q_vector->txr_count) {
3587 if (q_vector->txr_count == 1)
3588 napi->poll = &ixgbe_clean_txonly;
3589 else if (q_vector->rxr_count == 1)
3590 napi->poll = &ixgbe_clean_rxonly;
3591 }
3592 }
f0848276
JB		 3593
3594 napi_enable(napi);
021230d4
AV		 3595 }
3596}
3597
3598static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3599{
3600 int q_idx;
3601 struct ixgbe_q_vector *q_vector;
3602 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3603
3604 /* legacy and MSI only use one vector */
3605 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3606 q_vectors = 1;
3607
3608 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3609 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3610 napi_disable(&q_vector->napi);
3611 }
3612}
3613
7a6b6f51 3614#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3615/*
3616 * ixgbe_configure_dcb - Configure DCB hardware
3617 * @adapter: ixgbe adapter struct
3618 *
3619 * This is called by the driver on open to configure the DCB hardware.
3620 * This is also called by the gennetlink interface when reconfiguring
3621 * the DCB state.
3622 */
3623static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3624{
3625 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3626 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3627
67ebd791
AD		 3628 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3629 if (hw->mac.type == ixgbe_mac_82598EB)
3630 netif_set_gso_max_size(adapter->netdev, 65536);
3631 return;
3632 }
3633
3634 if (hw->mac.type == ixgbe_mac_82598EB)
3635 netif_set_gso_max_size(adapter->netdev, 32768);
3636
9806307a
JF		 3637#ifdef CONFIG_FCOE
3638 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3639 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3640#endif
3641
80ab193d 3642 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3643 DCB_TX_CONFIG);
80ab193d 3644 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3645 DCB_RX_CONFIG);
2f90b865 3646
2f90b865 3647 /* Enable VLAN tag insert/strip */
f62bbb5e 3648 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3649
2f90b865 3650 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3651
3652 /* reconfigure the hardware */
3653 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
2f90b865
AD		 3654}
3655
3656#endif
9a799d71
AK		 3657static void ixgbe_configure(struct ixgbe_adapter *adapter)
3658{
3659 struct net_device *netdev = adapter->netdev;
c4cf55e5 3660 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3661 int i;
3662
7a6b6f51 3663#ifdef CONFIG_IXGBE_DCB
67ebd791 3664 ixgbe_configure_dcb(adapter);
2f90b865 3665#endif
9a799d71 3666
f62bbb5e
JG		 3667 ixgbe_set_rx_mode(netdev);
3668 ixgbe_restore_vlan(adapter);
3669
eacd73f7
YZ		 3670#ifdef IXGBE_FCOE
3671 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3672 ixgbe_configure_fcoe(adapter);
3673
3674#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3675 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3676 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3677 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3678 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3679 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3680 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3681 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3682 }
933d41f1 3683 ixgbe_configure_virtualization(adapter);
c4cf55e5 3684
9a799d71
AK		 3685 ixgbe_configure_tx(adapter);
3686 ixgbe_configure_rx(adapter);
9a799d71
AK		 3687}
3688
e8e26350
PW		 3689static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3690{
3691 switch (hw->phy.type) {
3692 case ixgbe_phy_sfp_avago:
3693 case ixgbe_phy_sfp_ftl:
3694 case ixgbe_phy_sfp_intel:
3695 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3696 case ixgbe_phy_sfp_passive_tyco:
3697 case ixgbe_phy_sfp_passive_unknown:
3698 case ixgbe_phy_sfp_active_unknown:
3699 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3700 return true;
3701 default:
3702 return false;
3703 }
3704}
3705
0ecc061d 3706/**
e8e26350
PW		 3707 * ixgbe_sfp_link_config - set up SFP+ link
3708 * @adapter: pointer to private adapter struct
3709 **/
3710static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3711{
3712 struct ixgbe_hw *hw = &adapter->hw;
3713
3714 if (hw->phy.multispeed_fiber) {
3715 /*
3716 * In multispeed fiber setups, the device may not have
3717 * had a physical connection when the driver loaded.
3718 * If that's the case, the initial link configuration
3719 * couldn't get the MAC into 10G or 1G mode, so we'll
3720 * never have a link status change interrupt fire.
3721 * We need to try and force an autonegotiation
3722 * session, then bring up link.
3723 */
3724 hw->mac.ops.setup_sfp(hw);
3725 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3726 schedule_work(&adapter->multispeed_fiber_task);
3727 } else {
3728 /*
3729 * Direct Attach Cu and non-multispeed fiber modules
3730 * still need to be configured properly prior to
3731 * attempting link.
3732 */
3733 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3734 schedule_work(&adapter->sfp_config_module_task);
3735 }
3736}
3737
3738/**
3739 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3740 * @hw: pointer to private hardware struct
3741 *
3742 * Returns 0 on success, negative on failure
3743 **/
e8e26350 3744static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3745{
3746 u32 autoneg;
8620a103 3747 bool negotiation, link_up = false;
0ecc061d
PWJ		 3748 u32 ret = IXGBE_ERR_LINK_SETUP;
3749
3750 if (hw->mac.ops.check_link)
3751 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3752
3753 if (ret)
3754 goto link_cfg_out;
3755
3756 if (hw->mac.ops.get_link_capabilities)
e8e9f696
JP		 3757 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3758 &negotiation);
0ecc061d
PWJ		 3759 if (ret)
3760 goto link_cfg_out;
3761
8620a103
MC		 3762 if (hw->mac.ops.setup_link)
3763 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3764link_cfg_out:
3765 return ret;
3766}
3767
a34bcfff 3768static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3769{
9a799d71 3770 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3771 u32 gpie = 0;
9a799d71 3772
9b471446 3773 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3774 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3775 IXGBE_GPIE_OCD;
3776 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3777 /*
3778 * use EIAM to auto-mask when MSI-X interrupt is asserted
3779 * this saves a register write for every interrupt
3780 */
3781 switch (hw->mac.type) {
3782 case ixgbe_mac_82598EB:
3783 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3784 break;
9b471446 3785 case ixgbe_mac_82599EB:
b93a2226
DS		 3786 case ixgbe_mac_X540:
3787 default:
9b471446
JB		 3788 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3789 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3790 break;
3791 }
3792 } else {
021230d4
AV		 3793 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3794 * specifically only auto mask tx and rx interrupts */
3795 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3796 }
9a799d71 3797
a34bcfff
AD		 3798 /* XXX: to interrupt immediately for EICS writes, enable this */
3799 /* gpie |= IXGBE_GPIE_EIMEN; */
3800
3801 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3802 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3803 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3804 }
3805
a34bcfff
AD		 3806 /* Enable fan failure interrupt */
3807 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3808 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3809
a34bcfff 3810 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3811 gpie |= IXGBE_SDP1_GPIEN;
3812 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3813
3814 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3815}
3816
3817static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3818{
3819 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3820 int err;
a34bcfff
AD		 3821 u32 ctrl_ext;
3822
3823 ixgbe_get_hw_control(adapter);
3824 ixgbe_setup_gpie(adapter);
e8e26350 3825
9a799d71
AK		 3826 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3827 ixgbe_configure_msix(adapter);
3828 else
3829 ixgbe_configure_msi_and_legacy(adapter);
3830
c6ecf39a
DS		 3831 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3832 if (hw->mac.ops.enable_tx_laser &&
3833 ((hw->phy.multispeed_fiber) ||
9f911707 3834 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3835 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3836 hw->mac.ops.enable_tx_laser(hw);
3837
9a799d71 3838 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3839 ixgbe_napi_enable_all(adapter);
3840
73c4b7cd
AD		 3841 if (ixgbe_is_sfp(hw)) {
3842 ixgbe_sfp_link_config(adapter);
3843 } else {
3844 err = ixgbe_non_sfp_link_config(hw);
3845 if (err)
3846 e_err(probe, "link_config FAILED %d\n", err);
3847 }
3848
021230d4
AV		 3849 /* clear any pending interrupts, may auto mask */
3850 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3851 ixgbe_irq_enable(adapter, true, true);
9a799d71 3852
bf069c97
DS		 3853 /*
3854 * If this adapter has a fan, check to see if we had a failure
3855 * before we enabled the interrupt.
3856 */
3857 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3858 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3859 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3860 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3861 }
3862
e8e26350
PW		 3863 /*
3864 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3865 * arrived before interrupts were enabled but after probe. Such
3866 * devices wouldn't have their type identified yet. We need to
3867 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3868 * If we're not hot-pluggable SFP+, we just need to configure link
3869 * and bring it up.
3870 */
73c4b7cd
AD		 3871 if (hw->phy.type == ixgbe_phy_unknown)
3872 schedule_work(&adapter->sfp_config_module_task);
0ecc061d 3873
1da100bb 3874 /* enable transmits */
477de6ed 3875 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3876
9a799d71
AK		 3877 /* bring the link up in the watchdog, this could race with our first
3878 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3879 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3880 adapter->link_check_timeout = jiffies;
9a799d71 3881 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3882
3883 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3884 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3885 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3886 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3887
9a799d71
AK		 3888 return 0;
3889}
3890
d4f80882
AV		 3891void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3892{
3893 WARN_ON(in_interrupt());
3894 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3895 msleep(1);
3896 ixgbe_down(adapter);
5809a1ae
GR		 3897 /*
3898 * If SR-IOV enabled then wait a bit before bringing the adapter
3899 * back up to give the VFs time to respond to the reset. The
3900 * two second wait is based upon the watchdog timer cycle in
3901 * the VF driver.
3902 */
3903 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3904 msleep(2000);
d4f80882
AV		 3905 ixgbe_up(adapter);
3906 clear_bit(__IXGBE_RESETTING, &adapter->state);
3907}
3908
9a799d71
AK		 3909int ixgbe_up(struct ixgbe_adapter *adapter)
3910{
3911 /* hardware has been reset, we need to reload some things */
3912 ixgbe_configure(adapter);
3913
3914 return ixgbe_up_complete(adapter);
3915}
3916
3917void ixgbe_reset(struct ixgbe_adapter *adapter)
3918{
c44ade9e 3919 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3920 int err;
3921
3922 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3923 switch (err) {
3924 case 0:
3925 case IXGBE_ERR_SFP_NOT_PRESENT:
3926 break;
3927 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3928 e_dev_err("master disable timed out\n");
da4dd0f7 3929 break;
794caeb2
PWJ		 3930 case IXGBE_ERR_EEPROM_VERSION:
3931 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3932 e_dev_warn("This device is a pre-production adapter/LOM. "
3933 "Please be aware there may be issuesassociated with "
3934 "your hardware. If you are experiencing problems "
3935 "please contact your Intel or hardware "
3936 "representative who provided you with this "
3937 "hardware.\n");
794caeb2 3938 break;
da4dd0f7 3939 default:
849c4542 3940 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3941 }
9a799d71
AK		 3942
3943 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3944 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3945 IXGBE_RAH_AV);
9a799d71
AK		 3946}
3947
9a799d71
AK		 3948/**
3949 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3950 * @rx_ring: ring to free buffers from
3951 **/
b6ec895e 3952static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3953{
b6ec895e 3954 struct device *dev = rx_ring->dev;
9a799d71 3955 unsigned long size;
b6ec895e 3956 u16 i;
9a799d71 3957
84418e3b
AD		 3958 /* ring already cleared, nothing to do */
3959 if (!rx_ring->rx_buffer_info)
3960 return;
9a799d71 3961
84418e3b 3962 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3963 for (i = 0; i < rx_ring->count; i++) {
3964 struct ixgbe_rx_buffer *rx_buffer_info;
3965
3966 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3967 if (rx_buffer_info->dma) {
b6ec895e 3968 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3969 rx_ring->rx_buf_len,
1b507730 3970 DMA_FROM_DEVICE);
9a799d71
AK		 3971 rx_buffer_info->dma = 0;
3972 }
3973 if (rx_buffer_info->skb) {
f8212f97 3974 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3975 rx_buffer_info->skb = NULL;
f8212f97
AD		 3976 do {
3977 struct sk_buff *this = skb;
e8171aaa 3978 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3979 dma_unmap_single(dev,
1b507730 3980 IXGBE_RSC_CB(this)->dma,
e8e9f696 3981 rx_ring->rx_buf_len,
1b507730 3982 DMA_FROM_DEVICE);
fd3686a8 3983 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3984 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3985 }
f8212f97
AD		 3986 skb = skb->prev;
3987 dev_kfree_skb(this);
3988 } while (skb);
9a799d71
AK		 3989 }
3990 if (!rx_buffer_info->page)
3991 continue;
4f57ca6e 3992 if (rx_buffer_info->page_dma) {
b6ec895e 3993 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3994 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3995 rx_buffer_info->page_dma = 0;
3996 }
9a799d71
AK		 3997 put_page(rx_buffer_info->page);
3998 rx_buffer_info->page = NULL;
762f4c57 3999 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4000 }
4001
4002 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4003 memset(rx_ring->rx_buffer_info, 0, size);
4004
4005 /* Zero out the descriptor ring */
4006 memset(rx_ring->desc, 0, rx_ring->size);
4007
4008 rx_ring->next_to_clean = 0;
4009 rx_ring->next_to_use = 0;
9a799d71
AK		 4010}
4011
4012/**
4013 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4014 * @tx_ring: ring to be cleaned
4015 **/
b6ec895e 4016static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4017{
4018 struct ixgbe_tx_buffer *tx_buffer_info;
4019 unsigned long size;
b6ec895e 4020 u16 i;
9a799d71 4021
84418e3b
AD		 4022 /* ring already cleared, nothing to do */
4023 if (!tx_ring->tx_buffer_info)
4024 return;
9a799d71 4025
84418e3b 4026 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4027 for (i = 0; i < tx_ring->count; i++) {
4028 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4029 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4030 }
4031
4032 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4033 memset(tx_ring->tx_buffer_info, 0, size);
4034
4035 /* Zero out the descriptor ring */
4036 memset(tx_ring->desc, 0, tx_ring->size);
4037
4038 tx_ring->next_to_use = 0;
4039 tx_ring->next_to_clean = 0;
9a799d71
AK		 4040}
4041
4042/**
021230d4 4043 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4044 * @adapter: board private structure
4045 **/
021230d4 4046static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4047{
4048 int i;
4049
021230d4 4050 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4051 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4052}
4053
4054/**
021230d4 4055 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4056 * @adapter: board private structure
4057 **/
021230d4 4058static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4059{
4060 int i;
4061
021230d4 4062 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4063 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4064}
4065
4066void ixgbe_down(struct ixgbe_adapter *adapter)
4067{
4068 struct net_device *netdev = adapter->netdev;
7f821875 4069 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4070 u32 rxctrl;
7f821875 4071 u32 txdctl;
bf29ee6c 4072 int i;
b25ebfd2 4073 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4074
4075 /* signal that we are down to the interrupt handler */
4076 set_bit(__IXGBE_DOWN, &adapter->state);
4077
767081ad
GR		 4078 /* disable receive for all VFs and wait one second */
4079 if (adapter->num_vfs) {
767081ad
GR		 4080 /* ping all the active vfs to let them know we are going down */
4081 ixgbe_ping_all_vfs(adapter);
581d1aa7 4082
767081ad
GR		 4083 /* Disable all VFTE/VFRE TX/RX */
4084 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 4085
4086 /* Mark all the VFs as inactive */
4087 for (i = 0 ; i < adapter->num_vfs; i++)
4088 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 4089 }
4090
9a799d71 4091 /* disable receives */
7f821875
JB		 4092 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4093 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4094
2d39d576
YZ		 4095 /* disable all enabled rx queues */
4096 for (i = 0; i < adapter->num_rx_queues; i++)
4097 /* this call also flushes the previous write */
4098 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4099
9a799d71
AK		 4100 msleep(10);
4101
7f821875
JB		 4102 netif_tx_stop_all_queues(netdev);
4103
0a1f87cb
DS		 4104 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4105 del_timer_sync(&adapter->sfp_timer);
9a799d71 4106 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 4107 cancel_work_sync(&adapter->watchdog_task);
9a799d71 4108
c0dfb90e
JF		 4109 netif_carrier_off(netdev);
4110 netif_tx_disable(netdev);
4111
4112 ixgbe_irq_disable(adapter);
4113
4114 ixgbe_napi_disable_all(adapter);
4115
b25ebfd2
PW		 4116 /* Cleanup the affinity_hint CPU mask memory and callback */
4117 for (i = 0; i < num_q_vectors; i++) {
4118 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4119 /* clear the affinity_mask in the IRQ descriptor */
4120 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4121 /* release the CPU mask memory */
4122 free_cpumask_var(q_vector->affinity_mask);
4123 }
4124
c4cf55e5
PWJ		 4125 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4126 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4127 cancel_work_sync(&adapter->fdir_reinit_task);
4128
119fc60a
MC		 4129 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4130 cancel_work_sync(&adapter->check_overtemp_task);
4131
7f821875
JB		 4132 /* disable transmits in the hardware now that interrupts are off */
4133 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c
AD		 4134 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4135 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4136 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
e8e9f696 4137 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 4138 }
88512539 4139 /* Disable the Tx DMA engine on 82599 */
bd508178
AD		 4140 switch (hw->mac.type) {
4141 case ixgbe_mac_82599EB:
b93a2226 4142 case ixgbe_mac_X540:
88512539 4143 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4144 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4145 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4146 break;
4147 default:
4148 break;
4149 }
7f821875 4150
9a713e7c
PW		 4151 /* clear n-tuple filters that are cached */
4152 ethtool_ntuple_flush(netdev);
4153
6f4a0e45
PL		 4154 if (!pci_channel_offline(adapter->pdev))
4155 ixgbe_reset(adapter);
c6ecf39a
DS		 4156
4157 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4158 if (hw->mac.ops.disable_tx_laser &&
4159 ((hw->phy.multispeed_fiber) ||
9f911707 4160 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4161 (hw->mac.type == ixgbe_mac_82599EB))))
4162 hw->mac.ops.disable_tx_laser(hw);
4163
9a799d71
AK		 4164 ixgbe_clean_all_tx_rings(adapter);
4165 ixgbe_clean_all_rx_rings(adapter);
4166
5dd2d332 4167#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4168 /* since we reset the hardware DCA settings were cleared */
e35ec126 4169 ixgbe_setup_dca(adapter);
96b0e0f6 4170#endif
9a799d71
AK		 4171}
4172
9a799d71 4173/**
021230d4
AV		 4174 * ixgbe_poll - NAPI Rx polling callback
4175 * @napi: structure for representing this polling device
4176 * @budget: how many packets driver is allowed to clean
4177 *
4178 * This function is used for legacy and MSI, NAPI mode
9a799d71 4179 **/
021230d4 4180static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4181{
9a1a69ad 4182 struct ixgbe_q_vector *q_vector =
e8e9f696 4183 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4184 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4185 int tx_clean_complete, work_done = 0;
9a799d71 4186
5dd2d332 4187#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4188 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4189 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4190#endif
4191
4a0b9ca0
PW		 4192 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4193 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4194
9a1a69ad 4195 if (!tx_clean_complete)
d2c7ddd6
DM		 4196 work_done = budget;
4197
53e52c72
DM		 4198 /* If budget not fully consumed, exit the polling mode */
4199 if (work_done < budget) {
288379f0 4200 napi_complete(napi);
f7554a2b 4201 if (adapter->rx_itr_setting & 1)
f494e8fa 4202 ixgbe_set_itr(adapter);
d4f80882 4203 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4204 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4205 }
9a799d71
AK		 4206 return work_done;
4207}
4208
4209/**
4210 * ixgbe_tx_timeout - Respond to a Tx Hang
4211 * @netdev: network interface device structure
4212 **/
4213static void ixgbe_tx_timeout(struct net_device *netdev)
4214{
4215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4216
c84d324c
JF		 4217 adapter->tx_timeout_count++;
4218
9a799d71
AK		 4219 /* Do the reset outside of interrupt context */
4220 schedule_work(&adapter->reset_task);
4221}
4222
4223static void ixgbe_reset_task(struct work_struct *work)
4224{
4225 struct ixgbe_adapter *adapter;
4226 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4227
2f90b865
AD		 4228 /* If we're already down or resetting, just bail */
4229 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4230 test_bit(__IXGBE_RESETTING, &adapter->state))
4231 return;
4232
dcd79aeb
TI		 4233 ixgbe_dump(adapter);
4234 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 4235 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4236}
4237
bc97114d
PWJ		 4238#ifdef CONFIG_IXGBE_DCB
4239static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 4240{
bc97114d 4241 bool ret = false;
0cefafad 4242 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 4243
0cefafad
JB		 4244 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4245 return ret;
4246
4247 f->mask = 0x7 << 3;
4248 adapter->num_rx_queues = f->indices;
4249 adapter->num_tx_queues = f->indices;
4250 ret = true;
2f90b865 4251
bc97114d
PWJ		 4252 return ret;
4253}
4254#endif
4255
4df10466
JB		 4256/**
4257 * ixgbe_set_rss_queues: Allocate queues for RSS
4258 * @adapter: board private structure to initialize
4259 *
4260 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4261 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4262 *
4263 **/
bc97114d
PWJ		 4264static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4265{
4266 bool ret = false;
0cefafad 4267 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4268
4269 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4270 f->mask = 0xF;
4271 adapter->num_rx_queues = f->indices;
4272 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4273 ret = true;
4274 } else {
bc97114d 4275 ret = false;
b9804972
JB		 4276 }
4277
bc97114d
PWJ		 4278 return ret;
4279}
4280
c4cf55e5
PWJ		 4281/**
4282 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4283 * @adapter: board private structure to initialize
4284 *
4285 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4286 * to the original CPU that initiated the Tx session. This runs in addition
4287 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4288 * Rx load across CPUs using RSS.
4289 *
4290 **/
e8e9f696 4291static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4292{
4293 bool ret = false;
4294 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4295
4296 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4297 f_fdir->mask = 0;
4298
4299 /* Flow Director must have RSS enabled */
4300 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4301 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4302 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4303 adapter->num_tx_queues = f_fdir->indices;
4304 adapter->num_rx_queues = f_fdir->indices;
4305 ret = true;
4306 } else {
4307 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4308 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4309 }
4310 return ret;
4311}
4312
0331a832
YZ		 4313#ifdef IXGBE_FCOE
4314/**
4315 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4316 * @adapter: board private structure to initialize
4317 *
4318 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4319 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4320 * rx queues out of the max number of rx queues, instead, it is used as the
4321 * index of the first rx queue used by FCoE.
4322 *
4323 **/
4324static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4325{
4326 bool ret = false;
4327 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4328
4329 f->indices = min((int)num_online_cpus(), f->indices);
4330 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 4331 adapter->num_rx_queues = 1;
4332 adapter->num_tx_queues = 1;
0331a832
YZ		 4333#ifdef CONFIG_IXGBE_DCB
4334 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 4335 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 4336 ixgbe_set_dcb_queues(adapter);
4337 }
4338#endif
4339 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4340 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4341 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4342 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4343 ixgbe_set_fdir_queues(adapter);
4344 else
4345 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4346 }
4347 /* adding FCoE rx rings to the end */
4348 f->mask = adapter->num_rx_queues;
4349 adapter->num_rx_queues += f->indices;
8de8b2e6 4350 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4351
4352 ret = true;
4353 }
4354
4355 return ret;
4356}
4357
4358#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4359/**
4360 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4361 * @adapter: board private structure to initialize
4362 *
4363 * IOV doesn't actually use anything, so just NAK the
4364 * request for now and let the other queue routines
4365 * figure out what to do.
4366 */
4367static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4368{
4369 return false;
4370}
4371
4df10466
JB		 4372/*
4373 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4374 * @adapter: board private structure to initialize
4375 *
4376 * This is the top level queue allocation routine. The order here is very
4377 * important, starting with the "most" number of features turned on at once,
4378 * and ending with the smallest set of features. This way large combinations
4379 * can be allocated if they're turned on, and smaller combinations are the
4380 * fallthrough conditions.
4381 *
4382 **/
847f53ff 4383static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4384{
1cdd1ec8
GR		 4385 /* Start with base case */
4386 adapter->num_rx_queues = 1;
4387 adapter->num_tx_queues = 1;
4388 adapter->num_rx_pools = adapter->num_rx_queues;
4389 adapter->num_rx_queues_per_pool = 1;
4390
4391 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4392 goto done;
1cdd1ec8 4393
0331a832
YZ		 4394#ifdef IXGBE_FCOE
4395 if (ixgbe_set_fcoe_queues(adapter))
4396 goto done;
4397
4398#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4399#ifdef CONFIG_IXGBE_DCB
4400 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4401 goto done;
bc97114d
PWJ		 4402
4403#endif
c4cf55e5
PWJ		 4404 if (ixgbe_set_fdir_queues(adapter))
4405 goto done;
4406
bc97114d 4407 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4408 goto done;
4409
4410 /* fallback to base case */
4411 adapter->num_rx_queues = 1;
4412 adapter->num_tx_queues = 1;
4413
4414done:
847f53ff 4415 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4416 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4417 return netif_set_real_num_rx_queues(adapter->netdev,
4418 adapter->num_rx_queues);
b9804972
JB		 4419}
4420
021230d4 4421static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4422 int vectors)
021230d4
AV		 4423{
4424 int err, vector_threshold;
4425
4426 /* We'll want at least 3 (vector_threshold):
4427 * 1) TxQ[0] Cleanup
4428 * 2) RxQ[0] Cleanup
4429 * 3) Other (Link Status Change, etc.)
4430 * 4) TCP Timer (optional)
4431 */
4432 vector_threshold = MIN_MSIX_COUNT;
4433
4434 /* The more we get, the more we will assign to Tx/Rx Cleanup
4435 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4436 * Right now, we simply care about how many we'll get; we'll
4437 * set them up later while requesting irq's.
4438 */
4439 while (vectors >= vector_threshold) {
4440 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4441 vectors);
021230d4
AV		 4442 if (!err) /* Success in acquiring all requested vectors. */
4443 break;
4444 else if (err < 0)
4445 vectors = 0; /* Nasty failure, quit now */
4446 else /* err == number of vectors we should try again with */
4447 vectors = err;
4448 }
4449
4450 if (vectors < vector_threshold) {
4451 /* Can't allocate enough MSI-X interrupts? Oh well.
4452 * This just means we'll go with either a single MSI
4453 * vector or fall back to legacy interrupts.
4454 */
849c4542
ET		 4455 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4456 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4457 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4458 kfree(adapter->msix_entries);
4459 adapter->msix_entries = NULL;
021230d4
AV		 4460 } else {
4461 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4462 /*
4463 * Adjust for only the vectors we'll use, which is minimum
4464 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4465 * vectors we were allocated.
4466 */
4467 adapter->num_msix_vectors = min(vectors,
e8e9f696 4468 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4469 }
4470}
4471
021230d4 4472/**
bc97114d 4473 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4474 * @adapter: board private structure to initialize
4475 *
bc97114d
PWJ		 4476 * Cache the descriptor ring offsets for RSS to the assigned rings.
4477 *
021230d4 4478 **/
bc97114d 4479static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4480{
bc97114d 4481 int i;
bc97114d 4482
9d6b758f
AD		 4483 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4484 return false;
bc97114d 4485
9d6b758f
AD		 4486 for (i = 0; i < adapter->num_rx_queues; i++)
4487 adapter->rx_ring[i]->reg_idx = i;
4488 for (i = 0; i < adapter->num_tx_queues; i++)
4489 adapter->tx_ring[i]->reg_idx = i;
4490
4491 return true;
bc97114d
PWJ		 4492}
4493
4494#ifdef CONFIG_IXGBE_DCB
4495/**
4496 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4497 * @adapter: board private structure to initialize
4498 *
4499 * Cache the descriptor ring offsets for DCB to the assigned rings.
4500 *
4501 **/
4502static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4503{
4504 int i;
4505 bool ret = false;
4506 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4507
bd508178
AD		 4508 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4509 return false;
f92ef202 4510
bd508178
AD		 4511 /* the number of queues is assumed to be symmetric */
4512 switch (adapter->hw.mac.type) {
4513 case ixgbe_mac_82598EB:
4514 for (i = 0; i < dcb_i; i++) {
4515 adapter->rx_ring[i]->reg_idx = i << 3;
4516 adapter->tx_ring[i]->reg_idx = i << 2;
4517 }
4518 ret = true;
4519 break;
4520 case ixgbe_mac_82599EB:
b93a2226 4521 case ixgbe_mac_X540:
bd508178
AD		 4522 if (dcb_i == 8) {
4523 /*
4524 * Tx TC0 starts at: descriptor queue 0
4525 * Tx TC1 starts at: descriptor queue 32
4526 * Tx TC2 starts at: descriptor queue 64
4527 * Tx TC3 starts at: descriptor queue 80
4528 * Tx TC4 starts at: descriptor queue 96
4529 * Tx TC5 starts at: descriptor queue 104
4530 * Tx TC6 starts at: descriptor queue 112
4531 * Tx TC7 starts at: descriptor queue 120
4532 *
4533 * Rx TC0-TC7 are offset by 16 queues each
4534 */
4535 for (i = 0; i < 3; i++) {
4536 adapter->tx_ring[i]->reg_idx = i << 5;
4537 adapter->rx_ring[i]->reg_idx = i << 4;
e8e26350 4538 }
bd508178
AD		 4539 for ( ; i < 5; i++) {
4540 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4541 adapter->rx_ring[i]->reg_idx = i << 4;
4542 }
4543 for ( ; i < dcb_i; i++) {
4544 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4545 adapter->rx_ring[i]->reg_idx = i << 4;
4546 }
4547 ret = true;
4548 } else if (dcb_i == 4) {
4549 /*
4550 * Tx TC0 starts at: descriptor queue 0
4551 * Tx TC1 starts at: descriptor queue 64
4552 * Tx TC2 starts at: descriptor queue 96
4553 * Tx TC3 starts at: descriptor queue 112
4554 *
4555 * Rx TC0-TC3 are offset by 32 queues each
4556 */
4557 adapter->tx_ring[0]->reg_idx = 0;
4558 adapter->tx_ring[1]->reg_idx = 64;
4559 adapter->tx_ring[2]->reg_idx = 96;
4560 adapter->tx_ring[3]->reg_idx = 112;
4561 for (i = 0 ; i < dcb_i; i++)
4562 adapter->rx_ring[i]->reg_idx = i << 5;
4563 ret = true;
021230d4 4564 }
bd508178
AD		 4565 break;
4566 default:
4567 break;
021230d4 4568 }
bc97114d
PWJ		 4569 return ret;
4570}
4571#endif
4572
c4cf55e5
PWJ		 4573/**
4574 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4575 * @adapter: board private structure to initialize
4576 *
4577 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4578 *
4579 **/
e8e9f696 4580static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4581{
4582 int i;
4583 bool ret = false;
4584
4585 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4586 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4587 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4588 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4589 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4590 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4591 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4592 ret = true;
4593 }
4594
4595 return ret;
4596}
4597
0331a832
YZ		 4598#ifdef IXGBE_FCOE
4599/**
4600 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4601 * @adapter: board private structure to initialize
4602 *
4603 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4604 *
4605 */
4606static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4607{
0331a832 4608 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4609 int i;
4610 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4611
4612 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4613 return false;
0331a832 4614
0331a832 4615#ifdef CONFIG_IXGBE_DCB
bf29ee6c
AD		 4616 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4617 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
8de8b2e6 4618
bf29ee6c
AD		 4619 ixgbe_cache_ring_dcb(adapter);
4620 /* find out queues in TC for FCoE */
4621 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4622 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4623 /*
4624 * In 82599, the number of Tx queues for each traffic
4625 * class for both 8-TC and 4-TC modes are:
4626 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4627 * 8 TCs: 32 32 16 16 8 8 8 8
4628 * 4 TCs: 64 64 32 32
4629 * We have max 8 queues for FCoE, where 8 the is
4630 * FCoE redirection table size. If TC for FCoE is
4631 * less than or equal to TC3, we have enough queues
4632 * to add max of 8 queues for FCoE, so we start FCoE
4633 * Tx queue from the next one, i.e., reg_idx + 1.
4634 * If TC for FCoE is above TC3, implying 8 TC mode,
4635 * and we need 8 for FCoE, we have to take all queues
4636 * in that traffic class for FCoE.
4637 */
4638 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4639 fcoe_tx_i--;
4640 }
0331a832 4641#endif /* CONFIG_IXGBE_DCB */
bf29ee6c
AD		 4642 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4643 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4644 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4645 ixgbe_cache_ring_fdir(adapter);
4646 else
4647 ixgbe_cache_ring_rss(adapter);
8faa2a78 4648
bf29ee6c
AD		 4649 fcoe_rx_i = f->mask;
4650 fcoe_tx_i = f->mask;
0331a832 4651 }
bf29ee6c
AD		 4652 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4653 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4654 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4655 }
4656 return true;
0331a832
YZ		 4657}
4658
4659#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4660/**
4661 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4662 * @adapter: board private structure to initialize
4663 *
4664 * SR-IOV doesn't use any descriptor rings but changes the default if
4665 * no other mapping is used.
4666 *
4667 */
4668static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4669{
4a0b9ca0
PW		 4670 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4671 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4672 if (adapter->num_vfs)
4673 return true;
4674 else
4675 return false;
4676}
4677
bc97114d
PWJ		 4678/**
4679 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4680 * @adapter: board private structure to initialize
4681 *
4682 * Once we know the feature-set enabled for the device, we'll cache
4683 * the register offset the descriptor ring is assigned to.
4684 *
4685 * Note, the order the various feature calls is important. It must start with
4686 * the "most" features enabled at the same time, then trickle down to the
4687 * least amount of features turned on at once.
4688 **/
4689static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4690{
4691 /* start with default case */
4a0b9ca0
PW		 4692 adapter->rx_ring[0]->reg_idx = 0;
4693 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4694
1cdd1ec8
GR		 4695 if (ixgbe_cache_ring_sriov(adapter))
4696 return;
4697
0331a832
YZ		 4698#ifdef IXGBE_FCOE
4699 if (ixgbe_cache_ring_fcoe(adapter))
4700 return;
4701
4702#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4703#ifdef CONFIG_IXGBE_DCB
4704 if (ixgbe_cache_ring_dcb(adapter))
4705 return;
4706
4707#endif
c4cf55e5
PWJ		 4708 if (ixgbe_cache_ring_fdir(adapter))
4709 return;
4710
bc97114d
PWJ		 4711 if (ixgbe_cache_ring_rss(adapter))
4712 return;
021230d4
AV		 4713}
4714
9a799d71
AK		 4715/**
4716 * ixgbe_alloc_queues - Allocate memory for all rings
4717 * @adapter: board private structure to initialize
4718 *
4719 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4720 * number of queues at compile-time. The polling_netdev array is
4721 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4722 **/
2f90b865 4723static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4724{
e2ddeba9 4725 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4726
e2ddeba9
ED		 4727 if (nid < 0 || !node_online(nid))
4728 nid = first_online_node;
4729
4730 for (; tx < adapter->num_tx_queues; tx++) {
4731 struct ixgbe_ring *ring;
4732
4733 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4734 if (!ring)
e2ddeba9 4735 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4736 if (!ring)
e2ddeba9 4737 goto err_allocation;
4a0b9ca0 4738 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4739 ring->queue_index = tx;
4740 ring->numa_node = nid;
b6ec895e 4741 ring->dev = &adapter->pdev->dev;
fc77dc3c 4742 ring->netdev = adapter->netdev;
4a0b9ca0 4743
e2ddeba9 4744 adapter->tx_ring[tx] = ring;
021230d4 4745 }
b9804972 4746
e2ddeba9
ED		 4747 for (; rx < adapter->num_rx_queues; rx++) {
4748 struct ixgbe_ring *ring;
4a0b9ca0 4749
e2ddeba9 4750 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4751 if (!ring)
e2ddeba9 4752 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4753 if (!ring)
e2ddeba9
ED		 4754 goto err_allocation;
4755 ring->count = adapter->rx_ring_count;
4756 ring->queue_index = rx;
4757 ring->numa_node = nid;
b6ec895e 4758 ring->dev = &adapter->pdev->dev;
fc77dc3c 4759 ring->netdev = adapter->netdev;
4a0b9ca0 4760
e2ddeba9 4761 adapter->rx_ring[rx] = ring;
021230d4
AV		 4762 }
4763
4764 ixgbe_cache_ring_register(adapter);
4765
4766 return 0;
4767
e2ddeba9
ED		 4768err_allocation:
4769 while (tx)
4770 kfree(adapter->tx_ring[--tx]);
4771
4772 while (rx)
4773 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4774 return -ENOMEM;
4775}
4776
4777/**
4778 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4779 * @adapter: board private structure to initialize
4780 *
4781 * Attempt to configure the interrupts using the best available
4782 * capabilities of the hardware and the kernel.
4783 **/
feea6a57 4784static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4785{
8be0e467 4786 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4787 int err = 0;
4788 int vector, v_budget;
4789
4790 /*
4791 * It's easy to be greedy for MSI-X vectors, but it really
4792 * doesn't do us much good if we have a lot more vectors
4793 * than CPU's. So let's be conservative and only ask for
342bde1b 4794 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4795 */
4796 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4797 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4798
4799 /*
4800 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4801 * hw.mac->max_msix_vectors vectors. With features
4802 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4803 * descriptor queues supported by our device. Thus, we cap it off in
4804 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4805 */
8be0e467 4806 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4807
4808 /* A failure in MSI-X entry allocation isn't fatal, but it does
4809 * mean we disable MSI-X capabilities of the adapter. */
4810 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4811 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4812 if (adapter->msix_entries) {
4813 for (vector = 0; vector < v_budget; vector++)
4814 adapter->msix_entries[vector].entry = vector;
021230d4 4815
7a921c93 4816 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4817
7a921c93
AD		 4818 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4819 goto out;
4820 }
26d27844 4821
7a921c93
AD		 4822 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4823 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4824 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4825 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4826 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4827 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4828 ixgbe_disable_sriov(adapter);
4829
847f53ff
BH		 4830 err = ixgbe_set_num_queues(adapter);
4831 if (err)
4832 return err;
021230d4 4833
021230d4
AV		 4834 err = pci_enable_msi(adapter->pdev);
4835 if (!err) {
4836 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4837 } else {
849c4542
ET		 4838 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4839 "Unable to allocate MSI interrupt, "
4840 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4841 /* reset err */
4842 err = 0;
4843 }
4844
4845out:
021230d4
AV		 4846 return err;
4847}
4848
7a921c93
AD		 4849/**
4850 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4851 * @adapter: board private structure to initialize
4852 *
4853 * We allocate one q_vector per queue interrupt. If allocation fails we
4854 * return -ENOMEM.
4855 **/
4856static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4857{
4858 int q_idx, num_q_vectors;
4859 struct ixgbe_q_vector *q_vector;
4860 int napi_vectors;
4861 int (*poll)(struct napi_struct *, int);
4862
4863 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4864 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4865 napi_vectors = adapter->num_rx_queues;
91281fd3 4866 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4867 } else {
4868 num_q_vectors = 1;
4869 napi_vectors = 1;
4870 poll = &ixgbe_poll;
4871 }
4872
4873 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4874 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4875 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4876 if (!q_vector)
4877 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4878 GFP_KERNEL);
7a921c93
AD		 4879 if (!q_vector)
4880 goto err_out;
4881 q_vector->adapter = adapter;
f7554a2b
NS		 4882 if (q_vector->txr_count && !q_vector->rxr_count)
4883 q_vector->eitr = adapter->tx_eitr_param;
4884 else
4885 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4886 q_vector->v_idx = q_idx;
91281fd3 4887 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4888 adapter->q_vector[q_idx] = q_vector;
4889 }
4890
4891 return 0;
4892
4893err_out:
4894 while (q_idx) {
4895 q_idx--;
4896 q_vector = adapter->q_vector[q_idx];
4897 netif_napi_del(&q_vector->napi);
4898 kfree(q_vector);
4899 adapter->q_vector[q_idx] = NULL;
4900 }
4901 return -ENOMEM;
4902}
4903
4904/**
4905 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4906 * @adapter: board private structure to initialize
4907 *
4908 * This function frees the memory allocated to the q_vectors. In addition if
4909 * NAPI is enabled it will delete any references to the NAPI struct prior
4910 * to freeing the q_vector.
4911 **/
4912static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4913{
4914 int q_idx, num_q_vectors;
7a921c93 4915
91281fd3 4916 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4917 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4918 else
7a921c93 4919 num_q_vectors = 1;
7a921c93
AD		 4920
4921 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4922 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4923 adapter->q_vector[q_idx] = NULL;
91281fd3 4924 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4925 kfree(q_vector);
4926 }
4927}
4928
7b25cdba 4929static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4930{
4931 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4932 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4933 pci_disable_msix(adapter->pdev);
4934 kfree(adapter->msix_entries);
4935 adapter->msix_entries = NULL;
4936 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4937 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4938 pci_disable_msi(adapter->pdev);
4939 }
021230d4
AV		 4940}
4941
4942/**
4943 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4944 * @adapter: board private structure to initialize
4945 *
4946 * We determine which interrupt scheme to use based on...
4947 * - Kernel support (MSI, MSI-X)
4948 * - which can be user-defined (via MODULE_PARAM)
4949 * - Hardware queue count (num_*_queues)
4950 * - defined by miscellaneous hardware support/features (RSS, etc.)
4951 **/
2f90b865 4952int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4953{
4954 int err;
4955
4956 /* Number of supported queues */
847f53ff
BH		 4957 err = ixgbe_set_num_queues(adapter);
4958 if (err)
4959 return err;
021230d4 4960
021230d4
AV		 4961 err = ixgbe_set_interrupt_capability(adapter);
4962 if (err) {
849c4542 4963 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4964 goto err_set_interrupt;
9a799d71
AK		 4965 }
4966
7a921c93
AD		 4967 err = ixgbe_alloc_q_vectors(adapter);
4968 if (err) {
849c4542 4969 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4970 goto err_alloc_q_vectors;
4971 }
4972
4973 err = ixgbe_alloc_queues(adapter);
4974 if (err) {
849c4542 4975 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4976 goto err_alloc_queues;
4977 }
4978
849c4542 4979 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4980 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4981 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4982
4983 set_bit(__IXGBE_DOWN, &adapter->state);
4984
9a799d71 4985 return 0;
021230d4 4986
7a921c93
AD		 4987err_alloc_queues:
4988 ixgbe_free_q_vectors(adapter);
4989err_alloc_q_vectors:
4990 ixgbe_reset_interrupt_capability(adapter);
021230d4 4991err_set_interrupt:
7a921c93
AD		 4992 return err;
4993}
4994
1a51502b
ED		 4995static void ring_free_rcu(struct rcu_head *head)
4996{
4997 kfree(container_of(head, struct ixgbe_ring, rcu));
4998}
4999
7a921c93
AD		 5000/**
5001 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5002 * @adapter: board private structure to clear interrupt scheme on
5003 *
5004 * We go through and clear interrupt specific resources and reset the structure
5005 * to pre-load conditions
5006 **/
5007void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5008{
4a0b9ca0
PW		 5009 int i;
5010
5011 for (i = 0; i < adapter->num_tx_queues; i++) {
5012 kfree(adapter->tx_ring[i]);
5013 adapter->tx_ring[i] = NULL;
5014 }
5015 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5016 struct ixgbe_ring *ring = adapter->rx_ring[i];
5017
5018 /* ixgbe_get_stats64() might access this ring, we must wait
5019 * a grace period before freeing it.
5020 */
5021 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 5022 adapter->rx_ring[i] = NULL;
5023 }
7a921c93 5024
b8eb3a10
DS		 5025 adapter->num_tx_queues = 0;
5026 adapter->num_rx_queues = 0;
5027
7a921c93
AD		 5028 ixgbe_free_q_vectors(adapter);
5029 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5030}
5031
c4900be0
DS		 5032/**
5033 * ixgbe_sfp_timer - worker thread to find a missing module
5034 * @data: pointer to our adapter struct
5035 **/
5036static void ixgbe_sfp_timer(unsigned long data)
5037{
5038 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5039
4df10466
JB		 5040 /*
5041 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 5042 * delays that sfp+ detection requires
5043 */
5044 schedule_work(&adapter->sfp_task);
5045}
5046
5047/**
5048 * ixgbe_sfp_task - worker thread to find a missing module
5049 * @work: pointer to work_struct containing our data
5050 **/
5051static void ixgbe_sfp_task(struct work_struct *work)
5052{
5053 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5054 struct ixgbe_adapter,
5055 sfp_task);
c4900be0
DS		 5056 struct ixgbe_hw *hw = &adapter->hw;
5057
5058 if ((hw->phy.type == ixgbe_phy_nl) &&
5059 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5060 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5061 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 5062 goto reschedule;
5063 ret = hw->phy.ops.reset(hw);
5064 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5065 e_dev_err("failed to initialize because an unsupported "
5066 "SFP+ module type was detected.\n");
5067 e_dev_err("Reload the driver after installing a "
5068 "supported module.\n");
c4900be0
DS		 5069 unregister_netdev(adapter->netdev);
5070 } else {
396e799c 5071 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 5072 }
5073 /* don't need this routine any more */
5074 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5075 }
5076 return;
5077reschedule:
5078 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5079 mod_timer(&adapter->sfp_timer,
e8e9f696 5080 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 5081}
5082
9a799d71
AK		 5083/**
5084 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5085 * @adapter: board private structure to initialize
5086 *
5087 * ixgbe_sw_init initializes the Adapter private data structure.
5088 * Fields are initialized based on PCI device information and
5089 * OS network device settings (MTU size).
5090 **/
5091static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5092{
5093 struct ixgbe_hw *hw = &adapter->hw;
5094 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5095 struct net_device *dev = adapter->netdev;
021230d4 5096 unsigned int rss;
7a6b6f51 5097#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5098 int j;
5099 struct tc_configuration *tc;
5100#endif
16b61beb 5101 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5102
c44ade9e
JB		 5103 /* PCI config space info */
5104
5105 hw->vendor_id = pdev->vendor;
5106 hw->device_id = pdev->device;
5107 hw->revision_id = pdev->revision;
5108 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5109 hw->subsystem_device_id = pdev->subsystem_device;
5110
021230d4
AV		 5111 /* Set capability flags */
5112 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5113 adapter->ring_feature[RING_F_RSS].indices = rss;
5114 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 5115 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bd508178
AD		 5116 switch (hw->mac.type) {
5117 case ixgbe_mac_82598EB:
bf069c97
DS		 5118 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5119 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5120 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5121 break;
5122 case ixgbe_mac_82599EB:
b93a2226 5123 case ixgbe_mac_X540:
e8e26350 5124 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5125 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5126 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5127 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5128 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 5129 if (dev->features & NETIF_F_NTUPLE) {
5130 /* Flow Director perfect filter enabled */
5131 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
5132 adapter->atr_sample_rate = 0;
5133 spin_lock_init(&adapter->fdir_perfect_lock);
5134 } else {
5135 /* Flow Director hash filters enabled */
5136 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5137 adapter->atr_sample_rate = 20;
5138 }
c4cf55e5 5139 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5140 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 5141 adapter->fdir_pballoc = 0;
eacd73f7 5142#ifdef IXGBE_FCOE
0d551589
YZ		 5143 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5144 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5145 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5146#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 5147 /* Default traffic class to use for FCoE */
5148 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 5149 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5150#endif
eacd73f7 5151#endif /* IXGBE_FCOE */
bd508178
AD		 5152 break;
5153 default:
5154 break;
f8212f97 5155 }
2f90b865 5156
7a6b6f51 5157#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5158 /* Configure DCB traffic classes */
5159 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5160 tc = &adapter->dcb_cfg.tc_config[j];
5161 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5162 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5163 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5164 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5165 tc->dcb_pfc = pfc_disabled;
5166 }
5167 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5168 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5169 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 5170 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 5171 adapter->dcb_cfg.round_robin_enable = false;
5172 adapter->dcb_set_bitmap = 0x00;
5173 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e8e9f696 5174 adapter->ring_feature[RING_F_DCB].indices);
2f90b865
AD		 5175
5176#endif
9a799d71
AK		 5177
5178 /* default flow control settings */
cd7664f6 5179 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5180 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5181#ifdef CONFIG_DCB
5182 adapter->last_lfc_mode = hw->fc.current_mode;
5183#endif
16b61beb
JF		 5184 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5185 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5186 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5187 hw->fc.send_xon = true;
71fd570b 5188 hw->fc.disable_fc_autoneg = false;
9a799d71 5189
30efa5a3 5190 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5191 adapter->rx_itr_setting = 1;
5192 adapter->rx_eitr_param = 20000;
5193 adapter->tx_itr_setting = 1;
5194 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5195
5196 /* set defaults for eitr in MegaBytes */
5197 adapter->eitr_low = 10;
5198 adapter->eitr_high = 20;
5199
5200 /* set default ring sizes */
5201 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5202 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5203
9a799d71 5204 /* initialize eeprom parameters */
c44ade9e 5205 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5206 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5207 return -EIO;
5208 }
5209
021230d4 5210 /* enable rx csum by default */
9a799d71
AK		 5211 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5212
1a6c14a2
JB		 5213 /* get assigned NUMA node */
5214 adapter->node = dev_to_node(&pdev->dev);
5215
9a799d71
AK		 5216 set_bit(__IXGBE_DOWN, &adapter->state);
5217
5218 return 0;
5219}
5220
5221/**
5222 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5223 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5224 *
5225 * Return 0 on success, negative on failure
5226 **/
b6ec895e 5227int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5228{
b6ec895e 5229 struct device *dev = tx_ring->dev;
9a799d71
AK		 5230 int size;
5231
3a581073 5232 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5233 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5234 if (!tx_ring->tx_buffer_info)
89bf67f1 5235 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5236 if (!tx_ring->tx_buffer_info)
5237 goto err;
9a799d71
AK		 5238
5239 /* round up to nearest 4K */
12207e49 5240 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5241 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5242
b6ec895e 5243 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5244 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5245 if (!tx_ring->desc)
5246 goto err;
9a799d71 5247
3a581073
JB		 5248 tx_ring->next_to_use = 0;
5249 tx_ring->next_to_clean = 0;
5250 tx_ring->work_limit = tx_ring->count;
9a799d71 5251 return 0;
e01c31a5
JB		 5252
5253err:
5254 vfree(tx_ring->tx_buffer_info);
5255 tx_ring->tx_buffer_info = NULL;
b6ec895e 5256 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5257 return -ENOMEM;
9a799d71
AK		 5258}
5259
69888674
AD		 5260/**
5261 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5262 * @adapter: board private structure
5263 *
5264 * If this function returns with an error, then it's possible one or
5265 * more of the rings is populated (while the rest are not). It is the
5266 * callers duty to clean those orphaned rings.
5267 *
5268 * Return 0 on success, negative on failure
5269 **/
5270static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5271{
5272 int i, err = 0;
5273
5274 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5275 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5276 if (!err)
5277 continue;
396e799c 5278 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5279 break;
5280 }
5281
5282 return err;
5283}
5284
9a799d71
AK		 5285/**
5286 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5287 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5288 *
5289 * Returns 0 on success, negative on failure
5290 **/
b6ec895e 5291int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5292{
b6ec895e 5293 struct device *dev = rx_ring->dev;
021230d4 5294 int size;
9a799d71 5295
3a581073 5296 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5297 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5298 if (!rx_ring->rx_buffer_info)
89bf67f1 5299 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5300 if (!rx_ring->rx_buffer_info)
5301 goto err;
9a799d71 5302
9a799d71 5303 /* Round up to nearest 4K */
3a581073
JB		 5304 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5305 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5306
b6ec895e 5307 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5308 &rx_ring->dma, GFP_KERNEL);
9a799d71 5309
b6ec895e
AD		 5310 if (!rx_ring->desc)
5311 goto err;
9a799d71 5312
3a581073
JB		 5313 rx_ring->next_to_clean = 0;
5314 rx_ring->next_to_use = 0;
9a799d71
AK		 5315
5316 return 0;
b6ec895e
AD		 5317err:
5318 vfree(rx_ring->rx_buffer_info);
5319 rx_ring->rx_buffer_info = NULL;
5320 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5321 return -ENOMEM;
9a799d71
AK		 5322}
5323
69888674
AD		 5324/**
5325 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5326 * @adapter: board private structure
5327 *
5328 * If this function returns with an error, then it's possible one or
5329 * more of the rings is populated (while the rest are not). It is the
5330 * callers duty to clean those orphaned rings.
5331 *
5332 * Return 0 on success, negative on failure
5333 **/
69888674
AD		 5334static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5335{
5336 int i, err = 0;
5337
5338 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5339 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5340 if (!err)
5341 continue;
396e799c 5342 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5343 break;
5344 }
5345
5346 return err;
5347}
5348
9a799d71
AK		 5349/**
5350 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5351 * @tx_ring: Tx descriptor ring for a specific queue
5352 *
5353 * Free all transmit software resources
5354 **/
b6ec895e 5355void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5356{
b6ec895e 5357 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5358
5359 vfree(tx_ring->tx_buffer_info);
5360 tx_ring->tx_buffer_info = NULL;
5361
b6ec895e
AD		 5362 /* if not set, then don't free */
5363 if (!tx_ring->desc)
5364 return;
5365
5366 dma_free_coherent(tx_ring->dev, tx_ring->size,
5367 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5368
5369 tx_ring->desc = NULL;
5370}
5371
5372/**
5373 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5374 * @adapter: board private structure
5375 *
5376 * Free all transmit software resources
5377 **/
5378static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5379{
5380 int i;
5381
5382 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5383 if (adapter->tx_ring[i]->desc)
b6ec895e 5384 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5385}
5386
5387/**
b4617240 5388 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5389 * @rx_ring: ring to clean the resources from
5390 *
5391 * Free all receive software resources
5392 **/
b6ec895e 5393void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5394{
b6ec895e 5395 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5396
5397 vfree(rx_ring->rx_buffer_info);
5398 rx_ring->rx_buffer_info = NULL;
5399
b6ec895e
AD		 5400 /* if not set, then don't free */
5401 if (!rx_ring->desc)
5402 return;
5403
5404 dma_free_coherent(rx_ring->dev, rx_ring->size,
5405 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5406
5407 rx_ring->desc = NULL;
5408}
5409
5410/**
5411 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5412 * @adapter: board private structure
5413 *
5414 * Free all receive software resources
5415 **/
5416static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5417{
5418 int i;
5419
5420 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5421 if (adapter->rx_ring[i]->desc)
b6ec895e 5422 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5423}
5424
9a799d71
AK		 5425/**
5426 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5427 * @netdev: network interface device structure
5428 * @new_mtu: new value for maximum frame size
5429 *
5430 * Returns 0 on success, negative on failure
5431 **/
5432static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5433{
5434 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5435 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5436 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5437
42c783c5
JB		 5438 /* MTU < 68 is an error and causes problems on some kernels */
5439 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5440 return -EINVAL;
5441
396e799c 5442 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5443 /* must set new MTU before calling down or up */
9a799d71
AK		 5444 netdev->mtu = new_mtu;
5445
16b61beb
JF		 5446 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5447 hw->fc.low_water = FC_LOW_WATER(max_frame);
5448
d4f80882
AV		 5449 if (netif_running(netdev))
5450 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5451
5452 return 0;
5453}
5454
5455/**
5456 * ixgbe_open - Called when a network interface is made active
5457 * @netdev: network interface device structure
5458 *
5459 * Returns 0 on success, negative value on failure
5460 *
5461 * The open entry point is called when a network interface is made
5462 * active by the system (IFF_UP). At this point all resources needed
5463 * for transmit and receive operations are allocated, the interrupt
5464 * handler is registered with the OS, the watchdog timer is started,
5465 * and the stack is notified that the interface is ready.
5466 **/
5467static int ixgbe_open(struct net_device *netdev)
5468{
5469 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5470 int err;
4bebfaa5
AK		 5471
5472 /* disallow open during test */
5473 if (test_bit(__IXGBE_TESTING, &adapter->state))
5474 return -EBUSY;
9a799d71 5475
54386467
JB		 5476 netif_carrier_off(netdev);
5477
9a799d71
AK		 5478 /* allocate transmit descriptors */
5479 err = ixgbe_setup_all_tx_resources(adapter);
5480 if (err)
5481 goto err_setup_tx;
5482
9a799d71
AK		 5483 /* allocate receive descriptors */
5484 err = ixgbe_setup_all_rx_resources(adapter);
5485 if (err)
5486 goto err_setup_rx;
5487
5488 ixgbe_configure(adapter);
5489
021230d4 5490 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5491 if (err)
5492 goto err_req_irq;
5493
9a799d71
AK		 5494 err = ixgbe_up_complete(adapter);
5495 if (err)
5496 goto err_up;
5497
d55b53ff
JK		 5498 netif_tx_start_all_queues(netdev);
5499
9a799d71
AK		 5500 return 0;
5501
5502err_up:
5eba3699 5503 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5504 ixgbe_free_irq(adapter);
5505err_req_irq:
9a799d71 5506err_setup_rx:
a20a1199 5507 ixgbe_free_all_rx_resources(adapter);
9a799d71 5508err_setup_tx:
a20a1199 5509 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5510 ixgbe_reset(adapter);
5511
5512 return err;
5513}
5514
5515/**
5516 * ixgbe_close - Disables a network interface
5517 * @netdev: network interface device structure
5518 *
5519 * Returns 0, this is not allowed to fail
5520 *
5521 * The close entry point is called when an interface is de-activated
5522 * by the OS. The hardware is still under the drivers control, but
5523 * needs to be disabled. A global MAC reset is issued to stop the
5524 * hardware, and all transmit and receive resources are freed.
5525 **/
5526static int ixgbe_close(struct net_device *netdev)
5527{
5528 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5529
5530 ixgbe_down(adapter);
5531 ixgbe_free_irq(adapter);
5532
5533 ixgbe_free_all_tx_resources(adapter);
5534 ixgbe_free_all_rx_resources(adapter);
5535
5eba3699 5536 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5537
5538 return 0;
5539}
5540
b3c8b4ba
AD		 5541#ifdef CONFIG_PM
5542static int ixgbe_resume(struct pci_dev *pdev)
5543{
c60fbb00
AD		 5544 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5545 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5546 u32 err;
5547
5548 pci_set_power_state(pdev, PCI_D0);
5549 pci_restore_state(pdev);
656ab817
DS		 5550 /*
5551 * pci_restore_state clears dev->state_saved so call
5552 * pci_save_state to restore it.
5553 */
5554 pci_save_state(pdev);
9ce77666 5555
5556 err = pci_enable_device_mem(pdev);
b3c8b4ba 5557 if (err) {
849c4542 5558 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5559 return err;
5560 }
5561 pci_set_master(pdev);
5562
dd4d8ca6 5563 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5564
5565 err = ixgbe_init_interrupt_scheme(adapter);
5566 if (err) {
849c4542 5567 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5568 return err;
5569 }
5570
b3c8b4ba
AD		 5571 ixgbe_reset(adapter);
5572
495dce12
WJP		 5573 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5574
b3c8b4ba 5575 if (netif_running(netdev)) {
c60fbb00 5576 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5577 if (err)
5578 return err;
5579 }
5580
5581 netif_device_attach(netdev);
5582
5583 return 0;
5584}
b3c8b4ba 5585#endif /* CONFIG_PM */
9d8d05ae
RW		 5586
5587static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5588{
c60fbb00
AD		 5589 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5590 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5591 struct ixgbe_hw *hw = &adapter->hw;
5592 u32 ctrl, fctrl;
5593 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5594#ifdef CONFIG_PM
5595 int retval = 0;
5596#endif
5597
5598 netif_device_detach(netdev);
5599
5600 if (netif_running(netdev)) {
5601 ixgbe_down(adapter);
5602 ixgbe_free_irq(adapter);
5603 ixgbe_free_all_tx_resources(adapter);
5604 ixgbe_free_all_rx_resources(adapter);
5605 }
b3c8b4ba 5606
5f5ae6fc
AD		 5607 ixgbe_clear_interrupt_scheme(adapter);
5608
b3c8b4ba
AD		 5609#ifdef CONFIG_PM
5610 retval = pci_save_state(pdev);
5611 if (retval)
5612 return retval;
4df10466 5613
b3c8b4ba 5614#endif
e8e26350
PW		 5615 if (wufc) {
5616 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5617
e8e26350
PW		 5618 /* turn on all-multi mode if wake on multicast is enabled */
5619 if (wufc & IXGBE_WUFC_MC) {
5620 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5621 fctrl |= IXGBE_FCTRL_MPE;
5622 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5623 }
5624
5625 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5626 ctrl |= IXGBE_CTRL_GIO_DIS;
5627 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5628
5629 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5630 } else {
5631 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5632 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5633 }
5634
bd508178
AD		 5635 switch (hw->mac.type) {
5636 case ixgbe_mac_82598EB:
dd4d8ca6 5637 pci_wake_from_d3(pdev, false);
bd508178
AD		 5638 break;
5639 case ixgbe_mac_82599EB:
b93a2226 5640 case ixgbe_mac_X540:
bd508178
AD		 5641 pci_wake_from_d3(pdev, !!wufc);
5642 break;
5643 default:
5644 break;
5645 }
b3c8b4ba 5646
9d8d05ae
RW		 5647 *enable_wake = !!wufc;
5648
b3c8b4ba
AD		 5649 ixgbe_release_hw_control(adapter);
5650
5651 pci_disable_device(pdev);
5652
9d8d05ae
RW		 5653 return 0;
5654}
5655
5656#ifdef CONFIG_PM
5657static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5658{
5659 int retval;
5660 bool wake;
5661
5662 retval = __ixgbe_shutdown(pdev, &wake);
5663 if (retval)
5664 return retval;
5665
5666 if (wake) {
5667 pci_prepare_to_sleep(pdev);
5668 } else {
5669 pci_wake_from_d3(pdev, false);
5670 pci_set_power_state(pdev, PCI_D3hot);
5671 }
b3c8b4ba
AD		 5672
5673 return 0;
5674}
9d8d05ae 5675#endif /* CONFIG_PM */
b3c8b4ba
AD		 5676
5677static void ixgbe_shutdown(struct pci_dev *pdev)
5678{
9d8d05ae
RW		 5679 bool wake;
5680
5681 __ixgbe_shutdown(pdev, &wake);
5682
5683 if (system_state == SYSTEM_POWER_OFF) {
5684 pci_wake_from_d3(pdev, wake);
5685 pci_set_power_state(pdev, PCI_D3hot);
5686 }
b3c8b4ba
AD		 5687}
5688
9a799d71
AK		 5689/**
5690 * ixgbe_update_stats - Update the board statistics counters.
5691 * @adapter: board private structure
5692 **/
5693void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5694{
2d86f139 5695 struct net_device *netdev = adapter->netdev;
9a799d71 5696 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5697 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5698 u64 total_mpc = 0;
5699 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5700 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5701 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5702 u64 bytes = 0, packets = 0;
9a799d71 5703
d08935c2
DS		 5704 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5705 test_bit(__IXGBE_RESETTING, &adapter->state))
5706 return;
5707
94b982b2 5708 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5709 u64 rsc_count = 0;
94b982b2 5710 u64 rsc_flush = 0;
d51019a4
PW		 5711 for (i = 0; i < 16; i++)
5712 adapter->hw_rx_no_dma_resources +=
7ca647bd 5713 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5714 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5715 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5716 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5717 }
5718 adapter->rsc_total_count = rsc_count;
5719 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5720 }
5721
5b7da515
AD		 5722 for (i = 0; i < adapter->num_rx_queues; i++) {
5723 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5724 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5725 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5726 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5727 bytes += rx_ring->stats.bytes;
5728 packets += rx_ring->stats.packets;
5729 }
5730 adapter->non_eop_descs = non_eop_descs;
5731 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5732 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5733 netdev->stats.rx_bytes = bytes;
5734 netdev->stats.rx_packets = packets;
5735
5736 bytes = 0;
5737 packets = 0;
7ca3bc58 5738 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5739 for (i = 0; i < adapter->num_tx_queues; i++) {
5740 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5741 restart_queue += tx_ring->tx_stats.restart_queue;
5742 tx_busy += tx_ring->tx_stats.tx_busy;
5743 bytes += tx_ring->stats.bytes;
5744 packets += tx_ring->stats.packets;
5745 }
eb985f09 5746 adapter->restart_queue = restart_queue;
5b7da515
AD		 5747 adapter->tx_busy = tx_busy;
5748 netdev->stats.tx_bytes = bytes;
5749 netdev->stats.tx_packets = packets;
7ca3bc58 5750
7ca647bd 5751 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5752 for (i = 0; i < 8; i++) {
5753 /* for packet buffers not used, the register should read 0 */
5754 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5755 missed_rx += mpc;
7ca647bd
JP		 5756 hwstats->mpc[i] += mpc;
5757 total_mpc += hwstats->mpc[i];
e8e26350 5758 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5759 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5760 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5761 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5762 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5763 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5764 switch (hw->mac.type) {
5765 case ixgbe_mac_82598EB:
7ca647bd
JP		 5766 hwstats->pxonrxc[i] +=
5767 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5768 break;
5769 case ixgbe_mac_82599EB:
b93a2226 5770 case ixgbe_mac_X540:
bd508178
AD		 5771 hwstats->pxonrxc[i] +=
5772 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5773 break;
5774 default:
5775 break;
e8e26350 5776 }
7ca647bd
JP		 5777 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5778 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5779 }
7ca647bd 5780 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5781 /* work around hardware counting issue */
7ca647bd 5782 hwstats->gprc -= missed_rx;
6f11eef7 5783
c84d324c
JF		 5784 ixgbe_update_xoff_received(adapter);
5785
6f11eef7 5786 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5787 switch (hw->mac.type) {
5788 case ixgbe_mac_82598EB:
5789 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5790 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5791 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5792 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5793 break;
5794 case ixgbe_mac_82599EB:
b93a2226 5795 case ixgbe_mac_X540:
7ca647bd 5796 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5797 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5798 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5799 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5800 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5801 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5802 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5803 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5804 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5805#ifdef IXGBE_FCOE
7ca647bd
JP		 5806 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5807 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5808 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5809 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5810 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5811 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5812#endif /* IXGBE_FCOE */
bd508178
AD		 5813 break;
5814 default:
5815 break;
e8e26350 5816 }
9a799d71 5817 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5818 hwstats->bprc += bprc;
5819 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5820 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5821 hwstats->mprc -= bprc;
5822 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5823 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5824 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5825 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5826 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5827 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5828 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5829 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5830 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5831 hwstats->lxontxc += lxon;
6f11eef7 5832 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5833 hwstats->lxofftxc += lxoff;
5834 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5835 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5836 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5837 /*
5838 * 82598 errata - tx of flow control packets is included in tx counters
5839 */
5840 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5841 hwstats->gptc -= xon_off_tot;
5842 hwstats->mptc -= xon_off_tot;
5843 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5844 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5845 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5846 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5847 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5848 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5849 hwstats->ptc64 -= xon_off_tot;
5850 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5851 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5852 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5853 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5854 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5855 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5856
5857 /* Fill out the OS statistics structure */
7ca647bd 5858 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5859
5860 /* Rx Errors */
7ca647bd 5861 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5862 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5863 netdev->stats.rx_length_errors = hwstats->rlec;
5864 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5865 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5866}
5867
5868/**
5869 * ixgbe_watchdog - Timer Call-back
5870 * @data: pointer to adapter cast into an unsigned long
5871 **/
5872static void ixgbe_watchdog(unsigned long data)
5873{
5874 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5875 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5876 u64 eics = 0;
5877 int i;
cf8280ee 5878
fe49f04a
AD		 5879 /*
5880 * Do the watchdog outside of interrupt context due to the lovely
5881 * delays that some of the newer hardware requires
5882 */
22d5a71b 5883
fe49f04a
AD		 5884 if (test_bit(__IXGBE_DOWN, &adapter->state))
5885 goto watchdog_short_circuit;
22d5a71b 5886
fe49f04a
AD		 5887 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5888 /*
5889 * for legacy and MSI interrupts don't set any bits
5890 * that are enabled for EIAM, because this operation
5891 * would set *both* EIMS and EICS for any bit in EIAM
5892 */
5893 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5894 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5895 goto watchdog_reschedule;
5896 }
5897
5898 /* get one bit for every active tx/rx interrupt vector */
5899 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5900 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5901 if (qv->rxr_count || qv->txr_count)
5902 eics |= ((u64)1 << i);
cf8280ee 5903 }
9a799d71 5904
fe49f04a
AD		 5905 /* Cause software interrupt to ensure rx rings are cleaned */
5906 ixgbe_irq_rearm_queues(adapter, eics);
5907
5908watchdog_reschedule:
5909 /* Reset the timer */
5910 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5911
5912watchdog_short_circuit:
cf8280ee
JB		 5913 schedule_work(&adapter->watchdog_task);
5914}
5915
e8e26350
PW		 5916/**
5917 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5918 * @work: pointer to work_struct containing our data
5919 **/
5920static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5921{
5922 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5923 struct ixgbe_adapter,
5924 multispeed_fiber_task);
e8e26350
PW		 5925 struct ixgbe_hw *hw = &adapter->hw;
5926 u32 autoneg;
8620a103 5927 bool negotiation;
e8e26350
PW		 5928
5929 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5930 autoneg = hw->phy.autoneg_advertised;
5931 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5932 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5933 hw->mac.autotry_restart = false;
8620a103
MC		 5934 if (hw->mac.ops.setup_link)
5935 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5936 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5937 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5938}
5939
5940/**
5941 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5942 * @work: pointer to work_struct containing our data
5943 **/
5944static void ixgbe_sfp_config_module_task(struct work_struct *work)
5945{
5946 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5947 struct ixgbe_adapter,
5948 sfp_config_module_task);
e8e26350
PW		 5949 struct ixgbe_hw *hw = &adapter->hw;
5950 u32 err;
5951
5952 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5953
5954 /* Time for electrical oscillations to settle down */
5955 msleep(100);
e8e26350 5956 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5957
e8e26350 5958 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5959 e_dev_err("failed to initialize because an unsupported SFP+ "
5960 "module type was detected.\n");
5961 e_dev_err("Reload the driver after installing a supported "
5962 "module.\n");
63d6e1d8 5963 unregister_netdev(adapter->netdev);
e8e26350
PW		 5964 return;
5965 }
5966 hw->mac.ops.setup_sfp(hw);
5967
8d1c3c07 5968 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5969 /* This will also work for DA Twinax connections */
5970 schedule_work(&adapter->multispeed_fiber_task);
5971 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5972}
5973
c4cf55e5
PWJ		 5974/**
5975 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5976 * @work: pointer to work_struct containing our data
5977 **/
5978static void ixgbe_fdir_reinit_task(struct work_struct *work)
5979{
5980 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5981 struct ixgbe_adapter,
5982 fdir_reinit_task);
c4cf55e5
PWJ		 5983 struct ixgbe_hw *hw = &adapter->hw;
5984 int i;
5985
5986 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5987 for (i = 0; i < adapter->num_tx_queues; i++)
7d637bcc
AD		 5988 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5989 &(adapter->tx_ring[i]->state));
c4cf55e5 5990 } else {
396e799c 5991 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5992 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5993 }
5994 /* Done FDIR Re-initialization, enable transmits */
5995 netif_tx_start_all_queues(adapter->netdev);
5996}
5997
a985b6c3
GR		 5998static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5999{
6000 u32 ssvpc;
6001
6002 /* Do not perform spoof check for 82598 */
6003 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6004 return;
6005
6006 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6007
6008 /*
6009 * ssvpc register is cleared on read, if zero then no
6010 * spoofed packets in the last interval.
6011 */
6012 if (!ssvpc)
6013 return;
6014
6015 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6016}
6017
10eec955
JF		 6018static DEFINE_MUTEX(ixgbe_watchdog_lock);
6019
cf8280ee 6020/**
69888674
AD		 6021 * ixgbe_watchdog_task - worker thread to bring link up
6022 * @work: pointer to work_struct containing our data
cf8280ee
JB		 6023 **/
6024static void ixgbe_watchdog_task(struct work_struct *work)
6025{
6026 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6027 struct ixgbe_adapter,
6028 watchdog_task);
cf8280ee
JB		 6029 struct net_device *netdev = adapter->netdev;
6030 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 6031 u32 link_speed;
6032 bool link_up;
bc59fcda
NS		 6033 int i;
6034 struct ixgbe_ring *tx_ring;
6035 int some_tx_pending = 0;
cf8280ee 6036
10eec955
JF		 6037 mutex_lock(&ixgbe_watchdog_lock);
6038
6039 link_up = adapter->link_up;
6040 link_speed = adapter->link_speed;
cf8280ee
JB		 6041
6042 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6043 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 6044 if (link_up) {
6045#ifdef CONFIG_DCB
6046 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6047 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 6048 hw->mac.ops.fc_enable(hw, i);
264857b8 6049 } else {
620fa036 6050 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 6051 }
6052#else
620fa036 6053 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 6054#endif
6055 }
6056
cf8280ee
JB		 6057 if (link_up ||
6058 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 6059 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 6060 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 6061 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 6062 }
6063 adapter->link_up = link_up;
6064 adapter->link_speed = link_speed;
6065 }
9a799d71
AK		 6066
6067 if (link_up) {
6068 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 6069 bool flow_rx, flow_tx;
6070
bd508178
AD		 6071 switch (hw->mac.type) {
6072 case ixgbe_mac_82598EB: {
e8e26350
PW		 6073 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6074 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 6075 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6076 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350 6077 }
bd508178 6078 break;
b93a2226
DS		 6079 case ixgbe_mac_82599EB:
6080 case ixgbe_mac_X540: {
bd508178
AD		 6081 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6082 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6083 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6084 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6085 }
6086 break;
6087 default:
6088 flow_tx = false;
6089 flow_rx = false;
6090 break;
6091 }
e8e26350 6092
396e799c 6093 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 6094 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 6095 "10 Gbps" :
6096 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6097 "1 Gbps" : "unknown speed")),
e8e26350 6098 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 6099 (flow_rx ? "RX" :
6100 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 6101
6102 netif_carrier_on(netdev);
9a799d71
AK		 6103 } else {
6104 /* Force detection of hung controller */
7d637bcc
AD		 6105 for (i = 0; i < adapter->num_tx_queues; i++) {
6106 tx_ring = adapter->tx_ring[i];
6107 set_check_for_tx_hang(tx_ring);
6108 }
9a799d71
AK		 6109 }
6110 } else {
cf8280ee
JB		 6111 adapter->link_up = false;
6112 adapter->link_speed = 0;
9a799d71 6113 if (netif_carrier_ok(netdev)) {
396e799c 6114 e_info(drv, "NIC Link is Down\n");
9a799d71 6115 netif_carrier_off(netdev);
9a799d71
AK		 6116 }
6117 }
6118
bc59fcda
NS		 6119 if (!netif_carrier_ok(netdev)) {
6120 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 6121 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6122 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6123 some_tx_pending = 1;
6124 break;
6125 }
6126 }
6127
6128 if (some_tx_pending) {
6129 /* We've lost link, so the controller stops DMA,
6130 * but we've got queued Tx work that's never going
6131 * to get done, so reset controller to flush Tx.
6132 * (Do the reset outside of interrupt context).
6133 */
6134 schedule_work(&adapter->reset_task);
6135 }
6136 }
6137
a985b6c3 6138 ixgbe_spoof_check(adapter);
9a799d71 6139 ixgbe_update_stats(adapter);
10eec955 6140 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 6141}
6142
9a799d71 6143static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 6144 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 6145 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 6146{
6147 struct ixgbe_adv_tx_context_desc *context_desc;
6148 unsigned int i;
6149 int err;
6150 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 6151 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6152 u32 mss_l4len_idx, l4len;
9a799d71
AK		 6153
6154 if (skb_is_gso(skb)) {
6155 if (skb_header_cloned(skb)) {
6156 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6157 if (err)
6158 return err;
6159 }
6160 l4len = tcp_hdrlen(skb);
6161 *hdr_len += l4len;
6162
5e09a105 6163 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 6164 struct iphdr *iph = ip_hdr(skb);
6165 iph->tot_len = 0;
6166 iph->check = 0;
6167 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 6168 iph->daddr, 0,
6169 IPPROTO_TCP,
6170 0);
8e1e8a47 6171 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 6172 ipv6_hdr(skb)->payload_len = 0;
6173 tcp_hdr(skb)->check =
6174 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 6175 &ipv6_hdr(skb)->daddr,
6176 0, IPPROTO_TCP, 0);
9a799d71
AK		 6177 }
6178
6179 i = tx_ring->next_to_use;
6180
6181 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6182 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6183
6184 /* VLAN MACLEN IPLEN */
6185 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6186 vlan_macip_lens |=
6187 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6188 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6189 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6190 *hdr_len += skb_network_offset(skb);
6191 vlan_macip_lens |=
6192 (skb_transport_header(skb) - skb_network_header(skb));
6193 *hdr_len +=
6194 (skb_transport_header(skb) - skb_network_header(skb));
6195 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6196 context_desc->seqnum_seed = 0;
6197
6198 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6199 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6200 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6201
5e09a105 6202 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6203 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6204 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6205 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6206
6207 /* MSS L4LEN IDX */
9f8cdf4f 6208 mss_l4len_idx =
9a799d71
AK		 6209 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6210 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6211 /* use index 1 for TSO */
6212 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6213 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6214
6215 tx_buffer_info->time_stamp = jiffies;
6216 tx_buffer_info->next_to_watch = i;
6217
6218 i++;
6219 if (i == tx_ring->count)
6220 i = 0;
6221 tx_ring->next_to_use = i;
6222
6223 return true;
6224 }
6225 return false;
6226}
6227
5e09a105
HZ		 6228static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6229 __be16 protocol)
7ca647bd
JP		 6230{
6231 u32 rtn = 0;
7ca647bd
JP		 6232
6233 switch (protocol) {
6234 case cpu_to_be16(ETH_P_IP):
6235 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6236 switch (ip_hdr(skb)->protocol) {
6237 case IPPROTO_TCP:
6238 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6239 break;
6240 case IPPROTO_SCTP:
6241 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6242 break;
6243 }
6244 break;
6245 case cpu_to_be16(ETH_P_IPV6):
6246 /* XXX what about other V6 headers?? */
6247 switch (ipv6_hdr(skb)->nexthdr) {
6248 case IPPROTO_TCP:
6249 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6250 break;
6251 case IPPROTO_SCTP:
6252 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6253 break;
6254 }
6255 break;
6256 default:
6257 if (unlikely(net_ratelimit()))
6258 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6259 protocol);
7ca647bd
JP		 6260 break;
6261 }
6262
6263 return rtn;
6264}
6265
9a799d71 6266static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6267 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6268 struct sk_buff *skb, u32 tx_flags,
6269 __be16 protocol)
9a799d71
AK		 6270{
6271 struct ixgbe_adv_tx_context_desc *context_desc;
6272 unsigned int i;
6273 struct ixgbe_tx_buffer *tx_buffer_info;
6274 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6275
6276 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6277 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6278 i = tx_ring->next_to_use;
6279 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6280 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6281
6282 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6283 vlan_macip_lens |=
6284 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6285 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6286 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6287 if (skb->ip_summed == CHECKSUM_PARTIAL)
6288 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6289 skb_network_header(skb));
9a799d71
AK		 6290
6291 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6292 context_desc->seqnum_seed = 0;
6293
6294 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6295 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6296
7ca647bd 6297 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6298 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6299
6300 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6301 /* use index zero for tx checksum offload */
9a799d71
AK		 6302 context_desc->mss_l4len_idx = 0;
6303
6304 tx_buffer_info->time_stamp = jiffies;
6305 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6306
9a799d71
AK		 6307 i++;
6308 if (i == tx_ring->count)
6309 i = 0;
6310 tx_ring->next_to_use = i;
6311
6312 return true;
6313 }
9f8cdf4f 6314
9a799d71
AK		 6315 return false;
6316}
6317
6318static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6319 struct ixgbe_ring *tx_ring,
6320 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6321 unsigned int first, const u8 hdr_len)
9a799d71 6322{
b6ec895e 6323 struct device *dev = tx_ring->dev;
9a799d71 6324 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6325 unsigned int len;
6326 unsigned int total = skb->len;
9a799d71
AK		 6327 unsigned int offset = 0, size, count = 0, i;
6328 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6329 unsigned int f;
8ad494b0
AD		 6330 unsigned int bytecount = skb->len;
6331 u16 gso_segs = 1;
9a799d71
AK		 6332
6333 i = tx_ring->next_to_use;
6334
eacd73f7
YZ		 6335 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6336 /* excluding fcoe_crc_eof for FCoE */
6337 total -= sizeof(struct fcoe_crc_eof);
6338
6339 len = min(skb_headlen(skb), total);
9a799d71
AK		 6340 while (len) {
6341 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6342 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6343
6344 tx_buffer_info->length = size;
e5a43549 6345 tx_buffer_info->mapped_as_page = false;
b6ec895e 6346 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6347 skb->data + offset,
1b507730 6348 size, DMA_TO_DEVICE);
b6ec895e 6349 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6350 goto dma_error;
9a799d71
AK		 6351 tx_buffer_info->time_stamp = jiffies;
6352 tx_buffer_info->next_to_watch = i;
6353
6354 len -= size;
eacd73f7 6355 total -= size;
9a799d71
AK		 6356 offset += size;
6357 count++;
44df32c5
AD		 6358
6359 if (len) {
6360 i++;
6361 if (i == tx_ring->count)
6362 i = 0;
6363 }
9a799d71
AK		 6364 }
6365
6366 for (f = 0; f < nr_frags; f++) {
6367 struct skb_frag_struct *frag;
6368
6369 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6370 len = min((unsigned int)frag->size, total);
e5a43549 6371 offset = frag->page_offset;
9a799d71
AK		 6372
6373 while (len) {
44df32c5
AD		 6374 i++;
6375 if (i == tx_ring->count)
6376 i = 0;
6377
9a799d71
AK		 6378 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6379 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6380
6381 tx_buffer_info->length = size;
b6ec895e 6382 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6383 frag->page,
6384 offset, size,
1b507730 6385 DMA_TO_DEVICE);
e5a43549 6386 tx_buffer_info->mapped_as_page = true;
b6ec895e 6387 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6388 goto dma_error;
9a799d71
AK		 6389 tx_buffer_info->time_stamp = jiffies;
6390 tx_buffer_info->next_to_watch = i;
6391
6392 len -= size;
eacd73f7 6393 total -= size;
9a799d71
AK		 6394 offset += size;
6395 count++;
9a799d71 6396 }
eacd73f7
YZ		 6397 if (total == 0)
6398 break;
9a799d71 6399 }
44df32c5 6400
8ad494b0
AD		 6401 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6402 gso_segs = skb_shinfo(skb)->gso_segs;
6403#ifdef IXGBE_FCOE
6404 /* adjust for FCoE Sequence Offload */
6405 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6406 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6407 skb_shinfo(skb)->gso_size);
6408#endif /* IXGBE_FCOE */
6409 bytecount += (gso_segs - 1) * hdr_len;
6410
6411 /* multiply data chunks by size of headers */
6412 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6413 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6414 tx_ring->tx_buffer_info[i].skb = skb;
6415 tx_ring->tx_buffer_info[first].next_to_watch = i;
6416
e5a43549
AD		 6417 return count;
6418
6419dma_error:
849c4542 6420 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6421
6422 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6423 tx_buffer_info->dma = 0;
6424 tx_buffer_info->time_stamp = 0;
6425 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6426 if (count)
6427 count--;
e5a43549
AD		 6428
6429 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6430 while (count--) {
e8e9f696 6431 if (i == 0)
e5a43549 6432 i += tx_ring->count;
c1fa347f 6433 i--;
e5a43549 6434 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6435 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6436 }
6437
e44d38e1 6438 return 0;
9a799d71
AK		 6439}
6440
84ea2591 6441static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6442 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6443{
6444 union ixgbe_adv_tx_desc *tx_desc = NULL;
6445 struct ixgbe_tx_buffer *tx_buffer_info;
6446 u32 olinfo_status = 0, cmd_type_len = 0;
6447 unsigned int i;
6448 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6449
6450 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6451
6452 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6453
6454 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6455 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6456
6457 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6458 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6459
6460 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6461 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6462
4eeae6fd
PW		 6463 /* use index 1 context for tso */
6464 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6465 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6466 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6467 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6468
6469 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6470 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6471 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6472
eacd73f7
YZ		 6473 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6474 olinfo_status |= IXGBE_ADVTXD_CC;
6475 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6476 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6477 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6478 }
6479
9a799d71
AK		 6480 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6481
6482 i = tx_ring->next_to_use;
6483 while (count--) {
6484 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6485 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6486 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6487 tx_desc->read.cmd_type_len =
e8e9f696 6488 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6489 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6490 i++;
6491 if (i == tx_ring->count)
6492 i = 0;
6493 }
6494
6495 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6496
6497 /*
6498 * Force memory writes to complete before letting h/w
6499 * know there are new descriptors to fetch. (Only
6500 * applicable for weak-ordered memory model archs,
6501 * such as IA-64).
6502 */
6503 wmb();
6504
6505 tx_ring->next_to_use = i;
84ea2591 6506 writel(i, tx_ring->tail);
9a799d71
AK		 6507}
6508
c4cf55e5 6509static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
ee9e0f0b 6510 u8 queue, u32 tx_flags, __be16 protocol)
c4cf55e5 6511{
905e4a41 6512 union ixgbe_atr_input atr_input;
c4cf55e5
PWJ		 6513 struct iphdr *iph = ip_hdr(skb);
6514 struct ethhdr *eth = (struct ethhdr *)skb->data;
ee9e0f0b 6515 struct tcphdr *th;
905e4a41 6516 __be16 vlan_id;
c4cf55e5 6517
ee9e0f0b
AD		 6518 /* Right now, we support IPv4 w/ TCP only */
6519 if (protocol != htons(ETH_P_IP) ||
6520 iph->protocol != IPPROTO_TCP)
d3ead241 6521 return;
c4cf55e5 6522
905e4a41 6523 memset(&atr_input, 0, sizeof(union ixgbe_atr_input));
c4cf55e5 6524
905e4a41 6525 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
ee9e0f0b
AD		 6526
6527 th = tcp_hdr(skb);
c4cf55e5
PWJ		 6528
6529 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
ee9e0f0b
AD		 6530 ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6531 ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6532 ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
905e4a41 6533 ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_FLOW_TYPE_TCPV4);
c4cf55e5 6534 /* src and dst are inverted, think how the receiver sees them */
ee9e0f0b
AD		 6535 ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6536 ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
c4cf55e5
PWJ		 6537
6538 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6539 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6540}
6541
fc77dc3c 6542static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6543{
fc77dc3c 6544 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6545 /* Herbert's original patch had:
6546 * smp_mb__after_netif_stop_queue();
6547 * but since that doesn't exist yet, just open code it. */
6548 smp_mb();
6549
6550 /* We need to check again in a case another CPU has just
6551 * made room available. */
6552 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6553 return -EBUSY;
6554
6555 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6556 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6557 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6558 return 0;
6559}
6560
fc77dc3c 6561static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6562{
6563 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6564 return 0;
fc77dc3c 6565 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6566}
6567
09a3b1f8
SH		 6568static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6569{
6570 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6571 int txq = smp_processor_id();
56075a98 6572#ifdef IXGBE_FCOE
5e09a105
HZ		 6573 __be16 protocol;
6574
6575 protocol = vlan_get_protocol(skb);
6576
6577 if ((protocol == htons(ETH_P_FCOE)) ||
6578 (protocol == htons(ETH_P_FIP))) {
56075a98
JF		 6579 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6580 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6581 txq += adapter->ring_feature[RING_F_FCOE].mask;
6582 return txq;
4bc091d8 6583#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6584 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6585 txq = adapter->fcoe.up;
6586 return txq;
4bc091d8 6587#endif
56075a98
JF		 6588 }
6589 }
6590#endif
6591
fdd3d631
KK		 6592 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6593 while (unlikely(txq >= dev->real_num_tx_queues))
6594 txq -= dev->real_num_tx_queues;
5f715823 6595 return txq;
fdd3d631 6596 }
c4cf55e5 6597
2ea186ae
JF		 6598 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6599 if (skb->priority == TC_PRIO_CONTROL)
6600 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6601 else
6602 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6603 >> 13;
6604 return txq;
6605 }
09a3b1f8
SH		 6606
6607 return skb_tx_hash(dev, skb);
6608}
6609
fc77dc3c 6610netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6611 struct ixgbe_adapter *adapter,
6612 struct ixgbe_ring *tx_ring)
9a799d71 6613{
fc77dc3c 6614 struct net_device *netdev = tx_ring->netdev;
60d51134 6615 struct netdev_queue *txq;
9a799d71
AK		 6616 unsigned int first;
6617 unsigned int tx_flags = 0;
30eba97a 6618 u8 hdr_len = 0;
5f715823 6619 int tso;
9a799d71
AK		 6620 int count = 0;
6621 unsigned int f;
5e09a105
HZ		 6622 __be16 protocol;
6623
6624 protocol = vlan_get_protocol(skb);
9f8cdf4f 6625
eab6d18d 6626 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6627 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6628 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6629 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6630 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6631 }
6632 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6633 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6634 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6635 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6636 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6637 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6638 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6639 }
eacd73f7 6640
09ad1cc0 6641#ifdef IXGBE_FCOE
56075a98
JF		 6642 /* for FCoE with DCB, we force the priority to what
6643 * was specified by the switch */
6644 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
5e09a105
HZ		 6645 (protocol == htons(ETH_P_FCOE) ||
6646 protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6647#ifdef CONFIG_IXGBE_DCB
6648 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6649 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6650 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6651 tx_flags |= ((adapter->fcoe.up << 13)
6652 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6653 }
6654#endif
ca77cd59 6655 /* flag for FCoE offloads */
5e09a105 6656 if (protocol == htons(ETH_P_FCOE))
ca77cd59 6657 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6658 }
ca77cd59
RL		 6659#endif
6660
eacd73f7 6661 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6662 if (skb_is_gso(skb) ||
6663 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6664 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6665 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6666 count++;
6667
9f8cdf4f
JB		 6668 count += TXD_USE_COUNT(skb_headlen(skb));
6669 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6670 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6671
fc77dc3c 6672 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6673 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6674 return NETDEV_TX_BUSY;
6675 }
9a799d71 6676
9a799d71 6677 first = tx_ring->next_to_use;
eacd73f7
YZ		 6678 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6679#ifdef IXGBE_FCOE
6680 /* setup tx offload for FCoE */
6681 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6682 if (tso < 0) {
6683 dev_kfree_skb_any(skb);
6684 return NETDEV_TX_OK;
6685 }
6686 if (tso)
6687 tx_flags |= IXGBE_TX_FLAGS_FSO;
6688#endif /* IXGBE_FCOE */
6689 } else {
5e09a105 6690 if (protocol == htons(ETH_P_IP))
eacd73f7 6691 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6692 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6693 protocol);
eacd73f7
YZ		 6694 if (tso < 0) {
6695 dev_kfree_skb_any(skb);
6696 return NETDEV_TX_OK;
6697 }
9a799d71 6698
eacd73f7
YZ		 6699 if (tso)
6700 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6701 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6702 protocol) &&
eacd73f7
YZ		 6703 (skb->ip_summed == CHECKSUM_PARTIAL))
6704 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6705 }
9a799d71 6706
8ad494b0 6707 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6708 if (count) {
c4cf55e5
PWJ		 6709 /* add the ATR filter if ATR is on */
6710 if (tx_ring->atr_sample_rate) {
6711 ++tx_ring->atr_count;
6712 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
7d637bcc
AD		 6713 test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6714 &tx_ring->state)) {
c4cf55e5 6715 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5e09a105 6716 tx_flags, protocol);
c4cf55e5
PWJ		 6717 tx_ring->atr_count = 0;
6718 }
6719 }
60d51134
ED		 6720 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6721 txq->tx_bytes += skb->len;
6722 txq->tx_packets++;
84ea2591 6723 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6724 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6725
44df32c5
AD		 6726 } else {
6727 dev_kfree_skb_any(skb);
6728 tx_ring->tx_buffer_info[first].time_stamp = 0;
6729 tx_ring->next_to_use = first;
6730 }
9a799d71
AK		 6731
6732 return NETDEV_TX_OK;
6733}
6734
84418e3b
AD		 6735static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6736{
6737 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6738 struct ixgbe_ring *tx_ring;
6739
6740 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6741 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6742}
6743
9a799d71
AK		 6744/**
6745 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6746 * @netdev: network interface device structure
6747 * @p: pointer to an address structure
6748 *
6749 * Returns 0 on success, negative on failure
6750 **/
6751static int ixgbe_set_mac(struct net_device *netdev, void *p)
6752{
6753 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6754 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6755 struct sockaddr *addr = p;
6756
6757 if (!is_valid_ether_addr(addr->sa_data))
6758 return -EADDRNOTAVAIL;
6759
6760 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6761 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6762
1cdd1ec8
GR		 6763 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6764 IXGBE_RAH_AV);
9a799d71
AK		 6765
6766 return 0;
6767}
6768
6b73e10d
BH		 6769static int
6770ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6771{
6772 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6773 struct ixgbe_hw *hw = &adapter->hw;
6774 u16 value;
6775 int rc;
6776
6777 if (prtad != hw->phy.mdio.prtad)
6778 return -EINVAL;
6779 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6780 if (!rc)
6781 rc = value;
6782 return rc;
6783}
6784
6785static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6786 u16 addr, u16 value)
6787{
6788 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6789 struct ixgbe_hw *hw = &adapter->hw;
6790
6791 if (prtad != hw->phy.mdio.prtad)
6792 return -EINVAL;
6793 return hw->phy.ops.write_reg(hw, addr, devad, value);
6794}
6795
6796static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6797{
6798 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6799
6800 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6801}
6802
0365e6e4
PW		 6803/**
6804 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6805 * netdev->dev_addrs
0365e6e4
PW		 6806 * @netdev: network interface device structure
6807 *
6808 * Returns non-zero on failure
6809 **/
6810static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6811{
6812 int err = 0;
6813 struct ixgbe_adapter *adapter = netdev_priv(dev);
6814 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6815
6816 if (is_valid_ether_addr(mac->san_addr)) {
6817 rtnl_lock();
6818 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6819 rtnl_unlock();
6820 }
6821 return err;
6822}
6823
6824/**
6825 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6826 * netdev->dev_addrs
0365e6e4
PW		 6827 * @netdev: network interface device structure
6828 *
6829 * Returns non-zero on failure
6830 **/
6831static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6832{
6833 int err = 0;
6834 struct ixgbe_adapter *adapter = netdev_priv(dev);
6835 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6836
6837 if (is_valid_ether_addr(mac->san_addr)) {
6838 rtnl_lock();
6839 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6840 rtnl_unlock();
6841 }
6842 return err;
6843}
6844
9a799d71
AK		 6845#ifdef CONFIG_NET_POLL_CONTROLLER
6846/*
6847 * Polling 'interrupt' - used by things like netconsole to send skbs
6848 * without having to re-enable interrupts. It's not called while
6849 * the interrupt routine is executing.
6850 */
6851static void ixgbe_netpoll(struct net_device *netdev)
6852{
6853 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6854 int i;
9a799d71 6855
1a647bd2
AD		 6856 /* if interface is down do nothing */
6857 if (test_bit(__IXGBE_DOWN, &adapter->state))
6858 return;
6859
9a799d71 6860 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6861 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6862 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6863 for (i = 0; i < num_q_vectors; i++) {
6864 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6865 ixgbe_msix_clean_many(0, q_vector);
6866 }
6867 } else {
6868 ixgbe_intr(adapter->pdev->irq, netdev);
6869 }
9a799d71 6870 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6871}
6872#endif
6873
de1036b1
ED		 6874static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6875 struct rtnl_link_stats64 *stats)
6876{
6877 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6878 int i;
6879
6880 /* accurate rx/tx bytes/packets stats */
6881 dev_txq_stats_fold(netdev, stats);
1a51502b 6882 rcu_read_lock();
de1036b1 6883 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6884 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6885 u64 bytes, packets;
6886 unsigned int start;
6887
1a51502b
ED		 6888 if (ring) {
6889 do {
6890 start = u64_stats_fetch_begin_bh(&ring->syncp);
6891 packets = ring->stats.packets;
6892 bytes = ring->stats.bytes;
6893 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6894 stats->rx_packets += packets;
6895 stats->rx_bytes += bytes;
6896 }
de1036b1 6897 }
1a51502b 6898 rcu_read_unlock();
de1036b1
ED		 6899 /* following stats updated by ixgbe_watchdog_task() */
6900 stats->multicast = netdev->stats.multicast;
6901 stats->rx_errors = netdev->stats.rx_errors;
6902 stats->rx_length_errors = netdev->stats.rx_length_errors;
6903 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6904 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6905 return stats;
6906}
6907
6908
0edc3527 6909static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6910 .ndo_open = ixgbe_open,
0edc3527 6911 .ndo_stop = ixgbe_close,
00829823 6912 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6913 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6914 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6915 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6916 .ndo_validate_addr = eth_validate_addr,
6917 .ndo_set_mac_address = ixgbe_set_mac,
6918 .ndo_change_mtu = ixgbe_change_mtu,
6919 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6920 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6921 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6922 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6923 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6924 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6925 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6926 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6927 .ndo_get_stats64 = ixgbe_get_stats64,
0edc3527
SH		 6928#ifdef CONFIG_NET_POLL_CONTROLLER
6929 .ndo_poll_controller = ixgbe_netpoll,
6930#endif
332d4a7d
YZ		 6931#ifdef IXGBE_FCOE
6932 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6933 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6934 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6935 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6936 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6937#endif /* IXGBE_FCOE */
0edc3527
SH		 6938};
6939
1cdd1ec8
GR		 6940static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6941 const struct ixgbe_info *ii)
6942{
6943#ifdef CONFIG_PCI_IOV
6944 struct ixgbe_hw *hw = &adapter->hw;
6945 int err;
6946
3377eba7 6947 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 6948 return;
6949
6950 /* The 82599 supports up to 64 VFs per physical function
6951 * but this implementation limits allocation to 63 so that
6952 * basic networking resources are still available to the
6953 * physical function
6954 */
6955 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6956 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6957 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6958 if (err) {
396e799c 6959 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6960 goto err_novfs;
6961 }
6962 /* If call to enable VFs succeeded then allocate memory
6963 * for per VF control structures.
6964 */
6965 adapter->vfinfo =
6966 kcalloc(adapter->num_vfs,
6967 sizeof(struct vf_data_storage), GFP_KERNEL);
6968 if (adapter->vfinfo) {
6969 /* Now that we're sure SR-IOV is enabled
6970 * and memory allocated set up the mailbox parameters
6971 */
6972 ixgbe_init_mbx_params_pf(hw);
6973 memcpy(&hw->mbx.ops, ii->mbx_ops,
6974 sizeof(hw->mbx.ops));
6975
6976 /* Disable RSC when in SR-IOV mode */
6977 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6978 IXGBE_FLAG2_RSC_ENABLED);
6979 return;
6980 }
6981
6982 /* Oh oh */
396e799c
ET		 6983 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6984 "SRIOV disabled\n");
1cdd1ec8
GR		 6985 pci_disable_sriov(adapter->pdev);
6986
6987err_novfs:
6988 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6989 adapter->num_vfs = 0;
6990#endif /* CONFIG_PCI_IOV */
6991}
6992
9a799d71
AK		 6993/**
6994 * ixgbe_probe - Device Initialization Routine
6995 * @pdev: PCI device information struct
6996 * @ent: entry in ixgbe_pci_tbl
6997 *
6998 * Returns 0 on success, negative on failure
6999 *
7000 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7001 * The OS initialization, configuring of the adapter private structure,
7002 * and a hardware reset occur.
7003 **/
7004static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7005 const struct pci_device_id *ent)
9a799d71
AK		 7006{
7007 struct net_device *netdev;
7008 struct ixgbe_adapter *adapter = NULL;
7009 struct ixgbe_hw *hw;
7010 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7011 static int cards_found;
7012 int i, err, pci_using_dac;
289700db 7013 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7014 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7015#ifdef IXGBE_FCOE
7016 u16 device_caps;
7017#endif
289700db 7018 u32 eec;
9a799d71 7019
bded64a7
AG		 7020 /* Catch broken hardware that put the wrong VF device ID in
7021 * the PCIe SR-IOV capability.
7022 */
7023 if (pdev->is_virtfn) {
7024 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7025 pci_name(pdev), pdev->vendor, pdev->device);
7026 return -EINVAL;
7027 }
7028
9ce77666 7029 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7030 if (err)
7031 return err;
7032
1b507730
NN		 7033 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7034 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7035 pci_using_dac = 1;
7036 } else {
1b507730 7037 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7038 if (err) {
1b507730
NN		 7039 err = dma_set_coherent_mask(&pdev->dev,
7040 DMA_BIT_MASK(32));
9a799d71 7041 if (err) {
b8bc0421
DC		 7042 dev_err(&pdev->dev,
7043 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7044 goto err_dma;
7045 }
7046 }
7047 pci_using_dac = 0;
7048 }
7049
9ce77666 7050 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7051 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7052 if (err) {
b8bc0421
DC		 7053 dev_err(&pdev->dev,
7054 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7055 goto err_pci_reg;
7056 }
7057
19d5afd4 7058 pci_enable_pcie_error_reporting(pdev);
6fabd715 7059
9a799d71 7060 pci_set_master(pdev);
fb3b27bc 7061 pci_save_state(pdev);
9a799d71 7062
c85a2618
JF		 7063 if (ii->mac == ixgbe_mac_82598EB)
7064 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7065 else
7066 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7067
7068 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7069#ifdef IXGBE_FCOE
7070 indices += min_t(unsigned int, num_possible_cpus(),
7071 IXGBE_MAX_FCOE_INDICES);
7072#endif
c85a2618 7073 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7074 if (!netdev) {
7075 err = -ENOMEM;
7076 goto err_alloc_etherdev;
7077 }
7078
9a799d71
AK		 7079 SET_NETDEV_DEV(netdev, &pdev->dev);
7080
9a799d71 7081 adapter = netdev_priv(netdev);
c60fbb00 7082 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7083
7084 adapter->netdev = netdev;
7085 adapter->pdev = pdev;
7086 hw = &adapter->hw;
7087 hw->back = adapter;
7088 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7089
05857980 7090 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7091 pci_resource_len(pdev, 0));
9a799d71
AK		 7092 if (!hw->hw_addr) {
7093 err = -EIO;
7094 goto err_ioremap;
7095 }
7096
7097 for (i = 1; i <= 5; i++) {
7098 if (pci_resource_len(pdev, i) == 0)
7099 continue;
7100 }
7101
0edc3527 7102 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7103 ixgbe_set_ethtool_ops(netdev);
9a799d71 7104 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7105 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7106
9a799d71
AK		 7107 adapter->bd_number = cards_found;
7108
9a799d71
AK		 7109 /* Setup hw api */
7110 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7111 hw->mac.type = ii->mac;
9a799d71 7112
c44ade9e
JB		 7113 /* EEPROM */
7114 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7115 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7116 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7117 if (!(eec & (1 << 8)))
7118 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7119
7120 /* PHY */
7121 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7122 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7123 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7124 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7125 hw->phy.mdio.mmds = 0;
7126 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7127 hw->phy.mdio.dev = netdev;
7128 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7129 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 7130
7131 /* set up this timer and work struct before calling get_invariants
7132 * which might start the timer
7133 */
7134 init_timer(&adapter->sfp_timer);
c061b18d 7135 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 7136 adapter->sfp_timer.data = (unsigned long) adapter;
7137
7138 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 7139
e8e26350
PW		 7140 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7141 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7142
7143 /* a new SFP+ module arrival, called from GPI SDP2 context */
7144 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 7145 ixgbe_sfp_config_module_task);
e8e26350 7146
8ca783ab 7147 ii->get_invariants(hw);
9a799d71
AK		 7148
7149 /* setup the private structure */
7150 err = ixgbe_sw_init(adapter);
7151 if (err)
7152 goto err_sw_init;
7153
e86bff0e 7154 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7155 switch (adapter->hw.mac.type) {
7156 case ixgbe_mac_82599EB:
7157 case ixgbe_mac_X540:
e86bff0e 7158 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7159 break;
7160 default:
7161 break;
7162 }
e86bff0e 7163
bf069c97
DS		 7164 /*
7165 * If there is a fan on this device and it has failed log the
7166 * failure.
7167 */
7168 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7169 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7170 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7171 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7172 }
7173
c44ade9e 7174 /* reset_hw fills in the perm_addr as well */
119fc60a 7175 hw->phy.reset_if_overtemp = true;
c44ade9e 7176 err = hw->mac.ops.reset_hw(hw);
119fc60a 7177 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7178 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7179 hw->mac.type == ixgbe_mac_82598EB) {
7180 /*
7181 * Start a kernel thread to watch for a module to arrive.
7182 * Only do this for 82598, since 82599 will generate
7183 * interrupts on module arrival.
7184 */
7185 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7186 mod_timer(&adapter->sfp_timer,
7187 round_jiffies(jiffies + (2 * HZ)));
7188 err = 0;
7189 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 7190 e_dev_err("failed to initialize because an unsupported SFP+ "
7191 "module type was detected.\n");
7192 e_dev_err("Reload the driver after installing a supported "
7193 "module.\n");
04f165ef
PW		 7194 goto err_sw_init;
7195 } else if (err) {
849c4542 7196 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7197 goto err_sw_init;
7198 }
7199
1cdd1ec8
GR		 7200 ixgbe_probe_vf(adapter, ii);
7201
396e799c 7202 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7203 NETIF_F_IP_CSUM |
7204 NETIF_F_HW_VLAN_TX |
7205 NETIF_F_HW_VLAN_RX |
7206 NETIF_F_HW_VLAN_FILTER;
9a799d71 7207
e9990a9c 7208 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7209 netdev->features |= NETIF_F_TSO;
9a799d71 7210 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7211 netdev->features |= NETIF_F_GRO;
ad31c402 7212
45a5ead0
JB		 7213 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7214 netdev->features |= NETIF_F_SCTP_CSUM;
7215
ad31c402
JK		 7216 netdev->vlan_features |= NETIF_F_TSO;
7217 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7218 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7219 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7220 netdev->vlan_features |= NETIF_F_SG;
7221
1cdd1ec8
GR		 7222 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7223 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7224 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 7225 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7226 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7227
7a6b6f51 7228#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7229 netdev->dcbnl_ops = &dcbnl_ops;
7230#endif
7231
eacd73f7 7232#ifdef IXGBE_FCOE
0d551589 7233 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7234 if (hw->mac.ops.get_device_caps) {
7235 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7236 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7237 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7238 }
7239 }
5e09d7f6
YZ		 7240 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7241 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7242 netdev->vlan_features |= NETIF_F_FSO;
7243 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7244 }
eacd73f7 7245#endif /* IXGBE_FCOE */
7b872a55 7246 if (pci_using_dac) {
9a799d71 7247 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7248 netdev->vlan_features |= NETIF_F_HIGHDMA;
7249 }
9a799d71 7250
0c19d6af 7251 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7252 netdev->features |= NETIF_F_LRO;
7253
9a799d71 7254 /* make sure the EEPROM is good */
c44ade9e 7255 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7256 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7257 err = -EIO;
7258 goto err_eeprom;
7259 }
7260
7261 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7262 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7263
c44ade9e 7264 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7265 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7266 err = -EIO;
7267 goto err_eeprom;
7268 }
7269
c6ecf39a
DS		 7270 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7271 if (hw->mac.ops.disable_tx_laser &&
7272 ((hw->phy.multispeed_fiber) ||
9f911707 7273 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7274 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7275 hw->mac.ops.disable_tx_laser(hw);
7276
9a799d71 7277 init_timer(&adapter->watchdog_timer);
c061b18d 7278 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 7279 adapter->watchdog_timer.data = (unsigned long)adapter;
7280
7281 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 7282 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 7283
021230d4
AV		 7284 err = ixgbe_init_interrupt_scheme(adapter);
7285 if (err)
7286 goto err_sw_init;
9a799d71 7287
e8e26350 7288 switch (pdev->device) {
0b077fea
DS		 7289 case IXGBE_DEV_ID_82599_SFP:
7290 /* Only this subdevice supports WOL */
7291 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7292 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7293 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7294 break;
50d6c681
AD		 7295 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7296 /* All except this subdevice support WOL */
0b077fea
DS		 7297 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7298 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7299 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7300 break;
e8e26350 7301 case IXGBE_DEV_ID_82599_KX4:
495dce12 7302 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7303 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7304 break;
7305 default:
7306 adapter->wol = 0;
7307 break;
7308 }
e8e26350
PW		 7309 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7310
04f165ef
PW		 7311 /* pick up the PCI bus settings for reporting later */
7312 hw->mac.ops.get_bus_info(hw);
7313
9a799d71 7314 /* print bus type/speed/width info */
849c4542 7315 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 7316 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7317 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7318 "Unknown"),
7319 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7320 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7321 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7322 "Unknown"),
7323 netdev->dev_addr);
289700db
DS		 7324
7325 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7326 if (err)
9fe93afd 7327 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7328 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7329 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7330 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7331 part_str);
e8e26350 7332 else
289700db
DS		 7333 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7334 hw->mac.type, hw->phy.type, part_str);
9a799d71 7335
e8e26350 7336 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7337 e_dev_warn("PCI-Express bandwidth available for this card is "
7338 "not sufficient for optimal performance.\n");
7339 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7340 "is required.\n");
0c254d86
AK		 7341 }
7342
34b0368c
PWJ		 7343 /* save off EEPROM version number */
7344 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7345
9a799d71 7346 /* reset the hardware with the new settings */
794caeb2 7347 err = hw->mac.ops.start_hw(hw);
c44ade9e 7348
794caeb2
PWJ		 7349 if (err == IXGBE_ERR_EEPROM_VERSION) {
7350 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7351 e_dev_warn("This device is a pre-production adapter/LOM. "
7352 "Please be aware there may be issues associated "
7353 "with your hardware. If you are experiencing "
7354 "problems please contact your Intel or hardware "
7355 "representative who provided you with this "
7356 "hardware.\n");
794caeb2 7357 }
9a799d71
AK		 7358 strcpy(netdev->name, "eth%d");
7359 err = register_netdev(netdev);
7360 if (err)
7361 goto err_register;
7362
54386467
JB		 7363 /* carrier off reporting is important to ethtool even BEFORE open */
7364 netif_carrier_off(netdev);
7365
c4cf55e5
PWJ		 7366 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7367 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7368 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7369
119fc60a 7370 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7371 INIT_WORK(&adapter->check_overtemp_task,
7372 ixgbe_check_overtemp_task);
5dd2d332 7373#ifdef CONFIG_IXGBE_DCA
652f093f 7374 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7375 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7376 ixgbe_setup_dca(adapter);
7377 }
7378#endif
1cdd1ec8 7379 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7380 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7381 for (i = 0; i < adapter->num_vfs; i++)
7382 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7383 }
7384
0365e6e4
PW		 7385 /* add san mac addr to netdev */
7386 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7387
849c4542 7388 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7389 cards_found++;
7390 return 0;
7391
7392err_register:
5eba3699 7393 ixgbe_release_hw_control(adapter);
7a921c93 7394 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7395err_sw_init:
7396err_eeprom:
1cdd1ec8
GR		 7397 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7398 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7399 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7400 del_timer_sync(&adapter->sfp_timer);
7401 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7402 cancel_work_sync(&adapter->multispeed_fiber_task);
7403 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7404 iounmap(hw->hw_addr);
7405err_ioremap:
7406 free_netdev(netdev);
7407err_alloc_etherdev:
e8e9f696
JP		 7408 pci_release_selected_regions(pdev,
7409 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7410err_pci_reg:
7411err_dma:
7412 pci_disable_device(pdev);
7413 return err;
7414}
7415
7416/**
7417 * ixgbe_remove - Device Removal Routine
7418 * @pdev: PCI device information struct
7419 *
7420 * ixgbe_remove is called by the PCI subsystem to alert the driver
7421 * that it should release a PCI device. The could be caused by a
7422 * Hot-Plug event, or because the driver is going to be removed from
7423 * memory.
7424 **/
7425static void __devexit ixgbe_remove(struct pci_dev *pdev)
7426{
c60fbb00
AD		 7427 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7428 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7429
7430 set_bit(__IXGBE_DOWN, &adapter->state);
760141a5
TH		 7431
7432 /*
7433 * The timers may be rescheduled, so explicitly disable them
7434 * from being rescheduled.
c4900be0
DS		 7435 */
7436 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71 7437 del_timer_sync(&adapter->watchdog_timer);
c4900be0 7438 del_timer_sync(&adapter->sfp_timer);
760141a5 7439
c4900be0
DS		 7440 cancel_work_sync(&adapter->watchdog_task);
7441 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7442 cancel_work_sync(&adapter->multispeed_fiber_task);
7443 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7444 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7445 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7446 cancel_work_sync(&adapter->fdir_reinit_task);
760141a5
TH		 7447 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7448 cancel_work_sync(&adapter->check_overtemp_task);
9a799d71 7449
5dd2d332 7450#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7451 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7452 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7453 dca_remove_requester(&pdev->dev);
7454 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7455 }
7456
7457#endif
332d4a7d
YZ		 7458#ifdef IXGBE_FCOE
7459 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7460 ixgbe_cleanup_fcoe(adapter);
7461
7462#endif /* IXGBE_FCOE */
0365e6e4
PW		 7463
7464 /* remove the added san mac */
7465 ixgbe_del_sanmac_netdev(netdev);
7466
c4900be0
DS		 7467 if (netdev->reg_state == NETREG_REGISTERED)
7468 unregister_netdev(netdev);
9a799d71 7469
1cdd1ec8
GR		 7470 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7471 ixgbe_disable_sriov(adapter);
7472
7a921c93 7473 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7474
021230d4 7475 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7476
7477 iounmap(adapter->hw.hw_addr);
9ce77666 7478 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7479 IORESOURCE_MEM));
9a799d71 7480
849c4542 7481 e_dev_info("complete\n");
021230d4 7482
9a799d71
AK		 7483 free_netdev(netdev);
7484
19d5afd4 7485 pci_disable_pcie_error_reporting(pdev);
6fabd715 7486
9a799d71
AK		 7487 pci_disable_device(pdev);
7488}
7489
7490/**
7491 * ixgbe_io_error_detected - called when PCI error is detected
7492 * @pdev: Pointer to PCI device
7493 * @state: The current pci connection state
7494 *
7495 * This function is called after a PCI bus error affecting
7496 * this device has been detected.
7497 */
7498static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7499 pci_channel_state_t state)
9a799d71 7500{
c60fbb00
AD		 7501 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7502 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7503
7504 netif_device_detach(netdev);
7505
3044b8d1
BL		 7506 if (state == pci_channel_io_perm_failure)
7507 return PCI_ERS_RESULT_DISCONNECT;
7508
9a799d71
AK		 7509 if (netif_running(netdev))
7510 ixgbe_down(adapter);
7511 pci_disable_device(pdev);
7512
b4617240 7513 /* Request a slot reset. */
9a799d71
AK		 7514 return PCI_ERS_RESULT_NEED_RESET;
7515}
7516
7517/**
7518 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7519 * @pdev: Pointer to PCI device
7520 *
7521 * Restart the card from scratch, as if from a cold-boot.
7522 */
7523static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7524{
c60fbb00 7525 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7526 pci_ers_result_t result;
7527 int err;
9a799d71 7528
9ce77666 7529 if (pci_enable_device_mem(pdev)) {
396e799c 7530 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7531 result = PCI_ERS_RESULT_DISCONNECT;
7532 } else {
7533 pci_set_master(pdev);
7534 pci_restore_state(pdev);
c0e1f68b 7535 pci_save_state(pdev);
9a799d71 7536
dd4d8ca6 7537 pci_wake_from_d3(pdev, false);
9a799d71 7538
6fabd715 7539 ixgbe_reset(adapter);
88512539 7540 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7541 result = PCI_ERS_RESULT_RECOVERED;
7542 }
7543
7544 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7545 if (err) {
849c4542
ET		 7546 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7547 "failed 0x%0x\n", err);
6fabd715
PWJ		 7548 /* non-fatal, continue */
7549 }
9a799d71 7550
6fabd715 7551 return result;
9a799d71
AK		 7552}
7553
7554/**
7555 * ixgbe_io_resume - called when traffic can start flowing again.
7556 * @pdev: Pointer to PCI device
7557 *
7558 * This callback is called when the error recovery driver tells us that
7559 * its OK to resume normal operation.
7560 */
7561static void ixgbe_io_resume(struct pci_dev *pdev)
7562{
c60fbb00
AD		 7563 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7564 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7565
7566 if (netif_running(netdev)) {
7567 if (ixgbe_up(adapter)) {
396e799c 7568 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7569 return;
7570 }
7571 }
7572
7573 netif_device_attach(netdev);
9a799d71
AK		 7574}
7575
7576static struct pci_error_handlers ixgbe_err_handler = {
7577 .error_detected = ixgbe_io_error_detected,
7578 .slot_reset = ixgbe_io_slot_reset,
7579 .resume = ixgbe_io_resume,
7580};
7581
7582static struct pci_driver ixgbe_driver = {
7583 .name = ixgbe_driver_name,
7584 .id_table = ixgbe_pci_tbl,
7585 .probe = ixgbe_probe,
7586 .remove = __devexit_p(ixgbe_remove),
7587#ifdef CONFIG_PM
7588 .suspend = ixgbe_suspend,
7589 .resume = ixgbe_resume,
7590#endif
7591 .shutdown = ixgbe_shutdown,
7592 .err_handler = &ixgbe_err_handler
7593};
7594
7595/**
7596 * ixgbe_init_module - Driver Registration Routine
7597 *
7598 * ixgbe_init_module is the first routine called when the driver is
7599 * loaded. All it does is register with the PCI subsystem.
7600 **/
7601static int __init ixgbe_init_module(void)
7602{
7603 int ret;
c7689578 7604 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7605 pr_info("%s\n", ixgbe_copyright);
9a799d71 7606
5dd2d332 7607#ifdef CONFIG_IXGBE_DCA
bd0362dd 7608 dca_register_notify(&dca_notifier);
bd0362dd 7609#endif
5dd2d332 7610
9a799d71
AK		 7611 ret = pci_register_driver(&ixgbe_driver);
7612 return ret;
7613}
b4617240 7614
9a799d71
AK		 7615module_init(ixgbe_init_module);
7616
7617/**
7618 * ixgbe_exit_module - Driver Exit Cleanup Routine
7619 *
7620 * ixgbe_exit_module is called just before the driver is removed
7621 * from memory.
7622 **/
7623static void __exit ixgbe_exit_module(void)
7624{
5dd2d332 7625#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7626 dca_unregister_notify(&dca_notifier);
7627#endif
9a799d71 7628 pci_unregister_driver(&ixgbe_driver);
1a51502b 7629 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7630}
bd0362dd 7631
5dd2d332 7632#ifdef CONFIG_IXGBE_DCA
bd0362dd 7633static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7634 void *p)
bd0362dd
JC		 7635{
7636 int ret_val;
7637
7638 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7639 __ixgbe_notify_dca);
bd0362dd
JC		 7640
7641 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7642}
b453368d 7643
5dd2d332 7644#endif /* CONFIG_IXGBE_DCA */
849c4542 7645
b453368d 7646/**
849c4542 7647 * ixgbe_get_hw_dev return device
b453368d
AD		 7648 * used by hardware layer to print debugging information
7649 **/
849c4542 7650struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7651{
7652 struct ixgbe_adapter *adapter = hw->back;
849c4542 7653 return adapter->netdev;
b453368d 7654}
bd0362dd 7655
9a799d71
AK		 7656module_exit(ixgbe_exit_module);
7657
7658/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)