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ixgbe: add rxhash support
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 54#define MAJ 3
c89c7112
DS		 55#define MIN 3
56#define BUILD 8
75e3d3c6
JK		 57#define KFIX 2
58#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
59 __stringify(BUILD) "-k" __stringify(KFIX)
9c8eb720 60const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 61static const char ixgbe_copyright[] =
62 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 63
64static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 65 [board_82598] = &ixgbe_82598_info,
e8e26350 66 [board_82599] = &ixgbe_82599_info,
fe15e8e1 67 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 68};
69
70/* ixgbe_pci_tbl - PCI Device ID Table
71 *
72 * Wildcard entries (PCI_ANY_ID) should come last
73 * Last entry must be all 0s
74 *
75 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
76 * Class, Class Mask, private data (not used) }
77 */
a3aa1884 78static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
80 board_82598 },
9a799d71 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 84 board_82598 },
0befdb3e
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
86 board_82598 },
3845bec0
PWJ		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
88 board_82598 },
9a799d71 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 90 board_82598 },
8d792cd9
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
96 board_82598 },
b95f5fcb
JB		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
98 board_82598 },
c4900be0
DS		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
100 board_82598 },
2f21bdd3
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
102 board_82598 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
104 board_82599 },
1fcf03e6
PWJ		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
106 board_82599 },
74757d49
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
108 board_82599 },
e8e26350
PW		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
110 board_82599 },
38ad1c8e
DS		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
112 board_82599 },
dbfec662
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
114 board_82599 },
8911184f
PWJ		 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
116 board_82599 },
dbffcb21
DS		 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
118 board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
120 board_82599 },
119fc60a
MC		 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
122 board_82599 },
312eb931
DS		 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
124 board_82599 },
b93a2226 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 126 board_X540 },
4c40ef02
ET		 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
128 board_82599 },
9a799d71
AK		 129
130 /* required last entry */
131 {0, }
132};
133MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
134
5dd2d332 135#ifdef CONFIG_IXGBE_DCA
bd0362dd 136static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 137 void *p);
bd0362dd
JC		 138static struct notifier_block dca_notifier = {
139 .notifier_call = ixgbe_notify_dca,
140 .next = NULL,
141 .priority = 0
142};
143#endif
144
1cdd1ec8
GR		 145#ifdef CONFIG_PCI_IOV
146static unsigned int max_vfs;
147module_param(max_vfs, uint, 0);
e8e9f696
JP		 148MODULE_PARM_DESC(max_vfs,
149 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 150#endif /* CONFIG_PCI_IOV */
151
9a799d71
AK		 152MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
153MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
154MODULE_LICENSE("GPL");
155MODULE_VERSION(DRV_VERSION);
156
157#define DEFAULT_DEBUG_LEVEL_SHIFT 3
158
1cdd1ec8
GR		 159static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
160{
161 struct ixgbe_hw *hw = &adapter->hw;
162 u32 gcr;
163 u32 gpie;
164 u32 vmdctl;
165
166#ifdef CONFIG_PCI_IOV
167 /* disable iov and allow time for transactions to clear */
168 pci_disable_sriov(adapter->pdev);
169#endif
170
171 /* turn off device IOV mode */
172 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
173 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
174 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
175 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
176 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
177 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
178
179 /* set default pool back to 0 */
180 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
181 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
182 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
183
184 /* take a breather then clean up driver data */
185 msleep(100);
e8e9f696
JP		 186
187 kfree(adapter->vfinfo);
1cdd1ec8
GR		 188 adapter->vfinfo = NULL;
189
190 adapter->num_vfs = 0;
191 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
192}
193
dcd79aeb
TI		 194struct ixgbe_reg_info {
195 u32 ofs;
196 char *name;
197};
198
199static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
200
201 /* General Registers */
202 {IXGBE_CTRL, "CTRL"},
203 {IXGBE_STATUS, "STATUS"},
204 {IXGBE_CTRL_EXT, "CTRL_EXT"},
205
206 /* Interrupt Registers */
207 {IXGBE_EICR, "EICR"},
208
209 /* RX Registers */
210 {IXGBE_SRRCTL(0), "SRRCTL"},
211 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
212 {IXGBE_RDLEN(0), "RDLEN"},
213 {IXGBE_RDH(0), "RDH"},
214 {IXGBE_RDT(0), "RDT"},
215 {IXGBE_RXDCTL(0), "RXDCTL"},
216 {IXGBE_RDBAL(0), "RDBAL"},
217 {IXGBE_RDBAH(0), "RDBAH"},
218
219 /* TX Registers */
220 {IXGBE_TDBAL(0), "TDBAL"},
221 {IXGBE_TDBAH(0), "TDBAH"},
222 {IXGBE_TDLEN(0), "TDLEN"},
223 {IXGBE_TDH(0), "TDH"},
224 {IXGBE_TDT(0), "TDT"},
225 {IXGBE_TXDCTL(0), "TXDCTL"},
226
227 /* List Terminator */
228 {}
229};
230
231
232/*
233 * ixgbe_regdump - register printout routine
234 */
235static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
236{
237 int i = 0, j = 0;
238 char rname[16];
239 u32 regs[64];
240
241 switch (reginfo->ofs) {
242 case IXGBE_SRRCTL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
245 break;
246 case IXGBE_DCA_RXCTRL(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
249 break;
250 case IXGBE_RDLEN(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
253 break;
254 case IXGBE_RDH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
257 break;
258 case IXGBE_RDT(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
261 break;
262 case IXGBE_RXDCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
265 break;
266 case IXGBE_RDBAL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
269 break;
270 case IXGBE_RDBAH(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
273 break;
274 case IXGBE_TDBAL(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
277 break;
278 case IXGBE_TDBAH(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
281 break;
282 case IXGBE_TDLEN(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
285 break;
286 case IXGBE_TDH(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
289 break;
290 case IXGBE_TDT(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
293 break;
294 case IXGBE_TXDCTL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
297 break;
298 default:
c7689578 299 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 300 IXGBE_READ_REG(hw, reginfo->ofs));
301 return;
302 }
303
304 for (i = 0; i < 8; i++) {
305 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 306 pr_err("%-15s", rname);
dcd79aeb 307 for (j = 0; j < 8; j++)
c7689578
JP		 308 pr_cont(" %08x", regs[i*8+j]);
309 pr_cont("\n");
dcd79aeb
TI		 310 }
311
312}
313
314/*
315 * ixgbe_dump - Print registers, tx-rings and rx-rings
316 */
317static void ixgbe_dump(struct ixgbe_adapter *adapter)
318{
319 struct net_device *netdev = adapter->netdev;
320 struct ixgbe_hw *hw = &adapter->hw;
321 struct ixgbe_reg_info *reginfo;
322 int n = 0;
323 struct ixgbe_ring *tx_ring;
324 struct ixgbe_tx_buffer *tx_buffer_info;
325 union ixgbe_adv_tx_desc *tx_desc;
326 struct my_u0 { u64 a; u64 b; } *u0;
327 struct ixgbe_ring *rx_ring;
328 union ixgbe_adv_rx_desc *rx_desc;
329 struct ixgbe_rx_buffer *rx_buffer_info;
330 u32 staterr;
331 int i = 0;
332
333 if (!netif_msg_hw(adapter))
334 return;
335
336 /* Print netdevice Info */
337 if (netdev) {
338 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 339 pr_info("Device Name state "
dcd79aeb 340 "trans_start last_rx\n");
c7689578
JP		 341 pr_info("%-15s %016lX %016lX %016lX\n",
342 netdev->name,
343 netdev->state,
344 netdev->trans_start,
345 netdev->last_rx);
dcd79aeb
TI		 346 }
347
348 /* Print Registers */
349 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 350 pr_info(" Register Name Value\n");
dcd79aeb
TI		 351 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
352 reginfo->name; reginfo++) {
353 ixgbe_regdump(hw, reginfo);
354 }
355
356 /* Print TX Ring Summary */
357 if (!netdev || !netif_running(netdev))
358 goto exit;
359
360 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 361 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 362 for (n = 0; n < adapter->num_tx_queues; n++) {
363 tx_ring = adapter->tx_ring[n];
364 tx_buffer_info =
365 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 366 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 367 n, tx_ring->next_to_use, tx_ring->next_to_clean,
368 (u64)tx_buffer_info->dma,
369 tx_buffer_info->length,
370 tx_buffer_info->next_to_watch,
371 (u64)tx_buffer_info->time_stamp);
372 }
373
374 /* Print TX Rings */
375 if (!netif_msg_tx_done(adapter))
376 goto rx_ring_summary;
377
378 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
379
380 /* Transmit Descriptor Formats
381 *
382 * Advanced Transmit Descriptor
383 * +--------------------------------------------------------------+
384 * 0 | Buffer Address [63:0] |
385 * +--------------------------------------------------------------+
386 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
387 * +--------------------------------------------------------------+
388 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
389 */
390
391 for (n = 0; n < adapter->num_tx_queues; n++) {
392 tx_ring = adapter->tx_ring[n];
c7689578
JP		 393 pr_info("------------------------------------\n");
394 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
395 pr_info("------------------------------------\n");
396 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 397 "[PlPOIdStDDt Ln] [bi->dma ] "
398 "leng ntw timestamp bi->skb\n");
399
400 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 401 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 402 tx_buffer_info = &tx_ring->tx_buffer_info[i];
403 u0 = (struct my_u0 *)tx_desc;
c7689578 404 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 405 " %04X %3X %016llX %p", i,
406 le64_to_cpu(u0->a),
407 le64_to_cpu(u0->b),
408 (u64)tx_buffer_info->dma,
409 tx_buffer_info->length,
410 tx_buffer_info->next_to_watch,
411 (u64)tx_buffer_info->time_stamp,
412 tx_buffer_info->skb);
413 if (i == tx_ring->next_to_use &&
414 i == tx_ring->next_to_clean)
c7689578 415 pr_cont(" NTC/U\n");
dcd79aeb 416 else if (i == tx_ring->next_to_use)
c7689578 417 pr_cont(" NTU\n");
dcd79aeb 418 else if (i == tx_ring->next_to_clean)
c7689578 419 pr_cont(" NTC\n");
dcd79aeb 420 else
c7689578 421 pr_cont("\n");
dcd79aeb
TI		 422
423 if (netif_msg_pktdata(adapter) &&
424 tx_buffer_info->dma != 0)
425 print_hex_dump(KERN_INFO, "",
426 DUMP_PREFIX_ADDRESS, 16, 1,
427 phys_to_virt(tx_buffer_info->dma),
428 tx_buffer_info->length, true);
429 }
430 }
431
432 /* Print RX Rings Summary */
433rx_ring_summary:
434 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 435 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 436 for (n = 0; n < adapter->num_rx_queues; n++) {
437 rx_ring = adapter->rx_ring[n];
c7689578
JP		 438 pr_info("%5d %5X %5X\n",
439 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 440 }
441
442 /* Print RX Rings */
443 if (!netif_msg_rx_status(adapter))
444 goto exit;
445
446 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
447
448 /* Advanced Receive Descriptor (Read) Format
449 * 63 1 0
450 * +-----------------------------------------------------+
451 * 0 | Packet Buffer Address [63:1] |A0/NSE|
452 * +----------------------------------------------+------+
453 * 8 | Header Buffer Address [63:1] | DD |
454 * +-----------------------------------------------------+
455 *
456 *
457 * Advanced Receive Descriptor (Write-Back) Format
458 *
459 * 63 48 47 32 31 30 21 20 16 15 4 3 0
460 * +------------------------------------------------------+
461 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
462 * | Checksum Ident | | | | Type | Type |
463 * +------------------------------------------------------+
464 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
465 * +------------------------------------------------------+
466 * 63 48 47 32 31 20 19 0
467 */
468 for (n = 0; n < adapter->num_rx_queues; n++) {
469 rx_ring = adapter->rx_ring[n];
c7689578
JP		 470 pr_info("------------------------------------\n");
471 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
472 pr_info("------------------------------------\n");
473 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 474 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
475 "<-- Adv Rx Read format\n");
c7689578 476 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 477 "[vl er S cks ln] ---------------- [bi->skb] "
478 "<-- Adv Rx Write-Back format\n");
479
480 for (i = 0; i < rx_ring->count; i++) {
481 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 482 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 483 u0 = (struct my_u0 *)rx_desc;
484 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
485 if (staterr & IXGBE_RXD_STAT_DD) {
486 /* Descriptor Done */
c7689578 487 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 488 "%016llX ---------------- %p", i,
489 le64_to_cpu(u0->a),
490 le64_to_cpu(u0->b),
491 rx_buffer_info->skb);
492 } else {
c7689578 493 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 494 "%016llX %016llX %p", i,
495 le64_to_cpu(u0->a),
496 le64_to_cpu(u0->b),
497 (u64)rx_buffer_info->dma,
498 rx_buffer_info->skb);
499
500 if (netif_msg_pktdata(adapter)) {
501 print_hex_dump(KERN_INFO, "",
502 DUMP_PREFIX_ADDRESS, 16, 1,
503 phys_to_virt(rx_buffer_info->dma),
504 rx_ring->rx_buf_len, true);
505
506 if (rx_ring->rx_buf_len
507 < IXGBE_RXBUFFER_2048)
508 print_hex_dump(KERN_INFO, "",
509 DUMP_PREFIX_ADDRESS, 16, 1,
510 phys_to_virt(
511 rx_buffer_info->page_dma +
512 rx_buffer_info->page_offset
513 ),
514 PAGE_SIZE/2, true);
515 }
516 }
517
518 if (i == rx_ring->next_to_use)
c7689578 519 pr_cont(" NTU\n");
dcd79aeb 520 else if (i == rx_ring->next_to_clean)
c7689578 521 pr_cont(" NTC\n");
dcd79aeb 522 else
c7689578 523 pr_cont("\n");
dcd79aeb
TI		 524
525 }
526 }
527
528exit:
529 return;
530}
531
5eba3699
AV		 532static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
533{
534 u32 ctrl_ext;
535
536 /* Let firmware take over control of h/w */
537 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
538 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 539 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 540}
541
542static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
543{
544 u32 ctrl_ext;
545
546 /* Let firmware know the driver has taken over */
547 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 549 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 550}
9a799d71 551
e8e26350
PW		 552/*
553 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
554 * @adapter: pointer to adapter struct
555 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
556 * @queue: queue to map the corresponding interrupt to
557 * @msix_vector: the vector to map to the corresponding queue
558 *
559 */
560static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 561 u8 queue, u8 msix_vector)
9a799d71
AK		 562{
563 u32 ivar, index;
e8e26350
PW		 564 struct ixgbe_hw *hw = &adapter->hw;
565 switch (hw->mac.type) {
566 case ixgbe_mac_82598EB:
567 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
568 if (direction == -1)
569 direction = 0;
570 index = (((direction * 64) + queue) >> 2) & 0x1F;
571 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
572 ivar &= ~(0xFF << (8 * (queue & 0x3)));
573 ivar |= (msix_vector << (8 * (queue & 0x3)));
574 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
575 break;
576 case ixgbe_mac_82599EB:
b93a2226 577 case ixgbe_mac_X540:
e8e26350
PW		 578 if (direction == -1) {
579 /* other causes */
580 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
581 index = ((queue & 1) * 8);
582 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
583 ivar &= ~(0xFF << index);
584 ivar |= (msix_vector << index);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
586 break;
587 } else {
588 /* tx or rx causes */
589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
590 index = ((16 * (queue & 1)) + (8 * direction));
591 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
592 ivar &= ~(0xFF << index);
593 ivar |= (msix_vector << index);
594 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
595 break;
596 }
597 default:
598 break;
599 }
9a799d71
AK		 600}
601
fe49f04a 602static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 603 u64 qmask)
fe49f04a
AD		 604{
605 u32 mask;
606
bd508178
AD		 607 switch (adapter->hw.mac.type) {
608 case ixgbe_mac_82598EB:
fe49f04a
AD		 609 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 611 break;
612 case ixgbe_mac_82599EB:
b93a2226 613 case ixgbe_mac_X540:
fe49f04a
AD		 614 mask = (qmask & 0xFFFFFFFF);
615 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
616 mask = (qmask >> 32);
617 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 618 break;
619 default:
620 break;
fe49f04a
AD		 621 }
622}
623
b6ec895e
AD		 624void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
625 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 626{
e5a43549
AD		 627 if (tx_buffer_info->dma) {
628 if (tx_buffer_info->mapped_as_page)
b6ec895e 629 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 630 tx_buffer_info->dma,
631 tx_buffer_info->length,
1b507730 632 DMA_TO_DEVICE);
e5a43549 633 else
b6ec895e 634 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 635 tx_buffer_info->dma,
636 tx_buffer_info->length,
1b507730 637 DMA_TO_DEVICE);
e5a43549
AD		 638 tx_buffer_info->dma = 0;
639 }
9a799d71
AK		 640 if (tx_buffer_info->skb) {
641 dev_kfree_skb_any(tx_buffer_info->skb);
642 tx_buffer_info->skb = NULL;
643 }
44df32c5 644 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 645 /* tx_buffer_info must be completely set up in the transmit path */
646}
647
26f23d82 648/**
c84d324c
JF		 649 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
650 * @adapter: driver private struct
651 * @index: reg idx of queue to query (0-127)
26f23d82 652 *
25985edc 653 * Helper function to determine the traffic index for a particular
c84d324c 654 * register index.
26f23d82 655 *
c84d324c 656 * Returns : a tc index for use in range 0-7, or 0-3
26f23d82 657 */
3b2ee943 658static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
26f23d82 659{
c84d324c 660 int tc = -1;
e5b64635 661 int dcb_i = netdev_get_num_tc(adapter->netdev);
26f23d82 662
c84d324c
JF		 663 /* if DCB is not enabled the queues have no TC */
664 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
665 return tc;
26f23d82 666
c84d324c
JF		 667 /* check valid range */
668 if (reg_idx >= adapter->hw.mac.max_tx_queues)
669 return tc;
670
671 switch (adapter->hw.mac.type) {
672 case ixgbe_mac_82598EB:
673 tc = reg_idx >> 2;
674 break;
675 default:
676 if (dcb_i != 4 && dcb_i != 8)
6837e895 677 break;
c84d324c
JF		 678
679 /* if VMDq is enabled the lowest order bits determine TC */
680 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
681 IXGBE_FLAG_VMDQ_ENABLED)) {
682 tc = reg_idx & (dcb_i - 1);
683 break;
684 }
685
686 /*
687 * Convert the reg_idx into the correct TC. This bitmask
688 * targets the last full 32 ring traffic class and assigns
689 * it a value of 1. From there the rest of the rings are
690 * based on shifting the mask further up to include the
691 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
692 * will only ever be 8 or 4 and that reg_idx will never
693 * be greater then 128. The code without the power of 2
694 * optimizations would be:
695 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
696 */
697 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
698 tc >>= 9 - (reg_idx >> 5);
699 }
700
701 return tc;
702}
703
704static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
705{
706 struct ixgbe_hw *hw = &adapter->hw;
707 struct ixgbe_hw_stats *hwstats = &adapter->stats;
708 u32 data = 0;
709 u32 xoff[8] = {0};
710 int i;
711
712 if ((hw->fc.current_mode == ixgbe_fc_full) ||
713 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
714 switch (hw->mac.type) {
715 case ixgbe_mac_82598EB:
716 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 717 break;
718 default:
c84d324c
JF		 719 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
720 }
721 hwstats->lxoffrxc += data;
722
723 /* refill credits (no tx hang) if we received xoff */
724 if (!data)
725 return;
726
727 for (i = 0; i < adapter->num_tx_queues; i++)
728 clear_bit(__IXGBE_HANG_CHECK_ARMED,
729 &adapter->tx_ring[i]->state);
730 return;
731 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
732 return;
733
734 /* update stats for each tc, only valid with PFC enabled */
735 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
736 switch (hw->mac.type) {
737 case ixgbe_mac_82598EB:
738 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 739 break;
c84d324c
JF		 740 default:
741 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 742 }
c84d324c
JF		 743 hwstats->pxoffrxc[i] += xoff[i];
744 }
745
746 /* disarm tx queues that have received xoff frames */
747 for (i = 0; i < adapter->num_tx_queues; i++) {
748 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
749 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
750
751 if (xoff[tc])
752 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 753 }
26f23d82
YZ		 754}
755
c84d324c 756static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 757{
c84d324c
JF		 758 return ring->tx_stats.completed;
759}
760
761static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
762{
763 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 764 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 765
c84d324c
JF		 766 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
767 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
768
769 if (head != tail)
770 return (head < tail) ?
771 tail - head : (tail + ring->count - head);
772
773 return 0;
774}
775
776static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
777{
778 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
779 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
780 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
781 bool ret = false;
782
7d637bcc 783 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 784
785 /*
786 * Check for a hung queue, but be thorough. This verifies
787 * that a transmit has been completed since the previous
788 * check AND there is at least one packet pending. The
789 * ARMED bit is set to indicate a potential hang. The
790 * bit is cleared if a pause frame is received to remove
791 * false hang detection due to PFC or 802.3x frames. By
792 * requiring this to fail twice we avoid races with
793 * pfc clearing the ARMED bit and conditions where we
794 * run the check_tx_hang logic with a transmit completion
795 * pending but without time to complete it yet.
796 */
797 if ((tx_done_old == tx_done) && tx_pending) {
798 /* make sure it is true for two checks in a row */
799 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
800 &tx_ring->state);
801 } else {
802 /* update completed stats and continue */
803 tx_ring->tx_stats.tx_done_old = tx_done;
804 /* reset the countdown */
805 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 806 }
807
c84d324c 808 return ret;
9a799d71
AK		 809}
810
b4617240
PW		 811#define IXGBE_MAX_TXD_PWR 14
812#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 813
814/* Tx Descriptors needed, worst case */
815#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
816 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
817#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 818 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 819
e01c31a5
JB		 820static void ixgbe_tx_timeout(struct net_device *netdev);
821
9a799d71
AK		 822/**
823 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 824 * @q_vector: structure containing interrupt and ring information
e01c31a5 825 * @tx_ring: tx ring to clean
9a799d71 826 **/
fe49f04a 827static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 828 struct ixgbe_ring *tx_ring)
9a799d71 829{
fe49f04a 830 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 831 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
832 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 833 unsigned int total_bytes = 0, total_packets = 0;
b953799e 834 u16 i, eop, count = 0;
9a799d71
AK		 835
836 i = tx_ring->next_to_clean;
12207e49 837 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 838 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 839
840 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 841 (count < tx_ring->work_limit)) {
12207e49 842 bool cleaned = false;
2d0bb1c1 843 rmb(); /* read buffer_info after eop_desc */
12207e49 844 for ( ; !cleaned; count++) {
31f05a2d 845 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 846 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 847
848 tx_desc->wb.status = 0;
12207e49 849 cleaned = (i == eop);
9a799d71 850
8ad494b0
AD		 851 i++;
852 if (i == tx_ring->count)
853 i = 0;
e01c31a5 854
8ad494b0
AD		 855 if (cleaned && tx_buffer_info->skb) {
856 total_bytes += tx_buffer_info->bytecount;
857 total_packets += tx_buffer_info->gso_segs;
e092be60 858 }
e01c31a5 859
b6ec895e 860 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 861 tx_buffer_info);
e01c31a5 862 }
12207e49 863
c84d324c 864 tx_ring->tx_stats.completed++;
12207e49 865 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 866 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 867 }
868
9a799d71 869 tx_ring->next_to_clean = i;
b953799e
AD		 870 tx_ring->total_bytes += total_bytes;
871 tx_ring->total_packets += total_packets;
872 u64_stats_update_begin(&tx_ring->syncp);
873 tx_ring->stats.packets += total_packets;
874 tx_ring->stats.bytes += total_bytes;
875 u64_stats_update_end(&tx_ring->syncp);
876
c84d324c
JF		 877 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
878 /* schedule immediate reset if we believe we hung */
879 struct ixgbe_hw *hw = &adapter->hw;
880 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
881 e_err(drv, "Detected Tx Unit Hang\n"
882 " Tx Queue <%d>\n"
883 " TDH, TDT <%x>, <%x>\n"
884 " next_to_use <%x>\n"
885 " next_to_clean <%x>\n"
886 "tx_buffer_info[next_to_clean]\n"
887 " time_stamp <%lx>\n"
888 " jiffies <%lx>\n",
889 tx_ring->queue_index,
890 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
891 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
892 tx_ring->next_to_use, eop,
893 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
894
895 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
896
897 e_info(probe,
898 "tx hang %d detected on queue %d, resetting adapter\n",
899 adapter->tx_timeout_count + 1, tx_ring->queue_index);
900
b953799e 901 /* schedule immediate reset if we believe we hung */
b953799e
AD		 902 ixgbe_tx_timeout(adapter->netdev);
903
904 /* the adapter is about to reset, no point in enabling stuff */
905 return true;
906 }
9a799d71 907
e092be60 908#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 909 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 910 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 911 /* Make sure that anybody stopping the queue after this
912 * sees the new next_to_clean.
913 */
914 smp_mb();
fc77dc3c 915 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 916 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 917 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 918 ++tx_ring->tx_stats.restart_queue;
30eba97a 919 }
e092be60 920 }
9a799d71 921
807540ba 922 return count < tx_ring->work_limit;
9a799d71
AK		 923}
924
5dd2d332 925#ifdef CONFIG_IXGBE_DCA
bd0362dd 926static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 927 struct ixgbe_ring *rx_ring,
928 int cpu)
bd0362dd 929{
33cf09c9 930 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 931 u32 rxctrl;
33cf09c9
AD		 932 u8 reg_idx = rx_ring->reg_idx;
933
934 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
935 switch (hw->mac.type) {
936 case ixgbe_mac_82598EB:
937 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
938 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
939 break;
940 case ixgbe_mac_82599EB:
b93a2226 941 case ixgbe_mac_X540:
33cf09c9
AD		 942 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
943 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
944 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
945 break;
946 default:
947 break;
bd0362dd 948 }
33cf09c9
AD		 949 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
950 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
951 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 952 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 953}
954
955static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 956 struct ixgbe_ring *tx_ring,
957 int cpu)
bd0362dd 958{
33cf09c9 959 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 960 u32 txctrl;
33cf09c9
AD		 961 u8 reg_idx = tx_ring->reg_idx;
962
963 switch (hw->mac.type) {
964 case ixgbe_mac_82598EB:
965 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
966 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
967 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
968 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 969 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
970 break;
971 case ixgbe_mac_82599EB:
b93a2226 972 case ixgbe_mac_X540:
33cf09c9
AD		 973 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
974 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
975 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
976 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
977 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 978 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
979 break;
980 default:
981 break;
982 }
983}
984
985static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
986{
987 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 988 int cpu = get_cpu();
33cf09c9
AD		 989 long r_idx;
990 int i;
bd0362dd 991
33cf09c9
AD		 992 if (q_vector->cpu == cpu)
993 goto out_no_update;
994
995 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
996 for (i = 0; i < q_vector->txr_count; i++) {
997 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
998 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
999 r_idx + 1);
bd0362dd 1000 }
33cf09c9
AD		 1001
1002 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1003 for (i = 0; i < q_vector->rxr_count; i++) {
1004 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1005 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1006 r_idx + 1);
1007 }
1008
1009 q_vector->cpu = cpu;
1010out_no_update:
bd0362dd
JC		 1011 put_cpu();
1012}
1013
1014static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1015{
33cf09c9 1016 int num_q_vectors;
bd0362dd
JC		 1017 int i;
1018
1019 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1020 return;
1021
e35ec126
AD		 1022 /* always use CB2 mode, difference is masked in the CB driver */
1023 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1024
33cf09c9
AD		 1025 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1026 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1027 else
1028 num_q_vectors = 1;
1029
1030 for (i = 0; i < num_q_vectors; i++) {
1031 adapter->q_vector[i]->cpu = -1;
1032 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1033 }
1034}
1035
1036static int __ixgbe_notify_dca(struct device *dev, void *data)
1037{
c60fbb00 1038 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1039 unsigned long event = *(unsigned long *)data;
1040
33cf09c9
AD		 1041 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1042 return 0;
1043
bd0362dd
JC		 1044 switch (event) {
1045 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1046 /* if we're already enabled, don't do it again */
1047 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1048 break;
652f093f 1049 if (dca_add_requester(dev) == 0) {
96b0e0f6 1050 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1051 ixgbe_setup_dca(adapter);
1052 break;
1053 }
1054 /* Fall Through since DCA is disabled. */
1055 case DCA_PROVIDER_REMOVE:
1056 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1057 dca_remove_requester(dev);
1058 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1059 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1060 }
1061 break;
1062 }
1063
652f093f 1064 return 0;
bd0362dd 1065}
5dd2d332 1066#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 1067
1068static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1069 struct sk_buff *skb)
1070{
1071 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1072}
1073
9a799d71
AK		 1074/**
1075 * ixgbe_receive_skb - Send a completed packet up the stack
1076 * @adapter: board private structure
1077 * @skb: packet to send up
177db6ff
MC		 1078 * @status: hardware indication of status of receive
1079 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1080 * @rx_desc: rx descriptor
9a799d71 1081 **/
78b6f4ce 1082static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1083 struct sk_buff *skb, u8 status,
1084 struct ixgbe_ring *ring,
1085 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1086{
78b6f4ce
HX		 1087 struct ixgbe_adapter *adapter = q_vector->adapter;
1088 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1089 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1090 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1091
f62bbb5e
JG		 1092 if (is_vlan && (tag & VLAN_VID_MASK))
1093 __vlan_hwaccel_put_tag(skb, tag);
1094
1095 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1096 napi_gro_receive(napi, skb);
1097 else
1098 netif_rx(skb);
9a799d71
AK		 1099}
1100
e59bd25d
AV		 1101/**
1102 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1103 * @adapter: address of board private structure
1104 * @status_err: hardware indication of status of receive
1105 * @skb: skb currently being received and modified
1106 **/
9a799d71 1107static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1108 union ixgbe_adv_rx_desc *rx_desc,
1109 struct sk_buff *skb)
9a799d71 1110{
8bae1b2b
DS		 1111 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1112
bc8acf2c 1113 skb_checksum_none_assert(skb);
9a799d71 1114
712744be
JB		 1115 /* Rx csum disabled */
1116 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1117 return;
e59bd25d
AV		 1118
1119 /* if IP and error */
1120 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1121 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1122 adapter->hw_csum_rx_error++;
1123 return;
1124 }
e59bd25d
AV		 1125
1126 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1127 return;
1128
1129 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1130 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1131
1132 /*
1133 * 82599 errata, UDP frames with a 0 checksum can be marked as
1134 * checksum errors.
1135 */
1136 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1137 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1138 return;
1139
e59bd25d
AV		 1140 adapter->hw_csum_rx_error++;
1141 return;
1142 }
1143
9a799d71 1144 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1145 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1146}
1147
84ea2591 1148static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1149{
1150 /*
1151 * Force memory writes to complete before letting h/w
1152 * know there are new descriptors to fetch. (Only
1153 * applicable for weak-ordered memory model archs,
1154 * such as IA-64).
1155 */
1156 wmb();
84ea2591 1157 writel(val, rx_ring->tail);
e8e26350
PW		 1158}
1159
9a799d71
AK		 1160/**
1161 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1162 * @rx_ring: ring to place buffers on
1163 * @cleaned_count: number of buffers to replace
9a799d71 1164 **/
fc77dc3c 1165void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1166{
9a799d71 1167 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1168 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1169 struct sk_buff *skb;
1170 u16 i = rx_ring->next_to_use;
9a799d71 1171
fc77dc3c
AD		 1172 /* do nothing if no valid netdev defined */
1173 if (!rx_ring->netdev)
1174 return;
1175
9a799d71 1176 while (cleaned_count--) {
31f05a2d 1177 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1178 bi = &rx_ring->rx_buffer_info[i];
1179 skb = bi->skb;
9a799d71 1180
d5f398ed 1181 if (!skb) {
fc77dc3c 1182 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1183 rx_ring->rx_buf_len);
9a799d71 1184 if (!skb) {
5b7da515 1185 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1186 goto no_buffers;
1187 }
d716a7d8
AD		 1188 /* initialize queue mapping */
1189 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1190 bi->skb = skb;
d716a7d8 1191 }
9a799d71 1192
d716a7d8 1193 if (!bi->dma) {
b6ec895e 1194 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1195 skb->data,
e8e9f696 1196 rx_ring->rx_buf_len,
1b507730 1197 DMA_FROM_DEVICE);
b6ec895e 1198 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1199 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1200 bi->dma = 0;
1201 goto no_buffers;
1202 }
9a799d71 1203 }
d5f398ed 1204
7d637bcc 1205 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1206 if (!bi->page) {
fc77dc3c 1207 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1208 if (!bi->page) {
5b7da515 1209 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1210 goto no_buffers;
1211 }
1212 }
1213
1214 if (!bi->page_dma) {
1215 /* use a half page if we're re-using */
1216 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1217 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1218 bi->page,
1219 bi->page_offset,
1220 PAGE_SIZE / 2,
1221 DMA_FROM_DEVICE);
b6ec895e 1222 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1223 bi->page_dma)) {
5b7da515 1224 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1225 bi->page_dma = 0;
1226 goto no_buffers;
1227 }
1228 }
1229
1230 /* Refresh the desc even if buffer_addrs didn't change
1231 * because each write-back erases this info. */
3a581073
JB		 1232 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1233 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1234 } else {
3a581073 1235 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1236 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1237 }
1238
1239 i++;
1240 if (i == rx_ring->count)
1241 i = 0;
9a799d71 1242 }
7c6e0a43 1243
9a799d71
AK		 1244no_buffers:
1245 if (rx_ring->next_to_use != i) {
1246 rx_ring->next_to_use = i;
84ea2591 1247 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1248 }
1249}
1250
c267fc16 1251static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1252{
c267fc16
AD		 1253 /* HW will not DMA in data larger than the given buffer, even if it
1254 * parses the (NFS, of course) header to be larger. In that case, it
1255 * fills the header buffer and spills the rest into the page.
1256 */
1257 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1258 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1259 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1260 if (hlen > IXGBE_RX_HDR_SIZE)
1261 hlen = IXGBE_RX_HDR_SIZE;
1262 return hlen;
7c6e0a43
JB		 1263}
1264
f8212f97
AD		 1265/**
1266 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1267 * @skb: pointer to the last skb in the rsc queue
1268 *
1269 * This function changes a queue full of hw rsc buffers into a completed
1270 * packet. It uses the ->prev pointers to find the first packet and then
1271 * turns it into the frag list owner.
1272 **/
aa80175a 1273static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1274{
1275 unsigned int frag_list_size = 0;
aa80175a 1276 unsigned int skb_cnt = 1;
f8212f97
AD		 1277
1278 while (skb->prev) {
1279 struct sk_buff *prev = skb->prev;
1280 frag_list_size += skb->len;
1281 skb->prev = NULL;
1282 skb = prev;
aa80175a 1283 skb_cnt++;
f8212f97
AD		 1284 }
1285
1286 skb_shinfo(skb)->frag_list = skb->next;
1287 skb->next = NULL;
1288 skb->len += frag_list_size;
1289 skb->data_len += frag_list_size;
1290 skb->truesize += frag_list_size;
aa80175a
AD		 1291 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1292
f8212f97
AD		 1293 return skb;
1294}
1295
aa80175a
AD		 1296static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1297{
1298 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1299 IXGBE_RXDADV_RSCCNT_MASK);
1300}
43634e82 1301
c267fc16 1302static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1303 struct ixgbe_ring *rx_ring,
1304 int *work_done, int work_to_do)
9a799d71 1305{
78b6f4ce 1306 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1307 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1308 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1309 struct sk_buff *skb;
d2f4fbe2 1310 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1311 const int current_node = numa_node_id();
3d8fd385
YZ		 1312#ifdef IXGBE_FCOE
1313 int ddp_bytes = 0;
1314#endif /* IXGBE_FCOE */
c267fc16
AD		 1315 u32 staterr;
1316 u16 i;
1317 u16 cleaned_count = 0;
aa80175a 1318 bool pkt_is_rsc = false;
9a799d71
AK		 1319
1320 i = rx_ring->next_to_clean;
31f05a2d 1321 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1322 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1323
1324 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1325 u32 upper_len = 0;
9a799d71 1326
3c945e5b 1327 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1328
c267fc16
AD		 1329 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1330
9a799d71 1331 skb = rx_buffer_info->skb;
9a799d71 1332 rx_buffer_info->skb = NULL;
c267fc16 1333 prefetch(skb->data);
9a799d71 1334
c267fc16 1335 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1336 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1337
1338 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1339 if (rx_buffer_info->dma) {
c267fc16 1340 u16 hlen;
aa80175a 1341 if (pkt_is_rsc &&
c267fc16
AD		 1342 !(staterr & IXGBE_RXD_STAT_EOP) &&
1343 !skb->prev) {
43634e82
MC		 1344 /*
1345 * When HWRSC is enabled, delay unmapping
1346 * of the first packet. It carries the
1347 * header information, HW may still
1348 * access the header after the writeback.
1349 * Only unmap it when EOP is reached
1350 */
e8171aaa 1351 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1352 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1353 } else {
b6ec895e 1354 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1355 rx_buffer_info->dma,
1356 rx_ring->rx_buf_len,
1357 DMA_FROM_DEVICE);
e8171aaa 1358 }
4f57ca6e 1359 rx_buffer_info->dma = 0;
c267fc16
AD		 1360
1361 if (ring_is_ps_enabled(rx_ring)) {
1362 hlen = ixgbe_get_hlen(rx_desc);
1363 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1364 } else {
1365 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1366 }
1367
1368 skb_put(skb, hlen);
1369 } else {
1370 /* assume packet split since header is unmapped */
1371 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1372 }
1373
1374 if (upper_len) {
b6ec895e
AD		 1375 dma_unmap_page(rx_ring->dev,
1376 rx_buffer_info->page_dma,
1377 PAGE_SIZE / 2,
1378 DMA_FROM_DEVICE);
9a799d71
AK		 1379 rx_buffer_info->page_dma = 0;
1380 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1381 rx_buffer_info->page,
1382 rx_buffer_info->page_offset,
1383 upper_len);
762f4c57 1384
c267fc16
AD		 1385 if ((page_count(rx_buffer_info->page) == 1) &&
1386 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1387 get_page(rx_buffer_info->page);
c267fc16
AD		 1388 else
1389 rx_buffer_info->page = NULL;
9a799d71
AK		 1390
1391 skb->len += upper_len;
1392 skb->data_len += upper_len;
1393 skb->truesize += upper_len;
1394 }
1395
1396 i++;
1397 if (i == rx_ring->count)
1398 i = 0;
9a799d71 1399
31f05a2d 1400 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1401 prefetch(next_rxd);
9a799d71 1402 cleaned_count++;
f8212f97 1403
aa80175a 1404 if (pkt_is_rsc) {
f8212f97
AD		 1405 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1406 IXGBE_RXDADV_NEXTP_SHIFT;
1407 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1408 } else {
1409 next_buffer = &rx_ring->rx_buffer_info[i];
1410 }
1411
c267fc16 1412 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1413 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1414 rx_buffer_info->skb = next_buffer->skb;
1415 rx_buffer_info->dma = next_buffer->dma;
1416 next_buffer->skb = skb;
1417 next_buffer->dma = 0;
1418 } else {
1419 skb->next = next_buffer->skb;
1420 skb->next->prev = skb;
1421 }
5b7da515 1422 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1423 goto next_desc;
1424 }
1425
aa80175a
AD		 1426 if (skb->prev) {
1427 skb = ixgbe_transform_rsc_queue(skb);
1428 /* if we got here without RSC the packet is invalid */
1429 if (!pkt_is_rsc) {
1430 __pskb_trim(skb, 0);
1431 rx_buffer_info->skb = skb;
1432 goto next_desc;
1433 }
1434 }
c267fc16
AD		 1435
1436 if (ring_is_rsc_enabled(rx_ring)) {
1437 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1438 dma_unmap_single(rx_ring->dev,
1439 IXGBE_RSC_CB(skb)->dma,
1440 rx_ring->rx_buf_len,
1441 DMA_FROM_DEVICE);
1442 IXGBE_RSC_CB(skb)->dma = 0;
1443 IXGBE_RSC_CB(skb)->delay_unmap = false;
1444 }
aa80175a
AD		 1445 }
1446 if (pkt_is_rsc) {
c267fc16
AD		 1447 if (ring_is_ps_enabled(rx_ring))
1448 rx_ring->rx_stats.rsc_count +=
aa80175a 1449 skb_shinfo(skb)->nr_frags;
c267fc16 1450 else
aa80175a
AD		 1451 rx_ring->rx_stats.rsc_count +=
1452 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1453 rx_ring->rx_stats.rsc_flush++;
1454 }
1455
1456 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1457 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1458 /* trim packet back to size 0 and recycle it */
1459 __pskb_trim(skb, 0);
1460 rx_buffer_info->skb = skb;
9a799d71
AK		 1461 goto next_desc;
1462 }
1463
8bae1b2b 1464 ixgbe_rx_checksum(adapter, rx_desc, skb);
67a74ee2
ET		 1465 if (adapter->netdev->features & NETIF_F_RXHASH)
1466 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1467
1468 /* probably a little skewed due to removing CRC */
1469 total_rx_bytes += skb->len;
1470 total_rx_packets++;
1471
fc77dc3c 1472 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1473#ifdef IXGBE_FCOE
1474 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1475 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1476 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1477 if (!ddp_bytes)
332d4a7d 1478 goto next_desc;
3d8fd385 1479 }
332d4a7d 1480#endif /* IXGBE_FCOE */
fdaff1ce 1481 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1482
1483next_desc:
1484 rx_desc->wb.upper.status_error = 0;
1485
c267fc16
AD		 1486 (*work_done)++;
1487 if (*work_done >= work_to_do)
1488 break;
1489
9a799d71
AK		 1490 /* return some buffers to hardware, one at a time is too slow */
1491 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1492 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1493 cleaned_count = 0;
1494 }
1495
1496 /* use prefetched values */
1497 rx_desc = next_rxd;
9a799d71 1498 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1499 }
1500
9a799d71
AK		 1501 rx_ring->next_to_clean = i;
1502 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1503
1504 if (cleaned_count)
fc77dc3c 1505 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1506
3d8fd385
YZ		 1507#ifdef IXGBE_FCOE
1508 /* include DDPed FCoE data */
1509 if (ddp_bytes > 0) {
1510 unsigned int mss;
1511
fc77dc3c 1512 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1513 sizeof(struct fc_frame_header) -
1514 sizeof(struct fcoe_crc_eof);
1515 if (mss > 512)
1516 mss &= ~511;
1517 total_rx_bytes += ddp_bytes;
1518 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1519 }
1520#endif /* IXGBE_FCOE */
1521
f494e8fa
AV		 1522 rx_ring->total_packets += total_rx_packets;
1523 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1524 u64_stats_update_begin(&rx_ring->syncp);
1525 rx_ring->stats.packets += total_rx_packets;
1526 rx_ring->stats.bytes += total_rx_bytes;
1527 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1528}
1529
021230d4 1530static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1531/**
1532 * ixgbe_configure_msix - Configure MSI-X hardware
1533 * @adapter: board private structure
1534 *
1535 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1536 * interrupts.
1537 **/
1538static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1539{
021230d4 1540 struct ixgbe_q_vector *q_vector;
bf29ee6c 1541 int i, q_vectors, v_idx, r_idx;
021230d4 1542 u32 mask;
9a799d71 1543
021230d4 1544 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1545
4df10466
JB		 1546 /*
1547 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1548 * corresponding register.
1549 */
1550 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1551 q_vector = adapter->q_vector[v_idx];
984b3f57 1552 /* XXX for_each_set_bit(...) */
021230d4 1553 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1554 adapter->num_rx_queues);
021230d4
AV		 1555
1556 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1557 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1558 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1559 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1560 adapter->num_rx_queues,
1561 r_idx + 1);
021230d4
AV		 1562 }
1563 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1564 adapter->num_tx_queues);
021230d4
AV		 1565
1566 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1567 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1568 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1569 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1570 adapter->num_tx_queues,
1571 r_idx + 1);
021230d4
AV		 1572 }
1573
021230d4 1574 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1575 /* tx only */
1576 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1577 else if (q_vector->rxr_count)
f7554a2b
NS		 1578 /* rx or mixed */
1579 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1580
fe49f04a 1581 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1582 /* If Flow Director is enabled, set interrupt affinity */
1583 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1584 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1585 /*
1586 * Allocate the affinity_hint cpumask, assign the mask
1587 * for this vector, and set our affinity_hint for
1588 * this irq.
1589 */
1590 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1591 GFP_KERNEL))
1592 return;
1593 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1594 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1595 q_vector->affinity_mask);
1596 }
9a799d71
AK		 1597 }
1598
bd508178
AD		 1599 switch (adapter->hw.mac.type) {
1600 case ixgbe_mac_82598EB:
e8e26350 1601 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1602 v_idx);
bd508178
AD		 1603 break;
1604 case ixgbe_mac_82599EB:
b93a2226 1605 case ixgbe_mac_X540:
e8e26350 1606 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1607 break;
1608
1609 default:
1610 break;
1611 }
021230d4
AV		 1612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1613
41fb9248 1614 /* set up to autoclear timer, and the vectors */
021230d4 1615 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1616 if (adapter->num_vfs)
1617 mask &= ~(IXGBE_EIMS_OTHER |
1618 IXGBE_EIMS_MAILBOX |
1619 IXGBE_EIMS_LSC);
1620 else
1621 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1623}
1624
f494e8fa
AV		 1625enum latency_range {
1626 lowest_latency = 0,
1627 low_latency = 1,
1628 bulk_latency = 2,
1629 latency_invalid = 255
1630};
1631
1632/**
1633 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1634 * @adapter: pointer to adapter
1635 * @eitr: eitr setting (ints per sec) to give last timeslice
1636 * @itr_setting: current throttle rate in ints/second
1637 * @packets: the number of packets during this measurement interval
1638 * @bytes: the number of bytes during this measurement interval
1639 *
1640 * Stores a new ITR value based on packets and byte
1641 * counts during the last interrupt. The advantage of per interrupt
1642 * computation is faster updates and more accurate ITR for the current
1643 * traffic pattern. Constants in this function were computed
1644 * based on theoretical maximum wire speed and thresholds were set based
1645 * on testing data as well as attempting to minimize response time
1646 * while increasing bulk throughput.
1647 * this functionality is controlled by the InterruptThrottleRate module
1648 * parameter (see ixgbe_param.c)
1649 **/
1650static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1651 u32 eitr, u8 itr_setting,
1652 int packets, int bytes)
f494e8fa
AV		 1653{
1654 unsigned int retval = itr_setting;
1655 u32 timepassed_us;
1656 u64 bytes_perint;
1657
1658 if (packets == 0)
1659 goto update_itr_done;
1660
1661
1662 /* simple throttlerate management
1663 * 0-20MB/s lowest (100000 ints/s)
1664 * 20-100MB/s low (20000 ints/s)
1665 * 100-1249MB/s bulk (8000 ints/s)
1666 */
1667 /* what was last interrupt timeslice? */
1668 timepassed_us = 1000000/eitr;
1669 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1670
1671 switch (itr_setting) {
1672 case lowest_latency:
1673 if (bytes_perint > adapter->eitr_low)
1674 retval = low_latency;
1675 break;
1676 case low_latency:
1677 if (bytes_perint > adapter->eitr_high)
1678 retval = bulk_latency;
1679 else if (bytes_perint <= adapter->eitr_low)
1680 retval = lowest_latency;
1681 break;
1682 case bulk_latency:
1683 if (bytes_perint <= adapter->eitr_high)
1684 retval = low_latency;
1685 break;
1686 }
1687
1688update_itr_done:
1689 return retval;
1690}
1691
509ee935
JB		 1692/**
1693 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1694 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1695 *
1696 * This function is made to be called by ethtool and by the driver
1697 * when it needs to update EITR registers at runtime. Hardware
1698 * specific quirks/differences are taken care of here.
1699 */
fe49f04a 1700void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1701{
fe49f04a 1702 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1703 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1704 int v_idx = q_vector->v_idx;
1705 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1706
bd508178
AD		 1707 switch (adapter->hw.mac.type) {
1708 case ixgbe_mac_82598EB:
509ee935
JB		 1709 /* must write high and low 16 bits to reset counter */
1710 itr_reg |= (itr_reg << 16);
bd508178
AD		 1711 break;
1712 case ixgbe_mac_82599EB:
b93a2226 1713 case ixgbe_mac_X540:
f8d1dcaf 1714 /*
b93a2226 1715 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1716 * max interrupt rate, but there is an errata where it can
1717 * not be zero with RSC
1718 */
1719 if (itr_reg == 8 &&
1720 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1721 itr_reg = 0;
1722
509ee935
JB		 1723 /*
1724 * set the WDIS bit to not clear the timer bits and cause an
1725 * immediate assertion of the interrupt
1726 */
1727 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1728 break;
1729 default:
1730 break;
509ee935
JB		 1731 }
1732 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1733}
1734
f494e8fa
AV		 1735static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1736{
1737 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1738 int i, r_idx;
f494e8fa
AV		 1739 u32 new_itr;
1740 u8 current_itr, ret_itr;
f494e8fa
AV		 1741
1742 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1743 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1744 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1745 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1746 q_vector->tx_itr,
1747 tx_ring->total_packets,
1748 tx_ring->total_bytes);
f494e8fa
AV		 1749 /* if the result for this queue would decrease interrupt
1750 * rate for this vector then use that result */
30efa5a3 1751 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1752 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1753 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1754 r_idx + 1);
f494e8fa
AV		 1755 }
1756
1757 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1758 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1759 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1760 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1761 q_vector->rx_itr,
1762 rx_ring->total_packets,
1763 rx_ring->total_bytes);
f494e8fa
AV		 1764 /* if the result for this queue would decrease interrupt
1765 * rate for this vector then use that result */
30efa5a3 1766 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1767 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1768 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1769 r_idx + 1);
f494e8fa
AV		 1770 }
1771
30efa5a3 1772 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1773
1774 switch (current_itr) {
1775 /* counts and packets in update_itr are dependent on these numbers */
1776 case lowest_latency:
1777 new_itr = 100000;
1778 break;
1779 case low_latency:
1780 new_itr = 20000; /* aka hwitr = ~200 */
1781 break;
1782 case bulk_latency:
1783 default:
1784 new_itr = 8000;
1785 break;
1786 }
1787
1788 if (new_itr != q_vector->eitr) {
fe49f04a 1789 /* do an exponential smoothing */
125601bf 1790 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1791
1792 /* save the algorithm value here, not the smoothed one */
1793 q_vector->eitr = new_itr;
fe49f04a
AD		 1794
1795 ixgbe_write_eitr(q_vector);
f494e8fa 1796 }
f494e8fa
AV		 1797}
1798
119fc60a
MC		 1799/**
1800 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1801 * @work: pointer to work_struct containing our data
1802 **/
1803static void ixgbe_check_overtemp_task(struct work_struct *work)
1804{
1805 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1806 struct ixgbe_adapter,
1807 check_overtemp_task);
119fc60a
MC		 1808 struct ixgbe_hw *hw = &adapter->hw;
1809 u32 eicr = adapter->interrupt_event;
1810
7ca647bd
JP		 1811 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1812 return;
1813
1814 switch (hw->device_id) {
1815 case IXGBE_DEV_ID_82599_T3_LOM: {
1816 u32 autoneg;
1817 bool link_up = false;
1818
1819 if (hw->mac.ops.check_link)
1820 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1821
1822 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1823 (eicr & IXGBE_EICR_LSC))
1824 /* Check if this is due to overtemp */
1825 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1826 break;
1827 return;
1828 }
1829 default:
1830 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1831 return;
7ca647bd 1832 break;
119fc60a 1833 }
7ca647bd
JP		 1834 e_crit(drv,
1835 "Network adapter has been stopped because it has over heated. "
1836 "Restart the computer. If the problem persists, "
1837 "power off the system and replace the adapter\n");
1838 /* write to clear the interrupt */
1839 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1840}
1841
0befdb3e
JB		 1842static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1843{
1844 struct ixgbe_hw *hw = &adapter->hw;
1845
1846 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1847 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1848 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1849 /* write to clear the interrupt */
1850 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1851 }
1852}
cf8280ee 1853
e8e26350
PW		 1854static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1855{
1856 struct ixgbe_hw *hw = &adapter->hw;
1857
73c4b7cd
AD		 1858 if (eicr & IXGBE_EICR_GPI_SDP2) {
1859 /* Clear the interrupt */
1860 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1861 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1862 schedule_work(&adapter->sfp_config_module_task);
1863 }
1864
e8e26350
PW		 1865 if (eicr & IXGBE_EICR_GPI_SDP1) {
1866 /* Clear the interrupt */
1867 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
73c4b7cd
AD		 1868 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1869 schedule_work(&adapter->multispeed_fiber_task);
e8e26350
PW		 1870 }
1871}
1872
cf8280ee
JB		 1873static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1874{
1875 struct ixgbe_hw *hw = &adapter->hw;
1876
1877 adapter->lsc_int++;
1878 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1879 adapter->link_check_timeout = jiffies;
1880 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1881 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1882 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1883 schedule_work(&adapter->watchdog_task);
1884 }
1885}
1886
9a799d71
AK		 1887static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1888{
1889 struct net_device *netdev = data;
1890 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1891 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1892 u32 eicr;
1893
1894 /*
1895 * Workaround for Silicon errata. Use clear-by-write instead
1896 * of clear-by-read. Reading with EICS will return the
1897 * interrupt causes without clearing, which later be done
1898 * with the write to EICR.
1899 */
1900 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1901 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1902
cf8280ee
JB		 1903 if (eicr & IXGBE_EICR_LSC)
1904 ixgbe_check_lsc(adapter);
d4f80882 1905
1cdd1ec8
GR		 1906 if (eicr & IXGBE_EICR_MAILBOX)
1907 ixgbe_msg_task(adapter);
1908
bd508178
AD		 1909 switch (hw->mac.type) {
1910 case ixgbe_mac_82599EB:
d994653d
DS		 1911 ixgbe_check_sfp_event(adapter, eicr);
1912 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1913 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1914 adapter->interrupt_event = eicr;
1915 schedule_work(&adapter->check_overtemp_task);
1916 }
1917 /* now fallthrough to handle Flow Director */
b93a2226 1918 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1919 /* Handle Flow Director Full threshold interrupt */
1920 if (eicr & IXGBE_EICR_FLOW_DIR) {
1921 int i;
1922 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1923 /* Disable transmits before FDIR Re-initialization */
1924 netif_tx_stop_all_queues(netdev);
1925 for (i = 0; i < adapter->num_tx_queues; i++) {
1926 struct ixgbe_ring *tx_ring =
e8e9f696 1927 adapter->tx_ring[i];
7d637bcc
AD		 1928 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1929 &tx_ring->state))
c4cf55e5
PWJ		 1930 schedule_work(&adapter->fdir_reinit_task);
1931 }
1932 }
bd508178
AD		 1933 break;
1934 default:
1935 break;
c4cf55e5 1936 }
bd508178
AD		 1937
1938 ixgbe_check_fan_failure(adapter, eicr);
1939
d4f80882
AV		 1940 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1941 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1942
1943 return IRQ_HANDLED;
1944}
1945
fe49f04a
AD		 1946static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1947 u64 qmask)
1948{
1949 u32 mask;
bd508178 1950 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1951
bd508178
AD		 1952 switch (hw->mac.type) {
1953 case ixgbe_mac_82598EB:
fe49f04a 1954 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1955 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1956 break;
1957 case ixgbe_mac_82599EB:
b93a2226 1958 case ixgbe_mac_X540:
fe49f04a 1959 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1960 if (mask)
1961 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1962 mask = (qmask >> 32);
bd508178
AD		 1963 if (mask)
1964 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1965 break;
1966 default:
1967 break;
fe49f04a
AD		 1968 }
1969 /* skip the flush */
1970}
1971
1972static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1973 u64 qmask)
fe49f04a
AD		 1974{
1975 u32 mask;
bd508178 1976 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1977
bd508178
AD		 1978 switch (hw->mac.type) {
1979 case ixgbe_mac_82598EB:
fe49f04a 1980 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1981 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1982 break;
1983 case ixgbe_mac_82599EB:
b93a2226 1984 case ixgbe_mac_X540:
fe49f04a 1985 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1986 if (mask)
1987 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1988 mask = (qmask >> 32);
bd508178
AD		 1989 if (mask)
1990 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1991 break;
1992 default:
1993 break;
fe49f04a
AD		 1994 }
1995 /* skip the flush */
1996}
1997
9a799d71
AK		 1998static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1999{
021230d4
AV		 2000 struct ixgbe_q_vector *q_vector = data;
2001 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2002 struct ixgbe_ring *tx_ring;
021230d4
AV		 2003 int i, r_idx;
2004
2005 if (!q_vector->txr_count)
2006 return IRQ_HANDLED;
2007
2008 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2009 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2010 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 2011 tx_ring->total_bytes = 0;
2012 tx_ring->total_packets = 0;
021230d4 2013 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2014 r_idx + 1);
021230d4 2015 }
9a799d71 2016
9b471446 2017 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2018 napi_schedule(&q_vector->napi);
2019
9a799d71
AK		 2020 return IRQ_HANDLED;
2021}
2022
021230d4
AV		 2023/**
2024 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2025 * @irq: unused
2026 * @data: pointer to our q_vector struct for this interrupt vector
2027 **/
9a799d71
AK		 2028static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2029{
021230d4
AV		 2030 struct ixgbe_q_vector *q_vector = data;
2031 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2032 struct ixgbe_ring *rx_ring;
021230d4 2033 int r_idx;
30efa5a3 2034 int i;
021230d4 2035
33cf09c9
AD		 2036#ifdef CONFIG_IXGBE_DCA
2037 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2038 ixgbe_update_dca(q_vector);
2039#endif
2040
021230d4 2041 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2042 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2043 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2044 rx_ring->total_bytes = 0;
2045 rx_ring->total_packets = 0;
2046 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2047 r_idx + 1);
30efa5a3
JB		 2048 }
2049
021230d4
AV		 2050 if (!q_vector->rxr_count)
2051 return IRQ_HANDLED;
2052
9b471446 2053 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2054 napi_schedule(&q_vector->napi);
021230d4
AV		 2055
2056 return IRQ_HANDLED;
2057}
2058
2059static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2060{
91281fd3
AD		 2061 struct ixgbe_q_vector *q_vector = data;
2062 struct ixgbe_adapter *adapter = q_vector->adapter;
2063 struct ixgbe_ring *ring;
2064 int r_idx;
2065 int i;
2066
2067 if (!q_vector->txr_count && !q_vector->rxr_count)
2068 return IRQ_HANDLED;
2069
2070 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2071 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2072 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2073 ring->total_bytes = 0;
2074 ring->total_packets = 0;
2075 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2076 r_idx + 1);
91281fd3
AD		 2077 }
2078
2079 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2080 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2081 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2082 ring->total_bytes = 0;
2083 ring->total_packets = 0;
2084 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2085 r_idx + 1);
91281fd3
AD		 2086 }
2087
9b471446 2088 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2089 napi_schedule(&q_vector->napi);
9a799d71 2090
9a799d71
AK		 2091 return IRQ_HANDLED;
2092}
2093
021230d4
AV		 2094/**
2095 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2096 * @napi: napi struct with our devices info in it
2097 * @budget: amount of work driver is allowed to do this pass, in packets
2098 *
f0848276
JB		 2099 * This function is optimized for cleaning one queue only on a single
2100 * q_vector!!!
021230d4 2101 **/
9a799d71
AK		 2102static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2103{
021230d4 2104 struct ixgbe_q_vector *q_vector =
e8e9f696 2105 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2106 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2107 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2108 int work_done = 0;
021230d4 2109 long r_idx;
9a799d71 2110
5dd2d332 2111#ifdef CONFIG_IXGBE_DCA
bd0362dd 2112 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2113 ixgbe_update_dca(q_vector);
bd0362dd 2114#endif
9a799d71 2115
33cf09c9
AD		 2116 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2117 rx_ring = adapter->rx_ring[r_idx];
2118
78b6f4ce 2119 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2120
021230d4
AV		 2121 /* If all Rx work done, exit the polling mode */
2122 if (work_done < budget) {
288379f0 2123 napi_complete(napi);
f7554a2b 2124 if (adapter->rx_itr_setting & 1)
f494e8fa 2125 ixgbe_set_itr_msix(q_vector);
9a799d71 2126 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2127 ixgbe_irq_enable_queues(adapter,
e8e9f696 2128 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2129 }
2130
2131 return work_done;
2132}
2133
f0848276 2134/**
91281fd3 2135 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2136 * @napi: napi struct with our devices info in it
2137 * @budget: amount of work driver is allowed to do this pass, in packets
2138 *
2139 * This function will clean more than one rx queue associated with a
2140 * q_vector.
2141 **/
91281fd3 2142static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2143{
2144 struct ixgbe_q_vector *q_vector =
e8e9f696 2145 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2146 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2147 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2148 int work_done = 0, i;
2149 long r_idx;
91281fd3
AD		 2150 bool tx_clean_complete = true;
2151
33cf09c9
AD		 2152#ifdef CONFIG_IXGBE_DCA
2153 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2154 ixgbe_update_dca(q_vector);
2155#endif
2156
91281fd3
AD		 2157 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2158 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2159 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2160 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2161 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2162 r_idx + 1);
91281fd3 2163 }
f0848276
JB		 2164
2165 /* attempt to distribute budget to each queue fairly, but don't allow
2166 * the budget to go below 1 because we'll exit polling */
2167 budget /= (q_vector->rxr_count ?: 1);
2168 budget = max(budget, 1);
2169 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2170 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2171 ring = adapter->rx_ring[r_idx];
91281fd3 2172 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2173 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2174 r_idx + 1);
f0848276
JB		 2175 }
2176
2177 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2178 ring = adapter->rx_ring[r_idx];
f0848276 2179 /* If all Rx work done, exit the polling mode */
7f821875 2180 if (work_done < budget) {
288379f0 2181 napi_complete(napi);
f7554a2b 2182 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2183 ixgbe_set_itr_msix(q_vector);
2184 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2185 ixgbe_irq_enable_queues(adapter,
e8e9f696 2186 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2187 return 0;
2188 }
2189
2190 return work_done;
2191}
91281fd3
AD		 2192
2193/**
2194 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2195 * @napi: napi struct with our devices info in it
2196 * @budget: amount of work driver is allowed to do this pass, in packets
2197 *
2198 * This function is optimized for cleaning one queue only on a single
2199 * q_vector!!!
2200 **/
2201static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2202{
2203 struct ixgbe_q_vector *q_vector =
e8e9f696 2204 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2205 struct ixgbe_adapter *adapter = q_vector->adapter;
2206 struct ixgbe_ring *tx_ring = NULL;
2207 int work_done = 0;
2208 long r_idx;
2209
91281fd3
AD		 2210#ifdef CONFIG_IXGBE_DCA
2211 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2212 ixgbe_update_dca(q_vector);
91281fd3
AD		 2213#endif
2214
33cf09c9
AD		 2215 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2216 tx_ring = adapter->tx_ring[r_idx];
2217
91281fd3
AD		 2218 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2219 work_done = budget;
2220
f7554a2b 2221 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2222 if (work_done < budget) {
2223 napi_complete(napi);
f7554a2b 2224 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2225 ixgbe_set_itr_msix(q_vector);
2226 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2227 ixgbe_irq_enable_queues(adapter,
2228 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2229 }
2230
2231 return work_done;
2232}
2233
021230d4 2234static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2235 int r_idx)
021230d4 2236{
7a921c93 2237 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2238 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2239
2240 set_bit(r_idx, q_vector->rxr_idx);
2241 q_vector->rxr_count++;
2274543f 2242 rx_ring->q_vector = q_vector;
021230d4
AV		 2243}
2244
2245static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2246 int t_idx)
021230d4 2247{
7a921c93 2248 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2249 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2250
2251 set_bit(t_idx, q_vector->txr_idx);
2252 q_vector->txr_count++;
2274543f 2253 tx_ring->q_vector = q_vector;
021230d4
AV		 2254}
2255
9a799d71 2256/**
021230d4
AV		 2257 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2258 * @adapter: board private structure to initialize
9a799d71 2259 *
021230d4
AV		 2260 * This function maps descriptor rings to the queue-specific vectors
2261 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2262 * one vector per ring/queue, but on a constrained vector budget, we
2263 * group the rings as "efficiently" as possible. You would add new
2264 * mapping configurations in here.
9a799d71 2265 **/
d0759ebb 2266static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2267{
d0759ebb 2268 int q_vectors;
021230d4
AV		 2269 int v_start = 0;
2270 int rxr_idx = 0, txr_idx = 0;
2271 int rxr_remaining = adapter->num_rx_queues;
2272 int txr_remaining = adapter->num_tx_queues;
2273 int i, j;
2274 int rqpv, tqpv;
2275 int err = 0;
2276
2277 /* No mapping required if MSI-X is disabled. */
2278 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2279 goto out;
9a799d71 2280
d0759ebb
AD		 2281 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2282
021230d4
AV		 2283 /*
2284 * The ideal configuration...
2285 * We have enough vectors to map one per queue.
2286 */
d0759ebb 2287 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2288 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2289 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2290
021230d4
AV		 2291 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2292 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2293
9a799d71 2294 goto out;
021230d4 2295 }
9a799d71 2296
021230d4
AV		 2297 /*
2298 * If we don't have enough vectors for a 1-to-1
2299 * mapping, we'll have to group them so there are
2300 * multiple queues per vector.
2301 */
2302 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2303 for (i = v_start; i < q_vectors; i++) {
2304 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2305 for (j = 0; j < rqpv; j++) {
2306 map_vector_to_rxq(adapter, i, rxr_idx);
2307 rxr_idx++;
2308 rxr_remaining--;
2309 }
d0759ebb 2310 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2311 for (j = 0; j < tqpv; j++) {
2312 map_vector_to_txq(adapter, i, txr_idx);
2313 txr_idx++;
2314 txr_remaining--;
9a799d71 2315 }
9a799d71 2316 }
021230d4
AV		 2317out:
2318 return err;
2319}
2320
2321/**
2322 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2323 * @adapter: board private structure
2324 *
2325 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2326 * interrupts from the kernel.
2327 **/
2328static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2329{
2330 struct net_device *netdev = adapter->netdev;
2331 irqreturn_t (*handler)(int, void *);
2332 int i, vector, q_vectors, err;
e8e9f696 2333 int ri = 0, ti = 0;
021230d4
AV		 2334
2335 /* Decrement for Other and TCP Timer vectors */
2336 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2337
d0759ebb 2338 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2339 if (err)
d0759ebb 2340 return err;
021230d4 2341
d0759ebb
AD		 2342#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2343 ? &ixgbe_msix_clean_many : \
2344 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2345 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2346 NULL)
021230d4 2347 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2348 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2349 handler = SET_HANDLER(q_vector);
cb13fc20 2350
e8e9f696 2351 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2352 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2353 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2354 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2355 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2356 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2357 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2358 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2359 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2360 ti++;
d0759ebb
AD		 2361 } else {
2362 /* skip this unused q_vector */
2363 continue;
32aa77a4 2364 }
021230d4 2365 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2366 handler, 0, q_vector->name,
2367 q_vector);
9a799d71 2368 if (err) {
396e799c 2369 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2370 "Error: %d\n", err);
021230d4 2371 goto free_queue_irqs;
9a799d71 2372 }
9a799d71
AK		 2373 }
2374
d0759ebb 2375 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2376 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb 2377 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
9a799d71 2378 if (err) {
396e799c 2379 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2380 goto free_queue_irqs;
9a799d71
AK		 2381 }
2382
9a799d71
AK		 2383 return 0;
2384
021230d4
AV		 2385free_queue_irqs:
2386 for (i = vector - 1; i >= 0; i--)
2387 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2388 adapter->q_vector[i]);
021230d4
AV		 2389 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2390 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2391 kfree(adapter->msix_entries);
2392 adapter->msix_entries = NULL;
9a799d71
AK		 2393 return err;
2394}
2395
f494e8fa
AV		 2396static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2397{
7a921c93 2398 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2399 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2400 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2401 u32 new_itr = q_vector->eitr;
2402 u8 current_itr;
f494e8fa 2403
30efa5a3 2404 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2405 q_vector->tx_itr,
2406 tx_ring->total_packets,
2407 tx_ring->total_bytes);
30efa5a3 2408 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2409 q_vector->rx_itr,
2410 rx_ring->total_packets,
2411 rx_ring->total_bytes);
f494e8fa 2412
30efa5a3 2413 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2414
2415 switch (current_itr) {
2416 /* counts and packets in update_itr are dependent on these numbers */
2417 case lowest_latency:
2418 new_itr = 100000;
2419 break;
2420 case low_latency:
2421 new_itr = 20000; /* aka hwitr = ~200 */
2422 break;
2423 case bulk_latency:
2424 new_itr = 8000;
2425 break;
2426 default:
2427 break;
2428 }
2429
2430 if (new_itr != q_vector->eitr) {
fe49f04a 2431 /* do an exponential smoothing */
125601bf 2432 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2433
125601bf 2434 /* save the algorithm value here */
509ee935 2435 q_vector->eitr = new_itr;
fe49f04a
AD		 2436
2437 ixgbe_write_eitr(q_vector);
f494e8fa 2438 }
f494e8fa
AV		 2439}
2440
79aefa45
AD		 2441/**
2442 * ixgbe_irq_enable - Enable default interrupt generation settings
2443 * @adapter: board private structure
2444 **/
6af3b9eb
ET		 2445static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2446 bool flush)
79aefa45
AD		 2447{
2448 u32 mask;
835462fc
NS		 2449
2450 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2451 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2452 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2453 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2454 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2455 switch (adapter->hw.mac.type) {
2456 case ixgbe_mac_82599EB:
b93a2226 2457 case ixgbe_mac_X540:
2a41ff81 2458 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2459 mask |= IXGBE_EIMS_GPI_SDP1;
2460 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2461 if (adapter->num_vfs)
2462 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2463 break;
2464 default:
2465 break;
e8e26350 2466 }
c4cf55e5
PWJ		 2467 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2468 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2469 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2470
79aefa45 2471 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2472 if (queues)
2473 ixgbe_irq_enable_queues(adapter, ~0);
2474 if (flush)
2475 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2476
2477 if (adapter->num_vfs > 32) {
2478 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2479 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2480 }
79aefa45 2481}
021230d4 2482
9a799d71 2483/**
021230d4 2484 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2485 * @irq: interrupt number
2486 * @data: pointer to a network interface device structure
9a799d71
AK		 2487 **/
2488static irqreturn_t ixgbe_intr(int irq, void *data)
2489{
2490 struct net_device *netdev = data;
2491 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2492 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2493 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2494 u32 eicr;
2495
54037505 2496 /*
6af3b9eb 2497 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2498 * before the read of EICR.
2499 */
2500 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2501
021230d4
AV		 2502 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2503 * therefore no explict interrupt disable is necessary */
2504 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2505 if (!eicr) {
6af3b9eb
ET		 2506 /*
2507 * shared interrupt alert!
f47cf66e 2508 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2509 * have disabled interrupts due to EIAM
2510 * finish the workaround of silicon errata on 82598. Unmask
2511 * the interrupt that we masked before the EICR read.
2512 */
2513 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2514 ixgbe_irq_enable(adapter, true, true);
9a799d71 2515 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2516 }
9a799d71 2517
cf8280ee
JB		 2518 if (eicr & IXGBE_EICR_LSC)
2519 ixgbe_check_lsc(adapter);
021230d4 2520
bd508178
AD		 2521 switch (hw->mac.type) {
2522 case ixgbe_mac_82599EB:
e8e26350 2523 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2524 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2525 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2526 adapter->interrupt_event = eicr;
2527 schedule_work(&adapter->check_overtemp_task);
2528 }
2529 break;
2530 default:
2531 break;
2532 }
e8e26350 2533
0befdb3e
JB		 2534 ixgbe_check_fan_failure(adapter, eicr);
2535
7a921c93 2536 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2537 adapter->tx_ring[0]->total_packets = 0;
2538 adapter->tx_ring[0]->total_bytes = 0;
2539 adapter->rx_ring[0]->total_packets = 0;
2540 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2541 /* would disable interrupts here but EIAM disabled it */
7a921c93 2542 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2543 }
2544
6af3b9eb
ET		 2545 /*
2546 * re-enable link(maybe) and non-queue interrupts, no flush.
2547 * ixgbe_poll will re-enable the queue interrupts
2548 */
2549
2550 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2551 ixgbe_irq_enable(adapter, false, false);
2552
9a799d71
AK		 2553 return IRQ_HANDLED;
2554}
2555
021230d4
AV		 2556static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2557{
2558 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2559
2560 for (i = 0; i < q_vectors; i++) {
7a921c93 2561 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2562 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2563 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2564 q_vector->rxr_count = 0;
2565 q_vector->txr_count = 0;
2566 }
2567}
2568
9a799d71
AK		 2569/**
2570 * ixgbe_request_irq - initialize interrupts
2571 * @adapter: board private structure
2572 *
2573 * Attempts to configure interrupts using the best available
2574 * capabilities of the hardware and kernel.
2575 **/
021230d4 2576static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2577{
2578 struct net_device *netdev = adapter->netdev;
021230d4 2579 int err;
9a799d71 2580
021230d4
AV		 2581 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2582 err = ixgbe_request_msix_irqs(adapter);
2583 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2584 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2585 netdev->name, netdev);
021230d4 2586 } else {
a0607fd3 2587 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2588 netdev->name, netdev);
9a799d71
AK		 2589 }
2590
9a799d71 2591 if (err)
396e799c 2592 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2593
9a799d71
AK		 2594 return err;
2595}
2596
2597static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2598{
2599 struct net_device *netdev = adapter->netdev;
2600
2601 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2602 int i, q_vectors;
9a799d71 2603
021230d4
AV		 2604 q_vectors = adapter->num_msix_vectors;
2605
2606 i = q_vectors - 1;
9a799d71 2607 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2608
021230d4
AV		 2609 i--;
2610 for (; i >= 0; i--) {
894ff7cf
AD		 2611 /* free only the irqs that were actually requested */
2612 if (!adapter->q_vector[i]->rxr_count &&
2613 !adapter->q_vector[i]->txr_count)
2614 continue;
2615
021230d4 2616 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2617 adapter->q_vector[i]);
021230d4
AV		 2618 }
2619
2620 ixgbe_reset_q_vectors(adapter);
2621 } else {
2622 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2623 }
2624}
2625
22d5a71b
JB		 2626/**
2627 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2628 * @adapter: board private structure
2629 **/
2630static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2631{
bd508178
AD		 2632 switch (adapter->hw.mac.type) {
2633 case ixgbe_mac_82598EB:
835462fc 2634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2635 break;
2636 case ixgbe_mac_82599EB:
b93a2226 2637 case ixgbe_mac_X540:
835462fc
NS		 2638 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2640 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2641 if (adapter->num_vfs > 32)
2642 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2643 break;
2644 default:
2645 break;
22d5a71b
JB		 2646 }
2647 IXGBE_WRITE_FLUSH(&adapter->hw);
2648 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2649 int i;
2650 for (i = 0; i < adapter->num_msix_vectors; i++)
2651 synchronize_irq(adapter->msix_entries[i].vector);
2652 } else {
2653 synchronize_irq(adapter->pdev->irq);
2654 }
2655}
2656
9a799d71
AK		 2657/**
2658 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2659 *
2660 **/
2661static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2662{
9a799d71
AK		 2663 struct ixgbe_hw *hw = &adapter->hw;
2664
021230d4 2665 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2666 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2667
e8e26350
PW		 2668 ixgbe_set_ivar(adapter, 0, 0, 0);
2669 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2670
2671 map_vector_to_rxq(adapter, 0, 0);
2672 map_vector_to_txq(adapter, 0, 0);
2673
396e799c 2674 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2675}
2676
43e69bf0
AD		 2677/**
2678 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2679 * @adapter: board private structure
2680 * @ring: structure containing ring specific data
2681 *
2682 * Configure the Tx descriptor ring after a reset.
2683 **/
84418e3b
AD		 2684void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2685 struct ixgbe_ring *ring)
43e69bf0
AD		 2686{
2687 struct ixgbe_hw *hw = &adapter->hw;
2688 u64 tdba = ring->dma;
2f1860b8
AD		 2689 int wait_loop = 10;
2690 u32 txdctl;
bf29ee6c 2691 u8 reg_idx = ring->reg_idx;
43e69bf0 2692
2f1860b8
AD		 2693 /* disable queue to avoid issues while updating state */
2694 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2695 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2696 txdctl & ~IXGBE_TXDCTL_ENABLE);
2697 IXGBE_WRITE_FLUSH(hw);
2698
43e69bf0 2699 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2700 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2701 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2702 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2703 ring->count * sizeof(union ixgbe_adv_tx_desc));
2704 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2705 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2706 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2707
2f1860b8
AD		 2708 /* configure fetching thresholds */
2709 if (adapter->rx_itr_setting == 0) {
2710 /* cannot set wthresh when itr==0 */
2711 txdctl &= ~0x007F0000;
2712 } else {
2713 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2714 txdctl |= (8 << 16);
2715 }
2716 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2717 /* PThresh workaround for Tx hang with DFP enabled. */
2718 txdctl |= 32;
2719 }
2720
2721 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2722 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2723 adapter->atr_sample_rate) {
2724 ring->atr_sample_rate = adapter->atr_sample_rate;
2725 ring->atr_count = 0;
2726 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2727 } else {
2728 ring->atr_sample_rate = 0;
2729 }
2f1860b8 2730
c84d324c
JF		 2731 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2732
2f1860b8
AD		 2733 /* enable queue */
2734 txdctl |= IXGBE_TXDCTL_ENABLE;
2735 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2736
2737 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2738 if (hw->mac.type == ixgbe_mac_82598EB &&
2739 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2740 return;
2741
2742 /* poll to verify queue is enabled */
2743 do {
032b4325 2744 usleep_range(1000, 2000);
2f1860b8
AD		 2745 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2746 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2747 if (!wait_loop)
2748 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2749}
2750
120ff942
AD		 2751static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2752{
2753 struct ixgbe_hw *hw = &adapter->hw;
2754 u32 rttdcs;
2755 u32 mask;
2756
2757 if (hw->mac.type == ixgbe_mac_82598EB)
2758 return;
2759
2760 /* disable the arbiter while setting MTQC */
2761 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2762 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2763 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2764
2765 /* set transmit pool layout */
2766 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2767 switch (adapter->flags & mask) {
2768
2769 case (IXGBE_FLAG_SRIOV_ENABLED):
2770 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2771 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2772 break;
2773
2774 case (IXGBE_FLAG_DCB_ENABLED):
2775 /* We enable 8 traffic classes, DCB only */
2776 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2777 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2778 break;
2779
2780 default:
2781 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2782 break;
2783 }
2784
2785 /* re-enable the arbiter */
2786 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2787 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2788}
2789
9a799d71 2790/**
3a581073 2791 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2792 * @adapter: board private structure
2793 *
2794 * Configure the Tx unit of the MAC after a reset.
2795 **/
2796static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2797{
2f1860b8
AD		 2798 struct ixgbe_hw *hw = &adapter->hw;
2799 u32 dmatxctl;
43e69bf0 2800 u32 i;
9a799d71 2801
2f1860b8
AD		 2802 ixgbe_setup_mtqc(adapter);
2803
2804 if (hw->mac.type != ixgbe_mac_82598EB) {
2805 /* DMATXCTL.EN must be before Tx queues are enabled */
2806 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2807 dmatxctl |= IXGBE_DMATXCTL_TE;
2808 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2809 }
2810
9a799d71 2811 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2812 for (i = 0; i < adapter->num_tx_queues; i++)
2813 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2814}
2815
e8e26350 2816#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2817
a6616b42 2818static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2819 struct ixgbe_ring *rx_ring)
cc41ac7c 2820{
cc41ac7c 2821 u32 srrctl;
bf29ee6c 2822 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2823
bd508178
AD		 2824 switch (adapter->hw.mac.type) {
2825 case ixgbe_mac_82598EB: {
2826 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2827 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2828 reg_idx = reg_idx & mask;
cc41ac7c 2829 }
bd508178
AD		 2830 break;
2831 case ixgbe_mac_82599EB:
b93a2226 2832 case ixgbe_mac_X540:
bd508178
AD		 2833 default:
2834 break;
2835 }
2836
bf29ee6c 2837 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2838
2839 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2840 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2841 if (adapter->num_vfs)
2842 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2843
afafd5b0
AD		 2844 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2845 IXGBE_SRRCTL_BSIZEHDR_MASK;
2846
7d637bcc 2847 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2848#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2849 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2850#else
2851 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2852#endif
cc41ac7c 2853 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2854 } else {
afafd5b0
AD		 2855 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2856 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2857 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2858 }
e8e26350 2859
bf29ee6c 2860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2861}
9a799d71 2862
05abb126 2863static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2864{
05abb126
AD		 2865 struct ixgbe_hw *hw = &adapter->hw;
2866 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2867 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2868 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2869 u32 mrqc = 0, reta = 0;
2870 u32 rxcsum;
2871 int i, j;
0cefafad
JB		 2872 int mask;
2873
05abb126
AD		 2874 /* Fill out hash function seeds */
2875 for (i = 0; i < 10; i++)
2876 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2877
2878 /* Fill out redirection table */
2879 for (i = 0, j = 0; i < 128; i++, j++) {
2880 if (j == adapter->ring_feature[RING_F_RSS].indices)
2881 j = 0;
2882 /* reta = 4-byte sliding window of
2883 * 0x00..(indices-1)(indices-1)00..etc. */
2884 reta = (reta << 8) | (j * 0x11);
2885 if ((i & 3) == 3)
2886 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2887 }
0cefafad 2888
05abb126
AD		 2889 /* Disable indicating checksum in descriptor, enables RSS hash */
2890 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2891 rxcsum |= IXGBE_RXCSUM_PCSD;
2892 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2893
2894 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2895 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2896 else
2897 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2898#ifdef CONFIG_IXGBE_DCB
05abb126 2899 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2900#endif
05abb126
AD		 2901 | IXGBE_FLAG_SRIOV_ENABLED
2902 );
0cefafad
JB		 2903
2904 switch (mask) {
8187cd48
JF		 2905#ifdef CONFIG_IXGBE_DCB
2906 case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2907 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2908 break;
2909 case (IXGBE_FLAG_DCB_ENABLED):
2910 mrqc = IXGBE_MRQC_RT8TCEN;
2911 break;
2912#endif /* CONFIG_IXGBE_DCB */
0cefafad
JB		 2913 case (IXGBE_FLAG_RSS_ENABLED):
2914 mrqc = IXGBE_MRQC_RSSEN;
2915 break;
1cdd1ec8
GR		 2916 case (IXGBE_FLAG_SRIOV_ENABLED):
2917 mrqc = IXGBE_MRQC_VMDQEN;
2918 break;
0cefafad
JB		 2919 default:
2920 break;
2921 }
2922
05abb126
AD		 2923 /* Perform hash on these packet types */
2924 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2925 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2926 | IXGBE_MRQC_RSS_FIELD_IPV6
2927 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2928
2929 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2930}
2931
b93a2226
DS		 2932/**
2933 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2934 * @adapter: address of board private structure
2935 * @ring: structure containing ring specific data
2936 **/
2937void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2938 struct ixgbe_ring *ring)
2939{
2940 struct ixgbe_hw *hw = &adapter->hw;
2941 u32 rscctrl;
2942 u8 reg_idx = ring->reg_idx;
2943
2944 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2945 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2946 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2947}
2948
bb5a9ad2
NS		 2949/**
2950 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2951 * @adapter: address of board private structure
2952 * @index: index of ring to set
bb5a9ad2 2953 **/
b93a2226 2954void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2955 struct ixgbe_ring *ring)
bb5a9ad2 2956{
bb5a9ad2 2957 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2958 u32 rscctrl;
edd2ea55 2959 int rx_buf_len;
bf29ee6c 2960 u8 reg_idx = ring->reg_idx;
7367096a 2961
7d637bcc 2962 if (!ring_is_rsc_enabled(ring))
7367096a 2963 return;
bb5a9ad2 2964
7367096a
AD		 2965 rx_buf_len = ring->rx_buf_len;
2966 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2967 rscctrl |= IXGBE_RSCCTL_RSCEN;
2968 /*
2969 * we must limit the number of descriptors so that the
2970 * total size of max desc * buf_len is not greater
2971 * than 65535
2972 */
7d637bcc 2973 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2974#if (MAX_SKB_FRAGS > 16)
2975 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2976#elif (MAX_SKB_FRAGS > 8)
2977 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2978#elif (MAX_SKB_FRAGS > 4)
2979 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2980#else
2981 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2982#endif
2983 } else {
2984 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2985 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2986 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2987 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2988 else
2989 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2990 }
7367096a 2991 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2992}
2993
9e10e045
AD		 2994/**
2995 * ixgbe_set_uta - Set unicast filter table address
2996 * @adapter: board private structure
2997 *
2998 * The unicast table address is a register array of 32-bit registers.
2999 * The table is meant to be used in a way similar to how the MTA is used
3000 * however due to certain limitations in the hardware it is necessary to
3001 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3002 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3003 **/
3004static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3005{
3006 struct ixgbe_hw *hw = &adapter->hw;
3007 int i;
3008
3009 /* The UTA table only exists on 82599 hardware and newer */
3010 if (hw->mac.type < ixgbe_mac_82599EB)
3011 return;
3012
3013 /* we only need to do this if VMDq is enabled */
3014 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3015 return;
3016
3017 for (i = 0; i < 128; i++)
3018 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3019}
3020
3021#define IXGBE_MAX_RX_DESC_POLL 10
3022static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3023 struct ixgbe_ring *ring)
3024{
3025 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3026 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3027 u32 rxdctl;
bf29ee6c 3028 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3029
3030 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3031 if (hw->mac.type == ixgbe_mac_82598EB &&
3032 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3033 return;
3034
3035 do {
032b4325 3036 usleep_range(1000, 2000);
9e10e045
AD		 3037 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3038 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3039
3040 if (!wait_loop) {
3041 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3042 "the polling period\n", reg_idx);
3043 }
3044}
3045
2d39d576
YZ		 3046void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3047 struct ixgbe_ring *ring)
3048{
3049 struct ixgbe_hw *hw = &adapter->hw;
3050 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3051 u32 rxdctl;
3052 u8 reg_idx = ring->reg_idx;
3053
3054 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3055 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3056
3057 /* write value back with RXDCTL.ENABLE bit cleared */
3058 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3059
3060 if (hw->mac.type == ixgbe_mac_82598EB &&
3061 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3062 return;
3063
3064 /* the hardware may take up to 100us to really disable the rx queue */
3065 do {
3066 udelay(10);
3067 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3068 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3069
3070 if (!wait_loop) {
3071 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3072 "the polling period\n", reg_idx);
3073 }
3074}
3075
84418e3b
AD		 3076void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3077 struct ixgbe_ring *ring)
acd37177
AD		 3078{
3079 struct ixgbe_hw *hw = &adapter->hw;
3080 u64 rdba = ring->dma;
9e10e045 3081 u32 rxdctl;
bf29ee6c 3082 u8 reg_idx = ring->reg_idx;
acd37177 3083
9e10e045
AD		 3084 /* disable queue to avoid issues while updating state */
3085 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3086 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3087
acd37177
AD		 3088 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3089 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3090 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3091 ring->count * sizeof(union ixgbe_adv_rx_desc));
3092 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3093 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3094 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3095
3096 ixgbe_configure_srrctl(adapter, ring);
3097 ixgbe_configure_rscctl(adapter, ring);
3098
e9f98072
GR		 3099 /* If operating in IOV mode set RLPML for X540 */
3100 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3101 hw->mac.type == ixgbe_mac_X540) {
3102 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3103 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3104 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3105 }
3106
9e10e045
AD		 3107 if (hw->mac.type == ixgbe_mac_82598EB) {
3108 /*
3109 * enable cache line friendly hardware writes:
3110 * PTHRESH=32 descriptors (half the internal cache),
3111 * this also removes ugly rx_no_buffer_count increment
3112 * HTHRESH=4 descriptors (to minimize latency on fetch)
3113 * WTHRESH=8 burst writeback up to two cache lines
3114 */
3115 rxdctl &= ~0x3FFFFF;
3116 rxdctl |= 0x080420;
3117 }
3118
3119 /* enable receive descriptor ring */
3120 rxdctl |= IXGBE_RXDCTL_ENABLE;
3121 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3122
3123 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 3124 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 3125}
3126
48654521
AD		 3127static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3128{
3129 struct ixgbe_hw *hw = &adapter->hw;
3130 int p;
3131
3132 /* PSRTYPE must be initialized in non 82598 adapters */
3133 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3134 IXGBE_PSRTYPE_UDPHDR |
3135 IXGBE_PSRTYPE_IPV4HDR |
48654521 3136 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3137 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3138
3139 if (hw->mac.type == ixgbe_mac_82598EB)
3140 return;
3141
3142 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3143 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3144
3145 for (p = 0; p < adapter->num_rx_pools; p++)
3146 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3147 psrtype);
3148}
3149
f5b4a52e
AD		 3150static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3151{
3152 struct ixgbe_hw *hw = &adapter->hw;
3153 u32 gcr_ext;
3154 u32 vt_reg_bits;
3155 u32 reg_offset, vf_shift;
3156 u32 vmdctl;
3157
3158 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3159 return;
3160
3161 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3162 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3163 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3164 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3165
3166 vf_shift = adapter->num_vfs % 32;
3167 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3168
3169 /* Enable only the PF's pool for Tx/Rx */
3170 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3171 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3172 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3173 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3174 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3175
3176 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3177 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3178
3179 /*
3180 * Set up VF register offsets for selected VT Mode,
3181 * i.e. 32 or 64 VFs for SR-IOV
3182 */
3183 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3184 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3185 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3186 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3187
3188 /* enable Tx loopback for VF/PF communication */
3189 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3
GR		 3190 /* Enable MAC Anti-Spoofing */
3191 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3192 adapter->num_vfs);
f5b4a52e
AD		 3193}
3194
477de6ed 3195static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3196{
9a799d71
AK		 3197 struct ixgbe_hw *hw = &adapter->hw;
3198 struct net_device *netdev = adapter->netdev;
3199 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3200 int rx_buf_len;
477de6ed
AD		 3201 struct ixgbe_ring *rx_ring;
3202 int i;
3203 u32 mhadd, hlreg0;
48654521 3204
9a799d71 3205 /* Decide whether to use packet split mode or not */
a124339a
DS		 3206 /* On by default */
3207 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3208
1cdd1ec8 3209 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3210 if (adapter->num_vfs)
3211 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3212
3213 /* Disable packet split due to 82599 erratum #45 */
3214 if (hw->mac.type == ixgbe_mac_82599EB)
3215 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3216
3217 /* Set the RX buffer length according to the mode */
3218 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3219 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3220 } else {
0c19d6af 3221 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3222 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3223 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3224 else
477de6ed 3225 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3226 }
3227
63f39bd1 3228#ifdef IXGBE_FCOE
477de6ed
AD		 3229 /* adjust max frame to be able to do baby jumbo for FCoE */
3230 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3231 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3232 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3233
477de6ed
AD		 3234#endif /* IXGBE_FCOE */
3235 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3236 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3237 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3238 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3239
3240 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3241 }
3242
3243 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3244 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3245 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3246 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3247
0cefafad
JB		 3248 /*
3249 * Setup the HW Rx Head and Tail Descriptor Pointers and
3250 * the Base and Length of the Rx Descriptor Ring
3251 */
9a799d71 3252 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3253 rx_ring = adapter->rx_ring[i];
a6616b42 3254 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3255
6e455b89 3256 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3257 set_ring_ps_enabled(rx_ring);
3258 else
3259 clear_ring_ps_enabled(rx_ring);
3260
3261 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3262 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3263 else
7d637bcc 3264 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3265
63f39bd1 3266#ifdef IXGBE_FCOE
e8e9f696 3267 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3268 struct ixgbe_ring_feature *f;
3269 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3270 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3271 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3272 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3273 rx_ring->rx_buf_len =
e8e9f696 3274 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3275 } else if (!ring_is_rsc_enabled(rx_ring) &&
3276 !ring_is_ps_enabled(rx_ring)) {
3277 rx_ring->rx_buf_len =
3278 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3279 }
63f39bd1 3280 }
63f39bd1 3281#endif /* IXGBE_FCOE */
477de6ed 3282 }
477de6ed
AD		 3283}
3284
7367096a
AD		 3285static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3286{
3287 struct ixgbe_hw *hw = &adapter->hw;
3288 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3289
3290 switch (hw->mac.type) {
3291 case ixgbe_mac_82598EB:
3292 /*
3293 * For VMDq support of different descriptor types or
3294 * buffer sizes through the use of multiple SRRCTL
3295 * registers, RDRXCTL.MVMEN must be set to 1
3296 *
3297 * also, the manual doesn't mention it clearly but DCA hints
3298 * will only use queue 0's tags unless this bit is set. Side
3299 * effects of setting this bit are only that SRRCTL must be
3300 * fully programmed [0..15]
3301 */
3302 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3303 break;
3304 case ixgbe_mac_82599EB:
b93a2226 3305 case ixgbe_mac_X540:
7367096a
AD		 3306 /* Disable RSC for ACK packets */
3307 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3308 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3309 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3310 /* hardware requires some bits to be set by default */
3311 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3312 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3313 break;
3314 default:
3315 /* We should do nothing since we don't know this hardware */
3316 return;
3317 }
3318
3319 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3320}
3321
477de6ed
AD		 3322/**
3323 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3324 * @adapter: board private structure
3325 *
3326 * Configure the Rx unit of the MAC after a reset.
3327 **/
3328static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3329{
3330 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3331 int i;
3332 u32 rxctrl;
477de6ed
AD		 3333
3334 /* disable receives while setting up the descriptors */
3335 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3336 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3337
3338 ixgbe_setup_psrtype(adapter);
7367096a 3339 ixgbe_setup_rdrxctl(adapter);
477de6ed 3340
9e10e045 3341 /* Program registers for the distribution of queues */
f5b4a52e 3342 ixgbe_setup_mrqc(adapter);
f5b4a52e 3343
9e10e045
AD		 3344 ixgbe_set_uta(adapter);
3345
477de6ed
AD		 3346 /* set_rx_buffer_len must be called before ring initialization */
3347 ixgbe_set_rx_buffer_len(adapter);
3348
3349 /*
3350 * Setup the HW Rx Head and Tail Descriptor Pointers and
3351 * the Base and Length of the Rx Descriptor Ring
3352 */
9e10e045
AD		 3353 for (i = 0; i < adapter->num_rx_queues; i++)
3354 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3355
9e10e045
AD		 3356 /* disable drop enable for 82598 parts */
3357 if (hw->mac.type == ixgbe_mac_82598EB)
3358 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3359
3360 /* enable all receives */
3361 rxctrl |= IXGBE_RXCTRL_RXEN;
3362 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3363}
3364
068c89b0
DS		 3365static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3366{
3367 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3368 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3369 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3370
3371 /* add VID to filter table */
1ada1b1b 3372 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3373 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3374}
3375
3376static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3377{
3378 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3379 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3380 int pool_ndx = adapter->num_vfs;
068c89b0 3381
068c89b0 3382 /* remove VID from filter table */
1ada1b1b 3383 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3384 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3385}
3386
5f6c0181
JB		 3387/**
3388 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3389 * @adapter: driver data
3390 */
3391static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3392{
3393 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3394 u32 vlnctrl;
3395
3396 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3397 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3398 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3399}
3400
3401/**
3402 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3403 * @adapter: driver data
3404 */
3405static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3406{
3407 struct ixgbe_hw *hw = &adapter->hw;
3408 u32 vlnctrl;
3409
3410 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3411 vlnctrl |= IXGBE_VLNCTRL_VFE;
3412 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3413 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3414}
3415
3416/**
3417 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3418 * @adapter: driver data
3419 */
3420static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3421{
3422 struct ixgbe_hw *hw = &adapter->hw;
3423 u32 vlnctrl;
5f6c0181
JB		 3424 int i, j;
3425
3426 switch (hw->mac.type) {
3427 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3428 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3429 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3430 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3431 break;
3432 case ixgbe_mac_82599EB:
b93a2226 3433 case ixgbe_mac_X540:
5f6c0181
JB		 3434 for (i = 0; i < adapter->num_rx_queues; i++) {
3435 j = adapter->rx_ring[i]->reg_idx;
3436 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3437 vlnctrl &= ~IXGBE_RXDCTL_VME;
3438 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3439 }
3440 break;
3441 default:
3442 break;
3443 }
3444}
3445
3446/**
f62bbb5e 3447 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3448 * @adapter: driver data
3449 */
f62bbb5e 3450static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3451{
3452 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3453 u32 vlnctrl;
5f6c0181
JB		 3454 int i, j;
3455
3456 switch (hw->mac.type) {
3457 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3458 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3459 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3460 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3461 break;
3462 case ixgbe_mac_82599EB:
b93a2226 3463 case ixgbe_mac_X540:
5f6c0181
JB		 3464 for (i = 0; i < adapter->num_rx_queues; i++) {
3465 j = adapter->rx_ring[i]->reg_idx;
3466 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3467 vlnctrl |= IXGBE_RXDCTL_VME;
3468 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3469 }
3470 break;
3471 default:
3472 break;
3473 }
3474}
3475
9a799d71
AK		 3476static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3477{
f62bbb5e 3478 u16 vid;
9a799d71 3479
f62bbb5e
JG		 3480 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3481
3482 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3483 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3484}
3485
2850062a
AD		 3486/**
3487 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3488 * @netdev: network interface device structure
3489 *
3490 * Writes unicast address list to the RAR table.
3491 * Returns: -ENOMEM on failure/insufficient address space
3492 * 0 on no addresses written
3493 * X on writing X addresses to the RAR table
3494 **/
3495static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3496{
3497 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3498 struct ixgbe_hw *hw = &adapter->hw;
3499 unsigned int vfn = adapter->num_vfs;
3500 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3501 int count = 0;
3502
3503 /* return ENOMEM indicating insufficient memory for addresses */
3504 if (netdev_uc_count(netdev) > rar_entries)
3505 return -ENOMEM;
3506
3507 if (!netdev_uc_empty(netdev) && rar_entries) {
3508 struct netdev_hw_addr *ha;
3509 /* return error if we do not support writing to RAR table */
3510 if (!hw->mac.ops.set_rar)
3511 return -ENOMEM;
3512
3513 netdev_for_each_uc_addr(ha, netdev) {
3514 if (!rar_entries)
3515 break;
3516 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3517 vfn, IXGBE_RAH_AV);
3518 count++;
3519 }
3520 }
3521 /* write the addresses in reverse order to avoid write combining */
3522 for (; rar_entries > 0 ; rar_entries--)
3523 hw->mac.ops.clear_rar(hw, rar_entries);
3524
3525 return count;
3526}
3527
9a799d71 3528/**
2c5645cf 3529 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3530 * @netdev: network interface device structure
3531 *
2c5645cf
CL		 3532 * The set_rx_method entry point is called whenever the unicast/multicast
3533 * address list or the network interface flags are updated. This routine is
3534 * responsible for configuring the hardware for proper unicast, multicast and
3535 * promiscuous mode.
9a799d71 3536 **/
7f870475 3537void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3538{
3539 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3540 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3541 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3542 int count;
9a799d71
AK		 3543
3544 /* Check for Promiscuous and All Multicast modes */
3545
3546 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3547
f5dc442b
AD		 3548 /* set all bits that we expect to always be set */
3549 fctrl |= IXGBE_FCTRL_BAM;
3550 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3551 fctrl |= IXGBE_FCTRL_PMCF;
3552
2850062a
AD		 3553 /* clear the bits we are changing the status of */
3554 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3555
9a799d71 3556 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3557 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3558 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3559 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3560 /* don't hardware filter vlans in promisc mode */
3561 ixgbe_vlan_filter_disable(adapter);
9a799d71 3562 } else {
746b9f02
PM		 3563 if (netdev->flags & IFF_ALLMULTI) {
3564 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3565 vmolr |= IXGBE_VMOLR_MPE;
3566 } else {
3567 /*
3568 * Write addresses to the MTA, if the attempt fails
25985edc 3569 * then we should just turn on promiscuous mode so
2850062a
AD		 3570 * that we can at least receive multicast traffic
3571 */
3572 hw->mac.ops.update_mc_addr_list(hw, netdev);
3573 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3574 }
5f6c0181 3575 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3576 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3577 /*
3578 * Write addresses to available RAR registers, if there is not
3579 * sufficient space to store all the addresses then enable
25985edc 3580 * unicast promiscuous mode
2850062a
AD		 3581 */
3582 count = ixgbe_write_uc_addr_list(netdev);
3583 if (count < 0) {
3584 fctrl |= IXGBE_FCTRL_UPE;
3585 vmolr |= IXGBE_VMOLR_ROPE;
3586 }
9a799d71
AK		 3587 }
3588
2850062a 3589 if (adapter->num_vfs) {
1cdd1ec8 3590 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3591 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3592 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3593 IXGBE_VMOLR_ROPE);
3594 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3595 }
3596
3597 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3598
3599 if (netdev->features & NETIF_F_HW_VLAN_RX)
3600 ixgbe_vlan_strip_enable(adapter);
3601 else
3602 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3603}
3604
021230d4
AV		 3605static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3606{
3607 int q_idx;
3608 struct ixgbe_q_vector *q_vector;
3609 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3610
3611 /* legacy and MSI only use one vector */
3612 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3613 q_vectors = 1;
3614
3615 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3616 struct napi_struct *napi;
7a921c93 3617 q_vector = adapter->q_vector[q_idx];
f0848276 3618 napi = &q_vector->napi;
91281fd3
AD		 3619 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3620 if (!q_vector->rxr_count || !q_vector->txr_count) {
3621 if (q_vector->txr_count == 1)
3622 napi->poll = &ixgbe_clean_txonly;
3623 else if (q_vector->rxr_count == 1)
3624 napi->poll = &ixgbe_clean_rxonly;
3625 }
3626 }
f0848276
JB		 3627
3628 napi_enable(napi);
021230d4
AV		 3629 }
3630}
3631
3632static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3633{
3634 int q_idx;
3635 struct ixgbe_q_vector *q_vector;
3636 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3637
3638 /* legacy and MSI only use one vector */
3639 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3640 q_vectors = 1;
3641
3642 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3643 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3644 napi_disable(&q_vector->napi);
3645 }
3646}
3647
7a6b6f51 3648#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3649/*
3650 * ixgbe_configure_dcb - Configure DCB hardware
3651 * @adapter: ixgbe adapter struct
3652 *
3653 * This is called by the driver on open to configure the DCB hardware.
3654 * This is also called by the gennetlink interface when reconfiguring
3655 * the DCB state.
3656 */
3657static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3658{
3659 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3660 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3661
67ebd791
AD		 3662 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3663 if (hw->mac.type == ixgbe_mac_82598EB)
3664 netif_set_gso_max_size(adapter->netdev, 65536);
3665 return;
3666 }
3667
3668 if (hw->mac.type == ixgbe_mac_82598EB)
3669 netif_set_gso_max_size(adapter->netdev, 32768);
3670
2f90b865 3671
2f90b865 3672 /* Enable VLAN tag insert/strip */
f62bbb5e 3673 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3674
2f90b865 3675 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3676
3677 /* reconfigure the hardware */
c27931da
JF		 3678 if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) {
3679#ifdef CONFIG_FCOE
3680 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3681 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3682#endif
3683 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3684 DCB_TX_CONFIG);
3685 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3686 DCB_RX_CONFIG);
3687 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3688 } else {
3689 struct net_device *dev = adapter->netdev;
3690
3691 if (adapter->ixgbe_ieee_ets)
3692 dev->dcbnl_ops->ieee_setets(dev,
3693 adapter->ixgbe_ieee_ets);
3694 if (adapter->ixgbe_ieee_pfc)
3695 dev->dcbnl_ops->ieee_setpfc(dev,
3696 adapter->ixgbe_ieee_pfc);
3697 }
8187cd48
JF		 3698
3699 /* Enable RSS Hash per TC */
3700 if (hw->mac.type != ixgbe_mac_82598EB) {
3701 int i;
3702 u32 reg = 0;
3703
3704 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3705 u8 msb = 0;
3706 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3707
3708 while (cnt >>= 1)
3709 msb++;
3710
3711 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3712 }
3713 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3714 }
2f90b865
AD		 3715}
3716
3717#endif
9a799d71
AK		 3718static void ixgbe_configure(struct ixgbe_adapter *adapter)
3719{
3720 struct net_device *netdev = adapter->netdev;
c4cf55e5 3721 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3722 int i;
3723
7a6b6f51 3724#ifdef CONFIG_IXGBE_DCB
67ebd791 3725 ixgbe_configure_dcb(adapter);
2f90b865 3726#endif
9a799d71 3727
f62bbb5e
JG		 3728 ixgbe_set_rx_mode(netdev);
3729 ixgbe_restore_vlan(adapter);
3730
eacd73f7
YZ		 3731#ifdef IXGBE_FCOE
3732 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3733 ixgbe_configure_fcoe(adapter);
3734
3735#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3736 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3737 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3738 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3739 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3740 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3741 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3742 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3743 }
933d41f1 3744 ixgbe_configure_virtualization(adapter);
c4cf55e5 3745
9a799d71
AK		 3746 ixgbe_configure_tx(adapter);
3747 ixgbe_configure_rx(adapter);
9a799d71
AK		 3748}
3749
e8e26350
PW		 3750static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3751{
3752 switch (hw->phy.type) {
3753 case ixgbe_phy_sfp_avago:
3754 case ixgbe_phy_sfp_ftl:
3755 case ixgbe_phy_sfp_intel:
3756 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3757 case ixgbe_phy_sfp_passive_tyco:
3758 case ixgbe_phy_sfp_passive_unknown:
3759 case ixgbe_phy_sfp_active_unknown:
3760 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3761 return true;
3762 default:
3763 return false;
3764 }
3765}
3766
0ecc061d 3767/**
e8e26350
PW		 3768 * ixgbe_sfp_link_config - set up SFP+ link
3769 * @adapter: pointer to private adapter struct
3770 **/
3771static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3772{
3773 struct ixgbe_hw *hw = &adapter->hw;
3774
3775 if (hw->phy.multispeed_fiber) {
3776 /*
3777 * In multispeed fiber setups, the device may not have
3778 * had a physical connection when the driver loaded.
3779 * If that's the case, the initial link configuration
3780 * couldn't get the MAC into 10G or 1G mode, so we'll
3781 * never have a link status change interrupt fire.
3782 * We need to try and force an autonegotiation
3783 * session, then bring up link.
3784 */
4c7e604b
AG		 3785 if (hw->mac.ops.setup_sfp)
3786 hw->mac.ops.setup_sfp(hw);
e8e26350
PW		 3787 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3788 schedule_work(&adapter->multispeed_fiber_task);
3789 } else {
3790 /*
3791 * Direct Attach Cu and non-multispeed fiber modules
3792 * still need to be configured properly prior to
3793 * attempting link.
3794 */
3795 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3796 schedule_work(&adapter->sfp_config_module_task);
3797 }
3798}
3799
3800/**
3801 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3802 * @hw: pointer to private hardware struct
3803 *
3804 * Returns 0 on success, negative on failure
3805 **/
e8e26350 3806static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3807{
3808 u32 autoneg;
8620a103 3809 bool negotiation, link_up = false;
0ecc061d
PWJ		 3810 u32 ret = IXGBE_ERR_LINK_SETUP;
3811
3812 if (hw->mac.ops.check_link)
3813 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3814
3815 if (ret)
3816 goto link_cfg_out;
3817
0b0c2b31
ET		 3818 autoneg = hw->phy.autoneg_advertised;
3819 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3820 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3821 &negotiation);
0ecc061d
PWJ		 3822 if (ret)
3823 goto link_cfg_out;
3824
8620a103
MC		 3825 if (hw->mac.ops.setup_link)
3826 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3827link_cfg_out:
3828 return ret;
3829}
3830
a34bcfff 3831static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3832{
9a799d71 3833 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3834 u32 gpie = 0;
9a799d71 3835
9b471446 3836 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3837 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3838 IXGBE_GPIE_OCD;
3839 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3840 /*
3841 * use EIAM to auto-mask when MSI-X interrupt is asserted
3842 * this saves a register write for every interrupt
3843 */
3844 switch (hw->mac.type) {
3845 case ixgbe_mac_82598EB:
3846 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3847 break;
9b471446 3848 case ixgbe_mac_82599EB:
b93a2226
DS		 3849 case ixgbe_mac_X540:
3850 default:
9b471446
JB		 3851 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3852 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3853 break;
3854 }
3855 } else {
021230d4
AV		 3856 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3857 * specifically only auto mask tx and rx interrupts */
3858 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3859 }
9a799d71 3860
a34bcfff
AD		 3861 /* XXX: to interrupt immediately for EICS writes, enable this */
3862 /* gpie |= IXGBE_GPIE_EIMEN; */
3863
3864 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3865 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3866 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3867 }
3868
a34bcfff
AD		 3869 /* Enable fan failure interrupt */
3870 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3871 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3872
2698b208 3873 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3874 gpie |= IXGBE_SDP1_GPIEN;
3875 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3876 }
a34bcfff
AD		 3877
3878 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3879}
3880
3881static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3882{
3883 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3884 int err;
a34bcfff
AD		 3885 u32 ctrl_ext;
3886
3887 ixgbe_get_hw_control(adapter);
3888 ixgbe_setup_gpie(adapter);
e8e26350 3889
9a799d71
AK		 3890 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3891 ixgbe_configure_msix(adapter);
3892 else
3893 ixgbe_configure_msi_and_legacy(adapter);
3894
c6ecf39a
DS		 3895 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3896 if (hw->mac.ops.enable_tx_laser &&
3897 ((hw->phy.multispeed_fiber) ||
9f911707 3898 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3899 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3900 hw->mac.ops.enable_tx_laser(hw);
3901
9a799d71 3902 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3903 ixgbe_napi_enable_all(adapter);
3904
73c4b7cd
AD		 3905 if (ixgbe_is_sfp(hw)) {
3906 ixgbe_sfp_link_config(adapter);
3907 } else {
3908 err = ixgbe_non_sfp_link_config(hw);
3909 if (err)
3910 e_err(probe, "link_config FAILED %d\n", err);
3911 }
3912
021230d4
AV		 3913 /* clear any pending interrupts, may auto mask */
3914 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3915 ixgbe_irq_enable(adapter, true, true);
9a799d71 3916
bf069c97
DS		 3917 /*
3918 * If this adapter has a fan, check to see if we had a failure
3919 * before we enabled the interrupt.
3920 */
3921 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3922 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3923 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3924 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3925 }
3926
e8e26350
PW		 3927 /*
3928 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3929 * arrived before interrupts were enabled but after probe. Such
3930 * devices wouldn't have their type identified yet. We need to
3931 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3932 * If we're not hot-pluggable SFP+, we just need to configure link
3933 * and bring it up.
3934 */
21cc5b4f 3935 if (hw->phy.type == ixgbe_phy_none)
73c4b7cd 3936 schedule_work(&adapter->sfp_config_module_task);
0ecc061d 3937
1da100bb 3938 /* enable transmits */
477de6ed 3939 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3940
9a799d71
AK		 3941 /* bring the link up in the watchdog, this could race with our first
3942 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3943 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3944 adapter->link_check_timeout = jiffies;
9a799d71 3945 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3946
3947 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3948 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3949 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3950 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3951
9a799d71
AK		 3952 return 0;
3953}
3954
d4f80882
AV		 3955void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3956{
3957 WARN_ON(in_interrupt());
3958 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3959 usleep_range(1000, 2000);
d4f80882 3960 ixgbe_down(adapter);
5809a1ae
GR		 3961 /*
3962 * If SR-IOV enabled then wait a bit before bringing the adapter
3963 * back up to give the VFs time to respond to the reset. The
3964 * two second wait is based upon the watchdog timer cycle in
3965 * the VF driver.
3966 */
3967 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3968 msleep(2000);
d4f80882
AV		 3969 ixgbe_up(adapter);
3970 clear_bit(__IXGBE_RESETTING, &adapter->state);
3971}
3972
9a799d71
AK		 3973int ixgbe_up(struct ixgbe_adapter *adapter)
3974{
3975 /* hardware has been reset, we need to reload some things */
3976 ixgbe_configure(adapter);
3977
3978 return ixgbe_up_complete(adapter);
3979}
3980
3981void ixgbe_reset(struct ixgbe_adapter *adapter)
3982{
c44ade9e 3983 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3984 int err;
3985
3986 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3987 switch (err) {
3988 case 0:
3989 case IXGBE_ERR_SFP_NOT_PRESENT:
3990 break;
3991 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3992 e_dev_err("master disable timed out\n");
da4dd0f7 3993 break;
794caeb2
PWJ		 3994 case IXGBE_ERR_EEPROM_VERSION:
3995 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3996 e_dev_warn("This device is a pre-production adapter/LOM. "
3997 "Please be aware there may be issuesassociated with "
3998 "your hardware. If you are experiencing problems "
3999 "please contact your Intel or hardware "
4000 "representative who provided you with this "
4001 "hardware.\n");
794caeb2 4002 break;
da4dd0f7 4003 default:
849c4542 4004 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4005 }
9a799d71
AK		 4006
4007 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4008 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4009 IXGBE_RAH_AV);
9a799d71
AK		 4010}
4011
9a799d71
AK		 4012/**
4013 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4014 * @rx_ring: ring to free buffers from
4015 **/
b6ec895e 4016static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4017{
b6ec895e 4018 struct device *dev = rx_ring->dev;
9a799d71 4019 unsigned long size;
b6ec895e 4020 u16 i;
9a799d71 4021
84418e3b
AD		 4022 /* ring already cleared, nothing to do */
4023 if (!rx_ring->rx_buffer_info)
4024 return;
9a799d71 4025
84418e3b 4026 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4027 for (i = 0; i < rx_ring->count; i++) {
4028 struct ixgbe_rx_buffer *rx_buffer_info;
4029
4030 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4031 if (rx_buffer_info->dma) {
b6ec895e 4032 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4033 rx_ring->rx_buf_len,
1b507730 4034 DMA_FROM_DEVICE);
9a799d71
AK		 4035 rx_buffer_info->dma = 0;
4036 }
4037 if (rx_buffer_info->skb) {
f8212f97 4038 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4039 rx_buffer_info->skb = NULL;
f8212f97
AD		 4040 do {
4041 struct sk_buff *this = skb;
e8171aaa 4042 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 4043 dma_unmap_single(dev,
1b507730 4044 IXGBE_RSC_CB(this)->dma,
e8e9f696 4045 rx_ring->rx_buf_len,
1b507730 4046 DMA_FROM_DEVICE);
fd3686a8 4047 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 4048 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 4049 }
f8212f97
AD		 4050 skb = skb->prev;
4051 dev_kfree_skb(this);
4052 } while (skb);
9a799d71
AK		 4053 }
4054 if (!rx_buffer_info->page)
4055 continue;
4f57ca6e 4056 if (rx_buffer_info->page_dma) {
b6ec895e 4057 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4058 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4059 rx_buffer_info->page_dma = 0;
4060 }
9a799d71
AK		 4061 put_page(rx_buffer_info->page);
4062 rx_buffer_info->page = NULL;
762f4c57 4063 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4064 }
4065
4066 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4067 memset(rx_ring->rx_buffer_info, 0, size);
4068
4069 /* Zero out the descriptor ring */
4070 memset(rx_ring->desc, 0, rx_ring->size);
4071
4072 rx_ring->next_to_clean = 0;
4073 rx_ring->next_to_use = 0;
9a799d71
AK		 4074}
4075
4076/**
4077 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4078 * @tx_ring: ring to be cleaned
4079 **/
b6ec895e 4080static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4081{
4082 struct ixgbe_tx_buffer *tx_buffer_info;
4083 unsigned long size;
b6ec895e 4084 u16 i;
9a799d71 4085
84418e3b
AD		 4086 /* ring already cleared, nothing to do */
4087 if (!tx_ring->tx_buffer_info)
4088 return;
9a799d71 4089
84418e3b 4090 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4091 for (i = 0; i < tx_ring->count; i++) {
4092 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4093 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4094 }
4095
4096 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4097 memset(tx_ring->tx_buffer_info, 0, size);
4098
4099 /* Zero out the descriptor ring */
4100 memset(tx_ring->desc, 0, tx_ring->size);
4101
4102 tx_ring->next_to_use = 0;
4103 tx_ring->next_to_clean = 0;
9a799d71
AK		 4104}
4105
4106/**
021230d4 4107 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4108 * @adapter: board private structure
4109 **/
021230d4 4110static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4111{
4112 int i;
4113
021230d4 4114 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4115 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4116}
4117
4118/**
021230d4 4119 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4120 * @adapter: board private structure
4121 **/
021230d4 4122static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4123{
4124 int i;
4125
021230d4 4126 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4127 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4128}
4129
4130void ixgbe_down(struct ixgbe_adapter *adapter)
4131{
4132 struct net_device *netdev = adapter->netdev;
7f821875 4133 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4134 u32 rxctrl;
7f821875 4135 u32 txdctl;
bf29ee6c 4136 int i;
b25ebfd2 4137 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4138
4139 /* signal that we are down to the interrupt handler */
4140 set_bit(__IXGBE_DOWN, &adapter->state);
4141
767081ad
GR		 4142 /* disable receive for all VFs and wait one second */
4143 if (adapter->num_vfs) {
767081ad
GR		 4144 /* ping all the active vfs to let them know we are going down */
4145 ixgbe_ping_all_vfs(adapter);
581d1aa7 4146
767081ad
GR		 4147 /* Disable all VFTE/VFRE TX/RX */
4148 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 4149
4150 /* Mark all the VFs as inactive */
4151 for (i = 0 ; i < adapter->num_vfs; i++)
4152 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 4153 }
4154
9a799d71 4155 /* disable receives */
7f821875
JB		 4156 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4157 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4158
2d39d576
YZ		 4159 /* disable all enabled rx queues */
4160 for (i = 0; i < adapter->num_rx_queues; i++)
4161 /* this call also flushes the previous write */
4162 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4163
032b4325 4164 usleep_range(10000, 20000);
9a799d71 4165
7f821875
JB		 4166 netif_tx_stop_all_queues(netdev);
4167
0a1f87cb
DS		 4168 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4169 del_timer_sync(&adapter->sfp_timer);
9a799d71 4170 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 4171 cancel_work_sync(&adapter->watchdog_task);
9a799d71 4172
c0dfb90e
JF		 4173 netif_carrier_off(netdev);
4174 netif_tx_disable(netdev);
4175
4176 ixgbe_irq_disable(adapter);
4177
4178 ixgbe_napi_disable_all(adapter);
4179
b25ebfd2
PW		 4180 /* Cleanup the affinity_hint CPU mask memory and callback */
4181 for (i = 0; i < num_q_vectors; i++) {
4182 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4183 /* clear the affinity_mask in the IRQ descriptor */
4184 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4185 /* release the CPU mask memory */
4186 free_cpumask_var(q_vector->affinity_mask);
4187 }
4188
c4cf55e5
PWJ		 4189 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4190 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4191 cancel_work_sync(&adapter->fdir_reinit_task);
4192
119fc60a
MC		 4193 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4194 cancel_work_sync(&adapter->check_overtemp_task);
4195
7f821875
JB		 4196 /* disable transmits in the hardware now that interrupts are off */
4197 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c
AD		 4198 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4199 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4200 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
e8e9f696 4201 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 4202 }
88512539 4203 /* Disable the Tx DMA engine on 82599 */
bd508178
AD		 4204 switch (hw->mac.type) {
4205 case ixgbe_mac_82599EB:
b93a2226 4206 case ixgbe_mac_X540:
88512539 4207 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4208 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4209 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4210 break;
4211 default:
4212 break;
4213 }
7f821875 4214
6f4a0e45
PL		 4215 if (!pci_channel_offline(adapter->pdev))
4216 ixgbe_reset(adapter);
c6ecf39a
DS		 4217
4218 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4219 if (hw->mac.ops.disable_tx_laser &&
4220 ((hw->phy.multispeed_fiber) ||
9f911707 4221 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4222 (hw->mac.type == ixgbe_mac_82599EB))))
4223 hw->mac.ops.disable_tx_laser(hw);
4224
9a799d71
AK		 4225 ixgbe_clean_all_tx_rings(adapter);
4226 ixgbe_clean_all_rx_rings(adapter);
4227
5dd2d332 4228#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4229 /* since we reset the hardware DCA settings were cleared */
e35ec126 4230 ixgbe_setup_dca(adapter);
96b0e0f6 4231#endif
9a799d71
AK		 4232}
4233
9a799d71 4234/**
021230d4
AV		 4235 * ixgbe_poll - NAPI Rx polling callback
4236 * @napi: structure for representing this polling device
4237 * @budget: how many packets driver is allowed to clean
4238 *
4239 * This function is used for legacy and MSI, NAPI mode
9a799d71 4240 **/
021230d4 4241static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4242{
9a1a69ad 4243 struct ixgbe_q_vector *q_vector =
e8e9f696 4244 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4245 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4246 int tx_clean_complete, work_done = 0;
9a799d71 4247
5dd2d332 4248#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4249 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4250 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4251#endif
4252
4a0b9ca0
PW		 4253 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4254 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4255
9a1a69ad 4256 if (!tx_clean_complete)
d2c7ddd6
DM		 4257 work_done = budget;
4258
53e52c72
DM		 4259 /* If budget not fully consumed, exit the polling mode */
4260 if (work_done < budget) {
288379f0 4261 napi_complete(napi);
f7554a2b 4262 if (adapter->rx_itr_setting & 1)
f494e8fa 4263 ixgbe_set_itr(adapter);
d4f80882 4264 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4265 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4266 }
9a799d71
AK		 4267 return work_done;
4268}
4269
4270/**
4271 * ixgbe_tx_timeout - Respond to a Tx Hang
4272 * @netdev: network interface device structure
4273 **/
4274static void ixgbe_tx_timeout(struct net_device *netdev)
4275{
4276 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4277
c84d324c
JF		 4278 adapter->tx_timeout_count++;
4279
9a799d71
AK		 4280 /* Do the reset outside of interrupt context */
4281 schedule_work(&adapter->reset_task);
4282}
4283
4284static void ixgbe_reset_task(struct work_struct *work)
4285{
4286 struct ixgbe_adapter *adapter;
4287 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4288
2f90b865
AD		 4289 /* If we're already down or resetting, just bail */
4290 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4291 test_bit(__IXGBE_RESETTING, &adapter->state))
4292 return;
4293
dcd79aeb
TI		 4294 ixgbe_dump(adapter);
4295 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 4296 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4297}
4298
4df10466
JB		 4299/**
4300 * ixgbe_set_rss_queues: Allocate queues for RSS
4301 * @adapter: board private structure to initialize
4302 *
4303 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4304 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4305 *
4306 **/
bc97114d
PWJ		 4307static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4308{
4309 bool ret = false;
0cefafad 4310 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4311
4312 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4313 f->mask = 0xF;
4314 adapter->num_rx_queues = f->indices;
4315 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4316 ret = true;
4317 } else {
bc97114d 4318 ret = false;
b9804972
JB		 4319 }
4320
bc97114d
PWJ		 4321 return ret;
4322}
4323
c4cf55e5
PWJ		 4324/**
4325 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4326 * @adapter: board private structure to initialize
4327 *
4328 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4329 * to the original CPU that initiated the Tx session. This runs in addition
4330 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4331 * Rx load across CPUs using RSS.
4332 *
4333 **/
e8e9f696 4334static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4335{
4336 bool ret = false;
4337 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4338
4339 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4340 f_fdir->mask = 0;
4341
4342 /* Flow Director must have RSS enabled */
4343 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4344 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4345 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4346 adapter->num_tx_queues = f_fdir->indices;
4347 adapter->num_rx_queues = f_fdir->indices;
4348 ret = true;
4349 } else {
4350 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4351 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4352 }
4353 return ret;
4354}
4355
0331a832
YZ		 4356#ifdef IXGBE_FCOE
4357/**
4358 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4359 * @adapter: board private structure to initialize
4360 *
4361 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4362 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4363 * rx queues out of the max number of rx queues, instead, it is used as the
4364 * index of the first rx queue used by FCoE.
4365 *
4366 **/
4367static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4368{
0331a832
YZ		 4369 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4370
e5b64635
JF		 4371 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4372 return false;
4373
4374 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
0331a832 4375#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4376 int tc;
4377 struct net_device *dev = adapter->netdev;
4378
4379 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4380 f->indices = dev->tc_to_txq[tc].count;
4381 f->mask = dev->tc_to_txq[tc].offset;
0331a832 4382#endif
e5b64635
JF		 4383 } else {
4384 f->indices = min((int)num_online_cpus(), f->indices);
4385
4386 adapter->num_rx_queues = 1;
4387 adapter->num_tx_queues = 1;
4388
0331a832 4389 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4390 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4391 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4392 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4393 ixgbe_set_fdir_queues(adapter);
4394 else
4395 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4396 }
4397 /* adding FCoE rx rings to the end */
4398 f->mask = adapter->num_rx_queues;
4399 adapter->num_rx_queues += f->indices;
8de8b2e6 4400 adapter->num_tx_queues += f->indices;
e5b64635 4401 }
0331a832 4402
e5b64635
JF		 4403 return true;
4404}
4405#endif /* IXGBE_FCOE */
4406
4407#ifdef CONFIG_IXGBE_DCB
4408static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4409{
4410 bool ret = false;
4411 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4412 int i, q;
4413
4414 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4415 return ret;
4416
4417 f->indices = 0;
4418 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4419 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4420 f->indices += q;
0331a832
YZ		 4421 }
4422
e5b64635
JF		 4423 f->mask = 0x7 << 3;
4424 adapter->num_rx_queues = f->indices;
4425 adapter->num_tx_queues = f->indices;
4426 ret = true;
4427
4428#ifdef IXGBE_FCOE
4429 /* FCoE enabled queues require special configuration done through
4430 * configure_fcoe() and others. Here we map FCoE indices onto the
4431 * DCB queue pairs allowing FCoE to own configuration later.
4432 */
4433 ixgbe_set_fcoe_queues(adapter);
4434#endif
4435
0331a832
YZ		 4436 return ret;
4437}
e5b64635 4438#endif
0331a832 4439
1cdd1ec8
GR		 4440/**
4441 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4442 * @adapter: board private structure to initialize
4443 *
4444 * IOV doesn't actually use anything, so just NAK the
4445 * request for now and let the other queue routines
4446 * figure out what to do.
4447 */
4448static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4449{
4450 return false;
4451}
4452
4df10466 4453/*
25985edc 4454 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4455 * @adapter: board private structure to initialize
4456 *
4457 * This is the top level queue allocation routine. The order here is very
4458 * important, starting with the "most" number of features turned on at once,
4459 * and ending with the smallest set of features. This way large combinations
4460 * can be allocated if they're turned on, and smaller combinations are the
4461 * fallthrough conditions.
4462 *
4463 **/
847f53ff 4464static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4465{
1cdd1ec8
GR		 4466 /* Start with base case */
4467 adapter->num_rx_queues = 1;
4468 adapter->num_tx_queues = 1;
4469 adapter->num_rx_pools = adapter->num_rx_queues;
4470 adapter->num_rx_queues_per_pool = 1;
4471
4472 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4473 goto done;
1cdd1ec8 4474
bc97114d
PWJ		 4475#ifdef CONFIG_IXGBE_DCB
4476 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4477 goto done;
bc97114d
PWJ		 4478
4479#endif
e5b64635
JF		 4480#ifdef IXGBE_FCOE
4481 if (ixgbe_set_fcoe_queues(adapter))
4482 goto done;
4483
4484#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4485 if (ixgbe_set_fdir_queues(adapter))
4486 goto done;
4487
bc97114d 4488 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4489 goto done;
4490
4491 /* fallback to base case */
4492 adapter->num_rx_queues = 1;
4493 adapter->num_tx_queues = 1;
4494
4495done:
847f53ff 4496 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4497 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4498 return netif_set_real_num_rx_queues(adapter->netdev,
4499 adapter->num_rx_queues);
b9804972
JB		 4500}
4501
021230d4 4502static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4503 int vectors)
021230d4
AV		 4504{
4505 int err, vector_threshold;
4506
4507 /* We'll want at least 3 (vector_threshold):
4508 * 1) TxQ[0] Cleanup
4509 * 2) RxQ[0] Cleanup
4510 * 3) Other (Link Status Change, etc.)
4511 * 4) TCP Timer (optional)
4512 */
4513 vector_threshold = MIN_MSIX_COUNT;
4514
4515 /* The more we get, the more we will assign to Tx/Rx Cleanup
4516 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4517 * Right now, we simply care about how many we'll get; we'll
4518 * set them up later while requesting irq's.
4519 */
4520 while (vectors >= vector_threshold) {
4521 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4522 vectors);
021230d4
AV		 4523 if (!err) /* Success in acquiring all requested vectors. */
4524 break;
4525 else if (err < 0)
4526 vectors = 0; /* Nasty failure, quit now */
4527 else /* err == number of vectors we should try again with */
4528 vectors = err;
4529 }
4530
4531 if (vectors < vector_threshold) {
4532 /* Can't allocate enough MSI-X interrupts? Oh well.
4533 * This just means we'll go with either a single MSI
4534 * vector or fall back to legacy interrupts.
4535 */
849c4542
ET		 4536 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4537 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4538 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4539 kfree(adapter->msix_entries);
4540 adapter->msix_entries = NULL;
021230d4
AV		 4541 } else {
4542 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4543 /*
4544 * Adjust for only the vectors we'll use, which is minimum
4545 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4546 * vectors we were allocated.
4547 */
4548 adapter->num_msix_vectors = min(vectors,
e8e9f696 4549 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4550 }
4551}
4552
021230d4 4553/**
bc97114d 4554 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4555 * @adapter: board private structure to initialize
4556 *
bc97114d
PWJ		 4557 * Cache the descriptor ring offsets for RSS to the assigned rings.
4558 *
021230d4 4559 **/
bc97114d 4560static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4561{
bc97114d 4562 int i;
bc97114d 4563
9d6b758f
AD		 4564 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4565 return false;
bc97114d 4566
9d6b758f
AD		 4567 for (i = 0; i < adapter->num_rx_queues; i++)
4568 adapter->rx_ring[i]->reg_idx = i;
4569 for (i = 0; i < adapter->num_tx_queues; i++)
4570 adapter->tx_ring[i]->reg_idx = i;
4571
4572 return true;
bc97114d
PWJ		 4573}
4574
4575#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4576
4577/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4578static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4579 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4580{
4581 struct net_device *dev = adapter->netdev;
4582 struct ixgbe_hw *hw = &adapter->hw;
4583 u8 num_tcs = netdev_get_num_tc(dev);
4584
4585 *tx = 0;
4586 *rx = 0;
4587
4588 switch (hw->mac.type) {
4589 case ixgbe_mac_82598EB:
4590 *tx = tc << 3;
4591 *rx = tc << 2;
4592 break;
4593 case ixgbe_mac_82599EB:
4594 case ixgbe_mac_X540:
4595 if (num_tcs == 8) {
4596 if (tc < 3) {
4597 *tx = tc << 5;
4598 *rx = tc << 4;
4599 } else if (tc < 5) {
4600 *tx = ((tc + 2) << 4);
4601 *rx = tc << 4;
4602 } else if (tc < num_tcs) {
4603 *tx = ((tc + 8) << 3);
4604 *rx = tc << 4;
4605 }
4606 } else if (num_tcs == 4) {
4607 *rx = tc << 5;
4608 switch (tc) {
4609 case 0:
4610 *tx = 0;
4611 break;
4612 case 1:
4613 *tx = 64;
4614 break;
4615 case 2:
4616 *tx = 96;
4617 break;
4618 case 3:
4619 *tx = 112;
4620 break;
4621 default:
4622 break;
4623 }
4624 }
4625 break;
4626 default:
4627 break;
4628 }
4629}
4630
4631#define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4632
4633/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4634 * classes.
4635 *
4636 * @netdev: net device to configure
4637 * @tc: number of traffic classes to enable
4638 */
4639int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4640{
4641 int i;
4642 unsigned int q, offset = 0;
4643
4644 if (!tc) {
4645 netdev_reset_tc(dev);
4646 } else {
24095aa3
JF		 4647 struct ixgbe_adapter *adapter = netdev_priv(dev);
4648
4649 /* Hardware supports up to 8 traffic classes */
4650 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
e5b64635
JF		 4651 return -EINVAL;
4652
4653 /* Partition Tx queues evenly amongst traffic classes */
4654 for (i = 0; i < tc; i++) {
4655 q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4656 netdev_set_prio_tc_map(dev, i, i);
4657 netdev_set_tc_queue(dev, i, q, offset);
4658 offset += q;
4659 }
24095aa3
JF		 4660
4661 /* This enables multiple traffic class support in the hardware
4662 * which defaults to strict priority transmission by default.
4663 * If traffic classes are already enabled perhaps through DCB
4664 * code path then existing configuration will be used.
4665 */
4666 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4667 dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4668 struct ieee_ets ets = {
4669 .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4670 };
4671 u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4672
4673 dev->dcbnl_ops->setdcbx(dev, mode);
4674 dev->dcbnl_ops->ieee_setets(dev, &ets);
4675 }
e5b64635
JF		 4676 }
4677 return 0;
4678}
4679
bc97114d
PWJ		 4680/**
4681 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4682 * @adapter: board private structure to initialize
4683 *
4684 * Cache the descriptor ring offsets for DCB to the assigned rings.
4685 *
4686 **/
4687static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4688{
e5b64635
JF		 4689 struct net_device *dev = adapter->netdev;
4690 int i, j, k;
4691 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4692
bd508178
AD		 4693 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4694 return false;
f92ef202 4695
e5b64635
JF		 4696 for (i = 0, k = 0; i < num_tcs; i++) {
4697 unsigned int tx_s, rx_s;
4698 u16 count = dev->tc_to_txq[i].count;
4699
4700 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4701 for (j = 0; j < count; j++, k++) {
4702 adapter->tx_ring[k]->reg_idx = tx_s + j;
4703 adapter->rx_ring[k]->reg_idx = rx_s + j;
4704 adapter->tx_ring[k]->dcb_tc = i;
4705 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4706 }
021230d4 4707 }
e5b64635
JF		 4708
4709 return true;
bc97114d
PWJ		 4710}
4711#endif
4712
c4cf55e5
PWJ		 4713/**
4714 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4715 * @adapter: board private structure to initialize
4716 *
4717 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4718 *
4719 **/
e8e9f696 4720static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4721{
4722 int i;
4723 bool ret = false;
4724
4725 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4726 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4727 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4728 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4729 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4730 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4731 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4732 ret = true;
4733 }
4734
4735 return ret;
4736}
4737
0331a832
YZ		 4738#ifdef IXGBE_FCOE
4739/**
4740 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4741 * @adapter: board private structure to initialize
4742 *
4743 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4744 *
4745 */
4746static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4747{
0331a832 4748 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4749 int i;
4750 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4751
4752 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4753 return false;
0331a832 4754
bf29ee6c
AD		 4755 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4756 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4757 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4758 ixgbe_cache_ring_fdir(adapter);
4759 else
4760 ixgbe_cache_ring_rss(adapter);
8faa2a78 4761
bf29ee6c
AD		 4762 fcoe_rx_i = f->mask;
4763 fcoe_tx_i = f->mask;
0331a832 4764 }
bf29ee6c
AD		 4765 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4766 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4767 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4768 }
4769 return true;
0331a832
YZ		 4770}
4771
4772#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4773/**
4774 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4775 * @adapter: board private structure to initialize
4776 *
4777 * SR-IOV doesn't use any descriptor rings but changes the default if
4778 * no other mapping is used.
4779 *
4780 */
4781static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4782{
4a0b9ca0
PW		 4783 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4784 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4785 if (adapter->num_vfs)
4786 return true;
4787 else
4788 return false;
4789}
4790
bc97114d
PWJ		 4791/**
4792 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4793 * @adapter: board private structure to initialize
4794 *
4795 * Once we know the feature-set enabled for the device, we'll cache
4796 * the register offset the descriptor ring is assigned to.
4797 *
4798 * Note, the order the various feature calls is important. It must start with
4799 * the "most" features enabled at the same time, then trickle down to the
4800 * least amount of features turned on at once.
4801 **/
4802static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4803{
4804 /* start with default case */
4a0b9ca0
PW		 4805 adapter->rx_ring[0]->reg_idx = 0;
4806 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4807
1cdd1ec8
GR		 4808 if (ixgbe_cache_ring_sriov(adapter))
4809 return;
4810
e5b64635
JF		 4811#ifdef CONFIG_IXGBE_DCB
4812 if (ixgbe_cache_ring_dcb(adapter))
4813 return;
4814#endif
4815
0331a832
YZ		 4816#ifdef IXGBE_FCOE
4817 if (ixgbe_cache_ring_fcoe(adapter))
4818 return;
0331a832 4819#endif /* IXGBE_FCOE */
bc97114d 4820
c4cf55e5
PWJ		 4821 if (ixgbe_cache_ring_fdir(adapter))
4822 return;
4823
bc97114d
PWJ		 4824 if (ixgbe_cache_ring_rss(adapter))
4825 return;
021230d4
AV		 4826}
4827
9a799d71
AK		 4828/**
4829 * ixgbe_alloc_queues - Allocate memory for all rings
4830 * @adapter: board private structure to initialize
4831 *
4832 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4833 * number of queues at compile-time. The polling_netdev array is
4834 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4835 **/
2f90b865 4836static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4837{
e2ddeba9 4838 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4839
e2ddeba9
ED		 4840 if (nid < 0 || !node_online(nid))
4841 nid = first_online_node;
4842
4843 for (; tx < adapter->num_tx_queues; tx++) {
4844 struct ixgbe_ring *ring;
4845
4846 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4847 if (!ring)
e2ddeba9 4848 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4849 if (!ring)
e2ddeba9 4850 goto err_allocation;
4a0b9ca0 4851 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4852 ring->queue_index = tx;
4853 ring->numa_node = nid;
b6ec895e 4854 ring->dev = &adapter->pdev->dev;
fc77dc3c 4855 ring->netdev = adapter->netdev;
4a0b9ca0 4856
e2ddeba9 4857 adapter->tx_ring[tx] = ring;
021230d4 4858 }
b9804972 4859
e2ddeba9
ED		 4860 for (; rx < adapter->num_rx_queues; rx++) {
4861 struct ixgbe_ring *ring;
4a0b9ca0 4862
e2ddeba9 4863 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4864 if (!ring)
e2ddeba9 4865 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4866 if (!ring)
e2ddeba9
ED		 4867 goto err_allocation;
4868 ring->count = adapter->rx_ring_count;
4869 ring->queue_index = rx;
4870 ring->numa_node = nid;
b6ec895e 4871 ring->dev = &adapter->pdev->dev;
fc77dc3c 4872 ring->netdev = adapter->netdev;
4a0b9ca0 4873
e2ddeba9 4874 adapter->rx_ring[rx] = ring;
021230d4
AV		 4875 }
4876
4877 ixgbe_cache_ring_register(adapter);
4878
4879 return 0;
4880
e2ddeba9
ED		 4881err_allocation:
4882 while (tx)
4883 kfree(adapter->tx_ring[--tx]);
4884
4885 while (rx)
4886 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4887 return -ENOMEM;
4888}
4889
4890/**
4891 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4892 * @adapter: board private structure to initialize
4893 *
4894 * Attempt to configure the interrupts using the best available
4895 * capabilities of the hardware and the kernel.
4896 **/
feea6a57 4897static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4898{
8be0e467 4899 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4900 int err = 0;
4901 int vector, v_budget;
4902
4903 /*
4904 * It's easy to be greedy for MSI-X vectors, but it really
4905 * doesn't do us much good if we have a lot more vectors
4906 * than CPU's. So let's be conservative and only ask for
342bde1b 4907 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4908 */
4909 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4910 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4911
4912 /*
4913 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4914 * hw.mac->max_msix_vectors vectors. With features
4915 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4916 * descriptor queues supported by our device. Thus, we cap it off in
4917 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4918 */
8be0e467 4919 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4920
4921 /* A failure in MSI-X entry allocation isn't fatal, but it does
4922 * mean we disable MSI-X capabilities of the adapter. */
4923 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4924 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4925 if (adapter->msix_entries) {
4926 for (vector = 0; vector < v_budget; vector++)
4927 adapter->msix_entries[vector].entry = vector;
021230d4 4928
7a921c93 4929 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4930
7a921c93
AD		 4931 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4932 goto out;
4933 }
26d27844 4934
7a921c93
AD		 4935 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4936 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
45b9f509
AD		 4937 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4938 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4939 e_err(probe,
4940 "Flow Director is not supported while multiple "
4941 "queues are disabled. Disabling Flow Director\n");
4942 }
c4cf55e5
PWJ		 4943 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4944 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4945 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4946 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4947 ixgbe_disable_sriov(adapter);
4948
847f53ff
BH		 4949 err = ixgbe_set_num_queues(adapter);
4950 if (err)
4951 return err;
021230d4 4952
021230d4
AV		 4953 err = pci_enable_msi(adapter->pdev);
4954 if (!err) {
4955 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4956 } else {
849c4542
ET		 4957 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4958 "Unable to allocate MSI interrupt, "
4959 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4960 /* reset err */
4961 err = 0;
4962 }
4963
4964out:
021230d4
AV		 4965 return err;
4966}
4967
7a921c93
AD		 4968/**
4969 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4970 * @adapter: board private structure to initialize
4971 *
4972 * We allocate one q_vector per queue interrupt. If allocation fails we
4973 * return -ENOMEM.
4974 **/
4975static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4976{
4977 int q_idx, num_q_vectors;
4978 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4979 int (*poll)(struct napi_struct *, int);
4980
4981 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4982 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4983 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4984 } else {
4985 num_q_vectors = 1;
7a921c93
AD		 4986 poll = &ixgbe_poll;
4987 }
4988
4989 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4990 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4991 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4992 if (!q_vector)
4993 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4994 GFP_KERNEL);
7a921c93
AD		 4995 if (!q_vector)
4996 goto err_out;
4997 q_vector->adapter = adapter;
f7554a2b
NS		 4998 if (q_vector->txr_count && !q_vector->rxr_count)
4999 q_vector->eitr = adapter->tx_eitr_param;
5000 else
5001 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 5002 q_vector->v_idx = q_idx;
91281fd3 5003 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 5004 adapter->q_vector[q_idx] = q_vector;
5005 }
5006
5007 return 0;
5008
5009err_out:
5010 while (q_idx) {
5011 q_idx--;
5012 q_vector = adapter->q_vector[q_idx];
5013 netif_napi_del(&q_vector->napi);
5014 kfree(q_vector);
5015 adapter->q_vector[q_idx] = NULL;
5016 }
5017 return -ENOMEM;
5018}
5019
5020/**
5021 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5022 * @adapter: board private structure to initialize
5023 *
5024 * This function frees the memory allocated to the q_vectors. In addition if
5025 * NAPI is enabled it will delete any references to the NAPI struct prior
5026 * to freeing the q_vector.
5027 **/
5028static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5029{
5030 int q_idx, num_q_vectors;
7a921c93 5031
91281fd3 5032 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 5033 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5034 else
7a921c93 5035 num_q_vectors = 1;
7a921c93
AD		 5036
5037 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5038 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 5039 adapter->q_vector[q_idx] = NULL;
91281fd3 5040 netif_napi_del(&q_vector->napi);
7a921c93
AD		 5041 kfree(q_vector);
5042 }
5043}
5044
7b25cdba 5045static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5046{
5047 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5048 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5049 pci_disable_msix(adapter->pdev);
5050 kfree(adapter->msix_entries);
5051 adapter->msix_entries = NULL;
5052 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5053 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5054 pci_disable_msi(adapter->pdev);
5055 }
021230d4
AV		 5056}
5057
5058/**
5059 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5060 * @adapter: board private structure to initialize
5061 *
5062 * We determine which interrupt scheme to use based on...
5063 * - Kernel support (MSI, MSI-X)
5064 * - which can be user-defined (via MODULE_PARAM)
5065 * - Hardware queue count (num_*_queues)
5066 * - defined by miscellaneous hardware support/features (RSS, etc.)
5067 **/
2f90b865 5068int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5069{
5070 int err;
5071
5072 /* Number of supported queues */
847f53ff
BH		 5073 err = ixgbe_set_num_queues(adapter);
5074 if (err)
5075 return err;
021230d4 5076
021230d4
AV		 5077 err = ixgbe_set_interrupt_capability(adapter);
5078 if (err) {
849c4542 5079 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5080 goto err_set_interrupt;
9a799d71
AK		 5081 }
5082
7a921c93
AD		 5083 err = ixgbe_alloc_q_vectors(adapter);
5084 if (err) {
849c4542 5085 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5086 goto err_alloc_q_vectors;
5087 }
5088
5089 err = ixgbe_alloc_queues(adapter);
5090 if (err) {
849c4542 5091 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5092 goto err_alloc_queues;
5093 }
5094
849c4542 5095 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5096 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5097 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5098
5099 set_bit(__IXGBE_DOWN, &adapter->state);
5100
9a799d71 5101 return 0;
021230d4 5102
7a921c93
AD		 5103err_alloc_queues:
5104 ixgbe_free_q_vectors(adapter);
5105err_alloc_q_vectors:
5106 ixgbe_reset_interrupt_capability(adapter);
021230d4 5107err_set_interrupt:
7a921c93
AD		 5108 return err;
5109}
5110
1a51502b
ED		 5111static void ring_free_rcu(struct rcu_head *head)
5112{
5113 kfree(container_of(head, struct ixgbe_ring, rcu));
5114}
5115
7a921c93
AD		 5116/**
5117 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5118 * @adapter: board private structure to clear interrupt scheme on
5119 *
5120 * We go through and clear interrupt specific resources and reset the structure
5121 * to pre-load conditions
5122 **/
5123void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5124{
4a0b9ca0
PW		 5125 int i;
5126
5127 for (i = 0; i < adapter->num_tx_queues; i++) {
5128 kfree(adapter->tx_ring[i]);
5129 adapter->tx_ring[i] = NULL;
5130 }
5131 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5132 struct ixgbe_ring *ring = adapter->rx_ring[i];
5133
5134 /* ixgbe_get_stats64() might access this ring, we must wait
5135 * a grace period before freeing it.
5136 */
5137 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 5138 adapter->rx_ring[i] = NULL;
5139 }
7a921c93 5140
b8eb3a10
DS		 5141 adapter->num_tx_queues = 0;
5142 adapter->num_rx_queues = 0;
5143
7a921c93
AD		 5144 ixgbe_free_q_vectors(adapter);
5145 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5146}
5147
c4900be0
DS		 5148/**
5149 * ixgbe_sfp_timer - worker thread to find a missing module
5150 * @data: pointer to our adapter struct
5151 **/
5152static void ixgbe_sfp_timer(unsigned long data)
5153{
5154 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5155
4df10466
JB		 5156 /*
5157 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 5158 * delays that sfp+ detection requires
5159 */
5160 schedule_work(&adapter->sfp_task);
5161}
5162
5163/**
5164 * ixgbe_sfp_task - worker thread to find a missing module
5165 * @work: pointer to work_struct containing our data
5166 **/
5167static void ixgbe_sfp_task(struct work_struct *work)
5168{
5169 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5170 struct ixgbe_adapter,
5171 sfp_task);
c4900be0
DS		 5172 struct ixgbe_hw *hw = &adapter->hw;
5173
5174 if ((hw->phy.type == ixgbe_phy_nl) &&
5175 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5176 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5177 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 5178 goto reschedule;
5179 ret = hw->phy.ops.reset(hw);
5180 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5181 e_dev_err("failed to initialize because an unsupported "
5182 "SFP+ module type was detected.\n");
5183 e_dev_err("Reload the driver after installing a "
5184 "supported module.\n");
c4900be0
DS		 5185 unregister_netdev(adapter->netdev);
5186 } else {
396e799c 5187 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 5188 }
5189 /* don't need this routine any more */
5190 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5191 }
5192 return;
5193reschedule:
5194 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5195 mod_timer(&adapter->sfp_timer,
e8e9f696 5196 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 5197}
5198
9a799d71
AK		 5199/**
5200 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5201 * @adapter: board private structure to initialize
5202 *
5203 * ixgbe_sw_init initializes the Adapter private data structure.
5204 * Fields are initialized based on PCI device information and
5205 * OS network device settings (MTU size).
5206 **/
5207static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5208{
5209 struct ixgbe_hw *hw = &adapter->hw;
5210 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5211 struct net_device *dev = adapter->netdev;
021230d4 5212 unsigned int rss;
7a6b6f51 5213#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5214 int j;
5215 struct tc_configuration *tc;
5216#endif
16b61beb 5217 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5218
c44ade9e
JB		 5219 /* PCI config space info */
5220
5221 hw->vendor_id = pdev->vendor;
5222 hw->device_id = pdev->device;
5223 hw->revision_id = pdev->revision;
5224 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5225 hw->subsystem_device_id = pdev->subsystem_device;
5226
021230d4
AV		 5227 /* Set capability flags */
5228 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5229 adapter->ring_feature[RING_F_RSS].indices = rss;
5230 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 5231 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bd508178
AD		 5232 switch (hw->mac.type) {
5233 case ixgbe_mac_82598EB:
bf069c97
DS		 5234 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5235 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5236 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5237 break;
5238 case ixgbe_mac_82599EB:
b93a2226 5239 case ixgbe_mac_X540:
e8e26350 5240 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5241 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5242 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5243 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5244 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5245 /* n-tuple support exists, always init our spinlock */
5246 spin_lock_init(&adapter->fdir_perfect_lock);
5247 /* Flow Director hash filters enabled */
5248 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5249 adapter->atr_sample_rate = 20;
c4cf55e5 5250 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5251 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 5252 adapter->fdir_pballoc = 0;
eacd73f7 5253#ifdef IXGBE_FCOE
0d551589
YZ		 5254 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5255 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5256 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5257#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 5258 /* Default traffic class to use for FCoE */
5259 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 5260 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5261#endif
eacd73f7 5262#endif /* IXGBE_FCOE */
bd508178
AD		 5263 break;
5264 default:
5265 break;
f8212f97 5266 }
2f90b865 5267
7a6b6f51 5268#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5269 /* Configure DCB traffic classes */
5270 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5271 tc = &adapter->dcb_cfg.tc_config[j];
5272 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5273 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5274 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5275 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5276 tc->dcb_pfc = pfc_disabled;
5277 }
5278 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5279 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5280 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 5281 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5282 adapter->dcb_set_bitmap = 0x00;
3032309b 5283 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5284 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5285 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5286
5287#endif
9a799d71
AK		 5288
5289 /* default flow control settings */
cd7664f6 5290 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5291 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5292#ifdef CONFIG_DCB
5293 adapter->last_lfc_mode = hw->fc.current_mode;
5294#endif
16b61beb
JF		 5295 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5296 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5297 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5298 hw->fc.send_xon = true;
71fd570b 5299 hw->fc.disable_fc_autoneg = false;
9a799d71 5300
30efa5a3 5301 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5302 adapter->rx_itr_setting = 1;
5303 adapter->rx_eitr_param = 20000;
5304 adapter->tx_itr_setting = 1;
5305 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5306
5307 /* set defaults for eitr in MegaBytes */
5308 adapter->eitr_low = 10;
5309 adapter->eitr_high = 20;
5310
5311 /* set default ring sizes */
5312 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5313 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5314
9a799d71 5315 /* initialize eeprom parameters */
c44ade9e 5316 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5317 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5318 return -EIO;
5319 }
5320
021230d4 5321 /* enable rx csum by default */
9a799d71
AK		 5322 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5323
1a6c14a2
JB		 5324 /* get assigned NUMA node */
5325 adapter->node = dev_to_node(&pdev->dev);
5326
9a799d71
AK		 5327 set_bit(__IXGBE_DOWN, &adapter->state);
5328
5329 return 0;
5330}
5331
5332/**
5333 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5334 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5335 *
5336 * Return 0 on success, negative on failure
5337 **/
b6ec895e 5338int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5339{
b6ec895e 5340 struct device *dev = tx_ring->dev;
9a799d71
AK		 5341 int size;
5342
3a581073 5343 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5344 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5345 if (!tx_ring->tx_buffer_info)
89bf67f1 5346 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5347 if (!tx_ring->tx_buffer_info)
5348 goto err;
9a799d71
AK		 5349
5350 /* round up to nearest 4K */
12207e49 5351 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5352 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5353
b6ec895e 5354 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5355 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5356 if (!tx_ring->desc)
5357 goto err;
9a799d71 5358
3a581073
JB		 5359 tx_ring->next_to_use = 0;
5360 tx_ring->next_to_clean = 0;
5361 tx_ring->work_limit = tx_ring->count;
9a799d71 5362 return 0;
e01c31a5
JB		 5363
5364err:
5365 vfree(tx_ring->tx_buffer_info);
5366 tx_ring->tx_buffer_info = NULL;
b6ec895e 5367 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5368 return -ENOMEM;
9a799d71
AK		 5369}
5370
69888674
AD		 5371/**
5372 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5373 * @adapter: board private structure
5374 *
5375 * If this function returns with an error, then it's possible one or
5376 * more of the rings is populated (while the rest are not). It is the
5377 * callers duty to clean those orphaned rings.
5378 *
5379 * Return 0 on success, negative on failure
5380 **/
5381static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5382{
5383 int i, err = 0;
5384
5385 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5386 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5387 if (!err)
5388 continue;
396e799c 5389 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5390 break;
5391 }
5392
5393 return err;
5394}
5395
9a799d71
AK		 5396/**
5397 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5398 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5399 *
5400 * Returns 0 on success, negative on failure
5401 **/
b6ec895e 5402int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5403{
b6ec895e 5404 struct device *dev = rx_ring->dev;
021230d4 5405 int size;
9a799d71 5406
3a581073 5407 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5408 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5409 if (!rx_ring->rx_buffer_info)
89bf67f1 5410 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5411 if (!rx_ring->rx_buffer_info)
5412 goto err;
9a799d71 5413
9a799d71 5414 /* Round up to nearest 4K */
3a581073
JB		 5415 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5416 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5417
b6ec895e 5418 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5419 &rx_ring->dma, GFP_KERNEL);
9a799d71 5420
b6ec895e
AD		 5421 if (!rx_ring->desc)
5422 goto err;
9a799d71 5423
3a581073
JB		 5424 rx_ring->next_to_clean = 0;
5425 rx_ring->next_to_use = 0;
9a799d71
AK		 5426
5427 return 0;
b6ec895e
AD		 5428err:
5429 vfree(rx_ring->rx_buffer_info);
5430 rx_ring->rx_buffer_info = NULL;
5431 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5432 return -ENOMEM;
9a799d71
AK		 5433}
5434
69888674
AD		 5435/**
5436 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5437 * @adapter: board private structure
5438 *
5439 * If this function returns with an error, then it's possible one or
5440 * more of the rings is populated (while the rest are not). It is the
5441 * callers duty to clean those orphaned rings.
5442 *
5443 * Return 0 on success, negative on failure
5444 **/
69888674
AD		 5445static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5446{
5447 int i, err = 0;
5448
5449 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5450 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5451 if (!err)
5452 continue;
396e799c 5453 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5454 break;
5455 }
5456
5457 return err;
5458}
5459
9a799d71
AK		 5460/**
5461 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5462 * @tx_ring: Tx descriptor ring for a specific queue
5463 *
5464 * Free all transmit software resources
5465 **/
b6ec895e 5466void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5467{
b6ec895e 5468 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5469
5470 vfree(tx_ring->tx_buffer_info);
5471 tx_ring->tx_buffer_info = NULL;
5472
b6ec895e
AD		 5473 /* if not set, then don't free */
5474 if (!tx_ring->desc)
5475 return;
5476
5477 dma_free_coherent(tx_ring->dev, tx_ring->size,
5478 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5479
5480 tx_ring->desc = NULL;
5481}
5482
5483/**
5484 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5485 * @adapter: board private structure
5486 *
5487 * Free all transmit software resources
5488 **/
5489static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5490{
5491 int i;
5492
5493 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5494 if (adapter->tx_ring[i]->desc)
b6ec895e 5495 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5496}
5497
5498/**
b4617240 5499 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5500 * @rx_ring: ring to clean the resources from
5501 *
5502 * Free all receive software resources
5503 **/
b6ec895e 5504void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5505{
b6ec895e 5506 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5507
5508 vfree(rx_ring->rx_buffer_info);
5509 rx_ring->rx_buffer_info = NULL;
5510
b6ec895e
AD		 5511 /* if not set, then don't free */
5512 if (!rx_ring->desc)
5513 return;
5514
5515 dma_free_coherent(rx_ring->dev, rx_ring->size,
5516 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5517
5518 rx_ring->desc = NULL;
5519}
5520
5521/**
5522 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5523 * @adapter: board private structure
5524 *
5525 * Free all receive software resources
5526 **/
5527static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5528{
5529 int i;
5530
5531 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5532 if (adapter->rx_ring[i]->desc)
b6ec895e 5533 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5534}
5535
9a799d71
AK		 5536/**
5537 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5538 * @netdev: network interface device structure
5539 * @new_mtu: new value for maximum frame size
5540 *
5541 * Returns 0 on success, negative on failure
5542 **/
5543static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5544{
5545 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5546 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5547 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5548
42c783c5 5549 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5550 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5551 hw->mac.type != ixgbe_mac_X540) {
5552 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5553 return -EINVAL;
5554 } else {
5555 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5556 return -EINVAL;
5557 }
9a799d71 5558
396e799c 5559 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5560 /* must set new MTU before calling down or up */
9a799d71
AK		 5561 netdev->mtu = new_mtu;
5562
16b61beb
JF		 5563 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5564 hw->fc.low_water = FC_LOW_WATER(max_frame);
5565
d4f80882
AV		 5566 if (netif_running(netdev))
5567 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5568
5569 return 0;
5570}
5571
5572/**
5573 * ixgbe_open - Called when a network interface is made active
5574 * @netdev: network interface device structure
5575 *
5576 * Returns 0 on success, negative value on failure
5577 *
5578 * The open entry point is called when a network interface is made
5579 * active by the system (IFF_UP). At this point all resources needed
5580 * for transmit and receive operations are allocated, the interrupt
5581 * handler is registered with the OS, the watchdog timer is started,
5582 * and the stack is notified that the interface is ready.
5583 **/
5584static int ixgbe_open(struct net_device *netdev)
5585{
5586 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5587 int err;
4bebfaa5
AK		 5588
5589 /* disallow open during test */
5590 if (test_bit(__IXGBE_TESTING, &adapter->state))
5591 return -EBUSY;
9a799d71 5592
54386467
JB		 5593 netif_carrier_off(netdev);
5594
9a799d71
AK		 5595 /* allocate transmit descriptors */
5596 err = ixgbe_setup_all_tx_resources(adapter);
5597 if (err)
5598 goto err_setup_tx;
5599
9a799d71
AK		 5600 /* allocate receive descriptors */
5601 err = ixgbe_setup_all_rx_resources(adapter);
5602 if (err)
5603 goto err_setup_rx;
5604
5605 ixgbe_configure(adapter);
5606
021230d4 5607 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5608 if (err)
5609 goto err_req_irq;
5610
9a799d71
AK		 5611 err = ixgbe_up_complete(adapter);
5612 if (err)
5613 goto err_up;
5614
d55b53ff
JK		 5615 netif_tx_start_all_queues(netdev);
5616
9a799d71
AK		 5617 return 0;
5618
5619err_up:
5eba3699 5620 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5621 ixgbe_free_irq(adapter);
5622err_req_irq:
9a799d71 5623err_setup_rx:
a20a1199 5624 ixgbe_free_all_rx_resources(adapter);
9a799d71 5625err_setup_tx:
a20a1199 5626 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5627 ixgbe_reset(adapter);
5628
5629 return err;
5630}
5631
5632/**
5633 * ixgbe_close - Disables a network interface
5634 * @netdev: network interface device structure
5635 *
5636 * Returns 0, this is not allowed to fail
5637 *
5638 * The close entry point is called when an interface is de-activated
5639 * by the OS. The hardware is still under the drivers control, but
5640 * needs to be disabled. A global MAC reset is issued to stop the
5641 * hardware, and all transmit and receive resources are freed.
5642 **/
5643static int ixgbe_close(struct net_device *netdev)
5644{
5645 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5646
5647 ixgbe_down(adapter);
5648 ixgbe_free_irq(adapter);
5649
5650 ixgbe_free_all_tx_resources(adapter);
5651 ixgbe_free_all_rx_resources(adapter);
5652
5eba3699 5653 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5654
5655 return 0;
5656}
5657
b3c8b4ba
AD		 5658#ifdef CONFIG_PM
5659static int ixgbe_resume(struct pci_dev *pdev)
5660{
c60fbb00
AD		 5661 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5662 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5663 u32 err;
5664
5665 pci_set_power_state(pdev, PCI_D0);
5666 pci_restore_state(pdev);
656ab817
DS		 5667 /*
5668 * pci_restore_state clears dev->state_saved so call
5669 * pci_save_state to restore it.
5670 */
5671 pci_save_state(pdev);
9ce77666 5672
5673 err = pci_enable_device_mem(pdev);
b3c8b4ba 5674 if (err) {
849c4542 5675 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5676 return err;
5677 }
5678 pci_set_master(pdev);
5679
dd4d8ca6 5680 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5681
5682 err = ixgbe_init_interrupt_scheme(adapter);
5683 if (err) {
849c4542 5684 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5685 return err;
5686 }
5687
b3c8b4ba
AD		 5688 ixgbe_reset(adapter);
5689
495dce12
WJP		 5690 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5691
b3c8b4ba 5692 if (netif_running(netdev)) {
c60fbb00 5693 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5694 if (err)
5695 return err;
5696 }
5697
5698 netif_device_attach(netdev);
5699
5700 return 0;
5701}
b3c8b4ba 5702#endif /* CONFIG_PM */
9d8d05ae
RW		 5703
5704static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5705{
c60fbb00
AD		 5706 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5707 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5708 struct ixgbe_hw *hw = &adapter->hw;
5709 u32 ctrl, fctrl;
5710 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5711#ifdef CONFIG_PM
5712 int retval = 0;
5713#endif
5714
5715 netif_device_detach(netdev);
5716
5717 if (netif_running(netdev)) {
5718 ixgbe_down(adapter);
5719 ixgbe_free_irq(adapter);
5720 ixgbe_free_all_tx_resources(adapter);
5721 ixgbe_free_all_rx_resources(adapter);
5722 }
b3c8b4ba 5723
5f5ae6fc 5724 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5725#ifdef CONFIG_DCB
5726 kfree(adapter->ixgbe_ieee_pfc);
5727 kfree(adapter->ixgbe_ieee_ets);
5728#endif
5f5ae6fc 5729
b3c8b4ba
AD		 5730#ifdef CONFIG_PM
5731 retval = pci_save_state(pdev);
5732 if (retval)
5733 return retval;
4df10466 5734
b3c8b4ba 5735#endif
e8e26350
PW		 5736 if (wufc) {
5737 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5738
e8e26350
PW		 5739 /* turn on all-multi mode if wake on multicast is enabled */
5740 if (wufc & IXGBE_WUFC_MC) {
5741 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5742 fctrl |= IXGBE_FCTRL_MPE;
5743 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5744 }
5745
5746 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5747 ctrl |= IXGBE_CTRL_GIO_DIS;
5748 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5749
5750 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5751 } else {
5752 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5753 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5754 }
5755
bd508178
AD		 5756 switch (hw->mac.type) {
5757 case ixgbe_mac_82598EB:
dd4d8ca6 5758 pci_wake_from_d3(pdev, false);
bd508178
AD		 5759 break;
5760 case ixgbe_mac_82599EB:
b93a2226 5761 case ixgbe_mac_X540:
bd508178
AD		 5762 pci_wake_from_d3(pdev, !!wufc);
5763 break;
5764 default:
5765 break;
5766 }
b3c8b4ba 5767
9d8d05ae
RW		 5768 *enable_wake = !!wufc;
5769
b3c8b4ba
AD		 5770 ixgbe_release_hw_control(adapter);
5771
5772 pci_disable_device(pdev);
5773
9d8d05ae
RW		 5774 return 0;
5775}
5776
5777#ifdef CONFIG_PM
5778static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5779{
5780 int retval;
5781 bool wake;
5782
5783 retval = __ixgbe_shutdown(pdev, &wake);
5784 if (retval)
5785 return retval;
5786
5787 if (wake) {
5788 pci_prepare_to_sleep(pdev);
5789 } else {
5790 pci_wake_from_d3(pdev, false);
5791 pci_set_power_state(pdev, PCI_D3hot);
5792 }
b3c8b4ba
AD		 5793
5794 return 0;
5795}
9d8d05ae 5796#endif /* CONFIG_PM */
b3c8b4ba
AD		 5797
5798static void ixgbe_shutdown(struct pci_dev *pdev)
5799{
9d8d05ae
RW		 5800 bool wake;
5801
5802 __ixgbe_shutdown(pdev, &wake);
5803
5804 if (system_state == SYSTEM_POWER_OFF) {
5805 pci_wake_from_d3(pdev, wake);
5806 pci_set_power_state(pdev, PCI_D3hot);
5807 }
b3c8b4ba
AD		 5808}
5809
9a799d71
AK		 5810/**
5811 * ixgbe_update_stats - Update the board statistics counters.
5812 * @adapter: board private structure
5813 **/
5814void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5815{
2d86f139 5816 struct net_device *netdev = adapter->netdev;
9a799d71 5817 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5818 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5819 u64 total_mpc = 0;
5820 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5821 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5822 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5823 u64 bytes = 0, packets = 0;
9a799d71 5824
d08935c2
DS		 5825 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5826 test_bit(__IXGBE_RESETTING, &adapter->state))
5827 return;
5828
94b982b2 5829 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5830 u64 rsc_count = 0;
94b982b2 5831 u64 rsc_flush = 0;
d51019a4
PW		 5832 for (i = 0; i < 16; i++)
5833 adapter->hw_rx_no_dma_resources +=
7ca647bd 5834 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5835 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5836 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5837 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5838 }
5839 adapter->rsc_total_count = rsc_count;
5840 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5841 }
5842
5b7da515
AD		 5843 for (i = 0; i < adapter->num_rx_queues; i++) {
5844 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5845 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5846 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5847 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5848 bytes += rx_ring->stats.bytes;
5849 packets += rx_ring->stats.packets;
5850 }
5851 adapter->non_eop_descs = non_eop_descs;
5852 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5853 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5854 netdev->stats.rx_bytes = bytes;
5855 netdev->stats.rx_packets = packets;
5856
5857 bytes = 0;
5858 packets = 0;
7ca3bc58 5859 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5860 for (i = 0; i < adapter->num_tx_queues; i++) {
5861 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5862 restart_queue += tx_ring->tx_stats.restart_queue;
5863 tx_busy += tx_ring->tx_stats.tx_busy;
5864 bytes += tx_ring->stats.bytes;
5865 packets += tx_ring->stats.packets;
5866 }
eb985f09 5867 adapter->restart_queue = restart_queue;
5b7da515
AD		 5868 adapter->tx_busy = tx_busy;
5869 netdev->stats.tx_bytes = bytes;
5870 netdev->stats.tx_packets = packets;
7ca3bc58 5871
7ca647bd 5872 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5873 for (i = 0; i < 8; i++) {
5874 /* for packet buffers not used, the register should read 0 */
5875 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5876 missed_rx += mpc;
7ca647bd
JP		 5877 hwstats->mpc[i] += mpc;
5878 total_mpc += hwstats->mpc[i];
e8e26350 5879 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5880 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5881 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5882 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5883 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5884 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5885 switch (hw->mac.type) {
5886 case ixgbe_mac_82598EB:
7ca647bd
JP		 5887 hwstats->pxonrxc[i] +=
5888 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5889 break;
5890 case ixgbe_mac_82599EB:
b93a2226 5891 case ixgbe_mac_X540:
bd508178
AD		 5892 hwstats->pxonrxc[i] +=
5893 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5894 break;
5895 default:
5896 break;
e8e26350 5897 }
7ca647bd
JP		 5898 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5899 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5900 }
7ca647bd 5901 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5902 /* work around hardware counting issue */
7ca647bd 5903 hwstats->gprc -= missed_rx;
6f11eef7 5904
c84d324c
JF		 5905 ixgbe_update_xoff_received(adapter);
5906
6f11eef7 5907 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5908 switch (hw->mac.type) {
5909 case ixgbe_mac_82598EB:
5910 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5911 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5912 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5913 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5914 break;
5915 case ixgbe_mac_82599EB:
b93a2226 5916 case ixgbe_mac_X540:
7ca647bd 5917 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5918 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5919 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5920 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5921 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5922 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5923 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5924 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5925 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5926#ifdef IXGBE_FCOE
7ca647bd
JP		 5927 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5928 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5929 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5930 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5931 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5932 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5933#endif /* IXGBE_FCOE */
bd508178
AD		 5934 break;
5935 default:
5936 break;
e8e26350 5937 }
9a799d71 5938 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5939 hwstats->bprc += bprc;
5940 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5941 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5942 hwstats->mprc -= bprc;
5943 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5944 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5945 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5946 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5947 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5948 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5949 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5950 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5951 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5952 hwstats->lxontxc += lxon;
6f11eef7 5953 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5954 hwstats->lxofftxc += lxoff;
5955 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5956 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5957 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5958 /*
5959 * 82598 errata - tx of flow control packets is included in tx counters
5960 */
5961 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5962 hwstats->gptc -= xon_off_tot;
5963 hwstats->mptc -= xon_off_tot;
5964 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5965 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5966 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5967 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5968 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5969 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5970 hwstats->ptc64 -= xon_off_tot;
5971 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5972 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5973 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5974 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5975 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5976 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5977
5978 /* Fill out the OS statistics structure */
7ca647bd 5979 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5980
5981 /* Rx Errors */
7ca647bd 5982 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5983 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5984 netdev->stats.rx_length_errors = hwstats->rlec;
5985 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5986 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5987}
5988
5989/**
5990 * ixgbe_watchdog - Timer Call-back
5991 * @data: pointer to adapter cast into an unsigned long
5992 **/
5993static void ixgbe_watchdog(unsigned long data)
5994{
5995 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5996 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5997 u64 eics = 0;
5998 int i;
cf8280ee 5999
fe49f04a
AD		 6000 /*
6001 * Do the watchdog outside of interrupt context due to the lovely
6002 * delays that some of the newer hardware requires
6003 */
22d5a71b 6004
fe49f04a
AD		 6005 if (test_bit(__IXGBE_DOWN, &adapter->state))
6006 goto watchdog_short_circuit;
22d5a71b 6007
fe49f04a
AD		 6008 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6009 /*
6010 * for legacy and MSI interrupts don't set any bits
6011 * that are enabled for EIAM, because this operation
6012 * would set *both* EIMS and EICS for any bit in EIAM
6013 */
6014 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6015 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6016 goto watchdog_reschedule;
6017 }
6018
6019 /* get one bit for every active tx/rx interrupt vector */
6020 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6021 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6022 if (qv->rxr_count || qv->txr_count)
6023 eics |= ((u64)1 << i);
cf8280ee 6024 }
9a799d71 6025
fe49f04a
AD		 6026 /* Cause software interrupt to ensure rx rings are cleaned */
6027 ixgbe_irq_rearm_queues(adapter, eics);
6028
6029watchdog_reschedule:
6030 /* Reset the timer */
6031 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
6032
6033watchdog_short_circuit:
cf8280ee
JB		 6034 schedule_work(&adapter->watchdog_task);
6035}
6036
e8e26350
PW		 6037/**
6038 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
6039 * @work: pointer to work_struct containing our data
6040 **/
6041static void ixgbe_multispeed_fiber_task(struct work_struct *work)
6042{
6043 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6044 struct ixgbe_adapter,
6045 multispeed_fiber_task);
e8e26350
PW		 6046 struct ixgbe_hw *hw = &adapter->hw;
6047 u32 autoneg;
8620a103 6048 bool negotiation;
e8e26350
PW		 6049
6050 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 6051 autoneg = hw->phy.autoneg_advertised;
6052 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 6053 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 6054 hw->mac.autotry_restart = false;
8620a103
MC		 6055 if (hw->mac.ops.setup_link)
6056 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 6057 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6058 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
6059}
6060
6061/**
6062 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
6063 * @work: pointer to work_struct containing our data
6064 **/
6065static void ixgbe_sfp_config_module_task(struct work_struct *work)
6066{
6067 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6068 struct ixgbe_adapter,
6069 sfp_config_module_task);
e8e26350
PW		 6070 struct ixgbe_hw *hw = &adapter->hw;
6071 u32 err;
6072
6073 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 6074
6075 /* Time for electrical oscillations to settle down */
6076 msleep(100);
e8e26350 6077 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 6078
e8e26350 6079 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6080 e_dev_err("failed to initialize because an unsupported SFP+ "
6081 "module type was detected.\n");
6082 e_dev_err("Reload the driver after installing a supported "
6083 "module.\n");
63d6e1d8 6084 unregister_netdev(adapter->netdev);
e8e26350
PW		 6085 return;
6086 }
4c7e604b
AG		 6087 if (hw->mac.ops.setup_sfp)
6088 hw->mac.ops.setup_sfp(hw);
e8e26350 6089
8d1c3c07 6090 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 6091 /* This will also work for DA Twinax connections */
6092 schedule_work(&adapter->multispeed_fiber_task);
6093 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
6094}
6095
c4cf55e5
PWJ		 6096/**
6097 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
6098 * @work: pointer to work_struct containing our data
6099 **/
6100static void ixgbe_fdir_reinit_task(struct work_struct *work)
6101{
6102 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6103 struct ixgbe_adapter,
6104 fdir_reinit_task);
c4cf55e5
PWJ		 6105 struct ixgbe_hw *hw = &adapter->hw;
6106 int i;
6107
6108 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6109 for (i = 0; i < adapter->num_tx_queues; i++)
7d637bcc
AD		 6110 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6111 &(adapter->tx_ring[i]->state));
c4cf55e5 6112 } else {
396e799c 6113 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 6114 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 6115 }
6116 /* Done FDIR Re-initialization, enable transmits */
6117 netif_tx_start_all_queues(adapter->netdev);
6118}
6119
a985b6c3
GR		 6120static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6121{
6122 u32 ssvpc;
6123
6124 /* Do not perform spoof check for 82598 */
6125 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6126 return;
6127
6128 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6129
6130 /*
6131 * ssvpc register is cleared on read, if zero then no
6132 * spoofed packets in the last interval.
6133 */
6134 if (!ssvpc)
6135 return;
6136
6137 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6138}
6139
10eec955
JF		 6140static DEFINE_MUTEX(ixgbe_watchdog_lock);
6141
cf8280ee 6142/**
69888674
AD		 6143 * ixgbe_watchdog_task - worker thread to bring link up
6144 * @work: pointer to work_struct containing our data
cf8280ee
JB		 6145 **/
6146static void ixgbe_watchdog_task(struct work_struct *work)
6147{
6148 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6149 struct ixgbe_adapter,
6150 watchdog_task);
cf8280ee
JB		 6151 struct net_device *netdev = adapter->netdev;
6152 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 6153 u32 link_speed;
6154 bool link_up;
bc59fcda
NS		 6155 int i;
6156 struct ixgbe_ring *tx_ring;
6157 int some_tx_pending = 0;
cf8280ee 6158
10eec955
JF		 6159 mutex_lock(&ixgbe_watchdog_lock);
6160
6161 link_up = adapter->link_up;
6162 link_speed = adapter->link_speed;
cf8280ee
JB		 6163
6164 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6165 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 6166 if (link_up) {
6167#ifdef CONFIG_DCB
6168 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6169 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 6170 hw->mac.ops.fc_enable(hw, i);
264857b8 6171 } else {
620fa036 6172 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 6173 }
6174#else
620fa036 6175 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 6176#endif
6177 }
6178
cf8280ee
JB		 6179 if (link_up ||
6180 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 6181 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 6182 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 6183 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 6184 }
6185 adapter->link_up = link_up;
6186 adapter->link_speed = link_speed;
6187 }
9a799d71
AK		 6188
6189 if (link_up) {
6190 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 6191 bool flow_rx, flow_tx;
6192
bd508178
AD		 6193 switch (hw->mac.type) {
6194 case ixgbe_mac_82598EB: {
e8e26350
PW		 6195 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6196 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 6197 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6198 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350 6199 }
bd508178 6200 break;
b93a2226
DS		 6201 case ixgbe_mac_82599EB:
6202 case ixgbe_mac_X540: {
bd508178
AD		 6203 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6204 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6205 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6206 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6207 }
6208 break;
6209 default:
6210 flow_tx = false;
6211 flow_rx = false;
6212 break;
6213 }
e8e26350 6214
396e799c 6215 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 6216 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 6217 "10 Gbps" :
6218 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
1b1c0a48
AS		 6219 "1 Gbps" :
6220 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6221 "100 Mbps" :
6222 "unknown speed"))),
e8e26350 6223 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 6224 (flow_rx ? "RX" :
6225 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 6226
6227 netif_carrier_on(netdev);
ff4ab206 6228 ixgbe_check_vf_rate_limit(adapter);
9a799d71
AK		 6229 } else {
6230 /* Force detection of hung controller */
7d637bcc
AD		 6231 for (i = 0; i < adapter->num_tx_queues; i++) {
6232 tx_ring = adapter->tx_ring[i];
6233 set_check_for_tx_hang(tx_ring);
6234 }
9a799d71
AK		 6235 }
6236 } else {
cf8280ee
JB		 6237 adapter->link_up = false;
6238 adapter->link_speed = 0;
9a799d71 6239 if (netif_carrier_ok(netdev)) {
396e799c 6240 e_info(drv, "NIC Link is Down\n");
9a799d71 6241 netif_carrier_off(netdev);
9a799d71
AK		 6242 }
6243 }
6244
bc59fcda
NS		 6245 if (!netif_carrier_ok(netdev)) {
6246 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 6247 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6248 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6249 some_tx_pending = 1;
6250 break;
6251 }
6252 }
6253
6254 if (some_tx_pending) {
6255 /* We've lost link, so the controller stops DMA,
6256 * but we've got queued Tx work that's never going
6257 * to get done, so reset controller to flush Tx.
6258 * (Do the reset outside of interrupt context).
6259 */
6260 schedule_work(&adapter->reset_task);
6261 }
6262 }
6263
a985b6c3 6264 ixgbe_spoof_check(adapter);
9a799d71 6265 ixgbe_update_stats(adapter);
10eec955 6266 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 6267}
6268
9a799d71 6269static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 6270 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 6271 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 6272{
6273 struct ixgbe_adv_tx_context_desc *context_desc;
6274 unsigned int i;
6275 int err;
6276 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 6277 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6278 u32 mss_l4len_idx, l4len;
9a799d71
AK		 6279
6280 if (skb_is_gso(skb)) {
6281 if (skb_header_cloned(skb)) {
6282 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6283 if (err)
6284 return err;
6285 }
6286 l4len = tcp_hdrlen(skb);
6287 *hdr_len += l4len;
6288
5e09a105 6289 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 6290 struct iphdr *iph = ip_hdr(skb);
6291 iph->tot_len = 0;
6292 iph->check = 0;
6293 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 6294 iph->daddr, 0,
6295 IPPROTO_TCP,
6296 0);
8e1e8a47 6297 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 6298 ipv6_hdr(skb)->payload_len = 0;
6299 tcp_hdr(skb)->check =
6300 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 6301 &ipv6_hdr(skb)->daddr,
6302 0, IPPROTO_TCP, 0);
9a799d71
AK		 6303 }
6304
6305 i = tx_ring->next_to_use;
6306
6307 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6308 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6309
6310 /* VLAN MACLEN IPLEN */
6311 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6312 vlan_macip_lens |=
6313 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6314 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6315 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6316 *hdr_len += skb_network_offset(skb);
6317 vlan_macip_lens |=
6318 (skb_transport_header(skb) - skb_network_header(skb));
6319 *hdr_len +=
6320 (skb_transport_header(skb) - skb_network_header(skb));
6321 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6322 context_desc->seqnum_seed = 0;
6323
6324 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6325 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6326 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6327
5e09a105 6328 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6329 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6330 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6331 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6332
6333 /* MSS L4LEN IDX */
9f8cdf4f 6334 mss_l4len_idx =
9a799d71
AK		 6335 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6336 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6337 /* use index 1 for TSO */
6338 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6339 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6340
6341 tx_buffer_info->time_stamp = jiffies;
6342 tx_buffer_info->next_to_watch = i;
6343
6344 i++;
6345 if (i == tx_ring->count)
6346 i = 0;
6347 tx_ring->next_to_use = i;
6348
6349 return true;
6350 }
6351 return false;
6352}
6353
5e09a105
HZ		 6354static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6355 __be16 protocol)
7ca647bd
JP		 6356{
6357 u32 rtn = 0;
7ca647bd
JP		 6358
6359 switch (protocol) {
6360 case cpu_to_be16(ETH_P_IP):
6361 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6362 switch (ip_hdr(skb)->protocol) {
6363 case IPPROTO_TCP:
6364 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6365 break;
6366 case IPPROTO_SCTP:
6367 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6368 break;
6369 }
6370 break;
6371 case cpu_to_be16(ETH_P_IPV6):
6372 /* XXX what about other V6 headers?? */
6373 switch (ipv6_hdr(skb)->nexthdr) {
6374 case IPPROTO_TCP:
6375 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6376 break;
6377 case IPPROTO_SCTP:
6378 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6379 break;
6380 }
6381 break;
6382 default:
6383 if (unlikely(net_ratelimit()))
6384 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6385 protocol);
7ca647bd
JP		 6386 break;
6387 }
6388
6389 return rtn;
6390}
6391
9a799d71 6392static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6393 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6394 struct sk_buff *skb, u32 tx_flags,
6395 __be16 protocol)
9a799d71
AK		 6396{
6397 struct ixgbe_adv_tx_context_desc *context_desc;
6398 unsigned int i;
6399 struct ixgbe_tx_buffer *tx_buffer_info;
6400 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6401
6402 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6403 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6404 i = tx_ring->next_to_use;
6405 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6406 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6407
6408 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6409 vlan_macip_lens |=
6410 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6411 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6412 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6413 if (skb->ip_summed == CHECKSUM_PARTIAL)
6414 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6415 skb_network_header(skb));
9a799d71
AK		 6416
6417 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6418 context_desc->seqnum_seed = 0;
6419
6420 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6421 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6422
7ca647bd 6423 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6424 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6425
6426 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6427 /* use index zero for tx checksum offload */
9a799d71
AK		 6428 context_desc->mss_l4len_idx = 0;
6429
6430 tx_buffer_info->time_stamp = jiffies;
6431 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6432
9a799d71
AK		 6433 i++;
6434 if (i == tx_ring->count)
6435 i = 0;
6436 tx_ring->next_to_use = i;
6437
6438 return true;
6439 }
9f8cdf4f 6440
9a799d71
AK		 6441 return false;
6442}
6443
6444static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6445 struct ixgbe_ring *tx_ring,
6446 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6447 unsigned int first, const u8 hdr_len)
9a799d71 6448{
b6ec895e 6449 struct device *dev = tx_ring->dev;
9a799d71 6450 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6451 unsigned int len;
6452 unsigned int total = skb->len;
9a799d71
AK		 6453 unsigned int offset = 0, size, count = 0, i;
6454 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6455 unsigned int f;
8ad494b0
AD		 6456 unsigned int bytecount = skb->len;
6457 u16 gso_segs = 1;
9a799d71
AK		 6458
6459 i = tx_ring->next_to_use;
6460
eacd73f7
YZ		 6461 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6462 /* excluding fcoe_crc_eof for FCoE */
6463 total -= sizeof(struct fcoe_crc_eof);
6464
6465 len = min(skb_headlen(skb), total);
9a799d71
AK		 6466 while (len) {
6467 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6468 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6469
6470 tx_buffer_info->length = size;
e5a43549 6471 tx_buffer_info->mapped_as_page = false;
b6ec895e 6472 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6473 skb->data + offset,
1b507730 6474 size, DMA_TO_DEVICE);
b6ec895e 6475 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6476 goto dma_error;
9a799d71
AK		 6477 tx_buffer_info->time_stamp = jiffies;
6478 tx_buffer_info->next_to_watch = i;
6479
6480 len -= size;
eacd73f7 6481 total -= size;
9a799d71
AK		 6482 offset += size;
6483 count++;
44df32c5
AD		 6484
6485 if (len) {
6486 i++;
6487 if (i == tx_ring->count)
6488 i = 0;
6489 }
9a799d71
AK		 6490 }
6491
6492 for (f = 0; f < nr_frags; f++) {
6493 struct skb_frag_struct *frag;
6494
6495 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6496 len = min((unsigned int)frag->size, total);
e5a43549 6497 offset = frag->page_offset;
9a799d71
AK		 6498
6499 while (len) {
44df32c5
AD		 6500 i++;
6501 if (i == tx_ring->count)
6502 i = 0;
6503
9a799d71
AK		 6504 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6505 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6506
6507 tx_buffer_info->length = size;
b6ec895e 6508 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6509 frag->page,
6510 offset, size,
1b507730 6511 DMA_TO_DEVICE);
e5a43549 6512 tx_buffer_info->mapped_as_page = true;
b6ec895e 6513 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6514 goto dma_error;
9a799d71
AK		 6515 tx_buffer_info->time_stamp = jiffies;
6516 tx_buffer_info->next_to_watch = i;
6517
6518 len -= size;
eacd73f7 6519 total -= size;
9a799d71
AK		 6520 offset += size;
6521 count++;
9a799d71 6522 }
eacd73f7
YZ		 6523 if (total == 0)
6524 break;
9a799d71 6525 }
44df32c5 6526
8ad494b0
AD		 6527 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6528 gso_segs = skb_shinfo(skb)->gso_segs;
6529#ifdef IXGBE_FCOE
6530 /* adjust for FCoE Sequence Offload */
6531 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6532 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6533 skb_shinfo(skb)->gso_size);
6534#endif /* IXGBE_FCOE */
6535 bytecount += (gso_segs - 1) * hdr_len;
6536
6537 /* multiply data chunks by size of headers */
6538 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6539 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6540 tx_ring->tx_buffer_info[i].skb = skb;
6541 tx_ring->tx_buffer_info[first].next_to_watch = i;
6542
e5a43549
AD		 6543 return count;
6544
6545dma_error:
849c4542 6546 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6547
6548 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6549 tx_buffer_info->dma = 0;
6550 tx_buffer_info->time_stamp = 0;
6551 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6552 if (count)
6553 count--;
e5a43549
AD		 6554
6555 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6556 while (count--) {
e8e9f696 6557 if (i == 0)
e5a43549 6558 i += tx_ring->count;
c1fa347f 6559 i--;
e5a43549 6560 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6561 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6562 }
6563
e44d38e1 6564 return 0;
9a799d71
AK		 6565}
6566
84ea2591 6567static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6568 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6569{
6570 union ixgbe_adv_tx_desc *tx_desc = NULL;
6571 struct ixgbe_tx_buffer *tx_buffer_info;
6572 u32 olinfo_status = 0, cmd_type_len = 0;
6573 unsigned int i;
6574 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6575
6576 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6577
6578 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6579
6580 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6581 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6582
6583 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6584 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6585
6586 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6587 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6588
4eeae6fd
PW		 6589 /* use index 1 context for tso */
6590 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6591 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6592 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6593 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6594
6595 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6596 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6597 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6598
eacd73f7
YZ		 6599 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6600 olinfo_status |= IXGBE_ADVTXD_CC;
6601 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6602 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6603 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6604 }
6605
9a799d71
AK		 6606 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6607
6608 i = tx_ring->next_to_use;
6609 while (count--) {
6610 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6611 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6612 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6613 tx_desc->read.cmd_type_len =
e8e9f696 6614 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6615 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6616 i++;
6617 if (i == tx_ring->count)
6618 i = 0;
6619 }
6620
6621 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6622
6623 /*
6624 * Force memory writes to complete before letting h/w
6625 * know there are new descriptors to fetch. (Only
6626 * applicable for weak-ordered memory model archs,
6627 * such as IA-64).
6628 */
6629 wmb();
6630
6631 tx_ring->next_to_use = i;
84ea2591 6632 writel(i, tx_ring->tail);
9a799d71
AK		 6633}
6634
69830529
AD		 6635static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6636 u32 tx_flags, __be16 protocol)
6637{
6638 struct ixgbe_q_vector *q_vector = ring->q_vector;
6639 union ixgbe_atr_hash_dword input = { .dword = 0 };
6640 union ixgbe_atr_hash_dword common = { .dword = 0 };
6641 union {
6642 unsigned char *network;
6643 struct iphdr *ipv4;
6644 struct ipv6hdr *ipv6;
6645 } hdr;
ee9e0f0b 6646 struct tcphdr *th;
905e4a41 6647 __be16 vlan_id;
c4cf55e5 6648
69830529
AD		 6649 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6650 if (!q_vector)
6651 return;
6652
6653 /* do nothing if sampling is disabled */
6654 if (!ring->atr_sample_rate)
d3ead241 6655 return;
c4cf55e5 6656
69830529 6657 ring->atr_count++;
c4cf55e5 6658
69830529
AD		 6659 /* snag network header to get L4 type and address */
6660 hdr.network = skb_network_header(skb);
6661
6662 /* Currently only IPv4/IPv6 with TCP is supported */
6663 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6664 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6665 (protocol != __constant_htons(ETH_P_IP) ||
6666 hdr.ipv4->protocol != IPPROTO_TCP))
6667 return;
ee9e0f0b
AD		 6668
6669 th = tcp_hdr(skb);
c4cf55e5 6670
69830529
AD		 6671 /* skip this packet since the socket is closing */
6672 if (th->fin)
6673 return;
6674
6675 /* sample on all syn packets or once every atr sample count */
6676 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6677 return;
6678
6679 /* reset sample count */
6680 ring->atr_count = 0;
6681
6682 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6683
6684 /*
6685 * src and dst are inverted, think how the receiver sees them
6686 *
6687 * The input is broken into two sections, a non-compressed section
6688 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6689 * is XORed together and stored in the compressed dword.
6690 */
6691 input.formatted.vlan_id = vlan_id;
6692
6693 /*
6694 * since src port and flex bytes occupy the same word XOR them together
6695 * and write the value to source port portion of compressed dword
6696 */
6697 if (vlan_id)
6698 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6699 else
6700 common.port.src ^= th->dest ^ protocol;
6701 common.port.dst ^= th->source;
6702
6703 if (protocol == __constant_htons(ETH_P_IP)) {
6704 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6705 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6706 } else {
6707 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6708 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6709 hdr.ipv6->saddr.s6_addr32[1] ^
6710 hdr.ipv6->saddr.s6_addr32[2] ^
6711 hdr.ipv6->saddr.s6_addr32[3] ^
6712 hdr.ipv6->daddr.s6_addr32[0] ^
6713 hdr.ipv6->daddr.s6_addr32[1] ^
6714 hdr.ipv6->daddr.s6_addr32[2] ^
6715 hdr.ipv6->daddr.s6_addr32[3];
6716 }
c4cf55e5
PWJ		 6717
6718 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6719 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6720 input, common, ring->queue_index);
c4cf55e5
PWJ		 6721}
6722
fc77dc3c 6723static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6724{
fc77dc3c 6725 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6726 /* Herbert's original patch had:
6727 * smp_mb__after_netif_stop_queue();
6728 * but since that doesn't exist yet, just open code it. */
6729 smp_mb();
6730
6731 /* We need to check again in a case another CPU has just
6732 * made room available. */
6733 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6734 return -EBUSY;
6735
6736 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6737 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6738 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6739 return 0;
6740}
6741
fc77dc3c 6742static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6743{
6744 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6745 return 0;
fc77dc3c 6746 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6747}
6748
09a3b1f8
SH		 6749static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6750{
6751 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6752 int txq = smp_processor_id();
56075a98 6753#ifdef IXGBE_FCOE
5e09a105
HZ		 6754 __be16 protocol;
6755
6756 protocol = vlan_get_protocol(skb);
6757
e5b64635
JF		 6758 if (((protocol == htons(ETH_P_FCOE)) ||
6759 (protocol == htons(ETH_P_FIP))) &&
6760 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6761 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6762 txq += adapter->ring_feature[RING_F_FCOE].mask;
6763 return txq;
56075a98
JF		 6764 }
6765#endif
6766
fdd3d631
KK		 6767 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6768 while (unlikely(txq >= dev->real_num_tx_queues))
6769 txq -= dev->real_num_tx_queues;
5f715823 6770 return txq;
fdd3d631 6771 }
c4cf55e5 6772
09a3b1f8
SH		 6773 return skb_tx_hash(dev, skb);
6774}
6775
fc77dc3c 6776netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6777 struct ixgbe_adapter *adapter,
6778 struct ixgbe_ring *tx_ring)
9a799d71 6779{
9a799d71
AK		 6780 unsigned int first;
6781 unsigned int tx_flags = 0;
30eba97a 6782 u8 hdr_len = 0;
5f715823 6783 int tso;
9a799d71
AK		 6784 int count = 0;
6785 unsigned int f;
5e09a105
HZ		 6786 __be16 protocol;
6787
6788 protocol = vlan_get_protocol(skb);
9f8cdf4f 6789
eab6d18d 6790 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6791 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6792 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6793 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
e5b64635 6794 tx_flags |= tx_ring->dcb_tc << 13;
2f90b865
AD		 6795 }
6796 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6797 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6798 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6799 skb->priority != TC_PRIO_CONTROL) {
e5b64635 6800 tx_flags |= tx_ring->dcb_tc << 13;
2ea186ae
JF		 6801 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6802 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6803 }
eacd73f7 6804
09ad1cc0 6805#ifdef IXGBE_FCOE
56075a98
JF		 6806 /* for FCoE with DCB, we force the priority to what
6807 * was specified by the switch */
6808 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
e5b64635
JF		 6809 (protocol == htons(ETH_P_FCOE)))
6810 tx_flags |= IXGBE_TX_FLAGS_FCOE;
ca77cd59
RL		 6811#endif
6812
eacd73f7 6813 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6814 if (skb_is_gso(skb) ||
6815 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6816 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6817 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6818 count++;
6819
9f8cdf4f
JB		 6820 count += TXD_USE_COUNT(skb_headlen(skb));
6821 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6822 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6823
fc77dc3c 6824 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6825 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6826 return NETDEV_TX_BUSY;
6827 }
9a799d71 6828
9a799d71 6829 first = tx_ring->next_to_use;
eacd73f7
YZ		 6830 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6831#ifdef IXGBE_FCOE
6832 /* setup tx offload for FCoE */
6833 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6834 if (tso < 0) {
6835 dev_kfree_skb_any(skb);
6836 return NETDEV_TX_OK;
6837 }
6838 if (tso)
6839 tx_flags |= IXGBE_TX_FLAGS_FSO;
6840#endif /* IXGBE_FCOE */
6841 } else {
5e09a105 6842 if (protocol == htons(ETH_P_IP))
eacd73f7 6843 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6844 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6845 protocol);
eacd73f7
YZ		 6846 if (tso < 0) {
6847 dev_kfree_skb_any(skb);
6848 return NETDEV_TX_OK;
6849 }
9a799d71 6850
eacd73f7
YZ		 6851 if (tso)
6852 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6853 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6854 protocol) &&
eacd73f7
YZ		 6855 (skb->ip_summed == CHECKSUM_PARTIAL))
6856 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6857 }
9a799d71 6858
8ad494b0 6859 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6860 if (count) {
c4cf55e5 6861 /* add the ATR filter if ATR is on */
69830529
AD		 6862 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6863 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
84ea2591 6864 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6865 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6866
44df32c5
AD		 6867 } else {
6868 dev_kfree_skb_any(skb);
6869 tx_ring->tx_buffer_info[first].time_stamp = 0;
6870 tx_ring->next_to_use = first;
6871 }
9a799d71
AK		 6872
6873 return NETDEV_TX_OK;
6874}
6875
84418e3b
AD		 6876static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6877{
6878 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6879 struct ixgbe_ring *tx_ring;
6880
6881 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6882 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6883}
6884
9a799d71
AK		 6885/**
6886 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6887 * @netdev: network interface device structure
6888 * @p: pointer to an address structure
6889 *
6890 * Returns 0 on success, negative on failure
6891 **/
6892static int ixgbe_set_mac(struct net_device *netdev, void *p)
6893{
6894 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6895 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6896 struct sockaddr *addr = p;
6897
6898 if (!is_valid_ether_addr(addr->sa_data))
6899 return -EADDRNOTAVAIL;
6900
6901 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6902 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6903
1cdd1ec8
GR		 6904 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6905 IXGBE_RAH_AV);
9a799d71
AK		 6906
6907 return 0;
6908}
6909
6b73e10d
BH		 6910static int
6911ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6912{
6913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6914 struct ixgbe_hw *hw = &adapter->hw;
6915 u16 value;
6916 int rc;
6917
6918 if (prtad != hw->phy.mdio.prtad)
6919 return -EINVAL;
6920 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6921 if (!rc)
6922 rc = value;
6923 return rc;
6924}
6925
6926static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6927 u16 addr, u16 value)
6928{
6929 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6930 struct ixgbe_hw *hw = &adapter->hw;
6931
6932 if (prtad != hw->phy.mdio.prtad)
6933 return -EINVAL;
6934 return hw->phy.ops.write_reg(hw, addr, devad, value);
6935}
6936
6937static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6938{
6939 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6940
6941 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6942}
6943
0365e6e4
PW		 6944/**
6945 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6946 * netdev->dev_addrs
0365e6e4
PW		 6947 * @netdev: network interface device structure
6948 *
6949 * Returns non-zero on failure
6950 **/
6951static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6952{
6953 int err = 0;
6954 struct ixgbe_adapter *adapter = netdev_priv(dev);
6955 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6956
6957 if (is_valid_ether_addr(mac->san_addr)) {
6958 rtnl_lock();
6959 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6960 rtnl_unlock();
6961 }
6962 return err;
6963}
6964
6965/**
6966 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6967 * netdev->dev_addrs
0365e6e4
PW		 6968 * @netdev: network interface device structure
6969 *
6970 * Returns non-zero on failure
6971 **/
6972static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6973{
6974 int err = 0;
6975 struct ixgbe_adapter *adapter = netdev_priv(dev);
6976 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6977
6978 if (is_valid_ether_addr(mac->san_addr)) {
6979 rtnl_lock();
6980 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6981 rtnl_unlock();
6982 }
6983 return err;
6984}
6985
9a799d71
AK		 6986#ifdef CONFIG_NET_POLL_CONTROLLER
6987/*
6988 * Polling 'interrupt' - used by things like netconsole to send skbs
6989 * without having to re-enable interrupts. It's not called while
6990 * the interrupt routine is executing.
6991 */
6992static void ixgbe_netpoll(struct net_device *netdev)
6993{
6994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6995 int i;
9a799d71 6996
1a647bd2
AD		 6997 /* if interface is down do nothing */
6998 if (test_bit(__IXGBE_DOWN, &adapter->state))
6999 return;
7000
9a799d71 7001 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7002 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7003 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7004 for (i = 0; i < num_q_vectors; i++) {
7005 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7006 ixgbe_msix_clean_many(0, q_vector);
7007 }
7008 } else {
7009 ixgbe_intr(adapter->pdev->irq, netdev);
7010 }
9a799d71 7011 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7012}
7013#endif
7014
de1036b1
ED		 7015static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7016 struct rtnl_link_stats64 *stats)
7017{
7018 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7019 int i;
7020
1a51502b 7021 rcu_read_lock();
de1036b1 7022 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7023 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7024 u64 bytes, packets;
7025 unsigned int start;
7026
1a51502b
ED		 7027 if (ring) {
7028 do {
7029 start = u64_stats_fetch_begin_bh(&ring->syncp);
7030 packets = ring->stats.packets;
7031 bytes = ring->stats.bytes;
7032 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7033 stats->rx_packets += packets;
7034 stats->rx_bytes += bytes;
7035 }
de1036b1 7036 }
1ac9ad13
ED		 7037
7038 for (i = 0; i < adapter->num_tx_queues; i++) {
7039 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7040 u64 bytes, packets;
7041 unsigned int start;
7042
7043 if (ring) {
7044 do {
7045 start = u64_stats_fetch_begin_bh(&ring->syncp);
7046 packets = ring->stats.packets;
7047 bytes = ring->stats.bytes;
7048 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7049 stats->tx_packets += packets;
7050 stats->tx_bytes += bytes;
7051 }
7052 }
1a51502b 7053 rcu_read_unlock();
de1036b1
ED		 7054 /* following stats updated by ixgbe_watchdog_task() */
7055 stats->multicast = netdev->stats.multicast;
7056 stats->rx_errors = netdev->stats.rx_errors;
7057 stats->rx_length_errors = netdev->stats.rx_length_errors;
7058 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7059 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7060 return stats;
7061}
7062
7063
0edc3527 7064static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7065 .ndo_open = ixgbe_open,
0edc3527 7066 .ndo_stop = ixgbe_close,
00829823 7067 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7068 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7069 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7070 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7071 .ndo_validate_addr = eth_validate_addr,
7072 .ndo_set_mac_address = ixgbe_set_mac,
7073 .ndo_change_mtu = ixgbe_change_mtu,
7074 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7075 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7076 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7077 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7078 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7079 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7080 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7081 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7082 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3
JF		 7083#ifdef CONFIG_IXGBE_DCB
7084 .ndo_setup_tc = ixgbe_setup_tc,
7085#endif
0edc3527
SH		 7086#ifdef CONFIG_NET_POLL_CONTROLLER
7087 .ndo_poll_controller = ixgbe_netpoll,
7088#endif
332d4a7d
YZ		 7089#ifdef IXGBE_FCOE
7090 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7091 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7092 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7093 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7094 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7095 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7096#endif /* IXGBE_FCOE */
0edc3527
SH		 7097};
7098
1cdd1ec8
GR		 7099static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7100 const struct ixgbe_info *ii)
7101{
7102#ifdef CONFIG_PCI_IOV
7103 struct ixgbe_hw *hw = &adapter->hw;
7104 int err;
7105
3377eba7 7106 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7107 return;
7108
7109 /* The 82599 supports up to 64 VFs per physical function
7110 * but this implementation limits allocation to 63 so that
7111 * basic networking resources are still available to the
7112 * physical function
7113 */
7114 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7115 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7116 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7117 if (err) {
396e799c 7118 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7119 goto err_novfs;
7120 }
7121 /* If call to enable VFs succeeded then allocate memory
7122 * for per VF control structures.
7123 */
7124 adapter->vfinfo =
7125 kcalloc(adapter->num_vfs,
7126 sizeof(struct vf_data_storage), GFP_KERNEL);
7127 if (adapter->vfinfo) {
7128 /* Now that we're sure SR-IOV is enabled
7129 * and memory allocated set up the mailbox parameters
7130 */
7131 ixgbe_init_mbx_params_pf(hw);
7132 memcpy(&hw->mbx.ops, ii->mbx_ops,
7133 sizeof(hw->mbx.ops));
7134
7135 /* Disable RSC when in SR-IOV mode */
7136 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7137 IXGBE_FLAG2_RSC_ENABLED);
7138 return;
7139 }
7140
7141 /* Oh oh */
396e799c
ET		 7142 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7143 "SRIOV disabled\n");
1cdd1ec8
GR		 7144 pci_disable_sriov(adapter->pdev);
7145
7146err_novfs:
7147 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7148 adapter->num_vfs = 0;
7149#endif /* CONFIG_PCI_IOV */
7150}
7151
9a799d71
AK		 7152/**
7153 * ixgbe_probe - Device Initialization Routine
7154 * @pdev: PCI device information struct
7155 * @ent: entry in ixgbe_pci_tbl
7156 *
7157 * Returns 0 on success, negative on failure
7158 *
7159 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7160 * The OS initialization, configuring of the adapter private structure,
7161 * and a hardware reset occur.
7162 **/
7163static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7164 const struct pci_device_id *ent)
9a799d71
AK		 7165{
7166 struct net_device *netdev;
7167 struct ixgbe_adapter *adapter = NULL;
7168 struct ixgbe_hw *hw;
7169 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7170 static int cards_found;
7171 int i, err, pci_using_dac;
289700db 7172 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7173 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7174#ifdef IXGBE_FCOE
7175 u16 device_caps;
7176#endif
289700db 7177 u32 eec;
9a799d71 7178
bded64a7
AG		 7179 /* Catch broken hardware that put the wrong VF device ID in
7180 * the PCIe SR-IOV capability.
7181 */
7182 if (pdev->is_virtfn) {
7183 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7184 pci_name(pdev), pdev->vendor, pdev->device);
7185 return -EINVAL;
7186 }
7187
9ce77666 7188 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7189 if (err)
7190 return err;
7191
1b507730
NN		 7192 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7193 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7194 pci_using_dac = 1;
7195 } else {
1b507730 7196 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7197 if (err) {
1b507730
NN		 7198 err = dma_set_coherent_mask(&pdev->dev,
7199 DMA_BIT_MASK(32));
9a799d71 7200 if (err) {
b8bc0421
DC		 7201 dev_err(&pdev->dev,
7202 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7203 goto err_dma;
7204 }
7205 }
7206 pci_using_dac = 0;
7207 }
7208
9ce77666 7209 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7210 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7211 if (err) {
b8bc0421
DC		 7212 dev_err(&pdev->dev,
7213 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7214 goto err_pci_reg;
7215 }
7216
19d5afd4 7217 pci_enable_pcie_error_reporting(pdev);
6fabd715 7218
9a799d71 7219 pci_set_master(pdev);
fb3b27bc 7220 pci_save_state(pdev);
9a799d71 7221
c85a2618
JF		 7222 if (ii->mac == ixgbe_mac_82598EB)
7223 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7224 else
7225 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7226
e5b64635 7227#if defined(CONFIG_DCB)
c85a2618 7228 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
e5b64635 7229#elif defined(IXGBE_FCOE)
c85a2618
JF		 7230 indices += min_t(unsigned int, num_possible_cpus(),
7231 IXGBE_MAX_FCOE_INDICES);
7232#endif
c85a2618 7233 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7234 if (!netdev) {
7235 err = -ENOMEM;
7236 goto err_alloc_etherdev;
7237 }
7238
9a799d71
AK		 7239 SET_NETDEV_DEV(netdev, &pdev->dev);
7240
9a799d71 7241 adapter = netdev_priv(netdev);
c60fbb00 7242 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7243
7244 adapter->netdev = netdev;
7245 adapter->pdev = pdev;
7246 hw = &adapter->hw;
7247 hw->back = adapter;
7248 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7249
05857980 7250 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7251 pci_resource_len(pdev, 0));
9a799d71
AK		 7252 if (!hw->hw_addr) {
7253 err = -EIO;
7254 goto err_ioremap;
7255 }
7256
7257 for (i = 1; i <= 5; i++) {
7258 if (pci_resource_len(pdev, i) == 0)
7259 continue;
7260 }
7261
0edc3527 7262 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7263 ixgbe_set_ethtool_ops(netdev);
9a799d71 7264 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7265 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7266
9a799d71
AK		 7267 adapter->bd_number = cards_found;
7268
9a799d71
AK		 7269 /* Setup hw api */
7270 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7271 hw->mac.type = ii->mac;
9a799d71 7272
c44ade9e
JB		 7273 /* EEPROM */
7274 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7275 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7276 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7277 if (!(eec & (1 << 8)))
7278 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7279
7280 /* PHY */
7281 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7282 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7283 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7284 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7285 hw->phy.mdio.mmds = 0;
7286 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7287 hw->phy.mdio.dev = netdev;
7288 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7289 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 7290
7291 /* set up this timer and work struct before calling get_invariants
7292 * which might start the timer
7293 */
7294 init_timer(&adapter->sfp_timer);
c061b18d 7295 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 7296 adapter->sfp_timer.data = (unsigned long) adapter;
7297
7298 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 7299
e8e26350
PW		 7300 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7301 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7302
7303 /* a new SFP+ module arrival, called from GPI SDP2 context */
7304 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 7305 ixgbe_sfp_config_module_task);
e8e26350 7306
8ca783ab 7307 ii->get_invariants(hw);
9a799d71
AK		 7308
7309 /* setup the private structure */
7310 err = ixgbe_sw_init(adapter);
7311 if (err)
7312 goto err_sw_init;
7313
e86bff0e 7314 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7315 switch (adapter->hw.mac.type) {
7316 case ixgbe_mac_82599EB:
7317 case ixgbe_mac_X540:
e86bff0e 7318 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7319 break;
7320 default:
7321 break;
7322 }
e86bff0e 7323
bf069c97
DS		 7324 /*
7325 * If there is a fan on this device and it has failed log the
7326 * failure.
7327 */
7328 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7329 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7330 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7331 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7332 }
7333
c44ade9e 7334 /* reset_hw fills in the perm_addr as well */
119fc60a 7335 hw->phy.reset_if_overtemp = true;
c44ade9e 7336 err = hw->mac.ops.reset_hw(hw);
119fc60a 7337 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7338 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7339 hw->mac.type == ixgbe_mac_82598EB) {
7340 /*
7341 * Start a kernel thread to watch for a module to arrive.
7342 * Only do this for 82598, since 82599 will generate
7343 * interrupts on module arrival.
7344 */
7345 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7346 mod_timer(&adapter->sfp_timer,
7347 round_jiffies(jiffies + (2 * HZ)));
7348 err = 0;
7349 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 7350 e_dev_err("failed to initialize because an unsupported SFP+ "
7351 "module type was detected.\n");
7352 e_dev_err("Reload the driver after installing a supported "
7353 "module.\n");
04f165ef
PW		 7354 goto err_sw_init;
7355 } else if (err) {
849c4542 7356 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7357 goto err_sw_init;
7358 }
7359
1cdd1ec8
GR		 7360 ixgbe_probe_vf(adapter, ii);
7361
396e799c 7362 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7363 NETIF_F_IP_CSUM |
7364 NETIF_F_HW_VLAN_TX |
7365 NETIF_F_HW_VLAN_RX |
7366 NETIF_F_HW_VLAN_FILTER;
9a799d71 7367
e9990a9c 7368 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7369 netdev->features |= NETIF_F_TSO;
9a799d71 7370 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7371 netdev->features |= NETIF_F_GRO;
67a74ee2 7372 netdev->features |= NETIF_F_RXHASH;
ad31c402 7373
58be7666
DS		 7374 switch (adapter->hw.mac.type) {
7375 case ixgbe_mac_82599EB:
7376 case ixgbe_mac_X540:
45a5ead0 7377 netdev->features |= NETIF_F_SCTP_CSUM;
58be7666
DS		 7378 break;
7379 default:
7380 break;
7381 }
45a5ead0 7382
ad31c402
JK		 7383 netdev->vlan_features |= NETIF_F_TSO;
7384 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7385 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7386 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7387 netdev->vlan_features |= NETIF_F_SG;
7388
1cdd1ec8
GR		 7389 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7390 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7391 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7392
7a6b6f51 7393#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7394 netdev->dcbnl_ops = &dcbnl_ops;
7395#endif
7396
eacd73f7 7397#ifdef IXGBE_FCOE
0d551589 7398 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7399 if (hw->mac.ops.get_device_caps) {
7400 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7401 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7402 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7403 }
7404 }
5e09d7f6
YZ		 7405 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7406 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7407 netdev->vlan_features |= NETIF_F_FSO;
7408 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7409 }
eacd73f7 7410#endif /* IXGBE_FCOE */
7b872a55 7411 if (pci_using_dac) {
9a799d71 7412 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7413 netdev->vlan_features |= NETIF_F_HIGHDMA;
7414 }
9a799d71 7415
0c19d6af 7416 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7417 netdev->features |= NETIF_F_LRO;
7418
9a799d71 7419 /* make sure the EEPROM is good */
c44ade9e 7420 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7421 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7422 err = -EIO;
7423 goto err_eeprom;
7424 }
7425
7426 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7427 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7428
c44ade9e 7429 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7430 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7431 err = -EIO;
7432 goto err_eeprom;
7433 }
7434
c6ecf39a
DS		 7435 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7436 if (hw->mac.ops.disable_tx_laser &&
7437 ((hw->phy.multispeed_fiber) ||
9f911707 7438 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7439 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7440 hw->mac.ops.disable_tx_laser(hw);
7441
9a799d71 7442 init_timer(&adapter->watchdog_timer);
c061b18d 7443 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 7444 adapter->watchdog_timer.data = (unsigned long)adapter;
7445
7446 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 7447 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 7448
021230d4
AV		 7449 err = ixgbe_init_interrupt_scheme(adapter);
7450 if (err)
7451 goto err_sw_init;
9a799d71 7452
67a74ee2
ET		 7453 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7454 netdev->features &= ~NETIF_F_RXHASH;
7455
e8e26350 7456 switch (pdev->device) {
0b077fea
DS		 7457 case IXGBE_DEV_ID_82599_SFP:
7458 /* Only this subdevice supports WOL */
7459 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7460 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7461 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7462 break;
50d6c681
AD		 7463 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7464 /* All except this subdevice support WOL */
0b077fea
DS		 7465 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7466 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7467 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7468 break;
e8e26350 7469 case IXGBE_DEV_ID_82599_KX4:
495dce12 7470 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7471 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7472 break;
7473 default:
7474 adapter->wol = 0;
7475 break;
7476 }
e8e26350
PW		 7477 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7478
04f165ef
PW		 7479 /* pick up the PCI bus settings for reporting later */
7480 hw->mac.ops.get_bus_info(hw);
7481
9a799d71 7482 /* print bus type/speed/width info */
849c4542 7483 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7484 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7485 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7486 "Unknown"),
7487 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7488 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7489 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7490 "Unknown"),
7491 netdev->dev_addr);
289700db
DS		 7492
7493 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7494 if (err)
9fe93afd 7495 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7496 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7497 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7498 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7499 part_str);
e8e26350 7500 else
289700db
DS		 7501 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7502 hw->mac.type, hw->phy.type, part_str);
9a799d71 7503
e8e26350 7504 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7505 e_dev_warn("PCI-Express bandwidth available for this card is "
7506 "not sufficient for optimal performance.\n");
7507 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7508 "is required.\n");
0c254d86
AK		 7509 }
7510
34b0368c
PWJ		 7511 /* save off EEPROM version number */
7512 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7513
9a799d71 7514 /* reset the hardware with the new settings */
794caeb2 7515 err = hw->mac.ops.start_hw(hw);
c44ade9e 7516
794caeb2
PWJ		 7517 if (err == IXGBE_ERR_EEPROM_VERSION) {
7518 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7519 e_dev_warn("This device is a pre-production adapter/LOM. "
7520 "Please be aware there may be issues associated "
7521 "with your hardware. If you are experiencing "
7522 "problems please contact your Intel or hardware "
7523 "representative who provided you with this "
7524 "hardware.\n");
794caeb2 7525 }
9a799d71
AK		 7526 strcpy(netdev->name, "eth%d");
7527 err = register_netdev(netdev);
7528 if (err)
7529 goto err_register;
7530
54386467
JB		 7531 /* carrier off reporting is important to ethtool even BEFORE open */
7532 netif_carrier_off(netdev);
7533
c4cf55e5
PWJ		 7534 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7535 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7536 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7537
119fc60a 7538 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7539 INIT_WORK(&adapter->check_overtemp_task,
7540 ixgbe_check_overtemp_task);
5dd2d332 7541#ifdef CONFIG_IXGBE_DCA
652f093f 7542 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7543 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7544 ixgbe_setup_dca(adapter);
7545 }
7546#endif
1cdd1ec8 7547 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7548 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7549 for (i = 0; i < adapter->num_vfs; i++)
7550 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7551 }
7552
0365e6e4
PW		 7553 /* add san mac addr to netdev */
7554 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7555
849c4542 7556 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7557 cards_found++;
7558 return 0;
7559
7560err_register:
5eba3699 7561 ixgbe_release_hw_control(adapter);
7a921c93 7562 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7563err_sw_init:
7564err_eeprom:
1cdd1ec8
GR		 7565 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7566 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7567 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7568 del_timer_sync(&adapter->sfp_timer);
7569 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7570 cancel_work_sync(&adapter->multispeed_fiber_task);
7571 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7572 iounmap(hw->hw_addr);
7573err_ioremap:
7574 free_netdev(netdev);
7575err_alloc_etherdev:
e8e9f696
JP		 7576 pci_release_selected_regions(pdev,
7577 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7578err_pci_reg:
7579err_dma:
7580 pci_disable_device(pdev);
7581 return err;
7582}
7583
7584/**
7585 * ixgbe_remove - Device Removal Routine
7586 * @pdev: PCI device information struct
7587 *
7588 * ixgbe_remove is called by the PCI subsystem to alert the driver
7589 * that it should release a PCI device. The could be caused by a
7590 * Hot-Plug event, or because the driver is going to be removed from
7591 * memory.
7592 **/
7593static void __devexit ixgbe_remove(struct pci_dev *pdev)
7594{
c60fbb00
AD		 7595 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7596 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7597
7598 set_bit(__IXGBE_DOWN, &adapter->state);
760141a5
TH		 7599
7600 /*
7601 * The timers may be rescheduled, so explicitly disable them
7602 * from being rescheduled.
c4900be0
DS		 7603 */
7604 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71 7605 del_timer_sync(&adapter->watchdog_timer);
c4900be0 7606 del_timer_sync(&adapter->sfp_timer);
760141a5 7607
c4900be0
DS		 7608 cancel_work_sync(&adapter->watchdog_task);
7609 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7610 cancel_work_sync(&adapter->multispeed_fiber_task);
7611 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7612 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7613 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7614 cancel_work_sync(&adapter->fdir_reinit_task);
760141a5
TH		 7615 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7616 cancel_work_sync(&adapter->check_overtemp_task);
9a799d71 7617
5dd2d332 7618#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7619 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7620 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7621 dca_remove_requester(&pdev->dev);
7622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7623 }
7624
7625#endif
332d4a7d
YZ		 7626#ifdef IXGBE_FCOE
7627 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7628 ixgbe_cleanup_fcoe(adapter);
7629
7630#endif /* IXGBE_FCOE */
0365e6e4
PW		 7631
7632 /* remove the added san mac */
7633 ixgbe_del_sanmac_netdev(netdev);
7634
c4900be0
DS		 7635 if (netdev->reg_state == NETREG_REGISTERED)
7636 unregister_netdev(netdev);
9a799d71 7637
1cdd1ec8
GR		 7638 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7639 ixgbe_disable_sriov(adapter);
7640
7a921c93 7641 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7642
021230d4 7643 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7644
7645 iounmap(adapter->hw.hw_addr);
9ce77666 7646 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7647 IORESOURCE_MEM));
9a799d71 7648
849c4542 7649 e_dev_info("complete\n");
021230d4 7650
9a799d71
AK		 7651 free_netdev(netdev);
7652
19d5afd4 7653 pci_disable_pcie_error_reporting(pdev);
6fabd715 7654
9a799d71
AK		 7655 pci_disable_device(pdev);
7656}
7657
7658/**
7659 * ixgbe_io_error_detected - called when PCI error is detected
7660 * @pdev: Pointer to PCI device
7661 * @state: The current pci connection state
7662 *
7663 * This function is called after a PCI bus error affecting
7664 * this device has been detected.
7665 */
7666static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7667 pci_channel_state_t state)
9a799d71 7668{
c60fbb00
AD		 7669 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7670 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7671
7672 netif_device_detach(netdev);
7673
3044b8d1
BL		 7674 if (state == pci_channel_io_perm_failure)
7675 return PCI_ERS_RESULT_DISCONNECT;
7676
9a799d71
AK		 7677 if (netif_running(netdev))
7678 ixgbe_down(adapter);
7679 pci_disable_device(pdev);
7680
b4617240 7681 /* Request a slot reset. */
9a799d71
AK		 7682 return PCI_ERS_RESULT_NEED_RESET;
7683}
7684
7685/**
7686 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7687 * @pdev: Pointer to PCI device
7688 *
7689 * Restart the card from scratch, as if from a cold-boot.
7690 */
7691static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7692{
c60fbb00 7693 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7694 pci_ers_result_t result;
7695 int err;
9a799d71 7696
9ce77666 7697 if (pci_enable_device_mem(pdev)) {
396e799c 7698 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7699 result = PCI_ERS_RESULT_DISCONNECT;
7700 } else {
7701 pci_set_master(pdev);
7702 pci_restore_state(pdev);
c0e1f68b 7703 pci_save_state(pdev);
9a799d71 7704
dd4d8ca6 7705 pci_wake_from_d3(pdev, false);
9a799d71 7706
6fabd715 7707 ixgbe_reset(adapter);
88512539 7708 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7709 result = PCI_ERS_RESULT_RECOVERED;
7710 }
7711
7712 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7713 if (err) {
849c4542
ET		 7714 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7715 "failed 0x%0x\n", err);
6fabd715
PWJ		 7716 /* non-fatal, continue */
7717 }
9a799d71 7718
6fabd715 7719 return result;
9a799d71
AK		 7720}
7721
7722/**
7723 * ixgbe_io_resume - called when traffic can start flowing again.
7724 * @pdev: Pointer to PCI device
7725 *
7726 * This callback is called when the error recovery driver tells us that
7727 * its OK to resume normal operation.
7728 */
7729static void ixgbe_io_resume(struct pci_dev *pdev)
7730{
c60fbb00
AD		 7731 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7732 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7733
7734 if (netif_running(netdev)) {
7735 if (ixgbe_up(adapter)) {
396e799c 7736 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7737 return;
7738 }
7739 }
7740
7741 netif_device_attach(netdev);
9a799d71
AK		 7742}
7743
7744static struct pci_error_handlers ixgbe_err_handler = {
7745 .error_detected = ixgbe_io_error_detected,
7746 .slot_reset = ixgbe_io_slot_reset,
7747 .resume = ixgbe_io_resume,
7748};
7749
7750static struct pci_driver ixgbe_driver = {
7751 .name = ixgbe_driver_name,
7752 .id_table = ixgbe_pci_tbl,
7753 .probe = ixgbe_probe,
7754 .remove = __devexit_p(ixgbe_remove),
7755#ifdef CONFIG_PM
7756 .suspend = ixgbe_suspend,
7757 .resume = ixgbe_resume,
7758#endif
7759 .shutdown = ixgbe_shutdown,
7760 .err_handler = &ixgbe_err_handler
7761};
7762
7763/**
7764 * ixgbe_init_module - Driver Registration Routine
7765 *
7766 * ixgbe_init_module is the first routine called when the driver is
7767 * loaded. All it does is register with the PCI subsystem.
7768 **/
7769static int __init ixgbe_init_module(void)
7770{
7771 int ret;
c7689578 7772 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7773 pr_info("%s\n", ixgbe_copyright);
9a799d71 7774
5dd2d332 7775#ifdef CONFIG_IXGBE_DCA
bd0362dd 7776 dca_register_notify(&dca_notifier);
bd0362dd 7777#endif
5dd2d332 7778
9a799d71
AK		 7779 ret = pci_register_driver(&ixgbe_driver);
7780 return ret;
7781}
b4617240 7782
9a799d71
AK		 7783module_init(ixgbe_init_module);
7784
7785/**
7786 * ixgbe_exit_module - Driver Exit Cleanup Routine
7787 *
7788 * ixgbe_exit_module is called just before the driver is removed
7789 * from memory.
7790 **/
7791static void __exit ixgbe_exit_module(void)
7792{
5dd2d332 7793#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7794 dca_unregister_notify(&dca_notifier);
7795#endif
9a799d71 7796 pci_unregister_driver(&ixgbe_driver);
1a51502b 7797 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7798}
bd0362dd 7799
5dd2d332 7800#ifdef CONFIG_IXGBE_DCA
bd0362dd 7801static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7802 void *p)
bd0362dd
JC		 7803{
7804 int ret_val;
7805
7806 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7807 __ixgbe_notify_dca);
bd0362dd
JC		 7808
7809 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7810}
b453368d 7811
5dd2d332 7812#endif /* CONFIG_IXGBE_DCA */
849c4542 7813
9a799d71
AK		 7814module_exit(ixgbe_exit_module);
7815
7816/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)