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igb: Add support of SerDes Forced mode for certain hardware
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
45#include <linux/if_vlan.h>
70c71606 46#include <linux/prefetch.h>
eacd73f7 47#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 48
49#include "ixgbe.h"
50#include "ixgbe_common.h"
ee5f784a 51#include "ixgbe_dcb_82599.h"
1cdd1ec8 52#include "ixgbe_sriov.h"
9a799d71
AK		 53
54char ixgbe_driver_name[] = "ixgbe";
9c8eb720 55static const char ixgbe_driver_string[] =
e8e9f696 56 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 57#define MAJ 3
a38a104d 58#define MIN 4
c89c7112 59#define BUILD 8
75e3d3c6 60#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 61 __stringify(BUILD) "-k"
9c8eb720 62const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 63static const char ixgbe_copyright[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 65
66static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 67 [board_82598] = &ixgbe_82598_info,
e8e26350 68 [board_82599] = &ixgbe_82599_info,
fe15e8e1 69 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 70};
71
72/* ixgbe_pci_tbl - PCI Device ID Table
73 *
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
76 *
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
79 */
a3aa1884 80static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 84 board_82598 },
9a799d71 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 86 board_82598 },
0befdb3e
JB		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
88 board_82598 },
3845bec0
PWJ		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
90 board_82598 },
9a799d71 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 92 board_82598 },
8d792cd9
JB		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
94 board_82598 },
c4900be0
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
98 board_82598 },
b95f5fcb
JB		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
100 board_82598 },
c4900be0
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
102 board_82598 },
2f21bdd3
DS		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
104 board_82598 },
e8e26350
PW		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
106 board_82599 },
1fcf03e6
PWJ		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
108 board_82599 },
74757d49
DS		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
110 board_82599 },
e8e26350
PW		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
112 board_82599 },
38ad1c8e
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
114 board_82599 },
dbfec662
DS		 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
116 board_82599 },
8911184f
PWJ		 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
118 board_82599 },
dbffcb21
DS		 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
120 board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
122 board_82599 },
119fc60a
MC		 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
124 board_82599 },
312eb931
DS		 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
126 board_82599 },
b93a2226 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 128 board_X540 },
4c40ef02
ET		 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
130 board_82599 },
4f6290cf
DS		 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
132 board_82599 },
9a799d71
AK		 133
134 /* required last entry */
135 {0, }
136};
137MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138
5dd2d332 139#ifdef CONFIG_IXGBE_DCA
bd0362dd 140static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 141 void *p);
bd0362dd
JC		 142static struct notifier_block dca_notifier = {
143 .notifier_call = ixgbe_notify_dca,
144 .next = NULL,
145 .priority = 0
146};
147#endif
148
1cdd1ec8
GR		 149#ifdef CONFIG_PCI_IOV
150static unsigned int max_vfs;
151module_param(max_vfs, uint, 0);
e8e9f696
JP		 152MODULE_PARM_DESC(max_vfs,
153 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 154#endif /* CONFIG_PCI_IOV */
155
9a799d71
AK		 156MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158MODULE_LICENSE("GPL");
159MODULE_VERSION(DRV_VERSION);
160
161#define DEFAULT_DEBUG_LEVEL_SHIFT 3
162
1cdd1ec8
GR		 163static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
164{
165 struct ixgbe_hw *hw = &adapter->hw;
166 u32 gcr;
167 u32 gpie;
168 u32 vmdctl;
169
170#ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter->pdev);
173#endif
174
175 /* turn off device IOV mode */
176 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
177 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
178 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
179 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
180 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
181 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
182
183 /* set default pool back to 0 */
184 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
185 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
186 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
187
188 /* take a breather then clean up driver data */
189 msleep(100);
e8e9f696
JP		 190
191 kfree(adapter->vfinfo);
1cdd1ec8
GR		 192 adapter->vfinfo = NULL;
193
194 adapter->num_vfs = 0;
195 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
196}
197
7086400d
AD		 198static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199{
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203}
204
205static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206{
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212}
213
dcd79aeb
TI		 214struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217};
218
219static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249};
250
251
252/*
253 * ixgbe_regdump - register printout routine
254 */
255static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256{
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
c7689578 319 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 326 pr_err("%-15s", rname);
dcd79aeb 327 for (j = 0; j < 8; j++)
c7689578
JP		 328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
dcd79aeb
TI		 330 }
331
332}
333
334/*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337static void ixgbe_dump(struct ixgbe_adapter *adapter)
338{
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer_info;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 359 pr_info("Device Name state "
dcd79aeb 360 "trans_start last_rx\n");
c7689578
JP		 361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
dcd79aeb
TI		 366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 370 pr_info(" Register Name Value\n");
dcd79aeb
TI		 371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 382 for (n = 0; n < adapter->num_tx_queues; n++) {
383 tx_ring = adapter->tx_ring[n];
384 tx_buffer_info =
385 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 387 n, tx_ring->next_to_use, tx_ring->next_to_clean,
388 (u64)tx_buffer_info->dma,
389 tx_buffer_info->length,
390 tx_buffer_info->next_to_watch,
391 (u64)tx_buffer_info->time_stamp);
392 }
393
394 /* Print TX Rings */
395 if (!netif_msg_tx_done(adapter))
396 goto rx_ring_summary;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
399
400 /* Transmit Descriptor Formats
401 *
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
409 */
410
411 for (n = 0; n < adapter->num_tx_queues; n++) {
412 tx_ring = adapter->tx_ring[n];
c7689578
JP		 413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
419
420 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 421 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 422 tx_buffer_info = &tx_ring->tx_buffer_info[i];
423 u0 = (struct my_u0 *)tx_desc;
c7689578 424 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 425 " %04X %3X %016llX %p", i,
426 le64_to_cpu(u0->a),
427 le64_to_cpu(u0->b),
428 (u64)tx_buffer_info->dma,
429 tx_buffer_info->length,
430 tx_buffer_info->next_to_watch,
431 (u64)tx_buffer_info->time_stamp,
432 tx_buffer_info->skb);
433 if (i == tx_ring->next_to_use &&
434 i == tx_ring->next_to_clean)
c7689578 435 pr_cont(" NTC/U\n");
dcd79aeb 436 else if (i == tx_ring->next_to_use)
c7689578 437 pr_cont(" NTU\n");
dcd79aeb 438 else if (i == tx_ring->next_to_clean)
c7689578 439 pr_cont(" NTC\n");
dcd79aeb 440 else
c7689578 441 pr_cont("\n");
dcd79aeb
TI		 442
443 if (netif_msg_pktdata(adapter) &&
444 tx_buffer_info->dma != 0)
445 print_hex_dump(KERN_INFO, "",
446 DUMP_PREFIX_ADDRESS, 16, 1,
447 phys_to_virt(tx_buffer_info->dma),
448 tx_buffer_info->length, true);
449 }
450 }
451
452 /* Print RX Rings Summary */
453rx_ring_summary:
454 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 455 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 456 for (n = 0; n < adapter->num_rx_queues; n++) {
457 rx_ring = adapter->rx_ring[n];
c7689578
JP		 458 pr_info("%5d %5X %5X\n",
459 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 460 }
461
462 /* Print RX Rings */
463 if (!netif_msg_rx_status(adapter))
464 goto exit;
465
466 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
467
468 /* Advanced Receive Descriptor (Read) Format
469 * 63 1 0
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
475 *
476 *
477 * Advanced Receive Descriptor (Write-Back) Format
478 *
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
487 */
488 for (n = 0; n < adapter->num_rx_queues; n++) {
489 rx_ring = adapter->rx_ring[n];
c7689578
JP		 490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
c7689578 496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
499
500 for (i = 0; i < rx_ring->count; i++) {
501 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 502 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 503 u0 = (struct my_u0 *)rx_desc;
504 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
505 if (staterr & IXGBE_RXD_STAT_DD) {
506 /* Descriptor Done */
c7689578 507 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 508 "%016llX ---------------- %p", i,
509 le64_to_cpu(u0->a),
510 le64_to_cpu(u0->b),
511 rx_buffer_info->skb);
512 } else {
c7689578 513 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 514 "%016llX %016llX %p", i,
515 le64_to_cpu(u0->a),
516 le64_to_cpu(u0->b),
517 (u64)rx_buffer_info->dma,
518 rx_buffer_info->skb);
519
520 if (netif_msg_pktdata(adapter)) {
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS, 16, 1,
523 phys_to_virt(rx_buffer_info->dma),
524 rx_ring->rx_buf_len, true);
525
526 if (rx_ring->rx_buf_len
527 < IXGBE_RXBUFFER_2048)
528 print_hex_dump(KERN_INFO, "",
529 DUMP_PREFIX_ADDRESS, 16, 1,
530 phys_to_virt(
531 rx_buffer_info->page_dma +
532 rx_buffer_info->page_offset
533 ),
534 PAGE_SIZE/2, true);
535 }
536 }
537
538 if (i == rx_ring->next_to_use)
c7689578 539 pr_cont(" NTU\n");
dcd79aeb 540 else if (i == rx_ring->next_to_clean)
c7689578 541 pr_cont(" NTC\n");
dcd79aeb 542 else
c7689578 543 pr_cont("\n");
dcd79aeb
TI		 544
545 }
546 }
547
548exit:
549 return;
550}
551
5eba3699
AV		 552static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
553{
554 u32 ctrl_ext;
555
556 /* Let firmware take over control of h/w */
557 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
558 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 559 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 560}
561
562static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
563{
564 u32 ctrl_ext;
565
566 /* Let firmware know the driver has taken over */
567 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 569 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 570}
9a799d71 571
e8e26350
PW		 572/*
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
578 *
579 */
580static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 581 u8 queue, u8 msix_vector)
9a799d71
AK		 582{
583 u32 ivar, index;
e8e26350
PW		 584 struct ixgbe_hw *hw = &adapter->hw;
585 switch (hw->mac.type) {
586 case ixgbe_mac_82598EB:
587 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
588 if (direction == -1)
589 direction = 0;
590 index = (((direction * 64) + queue) >> 2) & 0x1F;
591 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
592 ivar &= ~(0xFF << (8 * (queue & 0x3)));
593 ivar |= (msix_vector << (8 * (queue & 0x3)));
594 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
595 break;
596 case ixgbe_mac_82599EB:
b93a2226 597 case ixgbe_mac_X540:
e8e26350
PW		 598 if (direction == -1) {
599 /* other causes */
600 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
601 index = ((queue & 1) * 8);
602 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
603 ivar &= ~(0xFF << index);
604 ivar |= (msix_vector << index);
605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
606 break;
607 } else {
608 /* tx or rx causes */
609 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
610 index = ((16 * (queue & 1)) + (8 * direction));
611 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
612 ivar &= ~(0xFF << index);
613 ivar |= (msix_vector << index);
614 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
615 break;
616 }
617 default:
618 break;
619 }
9a799d71
AK		 620}
621
fe49f04a 622static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 623 u64 qmask)
fe49f04a
AD		 624{
625 u32 mask;
626
bd508178
AD		 627 switch (adapter->hw.mac.type) {
628 case ixgbe_mac_82598EB:
fe49f04a
AD		 629 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 631 break;
632 case ixgbe_mac_82599EB:
b93a2226 633 case ixgbe_mac_X540:
fe49f04a
AD		 634 mask = (qmask & 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
636 mask = (qmask >> 32);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 638 break;
639 default:
640 break;
fe49f04a
AD		 641 }
642}
643
b6ec895e
AD		 644void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
645 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 646{
e5a43549
AD		 647 if (tx_buffer_info->dma) {
648 if (tx_buffer_info->mapped_as_page)
b6ec895e 649 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 650 tx_buffer_info->dma,
651 tx_buffer_info->length,
1b507730 652 DMA_TO_DEVICE);
e5a43549 653 else
b6ec895e 654 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 655 tx_buffer_info->dma,
656 tx_buffer_info->length,
1b507730 657 DMA_TO_DEVICE);
e5a43549
AD		 658 tx_buffer_info->dma = 0;
659 }
9a799d71
AK		 660 if (tx_buffer_info->skb) {
661 dev_kfree_skb_any(tx_buffer_info->skb);
662 tx_buffer_info->skb = NULL;
663 }
44df32c5 664 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 665 /* tx_buffer_info must be completely set up in the transmit path */
666}
667
c84d324c
JF		 668static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
669{
670 struct ixgbe_hw *hw = &adapter->hw;
671 struct ixgbe_hw_stats *hwstats = &adapter->stats;
672 u32 data = 0;
673 u32 xoff[8] = {0};
674 int i;
675
676 if ((hw->fc.current_mode == ixgbe_fc_full) ||
677 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
678 switch (hw->mac.type) {
679 case ixgbe_mac_82598EB:
680 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 681 break;
682 default:
c84d324c
JF		 683 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
684 }
685 hwstats->lxoffrxc += data;
686
687 /* refill credits (no tx hang) if we received xoff */
688 if (!data)
689 return;
690
691 for (i = 0; i < adapter->num_tx_queues; i++)
692 clear_bit(__IXGBE_HANG_CHECK_ARMED,
693 &adapter->tx_ring[i]->state);
694 return;
695 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
696 return;
697
698 /* update stats for each tc, only valid with PFC enabled */
699 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
700 switch (hw->mac.type) {
701 case ixgbe_mac_82598EB:
702 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 703 break;
c84d324c
JF		 704 default:
705 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 706 }
c84d324c
JF		 707 hwstats->pxoffrxc[i] += xoff[i];
708 }
709
710 /* disarm tx queues that have received xoff frames */
711 for (i = 0; i < adapter->num_tx_queues; i++) {
712 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 713 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 714
715 if (xoff[tc])
716 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 717 }
26f23d82
YZ		 718}
719
c84d324c 720static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 721{
c84d324c
JF		 722 return ring->tx_stats.completed;
723}
724
725static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
726{
727 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 728 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 729
c84d324c
JF		 730 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
731 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
732
733 if (head != tail)
734 return (head < tail) ?
735 tail - head : (tail + ring->count - head);
736
737 return 0;
738}
739
740static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
741{
742 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
743 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
744 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
745 bool ret = false;
746
7d637bcc 747 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 748
749 /*
750 * Check for a hung queue, but be thorough. This verifies
751 * that a transmit has been completed since the previous
752 * check AND there is at least one packet pending. The
753 * ARMED bit is set to indicate a potential hang. The
754 * bit is cleared if a pause frame is received to remove
755 * false hang detection due to PFC or 802.3x frames. By
756 * requiring this to fail twice we avoid races with
757 * pfc clearing the ARMED bit and conditions where we
758 * run the check_tx_hang logic with a transmit completion
759 * pending but without time to complete it yet.
760 */
761 if ((tx_done_old == tx_done) && tx_pending) {
762 /* make sure it is true for two checks in a row */
763 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
764 &tx_ring->state);
765 } else {
766 /* update completed stats and continue */
767 tx_ring->tx_stats.tx_done_old = tx_done;
768 /* reset the countdown */
769 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 770 }
771
c84d324c 772 return ret;
9a799d71
AK		 773}
774
c83c6cbd
AD		 775/**
776 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
777 * @adapter: driver private struct
778 **/
779static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
780{
781
782 /* Do the reset outside of interrupt context */
783 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
784 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
785 ixgbe_service_event_schedule(adapter);
786 }
787}
e01c31a5 788
9a799d71
AK		 789/**
790 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 791 * @q_vector: structure containing interrupt and ring information
e01c31a5 792 * @tx_ring: tx ring to clean
9a799d71 793 **/
fe49f04a 794static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 795 struct ixgbe_ring *tx_ring)
9a799d71 796{
fe49f04a 797 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 798 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
799 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 800 unsigned int total_bytes = 0, total_packets = 0;
b953799e 801 u16 i, eop, count = 0;
9a799d71
AK		 802
803 i = tx_ring->next_to_clean;
12207e49 804 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 805 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 806
807 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 808 (count < tx_ring->work_limit)) {
12207e49 809 bool cleaned = false;
2d0bb1c1 810 rmb(); /* read buffer_info after eop_desc */
12207e49 811 for ( ; !cleaned; count++) {
31f05a2d 812 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 813 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 814
815 tx_desc->wb.status = 0;
12207e49 816 cleaned = (i == eop);
9a799d71 817
8ad494b0
AD		 818 i++;
819 if (i == tx_ring->count)
820 i = 0;
e01c31a5 821
8ad494b0
AD		 822 if (cleaned && tx_buffer_info->skb) {
823 total_bytes += tx_buffer_info->bytecount;
824 total_packets += tx_buffer_info->gso_segs;
e092be60 825 }
e01c31a5 826
b6ec895e 827 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 828 tx_buffer_info);
e01c31a5 829 }
12207e49 830
c84d324c 831 tx_ring->tx_stats.completed++;
12207e49 832 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 833 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 834 }
835
9a799d71 836 tx_ring->next_to_clean = i;
b953799e
AD		 837 tx_ring->total_bytes += total_bytes;
838 tx_ring->total_packets += total_packets;
839 u64_stats_update_begin(&tx_ring->syncp);
840 tx_ring->stats.packets += total_packets;
841 tx_ring->stats.bytes += total_bytes;
842 u64_stats_update_end(&tx_ring->syncp);
843
c84d324c
JF		 844 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
845 /* schedule immediate reset if we believe we hung */
846 struct ixgbe_hw *hw = &adapter->hw;
847 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
848 e_err(drv, "Detected Tx Unit Hang\n"
849 " Tx Queue <%d>\n"
850 " TDH, TDT <%x>, <%x>\n"
851 " next_to_use <%x>\n"
852 " next_to_clean <%x>\n"
853 "tx_buffer_info[next_to_clean]\n"
854 " time_stamp <%lx>\n"
855 " jiffies <%lx>\n",
856 tx_ring->queue_index,
857 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
858 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
859 tx_ring->next_to_use, eop,
860 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
861
862 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
863
864 e_info(probe,
865 "tx hang %d detected on queue %d, resetting adapter\n",
866 adapter->tx_timeout_count + 1, tx_ring->queue_index);
867
b953799e 868 /* schedule immediate reset if we believe we hung */
c83c6cbd 869 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 870
871 /* the adapter is about to reset, no point in enabling stuff */
872 return true;
873 }
9a799d71 874
e092be60 875#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 876 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 877 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 878 /* Make sure that anybody stopping the queue after this
879 * sees the new next_to_clean.
880 */
881 smp_mb();
fc77dc3c 882 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 883 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 884 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 885 ++tx_ring->tx_stats.restart_queue;
30eba97a 886 }
e092be60 887 }
9a799d71 888
807540ba 889 return count < tx_ring->work_limit;
9a799d71
AK		 890}
891
5dd2d332 892#ifdef CONFIG_IXGBE_DCA
bd0362dd 893static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 894 struct ixgbe_ring *rx_ring,
895 int cpu)
bd0362dd 896{
33cf09c9 897 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 898 u32 rxctrl;
33cf09c9
AD		 899 u8 reg_idx = rx_ring->reg_idx;
900
901 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
902 switch (hw->mac.type) {
903 case ixgbe_mac_82598EB:
904 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
905 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
906 break;
907 case ixgbe_mac_82599EB:
b93a2226 908 case ixgbe_mac_X540:
33cf09c9
AD		 909 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
910 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
911 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
912 break;
913 default:
914 break;
bd0362dd 915 }
33cf09c9
AD		 916 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
917 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
918 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 919 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 920}
921
922static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 923 struct ixgbe_ring *tx_ring,
924 int cpu)
bd0362dd 925{
33cf09c9 926 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 927 u32 txctrl;
33cf09c9
AD		 928 u8 reg_idx = tx_ring->reg_idx;
929
930 switch (hw->mac.type) {
931 case ixgbe_mac_82598EB:
932 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
933 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
934 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
935 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 936 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
937 break;
938 case ixgbe_mac_82599EB:
b93a2226 939 case ixgbe_mac_X540:
33cf09c9
AD		 940 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
941 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
942 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
943 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
944 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 945 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
946 break;
947 default:
948 break;
949 }
950}
951
952static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
953{
954 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 955 int cpu = get_cpu();
33cf09c9
AD		 956 long r_idx;
957 int i;
bd0362dd 958
33cf09c9
AD		 959 if (q_vector->cpu == cpu)
960 goto out_no_update;
961
962 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
963 for (i = 0; i < q_vector->txr_count; i++) {
964 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
965 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
966 r_idx + 1);
bd0362dd 967 }
33cf09c9
AD		 968
969 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
970 for (i = 0; i < q_vector->rxr_count; i++) {
971 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
972 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
973 r_idx + 1);
974 }
975
976 q_vector->cpu = cpu;
977out_no_update:
bd0362dd
JC		 978 put_cpu();
979}
980
981static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
982{
33cf09c9 983 int num_q_vectors;
bd0362dd
JC		 984 int i;
985
986 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
987 return;
988
e35ec126
AD		 989 /* always use CB2 mode, difference is masked in the CB driver */
990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
991
33cf09c9
AD		 992 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
993 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
994 else
995 num_q_vectors = 1;
996
997 for (i = 0; i < num_q_vectors; i++) {
998 adapter->q_vector[i]->cpu = -1;
999 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1000 }
1001}
1002
1003static int __ixgbe_notify_dca(struct device *dev, void *data)
1004{
c60fbb00 1005 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1006 unsigned long event = *(unsigned long *)data;
1007
33cf09c9
AD		 1008 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1009 return 0;
1010
bd0362dd
JC		 1011 switch (event) {
1012 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1013 /* if we're already enabled, don't do it again */
1014 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1015 break;
652f093f 1016 if (dca_add_requester(dev) == 0) {
96b0e0f6 1017 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1018 ixgbe_setup_dca(adapter);
1019 break;
1020 }
1021 /* Fall Through since DCA is disabled. */
1022 case DCA_PROVIDER_REMOVE:
1023 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1024 dca_remove_requester(dev);
1025 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1026 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1027 }
1028 break;
1029 }
1030
652f093f 1031 return 0;
bd0362dd 1032}
5dd2d332 1033#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 1034
1035static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1036 struct sk_buff *skb)
1037{
1038 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1039}
1040
9a799d71
AK		 1041/**
1042 * ixgbe_receive_skb - Send a completed packet up the stack
1043 * @adapter: board private structure
1044 * @skb: packet to send up
177db6ff
MC		 1045 * @status: hardware indication of status of receive
1046 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1047 * @rx_desc: rx descriptor
9a799d71 1048 **/
78b6f4ce 1049static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1050 struct sk_buff *skb, u8 status,
1051 struct ixgbe_ring *ring,
1052 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1053{
78b6f4ce
HX		 1054 struct ixgbe_adapter *adapter = q_vector->adapter;
1055 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1056 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1057 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1058
f62bbb5e
JG		 1059 if (is_vlan && (tag & VLAN_VID_MASK))
1060 __vlan_hwaccel_put_tag(skb, tag);
1061
1062 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1063 napi_gro_receive(napi, skb);
1064 else
1065 netif_rx(skb);
9a799d71
AK		 1066}
1067
e59bd25d
AV		 1068/**
1069 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1070 * @adapter: address of board private structure
1071 * @status_err: hardware indication of status of receive
1072 * @skb: skb currently being received and modified
1073 **/
9a799d71 1074static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1075 union ixgbe_adv_rx_desc *rx_desc,
1076 struct sk_buff *skb)
9a799d71 1077{
8bae1b2b
DS		 1078 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1079
bc8acf2c 1080 skb_checksum_none_assert(skb);
9a799d71 1081
712744be
JB		 1082 /* Rx csum disabled */
1083 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1084 return;
e59bd25d
AV		 1085
1086 /* if IP and error */
1087 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1088 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1089 adapter->hw_csum_rx_error++;
1090 return;
1091 }
e59bd25d
AV		 1092
1093 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1094 return;
1095
1096 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1097 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1098
1099 /*
1100 * 82599 errata, UDP frames with a 0 checksum can be marked as
1101 * checksum errors.
1102 */
1103 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1104 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1105 return;
1106
e59bd25d
AV		 1107 adapter->hw_csum_rx_error++;
1108 return;
1109 }
1110
9a799d71 1111 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1112 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1113}
1114
84ea2591 1115static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1116{
1117 /*
1118 * Force memory writes to complete before letting h/w
1119 * know there are new descriptors to fetch. (Only
1120 * applicable for weak-ordered memory model archs,
1121 * such as IA-64).
1122 */
1123 wmb();
84ea2591 1124 writel(val, rx_ring->tail);
e8e26350
PW		 1125}
1126
9a799d71
AK		 1127/**
1128 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1129 * @rx_ring: ring to place buffers on
1130 * @cleaned_count: number of buffers to replace
9a799d71 1131 **/
fc77dc3c 1132void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1133{
9a799d71 1134 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1135 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1136 struct sk_buff *skb;
1137 u16 i = rx_ring->next_to_use;
9a799d71 1138
fc77dc3c
AD		 1139 /* do nothing if no valid netdev defined */
1140 if (!rx_ring->netdev)
1141 return;
1142
9a799d71 1143 while (cleaned_count--) {
31f05a2d 1144 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1145 bi = &rx_ring->rx_buffer_info[i];
1146 skb = bi->skb;
9a799d71 1147
d5f398ed 1148 if (!skb) {
fc77dc3c 1149 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1150 rx_ring->rx_buf_len);
9a799d71 1151 if (!skb) {
5b7da515 1152 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1153 goto no_buffers;
1154 }
d716a7d8
AD		 1155 /* initialize queue mapping */
1156 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1157 bi->skb = skb;
d716a7d8 1158 }
9a799d71 1159
d716a7d8 1160 if (!bi->dma) {
b6ec895e 1161 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1162 skb->data,
e8e9f696 1163 rx_ring->rx_buf_len,
1b507730 1164 DMA_FROM_DEVICE);
b6ec895e 1165 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1166 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1167 bi->dma = 0;
1168 goto no_buffers;
1169 }
9a799d71 1170 }
d5f398ed 1171
7d637bcc 1172 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1173 if (!bi->page) {
fc77dc3c 1174 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1175 if (!bi->page) {
5b7da515 1176 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1177 goto no_buffers;
1178 }
1179 }
1180
1181 if (!bi->page_dma) {
1182 /* use a half page if we're re-using */
1183 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1184 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1185 bi->page,
1186 bi->page_offset,
1187 PAGE_SIZE / 2,
1188 DMA_FROM_DEVICE);
b6ec895e 1189 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1190 bi->page_dma)) {
5b7da515 1191 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1192 bi->page_dma = 0;
1193 goto no_buffers;
1194 }
1195 }
1196
1197 /* Refresh the desc even if buffer_addrs didn't change
1198 * because each write-back erases this info. */
3a581073
JB		 1199 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1200 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1201 } else {
3a581073 1202 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1203 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1204 }
1205
1206 i++;
1207 if (i == rx_ring->count)
1208 i = 0;
9a799d71 1209 }
7c6e0a43 1210
9a799d71
AK		 1211no_buffers:
1212 if (rx_ring->next_to_use != i) {
1213 rx_ring->next_to_use = i;
84ea2591 1214 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1215 }
1216}
1217
c267fc16 1218static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1219{
c267fc16
AD		 1220 /* HW will not DMA in data larger than the given buffer, even if it
1221 * parses the (NFS, of course) header to be larger. In that case, it
1222 * fills the header buffer and spills the rest into the page.
1223 */
1224 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1225 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1226 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1227 if (hlen > IXGBE_RX_HDR_SIZE)
1228 hlen = IXGBE_RX_HDR_SIZE;
1229 return hlen;
7c6e0a43
JB		 1230}
1231
f8212f97
AD		 1232/**
1233 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1234 * @skb: pointer to the last skb in the rsc queue
1235 *
1236 * This function changes a queue full of hw rsc buffers into a completed
1237 * packet. It uses the ->prev pointers to find the first packet and then
1238 * turns it into the frag list owner.
1239 **/
aa80175a 1240static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1241{
1242 unsigned int frag_list_size = 0;
aa80175a 1243 unsigned int skb_cnt = 1;
f8212f97
AD		 1244
1245 while (skb->prev) {
1246 struct sk_buff *prev = skb->prev;
1247 frag_list_size += skb->len;
1248 skb->prev = NULL;
1249 skb = prev;
aa80175a 1250 skb_cnt++;
f8212f97
AD		 1251 }
1252
1253 skb_shinfo(skb)->frag_list = skb->next;
1254 skb->next = NULL;
1255 skb->len += frag_list_size;
1256 skb->data_len += frag_list_size;
1257 skb->truesize += frag_list_size;
aa80175a
AD		 1258 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1259
f8212f97
AD		 1260 return skb;
1261}
1262
aa80175a
AD		 1263static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1264{
1265 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1266 IXGBE_RXDADV_RSCCNT_MASK);
1267}
43634e82 1268
c267fc16 1269static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1270 struct ixgbe_ring *rx_ring,
1271 int *work_done, int work_to_do)
9a799d71 1272{
78b6f4ce 1273 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1274 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1275 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1276 struct sk_buff *skb;
d2f4fbe2 1277 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1278 const int current_node = numa_node_id();
3d8fd385
YZ		 1279#ifdef IXGBE_FCOE
1280 int ddp_bytes = 0;
1281#endif /* IXGBE_FCOE */
c267fc16
AD		 1282 u32 staterr;
1283 u16 i;
1284 u16 cleaned_count = 0;
aa80175a 1285 bool pkt_is_rsc = false;
9a799d71
AK		 1286
1287 i = rx_ring->next_to_clean;
31f05a2d 1288 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1289 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1290
1291 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1292 u32 upper_len = 0;
9a799d71 1293
3c945e5b 1294 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1295
c267fc16
AD		 1296 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1297
9a799d71 1298 skb = rx_buffer_info->skb;
9a799d71 1299 rx_buffer_info->skb = NULL;
c267fc16 1300 prefetch(skb->data);
9a799d71 1301
c267fc16 1302 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1303 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1304
1305 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1306 if (rx_buffer_info->dma) {
c267fc16 1307 u16 hlen;
aa80175a 1308 if (pkt_is_rsc &&
c267fc16
AD		 1309 !(staterr & IXGBE_RXD_STAT_EOP) &&
1310 !skb->prev) {
43634e82
MC		 1311 /*
1312 * When HWRSC is enabled, delay unmapping
1313 * of the first packet. It carries the
1314 * header information, HW may still
1315 * access the header after the writeback.
1316 * Only unmap it when EOP is reached
1317 */
e8171aaa 1318 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1319 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1320 } else {
b6ec895e 1321 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1322 rx_buffer_info->dma,
1323 rx_ring->rx_buf_len,
1324 DMA_FROM_DEVICE);
e8171aaa 1325 }
4f57ca6e 1326 rx_buffer_info->dma = 0;
c267fc16
AD		 1327
1328 if (ring_is_ps_enabled(rx_ring)) {
1329 hlen = ixgbe_get_hlen(rx_desc);
1330 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1331 } else {
1332 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1333 }
1334
1335 skb_put(skb, hlen);
1336 } else {
1337 /* assume packet split since header is unmapped */
1338 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1339 }
1340
1341 if (upper_len) {
b6ec895e
AD		 1342 dma_unmap_page(rx_ring->dev,
1343 rx_buffer_info->page_dma,
1344 PAGE_SIZE / 2,
1345 DMA_FROM_DEVICE);
9a799d71
AK		 1346 rx_buffer_info->page_dma = 0;
1347 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1348 rx_buffer_info->page,
1349 rx_buffer_info->page_offset,
1350 upper_len);
762f4c57 1351
c267fc16
AD		 1352 if ((page_count(rx_buffer_info->page) == 1) &&
1353 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1354 get_page(rx_buffer_info->page);
c267fc16
AD		 1355 else
1356 rx_buffer_info->page = NULL;
9a799d71
AK		 1357
1358 skb->len += upper_len;
1359 skb->data_len += upper_len;
1360 skb->truesize += upper_len;
1361 }
1362
1363 i++;
1364 if (i == rx_ring->count)
1365 i = 0;
9a799d71 1366
31f05a2d 1367 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1368 prefetch(next_rxd);
9a799d71 1369 cleaned_count++;
f8212f97 1370
aa80175a 1371 if (pkt_is_rsc) {
f8212f97
AD		 1372 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1373 IXGBE_RXDADV_NEXTP_SHIFT;
1374 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1375 } else {
1376 next_buffer = &rx_ring->rx_buffer_info[i];
1377 }
1378
c267fc16 1379 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1380 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1381 rx_buffer_info->skb = next_buffer->skb;
1382 rx_buffer_info->dma = next_buffer->dma;
1383 next_buffer->skb = skb;
1384 next_buffer->dma = 0;
1385 } else {
1386 skb->next = next_buffer->skb;
1387 skb->next->prev = skb;
1388 }
5b7da515 1389 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1390 goto next_desc;
1391 }
1392
aa80175a
AD		 1393 if (skb->prev) {
1394 skb = ixgbe_transform_rsc_queue(skb);
1395 /* if we got here without RSC the packet is invalid */
1396 if (!pkt_is_rsc) {
1397 __pskb_trim(skb, 0);
1398 rx_buffer_info->skb = skb;
1399 goto next_desc;
1400 }
1401 }
c267fc16
AD		 1402
1403 if (ring_is_rsc_enabled(rx_ring)) {
1404 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1405 dma_unmap_single(rx_ring->dev,
1406 IXGBE_RSC_CB(skb)->dma,
1407 rx_ring->rx_buf_len,
1408 DMA_FROM_DEVICE);
1409 IXGBE_RSC_CB(skb)->dma = 0;
1410 IXGBE_RSC_CB(skb)->delay_unmap = false;
1411 }
aa80175a
AD		 1412 }
1413 if (pkt_is_rsc) {
c267fc16
AD		 1414 if (ring_is_ps_enabled(rx_ring))
1415 rx_ring->rx_stats.rsc_count +=
aa80175a 1416 skb_shinfo(skb)->nr_frags;
c267fc16 1417 else
aa80175a
AD		 1418 rx_ring->rx_stats.rsc_count +=
1419 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1420 rx_ring->rx_stats.rsc_flush++;
1421 }
1422
1423 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1424 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1425 /* trim packet back to size 0 and recycle it */
1426 __pskb_trim(skb, 0);
1427 rx_buffer_info->skb = skb;
9a799d71
AK		 1428 goto next_desc;
1429 }
1430
8bae1b2b 1431 ixgbe_rx_checksum(adapter, rx_desc, skb);
67a74ee2
ET		 1432 if (adapter->netdev->features & NETIF_F_RXHASH)
1433 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1434
1435 /* probably a little skewed due to removing CRC */
1436 total_rx_bytes += skb->len;
1437 total_rx_packets++;
1438
fc77dc3c 1439 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1440#ifdef IXGBE_FCOE
1441 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1442 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1443 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1444 if (!ddp_bytes)
332d4a7d 1445 goto next_desc;
3d8fd385 1446 }
332d4a7d 1447#endif /* IXGBE_FCOE */
fdaff1ce 1448 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1449
1450next_desc:
1451 rx_desc->wb.upper.status_error = 0;
1452
c267fc16
AD		 1453 (*work_done)++;
1454 if (*work_done >= work_to_do)
1455 break;
1456
9a799d71
AK		 1457 /* return some buffers to hardware, one at a time is too slow */
1458 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1459 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1460 cleaned_count = 0;
1461 }
1462
1463 /* use prefetched values */
1464 rx_desc = next_rxd;
9a799d71 1465 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1466 }
1467
9a799d71 1468 rx_ring->next_to_clean = i;
7d4987de 1469 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1470
1471 if (cleaned_count)
fc77dc3c 1472 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1473
3d8fd385
YZ		 1474#ifdef IXGBE_FCOE
1475 /* include DDPed FCoE data */
1476 if (ddp_bytes > 0) {
1477 unsigned int mss;
1478
fc77dc3c 1479 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1480 sizeof(struct fc_frame_header) -
1481 sizeof(struct fcoe_crc_eof);
1482 if (mss > 512)
1483 mss &= ~511;
1484 total_rx_bytes += ddp_bytes;
1485 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1486 }
1487#endif /* IXGBE_FCOE */
1488
f494e8fa
AV		 1489 rx_ring->total_packets += total_rx_packets;
1490 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1491 u64_stats_update_begin(&rx_ring->syncp);
1492 rx_ring->stats.packets += total_rx_packets;
1493 rx_ring->stats.bytes += total_rx_bytes;
1494 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1495}
1496
021230d4 1497static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1498/**
1499 * ixgbe_configure_msix - Configure MSI-X hardware
1500 * @adapter: board private structure
1501 *
1502 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1503 * interrupts.
1504 **/
1505static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1506{
021230d4 1507 struct ixgbe_q_vector *q_vector;
bf29ee6c 1508 int i, q_vectors, v_idx, r_idx;
021230d4 1509 u32 mask;
9a799d71 1510
021230d4 1511 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1512
4df10466
JB		 1513 /*
1514 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1515 * corresponding register.
1516 */
1517 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1518 q_vector = adapter->q_vector[v_idx];
984b3f57 1519 /* XXX for_each_set_bit(...) */
021230d4 1520 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1521 adapter->num_rx_queues);
021230d4
AV		 1522
1523 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1524 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1525 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1526 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1527 adapter->num_rx_queues,
1528 r_idx + 1);
021230d4
AV		 1529 }
1530 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1531 adapter->num_tx_queues);
021230d4
AV		 1532
1533 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1534 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1535 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1536 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1537 adapter->num_tx_queues,
1538 r_idx + 1);
021230d4
AV		 1539 }
1540
021230d4 1541 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1542 /* tx only */
1543 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1544 else if (q_vector->rxr_count)
f7554a2b
NS		 1545 /* rx or mixed */
1546 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1547
fe49f04a 1548 ixgbe_write_eitr(q_vector);
03ecf91a
AD		 1549 /* If ATR is enabled, set interrupt affinity */
1550 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
b25ebfd2
PW		 1551 /*
1552 * Allocate the affinity_hint cpumask, assign the mask
1553 * for this vector, and set our affinity_hint for
1554 * this irq.
1555 */
1556 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1557 GFP_KERNEL))
1558 return;
1559 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1560 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1561 q_vector->affinity_mask);
1562 }
9a799d71
AK		 1563 }
1564
bd508178
AD		 1565 switch (adapter->hw.mac.type) {
1566 case ixgbe_mac_82598EB:
e8e26350 1567 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1568 v_idx);
bd508178
AD		 1569 break;
1570 case ixgbe_mac_82599EB:
b93a2226 1571 case ixgbe_mac_X540:
e8e26350 1572 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1573 break;
1574
1575 default:
1576 break;
1577 }
021230d4
AV		 1578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1579
41fb9248 1580 /* set up to autoclear timer, and the vectors */
021230d4 1581 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1582 if (adapter->num_vfs)
1583 mask &= ~(IXGBE_EIMS_OTHER |
1584 IXGBE_EIMS_MAILBOX |
1585 IXGBE_EIMS_LSC);
1586 else
1587 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1588 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1589}
1590
f494e8fa
AV		 1591enum latency_range {
1592 lowest_latency = 0,
1593 low_latency = 1,
1594 bulk_latency = 2,
1595 latency_invalid = 255
1596};
1597
1598/**
1599 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1600 * @adapter: pointer to adapter
1601 * @eitr: eitr setting (ints per sec) to give last timeslice
1602 * @itr_setting: current throttle rate in ints/second
1603 * @packets: the number of packets during this measurement interval
1604 * @bytes: the number of bytes during this measurement interval
1605 *
1606 * Stores a new ITR value based on packets and byte
1607 * counts during the last interrupt. The advantage of per interrupt
1608 * computation is faster updates and more accurate ITR for the current
1609 * traffic pattern. Constants in this function were computed
1610 * based on theoretical maximum wire speed and thresholds were set based
1611 * on testing data as well as attempting to minimize response time
1612 * while increasing bulk throughput.
1613 * this functionality is controlled by the InterruptThrottleRate module
1614 * parameter (see ixgbe_param.c)
1615 **/
1616static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1617 u32 eitr, u8 itr_setting,
1618 int packets, int bytes)
f494e8fa
AV		 1619{
1620 unsigned int retval = itr_setting;
1621 u32 timepassed_us;
1622 u64 bytes_perint;
1623
1624 if (packets == 0)
1625 goto update_itr_done;
1626
1627
1628 /* simple throttlerate management
1629 * 0-20MB/s lowest (100000 ints/s)
1630 * 20-100MB/s low (20000 ints/s)
1631 * 100-1249MB/s bulk (8000 ints/s)
1632 */
1633 /* what was last interrupt timeslice? */
1634 timepassed_us = 1000000/eitr;
1635 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1636
1637 switch (itr_setting) {
1638 case lowest_latency:
1639 if (bytes_perint > adapter->eitr_low)
1640 retval = low_latency;
1641 break;
1642 case low_latency:
1643 if (bytes_perint > adapter->eitr_high)
1644 retval = bulk_latency;
1645 else if (bytes_perint <= adapter->eitr_low)
1646 retval = lowest_latency;
1647 break;
1648 case bulk_latency:
1649 if (bytes_perint <= adapter->eitr_high)
1650 retval = low_latency;
1651 break;
1652 }
1653
1654update_itr_done:
1655 return retval;
1656}
1657
509ee935
JB		 1658/**
1659 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1660 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1661 *
1662 * This function is made to be called by ethtool and by the driver
1663 * when it needs to update EITR registers at runtime. Hardware
1664 * specific quirks/differences are taken care of here.
1665 */
fe49f04a 1666void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1667{
fe49f04a 1668 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1669 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1670 int v_idx = q_vector->v_idx;
1671 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1672
bd508178
AD		 1673 switch (adapter->hw.mac.type) {
1674 case ixgbe_mac_82598EB:
509ee935
JB		 1675 /* must write high and low 16 bits to reset counter */
1676 itr_reg |= (itr_reg << 16);
bd508178
AD		 1677 break;
1678 case ixgbe_mac_82599EB:
b93a2226 1679 case ixgbe_mac_X540:
f8d1dcaf 1680 /*
b93a2226 1681 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1682 * max interrupt rate, but there is an errata where it can
1683 * not be zero with RSC
1684 */
1685 if (itr_reg == 8 &&
1686 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1687 itr_reg = 0;
1688
509ee935
JB		 1689 /*
1690 * set the WDIS bit to not clear the timer bits and cause an
1691 * immediate assertion of the interrupt
1692 */
1693 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1694 break;
1695 default:
1696 break;
509ee935
JB		 1697 }
1698 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1699}
1700
f494e8fa
AV		 1701static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1702{
1703 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1704 int i, r_idx;
f494e8fa
AV		 1705 u32 new_itr;
1706 u8 current_itr, ret_itr;
f494e8fa
AV		 1707
1708 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1709 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1710 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1711 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1712 q_vector->tx_itr,
1713 tx_ring->total_packets,
1714 tx_ring->total_bytes);
f494e8fa
AV		 1715 /* if the result for this queue would decrease interrupt
1716 * rate for this vector then use that result */
30efa5a3 1717 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1718 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1719 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1720 r_idx + 1);
f494e8fa
AV		 1721 }
1722
1723 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1724 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1725 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1726 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1727 q_vector->rx_itr,
1728 rx_ring->total_packets,
1729 rx_ring->total_bytes);
f494e8fa
AV		 1730 /* if the result for this queue would decrease interrupt
1731 * rate for this vector then use that result */
30efa5a3 1732 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1733 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1734 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1735 r_idx + 1);
f494e8fa
AV		 1736 }
1737
30efa5a3 1738 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1739
1740 switch (current_itr) {
1741 /* counts and packets in update_itr are dependent on these numbers */
1742 case lowest_latency:
1743 new_itr = 100000;
1744 break;
1745 case low_latency:
1746 new_itr = 20000; /* aka hwitr = ~200 */
1747 break;
1748 case bulk_latency:
1749 default:
1750 new_itr = 8000;
1751 break;
1752 }
1753
1754 if (new_itr != q_vector->eitr) {
fe49f04a 1755 /* do an exponential smoothing */
125601bf 1756 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1757
1758 /* save the algorithm value here, not the smoothed one */
1759 q_vector->eitr = new_itr;
fe49f04a
AD		 1760
1761 ixgbe_write_eitr(q_vector);
f494e8fa 1762 }
f494e8fa
AV		 1763}
1764
119fc60a 1765/**
f0f9778d
AD		 1766 * ixgbe_check_overtemp_subtask - check for over tempurature
1767 * @adapter: pointer to adapter
119fc60a 1768 **/
f0f9778d 1769static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1770{
119fc60a
MC		 1771 struct ixgbe_hw *hw = &adapter->hw;
1772 u32 eicr = adapter->interrupt_event;
1773
f0f9778d 1774 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1775 return;
1776
f0f9778d
AD		 1777 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1778 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1779 return;
1780
1781 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1782
7ca647bd 1783 switch (hw->device_id) {
f0f9778d
AD		 1784 case IXGBE_DEV_ID_82599_T3_LOM:
1785 /*
1786 * Since the warning interrupt is for both ports
1787 * we don't have to check if:
1788 * - This interrupt wasn't for our port.
1789 * - We may have missed the interrupt so always have to
1790 * check if we got a LSC
1791 */
1792 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1793 !(eicr & IXGBE_EICR_LSC))
1794 return;
1795
1796 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1797 u32 autoneg;
1798 bool link_up = false;
7ca647bd 1799
7ca647bd
JP		 1800 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1801
f0f9778d
AD		 1802 if (link_up)
1803 return;
1804 }
1805
1806 /* Check if this is not due to overtemp */
1807 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1808 return;
1809
1810 break;
7ca647bd
JP		 1811 default:
1812 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1813 return;
7ca647bd 1814 break;
119fc60a 1815 }
7ca647bd
JP		 1816 e_crit(drv,
1817 "Network adapter has been stopped because it has over heated. "
1818 "Restart the computer. If the problem persists, "
1819 "power off the system and replace the adapter\n");
f0f9778d
AD		 1820
1821 adapter->interrupt_event = 0;
119fc60a
MC		 1822}
1823
0befdb3e
JB		 1824static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1825{
1826 struct ixgbe_hw *hw = &adapter->hw;
1827
1828 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1829 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1830 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1831 /* write to clear the interrupt */
1832 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1833 }
1834}
cf8280ee 1835
e8e26350
PW		 1836static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1837{
1838 struct ixgbe_hw *hw = &adapter->hw;
1839
73c4b7cd
AD		 1840 if (eicr & IXGBE_EICR_GPI_SDP2) {
1841 /* Clear the interrupt */
1842 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1843 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1844 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1845 ixgbe_service_event_schedule(adapter);
1846 }
73c4b7cd
AD		 1847 }
1848
e8e26350
PW		 1849 if (eicr & IXGBE_EICR_GPI_SDP1) {
1850 /* Clear the interrupt */
1851 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1852 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1853 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1854 ixgbe_service_event_schedule(adapter);
1855 }
e8e26350
PW		 1856 }
1857}
1858
cf8280ee
JB		 1859static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1860{
1861 struct ixgbe_hw *hw = &adapter->hw;
1862
1863 adapter->lsc_int++;
1864 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1865 adapter->link_check_timeout = jiffies;
1866 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1867 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1868 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1869 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1870 }
1871}
1872
9a799d71
AK		 1873static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1874{
a65151ba 1875 struct ixgbe_adapter *adapter = data;
9a799d71 1876 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1877 u32 eicr;
1878
1879 /*
1880 * Workaround for Silicon errata. Use clear-by-write instead
1881 * of clear-by-read. Reading with EICS will return the
1882 * interrupt causes without clearing, which later be done
1883 * with the write to EICR.
1884 */
1885 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1886 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1887
cf8280ee
JB		 1888 if (eicr & IXGBE_EICR_LSC)
1889 ixgbe_check_lsc(adapter);
d4f80882 1890
1cdd1ec8
GR		 1891 if (eicr & IXGBE_EICR_MAILBOX)
1892 ixgbe_msg_task(adapter);
1893
bd508178
AD		 1894 switch (hw->mac.type) {
1895 case ixgbe_mac_82599EB:
b93a2226 1896 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1897 /* Handle Flow Director Full threshold interrupt */
1898 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1899 int reinit_count = 0;
c4cf55e5 1900 int i;
c4cf55e5 1901 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1902 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1903 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1904 &ring->state))
1905 reinit_count++;
1906 }
1907 if (reinit_count) {
1908 /* no more flow director interrupts until after init */
1909 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1910 eicr &= ~IXGBE_EICR_FLOW_DIR;
1911 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1912 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1913 }
1914 }
f0f9778d
AD		 1915 ixgbe_check_sfp_event(adapter, eicr);
1916 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1917 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1918 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1919 adapter->interrupt_event = eicr;
1920 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1921 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1922 }
1923 }
bd508178
AD		 1924 break;
1925 default:
1926 break;
c4cf55e5 1927 }
bd508178
AD		 1928
1929 ixgbe_check_fan_failure(adapter, eicr);
1930
7086400d 1931 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1932 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7086400d
AD		 1933 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1934 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
9a799d71
AK		 1935
1936 return IRQ_HANDLED;
1937}
1938
fe49f04a
AD		 1939static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1940 u64 qmask)
1941{
1942 u32 mask;
bd508178 1943 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1944
bd508178
AD		 1945 switch (hw->mac.type) {
1946 case ixgbe_mac_82598EB:
fe49f04a 1947 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1948 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1949 break;
1950 case ixgbe_mac_82599EB:
b93a2226 1951 case ixgbe_mac_X540:
fe49f04a 1952 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1953 if (mask)
1954 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1955 mask = (qmask >> 32);
bd508178
AD		 1956 if (mask)
1957 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1958 break;
1959 default:
1960 break;
fe49f04a
AD		 1961 }
1962 /* skip the flush */
1963}
1964
1965static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1966 u64 qmask)
fe49f04a
AD		 1967{
1968 u32 mask;
bd508178 1969 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1970
bd508178
AD		 1971 switch (hw->mac.type) {
1972 case ixgbe_mac_82598EB:
fe49f04a 1973 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1974 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1975 break;
1976 case ixgbe_mac_82599EB:
b93a2226 1977 case ixgbe_mac_X540:
fe49f04a 1978 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1979 if (mask)
1980 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1981 mask = (qmask >> 32);
bd508178
AD		 1982 if (mask)
1983 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1984 break;
1985 default:
1986 break;
fe49f04a
AD		 1987 }
1988 /* skip the flush */
1989}
1990
9a799d71
AK		 1991static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1992{
021230d4
AV		 1993 struct ixgbe_q_vector *q_vector = data;
1994 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1995 struct ixgbe_ring *tx_ring;
021230d4
AV		 1996 int i, r_idx;
1997
1998 if (!q_vector->txr_count)
1999 return IRQ_HANDLED;
2000
2001 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2002 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2003 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 2004 tx_ring->total_bytes = 0;
2005 tx_ring->total_packets = 0;
021230d4 2006 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2007 r_idx + 1);
021230d4 2008 }
9a799d71 2009
9b471446 2010 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2011 napi_schedule(&q_vector->napi);
2012
9a799d71
AK		 2013 return IRQ_HANDLED;
2014}
2015
021230d4
AV		 2016/**
2017 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2018 * @irq: unused
2019 * @data: pointer to our q_vector struct for this interrupt vector
2020 **/
9a799d71
AK		 2021static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2022{
021230d4
AV		 2023 struct ixgbe_q_vector *q_vector = data;
2024 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2025 struct ixgbe_ring *rx_ring;
021230d4 2026 int r_idx;
30efa5a3 2027 int i;
021230d4 2028
33cf09c9
AD		 2029#ifdef CONFIG_IXGBE_DCA
2030 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2031 ixgbe_update_dca(q_vector);
2032#endif
2033
021230d4 2034 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2035 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2036 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2037 rx_ring->total_bytes = 0;
2038 rx_ring->total_packets = 0;
2039 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2040 r_idx + 1);
30efa5a3
JB		 2041 }
2042
021230d4
AV		 2043 if (!q_vector->rxr_count)
2044 return IRQ_HANDLED;
2045
9b471446 2046 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2047 napi_schedule(&q_vector->napi);
021230d4
AV		 2048
2049 return IRQ_HANDLED;
2050}
2051
2052static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2053{
91281fd3
AD		 2054 struct ixgbe_q_vector *q_vector = data;
2055 struct ixgbe_adapter *adapter = q_vector->adapter;
2056 struct ixgbe_ring *ring;
2057 int r_idx;
2058 int i;
2059
2060 if (!q_vector->txr_count && !q_vector->rxr_count)
2061 return IRQ_HANDLED;
2062
2063 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2064 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2065 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2066 ring->total_bytes = 0;
2067 ring->total_packets = 0;
2068 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2069 r_idx + 1);
91281fd3
AD		 2070 }
2071
2072 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2073 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2074 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2075 ring->total_bytes = 0;
2076 ring->total_packets = 0;
2077 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2078 r_idx + 1);
91281fd3
AD		 2079 }
2080
9b471446 2081 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2082 napi_schedule(&q_vector->napi);
9a799d71 2083
9a799d71
AK		 2084 return IRQ_HANDLED;
2085}
2086
021230d4
AV		 2087/**
2088 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2089 * @napi: napi struct with our devices info in it
2090 * @budget: amount of work driver is allowed to do this pass, in packets
2091 *
f0848276
JB		 2092 * This function is optimized for cleaning one queue only on a single
2093 * q_vector!!!
021230d4 2094 **/
9a799d71
AK		 2095static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2096{
021230d4 2097 struct ixgbe_q_vector *q_vector =
e8e9f696 2098 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2099 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2100 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2101 int work_done = 0;
021230d4 2102 long r_idx;
9a799d71 2103
5dd2d332 2104#ifdef CONFIG_IXGBE_DCA
bd0362dd 2105 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2106 ixgbe_update_dca(q_vector);
bd0362dd 2107#endif
9a799d71 2108
33cf09c9
AD		 2109 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2110 rx_ring = adapter->rx_ring[r_idx];
2111
78b6f4ce 2112 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2113
021230d4
AV		 2114 /* If all Rx work done, exit the polling mode */
2115 if (work_done < budget) {
288379f0 2116 napi_complete(napi);
f7554a2b 2117 if (adapter->rx_itr_setting & 1)
f494e8fa 2118 ixgbe_set_itr_msix(q_vector);
9a799d71 2119 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2120 ixgbe_irq_enable_queues(adapter,
e8e9f696 2121 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2122 }
2123
2124 return work_done;
2125}
2126
f0848276 2127/**
91281fd3 2128 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2129 * @napi: napi struct with our devices info in it
2130 * @budget: amount of work driver is allowed to do this pass, in packets
2131 *
2132 * This function will clean more than one rx queue associated with a
2133 * q_vector.
2134 **/
91281fd3 2135static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2136{
2137 struct ixgbe_q_vector *q_vector =
e8e9f696 2138 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2139 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2140 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2141 int work_done = 0, i;
2142 long r_idx;
91281fd3
AD		 2143 bool tx_clean_complete = true;
2144
33cf09c9
AD		 2145#ifdef CONFIG_IXGBE_DCA
2146 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2147 ixgbe_update_dca(q_vector);
2148#endif
2149
91281fd3
AD		 2150 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2151 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2152 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2153 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2154 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2155 r_idx + 1);
91281fd3 2156 }
f0848276
JB		 2157
2158 /* attempt to distribute budget to each queue fairly, but don't allow
2159 * the budget to go below 1 because we'll exit polling */
2160 budget /= (q_vector->rxr_count ?: 1);
2161 budget = max(budget, 1);
2162 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2163 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2164 ring = adapter->rx_ring[r_idx];
91281fd3 2165 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2166 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2167 r_idx + 1);
f0848276
JB		 2168 }
2169
2170 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2171 ring = adapter->rx_ring[r_idx];
f0848276 2172 /* If all Rx work done, exit the polling mode */
7f821875 2173 if (work_done < budget) {
288379f0 2174 napi_complete(napi);
f7554a2b 2175 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2176 ixgbe_set_itr_msix(q_vector);
2177 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2178 ixgbe_irq_enable_queues(adapter,
e8e9f696 2179 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2180 return 0;
2181 }
2182
2183 return work_done;
2184}
91281fd3
AD		 2185
2186/**
2187 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2188 * @napi: napi struct with our devices info in it
2189 * @budget: amount of work driver is allowed to do this pass, in packets
2190 *
2191 * This function is optimized for cleaning one queue only on a single
2192 * q_vector!!!
2193 **/
2194static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2195{
2196 struct ixgbe_q_vector *q_vector =
e8e9f696 2197 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2198 struct ixgbe_adapter *adapter = q_vector->adapter;
2199 struct ixgbe_ring *tx_ring = NULL;
2200 int work_done = 0;
2201 long r_idx;
2202
91281fd3
AD		 2203#ifdef CONFIG_IXGBE_DCA
2204 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2205 ixgbe_update_dca(q_vector);
91281fd3
AD		 2206#endif
2207
33cf09c9
AD		 2208 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2209 tx_ring = adapter->tx_ring[r_idx];
2210
91281fd3
AD		 2211 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2212 work_done = budget;
2213
f7554a2b 2214 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2215 if (work_done < budget) {
2216 napi_complete(napi);
f7554a2b 2217 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2218 ixgbe_set_itr_msix(q_vector);
2219 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2220 ixgbe_irq_enable_queues(adapter,
2221 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2222 }
2223
2224 return work_done;
2225}
2226
021230d4 2227static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2228 int r_idx)
021230d4 2229{
7a921c93 2230 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2231 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2232
2233 set_bit(r_idx, q_vector->rxr_idx);
2234 q_vector->rxr_count++;
2274543f 2235 rx_ring->q_vector = q_vector;
021230d4
AV		 2236}
2237
2238static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2239 int t_idx)
021230d4 2240{
7a921c93 2241 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2242 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2243
2244 set_bit(t_idx, q_vector->txr_idx);
2245 q_vector->txr_count++;
2274543f 2246 tx_ring->q_vector = q_vector;
021230d4
AV		 2247}
2248
9a799d71 2249/**
021230d4
AV		 2250 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2251 * @adapter: board private structure to initialize
9a799d71 2252 *
021230d4
AV		 2253 * This function maps descriptor rings to the queue-specific vectors
2254 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2255 * one vector per ring/queue, but on a constrained vector budget, we
2256 * group the rings as "efficiently" as possible. You would add new
2257 * mapping configurations in here.
9a799d71 2258 **/
d0759ebb 2259static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2260{
d0759ebb 2261 int q_vectors;
021230d4
AV		 2262 int v_start = 0;
2263 int rxr_idx = 0, txr_idx = 0;
2264 int rxr_remaining = adapter->num_rx_queues;
2265 int txr_remaining = adapter->num_tx_queues;
2266 int i, j;
2267 int rqpv, tqpv;
2268 int err = 0;
2269
2270 /* No mapping required if MSI-X is disabled. */
2271 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2272 goto out;
9a799d71 2273
d0759ebb
AD		 2274 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2275
021230d4
AV		 2276 /*
2277 * The ideal configuration...
2278 * We have enough vectors to map one per queue.
2279 */
d0759ebb 2280 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2281 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2282 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2283
021230d4
AV		 2284 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2285 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2286
9a799d71 2287 goto out;
021230d4 2288 }
9a799d71 2289
021230d4
AV		 2290 /*
2291 * If we don't have enough vectors for a 1-to-1
2292 * mapping, we'll have to group them so there are
2293 * multiple queues per vector.
2294 */
2295 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2296 for (i = v_start; i < q_vectors; i++) {
2297 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2298 for (j = 0; j < rqpv; j++) {
2299 map_vector_to_rxq(adapter, i, rxr_idx);
2300 rxr_idx++;
2301 rxr_remaining--;
2302 }
d0759ebb 2303 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2304 for (j = 0; j < tqpv; j++) {
2305 map_vector_to_txq(adapter, i, txr_idx);
2306 txr_idx++;
2307 txr_remaining--;
9a799d71 2308 }
9a799d71 2309 }
021230d4
AV		 2310out:
2311 return err;
2312}
2313
2314/**
2315 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2316 * @adapter: board private structure
2317 *
2318 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2319 * interrupts from the kernel.
2320 **/
2321static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2322{
2323 struct net_device *netdev = adapter->netdev;
2324 irqreturn_t (*handler)(int, void *);
2325 int i, vector, q_vectors, err;
e8e9f696 2326 int ri = 0, ti = 0;
021230d4
AV		 2327
2328 /* Decrement for Other and TCP Timer vectors */
2329 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2330
d0759ebb 2331 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2332 if (err)
d0759ebb 2333 return err;
021230d4 2334
d0759ebb
AD		 2335#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2336 ? &ixgbe_msix_clean_many : \
2337 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2338 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2339 NULL)
021230d4 2340 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2341 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2342 handler = SET_HANDLER(q_vector);
cb13fc20 2343
e8e9f696 2344 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2345 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2346 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2347 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2348 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2349 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2350 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2351 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2352 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2353 ti++;
d0759ebb
AD		 2354 } else {
2355 /* skip this unused q_vector */
2356 continue;
32aa77a4 2357 }
021230d4 2358 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2359 handler, 0, q_vector->name,
2360 q_vector);
9a799d71 2361 if (err) {
396e799c 2362 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2363 "Error: %d\n", err);
021230d4 2364 goto free_queue_irqs;
9a799d71 2365 }
9a799d71
AK		 2366 }
2367
d0759ebb 2368 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2369 err = request_irq(adapter->msix_entries[vector].vector,
a65151ba 2370 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
9a799d71 2371 if (err) {
396e799c 2372 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2373 goto free_queue_irqs;
9a799d71
AK		 2374 }
2375
9a799d71
AK		 2376 return 0;
2377
021230d4
AV		 2378free_queue_irqs:
2379 for (i = vector - 1; i >= 0; i--)
2380 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2381 adapter->q_vector[i]);
021230d4
AV		 2382 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2383 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2384 kfree(adapter->msix_entries);
2385 adapter->msix_entries = NULL;
9a799d71
AK		 2386 return err;
2387}
2388
f494e8fa
AV		 2389static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2390{
7a921c93 2391 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2392 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2393 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2394 u32 new_itr = q_vector->eitr;
2395 u8 current_itr;
f494e8fa 2396
30efa5a3 2397 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2398 q_vector->tx_itr,
2399 tx_ring->total_packets,
2400 tx_ring->total_bytes);
30efa5a3 2401 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2402 q_vector->rx_itr,
2403 rx_ring->total_packets,
2404 rx_ring->total_bytes);
f494e8fa 2405
30efa5a3 2406 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2407
2408 switch (current_itr) {
2409 /* counts and packets in update_itr are dependent on these numbers */
2410 case lowest_latency:
2411 new_itr = 100000;
2412 break;
2413 case low_latency:
2414 new_itr = 20000; /* aka hwitr = ~200 */
2415 break;
2416 case bulk_latency:
2417 new_itr = 8000;
2418 break;
2419 default:
2420 break;
2421 }
2422
2423 if (new_itr != q_vector->eitr) {
fe49f04a 2424 /* do an exponential smoothing */
125601bf 2425 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2426
125601bf 2427 /* save the algorithm value here */
509ee935 2428 q_vector->eitr = new_itr;
fe49f04a
AD		 2429
2430 ixgbe_write_eitr(q_vector);
f494e8fa 2431 }
f494e8fa
AV		 2432}
2433
79aefa45
AD		 2434/**
2435 * ixgbe_irq_enable - Enable default interrupt generation settings
2436 * @adapter: board private structure
2437 **/
6af3b9eb
ET		 2438static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2439 bool flush)
79aefa45
AD		 2440{
2441 u32 mask;
835462fc
NS		 2442
2443 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2444 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2445 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2446 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2447 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2448 switch (adapter->hw.mac.type) {
2449 case ixgbe_mac_82599EB:
b93a2226 2450 case ixgbe_mac_X540:
2a41ff81 2451 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2452 mask |= IXGBE_EIMS_GPI_SDP1;
2453 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2454 if (adapter->num_vfs)
2455 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2456 break;
2457 default:
2458 break;
e8e26350 2459 }
03ecf91a 2460 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
c4cf55e5 2461 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2462
79aefa45 2463 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2464 if (queues)
2465 ixgbe_irq_enable_queues(adapter, ~0);
2466 if (flush)
2467 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2468
2469 if (adapter->num_vfs > 32) {
2470 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2471 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2472 }
79aefa45 2473}
021230d4 2474
9a799d71 2475/**
021230d4 2476 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2477 * @irq: interrupt number
2478 * @data: pointer to a network interface device structure
9a799d71
AK		 2479 **/
2480static irqreturn_t ixgbe_intr(int irq, void *data)
2481{
a65151ba 2482 struct ixgbe_adapter *adapter = data;
9a799d71 2483 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2484 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2485 u32 eicr;
2486
54037505 2487 /*
6af3b9eb 2488 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2489 * before the read of EICR.
2490 */
2491 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2492
021230d4
AV		 2493 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2494 * therefore no explict interrupt disable is necessary */
2495 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2496 if (!eicr) {
6af3b9eb
ET		 2497 /*
2498 * shared interrupt alert!
f47cf66e 2499 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2500 * have disabled interrupts due to EIAM
2501 * finish the workaround of silicon errata on 82598. Unmask
2502 * the interrupt that we masked before the EICR read.
2503 */
2504 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2505 ixgbe_irq_enable(adapter, true, true);
9a799d71 2506 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2507 }
9a799d71 2508
cf8280ee
JB		 2509 if (eicr & IXGBE_EICR_LSC)
2510 ixgbe_check_lsc(adapter);
021230d4 2511
bd508178
AD		 2512 switch (hw->mac.type) {
2513 case ixgbe_mac_82599EB:
e8e26350 2514 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2515 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2516 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
f0f9778d
AD		 2517 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2518 adapter->interrupt_event = eicr;
2519 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2520 ixgbe_service_event_schedule(adapter);
2521 }
bd508178
AD		 2522 }
2523 break;
2524 default:
2525 break;
2526 }
e8e26350 2527
0befdb3e
JB		 2528 ixgbe_check_fan_failure(adapter, eicr);
2529
7a921c93 2530 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2531 adapter->tx_ring[0]->total_packets = 0;
2532 adapter->tx_ring[0]->total_bytes = 0;
2533 adapter->rx_ring[0]->total_packets = 0;
2534 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2535 /* would disable interrupts here but EIAM disabled it */
7a921c93 2536 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2537 }
2538
6af3b9eb
ET		 2539 /*
2540 * re-enable link(maybe) and non-queue interrupts, no flush.
2541 * ixgbe_poll will re-enable the queue interrupts
2542 */
2543
2544 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2545 ixgbe_irq_enable(adapter, false, false);
2546
9a799d71
AK		 2547 return IRQ_HANDLED;
2548}
2549
021230d4
AV		 2550static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2551{
2552 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2553
2554 for (i = 0; i < q_vectors; i++) {
7a921c93 2555 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2556 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2557 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2558 q_vector->rxr_count = 0;
2559 q_vector->txr_count = 0;
2560 }
2561}
2562
9a799d71
AK		 2563/**
2564 * ixgbe_request_irq - initialize interrupts
2565 * @adapter: board private structure
2566 *
2567 * Attempts to configure interrupts using the best available
2568 * capabilities of the hardware and kernel.
2569 **/
021230d4 2570static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2571{
2572 struct net_device *netdev = adapter->netdev;
021230d4 2573 int err;
9a799d71 2574
021230d4
AV		 2575 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2576 err = ixgbe_request_msix_irqs(adapter);
2577 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2578 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2579 netdev->name, adapter);
021230d4 2580 } else {
a0607fd3 2581 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2582 netdev->name, adapter);
9a799d71
AK		 2583 }
2584
9a799d71 2585 if (err)
396e799c 2586 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2587
9a799d71
AK		 2588 return err;
2589}
2590
2591static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2592{
9a799d71 2593 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2594 int i, q_vectors;
9a799d71 2595
021230d4
AV		 2596 q_vectors = adapter->num_msix_vectors;
2597
2598 i = q_vectors - 1;
a65151ba 2599 free_irq(adapter->msix_entries[i].vector, adapter);
9a799d71 2600
021230d4
AV		 2601 i--;
2602 for (; i >= 0; i--) {
894ff7cf
AD		 2603 /* free only the irqs that were actually requested */
2604 if (!adapter->q_vector[i]->rxr_count &&
2605 !adapter->q_vector[i]->txr_count)
2606 continue;
2607
021230d4 2608 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2609 adapter->q_vector[i]);
021230d4
AV		 2610 }
2611
2612 ixgbe_reset_q_vectors(adapter);
2613 } else {
a65151ba 2614 free_irq(adapter->pdev->irq, adapter);
9a799d71
AK		 2615 }
2616}
2617
22d5a71b
JB		 2618/**
2619 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2620 * @adapter: board private structure
2621 **/
2622static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2623{
bd508178
AD		 2624 switch (adapter->hw.mac.type) {
2625 case ixgbe_mac_82598EB:
835462fc 2626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2627 break;
2628 case ixgbe_mac_82599EB:
b93a2226 2629 case ixgbe_mac_X540:
835462fc
NS		 2630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2631 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2633 if (adapter->num_vfs > 32)
2634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2635 break;
2636 default:
2637 break;
22d5a71b
JB		 2638 }
2639 IXGBE_WRITE_FLUSH(&adapter->hw);
2640 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2641 int i;
2642 for (i = 0; i < adapter->num_msix_vectors; i++)
2643 synchronize_irq(adapter->msix_entries[i].vector);
2644 } else {
2645 synchronize_irq(adapter->pdev->irq);
2646 }
2647}
2648
9a799d71
AK		 2649/**
2650 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2651 *
2652 **/
2653static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2654{
9a799d71
AK		 2655 struct ixgbe_hw *hw = &adapter->hw;
2656
021230d4 2657 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2658 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2659
e8e26350
PW		 2660 ixgbe_set_ivar(adapter, 0, 0, 0);
2661 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2662
2663 map_vector_to_rxq(adapter, 0, 0);
2664 map_vector_to_txq(adapter, 0, 0);
2665
396e799c 2666 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2667}
2668
43e69bf0
AD		 2669/**
2670 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2671 * @adapter: board private structure
2672 * @ring: structure containing ring specific data
2673 *
2674 * Configure the Tx descriptor ring after a reset.
2675 **/
84418e3b
AD		 2676void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2677 struct ixgbe_ring *ring)
43e69bf0
AD		 2678{
2679 struct ixgbe_hw *hw = &adapter->hw;
2680 u64 tdba = ring->dma;
2f1860b8
AD		 2681 int wait_loop = 10;
2682 u32 txdctl;
bf29ee6c 2683 u8 reg_idx = ring->reg_idx;
43e69bf0 2684
2f1860b8
AD		 2685 /* disable queue to avoid issues while updating state */
2686 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2687 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2688 txdctl & ~IXGBE_TXDCTL_ENABLE);
2689 IXGBE_WRITE_FLUSH(hw);
2690
43e69bf0 2691 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2692 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2693 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2694 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2695 ring->count * sizeof(union ixgbe_adv_tx_desc));
2696 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2697 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2698 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2699
2f1860b8
AD		 2700 /* configure fetching thresholds */
2701 if (adapter->rx_itr_setting == 0) {
2702 /* cannot set wthresh when itr==0 */
2703 txdctl &= ~0x007F0000;
2704 } else {
2705 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2706 txdctl |= (8 << 16);
2707 }
2708 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2709 /* PThresh workaround for Tx hang with DFP enabled. */
2710 txdctl |= 32;
2711 }
2712
2713 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2714 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2715 adapter->atr_sample_rate) {
2716 ring->atr_sample_rate = adapter->atr_sample_rate;
2717 ring->atr_count = 0;
2718 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2719 } else {
2720 ring->atr_sample_rate = 0;
2721 }
2f1860b8 2722
c84d324c
JF		 2723 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2724
2f1860b8
AD		 2725 /* enable queue */
2726 txdctl |= IXGBE_TXDCTL_ENABLE;
2727 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2728
2729 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2730 if (hw->mac.type == ixgbe_mac_82598EB &&
2731 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2732 return;
2733
2734 /* poll to verify queue is enabled */
2735 do {
032b4325 2736 usleep_range(1000, 2000);
2f1860b8
AD		 2737 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2738 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2739 if (!wait_loop)
2740 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2741}
2742
120ff942
AD		 2743static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2744{
2745 struct ixgbe_hw *hw = &adapter->hw;
2746 u32 rttdcs;
72a32f1f 2747 u32 reg;
8b1c0b24 2748 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2749
2750 if (hw->mac.type == ixgbe_mac_82598EB)
2751 return;
2752
2753 /* disable the arbiter while setting MTQC */
2754 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2755 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2756 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2757
2758 /* set transmit pool layout */
8b1c0b24 2759 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2760 case (IXGBE_FLAG_SRIOV_ENABLED):
2761 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2762 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2763 break;
8b1c0b24
JF		 2764 default:
2765 if (!tcs)
2766 reg = IXGBE_MTQC_64Q_1PB;
2767 else if (tcs <= 4)
2768 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2769 else
2770 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2771
8b1c0b24 2772 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2773
8b1c0b24
JF		 2774 /* Enable Security TX Buffer IFG for multiple pb */
2775 if (tcs) {
2776 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2777 reg |= IXGBE_SECTX_DCB;
2778 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2779 }
120ff942
AD		 2780 break;
2781 }
2782
2783 /* re-enable the arbiter */
2784 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2785 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2786}
2787
9a799d71 2788/**
3a581073 2789 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2790 * @adapter: board private structure
2791 *
2792 * Configure the Tx unit of the MAC after a reset.
2793 **/
2794static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2795{
2f1860b8
AD		 2796 struct ixgbe_hw *hw = &adapter->hw;
2797 u32 dmatxctl;
43e69bf0 2798 u32 i;
9a799d71 2799
2f1860b8
AD		 2800 ixgbe_setup_mtqc(adapter);
2801
2802 if (hw->mac.type != ixgbe_mac_82598EB) {
2803 /* DMATXCTL.EN must be before Tx queues are enabled */
2804 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2805 dmatxctl |= IXGBE_DMATXCTL_TE;
2806 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2807 }
2808
9a799d71 2809 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2810 for (i = 0; i < adapter->num_tx_queues; i++)
2811 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2812}
2813
e8e26350 2814#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2815
a6616b42 2816static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2817 struct ixgbe_ring *rx_ring)
cc41ac7c 2818{
cc41ac7c 2819 u32 srrctl;
bf29ee6c 2820 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2821
bd508178
AD		 2822 switch (adapter->hw.mac.type) {
2823 case ixgbe_mac_82598EB: {
2824 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2825 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2826 reg_idx = reg_idx & mask;
cc41ac7c 2827 }
bd508178
AD		 2828 break;
2829 case ixgbe_mac_82599EB:
b93a2226 2830 case ixgbe_mac_X540:
bd508178
AD		 2831 default:
2832 break;
2833 }
2834
bf29ee6c 2835 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2836
2837 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2838 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2839 if (adapter->num_vfs)
2840 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2841
afafd5b0
AD		 2842 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2843 IXGBE_SRRCTL_BSIZEHDR_MASK;
2844
7d637bcc 2845 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2846#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2847 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2848#else
2849 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2850#endif
cc41ac7c 2851 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2852 } else {
afafd5b0
AD		 2853 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2854 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2855 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2856 }
e8e26350 2857
bf29ee6c 2858 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2859}
9a799d71 2860
05abb126 2861static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2862{
05abb126
AD		 2863 struct ixgbe_hw *hw = &adapter->hw;
2864 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2865 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2866 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2867 u32 mrqc = 0, reta = 0;
2868 u32 rxcsum;
2869 int i, j;
8b1c0b24 2870 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2871 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2872
2873 if (tcs)
2874 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2875
05abb126
AD		 2876 /* Fill out hash function seeds */
2877 for (i = 0; i < 10; i++)
2878 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2879
2880 /* Fill out redirection table */
2881 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2882 if (j == maxq)
05abb126
AD		 2883 j = 0;
2884 /* reta = 4-byte sliding window of
2885 * 0x00..(indices-1)(indices-1)00..etc. */
2886 reta = (reta << 8) | (j * 0x11);
2887 if ((i & 3) == 3)
2888 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2889 }
0cefafad 2890
05abb126
AD		 2891 /* Disable indicating checksum in descriptor, enables RSS hash */
2892 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2893 rxcsum |= IXGBE_RXCSUM_PCSD;
2894 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2895
8b1c0b24
JF		 2896 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2897 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2898 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2899 } else {
2900 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2901 | IXGBE_FLAG_SRIOV_ENABLED);
2902
2903 switch (mask) {
2904 case (IXGBE_FLAG_RSS_ENABLED):
2905 if (!tcs)
2906 mrqc = IXGBE_MRQC_RSSEN;
2907 else if (tcs <= 4)
2908 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2909 else
2910 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2911 break;
2912 case (IXGBE_FLAG_SRIOV_ENABLED):
2913 mrqc = IXGBE_MRQC_VMDQEN;
2914 break;
2915 default:
2916 break;
2917 }
0cefafad
JB		 2918 }
2919
05abb126
AD		 2920 /* Perform hash on these packet types */
2921 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2922 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2923 | IXGBE_MRQC_RSS_FIELD_IPV6
2924 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2925
2926 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2927}
2928
b93a2226
DS		 2929/**
2930 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2931 * @adapter: address of board private structure
2932 * @ring: structure containing ring specific data
2933 **/
2934void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2935 struct ixgbe_ring *ring)
2936{
2937 struct ixgbe_hw *hw = &adapter->hw;
2938 u32 rscctrl;
2939 u8 reg_idx = ring->reg_idx;
2940
2941 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2942 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2943 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2944}
2945
bb5a9ad2
NS		 2946/**
2947 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2948 * @adapter: address of board private structure
2949 * @index: index of ring to set
bb5a9ad2 2950 **/
b93a2226 2951void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2952 struct ixgbe_ring *ring)
bb5a9ad2 2953{
bb5a9ad2 2954 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2955 u32 rscctrl;
edd2ea55 2956 int rx_buf_len;
bf29ee6c 2957 u8 reg_idx = ring->reg_idx;
7367096a 2958
7d637bcc 2959 if (!ring_is_rsc_enabled(ring))
7367096a 2960 return;
bb5a9ad2 2961
7367096a
AD		 2962 rx_buf_len = ring->rx_buf_len;
2963 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2964 rscctrl |= IXGBE_RSCCTL_RSCEN;
2965 /*
2966 * we must limit the number of descriptors so that the
2967 * total size of max desc * buf_len is not greater
2968 * than 65535
2969 */
7d637bcc 2970 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2971#if (MAX_SKB_FRAGS > 16)
2972 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2973#elif (MAX_SKB_FRAGS > 8)
2974 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2975#elif (MAX_SKB_FRAGS > 4)
2976 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2977#else
2978 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2979#endif
2980 } else {
2981 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2982 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2983 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2984 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2985 else
2986 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2987 }
7367096a 2988 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2989}
2990
9e10e045
AD		 2991/**
2992 * ixgbe_set_uta - Set unicast filter table address
2993 * @adapter: board private structure
2994 *
2995 * The unicast table address is a register array of 32-bit registers.
2996 * The table is meant to be used in a way similar to how the MTA is used
2997 * however due to certain limitations in the hardware it is necessary to
2998 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2999 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3000 **/
3001static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3002{
3003 struct ixgbe_hw *hw = &adapter->hw;
3004 int i;
3005
3006 /* The UTA table only exists on 82599 hardware and newer */
3007 if (hw->mac.type < ixgbe_mac_82599EB)
3008 return;
3009
3010 /* we only need to do this if VMDq is enabled */
3011 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3012 return;
3013
3014 for (i = 0; i < 128; i++)
3015 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3016}
3017
3018#define IXGBE_MAX_RX_DESC_POLL 10
3019static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3020 struct ixgbe_ring *ring)
3021{
3022 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3023 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3024 u32 rxdctl;
bf29ee6c 3025 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3026
3027 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3028 if (hw->mac.type == ixgbe_mac_82598EB &&
3029 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3030 return;
3031
3032 do {
032b4325 3033 usleep_range(1000, 2000);
9e10e045
AD		 3034 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3035 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3036
3037 if (!wait_loop) {
3038 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3039 "the polling period\n", reg_idx);
3040 }
3041}
3042
2d39d576
YZ		 3043void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3044 struct ixgbe_ring *ring)
3045{
3046 struct ixgbe_hw *hw = &adapter->hw;
3047 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3048 u32 rxdctl;
3049 u8 reg_idx = ring->reg_idx;
3050
3051 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3052 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3053
3054 /* write value back with RXDCTL.ENABLE bit cleared */
3055 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3056
3057 if (hw->mac.type == ixgbe_mac_82598EB &&
3058 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3059 return;
3060
3061 /* the hardware may take up to 100us to really disable the rx queue */
3062 do {
3063 udelay(10);
3064 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3065 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3066
3067 if (!wait_loop) {
3068 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3069 "the polling period\n", reg_idx);
3070 }
3071}
3072
84418e3b
AD		 3073void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3074 struct ixgbe_ring *ring)
acd37177
AD		 3075{
3076 struct ixgbe_hw *hw = &adapter->hw;
3077 u64 rdba = ring->dma;
9e10e045 3078 u32 rxdctl;
bf29ee6c 3079 u8 reg_idx = ring->reg_idx;
acd37177 3080
9e10e045
AD		 3081 /* disable queue to avoid issues while updating state */
3082 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3083 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3084
acd37177
AD		 3085 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3086 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3087 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3088 ring->count * sizeof(union ixgbe_adv_rx_desc));
3089 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3090 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3091 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3092
3093 ixgbe_configure_srrctl(adapter, ring);
3094 ixgbe_configure_rscctl(adapter, ring);
3095
e9f98072
GR		 3096 /* If operating in IOV mode set RLPML for X540 */
3097 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3098 hw->mac.type == ixgbe_mac_X540) {
3099 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3100 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3101 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3102 }
3103
9e10e045
AD		 3104 if (hw->mac.type == ixgbe_mac_82598EB) {
3105 /*
3106 * enable cache line friendly hardware writes:
3107 * PTHRESH=32 descriptors (half the internal cache),
3108 * this also removes ugly rx_no_buffer_count increment
3109 * HTHRESH=4 descriptors (to minimize latency on fetch)
3110 * WTHRESH=8 burst writeback up to two cache lines
3111 */
3112 rxdctl &= ~0x3FFFFF;
3113 rxdctl |= 0x080420;
3114 }
3115
3116 /* enable receive descriptor ring */
3117 rxdctl |= IXGBE_RXDCTL_ENABLE;
3118 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3119
3120 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3121 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3122}
3123
48654521
AD		 3124static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3125{
3126 struct ixgbe_hw *hw = &adapter->hw;
3127 int p;
3128
3129 /* PSRTYPE must be initialized in non 82598 adapters */
3130 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3131 IXGBE_PSRTYPE_UDPHDR |
3132 IXGBE_PSRTYPE_IPV4HDR |
48654521 3133 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3134 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3135
3136 if (hw->mac.type == ixgbe_mac_82598EB)
3137 return;
3138
3139 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3140 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3141
3142 for (p = 0; p < adapter->num_rx_pools; p++)
3143 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3144 psrtype);
3145}
3146
f5b4a52e
AD		 3147static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3148{
3149 struct ixgbe_hw *hw = &adapter->hw;
3150 u32 gcr_ext;
3151 u32 vt_reg_bits;
3152 u32 reg_offset, vf_shift;
3153 u32 vmdctl;
3154
3155 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3156 return;
3157
3158 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3159 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3160 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3161 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3162
3163 vf_shift = adapter->num_vfs % 32;
3164 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3165
3166 /* Enable only the PF's pool for Tx/Rx */
3167 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3168 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3169 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3170 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3171 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3172
3173 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3174 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3175
3176 /*
3177 * Set up VF register offsets for selected VT Mode,
3178 * i.e. 32 or 64 VFs for SR-IOV
3179 */
3180 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3181 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3182 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3183 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3184
3185 /* enable Tx loopback for VF/PF communication */
3186 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3187 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 3188 hw->mac.ops.set_mac_anti_spoofing(hw,
3189 (adapter->antispoofing_enabled =
3190 (adapter->num_vfs != 0)),
a985b6c3 3191 adapter->num_vfs);
f5b4a52e
AD		 3192}
3193
477de6ed 3194static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3195{
9a799d71
AK		 3196 struct ixgbe_hw *hw = &adapter->hw;
3197 struct net_device *netdev = adapter->netdev;
3198 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3199 int rx_buf_len;
477de6ed
AD		 3200 struct ixgbe_ring *rx_ring;
3201 int i;
3202 u32 mhadd, hlreg0;
48654521 3203
9a799d71 3204 /* Decide whether to use packet split mode or not */
a124339a
DS		 3205 /* On by default */
3206 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3207
1cdd1ec8 3208 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3209 if (adapter->num_vfs)
3210 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3211
3212 /* Disable packet split due to 82599 erratum #45 */
3213 if (hw->mac.type == ixgbe_mac_82599EB)
3214 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3215
3216 /* Set the RX buffer length according to the mode */
3217 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3218 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3219 } else {
0c19d6af 3220 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3221 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3222 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3223 else
477de6ed 3224 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3225 }
3226
63f39bd1 3227#ifdef IXGBE_FCOE
477de6ed
AD		 3228 /* adjust max frame to be able to do baby jumbo for FCoE */
3229 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3230 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3231 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3232
477de6ed
AD		 3233#endif /* IXGBE_FCOE */
3234 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3235 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3236 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3237 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3238
3239 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3240 }
3241
3242 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3243 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3244 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3245 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3246
0cefafad
JB		 3247 /*
3248 * Setup the HW Rx Head and Tail Descriptor Pointers and
3249 * the Base and Length of the Rx Descriptor Ring
3250 */
9a799d71 3251 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3252 rx_ring = adapter->rx_ring[i];
a6616b42 3253 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3254
6e455b89 3255 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3256 set_ring_ps_enabled(rx_ring);
3257 else
3258 clear_ring_ps_enabled(rx_ring);
3259
3260 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3261 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3262 else
7d637bcc 3263 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3264
63f39bd1 3265#ifdef IXGBE_FCOE
e8e9f696 3266 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3267 struct ixgbe_ring_feature *f;
3268 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3269 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3270 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3271 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3272 rx_ring->rx_buf_len =
e8e9f696 3273 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3274 } else if (!ring_is_rsc_enabled(rx_ring) &&
3275 !ring_is_ps_enabled(rx_ring)) {
3276 rx_ring->rx_buf_len =
3277 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3278 }
63f39bd1 3279 }
63f39bd1 3280#endif /* IXGBE_FCOE */
477de6ed 3281 }
477de6ed
AD		 3282}
3283
7367096a
AD		 3284static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3285{
3286 struct ixgbe_hw *hw = &adapter->hw;
3287 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3288
3289 switch (hw->mac.type) {
3290 case ixgbe_mac_82598EB:
3291 /*
3292 * For VMDq support of different descriptor types or
3293 * buffer sizes through the use of multiple SRRCTL
3294 * registers, RDRXCTL.MVMEN must be set to 1
3295 *
3296 * also, the manual doesn't mention it clearly but DCA hints
3297 * will only use queue 0's tags unless this bit is set. Side
3298 * effects of setting this bit are only that SRRCTL must be
3299 * fully programmed [0..15]
3300 */
3301 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3302 break;
3303 case ixgbe_mac_82599EB:
b93a2226 3304 case ixgbe_mac_X540:
7367096a
AD		 3305 /* Disable RSC for ACK packets */
3306 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3307 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3308 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3309 /* hardware requires some bits to be set by default */
3310 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3311 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3312 break;
3313 default:
3314 /* We should do nothing since we don't know this hardware */
3315 return;
3316 }
3317
3318 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3319}
3320
477de6ed
AD		 3321/**
3322 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3323 * @adapter: board private structure
3324 *
3325 * Configure the Rx unit of the MAC after a reset.
3326 **/
3327static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3328{
3329 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3330 int i;
3331 u32 rxctrl;
477de6ed
AD		 3332
3333 /* disable receives while setting up the descriptors */
3334 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3335 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3336
3337 ixgbe_setup_psrtype(adapter);
7367096a 3338 ixgbe_setup_rdrxctl(adapter);
477de6ed 3339
9e10e045 3340 /* Program registers for the distribution of queues */
f5b4a52e 3341 ixgbe_setup_mrqc(adapter);
f5b4a52e 3342
9e10e045
AD		 3343 ixgbe_set_uta(adapter);
3344
477de6ed
AD		 3345 /* set_rx_buffer_len must be called before ring initialization */
3346 ixgbe_set_rx_buffer_len(adapter);
3347
3348 /*
3349 * Setup the HW Rx Head and Tail Descriptor Pointers and
3350 * the Base and Length of the Rx Descriptor Ring
3351 */
9e10e045
AD		 3352 for (i = 0; i < adapter->num_rx_queues; i++)
3353 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3354
9e10e045
AD		 3355 /* disable drop enable for 82598 parts */
3356 if (hw->mac.type == ixgbe_mac_82598EB)
3357 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3358
3359 /* enable all receives */
3360 rxctrl |= IXGBE_RXCTRL_RXEN;
3361 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3362}
3363
068c89b0
DS		 3364static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3365{
3366 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3367 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3368 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3369
3370 /* add VID to filter table */
1ada1b1b 3371 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3372 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3373}
3374
3375static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3376{
3377 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3378 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3379 int pool_ndx = adapter->num_vfs;
068c89b0 3380
068c89b0 3381 /* remove VID from filter table */
1ada1b1b 3382 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3383 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3384}
3385
5f6c0181
JB		 3386/**
3387 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3388 * @adapter: driver data
3389 */
3390static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3391{
3392 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3393 u32 vlnctrl;
3394
3395 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3396 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3397 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3398}
3399
3400/**
3401 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3402 * @adapter: driver data
3403 */
3404static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3405{
3406 struct ixgbe_hw *hw = &adapter->hw;
3407 u32 vlnctrl;
3408
3409 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3410 vlnctrl |= IXGBE_VLNCTRL_VFE;
3411 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3412 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3413}
3414
3415/**
3416 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3417 * @adapter: driver data
3418 */
3419static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3420{
3421 struct ixgbe_hw *hw = &adapter->hw;
3422 u32 vlnctrl;
5f6c0181
JB		 3423 int i, j;
3424
3425 switch (hw->mac.type) {
3426 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3427 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3428 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3429 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3430 break;
3431 case ixgbe_mac_82599EB:
b93a2226 3432 case ixgbe_mac_X540:
5f6c0181
JB		 3433 for (i = 0; i < adapter->num_rx_queues; i++) {
3434 j = adapter->rx_ring[i]->reg_idx;
3435 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3436 vlnctrl &= ~IXGBE_RXDCTL_VME;
3437 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3438 }
3439 break;
3440 default:
3441 break;
3442 }
3443}
3444
3445/**
f62bbb5e 3446 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3447 * @adapter: driver data
3448 */
f62bbb5e 3449static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3450{
3451 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3452 u32 vlnctrl;
5f6c0181
JB		 3453 int i, j;
3454
3455 switch (hw->mac.type) {
3456 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3457 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3458 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3459 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3460 break;
3461 case ixgbe_mac_82599EB:
b93a2226 3462 case ixgbe_mac_X540:
5f6c0181
JB		 3463 for (i = 0; i < adapter->num_rx_queues; i++) {
3464 j = adapter->rx_ring[i]->reg_idx;
3465 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3466 vlnctrl |= IXGBE_RXDCTL_VME;
3467 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3468 }
3469 break;
3470 default:
3471 break;
3472 }
3473}
3474
9a799d71
AK		 3475static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3476{
f62bbb5e 3477 u16 vid;
9a799d71 3478
f62bbb5e
JG		 3479 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3480
3481 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3482 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3483}
3484
2850062a
AD		 3485/**
3486 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3487 * @netdev: network interface device structure
3488 *
3489 * Writes unicast address list to the RAR table.
3490 * Returns: -ENOMEM on failure/insufficient address space
3491 * 0 on no addresses written
3492 * X on writing X addresses to the RAR table
3493 **/
3494static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3495{
3496 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3497 struct ixgbe_hw *hw = &adapter->hw;
3498 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3499 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3500 int count = 0;
3501
3502 /* return ENOMEM indicating insufficient memory for addresses */
3503 if (netdev_uc_count(netdev) > rar_entries)
3504 return -ENOMEM;
3505
3506 if (!netdev_uc_empty(netdev) && rar_entries) {
3507 struct netdev_hw_addr *ha;
3508 /* return error if we do not support writing to RAR table */
3509 if (!hw->mac.ops.set_rar)
3510 return -ENOMEM;
3511
3512 netdev_for_each_uc_addr(ha, netdev) {
3513 if (!rar_entries)
3514 break;
3515 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3516 vfn, IXGBE_RAH_AV);
3517 count++;
3518 }
3519 }
3520 /* write the addresses in reverse order to avoid write combining */
3521 for (; rar_entries > 0 ; rar_entries--)
3522 hw->mac.ops.clear_rar(hw, rar_entries);
3523
3524 return count;
3525}
3526
9a799d71 3527/**
2c5645cf 3528 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3529 * @netdev: network interface device structure
3530 *
2c5645cf
CL		 3531 * The set_rx_method entry point is called whenever the unicast/multicast
3532 * address list or the network interface flags are updated. This routine is
3533 * responsible for configuring the hardware for proper unicast, multicast and
3534 * promiscuous mode.
9a799d71 3535 **/
7f870475 3536void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3537{
3538 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3539 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3540 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3541 int count;
9a799d71
AK		 3542
3543 /* Check for Promiscuous and All Multicast modes */
3544
3545 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3546
f5dc442b
AD		 3547 /* set all bits that we expect to always be set */
3548 fctrl |= IXGBE_FCTRL_BAM;
3549 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3550 fctrl |= IXGBE_FCTRL_PMCF;
3551
2850062a
AD		 3552 /* clear the bits we are changing the status of */
3553 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3554
9a799d71 3555 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3556 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3557 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3558 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3559 /* don't hardware filter vlans in promisc mode */
3560 ixgbe_vlan_filter_disable(adapter);
9a799d71 3561 } else {
746b9f02
PM		 3562 if (netdev->flags & IFF_ALLMULTI) {
3563 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3564 vmolr |= IXGBE_VMOLR_MPE;
3565 } else {
3566 /*
3567 * Write addresses to the MTA, if the attempt fails
25985edc 3568 * then we should just turn on promiscuous mode so
2850062a
AD		 3569 * that we can at least receive multicast traffic
3570 */
3571 hw->mac.ops.update_mc_addr_list(hw, netdev);
3572 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3573 }
5f6c0181 3574 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3575 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3576 /*
3577 * Write addresses to available RAR registers, if there is not
3578 * sufficient space to store all the addresses then enable
25985edc 3579 * unicast promiscuous mode
2850062a
AD		 3580 */
3581 count = ixgbe_write_uc_addr_list(netdev);
3582 if (count < 0) {
3583 fctrl |= IXGBE_FCTRL_UPE;
3584 vmolr |= IXGBE_VMOLR_ROPE;
3585 }
9a799d71
AK		 3586 }
3587
2850062a 3588 if (adapter->num_vfs) {
1cdd1ec8 3589 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3590 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3591 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3592 IXGBE_VMOLR_ROPE);
3593 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3594 }
3595
3596 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3597
3598 if (netdev->features & NETIF_F_HW_VLAN_RX)
3599 ixgbe_vlan_strip_enable(adapter);
3600 else
3601 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3602}
3603
021230d4
AV		 3604static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3605{
3606 int q_idx;
3607 struct ixgbe_q_vector *q_vector;
3608 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3609
3610 /* legacy and MSI only use one vector */
3611 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3612 q_vectors = 1;
3613
3614 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3615 struct napi_struct *napi;
7a921c93 3616 q_vector = adapter->q_vector[q_idx];
f0848276 3617 napi = &q_vector->napi;
91281fd3
AD		 3618 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3619 if (!q_vector->rxr_count || !q_vector->txr_count) {
3620 if (q_vector->txr_count == 1)
3621 napi->poll = &ixgbe_clean_txonly;
3622 else if (q_vector->rxr_count == 1)
3623 napi->poll = &ixgbe_clean_rxonly;
3624 }
3625 }
f0848276
JB		 3626
3627 napi_enable(napi);
021230d4
AV		 3628 }
3629}
3630
3631static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3632{
3633 int q_idx;
3634 struct ixgbe_q_vector *q_vector;
3635 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3636
3637 /* legacy and MSI only use one vector */
3638 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3639 q_vectors = 1;
3640
3641 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3642 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3643 napi_disable(&q_vector->napi);
3644 }
3645}
3646
7a6b6f51 3647#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3648/*
3649 * ixgbe_configure_dcb - Configure DCB hardware
3650 * @adapter: ixgbe adapter struct
3651 *
3652 * This is called by the driver on open to configure the DCB hardware.
3653 * This is also called by the gennetlink interface when reconfiguring
3654 * the DCB state.
3655 */
3656static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3657{
3658 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3659 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3660
67ebd791
AD		 3661 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3662 if (hw->mac.type == ixgbe_mac_82598EB)
3663 netif_set_gso_max_size(adapter->netdev, 65536);
3664 return;
3665 }
3666
3667 if (hw->mac.type == ixgbe_mac_82598EB)
3668 netif_set_gso_max_size(adapter->netdev, 32768);
3669
2f90b865 3670
2f90b865 3671 /* Enable VLAN tag insert/strip */
f62bbb5e 3672 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3673
2f90b865 3674 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3675
3676 /* reconfigure the hardware */
6f70f6ac 3677 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3678#ifdef CONFIG_FCOE
3679 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3680 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3681#endif
3682 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3683 DCB_TX_CONFIG);
3684 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3685 DCB_RX_CONFIG);
3686 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3687 } else {
3688 struct net_device *dev = adapter->netdev;
3689
3690 if (adapter->ixgbe_ieee_ets)
3691 dev->dcbnl_ops->ieee_setets(dev,
3692 adapter->ixgbe_ieee_ets);
3693 if (adapter->ixgbe_ieee_pfc)
3694 dev->dcbnl_ops->ieee_setpfc(dev,
3695 adapter->ixgbe_ieee_pfc);
3696 }
8187cd48
JF		 3697
3698 /* Enable RSS Hash per TC */
3699 if (hw->mac.type != ixgbe_mac_82598EB) {
3700 int i;
3701 u32 reg = 0;
3702
3703 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3704 u8 msb = 0;
3705 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3706
3707 while (cnt >>= 1)
3708 msb++;
3709
3710 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3711 }
3712 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3713 }
2f90b865
AD		 3714}
3715
3716#endif
80605c65
JF		 3717
3718static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3719{
3720 int hdrm = 0;
3721 int num_tc = netdev_get_num_tc(adapter->netdev);
3722 struct ixgbe_hw *hw = &adapter->hw;
3723
3724 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3725 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3726 hdrm = 64 << adapter->fdir_pballoc;
3727
3728 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3729}
3730
e4911d57
AD		 3731static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3732{
3733 struct ixgbe_hw *hw = &adapter->hw;
3734 struct hlist_node *node, *node2;
3735 struct ixgbe_fdir_filter *filter;
3736
3737 spin_lock(&adapter->fdir_perfect_lock);
3738
3739 if (!hlist_empty(&adapter->fdir_filter_list))
3740 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3741
3742 hlist_for_each_entry_safe(filter, node, node2,
3743 &adapter->fdir_filter_list, fdir_node) {
3744 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3745 &filter->filter,
3746 filter->sw_idx,
3747 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3748 IXGBE_FDIR_DROP_QUEUE :
3749 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3750 }
3751
3752 spin_unlock(&adapter->fdir_perfect_lock);
3753}
3754
9a799d71
AK		 3755static void ixgbe_configure(struct ixgbe_adapter *adapter)
3756{
3757 struct net_device *netdev = adapter->netdev;
c4cf55e5 3758 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3759 int i;
3760
80605c65 3761 ixgbe_configure_pb(adapter);
7a6b6f51 3762#ifdef CONFIG_IXGBE_DCB
67ebd791 3763 ixgbe_configure_dcb(adapter);
2f90b865 3764#endif
9a799d71 3765
f62bbb5e
JG		 3766 ixgbe_set_rx_mode(netdev);
3767 ixgbe_restore_vlan(adapter);
3768
eacd73f7
YZ		 3769#ifdef IXGBE_FCOE
3770 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3771 ixgbe_configure_fcoe(adapter);
3772
3773#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3774 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3775 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3776 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3777 adapter->atr_sample_rate;
c4cf55e5 3778 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
e4911d57
AD		 3779 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3780 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3781 adapter->fdir_pballoc);
3782 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3783 }
933d41f1 3784 ixgbe_configure_virtualization(adapter);
c4cf55e5 3785
9a799d71
AK		 3786 ixgbe_configure_tx(adapter);
3787 ixgbe_configure_rx(adapter);
9a799d71
AK		 3788}
3789
e8e26350
PW		 3790static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3791{
3792 switch (hw->phy.type) {
3793 case ixgbe_phy_sfp_avago:
3794 case ixgbe_phy_sfp_ftl:
3795 case ixgbe_phy_sfp_intel:
3796 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3797 case ixgbe_phy_sfp_passive_tyco:
3798 case ixgbe_phy_sfp_passive_unknown:
3799 case ixgbe_phy_sfp_active_unknown:
3800 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3801 return true;
3802 default:
3803 return false;
3804 }
3805}
3806
0ecc061d 3807/**
e8e26350
PW		 3808 * ixgbe_sfp_link_config - set up SFP+ link
3809 * @adapter: pointer to private adapter struct
3810 **/
3811static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3812{
7086400d
AD		 3813 /*
3814 * We are assuming the worst case scenerio here, and that
3815 * is that an SFP was inserted/removed after the reset
3816 * but before SFP detection was enabled. As such the best
3817 * solution is to just start searching as soon as we start
3818 */
3819 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3820 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3821
7086400d 3822 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3823}
3824
3825/**
3826 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3827 * @hw: pointer to private hardware struct
3828 *
3829 * Returns 0 on success, negative on failure
3830 **/
e8e26350 3831static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3832{
3833 u32 autoneg;
8620a103 3834 bool negotiation, link_up = false;
0ecc061d
PWJ		 3835 u32 ret = IXGBE_ERR_LINK_SETUP;
3836
3837 if (hw->mac.ops.check_link)
3838 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3839
3840 if (ret)
3841 goto link_cfg_out;
3842
0b0c2b31
ET		 3843 autoneg = hw->phy.autoneg_advertised;
3844 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3845 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3846 &negotiation);
0ecc061d
PWJ		 3847 if (ret)
3848 goto link_cfg_out;
3849
8620a103
MC		 3850 if (hw->mac.ops.setup_link)
3851 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3852link_cfg_out:
3853 return ret;
3854}
3855
a34bcfff 3856static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3857{
9a799d71 3858 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3859 u32 gpie = 0;
9a799d71 3860
9b471446 3861 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3862 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3863 IXGBE_GPIE_OCD;
3864 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3865 /*
3866 * use EIAM to auto-mask when MSI-X interrupt is asserted
3867 * this saves a register write for every interrupt
3868 */
3869 switch (hw->mac.type) {
3870 case ixgbe_mac_82598EB:
3871 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3872 break;
9b471446 3873 case ixgbe_mac_82599EB:
b93a2226
DS		 3874 case ixgbe_mac_X540:
3875 default:
9b471446
JB		 3876 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3877 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3878 break;
3879 }
3880 } else {
021230d4
AV		 3881 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3882 * specifically only auto mask tx and rx interrupts */
3883 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3884 }
9a799d71 3885
a34bcfff
AD		 3886 /* XXX: to interrupt immediately for EICS writes, enable this */
3887 /* gpie |= IXGBE_GPIE_EIMEN; */
3888
3889 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3890 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3891 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3892 }
3893
a34bcfff
AD		 3894 /* Enable fan failure interrupt */
3895 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3896 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3897
2698b208 3898 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3899 gpie |= IXGBE_SDP1_GPIEN;
3900 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3901 }
a34bcfff
AD		 3902
3903 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3904}
3905
3906static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3907{
3908 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3909 int err;
a34bcfff
AD		 3910 u32 ctrl_ext;
3911
3912 ixgbe_get_hw_control(adapter);
3913 ixgbe_setup_gpie(adapter);
e8e26350 3914
9a799d71
AK		 3915 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3916 ixgbe_configure_msix(adapter);
3917 else
3918 ixgbe_configure_msi_and_legacy(adapter);
3919
c6ecf39a
DS		 3920 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3921 if (hw->mac.ops.enable_tx_laser &&
3922 ((hw->phy.multispeed_fiber) ||
9f911707 3923 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3924 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3925 hw->mac.ops.enable_tx_laser(hw);
3926
9a799d71 3927 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3928 ixgbe_napi_enable_all(adapter);
3929
73c4b7cd
AD		 3930 if (ixgbe_is_sfp(hw)) {
3931 ixgbe_sfp_link_config(adapter);
3932 } else {
3933 err = ixgbe_non_sfp_link_config(hw);
3934 if (err)
3935 e_err(probe, "link_config FAILED %d\n", err);
3936 }
3937
021230d4
AV		 3938 /* clear any pending interrupts, may auto mask */
3939 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3940 ixgbe_irq_enable(adapter, true, true);
9a799d71 3941
bf069c97
DS		 3942 /*
3943 * If this adapter has a fan, check to see if we had a failure
3944 * before we enabled the interrupt.
3945 */
3946 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3947 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3948 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3949 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3950 }
3951
1da100bb 3952 /* enable transmits */
477de6ed 3953 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3954
9a799d71
AK		 3955 /* bring the link up in the watchdog, this could race with our first
3956 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3957 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3958 adapter->link_check_timeout = jiffies;
7086400d 3959 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3960
3961 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3962 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3963 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3964 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3965
9a799d71
AK		 3966 return 0;
3967}
3968
d4f80882
AV		 3969void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3970{
3971 WARN_ON(in_interrupt());
7086400d
AD		 3972 /* put off any impending NetWatchDogTimeout */
3973 adapter->netdev->trans_start = jiffies;
3974
d4f80882 3975 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3976 usleep_range(1000, 2000);
d4f80882 3977 ixgbe_down(adapter);
5809a1ae
GR		 3978 /*
3979 * If SR-IOV enabled then wait a bit before bringing the adapter
3980 * back up to give the VFs time to respond to the reset. The
3981 * two second wait is based upon the watchdog timer cycle in
3982 * the VF driver.
3983 */
3984 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3985 msleep(2000);
d4f80882
AV		 3986 ixgbe_up(adapter);
3987 clear_bit(__IXGBE_RESETTING, &adapter->state);
3988}
3989
9a799d71
AK		 3990int ixgbe_up(struct ixgbe_adapter *adapter)
3991{
3992 /* hardware has been reset, we need to reload some things */
3993 ixgbe_configure(adapter);
3994
3995 return ixgbe_up_complete(adapter);
3996}
3997
3998void ixgbe_reset(struct ixgbe_adapter *adapter)
3999{
c44ade9e 4000 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4001 int err;
4002
7086400d
AD		 4003 /* lock SFP init bit to prevent race conditions with the watchdog */
4004 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4005 usleep_range(1000, 2000);
4006
4007 /* clear all SFP and link config related flags while holding SFP_INIT */
4008 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4009 IXGBE_FLAG2_SFP_NEEDS_RESET);
4010 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4011
8ca783ab 4012 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4013 switch (err) {
4014 case 0:
4015 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4016 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4017 break;
4018 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4019 e_dev_err("master disable timed out\n");
da4dd0f7 4020 break;
794caeb2
PWJ		 4021 case IXGBE_ERR_EEPROM_VERSION:
4022 /* We are running on a pre-production device, log a warning */
849c4542
ET		 4023 e_dev_warn("This device is a pre-production adapter/LOM. "
4024 "Please be aware there may be issuesassociated with "
4025 "your hardware. If you are experiencing problems "
4026 "please contact your Intel or hardware "
4027 "representative who provided you with this "
4028 "hardware.\n");
794caeb2 4029 break;
da4dd0f7 4030 default:
849c4542 4031 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4032 }
9a799d71 4033
7086400d
AD		 4034 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4035
9a799d71 4036 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4037 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4038 IXGBE_RAH_AV);
9a799d71
AK		 4039}
4040
9a799d71
AK		 4041/**
4042 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4043 * @rx_ring: ring to free buffers from
4044 **/
b6ec895e 4045static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4046{
b6ec895e 4047 struct device *dev = rx_ring->dev;
9a799d71 4048 unsigned long size;
b6ec895e 4049 u16 i;
9a799d71 4050
84418e3b
AD		 4051 /* ring already cleared, nothing to do */
4052 if (!rx_ring->rx_buffer_info)
4053 return;
9a799d71 4054
84418e3b 4055 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4056 for (i = 0; i < rx_ring->count; i++) {
4057 struct ixgbe_rx_buffer *rx_buffer_info;
4058
4059 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4060 if (rx_buffer_info->dma) {
b6ec895e 4061 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4062 rx_ring->rx_buf_len,
1b507730 4063 DMA_FROM_DEVICE);
9a799d71
AK		 4064 rx_buffer_info->dma = 0;
4065 }
4066 if (rx_buffer_info->skb) {
f8212f97 4067 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4068 rx_buffer_info->skb = NULL;
f8212f97
AD		 4069 do {
4070 struct sk_buff *this = skb;
e8171aaa 4071 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 4072 dma_unmap_single(dev,
1b507730 4073 IXGBE_RSC_CB(this)->dma,
e8e9f696 4074 rx_ring->rx_buf_len,
1b507730 4075 DMA_FROM_DEVICE);
fd3686a8 4076 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 4077 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 4078 }
f8212f97
AD		 4079 skb = skb->prev;
4080 dev_kfree_skb(this);
4081 } while (skb);
9a799d71
AK		 4082 }
4083 if (!rx_buffer_info->page)
4084 continue;
4f57ca6e 4085 if (rx_buffer_info->page_dma) {
b6ec895e 4086 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4087 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4088 rx_buffer_info->page_dma = 0;
4089 }
9a799d71
AK		 4090 put_page(rx_buffer_info->page);
4091 rx_buffer_info->page = NULL;
762f4c57 4092 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4093 }
4094
4095 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4096 memset(rx_ring->rx_buffer_info, 0, size);
4097
4098 /* Zero out the descriptor ring */
4099 memset(rx_ring->desc, 0, rx_ring->size);
4100
4101 rx_ring->next_to_clean = 0;
4102 rx_ring->next_to_use = 0;
9a799d71
AK		 4103}
4104
4105/**
4106 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4107 * @tx_ring: ring to be cleaned
4108 **/
b6ec895e 4109static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4110{
4111 struct ixgbe_tx_buffer *tx_buffer_info;
4112 unsigned long size;
b6ec895e 4113 u16 i;
9a799d71 4114
84418e3b
AD		 4115 /* ring already cleared, nothing to do */
4116 if (!tx_ring->tx_buffer_info)
4117 return;
9a799d71 4118
84418e3b 4119 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4120 for (i = 0; i < tx_ring->count; i++) {
4121 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4122 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4123 }
4124
4125 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4126 memset(tx_ring->tx_buffer_info, 0, size);
4127
4128 /* Zero out the descriptor ring */
4129 memset(tx_ring->desc, 0, tx_ring->size);
4130
4131 tx_ring->next_to_use = 0;
4132 tx_ring->next_to_clean = 0;
9a799d71
AK		 4133}
4134
4135/**
021230d4 4136 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4137 * @adapter: board private structure
4138 **/
021230d4 4139static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4140{
4141 int i;
4142
021230d4 4143 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4144 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4145}
4146
4147/**
021230d4 4148 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4149 * @adapter: board private structure
4150 **/
021230d4 4151static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4152{
4153 int i;
4154
021230d4 4155 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4156 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4157}
4158
e4911d57
AD		 4159static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4160{
4161 struct hlist_node *node, *node2;
4162 struct ixgbe_fdir_filter *filter;
4163
4164 spin_lock(&adapter->fdir_perfect_lock);
4165
4166 hlist_for_each_entry_safe(filter, node, node2,
4167 &adapter->fdir_filter_list, fdir_node) {
4168 hlist_del(&filter->fdir_node);
4169 kfree(filter);
4170 }
4171 adapter->fdir_filter_count = 0;
4172
4173 spin_unlock(&adapter->fdir_perfect_lock);
4174}
4175
9a799d71
AK		 4176void ixgbe_down(struct ixgbe_adapter *adapter)
4177{
4178 struct net_device *netdev = adapter->netdev;
7f821875 4179 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4180 u32 rxctrl;
bf29ee6c 4181 int i;
b25ebfd2 4182 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4183
4184 /* signal that we are down to the interrupt handler */
4185 set_bit(__IXGBE_DOWN, &adapter->state);
4186
4187 /* disable receives */
7f821875
JB		 4188 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4189 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4190
2d39d576
YZ		 4191 /* disable all enabled rx queues */
4192 for (i = 0; i < adapter->num_rx_queues; i++)
4193 /* this call also flushes the previous write */
4194 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4195
032b4325 4196 usleep_range(10000, 20000);
9a799d71 4197
7f821875
JB		 4198 netif_tx_stop_all_queues(netdev);
4199
7086400d 4200 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4201 netif_carrier_off(netdev);
4202 netif_tx_disable(netdev);
4203
4204 ixgbe_irq_disable(adapter);
4205
4206 ixgbe_napi_disable_all(adapter);
4207
d034acf1
AD		 4208 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4209 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4210 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4211
4212 del_timer_sync(&adapter->service_timer);
4213
34cecbbf
AD		 4214 /* disable receive for all VFs and wait one second */
4215 if (adapter->num_vfs) {
4216 /* ping all the active vfs to let them know we are going down */
4217 ixgbe_ping_all_vfs(adapter);
4218
4219 /* Disable all VFTE/VFRE TX/RX */
4220 ixgbe_disable_tx_rx(adapter);
4221
4222 /* Mark all the VFs as inactive */
4223 for (i = 0 ; i < adapter->num_vfs; i++)
4224 adapter->vfinfo[i].clear_to_send = 0;
4225 }
4226
b25ebfd2
PW		 4227 /* Cleanup the affinity_hint CPU mask memory and callback */
4228 for (i = 0; i < num_q_vectors; i++) {
4229 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4230 /* clear the affinity_mask in the IRQ descriptor */
4231 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4232 /* release the CPU mask memory */
4233 free_cpumask_var(q_vector->affinity_mask);
4234 }
4235
7f821875
JB		 4236 /* disable transmits in the hardware now that interrupts are off */
4237 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4238 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4239 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4240 }
34cecbbf
AD		 4241
4242 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4243 switch (hw->mac.type) {
4244 case ixgbe_mac_82599EB:
b93a2226 4245 case ixgbe_mac_X540:
88512539 4246 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4247 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4248 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4249 break;
4250 default:
4251 break;
4252 }
7f821875 4253
6f4a0e45
PL		 4254 if (!pci_channel_offline(adapter->pdev))
4255 ixgbe_reset(adapter);
c6ecf39a
DS		 4256
4257 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4258 if (hw->mac.ops.disable_tx_laser &&
4259 ((hw->phy.multispeed_fiber) ||
9f911707 4260 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4261 (hw->mac.type == ixgbe_mac_82599EB))))
4262 hw->mac.ops.disable_tx_laser(hw);
4263
9a799d71
AK		 4264 ixgbe_clean_all_tx_rings(adapter);
4265 ixgbe_clean_all_rx_rings(adapter);
4266
5dd2d332 4267#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4268 /* since we reset the hardware DCA settings were cleared */
e35ec126 4269 ixgbe_setup_dca(adapter);
96b0e0f6 4270#endif
9a799d71
AK		 4271}
4272
9a799d71 4273/**
021230d4
AV		 4274 * ixgbe_poll - NAPI Rx polling callback
4275 * @napi: structure for representing this polling device
4276 * @budget: how many packets driver is allowed to clean
4277 *
4278 * This function is used for legacy and MSI, NAPI mode
9a799d71 4279 **/
021230d4 4280static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4281{
9a1a69ad 4282 struct ixgbe_q_vector *q_vector =
e8e9f696 4283 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4284 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4285 int tx_clean_complete, work_done = 0;
9a799d71 4286
5dd2d332 4287#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4288 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4289 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4290#endif
4291
4a0b9ca0
PW		 4292 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4293 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4294
9a1a69ad 4295 if (!tx_clean_complete)
d2c7ddd6
DM		 4296 work_done = budget;
4297
53e52c72
DM		 4298 /* If budget not fully consumed, exit the polling mode */
4299 if (work_done < budget) {
288379f0 4300 napi_complete(napi);
f7554a2b 4301 if (adapter->rx_itr_setting & 1)
f494e8fa 4302 ixgbe_set_itr(adapter);
d4f80882 4303 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4304 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4305 }
9a799d71
AK		 4306 return work_done;
4307}
4308
4309/**
4310 * ixgbe_tx_timeout - Respond to a Tx Hang
4311 * @netdev: network interface device structure
4312 **/
4313static void ixgbe_tx_timeout(struct net_device *netdev)
4314{
4315 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4316
4317 /* Do the reset outside of interrupt context */
c83c6cbd 4318 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4319}
4320
4df10466
JB		 4321/**
4322 * ixgbe_set_rss_queues: Allocate queues for RSS
4323 * @adapter: board private structure to initialize
4324 *
4325 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4326 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4327 *
4328 **/
bc97114d
PWJ		 4329static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4330{
4331 bool ret = false;
0cefafad 4332 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4333
4334 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4335 f->mask = 0xF;
4336 adapter->num_rx_queues = f->indices;
4337 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4338 ret = true;
4339 } else {
bc97114d 4340 ret = false;
b9804972
JB		 4341 }
4342
bc97114d
PWJ		 4343 return ret;
4344}
4345
c4cf55e5
PWJ		 4346/**
4347 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4348 * @adapter: board private structure to initialize
4349 *
4350 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4351 * to the original CPU that initiated the Tx session. This runs in addition
4352 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4353 * Rx load across CPUs using RSS.
4354 *
4355 **/
e8e9f696 4356static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4357{
4358 bool ret = false;
4359 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4360
4361 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4362 f_fdir->mask = 0;
4363
4364 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4365 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4366 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4367 adapter->num_tx_queues = f_fdir->indices;
4368 adapter->num_rx_queues = f_fdir->indices;
4369 ret = true;
4370 } else {
4371 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4372 }
4373 return ret;
4374}
4375
0331a832
YZ		 4376#ifdef IXGBE_FCOE
4377/**
4378 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4379 * @adapter: board private structure to initialize
4380 *
4381 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4382 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4383 * rx queues out of the max number of rx queues, instead, it is used as the
4384 * index of the first rx queue used by FCoE.
4385 *
4386 **/
4387static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4388{
0331a832
YZ		 4389 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4390
e5b64635
JF		 4391 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4392 return false;
4393
e901acd6 4394 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4395
e901acd6
JF		 4396 adapter->num_rx_queues = 1;
4397 adapter->num_tx_queues = 1;
e5b64635 4398
e901acd6
JF		 4399 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4400 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4401 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4402 ixgbe_set_fdir_queues(adapter);
4403 else
4404 ixgbe_set_rss_queues(adapter);
e5b64635 4405 }
03ecf91a 4406
e901acd6
JF		 4407 /* adding FCoE rx rings to the end */
4408 f->mask = adapter->num_rx_queues;
4409 adapter->num_rx_queues += f->indices;
4410 adapter->num_tx_queues += f->indices;
0331a832 4411
e5b64635
JF		 4412 return true;
4413}
4414#endif /* IXGBE_FCOE */
4415
e901acd6
JF		 4416/* Artificial max queue cap per traffic class in DCB mode */
4417#define DCB_QUEUE_CAP 8
4418
e5b64635
JF		 4419#ifdef CONFIG_IXGBE_DCB
4420static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4421{
e901acd6
JF		 4422 int per_tc_q, q, i, offset = 0;
4423 struct net_device *dev = adapter->netdev;
4424 int tcs = netdev_get_num_tc(dev);
e5b64635 4425
e901acd6
JF		 4426 if (!tcs)
4427 return false;
e5b64635 4428
e901acd6
JF		 4429 /* Map queue offset and counts onto allocated tx queues */
4430 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4431 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4432
8b1c0b24 4433 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4434 netdev_set_prio_tc_map(dev, i, i);
4435 netdev_set_tc_queue(dev, i, q, offset);
4436 offset += q;
0331a832
YZ		 4437 }
4438
e901acd6
JF		 4439 adapter->num_tx_queues = q * tcs;
4440 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4441
4442#ifdef IXGBE_FCOE
e901acd6
JF		 4443 /* FCoE enabled queues require special configuration indexed
4444 * by feature specific indices and mask. Here we map FCoE
4445 * indices onto the DCB queue pairs allowing FCoE to own
4446 * configuration later.
e5b64635 4447 */
e901acd6
JF		 4448 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4449 int tc;
4450 struct ixgbe_ring_feature *f =
4451 &adapter->ring_feature[RING_F_FCOE];
4452
4453 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4454 f->indices = dev->tc_to_txq[tc].count;
4455 f->mask = dev->tc_to_txq[tc].offset;
4456 }
e5b64635
JF		 4457#endif
4458
e901acd6 4459 return true;
0331a832 4460}
e5b64635 4461#endif
0331a832 4462
1cdd1ec8
GR		 4463/**
4464 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4465 * @adapter: board private structure to initialize
4466 *
4467 * IOV doesn't actually use anything, so just NAK the
4468 * request for now and let the other queue routines
4469 * figure out what to do.
4470 */
4471static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4472{
4473 return false;
4474}
4475
4df10466 4476/*
25985edc 4477 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4478 * @adapter: board private structure to initialize
4479 *
4480 * This is the top level queue allocation routine. The order here is very
4481 * important, starting with the "most" number of features turned on at once,
4482 * and ending with the smallest set of features. This way large combinations
4483 * can be allocated if they're turned on, and smaller combinations are the
4484 * fallthrough conditions.
4485 *
4486 **/
847f53ff 4487static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4488{
1cdd1ec8
GR		 4489 /* Start with base case */
4490 adapter->num_rx_queues = 1;
4491 adapter->num_tx_queues = 1;
4492 adapter->num_rx_pools = adapter->num_rx_queues;
4493 adapter->num_rx_queues_per_pool = 1;
4494
4495 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4496 goto done;
1cdd1ec8 4497
bc97114d
PWJ		 4498#ifdef CONFIG_IXGBE_DCB
4499 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4500 goto done;
bc97114d
PWJ		 4501
4502#endif
e5b64635
JF		 4503#ifdef IXGBE_FCOE
4504 if (ixgbe_set_fcoe_queues(adapter))
4505 goto done;
4506
4507#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4508 if (ixgbe_set_fdir_queues(adapter))
4509 goto done;
4510
bc97114d 4511 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4512 goto done;
4513
4514 /* fallback to base case */
4515 adapter->num_rx_queues = 1;
4516 adapter->num_tx_queues = 1;
4517
4518done:
847f53ff 4519 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4520 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4521 return netif_set_real_num_rx_queues(adapter->netdev,
4522 adapter->num_rx_queues);
b9804972
JB		 4523}
4524
021230d4 4525static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4526 int vectors)
021230d4
AV		 4527{
4528 int err, vector_threshold;
4529
4530 /* We'll want at least 3 (vector_threshold):
4531 * 1) TxQ[0] Cleanup
4532 * 2) RxQ[0] Cleanup
4533 * 3) Other (Link Status Change, etc.)
4534 * 4) TCP Timer (optional)
4535 */
4536 vector_threshold = MIN_MSIX_COUNT;
4537
4538 /* The more we get, the more we will assign to Tx/Rx Cleanup
4539 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4540 * Right now, we simply care about how many we'll get; we'll
4541 * set them up later while requesting irq's.
4542 */
4543 while (vectors >= vector_threshold) {
4544 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4545 vectors);
021230d4
AV		 4546 if (!err) /* Success in acquiring all requested vectors. */
4547 break;
4548 else if (err < 0)
4549 vectors = 0; /* Nasty failure, quit now */
4550 else /* err == number of vectors we should try again with */
4551 vectors = err;
4552 }
4553
4554 if (vectors < vector_threshold) {
4555 /* Can't allocate enough MSI-X interrupts? Oh well.
4556 * This just means we'll go with either a single MSI
4557 * vector or fall back to legacy interrupts.
4558 */
849c4542
ET		 4559 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4560 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4561 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4562 kfree(adapter->msix_entries);
4563 adapter->msix_entries = NULL;
021230d4
AV		 4564 } else {
4565 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4566 /*
4567 * Adjust for only the vectors we'll use, which is minimum
4568 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4569 * vectors we were allocated.
4570 */
4571 adapter->num_msix_vectors = min(vectors,
e8e9f696 4572 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4573 }
4574}
4575
021230d4 4576/**
bc97114d 4577 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4578 * @adapter: board private structure to initialize
4579 *
bc97114d
PWJ		 4580 * Cache the descriptor ring offsets for RSS to the assigned rings.
4581 *
021230d4 4582 **/
bc97114d 4583static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4584{
bc97114d 4585 int i;
bc97114d 4586
9d6b758f
AD		 4587 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4588 return false;
bc97114d 4589
9d6b758f
AD		 4590 for (i = 0; i < adapter->num_rx_queues; i++)
4591 adapter->rx_ring[i]->reg_idx = i;
4592 for (i = 0; i < adapter->num_tx_queues; i++)
4593 adapter->tx_ring[i]->reg_idx = i;
4594
4595 return true;
bc97114d
PWJ		 4596}
4597
4598#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4599
4600/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4601static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4602 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4603{
4604 struct net_device *dev = adapter->netdev;
4605 struct ixgbe_hw *hw = &adapter->hw;
4606 u8 num_tcs = netdev_get_num_tc(dev);
4607
4608 *tx = 0;
4609 *rx = 0;
4610
4611 switch (hw->mac.type) {
4612 case ixgbe_mac_82598EB:
aba70d5e
JF		 4613 *tx = tc << 2;
4614 *rx = tc << 3;
e5b64635
JF		 4615 break;
4616 case ixgbe_mac_82599EB:
4617 case ixgbe_mac_X540:
4618 if (num_tcs == 8) {
4619 if (tc < 3) {
4620 *tx = tc << 5;
4621 *rx = tc << 4;
4622 } else if (tc < 5) {
4623 *tx = ((tc + 2) << 4);
4624 *rx = tc << 4;
4625 } else if (tc < num_tcs) {
4626 *tx = ((tc + 8) << 3);
4627 *rx = tc << 4;
4628 }
4629 } else if (num_tcs == 4) {
4630 *rx = tc << 5;
4631 switch (tc) {
4632 case 0:
4633 *tx = 0;
4634 break;
4635 case 1:
4636 *tx = 64;
4637 break;
4638 case 2:
4639 *tx = 96;
4640 break;
4641 case 3:
4642 *tx = 112;
4643 break;
4644 default:
4645 break;
4646 }
4647 }
4648 break;
4649 default:
4650 break;
4651 }
4652}
4653
bc97114d
PWJ		 4654/**
4655 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4656 * @adapter: board private structure to initialize
4657 *
4658 * Cache the descriptor ring offsets for DCB to the assigned rings.
4659 *
4660 **/
4661static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4662{
e5b64635
JF		 4663 struct net_device *dev = adapter->netdev;
4664 int i, j, k;
4665 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4666
8b1c0b24 4667 if (!num_tcs)
bd508178 4668 return false;
f92ef202 4669
e5b64635
JF		 4670 for (i = 0, k = 0; i < num_tcs; i++) {
4671 unsigned int tx_s, rx_s;
4672 u16 count = dev->tc_to_txq[i].count;
4673
4674 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4675 for (j = 0; j < count; j++, k++) {
4676 adapter->tx_ring[k]->reg_idx = tx_s + j;
4677 adapter->rx_ring[k]->reg_idx = rx_s + j;
4678 adapter->tx_ring[k]->dcb_tc = i;
4679 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4680 }
021230d4 4681 }
e5b64635
JF		 4682
4683 return true;
bc97114d
PWJ		 4684}
4685#endif
4686
c4cf55e5
PWJ		 4687/**
4688 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4689 * @adapter: board private structure to initialize
4690 *
4691 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4692 *
4693 **/
e8e9f696 4694static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4695{
4696 int i;
4697 bool ret = false;
4698
03ecf91a
AD		 4699 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4700 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4701 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4702 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4703 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4704 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4705 ret = true;
4706 }
4707
4708 return ret;
4709}
4710
0331a832
YZ		 4711#ifdef IXGBE_FCOE
4712/**
4713 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4714 * @adapter: board private structure to initialize
4715 *
4716 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4717 *
4718 */
4719static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4720{
0331a832 4721 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4722 int i;
4723 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4724
4725 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4726 return false;
0331a832 4727
bf29ee6c 4728 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4729 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4730 ixgbe_cache_ring_fdir(adapter);
4731 else
4732 ixgbe_cache_ring_rss(adapter);
8faa2a78 4733
bf29ee6c
AD		 4734 fcoe_rx_i = f->mask;
4735 fcoe_tx_i = f->mask;
0331a832 4736 }
bf29ee6c
AD		 4737 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4738 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4739 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4740 }
4741 return true;
0331a832
YZ		 4742}
4743
4744#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4745/**
4746 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4747 * @adapter: board private structure to initialize
4748 *
4749 * SR-IOV doesn't use any descriptor rings but changes the default if
4750 * no other mapping is used.
4751 *
4752 */
4753static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4754{
4a0b9ca0
PW		 4755 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4756 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4757 if (adapter->num_vfs)
4758 return true;
4759 else
4760 return false;
4761}
4762
bc97114d
PWJ		 4763/**
4764 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4765 * @adapter: board private structure to initialize
4766 *
4767 * Once we know the feature-set enabled for the device, we'll cache
4768 * the register offset the descriptor ring is assigned to.
4769 *
4770 * Note, the order the various feature calls is important. It must start with
4771 * the "most" features enabled at the same time, then trickle down to the
4772 * least amount of features turned on at once.
4773 **/
4774static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4775{
4776 /* start with default case */
4a0b9ca0
PW		 4777 adapter->rx_ring[0]->reg_idx = 0;
4778 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4779
1cdd1ec8
GR		 4780 if (ixgbe_cache_ring_sriov(adapter))
4781 return;
4782
e5b64635
JF		 4783#ifdef CONFIG_IXGBE_DCB
4784 if (ixgbe_cache_ring_dcb(adapter))
4785 return;
4786#endif
4787
0331a832
YZ		 4788#ifdef IXGBE_FCOE
4789 if (ixgbe_cache_ring_fcoe(adapter))
4790 return;
0331a832 4791#endif /* IXGBE_FCOE */
bc97114d 4792
c4cf55e5
PWJ		 4793 if (ixgbe_cache_ring_fdir(adapter))
4794 return;
4795
bc97114d
PWJ		 4796 if (ixgbe_cache_ring_rss(adapter))
4797 return;
021230d4
AV		 4798}
4799
9a799d71
AK		 4800/**
4801 * ixgbe_alloc_queues - Allocate memory for all rings
4802 * @adapter: board private structure to initialize
4803 *
4804 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4805 * number of queues at compile-time. The polling_netdev array is
4806 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4807 **/
2f90b865 4808static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4809{
e2ddeba9 4810 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4811
e2ddeba9
ED		 4812 if (nid < 0 || !node_online(nid))
4813 nid = first_online_node;
4814
4815 for (; tx < adapter->num_tx_queues; tx++) {
4816 struct ixgbe_ring *ring;
4817
4818 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4819 if (!ring)
e2ddeba9 4820 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4821 if (!ring)
e2ddeba9 4822 goto err_allocation;
4a0b9ca0 4823 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4824 ring->queue_index = tx;
4825 ring->numa_node = nid;
b6ec895e 4826 ring->dev = &adapter->pdev->dev;
fc77dc3c 4827 ring->netdev = adapter->netdev;
4a0b9ca0 4828
e2ddeba9 4829 adapter->tx_ring[tx] = ring;
021230d4 4830 }
b9804972 4831
e2ddeba9
ED		 4832 for (; rx < adapter->num_rx_queues; rx++) {
4833 struct ixgbe_ring *ring;
4a0b9ca0 4834
e2ddeba9 4835 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4836 if (!ring)
e2ddeba9 4837 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4838 if (!ring)
e2ddeba9
ED		 4839 goto err_allocation;
4840 ring->count = adapter->rx_ring_count;
4841 ring->queue_index = rx;
4842 ring->numa_node = nid;
b6ec895e 4843 ring->dev = &adapter->pdev->dev;
fc77dc3c 4844 ring->netdev = adapter->netdev;
4a0b9ca0 4845
e2ddeba9 4846 adapter->rx_ring[rx] = ring;
021230d4
AV		 4847 }
4848
4849 ixgbe_cache_ring_register(adapter);
4850
4851 return 0;
4852
e2ddeba9
ED		 4853err_allocation:
4854 while (tx)
4855 kfree(adapter->tx_ring[--tx]);
4856
4857 while (rx)
4858 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4859 return -ENOMEM;
4860}
4861
4862/**
4863 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4864 * @adapter: board private structure to initialize
4865 *
4866 * Attempt to configure the interrupts using the best available
4867 * capabilities of the hardware and the kernel.
4868 **/
feea6a57 4869static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4870{
8be0e467 4871 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4872 int err = 0;
4873 int vector, v_budget;
4874
4875 /*
4876 * It's easy to be greedy for MSI-X vectors, but it really
4877 * doesn't do us much good if we have a lot more vectors
4878 * than CPU's. So let's be conservative and only ask for
342bde1b 4879 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4880 */
4881 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4882 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4883
4884 /*
4885 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4886 * hw.mac->max_msix_vectors vectors. With features
4887 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4888 * descriptor queues supported by our device. Thus, we cap it off in
4889 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4890 */
8be0e467 4891 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4892
4893 /* A failure in MSI-X entry allocation isn't fatal, but it does
4894 * mean we disable MSI-X capabilities of the adapter. */
4895 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4896 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4897 if (adapter->msix_entries) {
4898 for (vector = 0; vector < v_budget; vector++)
4899 adapter->msix_entries[vector].entry = vector;
021230d4 4900
7a921c93 4901 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4902
7a921c93
AD		 4903 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4904 goto out;
4905 }
26d27844 4906
7a921c93
AD		 4907 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4908 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4909 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4910 e_err(probe,
03ecf91a 4911 "ATR is not supported while multiple "
45b9f509
AD		 4912 "queues are disabled. Disabling Flow Director\n");
4913 }
c4cf55e5 4914 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4915 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4916 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4917 ixgbe_disable_sriov(adapter);
4918
847f53ff
BH		 4919 err = ixgbe_set_num_queues(adapter);
4920 if (err)
4921 return err;
021230d4 4922
021230d4
AV		 4923 err = pci_enable_msi(adapter->pdev);
4924 if (!err) {
4925 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4926 } else {
849c4542
ET		 4927 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4928 "Unable to allocate MSI interrupt, "
4929 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4930 /* reset err */
4931 err = 0;
4932 }
4933
4934out:
021230d4
AV		 4935 return err;
4936}
4937
7a921c93
AD		 4938/**
4939 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4940 * @adapter: board private structure to initialize
4941 *
4942 * We allocate one q_vector per queue interrupt. If allocation fails we
4943 * return -ENOMEM.
4944 **/
4945static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4946{
4947 int q_idx, num_q_vectors;
4948 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4949 int (*poll)(struct napi_struct *, int);
4950
4951 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4952 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4953 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4954 } else {
4955 num_q_vectors = 1;
7a921c93
AD		 4956 poll = &ixgbe_poll;
4957 }
4958
4959 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4960 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4961 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4962 if (!q_vector)
4963 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4964 GFP_KERNEL);
7a921c93
AD		 4965 if (!q_vector)
4966 goto err_out;
4967 q_vector->adapter = adapter;
f7554a2b
NS		 4968 if (q_vector->txr_count && !q_vector->rxr_count)
4969 q_vector->eitr = adapter->tx_eitr_param;
4970 else
4971 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4972 q_vector->v_idx = q_idx;
91281fd3 4973 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4974 adapter->q_vector[q_idx] = q_vector;
4975 }
4976
4977 return 0;
4978
4979err_out:
4980 while (q_idx) {
4981 q_idx--;
4982 q_vector = adapter->q_vector[q_idx];
4983 netif_napi_del(&q_vector->napi);
4984 kfree(q_vector);
4985 adapter->q_vector[q_idx] = NULL;
4986 }
4987 return -ENOMEM;
4988}
4989
4990/**
4991 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4992 * @adapter: board private structure to initialize
4993 *
4994 * This function frees the memory allocated to the q_vectors. In addition if
4995 * NAPI is enabled it will delete any references to the NAPI struct prior
4996 * to freeing the q_vector.
4997 **/
4998static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4999{
5000 int q_idx, num_q_vectors;
7a921c93 5001
91281fd3 5002 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 5003 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5004 else
7a921c93 5005 num_q_vectors = 1;
7a921c93
AD		 5006
5007 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5008 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 5009 adapter->q_vector[q_idx] = NULL;
91281fd3 5010 netif_napi_del(&q_vector->napi);
7a921c93
AD		 5011 kfree(q_vector);
5012 }
5013}
5014
7b25cdba 5015static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5016{
5017 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5018 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5019 pci_disable_msix(adapter->pdev);
5020 kfree(adapter->msix_entries);
5021 adapter->msix_entries = NULL;
5022 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5023 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5024 pci_disable_msi(adapter->pdev);
5025 }
021230d4
AV		 5026}
5027
5028/**
5029 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5030 * @adapter: board private structure to initialize
5031 *
5032 * We determine which interrupt scheme to use based on...
5033 * - Kernel support (MSI, MSI-X)
5034 * - which can be user-defined (via MODULE_PARAM)
5035 * - Hardware queue count (num_*_queues)
5036 * - defined by miscellaneous hardware support/features (RSS, etc.)
5037 **/
2f90b865 5038int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5039{
5040 int err;
5041
5042 /* Number of supported queues */
847f53ff
BH		 5043 err = ixgbe_set_num_queues(adapter);
5044 if (err)
5045 return err;
021230d4 5046
021230d4
AV		 5047 err = ixgbe_set_interrupt_capability(adapter);
5048 if (err) {
849c4542 5049 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5050 goto err_set_interrupt;
9a799d71
AK		 5051 }
5052
7a921c93
AD		 5053 err = ixgbe_alloc_q_vectors(adapter);
5054 if (err) {
849c4542 5055 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5056 goto err_alloc_q_vectors;
5057 }
5058
5059 err = ixgbe_alloc_queues(adapter);
5060 if (err) {
849c4542 5061 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5062 goto err_alloc_queues;
5063 }
5064
849c4542 5065 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5066 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5067 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5068
5069 set_bit(__IXGBE_DOWN, &adapter->state);
5070
9a799d71 5071 return 0;
021230d4 5072
7a921c93
AD		 5073err_alloc_queues:
5074 ixgbe_free_q_vectors(adapter);
5075err_alloc_q_vectors:
5076 ixgbe_reset_interrupt_capability(adapter);
021230d4 5077err_set_interrupt:
7a921c93
AD		 5078 return err;
5079}
5080
5081/**
5082 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5083 * @adapter: board private structure to clear interrupt scheme on
5084 *
5085 * We go through and clear interrupt specific resources and reset the structure
5086 * to pre-load conditions
5087 **/
5088void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5089{
4a0b9ca0
PW		 5090 int i;
5091
5092 for (i = 0; i < adapter->num_tx_queues; i++) {
5093 kfree(adapter->tx_ring[i]);
5094 adapter->tx_ring[i] = NULL;
5095 }
5096 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5097 struct ixgbe_ring *ring = adapter->rx_ring[i];
5098
5099 /* ixgbe_get_stats64() might access this ring, we must wait
5100 * a grace period before freeing it.
5101 */
bcec8b65 5102 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 5103 adapter->rx_ring[i] = NULL;
5104 }
7a921c93 5105
b8eb3a10
DS		 5106 adapter->num_tx_queues = 0;
5107 adapter->num_rx_queues = 0;
5108
7a921c93
AD		 5109 ixgbe_free_q_vectors(adapter);
5110 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5111}
5112
5113/**
5114 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5115 * @adapter: board private structure to initialize
5116 *
5117 * ixgbe_sw_init initializes the Adapter private data structure.
5118 * Fields are initialized based on PCI device information and
5119 * OS network device settings (MTU size).
5120 **/
5121static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5122{
5123 struct ixgbe_hw *hw = &adapter->hw;
5124 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5125 struct net_device *dev = adapter->netdev;
021230d4 5126 unsigned int rss;
7a6b6f51 5127#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5128 int j;
5129 struct tc_configuration *tc;
5130#endif
16b61beb 5131 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5132
c44ade9e
JB		 5133 /* PCI config space info */
5134
5135 hw->vendor_id = pdev->vendor;
5136 hw->device_id = pdev->device;
5137 hw->revision_id = pdev->revision;
5138 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5139 hw->subsystem_device_id = pdev->subsystem_device;
5140
021230d4
AV		 5141 /* Set capability flags */
5142 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5143 adapter->ring_feature[RING_F_RSS].indices = rss;
5144 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5145 switch (hw->mac.type) {
5146 case ixgbe_mac_82598EB:
bf069c97
DS		 5147 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5148 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5149 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5150 break;
5151 case ixgbe_mac_82599EB:
b93a2226 5152 case ixgbe_mac_X540:
e8e26350 5153 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5154 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5155 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5156 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5157 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5158 /* n-tuple support exists, always init our spinlock */
5159 spin_lock_init(&adapter->fdir_perfect_lock);
5160 /* Flow Director hash filters enabled */
5161 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5162 adapter->atr_sample_rate = 20;
c4cf55e5 5163 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5164 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5165 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5166#ifdef IXGBE_FCOE
0d551589
YZ		 5167 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5168 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5169 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5170#ifdef CONFIG_IXGBE_DCB
6ee16520 5171 /* Default traffic class to use for FCoE */
56075a98 5172 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5173#endif
eacd73f7 5174#endif /* IXGBE_FCOE */
bd508178
AD		 5175 break;
5176 default:
5177 break;
f8212f97 5178 }
2f90b865 5179
7a6b6f51 5180#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5181 /* Configure DCB traffic classes */
5182 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5183 tc = &adapter->dcb_cfg.tc_config[j];
5184 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5185 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5186 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5187 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5188 tc->dcb_pfc = pfc_disabled;
5189 }
5190 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5191 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5192 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5193 adapter->dcb_set_bitmap = 0x00;
3032309b 5194 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5195 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5196 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5197
5198#endif
9a799d71
AK		 5199
5200 /* default flow control settings */
cd7664f6 5201 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5202 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5203#ifdef CONFIG_DCB
5204 adapter->last_lfc_mode = hw->fc.current_mode;
5205#endif
16b61beb
JF		 5206 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5207 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5208 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5209 hw->fc.send_xon = true;
71fd570b 5210 hw->fc.disable_fc_autoneg = false;
9a799d71 5211
30efa5a3 5212 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5213 adapter->rx_itr_setting = 1;
5214 adapter->rx_eitr_param = 20000;
5215 adapter->tx_itr_setting = 1;
5216 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5217
5218 /* set defaults for eitr in MegaBytes */
5219 adapter->eitr_low = 10;
5220 adapter->eitr_high = 20;
5221
5222 /* set default ring sizes */
5223 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5224 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5225
9a799d71 5226 /* initialize eeprom parameters */
c44ade9e 5227 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5228 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5229 return -EIO;
5230 }
5231
021230d4 5232 /* enable rx csum by default */
9a799d71
AK		 5233 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5234
1a6c14a2
JB		 5235 /* get assigned NUMA node */
5236 adapter->node = dev_to_node(&pdev->dev);
5237
9a799d71
AK		 5238 set_bit(__IXGBE_DOWN, &adapter->state);
5239
5240 return 0;
5241}
5242
5243/**
5244 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5245 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5246 *
5247 * Return 0 on success, negative on failure
5248 **/
b6ec895e 5249int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5250{
b6ec895e 5251 struct device *dev = tx_ring->dev;
9a799d71
AK		 5252 int size;
5253
3a581073 5254 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5255 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5256 if (!tx_ring->tx_buffer_info)
89bf67f1 5257 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5258 if (!tx_ring->tx_buffer_info)
5259 goto err;
9a799d71
AK		 5260
5261 /* round up to nearest 4K */
12207e49 5262 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5263 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5264
b6ec895e 5265 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5266 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5267 if (!tx_ring->desc)
5268 goto err;
9a799d71 5269
3a581073
JB		 5270 tx_ring->next_to_use = 0;
5271 tx_ring->next_to_clean = 0;
5272 tx_ring->work_limit = tx_ring->count;
9a799d71 5273 return 0;
e01c31a5
JB		 5274
5275err:
5276 vfree(tx_ring->tx_buffer_info);
5277 tx_ring->tx_buffer_info = NULL;
b6ec895e 5278 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5279 return -ENOMEM;
9a799d71
AK		 5280}
5281
69888674
AD		 5282/**
5283 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5284 * @adapter: board private structure
5285 *
5286 * If this function returns with an error, then it's possible one or
5287 * more of the rings is populated (while the rest are not). It is the
5288 * callers duty to clean those orphaned rings.
5289 *
5290 * Return 0 on success, negative on failure
5291 **/
5292static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5293{
5294 int i, err = 0;
5295
5296 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5297 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5298 if (!err)
5299 continue;
396e799c 5300 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5301 break;
5302 }
5303
5304 return err;
5305}
5306
9a799d71
AK		 5307/**
5308 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5309 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5310 *
5311 * Returns 0 on success, negative on failure
5312 **/
b6ec895e 5313int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5314{
b6ec895e 5315 struct device *dev = rx_ring->dev;
021230d4 5316 int size;
9a799d71 5317
3a581073 5318 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5319 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5320 if (!rx_ring->rx_buffer_info)
89bf67f1 5321 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5322 if (!rx_ring->rx_buffer_info)
5323 goto err;
9a799d71 5324
9a799d71 5325 /* Round up to nearest 4K */
3a581073
JB		 5326 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5327 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5328
b6ec895e 5329 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5330 &rx_ring->dma, GFP_KERNEL);
9a799d71 5331
b6ec895e
AD		 5332 if (!rx_ring->desc)
5333 goto err;
9a799d71 5334
3a581073
JB		 5335 rx_ring->next_to_clean = 0;
5336 rx_ring->next_to_use = 0;
9a799d71
AK		 5337
5338 return 0;
b6ec895e
AD		 5339err:
5340 vfree(rx_ring->rx_buffer_info);
5341 rx_ring->rx_buffer_info = NULL;
5342 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5343 return -ENOMEM;
9a799d71
AK		 5344}
5345
69888674
AD		 5346/**
5347 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5348 * @adapter: board private structure
5349 *
5350 * If this function returns with an error, then it's possible one or
5351 * more of the rings is populated (while the rest are not). It is the
5352 * callers duty to clean those orphaned rings.
5353 *
5354 * Return 0 on success, negative on failure
5355 **/
69888674
AD		 5356static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5357{
5358 int i, err = 0;
5359
5360 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5361 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5362 if (!err)
5363 continue;
396e799c 5364 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5365 break;
5366 }
5367
5368 return err;
5369}
5370
9a799d71
AK		 5371/**
5372 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5373 * @tx_ring: Tx descriptor ring for a specific queue
5374 *
5375 * Free all transmit software resources
5376 **/
b6ec895e 5377void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5378{
b6ec895e 5379 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5380
5381 vfree(tx_ring->tx_buffer_info);
5382 tx_ring->tx_buffer_info = NULL;
5383
b6ec895e
AD		 5384 /* if not set, then don't free */
5385 if (!tx_ring->desc)
5386 return;
5387
5388 dma_free_coherent(tx_ring->dev, tx_ring->size,
5389 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5390
5391 tx_ring->desc = NULL;
5392}
5393
5394/**
5395 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5396 * @adapter: board private structure
5397 *
5398 * Free all transmit software resources
5399 **/
5400static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5401{
5402 int i;
5403
5404 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5405 if (adapter->tx_ring[i]->desc)
b6ec895e 5406 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5407}
5408
5409/**
b4617240 5410 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5411 * @rx_ring: ring to clean the resources from
5412 *
5413 * Free all receive software resources
5414 **/
b6ec895e 5415void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5416{
b6ec895e 5417 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5418
5419 vfree(rx_ring->rx_buffer_info);
5420 rx_ring->rx_buffer_info = NULL;
5421
b6ec895e
AD		 5422 /* if not set, then don't free */
5423 if (!rx_ring->desc)
5424 return;
5425
5426 dma_free_coherent(rx_ring->dev, rx_ring->size,
5427 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5428
5429 rx_ring->desc = NULL;
5430}
5431
5432/**
5433 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5434 * @adapter: board private structure
5435 *
5436 * Free all receive software resources
5437 **/
5438static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5439{
5440 int i;
5441
5442 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5443 if (adapter->rx_ring[i]->desc)
b6ec895e 5444 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5445}
5446
9a799d71
AK		 5447/**
5448 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5449 * @netdev: network interface device structure
5450 * @new_mtu: new value for maximum frame size
5451 *
5452 * Returns 0 on success, negative on failure
5453 **/
5454static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5455{
5456 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5457 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5458 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5459
42c783c5 5460 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5461 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5462 hw->mac.type != ixgbe_mac_X540) {
5463 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5464 return -EINVAL;
5465 } else {
5466 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5467 return -EINVAL;
5468 }
9a799d71 5469
396e799c 5470 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5471 /* must set new MTU before calling down or up */
9a799d71
AK		 5472 netdev->mtu = new_mtu;
5473
16b61beb
JF		 5474 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5475 hw->fc.low_water = FC_LOW_WATER(max_frame);
5476
d4f80882
AV		 5477 if (netif_running(netdev))
5478 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5479
5480 return 0;
5481}
5482
5483/**
5484 * ixgbe_open - Called when a network interface is made active
5485 * @netdev: network interface device structure
5486 *
5487 * Returns 0 on success, negative value on failure
5488 *
5489 * The open entry point is called when a network interface is made
5490 * active by the system (IFF_UP). At this point all resources needed
5491 * for transmit and receive operations are allocated, the interrupt
5492 * handler is registered with the OS, the watchdog timer is started,
5493 * and the stack is notified that the interface is ready.
5494 **/
5495static int ixgbe_open(struct net_device *netdev)
5496{
5497 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5498 int err;
4bebfaa5
AK		 5499
5500 /* disallow open during test */
5501 if (test_bit(__IXGBE_TESTING, &adapter->state))
5502 return -EBUSY;
9a799d71 5503
54386467
JB		 5504 netif_carrier_off(netdev);
5505
9a799d71
AK		 5506 /* allocate transmit descriptors */
5507 err = ixgbe_setup_all_tx_resources(adapter);
5508 if (err)
5509 goto err_setup_tx;
5510
9a799d71
AK		 5511 /* allocate receive descriptors */
5512 err = ixgbe_setup_all_rx_resources(adapter);
5513 if (err)
5514 goto err_setup_rx;
5515
5516 ixgbe_configure(adapter);
5517
021230d4 5518 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5519 if (err)
5520 goto err_req_irq;
5521
9a799d71
AK		 5522 err = ixgbe_up_complete(adapter);
5523 if (err)
5524 goto err_up;
5525
d55b53ff
JK		 5526 netif_tx_start_all_queues(netdev);
5527
9a799d71
AK		 5528 return 0;
5529
5530err_up:
5eba3699 5531 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5532 ixgbe_free_irq(adapter);
5533err_req_irq:
9a799d71 5534err_setup_rx:
a20a1199 5535 ixgbe_free_all_rx_resources(adapter);
9a799d71 5536err_setup_tx:
a20a1199 5537 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5538 ixgbe_reset(adapter);
5539
5540 return err;
5541}
5542
5543/**
5544 * ixgbe_close - Disables a network interface
5545 * @netdev: network interface device structure
5546 *
5547 * Returns 0, this is not allowed to fail
5548 *
5549 * The close entry point is called when an interface is de-activated
5550 * by the OS. The hardware is still under the drivers control, but
5551 * needs to be disabled. A global MAC reset is issued to stop the
5552 * hardware, and all transmit and receive resources are freed.
5553 **/
5554static int ixgbe_close(struct net_device *netdev)
5555{
5556 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5557
5558 ixgbe_down(adapter);
5559 ixgbe_free_irq(adapter);
5560
e4911d57
AD		 5561 ixgbe_fdir_filter_exit(adapter);
5562
9a799d71
AK		 5563 ixgbe_free_all_tx_resources(adapter);
5564 ixgbe_free_all_rx_resources(adapter);
5565
5eba3699 5566 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5567
5568 return 0;
5569}
5570
b3c8b4ba
AD		 5571#ifdef CONFIG_PM
5572static int ixgbe_resume(struct pci_dev *pdev)
5573{
c60fbb00
AD		 5574 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5575 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5576 u32 err;
5577
5578 pci_set_power_state(pdev, PCI_D0);
5579 pci_restore_state(pdev);
656ab817
DS		 5580 /*
5581 * pci_restore_state clears dev->state_saved so call
5582 * pci_save_state to restore it.
5583 */
5584 pci_save_state(pdev);
9ce77666 5585
5586 err = pci_enable_device_mem(pdev);
b3c8b4ba 5587 if (err) {
849c4542 5588 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5589 return err;
5590 }
5591 pci_set_master(pdev);
5592
dd4d8ca6 5593 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5594
5595 err = ixgbe_init_interrupt_scheme(adapter);
5596 if (err) {
849c4542 5597 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5598 return err;
5599 }
5600
b3c8b4ba
AD		 5601 ixgbe_reset(adapter);
5602
495dce12
WJP		 5603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5604
b3c8b4ba 5605 if (netif_running(netdev)) {
c60fbb00 5606 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5607 if (err)
5608 return err;
5609 }
5610
5611 netif_device_attach(netdev);
5612
5613 return 0;
5614}
b3c8b4ba 5615#endif /* CONFIG_PM */
9d8d05ae
RW		 5616
5617static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5618{
c60fbb00
AD		 5619 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5620 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5621 struct ixgbe_hw *hw = &adapter->hw;
5622 u32 ctrl, fctrl;
5623 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5624#ifdef CONFIG_PM
5625 int retval = 0;
5626#endif
5627
5628 netif_device_detach(netdev);
5629
5630 if (netif_running(netdev)) {
5631 ixgbe_down(adapter);
5632 ixgbe_free_irq(adapter);
5633 ixgbe_free_all_tx_resources(adapter);
5634 ixgbe_free_all_rx_resources(adapter);
5635 }
b3c8b4ba 5636
5f5ae6fc 5637 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5638#ifdef CONFIG_DCB
5639 kfree(adapter->ixgbe_ieee_pfc);
5640 kfree(adapter->ixgbe_ieee_ets);
5641#endif
5f5ae6fc 5642
b3c8b4ba
AD		 5643#ifdef CONFIG_PM
5644 retval = pci_save_state(pdev);
5645 if (retval)
5646 return retval;
4df10466 5647
b3c8b4ba 5648#endif
e8e26350
PW		 5649 if (wufc) {
5650 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5651
e8e26350
PW		 5652 /* turn on all-multi mode if wake on multicast is enabled */
5653 if (wufc & IXGBE_WUFC_MC) {
5654 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5655 fctrl |= IXGBE_FCTRL_MPE;
5656 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5657 }
5658
5659 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5660 ctrl |= IXGBE_CTRL_GIO_DIS;
5661 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5662
5663 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5664 } else {
5665 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5666 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5667 }
5668
bd508178
AD		 5669 switch (hw->mac.type) {
5670 case ixgbe_mac_82598EB:
dd4d8ca6 5671 pci_wake_from_d3(pdev, false);
bd508178
AD		 5672 break;
5673 case ixgbe_mac_82599EB:
b93a2226 5674 case ixgbe_mac_X540:
bd508178
AD		 5675 pci_wake_from_d3(pdev, !!wufc);
5676 break;
5677 default:
5678 break;
5679 }
b3c8b4ba 5680
9d8d05ae
RW		 5681 *enable_wake = !!wufc;
5682
b3c8b4ba
AD		 5683 ixgbe_release_hw_control(adapter);
5684
5685 pci_disable_device(pdev);
5686
9d8d05ae
RW		 5687 return 0;
5688}
5689
5690#ifdef CONFIG_PM
5691static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5692{
5693 int retval;
5694 bool wake;
5695
5696 retval = __ixgbe_shutdown(pdev, &wake);
5697 if (retval)
5698 return retval;
5699
5700 if (wake) {
5701 pci_prepare_to_sleep(pdev);
5702 } else {
5703 pci_wake_from_d3(pdev, false);
5704 pci_set_power_state(pdev, PCI_D3hot);
5705 }
b3c8b4ba
AD		 5706
5707 return 0;
5708}
9d8d05ae 5709#endif /* CONFIG_PM */
b3c8b4ba
AD		 5710
5711static void ixgbe_shutdown(struct pci_dev *pdev)
5712{
9d8d05ae
RW		 5713 bool wake;
5714
5715 __ixgbe_shutdown(pdev, &wake);
5716
5717 if (system_state == SYSTEM_POWER_OFF) {
5718 pci_wake_from_d3(pdev, wake);
5719 pci_set_power_state(pdev, PCI_D3hot);
5720 }
b3c8b4ba
AD		 5721}
5722
9a799d71
AK		 5723/**
5724 * ixgbe_update_stats - Update the board statistics counters.
5725 * @adapter: board private structure
5726 **/
5727void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5728{
2d86f139 5729 struct net_device *netdev = adapter->netdev;
9a799d71 5730 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5731 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5732 u64 total_mpc = 0;
5733 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5734 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5735 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5736 u64 bytes = 0, packets = 0;
9a799d71 5737
d08935c2
DS		 5738 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5739 test_bit(__IXGBE_RESETTING, &adapter->state))
5740 return;
5741
94b982b2 5742 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5743 u64 rsc_count = 0;
94b982b2 5744 u64 rsc_flush = 0;
d51019a4
PW		 5745 for (i = 0; i < 16; i++)
5746 adapter->hw_rx_no_dma_resources +=
7ca647bd 5747 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5748 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5749 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5750 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5751 }
5752 adapter->rsc_total_count = rsc_count;
5753 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5754 }
5755
5b7da515
AD		 5756 for (i = 0; i < adapter->num_rx_queues; i++) {
5757 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5758 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5759 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5760 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5761 bytes += rx_ring->stats.bytes;
5762 packets += rx_ring->stats.packets;
5763 }
5764 adapter->non_eop_descs = non_eop_descs;
5765 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5766 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5767 netdev->stats.rx_bytes = bytes;
5768 netdev->stats.rx_packets = packets;
5769
5770 bytes = 0;
5771 packets = 0;
7ca3bc58 5772 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5773 for (i = 0; i < adapter->num_tx_queues; i++) {
5774 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5775 restart_queue += tx_ring->tx_stats.restart_queue;
5776 tx_busy += tx_ring->tx_stats.tx_busy;
5777 bytes += tx_ring->stats.bytes;
5778 packets += tx_ring->stats.packets;
5779 }
eb985f09 5780 adapter->restart_queue = restart_queue;
5b7da515
AD		 5781 adapter->tx_busy = tx_busy;
5782 netdev->stats.tx_bytes = bytes;
5783 netdev->stats.tx_packets = packets;
7ca3bc58 5784
7ca647bd 5785 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5786 for (i = 0; i < 8; i++) {
5787 /* for packet buffers not used, the register should read 0 */
5788 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5789 missed_rx += mpc;
7ca647bd
JP		 5790 hwstats->mpc[i] += mpc;
5791 total_mpc += hwstats->mpc[i];
e8e26350 5792 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5793 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5794 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5795 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5796 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5797 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5798 switch (hw->mac.type) {
5799 case ixgbe_mac_82598EB:
7ca647bd
JP		 5800 hwstats->pxonrxc[i] +=
5801 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5802 break;
5803 case ixgbe_mac_82599EB:
b93a2226 5804 case ixgbe_mac_X540:
bd508178
AD		 5805 hwstats->pxonrxc[i] +=
5806 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5807 break;
5808 default:
5809 break;
e8e26350 5810 }
7ca647bd
JP		 5811 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5812 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5813 }
7ca647bd 5814 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5815 /* work around hardware counting issue */
7ca647bd 5816 hwstats->gprc -= missed_rx;
6f11eef7 5817
c84d324c
JF		 5818 ixgbe_update_xoff_received(adapter);
5819
6f11eef7 5820 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5821 switch (hw->mac.type) {
5822 case ixgbe_mac_82598EB:
5823 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5824 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5825 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5826 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5827 break;
b93a2226 5828 case ixgbe_mac_X540:
58f6bcf9
ET		 5829 /* OS2BMC stats are X540 only*/
5830 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5831 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5832 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5833 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5834 case ixgbe_mac_82599EB:
7ca647bd 5835 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5836 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5837 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5838 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5839 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5840 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5841 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5842 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5843 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5844#ifdef IXGBE_FCOE
7ca647bd
JP		 5845 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5846 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5847 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5848 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5849 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5850 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5851#endif /* IXGBE_FCOE */
bd508178
AD		 5852 break;
5853 default:
5854 break;
e8e26350 5855 }
9a799d71 5856 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5857 hwstats->bprc += bprc;
5858 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5859 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5860 hwstats->mprc -= bprc;
5861 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5862 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5863 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5864 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5865 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5866 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5867 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5868 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5869 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5870 hwstats->lxontxc += lxon;
6f11eef7 5871 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5872 hwstats->lxofftxc += lxoff;
5873 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5874 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5875 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5876 /*
5877 * 82598 errata - tx of flow control packets is included in tx counters
5878 */
5879 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5880 hwstats->gptc -= xon_off_tot;
5881 hwstats->mptc -= xon_off_tot;
5882 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5883 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5884 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5885 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5886 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5887 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5888 hwstats->ptc64 -= xon_off_tot;
5889 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5890 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5891 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5892 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5893 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5894 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5895
5896 /* Fill out the OS statistics structure */
7ca647bd 5897 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5898
5899 /* Rx Errors */
7ca647bd 5900 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5901 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5902 netdev->stats.rx_length_errors = hwstats->rlec;
5903 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5904 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5905}
5906
5907/**
d034acf1
AD		 5908 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5909 * @adapter - pointer to the device adapter structure
9a799d71 5910 **/
d034acf1 5911static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5912{
cf8280ee 5913 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5914 int i;
cf8280ee 5915
d034acf1
AD		 5916 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5917 return;
5918
5919 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5920
d034acf1 5921 /* if interface is down do nothing */
fe49f04a 5922 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5923 return;
5924
5925 /* do nothing if we are not using signature filters */
5926 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5927 return;
5928
5929 adapter->fdir_overflow++;
5930
93c52dd0
AD		 5931 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5932 for (i = 0; i < adapter->num_tx_queues; i++)
5933 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5934 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5935 /* re-enable flow director interrupts */
5936 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5937 } else {
5938 e_err(probe, "failed to finish FDIR re-initialization, "
5939 "ignored adding FDIR ATR filters\n");
5940 }
93c52dd0
AD		 5941}
5942
5943/**
5944 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5945 * @adapter - pointer to the device adapter structure
5946 *
5947 * This function serves two purposes. First it strobes the interrupt lines
5948 * in order to make certain interrupts are occuring. Secondly it sets the
5949 * bits needed to check for TX hangs. As a result we should immediately
5950 * determine if a hang has occured.
5951 */
5952static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5953{
cf8280ee 5954 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5955 u64 eics = 0;
5956 int i;
cf8280ee 5957
93c52dd0
AD		 5958 /* If we're down or resetting, just bail */
5959 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5960 test_bit(__IXGBE_RESETTING, &adapter->state))
5961 return;
22d5a71b 5962
93c52dd0
AD		 5963 /* Force detection of hung controller */
5964 if (netif_carrier_ok(adapter->netdev)) {
5965 for (i = 0; i < adapter->num_tx_queues; i++)
5966 set_check_for_tx_hang(adapter->tx_ring[i]);
5967 }
22d5a71b 5968
fe49f04a
AD		 5969 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5970 /*
5971 * for legacy and MSI interrupts don't set any bits
5972 * that are enabled for EIAM, because this operation
5973 * would set *both* EIMS and EICS for any bit in EIAM
5974 */
5975 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5976 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5977 } else {
5978 /* get one bit for every active tx/rx interrupt vector */
5979 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5980 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5981 if (qv->rxr_count || qv->txr_count)
5982 eics |= ((u64)1 << i);
5983 }
cf8280ee 5984 }
9a799d71 5985
93c52dd0 5986 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5987 ixgbe_irq_rearm_queues(adapter, eics);
5988
cf8280ee
JB		 5989}
5990
e8e26350 5991/**
93c52dd0
AD		 5992 * ixgbe_watchdog_update_link - update the link status
5993 * @adapter - pointer to the device adapter structure
5994 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5995 **/
93c52dd0 5996static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5997{
e8e26350 5998 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5999 u32 link_speed = adapter->link_speed;
6000 bool link_up = adapter->link_up;
c4cf55e5 6001 int i;
e8e26350 6002
93c52dd0
AD		 6003 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6004 return;
6005
6006 if (hw->mac.ops.check_link) {
6007 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6008 } else {
93c52dd0
AD		 6009 /* always assume link is up, if no check link function */
6010 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6011 link_up = true;
c4cf55e5 6012 }
93c52dd0
AD		 6013 if (link_up) {
6014 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6015 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6016 hw->mac.ops.fc_enable(hw, i);
6017 } else {
6018 hw->mac.ops.fc_enable(hw, 0);
6019 }
6020 }
6021
6022 if (link_up ||
6023 time_after(jiffies, (adapter->link_check_timeout +
6024 IXGBE_TRY_LINK_TIMEOUT))) {
6025 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6026 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6027 IXGBE_WRITE_FLUSH(hw);
6028 }
6029
6030 adapter->link_up = link_up;
6031 adapter->link_speed = link_speed;
e8e26350
PW		 6032}
6033
6034/**
93c52dd0
AD		 6035 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6036 * print link up message
6037 * @adapter - pointer to the device adapter structure
e8e26350 6038 **/
93c52dd0 6039static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6040{
93c52dd0 6041 struct net_device *netdev = adapter->netdev;
e8e26350 6042 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6043 u32 link_speed = adapter->link_speed;
6044 bool flow_rx, flow_tx;
e8e26350 6045
93c52dd0
AD		 6046 /* only continue if link was previously down */
6047 if (netif_carrier_ok(netdev))
a985b6c3 6048 return;
63d6e1d8 6049
93c52dd0 6050 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6051
93c52dd0
AD		 6052 switch (hw->mac.type) {
6053 case ixgbe_mac_82598EB: {
6054 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6055 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6056 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6057 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6058 }
6059 break;
6060 case ixgbe_mac_X540:
6061 case ixgbe_mac_82599EB: {
6062 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6063 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6064 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6065 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6066 }
6067 break;
6068 default:
6069 flow_tx = false;
6070 flow_rx = false;
6071 break;
e8e26350 6072 }
93c52dd0
AD		 6073 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6074 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6075 "10 Gbps" :
6076 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6077 "1 Gbps" :
6078 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6079 "100 Mbps" :
6080 "unknown speed"))),
6081 ((flow_rx && flow_tx) ? "RX/TX" :
6082 (flow_rx ? "RX" :
6083 (flow_tx ? "TX" : "None"))));
e8e26350 6084
93c52dd0
AD		 6085 netif_carrier_on(netdev);
6086#ifdef HAVE_IPLINK_VF_CONFIG
6087 ixgbe_check_vf_rate_limit(adapter);
6088#endif /* HAVE_IPLINK_VF_CONFIG */
e8e26350
PW		 6089}
6090
c4cf55e5 6091/**
93c52dd0
AD		 6092 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6093 * print link down message
6094 * @adapter - pointer to the adapter structure
c4cf55e5 6095 **/
93c52dd0 6096static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6097{
cf8280ee 6098 struct net_device *netdev = adapter->netdev;
c4cf55e5 6099 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6100
93c52dd0
AD		 6101 adapter->link_up = false;
6102 adapter->link_speed = 0;
cf8280ee 6103
93c52dd0
AD		 6104 /* only continue if link was up previously */
6105 if (!netif_carrier_ok(netdev))
6106 return;
264857b8 6107
93c52dd0
AD		 6108 /* poll for SFP+ cable when link is down */
6109 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6110 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6111
93c52dd0
AD		 6112 e_info(drv, "NIC Link is Down\n");
6113 netif_carrier_off(netdev);
6114}
e8e26350 6115
93c52dd0
AD		 6116/**
6117 * ixgbe_watchdog_flush_tx - flush queues on link down
6118 * @adapter - pointer to the device adapter structure
6119 **/
6120static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6121{
c4cf55e5 6122 int i;
93c52dd0 6123 int some_tx_pending = 0;
c4cf55e5 6124
93c52dd0 6125 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6126 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6127 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6128 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6129 some_tx_pending = 1;
6130 break;
6131 }
6132 }
6133
6134 if (some_tx_pending) {
6135 /* We've lost link, so the controller stops DMA,
6136 * but we've got queued Tx work that's never going
6137 * to get done, so reset controller to flush Tx.
6138 * (Do the reset outside of interrupt context).
6139 */
c83c6cbd 6140 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6141 }
c4cf55e5 6142 }
c4cf55e5
PWJ		 6143}
6144
a985b6c3
GR		 6145static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6146{
6147 u32 ssvpc;
6148
6149 /* Do not perform spoof check for 82598 */
6150 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6151 return;
6152
6153 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6154
6155 /*
6156 * ssvpc register is cleared on read, if zero then no
6157 * spoofed packets in the last interval.
6158 */
6159 if (!ssvpc)
6160 return;
6161
6162 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6163}
6164
93c52dd0
AD		 6165/**
6166 * ixgbe_watchdog_subtask - check and bring link up
6167 * @adapter - pointer to the device adapter structure
6168 **/
6169static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6170{
6171 /* if interface is down do nothing */
6172 if (test_bit(__IXGBE_DOWN, &adapter->state))
6173 return;
6174
6175 ixgbe_watchdog_update_link(adapter);
6176
6177 if (adapter->link_up)
6178 ixgbe_watchdog_link_is_up(adapter);
6179 else
6180 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6181
a985b6c3 6182 ixgbe_spoof_check(adapter);
9a799d71 6183 ixgbe_update_stats(adapter);
93c52dd0
AD		 6184
6185 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6186}
10eec955 6187
cf8280ee 6188/**
7086400d
AD		 6189 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6190 * @adapter - the ixgbe adapter structure
cf8280ee 6191 **/
7086400d 6192static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6193{
cf8280ee 6194 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6195 s32 err;
cf8280ee 6196
7086400d
AD		 6197 /* not searching for SFP so there is nothing to do here */
6198 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6199 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6200 return;
10eec955 6201
7086400d
AD		 6202 /* someone else is in init, wait until next service event */
6203 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6204 return;
cf8280ee 6205
7086400d
AD		 6206 err = hw->phy.ops.identify_sfp(hw);
6207 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6208 goto sfp_out;
264857b8 6209
7086400d
AD		 6210 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6211 /* If no cable is present, then we need to reset
6212 * the next time we find a good cable. */
6213 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6214 }
9a799d71 6215
7086400d
AD		 6216 /* exit on error */
6217 if (err)
6218 goto sfp_out;
e8e26350 6219
7086400d
AD		 6220 /* exit if reset not needed */
6221 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6222 goto sfp_out;
9a799d71 6223
7086400d 6224 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6225
7086400d
AD		 6226 /*
6227 * A module may be identified correctly, but the EEPROM may not have
6228 * support for that module. setup_sfp() will fail in that case, so
6229 * we should not allow that module to load.
6230 */
6231 if (hw->mac.type == ixgbe_mac_82598EB)
6232 err = hw->phy.ops.reset(hw);
6233 else
6234 err = hw->mac.ops.setup_sfp(hw);
6235
6236 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6237 goto sfp_out;
6238
6239 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6240 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6241
6242sfp_out:
6243 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6244
6245 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6246 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6247 e_dev_err("failed to initialize because an unsupported "
6248 "SFP+ module type was detected.\n");
6249 e_dev_err("Reload the driver after installing a "
6250 "supported module.\n");
6251 unregister_netdev(adapter->netdev);
bc59fcda 6252 }
7086400d 6253}
bc59fcda 6254
7086400d
AD		 6255/**
6256 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6257 * @adapter - the ixgbe adapter structure
6258 **/
6259static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6260{
6261 struct ixgbe_hw *hw = &adapter->hw;
6262 u32 autoneg;
6263 bool negotiation;
6264
6265 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6266 return;
6267
6268 /* someone else is in init, wait until next service event */
6269 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6270 return;
6271
6272 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6273
6274 autoneg = hw->phy.autoneg_advertised;
6275 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6276 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6277 hw->mac.autotry_restart = false;
6278 if (hw->mac.ops.setup_link)
6279 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6280
6281 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6282 adapter->link_check_timeout = jiffies;
6283 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6284}
6285
6286/**
6287 * ixgbe_service_timer - Timer Call-back
6288 * @data: pointer to adapter cast into an unsigned long
6289 **/
6290static void ixgbe_service_timer(unsigned long data)
6291{
6292 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6293 unsigned long next_event_offset;
6294
6295 /* poll faster when waiting for link */
6296 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6297 next_event_offset = HZ / 10;
6298 else
6299 next_event_offset = HZ * 2;
6300
6301 /* Reset the timer */
6302 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6303
6304 ixgbe_service_event_schedule(adapter);
6305}
6306
c83c6cbd
AD		 6307static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6308{
6309 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6310 return;
6311
6312 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6313
6314 /* If we're already down or resetting, just bail */
6315 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6316 test_bit(__IXGBE_RESETTING, &adapter->state))
6317 return;
6318
6319 ixgbe_dump(adapter);
6320 netdev_err(adapter->netdev, "Reset adapter\n");
6321 adapter->tx_timeout_count++;
6322
6323 ixgbe_reinit_locked(adapter);
6324}
6325
7086400d
AD		 6326/**
6327 * ixgbe_service_task - manages and runs subtasks
6328 * @work: pointer to work_struct containing our data
6329 **/
6330static void ixgbe_service_task(struct work_struct *work)
6331{
6332 struct ixgbe_adapter *adapter = container_of(work,
6333 struct ixgbe_adapter,
6334 service_task);
6335
c83c6cbd 6336 ixgbe_reset_subtask(adapter);
7086400d
AD		 6337 ixgbe_sfp_detection_subtask(adapter);
6338 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6339 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6340 ixgbe_watchdog_subtask(adapter);
d034acf1 6341 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6342 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6343
6344 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6345}
6346
897ab156
AD		 6347void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6348 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6349{
6350 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6351 u16 i = tx_ring->next_to_use;
9a799d71 6352
897ab156 6353 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6354
897ab156
AD		 6355 i++;
6356 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6357
897ab156
AD		 6358 /* set bits to identify this as an advanced context descriptor */
6359 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6360
897ab156
AD		 6361 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6362 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6363 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6364 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6365}
9a799d71 6366
897ab156
AD		 6367static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6368 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6369{
6370 int err;
6371 u32 vlan_macip_lens, type_tucmd;
6372 u32 mss_l4len_idx, l4len;
9a799d71 6373
897ab156
AD		 6374 if (!skb_is_gso(skb))
6375 return 0;
9a799d71 6376
897ab156
AD		 6377 if (skb_header_cloned(skb)) {
6378 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6379 if (err)
6380 return err;
9a799d71 6381 }
9a799d71 6382
897ab156
AD		 6383 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6384 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6385
6386 if (protocol == __constant_htons(ETH_P_IP)) {
6387 struct iphdr *iph = ip_hdr(skb);
6388 iph->tot_len = 0;
6389 iph->check = 0;
6390 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6391 iph->daddr, 0,
6392 IPPROTO_TCP,
6393 0);
6394 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6395 } else if (skb_is_gso_v6(skb)) {
6396 ipv6_hdr(skb)->payload_len = 0;
6397 tcp_hdr(skb)->check =
6398 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6399 &ipv6_hdr(skb)->daddr,
6400 0, IPPROTO_TCP, 0);
6401 }
6402
6403 l4len = tcp_hdrlen(skb);
6404 *hdr_len = skb_transport_offset(skb) + l4len;
6405
6406 /* mss_l4len_id: use 1 as index for TSO */
6407 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6408 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6409 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6410
6411 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6412 vlan_macip_lens = skb_network_header_len(skb);
6413 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6414 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6415
6416 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6417 mss_l4len_idx);
6418
6419 return 1;
6420}
6421
6422static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6423 struct sk_buff *skb, u32 tx_flags,
6424 __be16 protocol)
7ca647bd 6425{
897ab156
AD		 6426 u32 vlan_macip_lens = 0;
6427 u32 mss_l4len_idx = 0;
6428 u32 type_tucmd = 0;
7ca647bd 6429
897ab156
AD		 6430 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6431 if (!(tx_flags & IXGBE_TX_FLAGS_VLAN))
6432 return false;
6433 } else {
6434 u8 l4_hdr = 0;
6435 switch (protocol) {
6436 case __constant_htons(ETH_P_IP):
6437 vlan_macip_lens |= skb_network_header_len(skb);
6438 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6439 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6440 break;
897ab156
AD		 6441 case __constant_htons(ETH_P_IPV6):
6442 vlan_macip_lens |= skb_network_header_len(skb);
6443 l4_hdr = ipv6_hdr(skb)->nexthdr;
6444 break;
6445 default:
6446 if (unlikely(net_ratelimit())) {
6447 dev_warn(tx_ring->dev,
6448 "partial checksum but proto=%x!\n",
6449 skb->protocol);
6450 }
7ca647bd
JP		 6451 break;
6452 }
897ab156
AD		 6453
6454 switch (l4_hdr) {
7ca647bd 6455 case IPPROTO_TCP:
897ab156
AD		 6456 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6457 mss_l4len_idx = tcp_hdrlen(skb) <<
6458 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6459 break;
6460 case IPPROTO_SCTP:
897ab156
AD		 6461 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6462 mss_l4len_idx = sizeof(struct sctphdr) <<
6463 IXGBE_ADVTXD_L4LEN_SHIFT;
6464 break;
6465 case IPPROTO_UDP:
6466 mss_l4len_idx = sizeof(struct udphdr) <<
6467 IXGBE_ADVTXD_L4LEN_SHIFT;
6468 break;
6469 default:
6470 if (unlikely(net_ratelimit())) {
6471 dev_warn(tx_ring->dev,
6472 "partial checksum but l4 proto=%x!\n",
6473 skb->protocol);
6474 }
7ca647bd
JP		 6475 break;
6476 }
7ca647bd
JP		 6477 }
6478
897ab156
AD		 6479 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6480 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6481
897ab156
AD		 6482 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6483 type_tucmd, mss_l4len_idx);
9a799d71 6484
897ab156 6485 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6486}
6487
6488static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6489 struct ixgbe_ring *tx_ring,
6490 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6491 unsigned int first, const u8 hdr_len)
9a799d71 6492{
b6ec895e 6493 struct device *dev = tx_ring->dev;
9a799d71 6494 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6495 unsigned int len;
6496 unsigned int total = skb->len;
63544e9c 6497 unsigned int offset = 0, size, count = 0;
9a799d71
AK		 6498 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6499 unsigned int f;
8ad494b0
AD		 6500 unsigned int bytecount = skb->len;
6501 u16 gso_segs = 1;
63544e9c 6502 u16 i;
9a799d71
AK		 6503
6504 i = tx_ring->next_to_use;
6505
eacd73f7
YZ		 6506 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6507 /* excluding fcoe_crc_eof for FCoE */
6508 total -= sizeof(struct fcoe_crc_eof);
6509
6510 len = min(skb_headlen(skb), total);
9a799d71
AK		 6511 while (len) {
6512 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6513 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6514
6515 tx_buffer_info->length = size;
e5a43549 6516 tx_buffer_info->mapped_as_page = false;
b6ec895e 6517 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6518 skb->data + offset,
1b507730 6519 size, DMA_TO_DEVICE);
b6ec895e 6520 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6521 goto dma_error;
9a799d71
AK		 6522 tx_buffer_info->time_stamp = jiffies;
6523 tx_buffer_info->next_to_watch = i;
6524
6525 len -= size;
eacd73f7 6526 total -= size;
9a799d71
AK		 6527 offset += size;
6528 count++;
44df32c5
AD		 6529
6530 if (len) {
6531 i++;
6532 if (i == tx_ring->count)
6533 i = 0;
6534 }
9a799d71
AK		 6535 }
6536
6537 for (f = 0; f < nr_frags; f++) {
6538 struct skb_frag_struct *frag;
6539
6540 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6541 len = min((unsigned int)frag->size, total);
e5a43549 6542 offset = frag->page_offset;
9a799d71
AK		 6543
6544 while (len) {
44df32c5
AD		 6545 i++;
6546 if (i == tx_ring->count)
6547 i = 0;
6548
9a799d71
AK		 6549 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6550 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6551
6552 tx_buffer_info->length = size;
b6ec895e 6553 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6554 frag->page,
6555 offset, size,
1b507730 6556 DMA_TO_DEVICE);
e5a43549 6557 tx_buffer_info->mapped_as_page = true;
b6ec895e 6558 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6559 goto dma_error;
9a799d71
AK		 6560 tx_buffer_info->time_stamp = jiffies;
6561 tx_buffer_info->next_to_watch = i;
6562
6563 len -= size;
eacd73f7 6564 total -= size;
9a799d71
AK		 6565 offset += size;
6566 count++;
9a799d71 6567 }
eacd73f7
YZ		 6568 if (total == 0)
6569 break;
9a799d71 6570 }
44df32c5 6571
8ad494b0
AD		 6572 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6573 gso_segs = skb_shinfo(skb)->gso_segs;
6574#ifdef IXGBE_FCOE
6575 /* adjust for FCoE Sequence Offload */
6576 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6577 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6578 skb_shinfo(skb)->gso_size);
6579#endif /* IXGBE_FCOE */
6580 bytecount += (gso_segs - 1) * hdr_len;
6581
6582 /* multiply data chunks by size of headers */
6583 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6584 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6585 tx_ring->tx_buffer_info[i].skb = skb;
6586 tx_ring->tx_buffer_info[first].next_to_watch = i;
6587
e5a43549
AD		 6588 return count;
6589
6590dma_error:
849c4542 6591 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6592
6593 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6594 tx_buffer_info->dma = 0;
6595 tx_buffer_info->time_stamp = 0;
6596 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6597 if (count)
6598 count--;
e5a43549
AD		 6599
6600 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6601 while (count--) {
e8e9f696 6602 if (i == 0)
e5a43549 6603 i += tx_ring->count;
c1fa347f 6604 i--;
e5a43549 6605 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6606 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6607 }
6608
e44d38e1 6609 return 0;
9a799d71
AK		 6610}
6611
84ea2591 6612static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6613 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6614{
6615 union ixgbe_adv_tx_desc *tx_desc = NULL;
6616 struct ixgbe_tx_buffer *tx_buffer_info;
6617 u32 olinfo_status = 0, cmd_type_len = 0;
6618 unsigned int i;
6619 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6620
6621 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6622
6623 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6624
6625 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6626 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6627
6628 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6629 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6630
6631 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6632 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6633
4eeae6fd
PW		 6634 /* use index 1 context for tso */
6635 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6636 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6637 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6638 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6639
6640 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6641 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6642 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6643
eacd73f7
YZ		 6644 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6645 olinfo_status |= IXGBE_ADVTXD_CC;
6646 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6647 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6648 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6649 }
6650
9a799d71
AK		 6651 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6652
6653 i = tx_ring->next_to_use;
6654 while (count--) {
6655 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6656 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6657 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6658 tx_desc->read.cmd_type_len =
e8e9f696 6659 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6660 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6661 i++;
6662 if (i == tx_ring->count)
6663 i = 0;
6664 }
6665
6666 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6667
6668 /*
6669 * Force memory writes to complete before letting h/w
6670 * know there are new descriptors to fetch. (Only
6671 * applicable for weak-ordered memory model archs,
6672 * such as IA-64).
6673 */
6674 wmb();
6675
6676 tx_ring->next_to_use = i;
84ea2591 6677 writel(i, tx_ring->tail);
9a799d71
AK		 6678}
6679
69830529
AD		 6680static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6681 u32 tx_flags, __be16 protocol)
6682{
6683 struct ixgbe_q_vector *q_vector = ring->q_vector;
6684 union ixgbe_atr_hash_dword input = { .dword = 0 };
6685 union ixgbe_atr_hash_dword common = { .dword = 0 };
6686 union {
6687 unsigned char *network;
6688 struct iphdr *ipv4;
6689 struct ipv6hdr *ipv6;
6690 } hdr;
ee9e0f0b 6691 struct tcphdr *th;
905e4a41 6692 __be16 vlan_id;
c4cf55e5 6693
69830529
AD		 6694 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6695 if (!q_vector)
6696 return;
6697
6698 /* do nothing if sampling is disabled */
6699 if (!ring->atr_sample_rate)
d3ead241 6700 return;
c4cf55e5 6701
69830529 6702 ring->atr_count++;
c4cf55e5 6703
69830529
AD		 6704 /* snag network header to get L4 type and address */
6705 hdr.network = skb_network_header(skb);
6706
6707 /* Currently only IPv4/IPv6 with TCP is supported */
6708 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6709 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6710 (protocol != __constant_htons(ETH_P_IP) ||
6711 hdr.ipv4->protocol != IPPROTO_TCP))
6712 return;
ee9e0f0b
AD		 6713
6714 th = tcp_hdr(skb);
c4cf55e5 6715
69830529
AD		 6716 /* skip this packet since the socket is closing */
6717 if (th->fin)
6718 return;
6719
6720 /* sample on all syn packets or once every atr sample count */
6721 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6722 return;
6723
6724 /* reset sample count */
6725 ring->atr_count = 0;
6726
6727 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6728
6729 /*
6730 * src and dst are inverted, think how the receiver sees them
6731 *
6732 * The input is broken into two sections, a non-compressed section
6733 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6734 * is XORed together and stored in the compressed dword.
6735 */
6736 input.formatted.vlan_id = vlan_id;
6737
6738 /*
6739 * since src port and flex bytes occupy the same word XOR them together
6740 * and write the value to source port portion of compressed dword
6741 */
6742 if (vlan_id)
6743 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6744 else
6745 common.port.src ^= th->dest ^ protocol;
6746 common.port.dst ^= th->source;
6747
6748 if (protocol == __constant_htons(ETH_P_IP)) {
6749 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6750 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6751 } else {
6752 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6753 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6754 hdr.ipv6->saddr.s6_addr32[1] ^
6755 hdr.ipv6->saddr.s6_addr32[2] ^
6756 hdr.ipv6->saddr.s6_addr32[3] ^
6757 hdr.ipv6->daddr.s6_addr32[0] ^
6758 hdr.ipv6->daddr.s6_addr32[1] ^
6759 hdr.ipv6->daddr.s6_addr32[2] ^
6760 hdr.ipv6->daddr.s6_addr32[3];
6761 }
c4cf55e5
PWJ		 6762
6763 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6764 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6765 input, common, ring->queue_index);
c4cf55e5
PWJ		 6766}
6767
63544e9c 6768static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6769{
fc77dc3c 6770 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6771 /* Herbert's original patch had:
6772 * smp_mb__after_netif_stop_queue();
6773 * but since that doesn't exist yet, just open code it. */
6774 smp_mb();
6775
6776 /* We need to check again in a case another CPU has just
6777 * made room available. */
7d4987de 6778 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6779 return -EBUSY;
6780
6781 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6782 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6783 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6784 return 0;
6785}
6786
63544e9c 6787static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6788{
7d4987de 6789 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6790 return 0;
fc77dc3c 6791 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6792}
6793
09a3b1f8
SH		 6794static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6795{
6796 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6797 int txq = smp_processor_id();
56075a98 6798#ifdef IXGBE_FCOE
5e09a105
HZ		 6799 __be16 protocol;
6800
6801 protocol = vlan_get_protocol(skb);
6802
e5b64635
JF		 6803 if (((protocol == htons(ETH_P_FCOE)) ||
6804 (protocol == htons(ETH_P_FIP))) &&
6805 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6806 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6807 txq += adapter->ring_feature[RING_F_FCOE].mask;
6808 return txq;
56075a98
JF		 6809 }
6810#endif
6811
fdd3d631
KK		 6812 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6813 while (unlikely(txq >= dev->real_num_tx_queues))
6814 txq -= dev->real_num_tx_queues;
5f715823 6815 return txq;
fdd3d631 6816 }
c4cf55e5 6817
09a3b1f8
SH		 6818 return skb_tx_hash(dev, skb);
6819}
6820
fc77dc3c 6821netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6822 struct ixgbe_adapter *adapter,
6823 struct ixgbe_ring *tx_ring)
9a799d71 6824{
5f715823 6825 int tso;
a535c30e
AD		 6826 u32 tx_flags = 0;
6827#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6828 unsigned short f;
6829#endif
63544e9c 6830 u16 first;
a535c30e 6831 u16 count = TXD_USE_COUNT(skb_headlen(skb));
5e09a105 6832 __be16 protocol;
63544e9c 6833 u8 hdr_len = 0;
5e09a105 6834
a535c30e
AD		 6835 /*
6836 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6837 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6838 * + 2 desc gap to keep tail from touching head,
6839 * + 1 desc for context descriptor,
6840 * otherwise try next time
6841 */
6842#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6843 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6844 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6845#else
6846 count += skb_shinfo(skb)->nr_frags;
6847#endif
6848 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6849 tx_ring->tx_stats.tx_busy++;
6850 return NETDEV_TX_BUSY;
6851 }
6852
5e09a105 6853 protocol = vlan_get_protocol(skb);
9f8cdf4f 6854
eab6d18d 6855 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6856 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6857 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6858 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
e5b64635 6859 tx_flags |= tx_ring->dcb_tc << 13;
2f90b865
AD		 6860 }
6861 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6862 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6863 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6864 skb->priority != TC_PRIO_CONTROL) {
e5b64635 6865 tx_flags |= tx_ring->dcb_tc << 13;
2ea186ae
JF		 6866 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6867 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6868 }
eacd73f7 6869
09ad1cc0 6870#ifdef IXGBE_FCOE
56075a98
JF		 6871 /* for FCoE with DCB, we force the priority to what
6872 * was specified by the switch */
6873 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
e5b64635
JF		 6874 (protocol == htons(ETH_P_FCOE)))
6875 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6876
a535c30e
AD		 6877#endif
6878 /* record the location of the first descriptor for this packet */
9a799d71 6879 first = tx_ring->next_to_use;
a535c30e 6880
eacd73f7
YZ		 6881 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6882#ifdef IXGBE_FCOE
6883 /* setup tx offload for FCoE */
897ab156
AD		 6884 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6885 if (tso < 0)
6886 goto out_drop;
6887 else if (tso)
eacd73f7
YZ		 6888 tx_flags |= IXGBE_TX_FLAGS_FSO;
6889#endif /* IXGBE_FCOE */
6890 } else {
5e09a105 6891 if (protocol == htons(ETH_P_IP))
eacd73f7 6892 tx_flags |= IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6893 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6894 if (tso < 0)
6895 goto out_drop;
6896 else if (tso)
eacd73f7 6897 tx_flags |= IXGBE_TX_FLAGS_TSO;
897ab156 6898 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
eacd73f7
YZ		 6899 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6900 }
9a799d71 6901
8ad494b0 6902 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6903 if (count) {
c4cf55e5 6904 /* add the ATR filter if ATR is on */
69830529
AD		 6905 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6906 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
84ea2591 6907 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6908 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6909
44df32c5 6910 } else {
44df32c5
AD		 6911 tx_ring->tx_buffer_info[first].time_stamp = 0;
6912 tx_ring->next_to_use = first;
897ab156 6913 goto out_drop;
44df32c5 6914 }
9a799d71
AK		 6915
6916 return NETDEV_TX_OK;
897ab156
AD		 6917
6918out_drop:
6919 dev_kfree_skb_any(skb);
6920 return NETDEV_TX_OK;
9a799d71
AK		 6921}
6922
84418e3b
AD		 6923static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6924{
6925 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6926 struct ixgbe_ring *tx_ring;
6927
6928 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6929 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6930}
6931
9a799d71
AK		 6932/**
6933 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6934 * @netdev: network interface device structure
6935 * @p: pointer to an address structure
6936 *
6937 * Returns 0 on success, negative on failure
6938 **/
6939static int ixgbe_set_mac(struct net_device *netdev, void *p)
6940{
6941 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6942 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6943 struct sockaddr *addr = p;
6944
6945 if (!is_valid_ether_addr(addr->sa_data))
6946 return -EADDRNOTAVAIL;
6947
6948 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6949 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6950
1cdd1ec8
GR		 6951 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6952 IXGBE_RAH_AV);
9a799d71
AK		 6953
6954 return 0;
6955}
6956
6b73e10d
BH		 6957static int
6958ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6959{
6960 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6961 struct ixgbe_hw *hw = &adapter->hw;
6962 u16 value;
6963 int rc;
6964
6965 if (prtad != hw->phy.mdio.prtad)
6966 return -EINVAL;
6967 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6968 if (!rc)
6969 rc = value;
6970 return rc;
6971}
6972
6973static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6974 u16 addr, u16 value)
6975{
6976 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6977 struct ixgbe_hw *hw = &adapter->hw;
6978
6979 if (prtad != hw->phy.mdio.prtad)
6980 return -EINVAL;
6981 return hw->phy.ops.write_reg(hw, addr, devad, value);
6982}
6983
6984static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6985{
6986 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6987
6988 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6989}
6990
0365e6e4
PW		 6991/**
6992 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6993 * netdev->dev_addrs
0365e6e4
PW		 6994 * @netdev: network interface device structure
6995 *
6996 * Returns non-zero on failure
6997 **/
6998static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6999{
7000 int err = 0;
7001 struct ixgbe_adapter *adapter = netdev_priv(dev);
7002 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7003
7004 if (is_valid_ether_addr(mac->san_addr)) {
7005 rtnl_lock();
7006 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7007 rtnl_unlock();
7008 }
7009 return err;
7010}
7011
7012/**
7013 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7014 * netdev->dev_addrs
0365e6e4
PW		 7015 * @netdev: network interface device structure
7016 *
7017 * Returns non-zero on failure
7018 **/
7019static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7020{
7021 int err = 0;
7022 struct ixgbe_adapter *adapter = netdev_priv(dev);
7023 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7024
7025 if (is_valid_ether_addr(mac->san_addr)) {
7026 rtnl_lock();
7027 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7028 rtnl_unlock();
7029 }
7030 return err;
7031}
7032
9a799d71
AK		 7033#ifdef CONFIG_NET_POLL_CONTROLLER
7034/*
7035 * Polling 'interrupt' - used by things like netconsole to send skbs
7036 * without having to re-enable interrupts. It's not called while
7037 * the interrupt routine is executing.
7038 */
7039static void ixgbe_netpoll(struct net_device *netdev)
7040{
7041 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7042 int i;
9a799d71 7043
1a647bd2
AD		 7044 /* if interface is down do nothing */
7045 if (test_bit(__IXGBE_DOWN, &adapter->state))
7046 return;
7047
9a799d71 7048 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7049 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7050 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7051 for (i = 0; i < num_q_vectors; i++) {
7052 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7053 ixgbe_msix_clean_many(0, q_vector);
7054 }
7055 } else {
7056 ixgbe_intr(adapter->pdev->irq, netdev);
7057 }
9a799d71 7058 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7059}
7060#endif
7061
de1036b1
ED		 7062static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7063 struct rtnl_link_stats64 *stats)
7064{
7065 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7066 int i;
7067
1a51502b 7068 rcu_read_lock();
de1036b1 7069 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7070 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7071 u64 bytes, packets;
7072 unsigned int start;
7073
1a51502b
ED		 7074 if (ring) {
7075 do {
7076 start = u64_stats_fetch_begin_bh(&ring->syncp);
7077 packets = ring->stats.packets;
7078 bytes = ring->stats.bytes;
7079 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7080 stats->rx_packets += packets;
7081 stats->rx_bytes += bytes;
7082 }
de1036b1 7083 }
1ac9ad13
ED		 7084
7085 for (i = 0; i < adapter->num_tx_queues; i++) {
7086 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7087 u64 bytes, packets;
7088 unsigned int start;
7089
7090 if (ring) {
7091 do {
7092 start = u64_stats_fetch_begin_bh(&ring->syncp);
7093 packets = ring->stats.packets;
7094 bytes = ring->stats.bytes;
7095 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7096 stats->tx_packets += packets;
7097 stats->tx_bytes += bytes;
7098 }
7099 }
1a51502b 7100 rcu_read_unlock();
de1036b1
ED		 7101 /* following stats updated by ixgbe_watchdog_task() */
7102 stats->multicast = netdev->stats.multicast;
7103 stats->rx_errors = netdev->stats.rx_errors;
7104 stats->rx_length_errors = netdev->stats.rx_length_errors;
7105 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7106 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7107 return stats;
7108}
7109
8b1c0b24
JF		 7110/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7111 * #adapter: pointer to ixgbe_adapter
7112 * @tc: number of traffic classes currently enabled
7113 *
7114 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7115 * 802.1Q priority maps to a packet buffer that exists.
7116 */
7117static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7118{
7119 struct ixgbe_hw *hw = &adapter->hw;
7120 u32 reg, rsave;
7121 int i;
7122
7123 /* 82598 have a static priority to TC mapping that can not
7124 * be changed so no validation is needed.
7125 */
7126 if (hw->mac.type == ixgbe_mac_82598EB)
7127 return;
7128
7129 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7130 rsave = reg;
7131
7132 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7133 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7134
7135 /* If up2tc is out of bounds default to zero */
7136 if (up2tc > tc)
7137 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7138 }
7139
7140 if (reg != rsave)
7141 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7142
7143 return;
7144}
7145
7146
7147/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7148 * classes.
7149 *
7150 * @netdev: net device to configure
7151 * @tc: number of traffic classes to enable
7152 */
7153int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7154{
8b1c0b24
JF		 7155 struct ixgbe_adapter *adapter = netdev_priv(dev);
7156 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24
JF		 7157
7158 /* If DCB is anabled do not remove traffic classes, multiple
7159 * traffic classes are required to implement DCB
7160 */
7161 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7162 return 0;
7163
7164 /* Hardware supports up to 8 traffic classes */
7165 if (tc > MAX_TRAFFIC_CLASS ||
7166 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7167 return -EINVAL;
7168
7169 /* Hardware has to reinitialize queues and interrupts to
7170 * match packet buffer alignment. Unfortunantly, the
7171 * hardware is not flexible enough to do this dynamically.
7172 */
7173 if (netif_running(dev))
7174 ixgbe_close(dev);
7175 ixgbe_clear_interrupt_scheme(adapter);
7176
7177 if (tc)
7178 netdev_set_num_tc(dev, tc);
7179 else
7180 netdev_reset_tc(dev);
7181
8b1c0b24
JF		 7182 ixgbe_init_interrupt_scheme(adapter);
7183 ixgbe_validate_rtr(adapter, tc);
7184 if (netif_running(dev))
7185 ixgbe_open(dev);
7186
7187 return 0;
7188}
de1036b1 7189
0edc3527 7190static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7191 .ndo_open = ixgbe_open,
0edc3527 7192 .ndo_stop = ixgbe_close,
00829823 7193 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7194 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7195 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7196 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7197 .ndo_validate_addr = eth_validate_addr,
7198 .ndo_set_mac_address = ixgbe_set_mac,
7199 .ndo_change_mtu = ixgbe_change_mtu,
7200 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7201 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7202 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7203 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7204 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7205 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7206 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7207 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7208 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7209 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7210#ifdef CONFIG_NET_POLL_CONTROLLER
7211 .ndo_poll_controller = ixgbe_netpoll,
7212#endif
332d4a7d
YZ		 7213#ifdef IXGBE_FCOE
7214 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7215 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7216 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7217 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7218 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7219 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7220#endif /* IXGBE_FCOE */
0edc3527
SH		 7221};
7222
1cdd1ec8
GR		 7223static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7224 const struct ixgbe_info *ii)
7225{
7226#ifdef CONFIG_PCI_IOV
7227 struct ixgbe_hw *hw = &adapter->hw;
7228 int err;
a1cbb15c
GR		 7229 int num_vf_macvlans, i;
7230 struct vf_macvlans *mv_list;
1cdd1ec8 7231
3377eba7 7232 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7233 return;
7234
7235 /* The 82599 supports up to 64 VFs per physical function
7236 * but this implementation limits allocation to 63 so that
7237 * basic networking resources are still available to the
7238 * physical function
7239 */
7240 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7241 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7242 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7243 if (err) {
396e799c 7244 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7245 goto err_novfs;
7246 }
a1cbb15c
GR		 7247
7248 num_vf_macvlans = hw->mac.num_rar_entries -
7249 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7250
7251 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7252 sizeof(struct vf_macvlans),
7253 GFP_KERNEL);
7254 if (mv_list) {
7255 /* Initialize list of VF macvlans */
7256 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7257 for (i = 0; i < num_vf_macvlans; i++) {
7258 mv_list->vf = -1;
7259 mv_list->free = true;
7260 mv_list->rar_entry = hw->mac.num_rar_entries -
7261 (i + adapter->num_vfs + 1);
7262 list_add(&mv_list->l, &adapter->vf_mvs.l);
7263 mv_list++;
7264 }
7265 }
7266
1cdd1ec8
GR		 7267 /* If call to enable VFs succeeded then allocate memory
7268 * for per VF control structures.
7269 */
7270 adapter->vfinfo =
7271 kcalloc(adapter->num_vfs,
7272 sizeof(struct vf_data_storage), GFP_KERNEL);
7273 if (adapter->vfinfo) {
7274 /* Now that we're sure SR-IOV is enabled
7275 * and memory allocated set up the mailbox parameters
7276 */
7277 ixgbe_init_mbx_params_pf(hw);
7278 memcpy(&hw->mbx.ops, ii->mbx_ops,
7279 sizeof(hw->mbx.ops));
7280
7281 /* Disable RSC when in SR-IOV mode */
7282 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7283 IXGBE_FLAG2_RSC_ENABLED);
7284 return;
7285 }
7286
7287 /* Oh oh */
396e799c
ET		 7288 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7289 "SRIOV disabled\n");
1cdd1ec8
GR		 7290 pci_disable_sriov(adapter->pdev);
7291
7292err_novfs:
7293 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7294 adapter->num_vfs = 0;
7295#endif /* CONFIG_PCI_IOV */
7296}
7297
9a799d71
AK		 7298/**
7299 * ixgbe_probe - Device Initialization Routine
7300 * @pdev: PCI device information struct
7301 * @ent: entry in ixgbe_pci_tbl
7302 *
7303 * Returns 0 on success, negative on failure
7304 *
7305 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7306 * The OS initialization, configuring of the adapter private structure,
7307 * and a hardware reset occur.
7308 **/
7309static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7310 const struct pci_device_id *ent)
9a799d71
AK		 7311{
7312 struct net_device *netdev;
7313 struct ixgbe_adapter *adapter = NULL;
7314 struct ixgbe_hw *hw;
7315 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7316 static int cards_found;
7317 int i, err, pci_using_dac;
289700db 7318 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7319 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7320#ifdef IXGBE_FCOE
7321 u16 device_caps;
7322#endif
289700db 7323 u32 eec;
9a799d71 7324
bded64a7
AG		 7325 /* Catch broken hardware that put the wrong VF device ID in
7326 * the PCIe SR-IOV capability.
7327 */
7328 if (pdev->is_virtfn) {
7329 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7330 pci_name(pdev), pdev->vendor, pdev->device);
7331 return -EINVAL;
7332 }
7333
9ce77666 7334 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7335 if (err)
7336 return err;
7337
1b507730
NN		 7338 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7339 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7340 pci_using_dac = 1;
7341 } else {
1b507730 7342 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7343 if (err) {
1b507730
NN		 7344 err = dma_set_coherent_mask(&pdev->dev,
7345 DMA_BIT_MASK(32));
9a799d71 7346 if (err) {
b8bc0421
DC		 7347 dev_err(&pdev->dev,
7348 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7349 goto err_dma;
7350 }
7351 }
7352 pci_using_dac = 0;
7353 }
7354
9ce77666 7355 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7356 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7357 if (err) {
b8bc0421
DC		 7358 dev_err(&pdev->dev,
7359 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7360 goto err_pci_reg;
7361 }
7362
19d5afd4 7363 pci_enable_pcie_error_reporting(pdev);
6fabd715 7364
9a799d71 7365 pci_set_master(pdev);
fb3b27bc 7366 pci_save_state(pdev);
9a799d71 7367
e901acd6
JF		 7368#ifdef CONFIG_IXGBE_DCB
7369 indices *= MAX_TRAFFIC_CLASS;
7370#endif
7371
c85a2618
JF		 7372 if (ii->mac == ixgbe_mac_82598EB)
7373 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7374 else
7375 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7376
e901acd6 7377#ifdef IXGBE_FCOE
c85a2618
JF		 7378 indices += min_t(unsigned int, num_possible_cpus(),
7379 IXGBE_MAX_FCOE_INDICES);
7380#endif
c85a2618 7381 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7382 if (!netdev) {
7383 err = -ENOMEM;
7384 goto err_alloc_etherdev;
7385 }
7386
9a799d71
AK		 7387 SET_NETDEV_DEV(netdev, &pdev->dev);
7388
9a799d71 7389 adapter = netdev_priv(netdev);
c60fbb00 7390 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7391
7392 adapter->netdev = netdev;
7393 adapter->pdev = pdev;
7394 hw = &adapter->hw;
7395 hw->back = adapter;
7396 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7397
05857980 7398 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7399 pci_resource_len(pdev, 0));
9a799d71
AK		 7400 if (!hw->hw_addr) {
7401 err = -EIO;
7402 goto err_ioremap;
7403 }
7404
7405 for (i = 1; i <= 5; i++) {
7406 if (pci_resource_len(pdev, i) == 0)
7407 continue;
7408 }
7409
0edc3527 7410 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7411 ixgbe_set_ethtool_ops(netdev);
9a799d71 7412 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7413 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7414
9a799d71
AK		 7415 adapter->bd_number = cards_found;
7416
9a799d71
AK		 7417 /* Setup hw api */
7418 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7419 hw->mac.type = ii->mac;
9a799d71 7420
c44ade9e
JB		 7421 /* EEPROM */
7422 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7423 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7424 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7425 if (!(eec & (1 << 8)))
7426 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7427
7428 /* PHY */
7429 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7430 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7431 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7432 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7433 hw->phy.mdio.mmds = 0;
7434 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7435 hw->phy.mdio.dev = netdev;
7436 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7437 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7438
8ca783ab 7439 ii->get_invariants(hw);
9a799d71
AK		 7440
7441 /* setup the private structure */
7442 err = ixgbe_sw_init(adapter);
7443 if (err)
7444 goto err_sw_init;
7445
e86bff0e 7446 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7447 switch (adapter->hw.mac.type) {
7448 case ixgbe_mac_82599EB:
7449 case ixgbe_mac_X540:
e86bff0e 7450 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7451 break;
7452 default:
7453 break;
7454 }
e86bff0e 7455
bf069c97
DS		 7456 /*
7457 * If there is a fan on this device and it has failed log the
7458 * failure.
7459 */
7460 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7461 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7462 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7463 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7464 }
7465
c44ade9e 7466 /* reset_hw fills in the perm_addr as well */
119fc60a 7467 hw->phy.reset_if_overtemp = true;
c44ade9e 7468 err = hw->mac.ops.reset_hw(hw);
119fc60a 7469 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7470 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7471 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7472 err = 0;
7473 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7474 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7475 "module type was detected.\n");
7476 e_dev_err("Reload the driver after installing a supported "
7477 "module.\n");
04f165ef
PW		 7478 goto err_sw_init;
7479 } else if (err) {
849c4542 7480 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7481 goto err_sw_init;
7482 }
7483
1cdd1ec8
GR		 7484 ixgbe_probe_vf(adapter, ii);
7485
396e799c 7486 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7487 NETIF_F_IP_CSUM |
7488 NETIF_F_HW_VLAN_TX |
7489 NETIF_F_HW_VLAN_RX |
7490 NETIF_F_HW_VLAN_FILTER;
9a799d71 7491
e9990a9c 7492 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7493 netdev->features |= NETIF_F_TSO;
9a799d71 7494 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7495 netdev->features |= NETIF_F_GRO;
67a74ee2 7496 netdev->features |= NETIF_F_RXHASH;
ad31c402 7497
58be7666
DS		 7498 switch (adapter->hw.mac.type) {
7499 case ixgbe_mac_82599EB:
7500 case ixgbe_mac_X540:
45a5ead0 7501 netdev->features |= NETIF_F_SCTP_CSUM;
58be7666
DS		 7502 break;
7503 default:
7504 break;
7505 }
45a5ead0 7506
ad31c402
JK		 7507 netdev->vlan_features |= NETIF_F_TSO;
7508 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7509 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7510 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7511 netdev->vlan_features |= NETIF_F_SG;
7512
1cdd1ec8
GR		 7513 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7514 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7515 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7516
7a6b6f51 7517#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7518 netdev->dcbnl_ops = &dcbnl_ops;
7519#endif
7520
eacd73f7 7521#ifdef IXGBE_FCOE
0d551589 7522 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7523 if (hw->mac.ops.get_device_caps) {
7524 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7525 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7526 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7527 }
7528 }
5e09d7f6
YZ		 7529 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7530 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7531 netdev->vlan_features |= NETIF_F_FSO;
7532 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7533 }
eacd73f7 7534#endif /* IXGBE_FCOE */
7b872a55 7535 if (pci_using_dac) {
9a799d71 7536 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7537 netdev->vlan_features |= NETIF_F_HIGHDMA;
7538 }
9a799d71 7539
0c19d6af 7540 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7541 netdev->features |= NETIF_F_LRO;
7542
9a799d71 7543 /* make sure the EEPROM is good */
c44ade9e 7544 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7545 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7546 err = -EIO;
7547 goto err_eeprom;
7548 }
7549
7550 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7551 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7552
c44ade9e 7553 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7554 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7555 err = -EIO;
7556 goto err_eeprom;
7557 }
7558
c6ecf39a
DS		 7559 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7560 if (hw->mac.ops.disable_tx_laser &&
7561 ((hw->phy.multispeed_fiber) ||
9f911707 7562 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7563 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7564 hw->mac.ops.disable_tx_laser(hw);
7565
7086400d
AD		 7566 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7567 (unsigned long) adapter);
9a799d71 7568
7086400d
AD		 7569 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7570 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7571
021230d4
AV		 7572 err = ixgbe_init_interrupt_scheme(adapter);
7573 if (err)
7574 goto err_sw_init;
9a799d71 7575
67a74ee2
ET		 7576 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7577 netdev->features &= ~NETIF_F_RXHASH;
7578
e8e26350 7579 switch (pdev->device) {
0b077fea
DS		 7580 case IXGBE_DEV_ID_82599_SFP:
7581 /* Only this subdevice supports WOL */
7582 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7583 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7584 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7585 break;
50d6c681
AD		 7586 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7587 /* All except this subdevice support WOL */
0b077fea
DS		 7588 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7589 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7590 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7591 break;
e8e26350 7592 case IXGBE_DEV_ID_82599_KX4:
495dce12 7593 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7594 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7595 break;
7596 default:
7597 adapter->wol = 0;
7598 break;
7599 }
e8e26350
PW		 7600 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7601
04f165ef
PW		 7602 /* pick up the PCI bus settings for reporting later */
7603 hw->mac.ops.get_bus_info(hw);
7604
9a799d71 7605 /* print bus type/speed/width info */
849c4542 7606 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7607 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7608 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7609 "Unknown"),
7610 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7611 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7612 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7613 "Unknown"),
7614 netdev->dev_addr);
289700db
DS		 7615
7616 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7617 if (err)
9fe93afd 7618 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7619 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7620 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7621 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7622 part_str);
e8e26350 7623 else
289700db
DS		 7624 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7625 hw->mac.type, hw->phy.type, part_str);
9a799d71 7626
e8e26350 7627 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7628 e_dev_warn("PCI-Express bandwidth available for this card is "
7629 "not sufficient for optimal performance.\n");
7630 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7631 "is required.\n");
0c254d86
AK		 7632 }
7633
34b0368c
PWJ		 7634 /* save off EEPROM version number */
7635 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7636
9a799d71 7637 /* reset the hardware with the new settings */
794caeb2 7638 err = hw->mac.ops.start_hw(hw);
c44ade9e 7639
794caeb2
PWJ		 7640 if (err == IXGBE_ERR_EEPROM_VERSION) {
7641 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7642 e_dev_warn("This device is a pre-production adapter/LOM. "
7643 "Please be aware there may be issues associated "
7644 "with your hardware. If you are experiencing "
7645 "problems please contact your Intel or hardware "
7646 "representative who provided you with this "
7647 "hardware.\n");
794caeb2 7648 }
9a799d71
AK		 7649 strcpy(netdev->name, "eth%d");
7650 err = register_netdev(netdev);
7651 if (err)
7652 goto err_register;
7653
54386467
JB		 7654 /* carrier off reporting is important to ethtool even BEFORE open */
7655 netif_carrier_off(netdev);
7656
5dd2d332 7657#ifdef CONFIG_IXGBE_DCA
652f093f 7658 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7659 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7660 ixgbe_setup_dca(adapter);
7661 }
7662#endif
1cdd1ec8 7663 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7664 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7665 for (i = 0; i < adapter->num_vfs; i++)
7666 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7667 }
7668
9612de92
ET		 7669 /* Inform firmware of driver version */
7670 if (hw->mac.ops.set_fw_drv_ver)
a38a104d
DS		 7671 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7672 FW_CEM_UNUSED_VER);
9612de92 7673
0365e6e4
PW		 7674 /* add san mac addr to netdev */
7675 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7676
849c4542 7677 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7678 cards_found++;
7679 return 0;
7680
7681err_register:
5eba3699 7682 ixgbe_release_hw_control(adapter);
7a921c93 7683 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7684err_sw_init:
7685err_eeprom:
1cdd1ec8
GR		 7686 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7687 ixgbe_disable_sriov(adapter);
7086400d 7688 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7689 iounmap(hw->hw_addr);
7690err_ioremap:
7691 free_netdev(netdev);
7692err_alloc_etherdev:
e8e9f696
JP		 7693 pci_release_selected_regions(pdev,
7694 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7695err_pci_reg:
7696err_dma:
7697 pci_disable_device(pdev);
7698 return err;
7699}
7700
7701/**
7702 * ixgbe_remove - Device Removal Routine
7703 * @pdev: PCI device information struct
7704 *
7705 * ixgbe_remove is called by the PCI subsystem to alert the driver
7706 * that it should release a PCI device. The could be caused by a
7707 * Hot-Plug event, or because the driver is going to be removed from
7708 * memory.
7709 **/
7710static void __devexit ixgbe_remove(struct pci_dev *pdev)
7711{
c60fbb00
AD		 7712 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7713 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7714
7715 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7716 cancel_work_sync(&adapter->service_task);
9a799d71 7717
5dd2d332 7718#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7719 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7720 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7721 dca_remove_requester(&pdev->dev);
7722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7723 }
7724
7725#endif
332d4a7d
YZ		 7726#ifdef IXGBE_FCOE
7727 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7728 ixgbe_cleanup_fcoe(adapter);
7729
7730#endif /* IXGBE_FCOE */
0365e6e4
PW		 7731
7732 /* remove the added san mac */
7733 ixgbe_del_sanmac_netdev(netdev);
7734
c4900be0
DS		 7735 if (netdev->reg_state == NETREG_REGISTERED)
7736 unregister_netdev(netdev);
9a799d71 7737
1cdd1ec8
GR		 7738 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7739 ixgbe_disable_sriov(adapter);
7740
7a921c93 7741 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7742
021230d4 7743 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7744
7745 iounmap(adapter->hw.hw_addr);
9ce77666 7746 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7747 IORESOURCE_MEM));
9a799d71 7748
849c4542 7749 e_dev_info("complete\n");
021230d4 7750
9a799d71
AK		 7751 free_netdev(netdev);
7752
19d5afd4 7753 pci_disable_pcie_error_reporting(pdev);
6fabd715 7754
9a799d71
AK		 7755 pci_disable_device(pdev);
7756}
7757
7758/**
7759 * ixgbe_io_error_detected - called when PCI error is detected
7760 * @pdev: Pointer to PCI device
7761 * @state: The current pci connection state
7762 *
7763 * This function is called after a PCI bus error affecting
7764 * this device has been detected.
7765 */
7766static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7767 pci_channel_state_t state)
9a799d71 7768{
c60fbb00
AD		 7769 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7770 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7771
7772 netif_device_detach(netdev);
7773
3044b8d1
BL		 7774 if (state == pci_channel_io_perm_failure)
7775 return PCI_ERS_RESULT_DISCONNECT;
7776
9a799d71
AK		 7777 if (netif_running(netdev))
7778 ixgbe_down(adapter);
7779 pci_disable_device(pdev);
7780
b4617240 7781 /* Request a slot reset. */
9a799d71
AK		 7782 return PCI_ERS_RESULT_NEED_RESET;
7783}
7784
7785/**
7786 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7787 * @pdev: Pointer to PCI device
7788 *
7789 * Restart the card from scratch, as if from a cold-boot.
7790 */
7791static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7792{
c60fbb00 7793 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7794 pci_ers_result_t result;
7795 int err;
9a799d71 7796
9ce77666 7797 if (pci_enable_device_mem(pdev)) {
396e799c 7798 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7799 result = PCI_ERS_RESULT_DISCONNECT;
7800 } else {
7801 pci_set_master(pdev);
7802 pci_restore_state(pdev);
c0e1f68b 7803 pci_save_state(pdev);
9a799d71 7804
dd4d8ca6 7805 pci_wake_from_d3(pdev, false);
9a799d71 7806
6fabd715 7807 ixgbe_reset(adapter);
88512539 7808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7809 result = PCI_ERS_RESULT_RECOVERED;
7810 }
7811
7812 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7813 if (err) {
849c4542
ET		 7814 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7815 "failed 0x%0x\n", err);
6fabd715
PWJ		 7816 /* non-fatal, continue */
7817 }
9a799d71 7818
6fabd715 7819 return result;
9a799d71
AK		 7820}
7821
7822/**
7823 * ixgbe_io_resume - called when traffic can start flowing again.
7824 * @pdev: Pointer to PCI device
7825 *
7826 * This callback is called when the error recovery driver tells us that
7827 * its OK to resume normal operation.
7828 */
7829static void ixgbe_io_resume(struct pci_dev *pdev)
7830{
c60fbb00
AD		 7831 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7832 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7833
7834 if (netif_running(netdev)) {
7835 if (ixgbe_up(adapter)) {
396e799c 7836 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7837 return;
7838 }
7839 }
7840
7841 netif_device_attach(netdev);
9a799d71
AK		 7842}
7843
7844static struct pci_error_handlers ixgbe_err_handler = {
7845 .error_detected = ixgbe_io_error_detected,
7846 .slot_reset = ixgbe_io_slot_reset,
7847 .resume = ixgbe_io_resume,
7848};
7849
7850static struct pci_driver ixgbe_driver = {
7851 .name = ixgbe_driver_name,
7852 .id_table = ixgbe_pci_tbl,
7853 .probe = ixgbe_probe,
7854 .remove = __devexit_p(ixgbe_remove),
7855#ifdef CONFIG_PM
7856 .suspend = ixgbe_suspend,
7857 .resume = ixgbe_resume,
7858#endif
7859 .shutdown = ixgbe_shutdown,
7860 .err_handler = &ixgbe_err_handler
7861};
7862
7863/**
7864 * ixgbe_init_module - Driver Registration Routine
7865 *
7866 * ixgbe_init_module is the first routine called when the driver is
7867 * loaded. All it does is register with the PCI subsystem.
7868 **/
7869static int __init ixgbe_init_module(void)
7870{
7871 int ret;
c7689578 7872 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7873 pr_info("%s\n", ixgbe_copyright);
9a799d71 7874
5dd2d332 7875#ifdef CONFIG_IXGBE_DCA
bd0362dd 7876 dca_register_notify(&dca_notifier);
bd0362dd 7877#endif
5dd2d332 7878
9a799d71
AK		 7879 ret = pci_register_driver(&ixgbe_driver);
7880 return ret;
7881}
b4617240 7882
9a799d71
AK		 7883module_init(ixgbe_init_module);
7884
7885/**
7886 * ixgbe_exit_module - Driver Exit Cleanup Routine
7887 *
7888 * ixgbe_exit_module is called just before the driver is removed
7889 * from memory.
7890 **/
7891static void __exit ixgbe_exit_module(void)
7892{
5dd2d332 7893#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7894 dca_unregister_notify(&dca_notifier);
7895#endif
9a799d71 7896 pci_unregister_driver(&ixgbe_driver);
1a51502b 7897 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7898}
bd0362dd 7899
5dd2d332 7900#ifdef CONFIG_IXGBE_DCA
bd0362dd 7901static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7902 void *p)
bd0362dd
JC		 7903{
7904 int ret_val;
7905
7906 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7907 __ixgbe_notify_dca);
bd0362dd
JC		 7908
7909 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7910}
b453368d 7911
5dd2d332 7912#endif /* CONFIG_IXGBE_DCA */
849c4542 7913
9a799d71
AK		 7914module_exit(ixgbe_exit_module);
7915
7916/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)