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ixgbe: IEEE 802.1Qaz, implement priority assignment table
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
310e5ca8 55#define DRV_VERSION "3.2.9-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 57static const char ixgbe_copyright[] =
58 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 59
60static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 61 [board_82598] = &ixgbe_82598_info,
e8e26350 62 [board_82599] = &ixgbe_82599_info,
fe15e8e1 63 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 64};
65
66/* ixgbe_pci_tbl - PCI Device ID Table
67 *
68 * Wildcard entries (PCI_ANY_ID) should come last
69 * Last entry must be all 0s
70 *
71 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
72 * Class, Class Mask, private data (not used) }
73 */
a3aa1884 74static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 78 board_82598 },
9a799d71 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 80 board_82598 },
0befdb3e
JB		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
82 board_82598 },
3845bec0
PWJ		 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
84 board_82598 },
9a799d71 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 86 board_82598 },
8d792cd9
JB		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
88 board_82598 },
c4900be0
DS		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
92 board_82598 },
b95f5fcb
JB		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
94 board_82598 },
c4900be0
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
96 board_82598 },
2f21bdd3
DS		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
98 board_82598 },
e8e26350
PW		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
100 board_82599 },
1fcf03e6
PWJ		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
102 board_82599 },
74757d49
DS		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
104 board_82599 },
e8e26350
PW		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
106 board_82599 },
38ad1c8e
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
108 board_82599 },
dbfec662
DS		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
110 board_82599 },
8911184f
PWJ		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
112 board_82599 },
dbffcb21
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
114 board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
116 board_82599 },
119fc60a
MC		 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
118 board_82599 },
312eb931
DS		 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
120 board_82599 },
b93a2226 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 122 board_X540 },
9a799d71
AK		 123
124 /* required last entry */
125 {0, }
126};
127MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
128
5dd2d332 129#ifdef CONFIG_IXGBE_DCA
bd0362dd 130static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 131 void *p);
bd0362dd
JC		 132static struct notifier_block dca_notifier = {
133 .notifier_call = ixgbe_notify_dca,
134 .next = NULL,
135 .priority = 0
136};
137#endif
138
1cdd1ec8
GR		 139#ifdef CONFIG_PCI_IOV
140static unsigned int max_vfs;
141module_param(max_vfs, uint, 0);
e8e9f696
JP		 142MODULE_PARM_DESC(max_vfs,
143 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 144#endif /* CONFIG_PCI_IOV */
145
9a799d71
AK		 146MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
147MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
148MODULE_LICENSE("GPL");
149MODULE_VERSION(DRV_VERSION);
150
151#define DEFAULT_DEBUG_LEVEL_SHIFT 3
152
1cdd1ec8
GR		 153static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
154{
155 struct ixgbe_hw *hw = &adapter->hw;
156 u32 gcr;
157 u32 gpie;
158 u32 vmdctl;
159
160#ifdef CONFIG_PCI_IOV
161 /* disable iov and allow time for transactions to clear */
162 pci_disable_sriov(adapter->pdev);
163#endif
164
165 /* turn off device IOV mode */
166 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
167 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
168 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
169 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
170 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
171 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
172
173 /* set default pool back to 0 */
174 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
175 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
176 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
177
178 /* take a breather then clean up driver data */
179 msleep(100);
e8e9f696
JP		 180
181 kfree(adapter->vfinfo);
1cdd1ec8
GR		 182 adapter->vfinfo = NULL;
183
184 adapter->num_vfs = 0;
185 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
186}
187
dcd79aeb
TI		 188struct ixgbe_reg_info {
189 u32 ofs;
190 char *name;
191};
192
193static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
194
195 /* General Registers */
196 {IXGBE_CTRL, "CTRL"},
197 {IXGBE_STATUS, "STATUS"},
198 {IXGBE_CTRL_EXT, "CTRL_EXT"},
199
200 /* Interrupt Registers */
201 {IXGBE_EICR, "EICR"},
202
203 /* RX Registers */
204 {IXGBE_SRRCTL(0), "SRRCTL"},
205 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
206 {IXGBE_RDLEN(0), "RDLEN"},
207 {IXGBE_RDH(0), "RDH"},
208 {IXGBE_RDT(0), "RDT"},
209 {IXGBE_RXDCTL(0), "RXDCTL"},
210 {IXGBE_RDBAL(0), "RDBAL"},
211 {IXGBE_RDBAH(0), "RDBAH"},
212
213 /* TX Registers */
214 {IXGBE_TDBAL(0), "TDBAL"},
215 {IXGBE_TDBAH(0), "TDBAH"},
216 {IXGBE_TDLEN(0), "TDLEN"},
217 {IXGBE_TDH(0), "TDH"},
218 {IXGBE_TDT(0), "TDT"},
219 {IXGBE_TXDCTL(0), "TXDCTL"},
220
221 /* List Terminator */
222 {}
223};
224
225
226/*
227 * ixgbe_regdump - register printout routine
228 */
229static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
230{
231 int i = 0, j = 0;
232 char rname[16];
233 u32 regs[64];
234
235 switch (reginfo->ofs) {
236 case IXGBE_SRRCTL(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
239 break;
240 case IXGBE_DCA_RXCTRL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
243 break;
244 case IXGBE_RDLEN(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
247 break;
248 case IXGBE_RDH(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
251 break;
252 case IXGBE_RDT(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
255 break;
256 case IXGBE_RXDCTL(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
259 break;
260 case IXGBE_RDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
263 break;
264 case IXGBE_RDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
267 break;
268 case IXGBE_TDBAL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
271 break;
272 case IXGBE_TDBAH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
275 break;
276 case IXGBE_TDLEN(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
279 break;
280 case IXGBE_TDH(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
283 break;
284 case IXGBE_TDT(0):
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
287 break;
288 case IXGBE_TXDCTL(0):
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
291 break;
292 default:
c7689578 293 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 294 IXGBE_READ_REG(hw, reginfo->ofs));
295 return;
296 }
297
298 for (i = 0; i < 8; i++) {
299 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 300 pr_err("%-15s", rname);
dcd79aeb 301 for (j = 0; j < 8; j++)
c7689578
JP		 302 pr_cont(" %08x", regs[i*8+j]);
303 pr_cont("\n");
dcd79aeb
TI		 304 }
305
306}
307
308/*
309 * ixgbe_dump - Print registers, tx-rings and rx-rings
310 */
311static void ixgbe_dump(struct ixgbe_adapter *adapter)
312{
313 struct net_device *netdev = adapter->netdev;
314 struct ixgbe_hw *hw = &adapter->hw;
315 struct ixgbe_reg_info *reginfo;
316 int n = 0;
317 struct ixgbe_ring *tx_ring;
318 struct ixgbe_tx_buffer *tx_buffer_info;
319 union ixgbe_adv_tx_desc *tx_desc;
320 struct my_u0 { u64 a; u64 b; } *u0;
321 struct ixgbe_ring *rx_ring;
322 union ixgbe_adv_rx_desc *rx_desc;
323 struct ixgbe_rx_buffer *rx_buffer_info;
324 u32 staterr;
325 int i = 0;
326
327 if (!netif_msg_hw(adapter))
328 return;
329
330 /* Print netdevice Info */
331 if (netdev) {
332 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 333 pr_info("Device Name state "
dcd79aeb 334 "trans_start last_rx\n");
c7689578
JP		 335 pr_info("%-15s %016lX %016lX %016lX\n",
336 netdev->name,
337 netdev->state,
338 netdev->trans_start,
339 netdev->last_rx);
dcd79aeb
TI		 340 }
341
342 /* Print Registers */
343 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 344 pr_info(" Register Name Value\n");
dcd79aeb
TI		 345 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
346 reginfo->name; reginfo++) {
347 ixgbe_regdump(hw, reginfo);
348 }
349
350 /* Print TX Ring Summary */
351 if (!netdev || !netif_running(netdev))
352 goto exit;
353
354 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 355 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 356 for (n = 0; n < adapter->num_tx_queues; n++) {
357 tx_ring = adapter->tx_ring[n];
358 tx_buffer_info =
359 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 360 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 361 n, tx_ring->next_to_use, tx_ring->next_to_clean,
362 (u64)tx_buffer_info->dma,
363 tx_buffer_info->length,
364 tx_buffer_info->next_to_watch,
365 (u64)tx_buffer_info->time_stamp);
366 }
367
368 /* Print TX Rings */
369 if (!netif_msg_tx_done(adapter))
370 goto rx_ring_summary;
371
372 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
373
374 /* Transmit Descriptor Formats
375 *
376 * Advanced Transmit Descriptor
377 * +--------------------------------------------------------------+
378 * 0 | Buffer Address [63:0] |
379 * +--------------------------------------------------------------+
380 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
381 * +--------------------------------------------------------------+
382 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
383 */
384
385 for (n = 0; n < adapter->num_tx_queues; n++) {
386 tx_ring = adapter->tx_ring[n];
c7689578
JP		 387 pr_info("------------------------------------\n");
388 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
389 pr_info("------------------------------------\n");
390 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 391 "[PlPOIdStDDt Ln] [bi->dma ] "
392 "leng ntw timestamp bi->skb\n");
393
394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 395 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 396 tx_buffer_info = &tx_ring->tx_buffer_info[i];
397 u0 = (struct my_u0 *)tx_desc;
c7689578 398 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 399 " %04X %3X %016llX %p", i,
400 le64_to_cpu(u0->a),
401 le64_to_cpu(u0->b),
402 (u64)tx_buffer_info->dma,
403 tx_buffer_info->length,
404 tx_buffer_info->next_to_watch,
405 (u64)tx_buffer_info->time_stamp,
406 tx_buffer_info->skb);
407 if (i == tx_ring->next_to_use &&
408 i == tx_ring->next_to_clean)
c7689578 409 pr_cont(" NTC/U\n");
dcd79aeb 410 else if (i == tx_ring->next_to_use)
c7689578 411 pr_cont(" NTU\n");
dcd79aeb 412 else if (i == tx_ring->next_to_clean)
c7689578 413 pr_cont(" NTC\n");
dcd79aeb 414 else
c7689578 415 pr_cont("\n");
dcd79aeb
TI		 416
417 if (netif_msg_pktdata(adapter) &&
418 tx_buffer_info->dma != 0)
419 print_hex_dump(KERN_INFO, "",
420 DUMP_PREFIX_ADDRESS, 16, 1,
421 phys_to_virt(tx_buffer_info->dma),
422 tx_buffer_info->length, true);
423 }
424 }
425
426 /* Print RX Rings Summary */
427rx_ring_summary:
428 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 429 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 430 for (n = 0; n < adapter->num_rx_queues; n++) {
431 rx_ring = adapter->rx_ring[n];
c7689578
JP		 432 pr_info("%5d %5X %5X\n",
433 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 434 }
435
436 /* Print RX Rings */
437 if (!netif_msg_rx_status(adapter))
438 goto exit;
439
440 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
441
442 /* Advanced Receive Descriptor (Read) Format
443 * 63 1 0
444 * +-----------------------------------------------------+
445 * 0 | Packet Buffer Address [63:1] |A0/NSE|
446 * +----------------------------------------------+------+
447 * 8 | Header Buffer Address [63:1] | DD |
448 * +-----------------------------------------------------+
449 *
450 *
451 * Advanced Receive Descriptor (Write-Back) Format
452 *
453 * 63 48 47 32 31 30 21 20 16 15 4 3 0
454 * +------------------------------------------------------+
455 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
456 * | Checksum Ident | | | | Type | Type |
457 * +------------------------------------------------------+
458 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
459 * +------------------------------------------------------+
460 * 63 48 47 32 31 20 19 0
461 */
462 for (n = 0; n < adapter->num_rx_queues; n++) {
463 rx_ring = adapter->rx_ring[n];
c7689578
JP		 464 pr_info("------------------------------------\n");
465 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
466 pr_info("------------------------------------\n");
467 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 468 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
469 "<-- Adv Rx Read format\n");
c7689578 470 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 471 "[vl er S cks ln] ---------------- [bi->skb] "
472 "<-- Adv Rx Write-Back format\n");
473
474 for (i = 0; i < rx_ring->count; i++) {
475 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 476 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 477 u0 = (struct my_u0 *)rx_desc;
478 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
479 if (staterr & IXGBE_RXD_STAT_DD) {
480 /* Descriptor Done */
c7689578 481 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 482 "%016llX ---------------- %p", i,
483 le64_to_cpu(u0->a),
484 le64_to_cpu(u0->b),
485 rx_buffer_info->skb);
486 } else {
c7689578 487 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 488 "%016llX %016llX %p", i,
489 le64_to_cpu(u0->a),
490 le64_to_cpu(u0->b),
491 (u64)rx_buffer_info->dma,
492 rx_buffer_info->skb);
493
494 if (netif_msg_pktdata(adapter)) {
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(rx_buffer_info->dma),
498 rx_ring->rx_buf_len, true);
499
500 if (rx_ring->rx_buf_len
501 < IXGBE_RXBUFFER_2048)
502 print_hex_dump(KERN_INFO, "",
503 DUMP_PREFIX_ADDRESS, 16, 1,
504 phys_to_virt(
505 rx_buffer_info->page_dma +
506 rx_buffer_info->page_offset
507 ),
508 PAGE_SIZE/2, true);
509 }
510 }
511
512 if (i == rx_ring->next_to_use)
c7689578 513 pr_cont(" NTU\n");
dcd79aeb 514 else if (i == rx_ring->next_to_clean)
c7689578 515 pr_cont(" NTC\n");
dcd79aeb 516 else
c7689578 517 pr_cont("\n");
dcd79aeb
TI		 518
519 }
520 }
521
522exit:
523 return;
524}
525
5eba3699
AV		 526static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
527{
528 u32 ctrl_ext;
529
530 /* Let firmware take over control of h/w */
531 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 533 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 534}
535
536static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
537{
538 u32 ctrl_ext;
539
540 /* Let firmware know the driver has taken over */
541 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 543 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 544}
9a799d71 545
e8e26350
PW		 546/*
547 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
548 * @adapter: pointer to adapter struct
549 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
550 * @queue: queue to map the corresponding interrupt to
551 * @msix_vector: the vector to map to the corresponding queue
552 *
553 */
554static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 555 u8 queue, u8 msix_vector)
9a799d71
AK		 556{
557 u32 ivar, index;
e8e26350
PW		 558 struct ixgbe_hw *hw = &adapter->hw;
559 switch (hw->mac.type) {
560 case ixgbe_mac_82598EB:
561 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
562 if (direction == -1)
563 direction = 0;
564 index = (((direction * 64) + queue) >> 2) & 0x1F;
565 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
566 ivar &= ~(0xFF << (8 * (queue & 0x3)));
567 ivar |= (msix_vector << (8 * (queue & 0x3)));
568 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
569 break;
570 case ixgbe_mac_82599EB:
b93a2226 571 case ixgbe_mac_X540:
e8e26350
PW		 572 if (direction == -1) {
573 /* other causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((queue & 1) * 8);
576 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
580 break;
581 } else {
582 /* tx or rx causes */
583 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
584 index = ((16 * (queue & 1)) + (8 * direction));
585 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
586 ivar &= ~(0xFF << index);
587 ivar |= (msix_vector << index);
588 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
589 break;
590 }
591 default:
592 break;
593 }
9a799d71
AK		 594}
595
fe49f04a 596static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 597 u64 qmask)
fe49f04a
AD		 598{
599 u32 mask;
600
bd508178
AD		 601 switch (adapter->hw.mac.type) {
602 case ixgbe_mac_82598EB:
fe49f04a
AD		 603 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 605 break;
606 case ixgbe_mac_82599EB:
b93a2226 607 case ixgbe_mac_X540:
fe49f04a
AD		 608 mask = (qmask & 0xFFFFFFFF);
609 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
610 mask = (qmask >> 32);
611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 612 break;
613 default:
614 break;
fe49f04a
AD		 615 }
616}
617
b6ec895e
AD		 618void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
619 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 620{
e5a43549
AD		 621 if (tx_buffer_info->dma) {
622 if (tx_buffer_info->mapped_as_page)
b6ec895e 623 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 624 tx_buffer_info->dma,
625 tx_buffer_info->length,
1b507730 626 DMA_TO_DEVICE);
e5a43549 627 else
b6ec895e 628 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 629 tx_buffer_info->dma,
630 tx_buffer_info->length,
1b507730 631 DMA_TO_DEVICE);
e5a43549
AD		 632 tx_buffer_info->dma = 0;
633 }
9a799d71
AK		 634 if (tx_buffer_info->skb) {
635 dev_kfree_skb_any(tx_buffer_info->skb);
636 tx_buffer_info->skb = NULL;
637 }
44df32c5 638 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 639 /* tx_buffer_info must be completely set up in the transmit path */
640}
641
26f23d82 642/**
c84d324c
JF		 643 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
644 * @adapter: driver private struct
645 * @index: reg idx of queue to query (0-127)
26f23d82 646 *
c84d324c
JF		 647 * Helper function to determine the traffic index for a paticular
648 * register index.
26f23d82 649 *
c84d324c 650 * Returns : a tc index for use in range 0-7, or 0-3
26f23d82 651 */
3b2ee943 652static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
26f23d82 653{
c84d324c 654 int tc = -1;
e5b64635 655 int dcb_i = netdev_get_num_tc(adapter->netdev);
26f23d82 656
c84d324c
JF		 657 /* if DCB is not enabled the queues have no TC */
658 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
659 return tc;
26f23d82 660
c84d324c
JF		 661 /* check valid range */
662 if (reg_idx >= adapter->hw.mac.max_tx_queues)
663 return tc;
664
665 switch (adapter->hw.mac.type) {
666 case ixgbe_mac_82598EB:
667 tc = reg_idx >> 2;
668 break;
669 default:
670 if (dcb_i != 4 && dcb_i != 8)
6837e895 671 break;
c84d324c
JF		 672
673 /* if VMDq is enabled the lowest order bits determine TC */
674 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
675 IXGBE_FLAG_VMDQ_ENABLED)) {
676 tc = reg_idx & (dcb_i - 1);
677 break;
678 }
679
680 /*
681 * Convert the reg_idx into the correct TC. This bitmask
682 * targets the last full 32 ring traffic class and assigns
683 * it a value of 1. From there the rest of the rings are
684 * based on shifting the mask further up to include the
685 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
686 * will only ever be 8 or 4 and that reg_idx will never
687 * be greater then 128. The code without the power of 2
688 * optimizations would be:
689 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
690 */
691 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
692 tc >>= 9 - (reg_idx >> 5);
693 }
694
695 return tc;
696}
697
698static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
699{
700 struct ixgbe_hw *hw = &adapter->hw;
701 struct ixgbe_hw_stats *hwstats = &adapter->stats;
702 u32 data = 0;
703 u32 xoff[8] = {0};
704 int i;
705
706 if ((hw->fc.current_mode == ixgbe_fc_full) ||
707 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
708 switch (hw->mac.type) {
709 case ixgbe_mac_82598EB:
710 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 711 break;
712 default:
c84d324c
JF		 713 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
714 }
715 hwstats->lxoffrxc += data;
716
717 /* refill credits (no tx hang) if we received xoff */
718 if (!data)
719 return;
720
721 for (i = 0; i < adapter->num_tx_queues; i++)
722 clear_bit(__IXGBE_HANG_CHECK_ARMED,
723 &adapter->tx_ring[i]->state);
724 return;
725 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
726 return;
727
728 /* update stats for each tc, only valid with PFC enabled */
729 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
730 switch (hw->mac.type) {
731 case ixgbe_mac_82598EB:
732 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 733 break;
c84d324c
JF		 734 default:
735 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 736 }
c84d324c
JF		 737 hwstats->pxoffrxc[i] += xoff[i];
738 }
739
740 /* disarm tx queues that have received xoff frames */
741 for (i = 0; i < adapter->num_tx_queues; i++) {
742 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
743 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
744
745 if (xoff[tc])
746 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 747 }
26f23d82
YZ		 748}
749
c84d324c 750static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 751{
c84d324c
JF		 752 return ring->tx_stats.completed;
753}
754
755static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
756{
757 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 758 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 759
c84d324c
JF		 760 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
761 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
762
763 if (head != tail)
764 return (head < tail) ?
765 tail - head : (tail + ring->count - head);
766
767 return 0;
768}
769
770static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
771{
772 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
773 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
774 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
775 bool ret = false;
776
7d637bcc 777 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 778
779 /*
780 * Check for a hung queue, but be thorough. This verifies
781 * that a transmit has been completed since the previous
782 * check AND there is at least one packet pending. The
783 * ARMED bit is set to indicate a potential hang. The
784 * bit is cleared if a pause frame is received to remove
785 * false hang detection due to PFC or 802.3x frames. By
786 * requiring this to fail twice we avoid races with
787 * pfc clearing the ARMED bit and conditions where we
788 * run the check_tx_hang logic with a transmit completion
789 * pending but without time to complete it yet.
790 */
791 if ((tx_done_old == tx_done) && tx_pending) {
792 /* make sure it is true for two checks in a row */
793 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
794 &tx_ring->state);
795 } else {
796 /* update completed stats and continue */
797 tx_ring->tx_stats.tx_done_old = tx_done;
798 /* reset the countdown */
799 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 800 }
801
c84d324c 802 return ret;
9a799d71
AK		 803}
804
b4617240
PW		 805#define IXGBE_MAX_TXD_PWR 14
806#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 807
808/* Tx Descriptors needed, worst case */
809#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
810 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
811#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 812 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 813
e01c31a5
JB		 814static void ixgbe_tx_timeout(struct net_device *netdev);
815
9a799d71
AK		 816/**
817 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 818 * @q_vector: structure containing interrupt and ring information
e01c31a5 819 * @tx_ring: tx ring to clean
9a799d71 820 **/
fe49f04a 821static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 822 struct ixgbe_ring *tx_ring)
9a799d71 823{
fe49f04a 824 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 825 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
826 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 827 unsigned int total_bytes = 0, total_packets = 0;
b953799e 828 u16 i, eop, count = 0;
9a799d71
AK		 829
830 i = tx_ring->next_to_clean;
12207e49 831 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 832 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 833
834 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 835 (count < tx_ring->work_limit)) {
12207e49 836 bool cleaned = false;
2d0bb1c1 837 rmb(); /* read buffer_info after eop_desc */
12207e49 838 for ( ; !cleaned; count++) {
31f05a2d 839 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 840 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 841
842 tx_desc->wb.status = 0;
12207e49 843 cleaned = (i == eop);
9a799d71 844
8ad494b0
AD		 845 i++;
846 if (i == tx_ring->count)
847 i = 0;
e01c31a5 848
8ad494b0
AD		 849 if (cleaned && tx_buffer_info->skb) {
850 total_bytes += tx_buffer_info->bytecount;
851 total_packets += tx_buffer_info->gso_segs;
e092be60 852 }
e01c31a5 853
b6ec895e 854 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 855 tx_buffer_info);
e01c31a5 856 }
12207e49 857
c84d324c 858 tx_ring->tx_stats.completed++;
12207e49 859 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 860 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 861 }
862
9a799d71 863 tx_ring->next_to_clean = i;
b953799e
AD		 864 tx_ring->total_bytes += total_bytes;
865 tx_ring->total_packets += total_packets;
866 u64_stats_update_begin(&tx_ring->syncp);
867 tx_ring->stats.packets += total_packets;
868 tx_ring->stats.bytes += total_bytes;
869 u64_stats_update_end(&tx_ring->syncp);
870
c84d324c
JF		 871 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
872 /* schedule immediate reset if we believe we hung */
873 struct ixgbe_hw *hw = &adapter->hw;
874 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
875 e_err(drv, "Detected Tx Unit Hang\n"
876 " Tx Queue <%d>\n"
877 " TDH, TDT <%x>, <%x>\n"
878 " next_to_use <%x>\n"
879 " next_to_clean <%x>\n"
880 "tx_buffer_info[next_to_clean]\n"
881 " time_stamp <%lx>\n"
882 " jiffies <%lx>\n",
883 tx_ring->queue_index,
884 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
885 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
886 tx_ring->next_to_use, eop,
887 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
888
889 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
890
891 e_info(probe,
892 "tx hang %d detected on queue %d, resetting adapter\n",
893 adapter->tx_timeout_count + 1, tx_ring->queue_index);
894
b953799e 895 /* schedule immediate reset if we believe we hung */
b953799e
AD		 896 ixgbe_tx_timeout(adapter->netdev);
897
898 /* the adapter is about to reset, no point in enabling stuff */
899 return true;
900 }
9a799d71 901
e092be60 902#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 903 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 904 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 905 /* Make sure that anybody stopping the queue after this
906 * sees the new next_to_clean.
907 */
908 smp_mb();
fc77dc3c 909 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 910 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 911 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 912 ++tx_ring->tx_stats.restart_queue;
30eba97a 913 }
e092be60 914 }
9a799d71 915
807540ba 916 return count < tx_ring->work_limit;
9a799d71
AK		 917}
918
5dd2d332 919#ifdef CONFIG_IXGBE_DCA
bd0362dd 920static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 921 struct ixgbe_ring *rx_ring,
922 int cpu)
bd0362dd 923{
33cf09c9 924 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 925 u32 rxctrl;
33cf09c9
AD		 926 u8 reg_idx = rx_ring->reg_idx;
927
928 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
929 switch (hw->mac.type) {
930 case ixgbe_mac_82598EB:
931 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
932 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
933 break;
934 case ixgbe_mac_82599EB:
b93a2226 935 case ixgbe_mac_X540:
33cf09c9
AD		 936 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
937 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
938 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
939 break;
940 default:
941 break;
bd0362dd 942 }
33cf09c9
AD		 943 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
944 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
945 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
946 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
947 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
948 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 949}
950
951static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 952 struct ixgbe_ring *tx_ring,
953 int cpu)
bd0362dd 954{
33cf09c9 955 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 956 u32 txctrl;
33cf09c9
AD		 957 u8 reg_idx = tx_ring->reg_idx;
958
959 switch (hw->mac.type) {
960 case ixgbe_mac_82598EB:
961 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
962 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
963 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
964 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
965 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
966 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
967 break;
968 case ixgbe_mac_82599EB:
b93a2226 969 case ixgbe_mac_X540:
33cf09c9
AD		 970 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
971 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
972 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
973 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
974 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
975 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
976 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
977 break;
978 default:
979 break;
980 }
981}
982
983static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
984{
985 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 986 int cpu = get_cpu();
33cf09c9
AD		 987 long r_idx;
988 int i;
bd0362dd 989
33cf09c9
AD		 990 if (q_vector->cpu == cpu)
991 goto out_no_update;
992
993 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
994 for (i = 0; i < q_vector->txr_count; i++) {
995 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
996 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
997 r_idx + 1);
bd0362dd 998 }
33cf09c9
AD		 999
1000 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1001 for (i = 0; i < q_vector->rxr_count; i++) {
1002 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1003 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1004 r_idx + 1);
1005 }
1006
1007 q_vector->cpu = cpu;
1008out_no_update:
bd0362dd
JC		 1009 put_cpu();
1010}
1011
1012static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1013{
33cf09c9 1014 int num_q_vectors;
bd0362dd
JC		 1015 int i;
1016
1017 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1018 return;
1019
e35ec126
AD		 1020 /* always use CB2 mode, difference is masked in the CB driver */
1021 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1022
33cf09c9
AD		 1023 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1024 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1025 else
1026 num_q_vectors = 1;
1027
1028 for (i = 0; i < num_q_vectors; i++) {
1029 adapter->q_vector[i]->cpu = -1;
1030 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1031 }
1032}
1033
1034static int __ixgbe_notify_dca(struct device *dev, void *data)
1035{
c60fbb00 1036 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1037 unsigned long event = *(unsigned long *)data;
1038
33cf09c9
AD		 1039 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1040 return 0;
1041
bd0362dd
JC		 1042 switch (event) {
1043 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1044 /* if we're already enabled, don't do it again */
1045 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1046 break;
652f093f 1047 if (dca_add_requester(dev) == 0) {
96b0e0f6 1048 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1049 ixgbe_setup_dca(adapter);
1050 break;
1051 }
1052 /* Fall Through since DCA is disabled. */
1053 case DCA_PROVIDER_REMOVE:
1054 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1055 dca_remove_requester(dev);
1056 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1057 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1058 }
1059 break;
1060 }
1061
652f093f 1062 return 0;
bd0362dd
JC		 1063}
1064
5dd2d332 1065#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 1066/**
1067 * ixgbe_receive_skb - Send a completed packet up the stack
1068 * @adapter: board private structure
1069 * @skb: packet to send up
177db6ff
MC		 1070 * @status: hardware indication of status of receive
1071 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1072 * @rx_desc: rx descriptor
9a799d71 1073 **/
78b6f4ce 1074static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1075 struct sk_buff *skb, u8 status,
1076 struct ixgbe_ring *ring,
1077 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1078{
78b6f4ce
HX		 1079 struct ixgbe_adapter *adapter = q_vector->adapter;
1080 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1081 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1082 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1083
f62bbb5e
JG		 1084 if (is_vlan && (tag & VLAN_VID_MASK))
1085 __vlan_hwaccel_put_tag(skb, tag);
1086
1087 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1088 napi_gro_receive(napi, skb);
1089 else
1090 netif_rx(skb);
9a799d71
AK		 1091}
1092
e59bd25d
AV		 1093/**
1094 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1095 * @adapter: address of board private structure
1096 * @status_err: hardware indication of status of receive
1097 * @skb: skb currently being received and modified
1098 **/
9a799d71 1099static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1100 union ixgbe_adv_rx_desc *rx_desc,
1101 struct sk_buff *skb)
9a799d71 1102{
8bae1b2b
DS		 1103 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1104
bc8acf2c 1105 skb_checksum_none_assert(skb);
9a799d71 1106
712744be
JB		 1107 /* Rx csum disabled */
1108 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1109 return;
e59bd25d
AV		 1110
1111 /* if IP and error */
1112 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1113 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1114 adapter->hw_csum_rx_error++;
1115 return;
1116 }
e59bd25d
AV		 1117
1118 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1119 return;
1120
1121 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1122 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1123
1124 /*
1125 * 82599 errata, UDP frames with a 0 checksum can be marked as
1126 * checksum errors.
1127 */
1128 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1129 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1130 return;
1131
e59bd25d
AV		 1132 adapter->hw_csum_rx_error++;
1133 return;
1134 }
1135
9a799d71 1136 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1137 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1138}
1139
84ea2591 1140static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1141{
1142 /*
1143 * Force memory writes to complete before letting h/w
1144 * know there are new descriptors to fetch. (Only
1145 * applicable for weak-ordered memory model archs,
1146 * such as IA-64).
1147 */
1148 wmb();
84ea2591 1149 writel(val, rx_ring->tail);
e8e26350
PW		 1150}
1151
9a799d71
AK		 1152/**
1153 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1154 * @rx_ring: ring to place buffers on
1155 * @cleaned_count: number of buffers to replace
9a799d71 1156 **/
fc77dc3c 1157void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1158{
9a799d71 1159 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1160 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1161 struct sk_buff *skb;
1162 u16 i = rx_ring->next_to_use;
9a799d71 1163
fc77dc3c
AD		 1164 /* do nothing if no valid netdev defined */
1165 if (!rx_ring->netdev)
1166 return;
1167
9a799d71 1168 while (cleaned_count--) {
31f05a2d 1169 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1170 bi = &rx_ring->rx_buffer_info[i];
1171 skb = bi->skb;
9a799d71 1172
d5f398ed 1173 if (!skb) {
fc77dc3c 1174 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1175 rx_ring->rx_buf_len);
9a799d71 1176 if (!skb) {
5b7da515 1177 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1178 goto no_buffers;
1179 }
d716a7d8
AD		 1180 /* initialize queue mapping */
1181 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1182 bi->skb = skb;
d716a7d8 1183 }
9a799d71 1184
d716a7d8 1185 if (!bi->dma) {
b6ec895e 1186 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1187 skb->data,
e8e9f696 1188 rx_ring->rx_buf_len,
1b507730 1189 DMA_FROM_DEVICE);
b6ec895e 1190 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1191 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1192 bi->dma = 0;
1193 goto no_buffers;
1194 }
9a799d71 1195 }
d5f398ed 1196
7d637bcc 1197 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1198 if (!bi->page) {
fc77dc3c 1199 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1200 if (!bi->page) {
5b7da515 1201 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1202 goto no_buffers;
1203 }
1204 }
1205
1206 if (!bi->page_dma) {
1207 /* use a half page if we're re-using */
1208 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1209 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1210 bi->page,
1211 bi->page_offset,
1212 PAGE_SIZE / 2,
1213 DMA_FROM_DEVICE);
b6ec895e 1214 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1215 bi->page_dma)) {
5b7da515 1216 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1217 bi->page_dma = 0;
1218 goto no_buffers;
1219 }
1220 }
1221
1222 /* Refresh the desc even if buffer_addrs didn't change
1223 * because each write-back erases this info. */
3a581073
JB		 1224 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1225 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1226 } else {
3a581073 1227 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1228 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1229 }
1230
1231 i++;
1232 if (i == rx_ring->count)
1233 i = 0;
9a799d71 1234 }
7c6e0a43 1235
9a799d71
AK		 1236no_buffers:
1237 if (rx_ring->next_to_use != i) {
1238 rx_ring->next_to_use = i;
84ea2591 1239 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1240 }
1241}
1242
c267fc16 1243static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1244{
c267fc16
AD		 1245 /* HW will not DMA in data larger than the given buffer, even if it
1246 * parses the (NFS, of course) header to be larger. In that case, it
1247 * fills the header buffer and spills the rest into the page.
1248 */
1249 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1250 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1251 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1252 if (hlen > IXGBE_RX_HDR_SIZE)
1253 hlen = IXGBE_RX_HDR_SIZE;
1254 return hlen;
7c6e0a43
JB		 1255}
1256
f8212f97
AD		 1257/**
1258 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1259 * @skb: pointer to the last skb in the rsc queue
1260 *
1261 * This function changes a queue full of hw rsc buffers into a completed
1262 * packet. It uses the ->prev pointers to find the first packet and then
1263 * turns it into the frag list owner.
1264 **/
aa80175a 1265static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1266{
1267 unsigned int frag_list_size = 0;
aa80175a 1268 unsigned int skb_cnt = 1;
f8212f97
AD		 1269
1270 while (skb->prev) {
1271 struct sk_buff *prev = skb->prev;
1272 frag_list_size += skb->len;
1273 skb->prev = NULL;
1274 skb = prev;
aa80175a 1275 skb_cnt++;
f8212f97
AD		 1276 }
1277
1278 skb_shinfo(skb)->frag_list = skb->next;
1279 skb->next = NULL;
1280 skb->len += frag_list_size;
1281 skb->data_len += frag_list_size;
1282 skb->truesize += frag_list_size;
aa80175a
AD		 1283 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1284
f8212f97
AD		 1285 return skb;
1286}
1287
aa80175a
AD		 1288static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1289{
1290 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1291 IXGBE_RXDADV_RSCCNT_MASK);
1292}
43634e82 1293
c267fc16 1294static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1295 struct ixgbe_ring *rx_ring,
1296 int *work_done, int work_to_do)
9a799d71 1297{
78b6f4ce 1298 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1299 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1300 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1301 struct sk_buff *skb;
d2f4fbe2 1302 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1303 const int current_node = numa_node_id();
3d8fd385
YZ		 1304#ifdef IXGBE_FCOE
1305 int ddp_bytes = 0;
1306#endif /* IXGBE_FCOE */
c267fc16
AD		 1307 u32 staterr;
1308 u16 i;
1309 u16 cleaned_count = 0;
aa80175a 1310 bool pkt_is_rsc = false;
9a799d71
AK		 1311
1312 i = rx_ring->next_to_clean;
31f05a2d 1313 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1314 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1315
1316 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1317 u32 upper_len = 0;
9a799d71 1318
3c945e5b 1319 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1320
c267fc16
AD		 1321 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1322
9a799d71 1323 skb = rx_buffer_info->skb;
9a799d71 1324 rx_buffer_info->skb = NULL;
c267fc16 1325 prefetch(skb->data);
9a799d71 1326
c267fc16 1327 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1328 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1329
1330 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1331 if (rx_buffer_info->dma) {
c267fc16 1332 u16 hlen;
aa80175a 1333 if (pkt_is_rsc &&
c267fc16
AD		 1334 !(staterr & IXGBE_RXD_STAT_EOP) &&
1335 !skb->prev) {
43634e82
MC		 1336 /*
1337 * When HWRSC is enabled, delay unmapping
1338 * of the first packet. It carries the
1339 * header information, HW may still
1340 * access the header after the writeback.
1341 * Only unmap it when EOP is reached
1342 */
e8171aaa 1343 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1344 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1345 } else {
b6ec895e 1346 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1347 rx_buffer_info->dma,
1348 rx_ring->rx_buf_len,
1349 DMA_FROM_DEVICE);
e8171aaa 1350 }
4f57ca6e 1351 rx_buffer_info->dma = 0;
c267fc16
AD		 1352
1353 if (ring_is_ps_enabled(rx_ring)) {
1354 hlen = ixgbe_get_hlen(rx_desc);
1355 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1356 } else {
1357 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1358 }
1359
1360 skb_put(skb, hlen);
1361 } else {
1362 /* assume packet split since header is unmapped */
1363 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1364 }
1365
1366 if (upper_len) {
b6ec895e
AD		 1367 dma_unmap_page(rx_ring->dev,
1368 rx_buffer_info->page_dma,
1369 PAGE_SIZE / 2,
1370 DMA_FROM_DEVICE);
9a799d71
AK		 1371 rx_buffer_info->page_dma = 0;
1372 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1373 rx_buffer_info->page,
1374 rx_buffer_info->page_offset,
1375 upper_len);
762f4c57 1376
c267fc16
AD		 1377 if ((page_count(rx_buffer_info->page) == 1) &&
1378 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1379 get_page(rx_buffer_info->page);
c267fc16
AD		 1380 else
1381 rx_buffer_info->page = NULL;
9a799d71
AK		 1382
1383 skb->len += upper_len;
1384 skb->data_len += upper_len;
1385 skb->truesize += upper_len;
1386 }
1387
1388 i++;
1389 if (i == rx_ring->count)
1390 i = 0;
9a799d71 1391
31f05a2d 1392 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1393 prefetch(next_rxd);
9a799d71 1394 cleaned_count++;
f8212f97 1395
aa80175a 1396 if (pkt_is_rsc) {
f8212f97
AD		 1397 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1398 IXGBE_RXDADV_NEXTP_SHIFT;
1399 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1400 } else {
1401 next_buffer = &rx_ring->rx_buffer_info[i];
1402 }
1403
c267fc16 1404 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1405 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1406 rx_buffer_info->skb = next_buffer->skb;
1407 rx_buffer_info->dma = next_buffer->dma;
1408 next_buffer->skb = skb;
1409 next_buffer->dma = 0;
1410 } else {
1411 skb->next = next_buffer->skb;
1412 skb->next->prev = skb;
1413 }
5b7da515 1414 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1415 goto next_desc;
1416 }
1417
aa80175a
AD		 1418 if (skb->prev) {
1419 skb = ixgbe_transform_rsc_queue(skb);
1420 /* if we got here without RSC the packet is invalid */
1421 if (!pkt_is_rsc) {
1422 __pskb_trim(skb, 0);
1423 rx_buffer_info->skb = skb;
1424 goto next_desc;
1425 }
1426 }
c267fc16
AD		 1427
1428 if (ring_is_rsc_enabled(rx_ring)) {
1429 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1430 dma_unmap_single(rx_ring->dev,
1431 IXGBE_RSC_CB(skb)->dma,
1432 rx_ring->rx_buf_len,
1433 DMA_FROM_DEVICE);
1434 IXGBE_RSC_CB(skb)->dma = 0;
1435 IXGBE_RSC_CB(skb)->delay_unmap = false;
1436 }
aa80175a
AD		 1437 }
1438 if (pkt_is_rsc) {
c267fc16
AD		 1439 if (ring_is_ps_enabled(rx_ring))
1440 rx_ring->rx_stats.rsc_count +=
aa80175a 1441 skb_shinfo(skb)->nr_frags;
c267fc16 1442 else
aa80175a
AD		 1443 rx_ring->rx_stats.rsc_count +=
1444 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1445 rx_ring->rx_stats.rsc_flush++;
1446 }
1447
1448 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1449 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1450 /* trim packet back to size 0 and recycle it */
1451 __pskb_trim(skb, 0);
1452 rx_buffer_info->skb = skb;
9a799d71
AK		 1453 goto next_desc;
1454 }
1455
8bae1b2b 1456 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1457
1458 /* probably a little skewed due to removing CRC */
1459 total_rx_bytes += skb->len;
1460 total_rx_packets++;
1461
fc77dc3c 1462 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1463#ifdef IXGBE_FCOE
1464 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1465 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1466 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1467 if (!ddp_bytes)
332d4a7d 1468 goto next_desc;
3d8fd385 1469 }
332d4a7d 1470#endif /* IXGBE_FCOE */
fdaff1ce 1471 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1472
1473next_desc:
1474 rx_desc->wb.upper.status_error = 0;
1475
c267fc16
AD		 1476 (*work_done)++;
1477 if (*work_done >= work_to_do)
1478 break;
1479
9a799d71
AK		 1480 /* return some buffers to hardware, one at a time is too slow */
1481 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1482 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1483 cleaned_count = 0;
1484 }
1485
1486 /* use prefetched values */
1487 rx_desc = next_rxd;
9a799d71 1488 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1489 }
1490
9a799d71
AK		 1491 rx_ring->next_to_clean = i;
1492 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1493
1494 if (cleaned_count)
fc77dc3c 1495 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1496
3d8fd385
YZ		 1497#ifdef IXGBE_FCOE
1498 /* include DDPed FCoE data */
1499 if (ddp_bytes > 0) {
1500 unsigned int mss;
1501
fc77dc3c 1502 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1503 sizeof(struct fc_frame_header) -
1504 sizeof(struct fcoe_crc_eof);
1505 if (mss > 512)
1506 mss &= ~511;
1507 total_rx_bytes += ddp_bytes;
1508 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1509 }
1510#endif /* IXGBE_FCOE */
1511
f494e8fa
AV		 1512 rx_ring->total_packets += total_rx_packets;
1513 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1514 u64_stats_update_begin(&rx_ring->syncp);
1515 rx_ring->stats.packets += total_rx_packets;
1516 rx_ring->stats.bytes += total_rx_bytes;
1517 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1518}
1519
021230d4 1520static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1521/**
1522 * ixgbe_configure_msix - Configure MSI-X hardware
1523 * @adapter: board private structure
1524 *
1525 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1526 * interrupts.
1527 **/
1528static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1529{
021230d4 1530 struct ixgbe_q_vector *q_vector;
bf29ee6c 1531 int i, q_vectors, v_idx, r_idx;
021230d4 1532 u32 mask;
9a799d71 1533
021230d4 1534 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1535
4df10466
JB		 1536 /*
1537 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1538 * corresponding register.
1539 */
1540 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1541 q_vector = adapter->q_vector[v_idx];
984b3f57 1542 /* XXX for_each_set_bit(...) */
021230d4 1543 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1544 adapter->num_rx_queues);
021230d4
AV		 1545
1546 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1547 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1548 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1549 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1550 adapter->num_rx_queues,
1551 r_idx + 1);
021230d4
AV		 1552 }
1553 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1554 adapter->num_tx_queues);
021230d4
AV		 1555
1556 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1557 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1558 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1559 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1560 adapter->num_tx_queues,
1561 r_idx + 1);
021230d4
AV		 1562 }
1563
021230d4 1564 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1565 /* tx only */
1566 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1567 else if (q_vector->rxr_count)
f7554a2b
NS		 1568 /* rx or mixed */
1569 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1570
fe49f04a 1571 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1572 /* If Flow Director is enabled, set interrupt affinity */
1573 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1574 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1575 /*
1576 * Allocate the affinity_hint cpumask, assign the mask
1577 * for this vector, and set our affinity_hint for
1578 * this irq.
1579 */
1580 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1581 GFP_KERNEL))
1582 return;
1583 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1584 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1585 q_vector->affinity_mask);
1586 }
9a799d71
AK		 1587 }
1588
bd508178
AD		 1589 switch (adapter->hw.mac.type) {
1590 case ixgbe_mac_82598EB:
e8e26350 1591 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1592 v_idx);
bd508178
AD		 1593 break;
1594 case ixgbe_mac_82599EB:
b93a2226 1595 case ixgbe_mac_X540:
e8e26350 1596 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1597 break;
1598
1599 default:
1600 break;
1601 }
021230d4
AV		 1602 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1603
41fb9248 1604 /* set up to autoclear timer, and the vectors */
021230d4 1605 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1606 if (adapter->num_vfs)
1607 mask &= ~(IXGBE_EIMS_OTHER |
1608 IXGBE_EIMS_MAILBOX |
1609 IXGBE_EIMS_LSC);
1610 else
1611 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1613}
1614
f494e8fa
AV		 1615enum latency_range {
1616 lowest_latency = 0,
1617 low_latency = 1,
1618 bulk_latency = 2,
1619 latency_invalid = 255
1620};
1621
1622/**
1623 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1624 * @adapter: pointer to adapter
1625 * @eitr: eitr setting (ints per sec) to give last timeslice
1626 * @itr_setting: current throttle rate in ints/second
1627 * @packets: the number of packets during this measurement interval
1628 * @bytes: the number of bytes during this measurement interval
1629 *
1630 * Stores a new ITR value based on packets and byte
1631 * counts during the last interrupt. The advantage of per interrupt
1632 * computation is faster updates and more accurate ITR for the current
1633 * traffic pattern. Constants in this function were computed
1634 * based on theoretical maximum wire speed and thresholds were set based
1635 * on testing data as well as attempting to minimize response time
1636 * while increasing bulk throughput.
1637 * this functionality is controlled by the InterruptThrottleRate module
1638 * parameter (see ixgbe_param.c)
1639 **/
1640static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1641 u32 eitr, u8 itr_setting,
1642 int packets, int bytes)
f494e8fa
AV		 1643{
1644 unsigned int retval = itr_setting;
1645 u32 timepassed_us;
1646 u64 bytes_perint;
1647
1648 if (packets == 0)
1649 goto update_itr_done;
1650
1651
1652 /* simple throttlerate management
1653 * 0-20MB/s lowest (100000 ints/s)
1654 * 20-100MB/s low (20000 ints/s)
1655 * 100-1249MB/s bulk (8000 ints/s)
1656 */
1657 /* what was last interrupt timeslice? */
1658 timepassed_us = 1000000/eitr;
1659 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1660
1661 switch (itr_setting) {
1662 case lowest_latency:
1663 if (bytes_perint > adapter->eitr_low)
1664 retval = low_latency;
1665 break;
1666 case low_latency:
1667 if (bytes_perint > adapter->eitr_high)
1668 retval = bulk_latency;
1669 else if (bytes_perint <= adapter->eitr_low)
1670 retval = lowest_latency;
1671 break;
1672 case bulk_latency:
1673 if (bytes_perint <= adapter->eitr_high)
1674 retval = low_latency;
1675 break;
1676 }
1677
1678update_itr_done:
1679 return retval;
1680}
1681
509ee935
JB		 1682/**
1683 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1684 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1685 *
1686 * This function is made to be called by ethtool and by the driver
1687 * when it needs to update EITR registers at runtime. Hardware
1688 * specific quirks/differences are taken care of here.
1689 */
fe49f04a 1690void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1691{
fe49f04a 1692 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1693 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1694 int v_idx = q_vector->v_idx;
1695 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1696
bd508178
AD		 1697 switch (adapter->hw.mac.type) {
1698 case ixgbe_mac_82598EB:
509ee935
JB		 1699 /* must write high and low 16 bits to reset counter */
1700 itr_reg |= (itr_reg << 16);
bd508178
AD		 1701 break;
1702 case ixgbe_mac_82599EB:
b93a2226 1703 case ixgbe_mac_X540:
f8d1dcaf 1704 /*
b93a2226 1705 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1706 * max interrupt rate, but there is an errata where it can
1707 * not be zero with RSC
1708 */
1709 if (itr_reg == 8 &&
1710 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1711 itr_reg = 0;
1712
509ee935
JB		 1713 /*
1714 * set the WDIS bit to not clear the timer bits and cause an
1715 * immediate assertion of the interrupt
1716 */
1717 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1718 break;
1719 default:
1720 break;
509ee935
JB		 1721 }
1722 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1723}
1724
f494e8fa
AV		 1725static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1726{
1727 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1728 int i, r_idx;
f494e8fa
AV		 1729 u32 new_itr;
1730 u8 current_itr, ret_itr;
f494e8fa
AV		 1731
1732 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1733 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1734 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1735 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1736 q_vector->tx_itr,
1737 tx_ring->total_packets,
1738 tx_ring->total_bytes);
f494e8fa
AV		 1739 /* if the result for this queue would decrease interrupt
1740 * rate for this vector then use that result */
30efa5a3 1741 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1742 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1743 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1744 r_idx + 1);
f494e8fa
AV		 1745 }
1746
1747 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1748 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1749 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1750 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1751 q_vector->rx_itr,
1752 rx_ring->total_packets,
1753 rx_ring->total_bytes);
f494e8fa
AV		 1754 /* if the result for this queue would decrease interrupt
1755 * rate for this vector then use that result */
30efa5a3 1756 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1757 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1758 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1759 r_idx + 1);
f494e8fa
AV		 1760 }
1761
30efa5a3 1762 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1763
1764 switch (current_itr) {
1765 /* counts and packets in update_itr are dependent on these numbers */
1766 case lowest_latency:
1767 new_itr = 100000;
1768 break;
1769 case low_latency:
1770 new_itr = 20000; /* aka hwitr = ~200 */
1771 break;
1772 case bulk_latency:
1773 default:
1774 new_itr = 8000;
1775 break;
1776 }
1777
1778 if (new_itr != q_vector->eitr) {
fe49f04a 1779 /* do an exponential smoothing */
125601bf 1780 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1781
1782 /* save the algorithm value here, not the smoothed one */
1783 q_vector->eitr = new_itr;
fe49f04a
AD		 1784
1785 ixgbe_write_eitr(q_vector);
f494e8fa 1786 }
f494e8fa
AV		 1787}
1788
119fc60a
MC		 1789/**
1790 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1791 * @work: pointer to work_struct containing our data
1792 **/
1793static void ixgbe_check_overtemp_task(struct work_struct *work)
1794{
1795 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1796 struct ixgbe_adapter,
1797 check_overtemp_task);
119fc60a
MC		 1798 struct ixgbe_hw *hw = &adapter->hw;
1799 u32 eicr = adapter->interrupt_event;
1800
7ca647bd
JP		 1801 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1802 return;
1803
1804 switch (hw->device_id) {
1805 case IXGBE_DEV_ID_82599_T3_LOM: {
1806 u32 autoneg;
1807 bool link_up = false;
1808
1809 if (hw->mac.ops.check_link)
1810 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1811
1812 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1813 (eicr & IXGBE_EICR_LSC))
1814 /* Check if this is due to overtemp */
1815 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1816 break;
1817 return;
1818 }
1819 default:
1820 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1821 return;
7ca647bd 1822 break;
119fc60a 1823 }
7ca647bd
JP		 1824 e_crit(drv,
1825 "Network adapter has been stopped because it has over heated. "
1826 "Restart the computer. If the problem persists, "
1827 "power off the system and replace the adapter\n");
1828 /* write to clear the interrupt */
1829 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1830}
1831
0befdb3e
JB		 1832static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1833{
1834 struct ixgbe_hw *hw = &adapter->hw;
1835
1836 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1837 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1838 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1839 /* write to clear the interrupt */
1840 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1841 }
1842}
cf8280ee 1843
e8e26350
PW		 1844static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1845{
1846 struct ixgbe_hw *hw = &adapter->hw;
1847
73c4b7cd
AD		 1848 if (eicr & IXGBE_EICR_GPI_SDP2) {
1849 /* Clear the interrupt */
1850 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1851 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1852 schedule_work(&adapter->sfp_config_module_task);
1853 }
1854
e8e26350
PW		 1855 if (eicr & IXGBE_EICR_GPI_SDP1) {
1856 /* Clear the interrupt */
1857 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
73c4b7cd
AD		 1858 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1859 schedule_work(&adapter->multispeed_fiber_task);
e8e26350
PW		 1860 }
1861}
1862
cf8280ee
JB		 1863static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1864{
1865 struct ixgbe_hw *hw = &adapter->hw;
1866
1867 adapter->lsc_int++;
1868 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1869 adapter->link_check_timeout = jiffies;
1870 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1871 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1872 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1873 schedule_work(&adapter->watchdog_task);
1874 }
1875}
1876
9a799d71
AK		 1877static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1878{
1879 struct net_device *netdev = data;
1880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1881 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1882 u32 eicr;
1883
1884 /*
1885 * Workaround for Silicon errata. Use clear-by-write instead
1886 * of clear-by-read. Reading with EICS will return the
1887 * interrupt causes without clearing, which later be done
1888 * with the write to EICR.
1889 */
1890 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1891 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1892
cf8280ee
JB		 1893 if (eicr & IXGBE_EICR_LSC)
1894 ixgbe_check_lsc(adapter);
d4f80882 1895
1cdd1ec8
GR		 1896 if (eicr & IXGBE_EICR_MAILBOX)
1897 ixgbe_msg_task(adapter);
1898
bd508178
AD		 1899 switch (hw->mac.type) {
1900 case ixgbe_mac_82599EB:
d994653d
DS		 1901 ixgbe_check_sfp_event(adapter, eicr);
1902 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1903 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1904 adapter->interrupt_event = eicr;
1905 schedule_work(&adapter->check_overtemp_task);
1906 }
1907 /* now fallthrough to handle Flow Director */
b93a2226 1908 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1909 /* Handle Flow Director Full threshold interrupt */
1910 if (eicr & IXGBE_EICR_FLOW_DIR) {
1911 int i;
1912 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1913 /* Disable transmits before FDIR Re-initialization */
1914 netif_tx_stop_all_queues(netdev);
1915 for (i = 0; i < adapter->num_tx_queues; i++) {
1916 struct ixgbe_ring *tx_ring =
e8e9f696 1917 adapter->tx_ring[i];
7d637bcc
AD		 1918 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1919 &tx_ring->state))
c4cf55e5
PWJ		 1920 schedule_work(&adapter->fdir_reinit_task);
1921 }
1922 }
bd508178
AD		 1923 break;
1924 default:
1925 break;
c4cf55e5 1926 }
bd508178
AD		 1927
1928 ixgbe_check_fan_failure(adapter, eicr);
1929
d4f80882
AV		 1930 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1931 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1932
1933 return IRQ_HANDLED;
1934}
1935
fe49f04a
AD		 1936static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1937 u64 qmask)
1938{
1939 u32 mask;
bd508178 1940 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1941
bd508178
AD		 1942 switch (hw->mac.type) {
1943 case ixgbe_mac_82598EB:
fe49f04a 1944 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1945 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1946 break;
1947 case ixgbe_mac_82599EB:
b93a2226 1948 case ixgbe_mac_X540:
fe49f04a 1949 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1950 if (mask)
1951 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1952 mask = (qmask >> 32);
bd508178
AD		 1953 if (mask)
1954 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1955 break;
1956 default:
1957 break;
fe49f04a
AD		 1958 }
1959 /* skip the flush */
1960}
1961
1962static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1963 u64 qmask)
fe49f04a
AD		 1964{
1965 u32 mask;
bd508178 1966 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1967
bd508178
AD		 1968 switch (hw->mac.type) {
1969 case ixgbe_mac_82598EB:
fe49f04a 1970 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1971 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1972 break;
1973 case ixgbe_mac_82599EB:
b93a2226 1974 case ixgbe_mac_X540:
fe49f04a 1975 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1976 if (mask)
1977 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1978 mask = (qmask >> 32);
bd508178
AD		 1979 if (mask)
1980 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1981 break;
1982 default:
1983 break;
fe49f04a
AD		 1984 }
1985 /* skip the flush */
1986}
1987
9a799d71
AK		 1988static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1989{
021230d4
AV		 1990 struct ixgbe_q_vector *q_vector = data;
1991 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1992 struct ixgbe_ring *tx_ring;
021230d4
AV		 1993 int i, r_idx;
1994
1995 if (!q_vector->txr_count)
1996 return IRQ_HANDLED;
1997
1998 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1999 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2000 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 2001 tx_ring->total_bytes = 0;
2002 tx_ring->total_packets = 0;
021230d4 2003 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2004 r_idx + 1);
021230d4 2005 }
9a799d71 2006
9b471446 2007 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2008 napi_schedule(&q_vector->napi);
2009
9a799d71
AK		 2010 return IRQ_HANDLED;
2011}
2012
021230d4
AV		 2013/**
2014 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2015 * @irq: unused
2016 * @data: pointer to our q_vector struct for this interrupt vector
2017 **/
9a799d71
AK		 2018static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2019{
021230d4
AV		 2020 struct ixgbe_q_vector *q_vector = data;
2021 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2022 struct ixgbe_ring *rx_ring;
021230d4 2023 int r_idx;
30efa5a3 2024 int i;
021230d4 2025
33cf09c9
AD		 2026#ifdef CONFIG_IXGBE_DCA
2027 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2028 ixgbe_update_dca(q_vector);
2029#endif
2030
021230d4 2031 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2032 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2033 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2034 rx_ring->total_bytes = 0;
2035 rx_ring->total_packets = 0;
2036 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2037 r_idx + 1);
30efa5a3
JB		 2038 }
2039
021230d4
AV		 2040 if (!q_vector->rxr_count)
2041 return IRQ_HANDLED;
2042
9b471446 2043 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2044 napi_schedule(&q_vector->napi);
021230d4
AV		 2045
2046 return IRQ_HANDLED;
2047}
2048
2049static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2050{
91281fd3
AD		 2051 struct ixgbe_q_vector *q_vector = data;
2052 struct ixgbe_adapter *adapter = q_vector->adapter;
2053 struct ixgbe_ring *ring;
2054 int r_idx;
2055 int i;
2056
2057 if (!q_vector->txr_count && !q_vector->rxr_count)
2058 return IRQ_HANDLED;
2059
2060 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2061 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2062 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2063 ring->total_bytes = 0;
2064 ring->total_packets = 0;
2065 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2066 r_idx + 1);
91281fd3
AD		 2067 }
2068
2069 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2070 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2071 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2072 ring->total_bytes = 0;
2073 ring->total_packets = 0;
2074 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2075 r_idx + 1);
91281fd3
AD		 2076 }
2077
9b471446 2078 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2079 napi_schedule(&q_vector->napi);
9a799d71 2080
9a799d71
AK		 2081 return IRQ_HANDLED;
2082}
2083
021230d4
AV		 2084/**
2085 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2086 * @napi: napi struct with our devices info in it
2087 * @budget: amount of work driver is allowed to do this pass, in packets
2088 *
f0848276
JB		 2089 * This function is optimized for cleaning one queue only on a single
2090 * q_vector!!!
021230d4 2091 **/
9a799d71
AK		 2092static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2093{
021230d4 2094 struct ixgbe_q_vector *q_vector =
e8e9f696 2095 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2096 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2097 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2098 int work_done = 0;
021230d4 2099 long r_idx;
9a799d71 2100
5dd2d332 2101#ifdef CONFIG_IXGBE_DCA
bd0362dd 2102 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2103 ixgbe_update_dca(q_vector);
bd0362dd 2104#endif
9a799d71 2105
33cf09c9
AD		 2106 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2107 rx_ring = adapter->rx_ring[r_idx];
2108
78b6f4ce 2109 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2110
021230d4
AV		 2111 /* If all Rx work done, exit the polling mode */
2112 if (work_done < budget) {
288379f0 2113 napi_complete(napi);
f7554a2b 2114 if (adapter->rx_itr_setting & 1)
f494e8fa 2115 ixgbe_set_itr_msix(q_vector);
9a799d71 2116 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2117 ixgbe_irq_enable_queues(adapter,
e8e9f696 2118 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2119 }
2120
2121 return work_done;
2122}
2123
f0848276 2124/**
91281fd3 2125 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2126 * @napi: napi struct with our devices info in it
2127 * @budget: amount of work driver is allowed to do this pass, in packets
2128 *
2129 * This function will clean more than one rx queue associated with a
2130 * q_vector.
2131 **/
91281fd3 2132static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2133{
2134 struct ixgbe_q_vector *q_vector =
e8e9f696 2135 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2136 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2137 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2138 int work_done = 0, i;
2139 long r_idx;
91281fd3
AD		 2140 bool tx_clean_complete = true;
2141
33cf09c9
AD		 2142#ifdef CONFIG_IXGBE_DCA
2143 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2144 ixgbe_update_dca(q_vector);
2145#endif
2146
91281fd3
AD		 2147 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2148 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2149 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2150 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2151 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2152 r_idx + 1);
91281fd3 2153 }
f0848276
JB		 2154
2155 /* attempt to distribute budget to each queue fairly, but don't allow
2156 * the budget to go below 1 because we'll exit polling */
2157 budget /= (q_vector->rxr_count ?: 1);
2158 budget = max(budget, 1);
2159 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2160 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2161 ring = adapter->rx_ring[r_idx];
91281fd3 2162 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2163 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2164 r_idx + 1);
f0848276
JB		 2165 }
2166
2167 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2168 ring = adapter->rx_ring[r_idx];
f0848276 2169 /* If all Rx work done, exit the polling mode */
7f821875 2170 if (work_done < budget) {
288379f0 2171 napi_complete(napi);
f7554a2b 2172 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2173 ixgbe_set_itr_msix(q_vector);
2174 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2175 ixgbe_irq_enable_queues(adapter,
e8e9f696 2176 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2177 return 0;
2178 }
2179
2180 return work_done;
2181}
91281fd3
AD		 2182
2183/**
2184 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2185 * @napi: napi struct with our devices info in it
2186 * @budget: amount of work driver is allowed to do this pass, in packets
2187 *
2188 * This function is optimized for cleaning one queue only on a single
2189 * q_vector!!!
2190 **/
2191static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2192{
2193 struct ixgbe_q_vector *q_vector =
e8e9f696 2194 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2195 struct ixgbe_adapter *adapter = q_vector->adapter;
2196 struct ixgbe_ring *tx_ring = NULL;
2197 int work_done = 0;
2198 long r_idx;
2199
91281fd3
AD		 2200#ifdef CONFIG_IXGBE_DCA
2201 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2202 ixgbe_update_dca(q_vector);
91281fd3
AD		 2203#endif
2204
33cf09c9
AD		 2205 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2206 tx_ring = adapter->tx_ring[r_idx];
2207
91281fd3
AD		 2208 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2209 work_done = budget;
2210
f7554a2b 2211 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2212 if (work_done < budget) {
2213 napi_complete(napi);
f7554a2b 2214 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2215 ixgbe_set_itr_msix(q_vector);
2216 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2217 ixgbe_irq_enable_queues(adapter,
2218 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2219 }
2220
2221 return work_done;
2222}
2223
021230d4 2224static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2225 int r_idx)
021230d4 2226{
7a921c93 2227 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2228 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2229
2230 set_bit(r_idx, q_vector->rxr_idx);
2231 q_vector->rxr_count++;
2274543f 2232 rx_ring->q_vector = q_vector;
021230d4
AV		 2233}
2234
2235static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2236 int t_idx)
021230d4 2237{
7a921c93 2238 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2239 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2240
2241 set_bit(t_idx, q_vector->txr_idx);
2242 q_vector->txr_count++;
2274543f 2243 tx_ring->q_vector = q_vector;
021230d4
AV		 2244}
2245
9a799d71 2246/**
021230d4
AV		 2247 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2248 * @adapter: board private structure to initialize
9a799d71 2249 *
021230d4
AV		 2250 * This function maps descriptor rings to the queue-specific vectors
2251 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2252 * one vector per ring/queue, but on a constrained vector budget, we
2253 * group the rings as "efficiently" as possible. You would add new
2254 * mapping configurations in here.
9a799d71 2255 **/
d0759ebb 2256static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2257{
d0759ebb 2258 int q_vectors;
021230d4
AV		 2259 int v_start = 0;
2260 int rxr_idx = 0, txr_idx = 0;
2261 int rxr_remaining = adapter->num_rx_queues;
2262 int txr_remaining = adapter->num_tx_queues;
2263 int i, j;
2264 int rqpv, tqpv;
2265 int err = 0;
2266
2267 /* No mapping required if MSI-X is disabled. */
2268 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2269 goto out;
9a799d71 2270
d0759ebb
AD		 2271 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2272
021230d4
AV		 2273 /*
2274 * The ideal configuration...
2275 * We have enough vectors to map one per queue.
2276 */
d0759ebb 2277 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2278 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2279 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2280
021230d4
AV		 2281 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2282 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2283
9a799d71 2284 goto out;
021230d4 2285 }
9a799d71 2286
021230d4
AV		 2287 /*
2288 * If we don't have enough vectors for a 1-to-1
2289 * mapping, we'll have to group them so there are
2290 * multiple queues per vector.
2291 */
2292 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2293 for (i = v_start; i < q_vectors; i++) {
2294 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2295 for (j = 0; j < rqpv; j++) {
2296 map_vector_to_rxq(adapter, i, rxr_idx);
2297 rxr_idx++;
2298 rxr_remaining--;
2299 }
d0759ebb 2300 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2301 for (j = 0; j < tqpv; j++) {
2302 map_vector_to_txq(adapter, i, txr_idx);
2303 txr_idx++;
2304 txr_remaining--;
9a799d71 2305 }
9a799d71 2306 }
021230d4
AV		 2307out:
2308 return err;
2309}
2310
2311/**
2312 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2313 * @adapter: board private structure
2314 *
2315 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2316 * interrupts from the kernel.
2317 **/
2318static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2319{
2320 struct net_device *netdev = adapter->netdev;
2321 irqreturn_t (*handler)(int, void *);
2322 int i, vector, q_vectors, err;
e8e9f696 2323 int ri = 0, ti = 0;
021230d4
AV		 2324
2325 /* Decrement for Other and TCP Timer vectors */
2326 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2327
d0759ebb 2328 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2329 if (err)
d0759ebb 2330 return err;
021230d4 2331
d0759ebb
AD		 2332#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2333 ? &ixgbe_msix_clean_many : \
2334 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2335 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2336 NULL)
021230d4 2337 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2338 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2339 handler = SET_HANDLER(q_vector);
cb13fc20 2340
e8e9f696 2341 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2342 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2343 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2344 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2345 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2346 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2347 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2348 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2349 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2350 ti++;
d0759ebb
AD		 2351 } else {
2352 /* skip this unused q_vector */
2353 continue;
32aa77a4 2354 }
021230d4 2355 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2356 handler, 0, q_vector->name,
2357 q_vector);
9a799d71 2358 if (err) {
396e799c 2359 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2360 "Error: %d\n", err);
021230d4 2361 goto free_queue_irqs;
9a799d71 2362 }
9a799d71
AK		 2363 }
2364
d0759ebb 2365 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2366 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb 2367 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
9a799d71 2368 if (err) {
396e799c 2369 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2370 goto free_queue_irqs;
9a799d71
AK		 2371 }
2372
9a799d71
AK		 2373 return 0;
2374
021230d4
AV		 2375free_queue_irqs:
2376 for (i = vector - 1; i >= 0; i--)
2377 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2378 adapter->q_vector[i]);
021230d4
AV		 2379 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2380 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2381 kfree(adapter->msix_entries);
2382 adapter->msix_entries = NULL;
9a799d71
AK		 2383 return err;
2384}
2385
f494e8fa
AV		 2386static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2387{
7a921c93 2388 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2389 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2390 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2391 u32 new_itr = q_vector->eitr;
2392 u8 current_itr;
f494e8fa 2393
30efa5a3 2394 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2395 q_vector->tx_itr,
2396 tx_ring->total_packets,
2397 tx_ring->total_bytes);
30efa5a3 2398 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2399 q_vector->rx_itr,
2400 rx_ring->total_packets,
2401 rx_ring->total_bytes);
f494e8fa 2402
30efa5a3 2403 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2404
2405 switch (current_itr) {
2406 /* counts and packets in update_itr are dependent on these numbers */
2407 case lowest_latency:
2408 new_itr = 100000;
2409 break;
2410 case low_latency:
2411 new_itr = 20000; /* aka hwitr = ~200 */
2412 break;
2413 case bulk_latency:
2414 new_itr = 8000;
2415 break;
2416 default:
2417 break;
2418 }
2419
2420 if (new_itr != q_vector->eitr) {
fe49f04a 2421 /* do an exponential smoothing */
125601bf 2422 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2423
125601bf 2424 /* save the algorithm value here */
509ee935 2425 q_vector->eitr = new_itr;
fe49f04a
AD		 2426
2427 ixgbe_write_eitr(q_vector);
f494e8fa 2428 }
f494e8fa
AV		 2429}
2430
79aefa45
AD		 2431/**
2432 * ixgbe_irq_enable - Enable default interrupt generation settings
2433 * @adapter: board private structure
2434 **/
6af3b9eb
ET		 2435static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2436 bool flush)
79aefa45
AD		 2437{
2438 u32 mask;
835462fc
NS		 2439
2440 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2441 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2442 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2443 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2444 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2445 switch (adapter->hw.mac.type) {
2446 case ixgbe_mac_82599EB:
b93a2226 2447 case ixgbe_mac_X540:
2a41ff81 2448 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2449 mask |= IXGBE_EIMS_GPI_SDP1;
2450 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2451 if (adapter->num_vfs)
2452 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2453 break;
2454 default:
2455 break;
e8e26350 2456 }
c4cf55e5
PWJ		 2457 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2458 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2459 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2460
79aefa45 2461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2462 if (queues)
2463 ixgbe_irq_enable_queues(adapter, ~0);
2464 if (flush)
2465 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2466
2467 if (adapter->num_vfs > 32) {
2468 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2469 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2470 }
79aefa45 2471}
021230d4 2472
9a799d71 2473/**
021230d4 2474 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2475 * @irq: interrupt number
2476 * @data: pointer to a network interface device structure
9a799d71
AK		 2477 **/
2478static irqreturn_t ixgbe_intr(int irq, void *data)
2479{
2480 struct net_device *netdev = data;
2481 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2482 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2483 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2484 u32 eicr;
2485
54037505 2486 /*
6af3b9eb 2487 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2488 * before the read of EICR.
2489 */
2490 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2491
021230d4
AV		 2492 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2493 * therefore no explict interrupt disable is necessary */
2494 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2495 if (!eicr) {
6af3b9eb
ET		 2496 /*
2497 * shared interrupt alert!
f47cf66e 2498 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2499 * have disabled interrupts due to EIAM
2500 * finish the workaround of silicon errata on 82598. Unmask
2501 * the interrupt that we masked before the EICR read.
2502 */
2503 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2504 ixgbe_irq_enable(adapter, true, true);
9a799d71 2505 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2506 }
9a799d71 2507
cf8280ee
JB		 2508 if (eicr & IXGBE_EICR_LSC)
2509 ixgbe_check_lsc(adapter);
021230d4 2510
bd508178
AD		 2511 switch (hw->mac.type) {
2512 case ixgbe_mac_82599EB:
e8e26350 2513 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2514 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2515 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2516 adapter->interrupt_event = eicr;
2517 schedule_work(&adapter->check_overtemp_task);
2518 }
2519 break;
2520 default:
2521 break;
2522 }
e8e26350 2523
0befdb3e
JB		 2524 ixgbe_check_fan_failure(adapter, eicr);
2525
7a921c93 2526 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2527 adapter->tx_ring[0]->total_packets = 0;
2528 adapter->tx_ring[0]->total_bytes = 0;
2529 adapter->rx_ring[0]->total_packets = 0;
2530 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2531 /* would disable interrupts here but EIAM disabled it */
7a921c93 2532 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2533 }
2534
6af3b9eb
ET		 2535 /*
2536 * re-enable link(maybe) and non-queue interrupts, no flush.
2537 * ixgbe_poll will re-enable the queue interrupts
2538 */
2539
2540 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2541 ixgbe_irq_enable(adapter, false, false);
2542
9a799d71
AK		 2543 return IRQ_HANDLED;
2544}
2545
021230d4
AV		 2546static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2547{
2548 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2549
2550 for (i = 0; i < q_vectors; i++) {
7a921c93 2551 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2552 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2553 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2554 q_vector->rxr_count = 0;
2555 q_vector->txr_count = 0;
2556 }
2557}
2558
9a799d71
AK		 2559/**
2560 * ixgbe_request_irq - initialize interrupts
2561 * @adapter: board private structure
2562 *
2563 * Attempts to configure interrupts using the best available
2564 * capabilities of the hardware and kernel.
2565 **/
021230d4 2566static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2567{
2568 struct net_device *netdev = adapter->netdev;
021230d4 2569 int err;
9a799d71 2570
021230d4
AV		 2571 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2572 err = ixgbe_request_msix_irqs(adapter);
2573 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2574 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2575 netdev->name, netdev);
021230d4 2576 } else {
a0607fd3 2577 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2578 netdev->name, netdev);
9a799d71
AK		 2579 }
2580
9a799d71 2581 if (err)
396e799c 2582 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2583
9a799d71
AK		 2584 return err;
2585}
2586
2587static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2588{
2589 struct net_device *netdev = adapter->netdev;
2590
2591 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2592 int i, q_vectors;
9a799d71 2593
021230d4
AV		 2594 q_vectors = adapter->num_msix_vectors;
2595
2596 i = q_vectors - 1;
9a799d71 2597 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2598
021230d4
AV		 2599 i--;
2600 for (; i >= 0; i--) {
894ff7cf
AD		 2601 /* free only the irqs that were actually requested */
2602 if (!adapter->q_vector[i]->rxr_count &&
2603 !adapter->q_vector[i]->txr_count)
2604 continue;
2605
021230d4 2606 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2607 adapter->q_vector[i]);
021230d4
AV		 2608 }
2609
2610 ixgbe_reset_q_vectors(adapter);
2611 } else {
2612 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2613 }
2614}
2615
22d5a71b
JB		 2616/**
2617 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2618 * @adapter: board private structure
2619 **/
2620static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2621{
bd508178
AD		 2622 switch (adapter->hw.mac.type) {
2623 case ixgbe_mac_82598EB:
835462fc 2624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2625 break;
2626 case ixgbe_mac_82599EB:
b93a2226 2627 case ixgbe_mac_X540:
835462fc
NS		 2628 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2631 if (adapter->num_vfs > 32)
2632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2633 break;
2634 default:
2635 break;
22d5a71b
JB		 2636 }
2637 IXGBE_WRITE_FLUSH(&adapter->hw);
2638 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2639 int i;
2640 for (i = 0; i < adapter->num_msix_vectors; i++)
2641 synchronize_irq(adapter->msix_entries[i].vector);
2642 } else {
2643 synchronize_irq(adapter->pdev->irq);
2644 }
2645}
2646
9a799d71
AK		 2647/**
2648 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2649 *
2650 **/
2651static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2652{
9a799d71
AK		 2653 struct ixgbe_hw *hw = &adapter->hw;
2654
021230d4 2655 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2656 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2657
e8e26350
PW		 2658 ixgbe_set_ivar(adapter, 0, 0, 0);
2659 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2660
2661 map_vector_to_rxq(adapter, 0, 0);
2662 map_vector_to_txq(adapter, 0, 0);
2663
396e799c 2664 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2665}
2666
43e69bf0
AD		 2667/**
2668 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2669 * @adapter: board private structure
2670 * @ring: structure containing ring specific data
2671 *
2672 * Configure the Tx descriptor ring after a reset.
2673 **/
84418e3b
AD		 2674void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2675 struct ixgbe_ring *ring)
43e69bf0
AD		 2676{
2677 struct ixgbe_hw *hw = &adapter->hw;
2678 u64 tdba = ring->dma;
2f1860b8
AD		 2679 int wait_loop = 10;
2680 u32 txdctl;
bf29ee6c 2681 u8 reg_idx = ring->reg_idx;
43e69bf0 2682
2f1860b8
AD		 2683 /* disable queue to avoid issues while updating state */
2684 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2685 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2686 txdctl & ~IXGBE_TXDCTL_ENABLE);
2687 IXGBE_WRITE_FLUSH(hw);
2688
43e69bf0 2689 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2690 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2691 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2692 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2693 ring->count * sizeof(union ixgbe_adv_tx_desc));
2694 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2695 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2696 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2697
2f1860b8
AD		 2698 /* configure fetching thresholds */
2699 if (adapter->rx_itr_setting == 0) {
2700 /* cannot set wthresh when itr==0 */
2701 txdctl &= ~0x007F0000;
2702 } else {
2703 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2704 txdctl |= (8 << 16);
2705 }
2706 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2707 /* PThresh workaround for Tx hang with DFP enabled. */
2708 txdctl |= 32;
2709 }
2710
2711 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2712 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2713 adapter->atr_sample_rate) {
2714 ring->atr_sample_rate = adapter->atr_sample_rate;
2715 ring->atr_count = 0;
2716 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2717 } else {
2718 ring->atr_sample_rate = 0;
2719 }
2f1860b8 2720
c84d324c
JF		 2721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2722
2f1860b8
AD		 2723 /* enable queue */
2724 txdctl |= IXGBE_TXDCTL_ENABLE;
2725 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2726
2727 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2728 if (hw->mac.type == ixgbe_mac_82598EB &&
2729 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2730 return;
2731
2732 /* poll to verify queue is enabled */
2733 do {
2734 msleep(1);
2735 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2736 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2737 if (!wait_loop)
2738 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2739}
2740
120ff942
AD		 2741static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2742{
2743 struct ixgbe_hw *hw = &adapter->hw;
2744 u32 rttdcs;
2745 u32 mask;
2746
2747 if (hw->mac.type == ixgbe_mac_82598EB)
2748 return;
2749
2750 /* disable the arbiter while setting MTQC */
2751 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2752 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2753 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2754
2755 /* set transmit pool layout */
2756 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2757 switch (adapter->flags & mask) {
2758
2759 case (IXGBE_FLAG_SRIOV_ENABLED):
2760 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2762 break;
2763
2764 case (IXGBE_FLAG_DCB_ENABLED):
2765 /* We enable 8 traffic classes, DCB only */
2766 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2767 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2768 break;
2769
2770 default:
2771 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2772 break;
2773 }
2774
2775 /* re-enable the arbiter */
2776 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2777 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2778}
2779
9a799d71 2780/**
3a581073 2781 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2782 * @adapter: board private structure
2783 *
2784 * Configure the Tx unit of the MAC after a reset.
2785 **/
2786static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2787{
2f1860b8
AD		 2788 struct ixgbe_hw *hw = &adapter->hw;
2789 u32 dmatxctl;
43e69bf0 2790 u32 i;
9a799d71 2791
2f1860b8
AD		 2792 ixgbe_setup_mtqc(adapter);
2793
2794 if (hw->mac.type != ixgbe_mac_82598EB) {
2795 /* DMATXCTL.EN must be before Tx queues are enabled */
2796 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2797 dmatxctl |= IXGBE_DMATXCTL_TE;
2798 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2799 }
2800
9a799d71 2801 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2802 for (i = 0; i < adapter->num_tx_queues; i++)
2803 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2804}
2805
e8e26350 2806#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2807
a6616b42 2808static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2809 struct ixgbe_ring *rx_ring)
cc41ac7c 2810{
cc41ac7c 2811 u32 srrctl;
bf29ee6c 2812 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2813
bd508178
AD		 2814 switch (adapter->hw.mac.type) {
2815 case ixgbe_mac_82598EB: {
2816 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2817 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2818 reg_idx = reg_idx & mask;
cc41ac7c 2819 }
bd508178
AD		 2820 break;
2821 case ixgbe_mac_82599EB:
b93a2226 2822 case ixgbe_mac_X540:
bd508178
AD		 2823 default:
2824 break;
2825 }
2826
bf29ee6c 2827 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2828
2829 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2830 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2831 if (adapter->num_vfs)
2832 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2833
afafd5b0
AD		 2834 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2835 IXGBE_SRRCTL_BSIZEHDR_MASK;
2836
7d637bcc 2837 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2838#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2839 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2840#else
2841 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2842#endif
cc41ac7c 2843 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2844 } else {
afafd5b0
AD		 2845 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2846 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2847 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2848 }
e8e26350 2849
bf29ee6c 2850 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2851}
9a799d71 2852
05abb126 2853static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2854{
05abb126
AD		 2855 struct ixgbe_hw *hw = &adapter->hw;
2856 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2857 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2858 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2859 u32 mrqc = 0, reta = 0;
2860 u32 rxcsum;
2861 int i, j;
0cefafad
JB		 2862 int mask;
2863
05abb126
AD		 2864 /* Fill out hash function seeds */
2865 for (i = 0; i < 10; i++)
2866 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2867
2868 /* Fill out redirection table */
2869 for (i = 0, j = 0; i < 128; i++, j++) {
2870 if (j == adapter->ring_feature[RING_F_RSS].indices)
2871 j = 0;
2872 /* reta = 4-byte sliding window of
2873 * 0x00..(indices-1)(indices-1)00..etc. */
2874 reta = (reta << 8) | (j * 0x11);
2875 if ((i & 3) == 3)
2876 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2877 }
0cefafad 2878
05abb126
AD		 2879 /* Disable indicating checksum in descriptor, enables RSS hash */
2880 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2881 rxcsum |= IXGBE_RXCSUM_PCSD;
2882 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2883
2884 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2885 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2886 else
2887 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2888#ifdef CONFIG_IXGBE_DCB
05abb126 2889 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2890#endif
05abb126
AD		 2891 | IXGBE_FLAG_SRIOV_ENABLED
2892 );
0cefafad
JB		 2893
2894 switch (mask) {
8187cd48
JF		 2895#ifdef CONFIG_IXGBE_DCB
2896 case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2897 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2898 break;
2899 case (IXGBE_FLAG_DCB_ENABLED):
2900 mrqc = IXGBE_MRQC_RT8TCEN;
2901 break;
2902#endif /* CONFIG_IXGBE_DCB */
0cefafad
JB		 2903 case (IXGBE_FLAG_RSS_ENABLED):
2904 mrqc = IXGBE_MRQC_RSSEN;
2905 break;
1cdd1ec8
GR		 2906 case (IXGBE_FLAG_SRIOV_ENABLED):
2907 mrqc = IXGBE_MRQC_VMDQEN;
2908 break;
0cefafad
JB		 2909 default:
2910 break;
2911 }
2912
05abb126
AD		 2913 /* Perform hash on these packet types */
2914 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2915 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2916 | IXGBE_MRQC_RSS_FIELD_IPV6
2917 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2918
2919 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2920}
2921
b93a2226
DS		 2922/**
2923 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2924 * @adapter: address of board private structure
2925 * @ring: structure containing ring specific data
2926 **/
2927void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2928 struct ixgbe_ring *ring)
2929{
2930 struct ixgbe_hw *hw = &adapter->hw;
2931 u32 rscctrl;
2932 u8 reg_idx = ring->reg_idx;
2933
2934 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2935 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2936 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2937}
2938
bb5a9ad2
NS		 2939/**
2940 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2941 * @adapter: address of board private structure
2942 * @index: index of ring to set
bb5a9ad2 2943 **/
b93a2226 2944void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2945 struct ixgbe_ring *ring)
bb5a9ad2 2946{
bb5a9ad2 2947 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2948 u32 rscctrl;
edd2ea55 2949 int rx_buf_len;
bf29ee6c 2950 u8 reg_idx = ring->reg_idx;
7367096a 2951
7d637bcc 2952 if (!ring_is_rsc_enabled(ring))
7367096a 2953 return;
bb5a9ad2 2954
7367096a
AD		 2955 rx_buf_len = ring->rx_buf_len;
2956 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2957 rscctrl |= IXGBE_RSCCTL_RSCEN;
2958 /*
2959 * we must limit the number of descriptors so that the
2960 * total size of max desc * buf_len is not greater
2961 * than 65535
2962 */
7d637bcc 2963 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2964#if (MAX_SKB_FRAGS > 16)
2965 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2966#elif (MAX_SKB_FRAGS > 8)
2967 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2968#elif (MAX_SKB_FRAGS > 4)
2969 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2970#else
2971 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2972#endif
2973 } else {
2974 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2975 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2976 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2977 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2978 else
2979 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2980 }
7367096a 2981 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2982}
2983
9e10e045
AD		 2984/**
2985 * ixgbe_set_uta - Set unicast filter table address
2986 * @adapter: board private structure
2987 *
2988 * The unicast table address is a register array of 32-bit registers.
2989 * The table is meant to be used in a way similar to how the MTA is used
2990 * however due to certain limitations in the hardware it is necessary to
2991 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2992 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2993 **/
2994static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2995{
2996 struct ixgbe_hw *hw = &adapter->hw;
2997 int i;
2998
2999 /* The UTA table only exists on 82599 hardware and newer */
3000 if (hw->mac.type < ixgbe_mac_82599EB)
3001 return;
3002
3003 /* we only need to do this if VMDq is enabled */
3004 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3005 return;
3006
3007 for (i = 0; i < 128; i++)
3008 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3009}
3010
3011#define IXGBE_MAX_RX_DESC_POLL 10
3012static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3013 struct ixgbe_ring *ring)
3014{
3015 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3016 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3017 u32 rxdctl;
bf29ee6c 3018 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3019
3020 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3021 if (hw->mac.type == ixgbe_mac_82598EB &&
3022 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3023 return;
3024
3025 do {
3026 msleep(1);
3027 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3028 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3029
3030 if (!wait_loop) {
3031 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3032 "the polling period\n", reg_idx);
3033 }
3034}
3035
2d39d576
YZ		 3036void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3037 struct ixgbe_ring *ring)
3038{
3039 struct ixgbe_hw *hw = &adapter->hw;
3040 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3041 u32 rxdctl;
3042 u8 reg_idx = ring->reg_idx;
3043
3044 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3045 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3046
3047 /* write value back with RXDCTL.ENABLE bit cleared */
3048 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3049
3050 if (hw->mac.type == ixgbe_mac_82598EB &&
3051 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3052 return;
3053
3054 /* the hardware may take up to 100us to really disable the rx queue */
3055 do {
3056 udelay(10);
3057 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3058 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3059
3060 if (!wait_loop) {
3061 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3062 "the polling period\n", reg_idx);
3063 }
3064}
3065
84418e3b
AD		 3066void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3067 struct ixgbe_ring *ring)
acd37177
AD		 3068{
3069 struct ixgbe_hw *hw = &adapter->hw;
3070 u64 rdba = ring->dma;
9e10e045 3071 u32 rxdctl;
bf29ee6c 3072 u8 reg_idx = ring->reg_idx;
acd37177 3073
9e10e045
AD		 3074 /* disable queue to avoid issues while updating state */
3075 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3076 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3077
acd37177
AD		 3078 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3079 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3080 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3081 ring->count * sizeof(union ixgbe_adv_rx_desc));
3082 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3083 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3084 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3085
3086 ixgbe_configure_srrctl(adapter, ring);
3087 ixgbe_configure_rscctl(adapter, ring);
3088
e9f98072
GR		 3089 /* If operating in IOV mode set RLPML for X540 */
3090 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3091 hw->mac.type == ixgbe_mac_X540) {
3092 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3093 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3094 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3095 }
3096
9e10e045
AD		 3097 if (hw->mac.type == ixgbe_mac_82598EB) {
3098 /*
3099 * enable cache line friendly hardware writes:
3100 * PTHRESH=32 descriptors (half the internal cache),
3101 * this also removes ugly rx_no_buffer_count increment
3102 * HTHRESH=4 descriptors (to minimize latency on fetch)
3103 * WTHRESH=8 burst writeback up to two cache lines
3104 */
3105 rxdctl &= ~0x3FFFFF;
3106 rxdctl |= 0x080420;
3107 }
3108
3109 /* enable receive descriptor ring */
3110 rxdctl |= IXGBE_RXDCTL_ENABLE;
3111 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3112
3113 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 3114 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 3115}
3116
48654521
AD		 3117static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3118{
3119 struct ixgbe_hw *hw = &adapter->hw;
3120 int p;
3121
3122 /* PSRTYPE must be initialized in non 82598 adapters */
3123 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3124 IXGBE_PSRTYPE_UDPHDR |
3125 IXGBE_PSRTYPE_IPV4HDR |
48654521 3126 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3127 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3128
3129 if (hw->mac.type == ixgbe_mac_82598EB)
3130 return;
3131
3132 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3133 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3134
3135 for (p = 0; p < adapter->num_rx_pools; p++)
3136 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3137 psrtype);
3138}
3139
f5b4a52e
AD		 3140static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3141{
3142 struct ixgbe_hw *hw = &adapter->hw;
3143 u32 gcr_ext;
3144 u32 vt_reg_bits;
3145 u32 reg_offset, vf_shift;
3146 u32 vmdctl;
3147
3148 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3149 return;
3150
3151 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3152 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3153 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3154 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3155
3156 vf_shift = adapter->num_vfs % 32;
3157 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3158
3159 /* Enable only the PF's pool for Tx/Rx */
3160 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3161 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3162 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3163 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3164 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3165
3166 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3167 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3168
3169 /*
3170 * Set up VF register offsets for selected VT Mode,
3171 * i.e. 32 or 64 VFs for SR-IOV
3172 */
3173 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3174 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3175 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3176 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3177
3178 /* enable Tx loopback for VF/PF communication */
3179 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3
GR		 3180 /* Enable MAC Anti-Spoofing */
3181 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3182 adapter->num_vfs);
f5b4a52e
AD		 3183}
3184
477de6ed 3185static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3186{
9a799d71
AK		 3187 struct ixgbe_hw *hw = &adapter->hw;
3188 struct net_device *netdev = adapter->netdev;
3189 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3190 int rx_buf_len;
477de6ed
AD		 3191 struct ixgbe_ring *rx_ring;
3192 int i;
3193 u32 mhadd, hlreg0;
48654521 3194
9a799d71 3195 /* Decide whether to use packet split mode or not */
a124339a
DS		 3196 /* On by default */
3197 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3198
1cdd1ec8 3199 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3200 if (adapter->num_vfs)
3201 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3202
3203 /* Disable packet split due to 82599 erratum #45 */
3204 if (hw->mac.type == ixgbe_mac_82599EB)
3205 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3206
3207 /* Set the RX buffer length according to the mode */
3208 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3209 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3210 } else {
0c19d6af 3211 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3212 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3213 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3214 else
477de6ed 3215 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3216 }
3217
63f39bd1 3218#ifdef IXGBE_FCOE
477de6ed
AD		 3219 /* adjust max frame to be able to do baby jumbo for FCoE */
3220 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3221 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3222 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3223
477de6ed
AD		 3224#endif /* IXGBE_FCOE */
3225 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3226 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3227 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3228 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3229
3230 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3231 }
3232
3233 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3234 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3235 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3236 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3237
0cefafad
JB		 3238 /*
3239 * Setup the HW Rx Head and Tail Descriptor Pointers and
3240 * the Base and Length of the Rx Descriptor Ring
3241 */
9a799d71 3242 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3243 rx_ring = adapter->rx_ring[i];
a6616b42 3244 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3245
6e455b89 3246 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3247 set_ring_ps_enabled(rx_ring);
3248 else
3249 clear_ring_ps_enabled(rx_ring);
3250
3251 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3252 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3253 else
7d637bcc 3254 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3255
63f39bd1 3256#ifdef IXGBE_FCOE
e8e9f696 3257 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3258 struct ixgbe_ring_feature *f;
3259 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3260 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3261 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3262 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3263 rx_ring->rx_buf_len =
e8e9f696 3264 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3265 } else if (!ring_is_rsc_enabled(rx_ring) &&
3266 !ring_is_ps_enabled(rx_ring)) {
3267 rx_ring->rx_buf_len =
3268 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3269 }
63f39bd1 3270 }
63f39bd1 3271#endif /* IXGBE_FCOE */
477de6ed 3272 }
477de6ed
AD		 3273}
3274
7367096a
AD		 3275static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3276{
3277 struct ixgbe_hw *hw = &adapter->hw;
3278 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3279
3280 switch (hw->mac.type) {
3281 case ixgbe_mac_82598EB:
3282 /*
3283 * For VMDq support of different descriptor types or
3284 * buffer sizes through the use of multiple SRRCTL
3285 * registers, RDRXCTL.MVMEN must be set to 1
3286 *
3287 * also, the manual doesn't mention it clearly but DCA hints
3288 * will only use queue 0's tags unless this bit is set. Side
3289 * effects of setting this bit are only that SRRCTL must be
3290 * fully programmed [0..15]
3291 */
3292 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3293 break;
3294 case ixgbe_mac_82599EB:
b93a2226 3295 case ixgbe_mac_X540:
7367096a
AD		 3296 /* Disable RSC for ACK packets */
3297 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3298 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3299 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3300 /* hardware requires some bits to be set by default */
3301 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3302 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3303 break;
3304 default:
3305 /* We should do nothing since we don't know this hardware */
3306 return;
3307 }
3308
3309 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3310}
3311
477de6ed
AD		 3312/**
3313 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3314 * @adapter: board private structure
3315 *
3316 * Configure the Rx unit of the MAC after a reset.
3317 **/
3318static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3319{
3320 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3321 int i;
3322 u32 rxctrl;
477de6ed
AD		 3323
3324 /* disable receives while setting up the descriptors */
3325 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3326 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3327
3328 ixgbe_setup_psrtype(adapter);
7367096a 3329 ixgbe_setup_rdrxctl(adapter);
477de6ed 3330
9e10e045 3331 /* Program registers for the distribution of queues */
f5b4a52e 3332 ixgbe_setup_mrqc(adapter);
f5b4a52e 3333
9e10e045
AD		 3334 ixgbe_set_uta(adapter);
3335
477de6ed
AD		 3336 /* set_rx_buffer_len must be called before ring initialization */
3337 ixgbe_set_rx_buffer_len(adapter);
3338
3339 /*
3340 * Setup the HW Rx Head and Tail Descriptor Pointers and
3341 * the Base and Length of the Rx Descriptor Ring
3342 */
9e10e045
AD		 3343 for (i = 0; i < adapter->num_rx_queues; i++)
3344 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3345
9e10e045
AD		 3346 /* disable drop enable for 82598 parts */
3347 if (hw->mac.type == ixgbe_mac_82598EB)
3348 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3349
3350 /* enable all receives */
3351 rxctrl |= IXGBE_RXCTRL_RXEN;
3352 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3353}
3354
068c89b0
DS		 3355static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3356{
3357 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3358 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3359 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3360
3361 /* add VID to filter table */
1ada1b1b 3362 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3363 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3364}
3365
3366static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3367{
3368 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3369 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3370 int pool_ndx = adapter->num_vfs;
068c89b0 3371
068c89b0 3372 /* remove VID from filter table */
1ada1b1b 3373 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3374 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3375}
3376
5f6c0181
JB		 3377/**
3378 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3379 * @adapter: driver data
3380 */
3381static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3382{
3383 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3384 u32 vlnctrl;
3385
3386 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3387 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3388 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3389}
3390
3391/**
3392 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3393 * @adapter: driver data
3394 */
3395static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3396{
3397 struct ixgbe_hw *hw = &adapter->hw;
3398 u32 vlnctrl;
3399
3400 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3401 vlnctrl |= IXGBE_VLNCTRL_VFE;
3402 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3403 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3404}
3405
3406/**
3407 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3408 * @adapter: driver data
3409 */
3410static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3411{
3412 struct ixgbe_hw *hw = &adapter->hw;
3413 u32 vlnctrl;
5f6c0181
JB		 3414 int i, j;
3415
3416 switch (hw->mac.type) {
3417 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3418 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3419 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3420 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3421 break;
3422 case ixgbe_mac_82599EB:
b93a2226 3423 case ixgbe_mac_X540:
5f6c0181
JB		 3424 for (i = 0; i < adapter->num_rx_queues; i++) {
3425 j = adapter->rx_ring[i]->reg_idx;
3426 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3427 vlnctrl &= ~IXGBE_RXDCTL_VME;
3428 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3429 }
3430 break;
3431 default:
3432 break;
3433 }
3434}
3435
3436/**
f62bbb5e 3437 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3438 * @adapter: driver data
3439 */
f62bbb5e 3440static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3441{
3442 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3443 u32 vlnctrl;
5f6c0181
JB		 3444 int i, j;
3445
3446 switch (hw->mac.type) {
3447 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3448 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3449 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3450 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3451 break;
3452 case ixgbe_mac_82599EB:
b93a2226 3453 case ixgbe_mac_X540:
5f6c0181
JB		 3454 for (i = 0; i < adapter->num_rx_queues; i++) {
3455 j = adapter->rx_ring[i]->reg_idx;
3456 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3457 vlnctrl |= IXGBE_RXDCTL_VME;
3458 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3459 }
3460 break;
3461 default:
3462 break;
3463 }
3464}
3465
9a799d71
AK		 3466static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3467{
f62bbb5e 3468 u16 vid;
9a799d71 3469
f62bbb5e
JG		 3470 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3471
3472 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3473 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3474}
3475
2850062a
AD		 3476/**
3477 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3478 * @netdev: network interface device structure
3479 *
3480 * Writes unicast address list to the RAR table.
3481 * Returns: -ENOMEM on failure/insufficient address space
3482 * 0 on no addresses written
3483 * X on writing X addresses to the RAR table
3484 **/
3485static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3486{
3487 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3488 struct ixgbe_hw *hw = &adapter->hw;
3489 unsigned int vfn = adapter->num_vfs;
3490 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3491 int count = 0;
3492
3493 /* return ENOMEM indicating insufficient memory for addresses */
3494 if (netdev_uc_count(netdev) > rar_entries)
3495 return -ENOMEM;
3496
3497 if (!netdev_uc_empty(netdev) && rar_entries) {
3498 struct netdev_hw_addr *ha;
3499 /* return error if we do not support writing to RAR table */
3500 if (!hw->mac.ops.set_rar)
3501 return -ENOMEM;
3502
3503 netdev_for_each_uc_addr(ha, netdev) {
3504 if (!rar_entries)
3505 break;
3506 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3507 vfn, IXGBE_RAH_AV);
3508 count++;
3509 }
3510 }
3511 /* write the addresses in reverse order to avoid write combining */
3512 for (; rar_entries > 0 ; rar_entries--)
3513 hw->mac.ops.clear_rar(hw, rar_entries);
3514
3515 return count;
3516}
3517
9a799d71 3518/**
2c5645cf 3519 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3520 * @netdev: network interface device structure
3521 *
2c5645cf
CL		 3522 * The set_rx_method entry point is called whenever the unicast/multicast
3523 * address list or the network interface flags are updated. This routine is
3524 * responsible for configuring the hardware for proper unicast, multicast and
3525 * promiscuous mode.
9a799d71 3526 **/
7f870475 3527void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3528{
3529 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3530 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3531 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3532 int count;
9a799d71
AK		 3533
3534 /* Check for Promiscuous and All Multicast modes */
3535
3536 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3537
f5dc442b
AD		 3538 /* set all bits that we expect to always be set */
3539 fctrl |= IXGBE_FCTRL_BAM;
3540 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3541 fctrl |= IXGBE_FCTRL_PMCF;
3542
2850062a
AD		 3543 /* clear the bits we are changing the status of */
3544 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3545
9a799d71 3546 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3547 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3548 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3549 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3550 /* don't hardware filter vlans in promisc mode */
3551 ixgbe_vlan_filter_disable(adapter);
9a799d71 3552 } else {
746b9f02
PM		 3553 if (netdev->flags & IFF_ALLMULTI) {
3554 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3555 vmolr |= IXGBE_VMOLR_MPE;
3556 } else {
3557 /*
3558 * Write addresses to the MTA, if the attempt fails
3559 * then we should just turn on promiscous mode so
3560 * that we can at least receive multicast traffic
3561 */
3562 hw->mac.ops.update_mc_addr_list(hw, netdev);
3563 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3564 }
5f6c0181 3565 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3566 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3567 /*
3568 * Write addresses to available RAR registers, if there is not
3569 * sufficient space to store all the addresses then enable
3570 * unicast promiscous mode
3571 */
3572 count = ixgbe_write_uc_addr_list(netdev);
3573 if (count < 0) {
3574 fctrl |= IXGBE_FCTRL_UPE;
3575 vmolr |= IXGBE_VMOLR_ROPE;
3576 }
9a799d71
AK		 3577 }
3578
2850062a 3579 if (adapter->num_vfs) {
1cdd1ec8 3580 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3581 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3582 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3583 IXGBE_VMOLR_ROPE);
3584 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3585 }
3586
3587 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3588
3589 if (netdev->features & NETIF_F_HW_VLAN_RX)
3590 ixgbe_vlan_strip_enable(adapter);
3591 else
3592 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3593}
3594
021230d4
AV		 3595static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3596{
3597 int q_idx;
3598 struct ixgbe_q_vector *q_vector;
3599 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3600
3601 /* legacy and MSI only use one vector */
3602 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3603 q_vectors = 1;
3604
3605 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3606 struct napi_struct *napi;
7a921c93 3607 q_vector = adapter->q_vector[q_idx];
f0848276 3608 napi = &q_vector->napi;
91281fd3
AD		 3609 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3610 if (!q_vector->rxr_count || !q_vector->txr_count) {
3611 if (q_vector->txr_count == 1)
3612 napi->poll = &ixgbe_clean_txonly;
3613 else if (q_vector->rxr_count == 1)
3614 napi->poll = &ixgbe_clean_rxonly;
3615 }
3616 }
f0848276
JB		 3617
3618 napi_enable(napi);
021230d4
AV		 3619 }
3620}
3621
3622static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3623{
3624 int q_idx;
3625 struct ixgbe_q_vector *q_vector;
3626 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3627
3628 /* legacy and MSI only use one vector */
3629 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3630 q_vectors = 1;
3631
3632 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3633 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3634 napi_disable(&q_vector->napi);
3635 }
3636}
3637
7a6b6f51 3638#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3639/*
3640 * ixgbe_configure_dcb - Configure DCB hardware
3641 * @adapter: ixgbe adapter struct
3642 *
3643 * This is called by the driver on open to configure the DCB hardware.
3644 * This is also called by the gennetlink interface when reconfiguring
3645 * the DCB state.
3646 */
3647static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3648{
3649 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3650 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3651
67ebd791
AD		 3652 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3653 if (hw->mac.type == ixgbe_mac_82598EB)
3654 netif_set_gso_max_size(adapter->netdev, 65536);
3655 return;
3656 }
3657
3658 if (hw->mac.type == ixgbe_mac_82598EB)
3659 netif_set_gso_max_size(adapter->netdev, 32768);
3660
9806307a
JF		 3661#ifdef CONFIG_FCOE
3662 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3663 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3664#endif
3665
80ab193d 3666 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3667 DCB_TX_CONFIG);
80ab193d 3668 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3669 DCB_RX_CONFIG);
2f90b865 3670
2f90b865 3671 /* Enable VLAN tag insert/strip */
f62bbb5e 3672 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3673
2f90b865 3674 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3675
3676 /* reconfigure the hardware */
3677 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
8187cd48
JF		 3678
3679 /* Enable RSS Hash per TC */
3680 if (hw->mac.type != ixgbe_mac_82598EB) {
3681 int i;
3682 u32 reg = 0;
3683
3684 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3685 u8 msb = 0;
3686 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3687
3688 while (cnt >>= 1)
3689 msb++;
3690
3691 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3692 }
3693 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3694 }
2f90b865
AD		 3695}
3696
3697#endif
9a799d71
AK		 3698static void ixgbe_configure(struct ixgbe_adapter *adapter)
3699{
3700 struct net_device *netdev = adapter->netdev;
c4cf55e5 3701 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3702 int i;
3703
7a6b6f51 3704#ifdef CONFIG_IXGBE_DCB
67ebd791 3705 ixgbe_configure_dcb(adapter);
2f90b865 3706#endif
9a799d71 3707
f62bbb5e
JG		 3708 ixgbe_set_rx_mode(netdev);
3709 ixgbe_restore_vlan(adapter);
3710
eacd73f7
YZ		 3711#ifdef IXGBE_FCOE
3712 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3713 ixgbe_configure_fcoe(adapter);
3714
3715#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3716 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3717 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3718 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3719 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3720 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3721 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3722 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3723 }
933d41f1 3724 ixgbe_configure_virtualization(adapter);
c4cf55e5 3725
9a799d71
AK		 3726 ixgbe_configure_tx(adapter);
3727 ixgbe_configure_rx(adapter);
9a799d71
AK		 3728}
3729
e8e26350
PW		 3730static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3731{
3732 switch (hw->phy.type) {
3733 case ixgbe_phy_sfp_avago:
3734 case ixgbe_phy_sfp_ftl:
3735 case ixgbe_phy_sfp_intel:
3736 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3737 case ixgbe_phy_sfp_passive_tyco:
3738 case ixgbe_phy_sfp_passive_unknown:
3739 case ixgbe_phy_sfp_active_unknown:
3740 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3741 return true;
3742 default:
3743 return false;
3744 }
3745}
3746
0ecc061d 3747/**
e8e26350
PW		 3748 * ixgbe_sfp_link_config - set up SFP+ link
3749 * @adapter: pointer to private adapter struct
3750 **/
3751static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3752{
3753 struct ixgbe_hw *hw = &adapter->hw;
3754
3755 if (hw->phy.multispeed_fiber) {
3756 /*
3757 * In multispeed fiber setups, the device may not have
3758 * had a physical connection when the driver loaded.
3759 * If that's the case, the initial link configuration
3760 * couldn't get the MAC into 10G or 1G mode, so we'll
3761 * never have a link status change interrupt fire.
3762 * We need to try and force an autonegotiation
3763 * session, then bring up link.
3764 */
4c7e604b
AG		 3765 if (hw->mac.ops.setup_sfp)
3766 hw->mac.ops.setup_sfp(hw);
e8e26350
PW		 3767 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3768 schedule_work(&adapter->multispeed_fiber_task);
3769 } else {
3770 /*
3771 * Direct Attach Cu and non-multispeed fiber modules
3772 * still need to be configured properly prior to
3773 * attempting link.
3774 */
3775 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3776 schedule_work(&adapter->sfp_config_module_task);
3777 }
3778}
3779
3780/**
3781 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3782 * @hw: pointer to private hardware struct
3783 *
3784 * Returns 0 on success, negative on failure
3785 **/
e8e26350 3786static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3787{
3788 u32 autoneg;
8620a103 3789 bool negotiation, link_up = false;
0ecc061d
PWJ		 3790 u32 ret = IXGBE_ERR_LINK_SETUP;
3791
3792 if (hw->mac.ops.check_link)
3793 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3794
3795 if (ret)
3796 goto link_cfg_out;
3797
0b0c2b31
ET		 3798 autoneg = hw->phy.autoneg_advertised;
3799 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3800 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3801 &negotiation);
0ecc061d
PWJ		 3802 if (ret)
3803 goto link_cfg_out;
3804
8620a103
MC		 3805 if (hw->mac.ops.setup_link)
3806 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3807link_cfg_out:
3808 return ret;
3809}
3810
a34bcfff 3811static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3812{
9a799d71 3813 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3814 u32 gpie = 0;
9a799d71 3815
9b471446 3816 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3817 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3818 IXGBE_GPIE_OCD;
3819 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3820 /*
3821 * use EIAM to auto-mask when MSI-X interrupt is asserted
3822 * this saves a register write for every interrupt
3823 */
3824 switch (hw->mac.type) {
3825 case ixgbe_mac_82598EB:
3826 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3827 break;
9b471446 3828 case ixgbe_mac_82599EB:
b93a2226
DS		 3829 case ixgbe_mac_X540:
3830 default:
9b471446
JB		 3831 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3832 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3833 break;
3834 }
3835 } else {
021230d4
AV		 3836 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3837 * specifically only auto mask tx and rx interrupts */
3838 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3839 }
9a799d71 3840
a34bcfff
AD		 3841 /* XXX: to interrupt immediately for EICS writes, enable this */
3842 /* gpie |= IXGBE_GPIE_EIMEN; */
3843
3844 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3845 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3846 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3847 }
3848
a34bcfff
AD		 3849 /* Enable fan failure interrupt */
3850 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3851 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3852
a34bcfff 3853 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3854 gpie |= IXGBE_SDP1_GPIEN;
3855 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3856
3857 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3858}
3859
3860static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3861{
3862 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3863 int err;
a34bcfff
AD		 3864 u32 ctrl_ext;
3865
3866 ixgbe_get_hw_control(adapter);
3867 ixgbe_setup_gpie(adapter);
e8e26350 3868
9a799d71
AK		 3869 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3870 ixgbe_configure_msix(adapter);
3871 else
3872 ixgbe_configure_msi_and_legacy(adapter);
3873
c6ecf39a
DS		 3874 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3875 if (hw->mac.ops.enable_tx_laser &&
3876 ((hw->phy.multispeed_fiber) ||
9f911707 3877 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3878 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3879 hw->mac.ops.enable_tx_laser(hw);
3880
9a799d71 3881 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3882 ixgbe_napi_enable_all(adapter);
3883
73c4b7cd
AD		 3884 if (ixgbe_is_sfp(hw)) {
3885 ixgbe_sfp_link_config(adapter);
3886 } else {
3887 err = ixgbe_non_sfp_link_config(hw);
3888 if (err)
3889 e_err(probe, "link_config FAILED %d\n", err);
3890 }
3891
021230d4
AV		 3892 /* clear any pending interrupts, may auto mask */
3893 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3894 ixgbe_irq_enable(adapter, true, true);
9a799d71 3895
bf069c97
DS		 3896 /*
3897 * If this adapter has a fan, check to see if we had a failure
3898 * before we enabled the interrupt.
3899 */
3900 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3901 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3902 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3903 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3904 }
3905
e8e26350
PW		 3906 /*
3907 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3908 * arrived before interrupts were enabled but after probe. Such
3909 * devices wouldn't have their type identified yet. We need to
3910 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3911 * If we're not hot-pluggable SFP+, we just need to configure link
3912 * and bring it up.
3913 */
21cc5b4f 3914 if (hw->phy.type == ixgbe_phy_none)
73c4b7cd 3915 schedule_work(&adapter->sfp_config_module_task);
0ecc061d 3916
1da100bb 3917 /* enable transmits */
477de6ed 3918 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3919
9a799d71
AK		 3920 /* bring the link up in the watchdog, this could race with our first
3921 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3922 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3923 adapter->link_check_timeout = jiffies;
9a799d71 3924 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3925
3926 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3927 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3928 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3929 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3930
9a799d71
AK		 3931 return 0;
3932}
3933
d4f80882
AV		 3934void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3935{
3936 WARN_ON(in_interrupt());
3937 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3938 msleep(1);
3939 ixgbe_down(adapter);
5809a1ae
GR		 3940 /*
3941 * If SR-IOV enabled then wait a bit before bringing the adapter
3942 * back up to give the VFs time to respond to the reset. The
3943 * two second wait is based upon the watchdog timer cycle in
3944 * the VF driver.
3945 */
3946 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3947 msleep(2000);
d4f80882
AV		 3948 ixgbe_up(adapter);
3949 clear_bit(__IXGBE_RESETTING, &adapter->state);
3950}
3951
9a799d71
AK		 3952int ixgbe_up(struct ixgbe_adapter *adapter)
3953{
3954 /* hardware has been reset, we need to reload some things */
3955 ixgbe_configure(adapter);
3956
3957 return ixgbe_up_complete(adapter);
3958}
3959
3960void ixgbe_reset(struct ixgbe_adapter *adapter)
3961{
c44ade9e 3962 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3963 int err;
3964
3965 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3966 switch (err) {
3967 case 0:
3968 case IXGBE_ERR_SFP_NOT_PRESENT:
3969 break;
3970 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3971 e_dev_err("master disable timed out\n");
da4dd0f7 3972 break;
794caeb2
PWJ		 3973 case IXGBE_ERR_EEPROM_VERSION:
3974 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3975 e_dev_warn("This device is a pre-production adapter/LOM. "
3976 "Please be aware there may be issuesassociated with "
3977 "your hardware. If you are experiencing problems "
3978 "please contact your Intel or hardware "
3979 "representative who provided you with this "
3980 "hardware.\n");
794caeb2 3981 break;
da4dd0f7 3982 default:
849c4542 3983 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3984 }
9a799d71
AK		 3985
3986 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3987 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3988 IXGBE_RAH_AV);
9a799d71
AK		 3989}
3990
9a799d71
AK		 3991/**
3992 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3993 * @rx_ring: ring to free buffers from
3994 **/
b6ec895e 3995static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3996{
b6ec895e 3997 struct device *dev = rx_ring->dev;
9a799d71 3998 unsigned long size;
b6ec895e 3999 u16 i;
9a799d71 4000
84418e3b
AD		 4001 /* ring already cleared, nothing to do */
4002 if (!rx_ring->rx_buffer_info)
4003 return;
9a799d71 4004
84418e3b 4005 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4006 for (i = 0; i < rx_ring->count; i++) {
4007 struct ixgbe_rx_buffer *rx_buffer_info;
4008
4009 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4010 if (rx_buffer_info->dma) {
b6ec895e 4011 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4012 rx_ring->rx_buf_len,
1b507730 4013 DMA_FROM_DEVICE);
9a799d71
AK		 4014 rx_buffer_info->dma = 0;
4015 }
4016 if (rx_buffer_info->skb) {
f8212f97 4017 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4018 rx_buffer_info->skb = NULL;
f8212f97
AD		 4019 do {
4020 struct sk_buff *this = skb;
e8171aaa 4021 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 4022 dma_unmap_single(dev,
1b507730 4023 IXGBE_RSC_CB(this)->dma,
e8e9f696 4024 rx_ring->rx_buf_len,
1b507730 4025 DMA_FROM_DEVICE);
fd3686a8 4026 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 4027 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 4028 }
f8212f97
AD		 4029 skb = skb->prev;
4030 dev_kfree_skb(this);
4031 } while (skb);
9a799d71
AK		 4032 }
4033 if (!rx_buffer_info->page)
4034 continue;
4f57ca6e 4035 if (rx_buffer_info->page_dma) {
b6ec895e 4036 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4037 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4038 rx_buffer_info->page_dma = 0;
4039 }
9a799d71
AK		 4040 put_page(rx_buffer_info->page);
4041 rx_buffer_info->page = NULL;
762f4c57 4042 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4043 }
4044
4045 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4046 memset(rx_ring->rx_buffer_info, 0, size);
4047
4048 /* Zero out the descriptor ring */
4049 memset(rx_ring->desc, 0, rx_ring->size);
4050
4051 rx_ring->next_to_clean = 0;
4052 rx_ring->next_to_use = 0;
9a799d71
AK		 4053}
4054
4055/**
4056 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4057 * @tx_ring: ring to be cleaned
4058 **/
b6ec895e 4059static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4060{
4061 struct ixgbe_tx_buffer *tx_buffer_info;
4062 unsigned long size;
b6ec895e 4063 u16 i;
9a799d71 4064
84418e3b
AD		 4065 /* ring already cleared, nothing to do */
4066 if (!tx_ring->tx_buffer_info)
4067 return;
9a799d71 4068
84418e3b 4069 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4070 for (i = 0; i < tx_ring->count; i++) {
4071 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4072 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4073 }
4074
4075 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4076 memset(tx_ring->tx_buffer_info, 0, size);
4077
4078 /* Zero out the descriptor ring */
4079 memset(tx_ring->desc, 0, tx_ring->size);
4080
4081 tx_ring->next_to_use = 0;
4082 tx_ring->next_to_clean = 0;
9a799d71
AK		 4083}
4084
4085/**
021230d4 4086 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4087 * @adapter: board private structure
4088 **/
021230d4 4089static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4090{
4091 int i;
4092
021230d4 4093 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4094 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4095}
4096
4097/**
021230d4 4098 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4099 * @adapter: board private structure
4100 **/
021230d4 4101static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4102{
4103 int i;
4104
021230d4 4105 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4106 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4107}
4108
4109void ixgbe_down(struct ixgbe_adapter *adapter)
4110{
4111 struct net_device *netdev = adapter->netdev;
7f821875 4112 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4113 u32 rxctrl;
7f821875 4114 u32 txdctl;
bf29ee6c 4115 int i;
b25ebfd2 4116 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4117
4118 /* signal that we are down to the interrupt handler */
4119 set_bit(__IXGBE_DOWN, &adapter->state);
4120
767081ad
GR		 4121 /* disable receive for all VFs and wait one second */
4122 if (adapter->num_vfs) {
767081ad
GR		 4123 /* ping all the active vfs to let them know we are going down */
4124 ixgbe_ping_all_vfs(adapter);
581d1aa7 4125
767081ad
GR		 4126 /* Disable all VFTE/VFRE TX/RX */
4127 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 4128
4129 /* Mark all the VFs as inactive */
4130 for (i = 0 ; i < adapter->num_vfs; i++)
4131 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 4132 }
4133
9a799d71 4134 /* disable receives */
7f821875
JB		 4135 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4136 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4137
2d39d576
YZ		 4138 /* disable all enabled rx queues */
4139 for (i = 0; i < adapter->num_rx_queues; i++)
4140 /* this call also flushes the previous write */
4141 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4142
9a799d71
AK		 4143 msleep(10);
4144
7f821875
JB		 4145 netif_tx_stop_all_queues(netdev);
4146
0a1f87cb
DS		 4147 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4148 del_timer_sync(&adapter->sfp_timer);
9a799d71 4149 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 4150 cancel_work_sync(&adapter->watchdog_task);
9a799d71 4151
c0dfb90e
JF		 4152 netif_carrier_off(netdev);
4153 netif_tx_disable(netdev);
4154
4155 ixgbe_irq_disable(adapter);
4156
4157 ixgbe_napi_disable_all(adapter);
4158
b25ebfd2
PW		 4159 /* Cleanup the affinity_hint CPU mask memory and callback */
4160 for (i = 0; i < num_q_vectors; i++) {
4161 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4162 /* clear the affinity_mask in the IRQ descriptor */
4163 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4164 /* release the CPU mask memory */
4165 free_cpumask_var(q_vector->affinity_mask);
4166 }
4167
c4cf55e5
PWJ		 4168 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4169 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4170 cancel_work_sync(&adapter->fdir_reinit_task);
4171
119fc60a
MC		 4172 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4173 cancel_work_sync(&adapter->check_overtemp_task);
4174
7f821875
JB		 4175 /* disable transmits in the hardware now that interrupts are off */
4176 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c
AD		 4177 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4178 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4179 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
e8e9f696 4180 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 4181 }
88512539 4182 /* Disable the Tx DMA engine on 82599 */
bd508178
AD		 4183 switch (hw->mac.type) {
4184 case ixgbe_mac_82599EB:
b93a2226 4185 case ixgbe_mac_X540:
88512539 4186 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4187 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4188 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4189 break;
4190 default:
4191 break;
4192 }
7f821875 4193
9a713e7c
PW		 4194 /* clear n-tuple filters that are cached */
4195 ethtool_ntuple_flush(netdev);
4196
6f4a0e45
PL		 4197 if (!pci_channel_offline(adapter->pdev))
4198 ixgbe_reset(adapter);
c6ecf39a
DS		 4199
4200 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4201 if (hw->mac.ops.disable_tx_laser &&
4202 ((hw->phy.multispeed_fiber) ||
9f911707 4203 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4204 (hw->mac.type == ixgbe_mac_82599EB))))
4205 hw->mac.ops.disable_tx_laser(hw);
4206
9a799d71
AK		 4207 ixgbe_clean_all_tx_rings(adapter);
4208 ixgbe_clean_all_rx_rings(adapter);
4209
5dd2d332 4210#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4211 /* since we reset the hardware DCA settings were cleared */
e35ec126 4212 ixgbe_setup_dca(adapter);
96b0e0f6 4213#endif
9a799d71
AK		 4214}
4215
9a799d71 4216/**
021230d4
AV		 4217 * ixgbe_poll - NAPI Rx polling callback
4218 * @napi: structure for representing this polling device
4219 * @budget: how many packets driver is allowed to clean
4220 *
4221 * This function is used for legacy and MSI, NAPI mode
9a799d71 4222 **/
021230d4 4223static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4224{
9a1a69ad 4225 struct ixgbe_q_vector *q_vector =
e8e9f696 4226 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4227 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4228 int tx_clean_complete, work_done = 0;
9a799d71 4229
5dd2d332 4230#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4231 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4232 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4233#endif
4234
4a0b9ca0
PW		 4235 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4236 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4237
9a1a69ad 4238 if (!tx_clean_complete)
d2c7ddd6
DM		 4239 work_done = budget;
4240
53e52c72
DM		 4241 /* If budget not fully consumed, exit the polling mode */
4242 if (work_done < budget) {
288379f0 4243 napi_complete(napi);
f7554a2b 4244 if (adapter->rx_itr_setting & 1)
f494e8fa 4245 ixgbe_set_itr(adapter);
d4f80882 4246 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4247 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4248 }
9a799d71
AK		 4249 return work_done;
4250}
4251
4252/**
4253 * ixgbe_tx_timeout - Respond to a Tx Hang
4254 * @netdev: network interface device structure
4255 **/
4256static void ixgbe_tx_timeout(struct net_device *netdev)
4257{
4258 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4259
c84d324c
JF		 4260 adapter->tx_timeout_count++;
4261
9a799d71
AK		 4262 /* Do the reset outside of interrupt context */
4263 schedule_work(&adapter->reset_task);
4264}
4265
4266static void ixgbe_reset_task(struct work_struct *work)
4267{
4268 struct ixgbe_adapter *adapter;
4269 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4270
2f90b865
AD		 4271 /* If we're already down or resetting, just bail */
4272 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4273 test_bit(__IXGBE_RESETTING, &adapter->state))
4274 return;
4275
dcd79aeb
TI		 4276 ixgbe_dump(adapter);
4277 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 4278 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4279}
4280
4df10466
JB		 4281/**
4282 * ixgbe_set_rss_queues: Allocate queues for RSS
4283 * @adapter: board private structure to initialize
4284 *
4285 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4286 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4287 *
4288 **/
bc97114d
PWJ		 4289static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4290{
4291 bool ret = false;
0cefafad 4292 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4293
4294 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4295 f->mask = 0xF;
4296 adapter->num_rx_queues = f->indices;
4297 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4298 ret = true;
4299 } else {
bc97114d 4300 ret = false;
b9804972
JB		 4301 }
4302
bc97114d
PWJ		 4303 return ret;
4304}
4305
c4cf55e5
PWJ		 4306/**
4307 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4308 * @adapter: board private structure to initialize
4309 *
4310 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4311 * to the original CPU that initiated the Tx session. This runs in addition
4312 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4313 * Rx load across CPUs using RSS.
4314 *
4315 **/
e8e9f696 4316static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4317{
4318 bool ret = false;
4319 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4320
4321 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4322 f_fdir->mask = 0;
4323
4324 /* Flow Director must have RSS enabled */
4325 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4326 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4327 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4328 adapter->num_tx_queues = f_fdir->indices;
4329 adapter->num_rx_queues = f_fdir->indices;
4330 ret = true;
4331 } else {
4332 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4333 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4334 }
4335 return ret;
4336}
4337
0331a832
YZ		 4338#ifdef IXGBE_FCOE
4339/**
4340 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4341 * @adapter: board private structure to initialize
4342 *
4343 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4344 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4345 * rx queues out of the max number of rx queues, instead, it is used as the
4346 * index of the first rx queue used by FCoE.
4347 *
4348 **/
4349static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4350{
0331a832
YZ		 4351 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4352
e5b64635
JF		 4353 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4354 return false;
4355
4356 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
0331a832 4357#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4358 int tc;
4359 struct net_device *dev = adapter->netdev;
4360
4361 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4362 f->indices = dev->tc_to_txq[tc].count;
4363 f->mask = dev->tc_to_txq[tc].offset;
0331a832 4364#endif
e5b64635
JF		 4365 } else {
4366 f->indices = min((int)num_online_cpus(), f->indices);
4367
4368 adapter->num_rx_queues = 1;
4369 adapter->num_tx_queues = 1;
4370
0331a832 4371 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4372 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4373 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4374 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4375 ixgbe_set_fdir_queues(adapter);
4376 else
4377 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4378 }
4379 /* adding FCoE rx rings to the end */
4380 f->mask = adapter->num_rx_queues;
4381 adapter->num_rx_queues += f->indices;
8de8b2e6 4382 adapter->num_tx_queues += f->indices;
e5b64635 4383 }
0331a832 4384
e5b64635
JF		 4385 return true;
4386}
4387#endif /* IXGBE_FCOE */
4388
4389#ifdef CONFIG_IXGBE_DCB
4390static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4391{
4392 bool ret = false;
4393 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4394 int i, q;
4395
4396 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4397 return ret;
4398
4399 f->indices = 0;
4400 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4401 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4402 f->indices += q;
0331a832
YZ		 4403 }
4404
e5b64635
JF		 4405 f->mask = 0x7 << 3;
4406 adapter->num_rx_queues = f->indices;
4407 adapter->num_tx_queues = f->indices;
4408 ret = true;
4409
4410#ifdef IXGBE_FCOE
4411 /* FCoE enabled queues require special configuration done through
4412 * configure_fcoe() and others. Here we map FCoE indices onto the
4413 * DCB queue pairs allowing FCoE to own configuration later.
4414 */
4415 ixgbe_set_fcoe_queues(adapter);
4416#endif
4417
0331a832
YZ		 4418 return ret;
4419}
e5b64635 4420#endif
0331a832 4421
1cdd1ec8
GR		 4422/**
4423 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4424 * @adapter: board private structure to initialize
4425 *
4426 * IOV doesn't actually use anything, so just NAK the
4427 * request for now and let the other queue routines
4428 * figure out what to do.
4429 */
4430static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4431{
4432 return false;
4433}
4434
4df10466
JB		 4435/*
4436 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4437 * @adapter: board private structure to initialize
4438 *
4439 * This is the top level queue allocation routine. The order here is very
4440 * important, starting with the "most" number of features turned on at once,
4441 * and ending with the smallest set of features. This way large combinations
4442 * can be allocated if they're turned on, and smaller combinations are the
4443 * fallthrough conditions.
4444 *
4445 **/
847f53ff 4446static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4447{
1cdd1ec8
GR		 4448 /* Start with base case */
4449 adapter->num_rx_queues = 1;
4450 adapter->num_tx_queues = 1;
4451 adapter->num_rx_pools = adapter->num_rx_queues;
4452 adapter->num_rx_queues_per_pool = 1;
4453
4454 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4455 goto done;
1cdd1ec8 4456
bc97114d
PWJ		 4457#ifdef CONFIG_IXGBE_DCB
4458 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4459 goto done;
bc97114d
PWJ		 4460
4461#endif
e5b64635
JF		 4462#ifdef IXGBE_FCOE
4463 if (ixgbe_set_fcoe_queues(adapter))
4464 goto done;
4465
4466#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4467 if (ixgbe_set_fdir_queues(adapter))
4468 goto done;
4469
bc97114d 4470 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4471 goto done;
4472
4473 /* fallback to base case */
4474 adapter->num_rx_queues = 1;
4475 adapter->num_tx_queues = 1;
4476
4477done:
847f53ff 4478 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4479 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4480 return netif_set_real_num_rx_queues(adapter->netdev,
4481 adapter->num_rx_queues);
b9804972
JB		 4482}
4483
021230d4 4484static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4485 int vectors)
021230d4
AV		 4486{
4487 int err, vector_threshold;
4488
4489 /* We'll want at least 3 (vector_threshold):
4490 * 1) TxQ[0] Cleanup
4491 * 2) RxQ[0] Cleanup
4492 * 3) Other (Link Status Change, etc.)
4493 * 4) TCP Timer (optional)
4494 */
4495 vector_threshold = MIN_MSIX_COUNT;
4496
4497 /* The more we get, the more we will assign to Tx/Rx Cleanup
4498 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4499 * Right now, we simply care about how many we'll get; we'll
4500 * set them up later while requesting irq's.
4501 */
4502 while (vectors >= vector_threshold) {
4503 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4504 vectors);
021230d4
AV		 4505 if (!err) /* Success in acquiring all requested vectors. */
4506 break;
4507 else if (err < 0)
4508 vectors = 0; /* Nasty failure, quit now */
4509 else /* err == number of vectors we should try again with */
4510 vectors = err;
4511 }
4512
4513 if (vectors < vector_threshold) {
4514 /* Can't allocate enough MSI-X interrupts? Oh well.
4515 * This just means we'll go with either a single MSI
4516 * vector or fall back to legacy interrupts.
4517 */
849c4542
ET		 4518 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4519 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4520 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4521 kfree(adapter->msix_entries);
4522 adapter->msix_entries = NULL;
021230d4
AV		 4523 } else {
4524 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4525 /*
4526 * Adjust for only the vectors we'll use, which is minimum
4527 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4528 * vectors we were allocated.
4529 */
4530 adapter->num_msix_vectors = min(vectors,
e8e9f696 4531 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4532 }
4533}
4534
021230d4 4535/**
bc97114d 4536 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4537 * @adapter: board private structure to initialize
4538 *
bc97114d
PWJ		 4539 * Cache the descriptor ring offsets for RSS to the assigned rings.
4540 *
021230d4 4541 **/
bc97114d 4542static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4543{
bc97114d 4544 int i;
bc97114d 4545
9d6b758f
AD		 4546 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4547 return false;
bc97114d 4548
9d6b758f
AD		 4549 for (i = 0; i < adapter->num_rx_queues; i++)
4550 adapter->rx_ring[i]->reg_idx = i;
4551 for (i = 0; i < adapter->num_tx_queues; i++)
4552 adapter->tx_ring[i]->reg_idx = i;
4553
4554 return true;
bc97114d
PWJ		 4555}
4556
4557#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4558
4559/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4560void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4561 unsigned int *tx, unsigned int *rx)
4562{
4563 struct net_device *dev = adapter->netdev;
4564 struct ixgbe_hw *hw = &adapter->hw;
4565 u8 num_tcs = netdev_get_num_tc(dev);
4566
4567 *tx = 0;
4568 *rx = 0;
4569
4570 switch (hw->mac.type) {
4571 case ixgbe_mac_82598EB:
4572 *tx = tc << 3;
4573 *rx = tc << 2;
4574 break;
4575 case ixgbe_mac_82599EB:
4576 case ixgbe_mac_X540:
4577 if (num_tcs == 8) {
4578 if (tc < 3) {
4579 *tx = tc << 5;
4580 *rx = tc << 4;
4581 } else if (tc < 5) {
4582 *tx = ((tc + 2) << 4);
4583 *rx = tc << 4;
4584 } else if (tc < num_tcs) {
4585 *tx = ((tc + 8) << 3);
4586 *rx = tc << 4;
4587 }
4588 } else if (num_tcs == 4) {
4589 *rx = tc << 5;
4590 switch (tc) {
4591 case 0:
4592 *tx = 0;
4593 break;
4594 case 1:
4595 *tx = 64;
4596 break;
4597 case 2:
4598 *tx = 96;
4599 break;
4600 case 3:
4601 *tx = 112;
4602 break;
4603 default:
4604 break;
4605 }
4606 }
4607 break;
4608 default:
4609 break;
4610 }
4611}
4612
4613#define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4614
4615/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4616 * classes.
4617 *
4618 * @netdev: net device to configure
4619 * @tc: number of traffic classes to enable
4620 */
4621int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4622{
4623 int i;
4624 unsigned int q, offset = 0;
4625
4626 if (!tc) {
4627 netdev_reset_tc(dev);
4628 } else {
24095aa3
JF		 4629 struct ixgbe_adapter *adapter = netdev_priv(dev);
4630
4631 /* Hardware supports up to 8 traffic classes */
4632 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
e5b64635
JF		 4633 return -EINVAL;
4634
4635 /* Partition Tx queues evenly amongst traffic classes */
4636 for (i = 0; i < tc; i++) {
4637 q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4638 netdev_set_prio_tc_map(dev, i, i);
4639 netdev_set_tc_queue(dev, i, q, offset);
4640 offset += q;
4641 }
24095aa3
JF		 4642
4643 /* This enables multiple traffic class support in the hardware
4644 * which defaults to strict priority transmission by default.
4645 * If traffic classes are already enabled perhaps through DCB
4646 * code path then existing configuration will be used.
4647 */
4648 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4649 dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4650 struct ieee_ets ets = {
4651 .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4652 };
4653 u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4654
4655 dev->dcbnl_ops->setdcbx(dev, mode);
4656 dev->dcbnl_ops->ieee_setets(dev, &ets);
4657 }
e5b64635
JF		 4658 }
4659 return 0;
4660}
4661
bc97114d
PWJ		 4662/**
4663 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4664 * @adapter: board private structure to initialize
4665 *
4666 * Cache the descriptor ring offsets for DCB to the assigned rings.
4667 *
4668 **/
4669static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4670{
e5b64635
JF		 4671 struct net_device *dev = adapter->netdev;
4672 int i, j, k;
4673 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4674
bd508178
AD		 4675 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4676 return false;
f92ef202 4677
e5b64635
JF		 4678 for (i = 0, k = 0; i < num_tcs; i++) {
4679 unsigned int tx_s, rx_s;
4680 u16 count = dev->tc_to_txq[i].count;
4681
4682 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4683 for (j = 0; j < count; j++, k++) {
4684 adapter->tx_ring[k]->reg_idx = tx_s + j;
4685 adapter->rx_ring[k]->reg_idx = rx_s + j;
4686 adapter->tx_ring[k]->dcb_tc = i;
4687 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4688 }
021230d4 4689 }
e5b64635
JF		 4690
4691 return true;
bc97114d
PWJ		 4692}
4693#endif
4694
c4cf55e5
PWJ		 4695/**
4696 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4697 * @adapter: board private structure to initialize
4698 *
4699 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4700 *
4701 **/
e8e9f696 4702static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4703{
4704 int i;
4705 bool ret = false;
4706
4707 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4708 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4709 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4710 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4711 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4712 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4713 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4714 ret = true;
4715 }
4716
4717 return ret;
4718}
4719
0331a832
YZ		 4720#ifdef IXGBE_FCOE
4721/**
4722 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4723 * @adapter: board private structure to initialize
4724 *
4725 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4726 *
4727 */
4728static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4729{
0331a832 4730 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4731 int i;
4732 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4733
4734 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4735 return false;
0331a832 4736
bf29ee6c
AD		 4737 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4738 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4739 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4740 ixgbe_cache_ring_fdir(adapter);
4741 else
4742 ixgbe_cache_ring_rss(adapter);
8faa2a78 4743
bf29ee6c
AD		 4744 fcoe_rx_i = f->mask;
4745 fcoe_tx_i = f->mask;
0331a832 4746 }
bf29ee6c
AD		 4747 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4748 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4749 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4750 }
4751 return true;
0331a832
YZ		 4752}
4753
4754#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4755/**
4756 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4757 * @adapter: board private structure to initialize
4758 *
4759 * SR-IOV doesn't use any descriptor rings but changes the default if
4760 * no other mapping is used.
4761 *
4762 */
4763static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4764{
4a0b9ca0
PW		 4765 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4766 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4767 if (adapter->num_vfs)
4768 return true;
4769 else
4770 return false;
4771}
4772
bc97114d
PWJ		 4773/**
4774 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4775 * @adapter: board private structure to initialize
4776 *
4777 * Once we know the feature-set enabled for the device, we'll cache
4778 * the register offset the descriptor ring is assigned to.
4779 *
4780 * Note, the order the various feature calls is important. It must start with
4781 * the "most" features enabled at the same time, then trickle down to the
4782 * least amount of features turned on at once.
4783 **/
4784static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4785{
4786 /* start with default case */
4a0b9ca0
PW		 4787 adapter->rx_ring[0]->reg_idx = 0;
4788 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4789
1cdd1ec8
GR		 4790 if (ixgbe_cache_ring_sriov(adapter))
4791 return;
4792
e5b64635
JF		 4793#ifdef CONFIG_IXGBE_DCB
4794 if (ixgbe_cache_ring_dcb(adapter))
4795 return;
4796#endif
4797
0331a832
YZ		 4798#ifdef IXGBE_FCOE
4799 if (ixgbe_cache_ring_fcoe(adapter))
4800 return;
0331a832 4801#endif /* IXGBE_FCOE */
bc97114d 4802
c4cf55e5
PWJ		 4803 if (ixgbe_cache_ring_fdir(adapter))
4804 return;
4805
bc97114d
PWJ		 4806 if (ixgbe_cache_ring_rss(adapter))
4807 return;
021230d4
AV		 4808}
4809
9a799d71
AK		 4810/**
4811 * ixgbe_alloc_queues - Allocate memory for all rings
4812 * @adapter: board private structure to initialize
4813 *
4814 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4815 * number of queues at compile-time. The polling_netdev array is
4816 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4817 **/
2f90b865 4818static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4819{
e2ddeba9 4820 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4821
e2ddeba9
ED		 4822 if (nid < 0 || !node_online(nid))
4823 nid = first_online_node;
4824
4825 for (; tx < adapter->num_tx_queues; tx++) {
4826 struct ixgbe_ring *ring;
4827
4828 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4829 if (!ring)
e2ddeba9 4830 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4831 if (!ring)
e2ddeba9 4832 goto err_allocation;
4a0b9ca0 4833 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4834 ring->queue_index = tx;
4835 ring->numa_node = nid;
b6ec895e 4836 ring->dev = &adapter->pdev->dev;
fc77dc3c 4837 ring->netdev = adapter->netdev;
4a0b9ca0 4838
e2ddeba9 4839 adapter->tx_ring[tx] = ring;
021230d4 4840 }
b9804972 4841
e2ddeba9
ED		 4842 for (; rx < adapter->num_rx_queues; rx++) {
4843 struct ixgbe_ring *ring;
4a0b9ca0 4844
e2ddeba9 4845 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4846 if (!ring)
e2ddeba9 4847 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4848 if (!ring)
e2ddeba9
ED		 4849 goto err_allocation;
4850 ring->count = adapter->rx_ring_count;
4851 ring->queue_index = rx;
4852 ring->numa_node = nid;
b6ec895e 4853 ring->dev = &adapter->pdev->dev;
fc77dc3c 4854 ring->netdev = adapter->netdev;
4a0b9ca0 4855
e2ddeba9 4856 adapter->rx_ring[rx] = ring;
021230d4
AV		 4857 }
4858
4859 ixgbe_cache_ring_register(adapter);
4860
4861 return 0;
4862
e2ddeba9
ED		 4863err_allocation:
4864 while (tx)
4865 kfree(adapter->tx_ring[--tx]);
4866
4867 while (rx)
4868 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4869 return -ENOMEM;
4870}
4871
4872/**
4873 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4874 * @adapter: board private structure to initialize
4875 *
4876 * Attempt to configure the interrupts using the best available
4877 * capabilities of the hardware and the kernel.
4878 **/
feea6a57 4879static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4880{
8be0e467 4881 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4882 int err = 0;
4883 int vector, v_budget;
4884
4885 /*
4886 * It's easy to be greedy for MSI-X vectors, but it really
4887 * doesn't do us much good if we have a lot more vectors
4888 * than CPU's. So let's be conservative and only ask for
342bde1b 4889 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4890 */
4891 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4892 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4893
4894 /*
4895 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4896 * hw.mac->max_msix_vectors vectors. With features
4897 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4898 * descriptor queues supported by our device. Thus, we cap it off in
4899 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4900 */
8be0e467 4901 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4902
4903 /* A failure in MSI-X entry allocation isn't fatal, but it does
4904 * mean we disable MSI-X capabilities of the adapter. */
4905 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4906 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4907 if (adapter->msix_entries) {
4908 for (vector = 0; vector < v_budget; vector++)
4909 adapter->msix_entries[vector].entry = vector;
021230d4 4910
7a921c93 4911 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4912
7a921c93
AD		 4913 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4914 goto out;
4915 }
26d27844 4916
7a921c93
AD		 4917 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4918 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
45b9f509
AD		 4919 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4920 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4921 e_err(probe,
4922 "Flow Director is not supported while multiple "
4923 "queues are disabled. Disabling Flow Director\n");
4924 }
c4cf55e5
PWJ		 4925 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4926 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4927 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4928 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4929 ixgbe_disable_sriov(adapter);
4930
847f53ff
BH		 4931 err = ixgbe_set_num_queues(adapter);
4932 if (err)
4933 return err;
021230d4 4934
021230d4
AV		 4935 err = pci_enable_msi(adapter->pdev);
4936 if (!err) {
4937 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4938 } else {
849c4542
ET		 4939 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4940 "Unable to allocate MSI interrupt, "
4941 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4942 /* reset err */
4943 err = 0;
4944 }
4945
4946out:
021230d4
AV		 4947 return err;
4948}
4949
7a921c93
AD		 4950/**
4951 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4952 * @adapter: board private structure to initialize
4953 *
4954 * We allocate one q_vector per queue interrupt. If allocation fails we
4955 * return -ENOMEM.
4956 **/
4957static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4958{
4959 int q_idx, num_q_vectors;
4960 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4961 int (*poll)(struct napi_struct *, int);
4962
4963 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4964 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4965 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4966 } else {
4967 num_q_vectors = 1;
7a921c93
AD		 4968 poll = &ixgbe_poll;
4969 }
4970
4971 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4972 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4973 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4974 if (!q_vector)
4975 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4976 GFP_KERNEL);
7a921c93
AD		 4977 if (!q_vector)
4978 goto err_out;
4979 q_vector->adapter = adapter;
f7554a2b
NS		 4980 if (q_vector->txr_count && !q_vector->rxr_count)
4981 q_vector->eitr = adapter->tx_eitr_param;
4982 else
4983 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4984 q_vector->v_idx = q_idx;
91281fd3 4985 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4986 adapter->q_vector[q_idx] = q_vector;
4987 }
4988
4989 return 0;
4990
4991err_out:
4992 while (q_idx) {
4993 q_idx--;
4994 q_vector = adapter->q_vector[q_idx];
4995 netif_napi_del(&q_vector->napi);
4996 kfree(q_vector);
4997 adapter->q_vector[q_idx] = NULL;
4998 }
4999 return -ENOMEM;
5000}
5001
5002/**
5003 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5004 * @adapter: board private structure to initialize
5005 *
5006 * This function frees the memory allocated to the q_vectors. In addition if
5007 * NAPI is enabled it will delete any references to the NAPI struct prior
5008 * to freeing the q_vector.
5009 **/
5010static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5011{
5012 int q_idx, num_q_vectors;
7a921c93 5013
91281fd3 5014 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 5015 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5016 else
7a921c93 5017 num_q_vectors = 1;
7a921c93
AD		 5018
5019 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5020 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 5021 adapter->q_vector[q_idx] = NULL;
91281fd3 5022 netif_napi_del(&q_vector->napi);
7a921c93
AD		 5023 kfree(q_vector);
5024 }
5025}
5026
7b25cdba 5027static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5028{
5029 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5030 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5031 pci_disable_msix(adapter->pdev);
5032 kfree(adapter->msix_entries);
5033 adapter->msix_entries = NULL;
5034 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5035 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5036 pci_disable_msi(adapter->pdev);
5037 }
021230d4
AV		 5038}
5039
5040/**
5041 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5042 * @adapter: board private structure to initialize
5043 *
5044 * We determine which interrupt scheme to use based on...
5045 * - Kernel support (MSI, MSI-X)
5046 * - which can be user-defined (via MODULE_PARAM)
5047 * - Hardware queue count (num_*_queues)
5048 * - defined by miscellaneous hardware support/features (RSS, etc.)
5049 **/
2f90b865 5050int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5051{
5052 int err;
5053
5054 /* Number of supported queues */
847f53ff
BH		 5055 err = ixgbe_set_num_queues(adapter);
5056 if (err)
5057 return err;
021230d4 5058
021230d4
AV		 5059 err = ixgbe_set_interrupt_capability(adapter);
5060 if (err) {
849c4542 5061 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5062 goto err_set_interrupt;
9a799d71
AK		 5063 }
5064
7a921c93
AD		 5065 err = ixgbe_alloc_q_vectors(adapter);
5066 if (err) {
849c4542 5067 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5068 goto err_alloc_q_vectors;
5069 }
5070
5071 err = ixgbe_alloc_queues(adapter);
5072 if (err) {
849c4542 5073 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5074 goto err_alloc_queues;
5075 }
5076
849c4542 5077 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5078 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5079 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5080
5081 set_bit(__IXGBE_DOWN, &adapter->state);
5082
9a799d71 5083 return 0;
021230d4 5084
7a921c93
AD		 5085err_alloc_queues:
5086 ixgbe_free_q_vectors(adapter);
5087err_alloc_q_vectors:
5088 ixgbe_reset_interrupt_capability(adapter);
021230d4 5089err_set_interrupt:
7a921c93
AD		 5090 return err;
5091}
5092
1a51502b
ED		 5093static void ring_free_rcu(struct rcu_head *head)
5094{
5095 kfree(container_of(head, struct ixgbe_ring, rcu));
5096}
5097
7a921c93
AD		 5098/**
5099 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5100 * @adapter: board private structure to clear interrupt scheme on
5101 *
5102 * We go through and clear interrupt specific resources and reset the structure
5103 * to pre-load conditions
5104 **/
5105void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5106{
4a0b9ca0
PW		 5107 int i;
5108
5109 for (i = 0; i < adapter->num_tx_queues; i++) {
5110 kfree(adapter->tx_ring[i]);
5111 adapter->tx_ring[i] = NULL;
5112 }
5113 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5114 struct ixgbe_ring *ring = adapter->rx_ring[i];
5115
5116 /* ixgbe_get_stats64() might access this ring, we must wait
5117 * a grace period before freeing it.
5118 */
5119 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 5120 adapter->rx_ring[i] = NULL;
5121 }
7a921c93 5122
b8eb3a10
DS		 5123 adapter->num_tx_queues = 0;
5124 adapter->num_rx_queues = 0;
5125
7a921c93
AD		 5126 ixgbe_free_q_vectors(adapter);
5127 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5128}
5129
c4900be0
DS		 5130/**
5131 * ixgbe_sfp_timer - worker thread to find a missing module
5132 * @data: pointer to our adapter struct
5133 **/
5134static void ixgbe_sfp_timer(unsigned long data)
5135{
5136 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5137
4df10466
JB		 5138 /*
5139 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 5140 * delays that sfp+ detection requires
5141 */
5142 schedule_work(&adapter->sfp_task);
5143}
5144
5145/**
5146 * ixgbe_sfp_task - worker thread to find a missing module
5147 * @work: pointer to work_struct containing our data
5148 **/
5149static void ixgbe_sfp_task(struct work_struct *work)
5150{
5151 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5152 struct ixgbe_adapter,
5153 sfp_task);
c4900be0
DS		 5154 struct ixgbe_hw *hw = &adapter->hw;
5155
5156 if ((hw->phy.type == ixgbe_phy_nl) &&
5157 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5158 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5159 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 5160 goto reschedule;
5161 ret = hw->phy.ops.reset(hw);
5162 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5163 e_dev_err("failed to initialize because an unsupported "
5164 "SFP+ module type was detected.\n");
5165 e_dev_err("Reload the driver after installing a "
5166 "supported module.\n");
c4900be0
DS		 5167 unregister_netdev(adapter->netdev);
5168 } else {
396e799c 5169 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 5170 }
5171 /* don't need this routine any more */
5172 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5173 }
5174 return;
5175reschedule:
5176 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5177 mod_timer(&adapter->sfp_timer,
e8e9f696 5178 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 5179}
5180
9a799d71
AK		 5181/**
5182 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5183 * @adapter: board private structure to initialize
5184 *
5185 * ixgbe_sw_init initializes the Adapter private data structure.
5186 * Fields are initialized based on PCI device information and
5187 * OS network device settings (MTU size).
5188 **/
5189static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5190{
5191 struct ixgbe_hw *hw = &adapter->hw;
5192 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5193 struct net_device *dev = adapter->netdev;
021230d4 5194 unsigned int rss;
7a6b6f51 5195#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5196 int j;
5197 struct tc_configuration *tc;
5198#endif
16b61beb 5199 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5200
c44ade9e
JB		 5201 /* PCI config space info */
5202
5203 hw->vendor_id = pdev->vendor;
5204 hw->device_id = pdev->device;
5205 hw->revision_id = pdev->revision;
5206 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5207 hw->subsystem_device_id = pdev->subsystem_device;
5208
021230d4
AV		 5209 /* Set capability flags */
5210 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5211 adapter->ring_feature[RING_F_RSS].indices = rss;
5212 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 5213 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bd508178
AD		 5214 switch (hw->mac.type) {
5215 case ixgbe_mac_82598EB:
bf069c97
DS		 5216 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5217 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5218 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5219 break;
5220 case ixgbe_mac_82599EB:
b93a2226 5221 case ixgbe_mac_X540:
e8e26350 5222 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5223 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5224 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5225 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5226 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5227 /* n-tuple support exists, always init our spinlock */
5228 spin_lock_init(&adapter->fdir_perfect_lock);
5229 /* Flow Director hash filters enabled */
5230 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5231 adapter->atr_sample_rate = 20;
c4cf55e5 5232 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5233 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 5234 adapter->fdir_pballoc = 0;
eacd73f7 5235#ifdef IXGBE_FCOE
0d551589
YZ		 5236 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5237 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5238 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5239#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 5240 /* Default traffic class to use for FCoE */
5241 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 5242 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5243#endif
eacd73f7 5244#endif /* IXGBE_FCOE */
bd508178
AD		 5245 break;
5246 default:
5247 break;
f8212f97 5248 }
2f90b865 5249
7a6b6f51 5250#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5251 /* Configure DCB traffic classes */
5252 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5253 tc = &adapter->dcb_cfg.tc_config[j];
5254 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5255 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5256 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5257 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5258 tc->dcb_pfc = pfc_disabled;
5259 }
5260 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5261 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5262 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 5263 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5264 adapter->dcb_set_bitmap = 0x00;
3032309b 5265 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5266 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5267 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5268
5269#endif
9a799d71
AK		 5270
5271 /* default flow control settings */
cd7664f6 5272 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5273 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5274#ifdef CONFIG_DCB
5275 adapter->last_lfc_mode = hw->fc.current_mode;
5276#endif
16b61beb
JF		 5277 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5278 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5279 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5280 hw->fc.send_xon = true;
71fd570b 5281 hw->fc.disable_fc_autoneg = false;
9a799d71 5282
30efa5a3 5283 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5284 adapter->rx_itr_setting = 1;
5285 adapter->rx_eitr_param = 20000;
5286 adapter->tx_itr_setting = 1;
5287 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5288
5289 /* set defaults for eitr in MegaBytes */
5290 adapter->eitr_low = 10;
5291 adapter->eitr_high = 20;
5292
5293 /* set default ring sizes */
5294 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5295 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5296
9a799d71 5297 /* initialize eeprom parameters */
c44ade9e 5298 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5299 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5300 return -EIO;
5301 }
5302
021230d4 5303 /* enable rx csum by default */
9a799d71
AK		 5304 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5305
1a6c14a2
JB		 5306 /* get assigned NUMA node */
5307 adapter->node = dev_to_node(&pdev->dev);
5308
9a799d71
AK		 5309 set_bit(__IXGBE_DOWN, &adapter->state);
5310
5311 return 0;
5312}
5313
5314/**
5315 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5316 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5317 *
5318 * Return 0 on success, negative on failure
5319 **/
b6ec895e 5320int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5321{
b6ec895e 5322 struct device *dev = tx_ring->dev;
9a799d71
AK		 5323 int size;
5324
3a581073 5325 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5326 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5327 if (!tx_ring->tx_buffer_info)
89bf67f1 5328 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5329 if (!tx_ring->tx_buffer_info)
5330 goto err;
9a799d71
AK		 5331
5332 /* round up to nearest 4K */
12207e49 5333 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5334 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5335
b6ec895e 5336 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5337 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5338 if (!tx_ring->desc)
5339 goto err;
9a799d71 5340
3a581073
JB		 5341 tx_ring->next_to_use = 0;
5342 tx_ring->next_to_clean = 0;
5343 tx_ring->work_limit = tx_ring->count;
9a799d71 5344 return 0;
e01c31a5
JB		 5345
5346err:
5347 vfree(tx_ring->tx_buffer_info);
5348 tx_ring->tx_buffer_info = NULL;
b6ec895e 5349 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5350 return -ENOMEM;
9a799d71
AK		 5351}
5352
69888674
AD		 5353/**
5354 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5355 * @adapter: board private structure
5356 *
5357 * If this function returns with an error, then it's possible one or
5358 * more of the rings is populated (while the rest are not). It is the
5359 * callers duty to clean those orphaned rings.
5360 *
5361 * Return 0 on success, negative on failure
5362 **/
5363static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5364{
5365 int i, err = 0;
5366
5367 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5368 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5369 if (!err)
5370 continue;
396e799c 5371 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5372 break;
5373 }
5374
5375 return err;
5376}
5377
9a799d71
AK		 5378/**
5379 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5380 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5381 *
5382 * Returns 0 on success, negative on failure
5383 **/
b6ec895e 5384int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5385{
b6ec895e 5386 struct device *dev = rx_ring->dev;
021230d4 5387 int size;
9a799d71 5388
3a581073 5389 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5390 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5391 if (!rx_ring->rx_buffer_info)
89bf67f1 5392 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5393 if (!rx_ring->rx_buffer_info)
5394 goto err;
9a799d71 5395
9a799d71 5396 /* Round up to nearest 4K */
3a581073
JB		 5397 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5398 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5399
b6ec895e 5400 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5401 &rx_ring->dma, GFP_KERNEL);
9a799d71 5402
b6ec895e
AD		 5403 if (!rx_ring->desc)
5404 goto err;
9a799d71 5405
3a581073
JB		 5406 rx_ring->next_to_clean = 0;
5407 rx_ring->next_to_use = 0;
9a799d71
AK		 5408
5409 return 0;
b6ec895e
AD		 5410err:
5411 vfree(rx_ring->rx_buffer_info);
5412 rx_ring->rx_buffer_info = NULL;
5413 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5414 return -ENOMEM;
9a799d71
AK		 5415}
5416
69888674
AD		 5417/**
5418 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5419 * @adapter: board private structure
5420 *
5421 * If this function returns with an error, then it's possible one or
5422 * more of the rings is populated (while the rest are not). It is the
5423 * callers duty to clean those orphaned rings.
5424 *
5425 * Return 0 on success, negative on failure
5426 **/
69888674
AD		 5427static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5428{
5429 int i, err = 0;
5430
5431 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5432 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5433 if (!err)
5434 continue;
396e799c 5435 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5436 break;
5437 }
5438
5439 return err;
5440}
5441
9a799d71
AK		 5442/**
5443 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5444 * @tx_ring: Tx descriptor ring for a specific queue
5445 *
5446 * Free all transmit software resources
5447 **/
b6ec895e 5448void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5449{
b6ec895e 5450 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5451
5452 vfree(tx_ring->tx_buffer_info);
5453 tx_ring->tx_buffer_info = NULL;
5454
b6ec895e
AD		 5455 /* if not set, then don't free */
5456 if (!tx_ring->desc)
5457 return;
5458
5459 dma_free_coherent(tx_ring->dev, tx_ring->size,
5460 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5461
5462 tx_ring->desc = NULL;
5463}
5464
5465/**
5466 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5467 * @adapter: board private structure
5468 *
5469 * Free all transmit software resources
5470 **/
5471static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5472{
5473 int i;
5474
5475 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5476 if (adapter->tx_ring[i]->desc)
b6ec895e 5477 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5478}
5479
5480/**
b4617240 5481 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5482 * @rx_ring: ring to clean the resources from
5483 *
5484 * Free all receive software resources
5485 **/
b6ec895e 5486void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5487{
b6ec895e 5488 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5489
5490 vfree(rx_ring->rx_buffer_info);
5491 rx_ring->rx_buffer_info = NULL;
5492
b6ec895e
AD		 5493 /* if not set, then don't free */
5494 if (!rx_ring->desc)
5495 return;
5496
5497 dma_free_coherent(rx_ring->dev, rx_ring->size,
5498 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5499
5500 rx_ring->desc = NULL;
5501}
5502
5503/**
5504 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5505 * @adapter: board private structure
5506 *
5507 * Free all receive software resources
5508 **/
5509static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5510{
5511 int i;
5512
5513 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5514 if (adapter->rx_ring[i]->desc)
b6ec895e 5515 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5516}
5517
9a799d71
AK		 5518/**
5519 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5520 * @netdev: network interface device structure
5521 * @new_mtu: new value for maximum frame size
5522 *
5523 * Returns 0 on success, negative on failure
5524 **/
5525static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5526{
5527 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5528 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5529 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5530
42c783c5 5531 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5532 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5533 hw->mac.type != ixgbe_mac_X540) {
5534 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5535 return -EINVAL;
5536 } else {
5537 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5538 return -EINVAL;
5539 }
9a799d71 5540
396e799c 5541 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5542 /* must set new MTU before calling down or up */
9a799d71
AK		 5543 netdev->mtu = new_mtu;
5544
16b61beb
JF		 5545 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5546 hw->fc.low_water = FC_LOW_WATER(max_frame);
5547
d4f80882
AV		 5548 if (netif_running(netdev))
5549 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5550
5551 return 0;
5552}
5553
5554/**
5555 * ixgbe_open - Called when a network interface is made active
5556 * @netdev: network interface device structure
5557 *
5558 * Returns 0 on success, negative value on failure
5559 *
5560 * The open entry point is called when a network interface is made
5561 * active by the system (IFF_UP). At this point all resources needed
5562 * for transmit and receive operations are allocated, the interrupt
5563 * handler is registered with the OS, the watchdog timer is started,
5564 * and the stack is notified that the interface is ready.
5565 **/
5566static int ixgbe_open(struct net_device *netdev)
5567{
5568 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5569 int err;
4bebfaa5
AK		 5570
5571 /* disallow open during test */
5572 if (test_bit(__IXGBE_TESTING, &adapter->state))
5573 return -EBUSY;
9a799d71 5574
54386467
JB		 5575 netif_carrier_off(netdev);
5576
9a799d71
AK		 5577 /* allocate transmit descriptors */
5578 err = ixgbe_setup_all_tx_resources(adapter);
5579 if (err)
5580 goto err_setup_tx;
5581
9a799d71
AK		 5582 /* allocate receive descriptors */
5583 err = ixgbe_setup_all_rx_resources(adapter);
5584 if (err)
5585 goto err_setup_rx;
5586
5587 ixgbe_configure(adapter);
5588
021230d4 5589 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5590 if (err)
5591 goto err_req_irq;
5592
9a799d71
AK		 5593 err = ixgbe_up_complete(adapter);
5594 if (err)
5595 goto err_up;
5596
d55b53ff
JK		 5597 netif_tx_start_all_queues(netdev);
5598
9a799d71
AK		 5599 return 0;
5600
5601err_up:
5eba3699 5602 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5603 ixgbe_free_irq(adapter);
5604err_req_irq:
9a799d71 5605err_setup_rx:
a20a1199 5606 ixgbe_free_all_rx_resources(adapter);
9a799d71 5607err_setup_tx:
a20a1199 5608 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5609 ixgbe_reset(adapter);
5610
5611 return err;
5612}
5613
5614/**
5615 * ixgbe_close - Disables a network interface
5616 * @netdev: network interface device structure
5617 *
5618 * Returns 0, this is not allowed to fail
5619 *
5620 * The close entry point is called when an interface is de-activated
5621 * by the OS. The hardware is still under the drivers control, but
5622 * needs to be disabled. A global MAC reset is issued to stop the
5623 * hardware, and all transmit and receive resources are freed.
5624 **/
5625static int ixgbe_close(struct net_device *netdev)
5626{
5627 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5628
5629 ixgbe_down(adapter);
5630 ixgbe_free_irq(adapter);
5631
5632 ixgbe_free_all_tx_resources(adapter);
5633 ixgbe_free_all_rx_resources(adapter);
5634
5eba3699 5635 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5636
5637 return 0;
5638}
5639
b3c8b4ba
AD		 5640#ifdef CONFIG_PM
5641static int ixgbe_resume(struct pci_dev *pdev)
5642{
c60fbb00
AD		 5643 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5644 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5645 u32 err;
5646
5647 pci_set_power_state(pdev, PCI_D0);
5648 pci_restore_state(pdev);
656ab817
DS		 5649 /*
5650 * pci_restore_state clears dev->state_saved so call
5651 * pci_save_state to restore it.
5652 */
5653 pci_save_state(pdev);
9ce77666 5654
5655 err = pci_enable_device_mem(pdev);
b3c8b4ba 5656 if (err) {
849c4542 5657 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5658 return err;
5659 }
5660 pci_set_master(pdev);
5661
dd4d8ca6 5662 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5663
5664 err = ixgbe_init_interrupt_scheme(adapter);
5665 if (err) {
849c4542 5666 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5667 return err;
5668 }
5669
b3c8b4ba
AD		 5670 ixgbe_reset(adapter);
5671
495dce12
WJP		 5672 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5673
b3c8b4ba 5674 if (netif_running(netdev)) {
c60fbb00 5675 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5676 if (err)
5677 return err;
5678 }
5679
5680 netif_device_attach(netdev);
5681
5682 return 0;
5683}
b3c8b4ba 5684#endif /* CONFIG_PM */
9d8d05ae
RW		 5685
5686static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5687{
c60fbb00
AD		 5688 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5689 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5690 struct ixgbe_hw *hw = &adapter->hw;
5691 u32 ctrl, fctrl;
5692 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5693#ifdef CONFIG_PM
5694 int retval = 0;
5695#endif
5696
5697 netif_device_detach(netdev);
5698
5699 if (netif_running(netdev)) {
5700 ixgbe_down(adapter);
5701 ixgbe_free_irq(adapter);
5702 ixgbe_free_all_tx_resources(adapter);
5703 ixgbe_free_all_rx_resources(adapter);
5704 }
b3c8b4ba 5705
5f5ae6fc 5706 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5707#ifdef CONFIG_DCB
5708 kfree(adapter->ixgbe_ieee_pfc);
5709 kfree(adapter->ixgbe_ieee_ets);
5710#endif
5f5ae6fc 5711
b3c8b4ba
AD		 5712#ifdef CONFIG_PM
5713 retval = pci_save_state(pdev);
5714 if (retval)
5715 return retval;
4df10466 5716
b3c8b4ba 5717#endif
e8e26350
PW		 5718 if (wufc) {
5719 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5720
e8e26350
PW		 5721 /* turn on all-multi mode if wake on multicast is enabled */
5722 if (wufc & IXGBE_WUFC_MC) {
5723 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5724 fctrl |= IXGBE_FCTRL_MPE;
5725 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5726 }
5727
5728 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5729 ctrl |= IXGBE_CTRL_GIO_DIS;
5730 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5731
5732 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5733 } else {
5734 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5735 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5736 }
5737
bd508178
AD		 5738 switch (hw->mac.type) {
5739 case ixgbe_mac_82598EB:
dd4d8ca6 5740 pci_wake_from_d3(pdev, false);
bd508178
AD		 5741 break;
5742 case ixgbe_mac_82599EB:
b93a2226 5743 case ixgbe_mac_X540:
bd508178
AD		 5744 pci_wake_from_d3(pdev, !!wufc);
5745 break;
5746 default:
5747 break;
5748 }
b3c8b4ba 5749
9d8d05ae
RW		 5750 *enable_wake = !!wufc;
5751
b3c8b4ba
AD		 5752 ixgbe_release_hw_control(adapter);
5753
5754 pci_disable_device(pdev);
5755
9d8d05ae
RW		 5756 return 0;
5757}
5758
5759#ifdef CONFIG_PM
5760static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5761{
5762 int retval;
5763 bool wake;
5764
5765 retval = __ixgbe_shutdown(pdev, &wake);
5766 if (retval)
5767 return retval;
5768
5769 if (wake) {
5770 pci_prepare_to_sleep(pdev);
5771 } else {
5772 pci_wake_from_d3(pdev, false);
5773 pci_set_power_state(pdev, PCI_D3hot);
5774 }
b3c8b4ba
AD		 5775
5776 return 0;
5777}
9d8d05ae 5778#endif /* CONFIG_PM */
b3c8b4ba
AD		 5779
5780static void ixgbe_shutdown(struct pci_dev *pdev)
5781{
9d8d05ae
RW		 5782 bool wake;
5783
5784 __ixgbe_shutdown(pdev, &wake);
5785
5786 if (system_state == SYSTEM_POWER_OFF) {
5787 pci_wake_from_d3(pdev, wake);
5788 pci_set_power_state(pdev, PCI_D3hot);
5789 }
b3c8b4ba
AD		 5790}
5791
9a799d71
AK		 5792/**
5793 * ixgbe_update_stats - Update the board statistics counters.
5794 * @adapter: board private structure
5795 **/
5796void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5797{
2d86f139 5798 struct net_device *netdev = adapter->netdev;
9a799d71 5799 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5800 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5801 u64 total_mpc = 0;
5802 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5803 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5804 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5805 u64 bytes = 0, packets = 0;
9a799d71 5806
d08935c2
DS		 5807 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5808 test_bit(__IXGBE_RESETTING, &adapter->state))
5809 return;
5810
94b982b2 5811 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5812 u64 rsc_count = 0;
94b982b2 5813 u64 rsc_flush = 0;
d51019a4
PW		 5814 for (i = 0; i < 16; i++)
5815 adapter->hw_rx_no_dma_resources +=
7ca647bd 5816 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5817 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5818 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5819 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5820 }
5821 adapter->rsc_total_count = rsc_count;
5822 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5823 }
5824
5b7da515
AD		 5825 for (i = 0; i < adapter->num_rx_queues; i++) {
5826 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5827 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5828 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5829 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5830 bytes += rx_ring->stats.bytes;
5831 packets += rx_ring->stats.packets;
5832 }
5833 adapter->non_eop_descs = non_eop_descs;
5834 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5835 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5836 netdev->stats.rx_bytes = bytes;
5837 netdev->stats.rx_packets = packets;
5838
5839 bytes = 0;
5840 packets = 0;
7ca3bc58 5841 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5842 for (i = 0; i < adapter->num_tx_queues; i++) {
5843 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5844 restart_queue += tx_ring->tx_stats.restart_queue;
5845 tx_busy += tx_ring->tx_stats.tx_busy;
5846 bytes += tx_ring->stats.bytes;
5847 packets += tx_ring->stats.packets;
5848 }
eb985f09 5849 adapter->restart_queue = restart_queue;
5b7da515
AD		 5850 adapter->tx_busy = tx_busy;
5851 netdev->stats.tx_bytes = bytes;
5852 netdev->stats.tx_packets = packets;
7ca3bc58 5853
7ca647bd 5854 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5855 for (i = 0; i < 8; i++) {
5856 /* for packet buffers not used, the register should read 0 */
5857 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5858 missed_rx += mpc;
7ca647bd
JP		 5859 hwstats->mpc[i] += mpc;
5860 total_mpc += hwstats->mpc[i];
e8e26350 5861 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5862 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5863 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5864 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5865 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5866 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5867 switch (hw->mac.type) {
5868 case ixgbe_mac_82598EB:
7ca647bd
JP		 5869 hwstats->pxonrxc[i] +=
5870 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5871 break;
5872 case ixgbe_mac_82599EB:
b93a2226 5873 case ixgbe_mac_X540:
bd508178
AD		 5874 hwstats->pxonrxc[i] +=
5875 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5876 break;
5877 default:
5878 break;
e8e26350 5879 }
7ca647bd
JP		 5880 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5881 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5882 }
7ca647bd 5883 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5884 /* work around hardware counting issue */
7ca647bd 5885 hwstats->gprc -= missed_rx;
6f11eef7 5886
c84d324c
JF		 5887 ixgbe_update_xoff_received(adapter);
5888
6f11eef7 5889 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5890 switch (hw->mac.type) {
5891 case ixgbe_mac_82598EB:
5892 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5893 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5894 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5895 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5896 break;
5897 case ixgbe_mac_82599EB:
b93a2226 5898 case ixgbe_mac_X540:
7ca647bd 5899 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5900 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5901 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5902 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5903 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5904 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5905 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5906 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5907 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5908#ifdef IXGBE_FCOE
7ca647bd
JP		 5909 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5910 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5911 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5912 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5913 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5914 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5915#endif /* IXGBE_FCOE */
bd508178
AD		 5916 break;
5917 default:
5918 break;
e8e26350 5919 }
9a799d71 5920 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5921 hwstats->bprc += bprc;
5922 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5923 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5924 hwstats->mprc -= bprc;
5925 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5926 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5927 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5928 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5929 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5930 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5931 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5932 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5933 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5934 hwstats->lxontxc += lxon;
6f11eef7 5935 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5936 hwstats->lxofftxc += lxoff;
5937 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5938 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5939 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5940 /*
5941 * 82598 errata - tx of flow control packets is included in tx counters
5942 */
5943 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5944 hwstats->gptc -= xon_off_tot;
5945 hwstats->mptc -= xon_off_tot;
5946 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5947 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5948 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5949 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5950 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5951 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5952 hwstats->ptc64 -= xon_off_tot;
5953 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5954 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5955 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5956 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5957 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5958 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5959
5960 /* Fill out the OS statistics structure */
7ca647bd 5961 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5962
5963 /* Rx Errors */
7ca647bd 5964 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5965 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5966 netdev->stats.rx_length_errors = hwstats->rlec;
5967 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5968 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5969}
5970
5971/**
5972 * ixgbe_watchdog - Timer Call-back
5973 * @data: pointer to adapter cast into an unsigned long
5974 **/
5975static void ixgbe_watchdog(unsigned long data)
5976{
5977 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5978 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5979 u64 eics = 0;
5980 int i;
cf8280ee 5981
fe49f04a
AD		 5982 /*
5983 * Do the watchdog outside of interrupt context due to the lovely
5984 * delays that some of the newer hardware requires
5985 */
22d5a71b 5986
fe49f04a
AD		 5987 if (test_bit(__IXGBE_DOWN, &adapter->state))
5988 goto watchdog_short_circuit;
22d5a71b 5989
fe49f04a
AD		 5990 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5991 /*
5992 * for legacy and MSI interrupts don't set any bits
5993 * that are enabled for EIAM, because this operation
5994 * would set *both* EIMS and EICS for any bit in EIAM
5995 */
5996 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5997 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5998 goto watchdog_reschedule;
5999 }
6000
6001 /* get one bit for every active tx/rx interrupt vector */
6002 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6003 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6004 if (qv->rxr_count || qv->txr_count)
6005 eics |= ((u64)1 << i);
cf8280ee 6006 }
9a799d71 6007
fe49f04a
AD		 6008 /* Cause software interrupt to ensure rx rings are cleaned */
6009 ixgbe_irq_rearm_queues(adapter, eics);
6010
6011watchdog_reschedule:
6012 /* Reset the timer */
6013 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
6014
6015watchdog_short_circuit:
cf8280ee
JB		 6016 schedule_work(&adapter->watchdog_task);
6017}
6018
e8e26350
PW		 6019/**
6020 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
6021 * @work: pointer to work_struct containing our data
6022 **/
6023static void ixgbe_multispeed_fiber_task(struct work_struct *work)
6024{
6025 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6026 struct ixgbe_adapter,
6027 multispeed_fiber_task);
e8e26350
PW		 6028 struct ixgbe_hw *hw = &adapter->hw;
6029 u32 autoneg;
8620a103 6030 bool negotiation;
e8e26350
PW		 6031
6032 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 6033 autoneg = hw->phy.autoneg_advertised;
6034 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 6035 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 6036 hw->mac.autotry_restart = false;
8620a103
MC		 6037 if (hw->mac.ops.setup_link)
6038 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 6039 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6040 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
6041}
6042
6043/**
6044 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
6045 * @work: pointer to work_struct containing our data
6046 **/
6047static void ixgbe_sfp_config_module_task(struct work_struct *work)
6048{
6049 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6050 struct ixgbe_adapter,
6051 sfp_config_module_task);
e8e26350
PW		 6052 struct ixgbe_hw *hw = &adapter->hw;
6053 u32 err;
6054
6055 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 6056
6057 /* Time for electrical oscillations to settle down */
6058 msleep(100);
e8e26350 6059 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 6060
e8e26350 6061 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6062 e_dev_err("failed to initialize because an unsupported SFP+ "
6063 "module type was detected.\n");
6064 e_dev_err("Reload the driver after installing a supported "
6065 "module.\n");
63d6e1d8 6066 unregister_netdev(adapter->netdev);
e8e26350
PW		 6067 return;
6068 }
4c7e604b
AG		 6069 if (hw->mac.ops.setup_sfp)
6070 hw->mac.ops.setup_sfp(hw);
e8e26350 6071
8d1c3c07 6072 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 6073 /* This will also work for DA Twinax connections */
6074 schedule_work(&adapter->multispeed_fiber_task);
6075 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
6076}
6077
c4cf55e5
PWJ		 6078/**
6079 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
6080 * @work: pointer to work_struct containing our data
6081 **/
6082static void ixgbe_fdir_reinit_task(struct work_struct *work)
6083{
6084 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6085 struct ixgbe_adapter,
6086 fdir_reinit_task);
c4cf55e5
PWJ		 6087 struct ixgbe_hw *hw = &adapter->hw;
6088 int i;
6089
6090 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6091 for (i = 0; i < adapter->num_tx_queues; i++)
7d637bcc
AD		 6092 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6093 &(adapter->tx_ring[i]->state));
c4cf55e5 6094 } else {
396e799c 6095 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 6096 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 6097 }
6098 /* Done FDIR Re-initialization, enable transmits */
6099 netif_tx_start_all_queues(adapter->netdev);
6100}
6101
a985b6c3
GR		 6102static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6103{
6104 u32 ssvpc;
6105
6106 /* Do not perform spoof check for 82598 */
6107 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6108 return;
6109
6110 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6111
6112 /*
6113 * ssvpc register is cleared on read, if zero then no
6114 * spoofed packets in the last interval.
6115 */
6116 if (!ssvpc)
6117 return;
6118
6119 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6120}
6121
10eec955
JF		 6122static DEFINE_MUTEX(ixgbe_watchdog_lock);
6123
cf8280ee 6124/**
69888674
AD		 6125 * ixgbe_watchdog_task - worker thread to bring link up
6126 * @work: pointer to work_struct containing our data
cf8280ee
JB		 6127 **/
6128static void ixgbe_watchdog_task(struct work_struct *work)
6129{
6130 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6131 struct ixgbe_adapter,
6132 watchdog_task);
cf8280ee
JB		 6133 struct net_device *netdev = adapter->netdev;
6134 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 6135 u32 link_speed;
6136 bool link_up;
bc59fcda
NS		 6137 int i;
6138 struct ixgbe_ring *tx_ring;
6139 int some_tx_pending = 0;
cf8280ee 6140
10eec955
JF		 6141 mutex_lock(&ixgbe_watchdog_lock);
6142
6143 link_up = adapter->link_up;
6144 link_speed = adapter->link_speed;
cf8280ee
JB		 6145
6146 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6147 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 6148 if (link_up) {
6149#ifdef CONFIG_DCB
6150 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6151 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 6152 hw->mac.ops.fc_enable(hw, i);
264857b8 6153 } else {
620fa036 6154 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 6155 }
6156#else
620fa036 6157 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 6158#endif
6159 }
6160
cf8280ee
JB		 6161 if (link_up ||
6162 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 6163 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 6164 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 6165 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 6166 }
6167 adapter->link_up = link_up;
6168 adapter->link_speed = link_speed;
6169 }
9a799d71
AK		 6170
6171 if (link_up) {
6172 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 6173 bool flow_rx, flow_tx;
6174
bd508178
AD		 6175 switch (hw->mac.type) {
6176 case ixgbe_mac_82598EB: {
e8e26350
PW		 6177 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6178 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 6179 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6180 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350 6181 }
bd508178 6182 break;
b93a2226
DS		 6183 case ixgbe_mac_82599EB:
6184 case ixgbe_mac_X540: {
bd508178
AD		 6185 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6186 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6187 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6188 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6189 }
6190 break;
6191 default:
6192 flow_tx = false;
6193 flow_rx = false;
6194 break;
6195 }
e8e26350 6196
396e799c 6197 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 6198 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 6199 "10 Gbps" :
6200 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
1b1c0a48
AS		 6201 "1 Gbps" :
6202 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6203 "100 Mbps" :
6204 "unknown speed"))),
e8e26350 6205 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 6206 (flow_rx ? "RX" :
6207 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 6208
6209 netif_carrier_on(netdev);
9a799d71
AK		 6210 } else {
6211 /* Force detection of hung controller */
7d637bcc
AD		 6212 for (i = 0; i < adapter->num_tx_queues; i++) {
6213 tx_ring = adapter->tx_ring[i];
6214 set_check_for_tx_hang(tx_ring);
6215 }
9a799d71
AK		 6216 }
6217 } else {
cf8280ee
JB		 6218 adapter->link_up = false;
6219 adapter->link_speed = 0;
9a799d71 6220 if (netif_carrier_ok(netdev)) {
396e799c 6221 e_info(drv, "NIC Link is Down\n");
9a799d71 6222 netif_carrier_off(netdev);
9a799d71
AK		 6223 }
6224 }
6225
bc59fcda
NS		 6226 if (!netif_carrier_ok(netdev)) {
6227 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 6228 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6229 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6230 some_tx_pending = 1;
6231 break;
6232 }
6233 }
6234
6235 if (some_tx_pending) {
6236 /* We've lost link, so the controller stops DMA,
6237 * but we've got queued Tx work that's never going
6238 * to get done, so reset controller to flush Tx.
6239 * (Do the reset outside of interrupt context).
6240 */
6241 schedule_work(&adapter->reset_task);
6242 }
6243 }
6244
a985b6c3 6245 ixgbe_spoof_check(adapter);
9a799d71 6246 ixgbe_update_stats(adapter);
10eec955 6247 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 6248}
6249
9a799d71 6250static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 6251 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 6252 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 6253{
6254 struct ixgbe_adv_tx_context_desc *context_desc;
6255 unsigned int i;
6256 int err;
6257 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 6258 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6259 u32 mss_l4len_idx, l4len;
9a799d71
AK		 6260
6261 if (skb_is_gso(skb)) {
6262 if (skb_header_cloned(skb)) {
6263 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6264 if (err)
6265 return err;
6266 }
6267 l4len = tcp_hdrlen(skb);
6268 *hdr_len += l4len;
6269
5e09a105 6270 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 6271 struct iphdr *iph = ip_hdr(skb);
6272 iph->tot_len = 0;
6273 iph->check = 0;
6274 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 6275 iph->daddr, 0,
6276 IPPROTO_TCP,
6277 0);
8e1e8a47 6278 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 6279 ipv6_hdr(skb)->payload_len = 0;
6280 tcp_hdr(skb)->check =
6281 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 6282 &ipv6_hdr(skb)->daddr,
6283 0, IPPROTO_TCP, 0);
9a799d71
AK		 6284 }
6285
6286 i = tx_ring->next_to_use;
6287
6288 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6289 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6290
6291 /* VLAN MACLEN IPLEN */
6292 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6293 vlan_macip_lens |=
6294 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6295 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6296 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6297 *hdr_len += skb_network_offset(skb);
6298 vlan_macip_lens |=
6299 (skb_transport_header(skb) - skb_network_header(skb));
6300 *hdr_len +=
6301 (skb_transport_header(skb) - skb_network_header(skb));
6302 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6303 context_desc->seqnum_seed = 0;
6304
6305 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6306 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6307 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6308
5e09a105 6309 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6310 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6311 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6312 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6313
6314 /* MSS L4LEN IDX */
9f8cdf4f 6315 mss_l4len_idx =
9a799d71
AK		 6316 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6317 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6318 /* use index 1 for TSO */
6319 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6320 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6321
6322 tx_buffer_info->time_stamp = jiffies;
6323 tx_buffer_info->next_to_watch = i;
6324
6325 i++;
6326 if (i == tx_ring->count)
6327 i = 0;
6328 tx_ring->next_to_use = i;
6329
6330 return true;
6331 }
6332 return false;
6333}
6334
5e09a105
HZ		 6335static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6336 __be16 protocol)
7ca647bd
JP		 6337{
6338 u32 rtn = 0;
7ca647bd
JP		 6339
6340 switch (protocol) {
6341 case cpu_to_be16(ETH_P_IP):
6342 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6343 switch (ip_hdr(skb)->protocol) {
6344 case IPPROTO_TCP:
6345 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6346 break;
6347 case IPPROTO_SCTP:
6348 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6349 break;
6350 }
6351 break;
6352 case cpu_to_be16(ETH_P_IPV6):
6353 /* XXX what about other V6 headers?? */
6354 switch (ipv6_hdr(skb)->nexthdr) {
6355 case IPPROTO_TCP:
6356 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6357 break;
6358 case IPPROTO_SCTP:
6359 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6360 break;
6361 }
6362 break;
6363 default:
6364 if (unlikely(net_ratelimit()))
6365 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6366 protocol);
7ca647bd
JP		 6367 break;
6368 }
6369
6370 return rtn;
6371}
6372
9a799d71 6373static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6374 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6375 struct sk_buff *skb, u32 tx_flags,
6376 __be16 protocol)
9a799d71
AK		 6377{
6378 struct ixgbe_adv_tx_context_desc *context_desc;
6379 unsigned int i;
6380 struct ixgbe_tx_buffer *tx_buffer_info;
6381 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6382
6383 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6384 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6385 i = tx_ring->next_to_use;
6386 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6387 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6388
6389 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6390 vlan_macip_lens |=
6391 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6392 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6393 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6394 if (skb->ip_summed == CHECKSUM_PARTIAL)
6395 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6396 skb_network_header(skb));
9a799d71
AK		 6397
6398 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6399 context_desc->seqnum_seed = 0;
6400
6401 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6402 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6403
7ca647bd 6404 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6405 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6406
6407 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6408 /* use index zero for tx checksum offload */
9a799d71
AK		 6409 context_desc->mss_l4len_idx = 0;
6410
6411 tx_buffer_info->time_stamp = jiffies;
6412 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6413
9a799d71
AK		 6414 i++;
6415 if (i == tx_ring->count)
6416 i = 0;
6417 tx_ring->next_to_use = i;
6418
6419 return true;
6420 }
9f8cdf4f 6421
9a799d71
AK		 6422 return false;
6423}
6424
6425static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6426 struct ixgbe_ring *tx_ring,
6427 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6428 unsigned int first, const u8 hdr_len)
9a799d71 6429{
b6ec895e 6430 struct device *dev = tx_ring->dev;
9a799d71 6431 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6432 unsigned int len;
6433 unsigned int total = skb->len;
9a799d71
AK		 6434 unsigned int offset = 0, size, count = 0, i;
6435 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6436 unsigned int f;
8ad494b0
AD		 6437 unsigned int bytecount = skb->len;
6438 u16 gso_segs = 1;
9a799d71
AK		 6439
6440 i = tx_ring->next_to_use;
6441
eacd73f7
YZ		 6442 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6443 /* excluding fcoe_crc_eof for FCoE */
6444 total -= sizeof(struct fcoe_crc_eof);
6445
6446 len = min(skb_headlen(skb), total);
9a799d71
AK		 6447 while (len) {
6448 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6449 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6450
6451 tx_buffer_info->length = size;
e5a43549 6452 tx_buffer_info->mapped_as_page = false;
b6ec895e 6453 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6454 skb->data + offset,
1b507730 6455 size, DMA_TO_DEVICE);
b6ec895e 6456 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6457 goto dma_error;
9a799d71
AK		 6458 tx_buffer_info->time_stamp = jiffies;
6459 tx_buffer_info->next_to_watch = i;
6460
6461 len -= size;
eacd73f7 6462 total -= size;
9a799d71
AK		 6463 offset += size;
6464 count++;
44df32c5
AD		 6465
6466 if (len) {
6467 i++;
6468 if (i == tx_ring->count)
6469 i = 0;
6470 }
9a799d71
AK		 6471 }
6472
6473 for (f = 0; f < nr_frags; f++) {
6474 struct skb_frag_struct *frag;
6475
6476 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6477 len = min((unsigned int)frag->size, total);
e5a43549 6478 offset = frag->page_offset;
9a799d71
AK		 6479
6480 while (len) {
44df32c5
AD		 6481 i++;
6482 if (i == tx_ring->count)
6483 i = 0;
6484
9a799d71
AK		 6485 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6486 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6487
6488 tx_buffer_info->length = size;
b6ec895e 6489 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6490 frag->page,
6491 offset, size,
1b507730 6492 DMA_TO_DEVICE);
e5a43549 6493 tx_buffer_info->mapped_as_page = true;
b6ec895e 6494 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6495 goto dma_error;
9a799d71
AK		 6496 tx_buffer_info->time_stamp = jiffies;
6497 tx_buffer_info->next_to_watch = i;
6498
6499 len -= size;
eacd73f7 6500 total -= size;
9a799d71
AK		 6501 offset += size;
6502 count++;
9a799d71 6503 }
eacd73f7
YZ		 6504 if (total == 0)
6505 break;
9a799d71 6506 }
44df32c5 6507
8ad494b0
AD		 6508 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6509 gso_segs = skb_shinfo(skb)->gso_segs;
6510#ifdef IXGBE_FCOE
6511 /* adjust for FCoE Sequence Offload */
6512 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6513 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6514 skb_shinfo(skb)->gso_size);
6515#endif /* IXGBE_FCOE */
6516 bytecount += (gso_segs - 1) * hdr_len;
6517
6518 /* multiply data chunks by size of headers */
6519 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6520 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6521 tx_ring->tx_buffer_info[i].skb = skb;
6522 tx_ring->tx_buffer_info[first].next_to_watch = i;
6523
e5a43549
AD		 6524 return count;
6525
6526dma_error:
849c4542 6527 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6528
6529 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6530 tx_buffer_info->dma = 0;
6531 tx_buffer_info->time_stamp = 0;
6532 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6533 if (count)
6534 count--;
e5a43549
AD		 6535
6536 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6537 while (count--) {
e8e9f696 6538 if (i == 0)
e5a43549 6539 i += tx_ring->count;
c1fa347f 6540 i--;
e5a43549 6541 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6542 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6543 }
6544
e44d38e1 6545 return 0;
9a799d71
AK		 6546}
6547
84ea2591 6548static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6549 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6550{
6551 union ixgbe_adv_tx_desc *tx_desc = NULL;
6552 struct ixgbe_tx_buffer *tx_buffer_info;
6553 u32 olinfo_status = 0, cmd_type_len = 0;
6554 unsigned int i;
6555 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6556
6557 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6558
6559 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6560
6561 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6562 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6563
6564 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6565 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6566
6567 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6568 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6569
4eeae6fd
PW		 6570 /* use index 1 context for tso */
6571 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6572 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6573 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6574 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6575
6576 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6577 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6578 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6579
eacd73f7
YZ		 6580 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6581 olinfo_status |= IXGBE_ADVTXD_CC;
6582 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6583 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6584 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6585 }
6586
9a799d71
AK		 6587 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6588
6589 i = tx_ring->next_to_use;
6590 while (count--) {
6591 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6592 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6593 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6594 tx_desc->read.cmd_type_len =
e8e9f696 6595 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6596 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6597 i++;
6598 if (i == tx_ring->count)
6599 i = 0;
6600 }
6601
6602 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6603
6604 /*
6605 * Force memory writes to complete before letting h/w
6606 * know there are new descriptors to fetch. (Only
6607 * applicable for weak-ordered memory model archs,
6608 * such as IA-64).
6609 */
6610 wmb();
6611
6612 tx_ring->next_to_use = i;
84ea2591 6613 writel(i, tx_ring->tail);
9a799d71
AK		 6614}
6615
69830529
AD		 6616static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6617 u32 tx_flags, __be16 protocol)
6618{
6619 struct ixgbe_q_vector *q_vector = ring->q_vector;
6620 union ixgbe_atr_hash_dword input = { .dword = 0 };
6621 union ixgbe_atr_hash_dword common = { .dword = 0 };
6622 union {
6623 unsigned char *network;
6624 struct iphdr *ipv4;
6625 struct ipv6hdr *ipv6;
6626 } hdr;
ee9e0f0b 6627 struct tcphdr *th;
905e4a41 6628 __be16 vlan_id;
c4cf55e5 6629
69830529
AD		 6630 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6631 if (!q_vector)
6632 return;
6633
6634 /* do nothing if sampling is disabled */
6635 if (!ring->atr_sample_rate)
d3ead241 6636 return;
c4cf55e5 6637
69830529 6638 ring->atr_count++;
c4cf55e5 6639
69830529
AD		 6640 /* snag network header to get L4 type and address */
6641 hdr.network = skb_network_header(skb);
6642
6643 /* Currently only IPv4/IPv6 with TCP is supported */
6644 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6645 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6646 (protocol != __constant_htons(ETH_P_IP) ||
6647 hdr.ipv4->protocol != IPPROTO_TCP))
6648 return;
ee9e0f0b
AD		 6649
6650 th = tcp_hdr(skb);
c4cf55e5 6651
69830529
AD		 6652 /* skip this packet since the socket is closing */
6653 if (th->fin)
6654 return;
6655
6656 /* sample on all syn packets or once every atr sample count */
6657 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6658 return;
6659
6660 /* reset sample count */
6661 ring->atr_count = 0;
6662
6663 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6664
6665 /*
6666 * src and dst are inverted, think how the receiver sees them
6667 *
6668 * The input is broken into two sections, a non-compressed section
6669 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6670 * is XORed together and stored in the compressed dword.
6671 */
6672 input.formatted.vlan_id = vlan_id;
6673
6674 /*
6675 * since src port and flex bytes occupy the same word XOR them together
6676 * and write the value to source port portion of compressed dword
6677 */
6678 if (vlan_id)
6679 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6680 else
6681 common.port.src ^= th->dest ^ protocol;
6682 common.port.dst ^= th->source;
6683
6684 if (protocol == __constant_htons(ETH_P_IP)) {
6685 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6686 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6687 } else {
6688 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6689 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6690 hdr.ipv6->saddr.s6_addr32[1] ^
6691 hdr.ipv6->saddr.s6_addr32[2] ^
6692 hdr.ipv6->saddr.s6_addr32[3] ^
6693 hdr.ipv6->daddr.s6_addr32[0] ^
6694 hdr.ipv6->daddr.s6_addr32[1] ^
6695 hdr.ipv6->daddr.s6_addr32[2] ^
6696 hdr.ipv6->daddr.s6_addr32[3];
6697 }
c4cf55e5
PWJ		 6698
6699 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6700 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6701 input, common, ring->queue_index);
c4cf55e5
PWJ		 6702}
6703
fc77dc3c 6704static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6705{
fc77dc3c 6706 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6707 /* Herbert's original patch had:
6708 * smp_mb__after_netif_stop_queue();
6709 * but since that doesn't exist yet, just open code it. */
6710 smp_mb();
6711
6712 /* We need to check again in a case another CPU has just
6713 * made room available. */
6714 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6715 return -EBUSY;
6716
6717 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6718 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6719 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6720 return 0;
6721}
6722
fc77dc3c 6723static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6724{
6725 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6726 return 0;
fc77dc3c 6727 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6728}
6729
09a3b1f8
SH		 6730static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6731{
6732 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6733 int txq = smp_processor_id();
56075a98 6734#ifdef IXGBE_FCOE
5e09a105
HZ		 6735 __be16 protocol;
6736
6737 protocol = vlan_get_protocol(skb);
6738
e5b64635
JF		 6739 if (((protocol == htons(ETH_P_FCOE)) ||
6740 (protocol == htons(ETH_P_FIP))) &&
6741 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6742 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6743 txq += adapter->ring_feature[RING_F_FCOE].mask;
6744 return txq;
56075a98
JF		 6745 }
6746#endif
6747
fdd3d631
KK		 6748 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6749 while (unlikely(txq >= dev->real_num_tx_queues))
6750 txq -= dev->real_num_tx_queues;
5f715823 6751 return txq;
fdd3d631 6752 }
c4cf55e5 6753
09a3b1f8
SH		 6754 return skb_tx_hash(dev, skb);
6755}
6756
fc77dc3c 6757netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6758 struct ixgbe_adapter *adapter,
6759 struct ixgbe_ring *tx_ring)
9a799d71 6760{
9a799d71
AK		 6761 unsigned int first;
6762 unsigned int tx_flags = 0;
30eba97a 6763 u8 hdr_len = 0;
5f715823 6764 int tso;
9a799d71
AK		 6765 int count = 0;
6766 unsigned int f;
5e09a105
HZ		 6767 __be16 protocol;
6768
6769 protocol = vlan_get_protocol(skb);
9f8cdf4f 6770
eab6d18d 6771 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6772 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6773 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6774 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
e5b64635 6775 tx_flags |= tx_ring->dcb_tc << 13;
2f90b865
AD		 6776 }
6777 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6778 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6779 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6780 skb->priority != TC_PRIO_CONTROL) {
e5b64635 6781 tx_flags |= tx_ring->dcb_tc << 13;
2ea186ae
JF		 6782 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6783 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6784 }
eacd73f7 6785
09ad1cc0 6786#ifdef IXGBE_FCOE
56075a98
JF		 6787 /* for FCoE with DCB, we force the priority to what
6788 * was specified by the switch */
6789 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
e5b64635
JF		 6790 (protocol == htons(ETH_P_FCOE)))
6791 tx_flags |= IXGBE_TX_FLAGS_FCOE;
ca77cd59
RL		 6792#endif
6793
eacd73f7 6794 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6795 if (skb_is_gso(skb) ||
6796 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6797 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6798 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6799 count++;
6800
9f8cdf4f
JB		 6801 count += TXD_USE_COUNT(skb_headlen(skb));
6802 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6803 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6804
fc77dc3c 6805 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6806 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6807 return NETDEV_TX_BUSY;
6808 }
9a799d71 6809
9a799d71 6810 first = tx_ring->next_to_use;
eacd73f7
YZ		 6811 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6812#ifdef IXGBE_FCOE
6813 /* setup tx offload for FCoE */
6814 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6815 if (tso < 0) {
6816 dev_kfree_skb_any(skb);
6817 return NETDEV_TX_OK;
6818 }
6819 if (tso)
6820 tx_flags |= IXGBE_TX_FLAGS_FSO;
6821#endif /* IXGBE_FCOE */
6822 } else {
5e09a105 6823 if (protocol == htons(ETH_P_IP))
eacd73f7 6824 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6825 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6826 protocol);
eacd73f7
YZ		 6827 if (tso < 0) {
6828 dev_kfree_skb_any(skb);
6829 return NETDEV_TX_OK;
6830 }
9a799d71 6831
eacd73f7
YZ		 6832 if (tso)
6833 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6834 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6835 protocol) &&
eacd73f7
YZ		 6836 (skb->ip_summed == CHECKSUM_PARTIAL))
6837 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6838 }
9a799d71 6839
8ad494b0 6840 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6841 if (count) {
c4cf55e5 6842 /* add the ATR filter if ATR is on */
69830529
AD		 6843 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6844 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
84ea2591 6845 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6846 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6847
44df32c5
AD		 6848 } else {
6849 dev_kfree_skb_any(skb);
6850 tx_ring->tx_buffer_info[first].time_stamp = 0;
6851 tx_ring->next_to_use = first;
6852 }
9a799d71
AK		 6853
6854 return NETDEV_TX_OK;
6855}
6856
84418e3b
AD		 6857static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6858{
6859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6860 struct ixgbe_ring *tx_ring;
6861
6862 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6863 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6864}
6865
9a799d71
AK		 6866/**
6867 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6868 * @netdev: network interface device structure
6869 * @p: pointer to an address structure
6870 *
6871 * Returns 0 on success, negative on failure
6872 **/
6873static int ixgbe_set_mac(struct net_device *netdev, void *p)
6874{
6875 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6876 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6877 struct sockaddr *addr = p;
6878
6879 if (!is_valid_ether_addr(addr->sa_data))
6880 return -EADDRNOTAVAIL;
6881
6882 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6883 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6884
1cdd1ec8
GR		 6885 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6886 IXGBE_RAH_AV);
9a799d71
AK		 6887
6888 return 0;
6889}
6890
6b73e10d
BH		 6891static int
6892ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6893{
6894 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6895 struct ixgbe_hw *hw = &adapter->hw;
6896 u16 value;
6897 int rc;
6898
6899 if (prtad != hw->phy.mdio.prtad)
6900 return -EINVAL;
6901 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6902 if (!rc)
6903 rc = value;
6904 return rc;
6905}
6906
6907static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6908 u16 addr, u16 value)
6909{
6910 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6911 struct ixgbe_hw *hw = &adapter->hw;
6912
6913 if (prtad != hw->phy.mdio.prtad)
6914 return -EINVAL;
6915 return hw->phy.ops.write_reg(hw, addr, devad, value);
6916}
6917
6918static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6919{
6920 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6921
6922 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6923}
6924
0365e6e4
PW		 6925/**
6926 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6927 * netdev->dev_addrs
0365e6e4
PW		 6928 * @netdev: network interface device structure
6929 *
6930 * Returns non-zero on failure
6931 **/
6932static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6933{
6934 int err = 0;
6935 struct ixgbe_adapter *adapter = netdev_priv(dev);
6936 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6937
6938 if (is_valid_ether_addr(mac->san_addr)) {
6939 rtnl_lock();
6940 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6941 rtnl_unlock();
6942 }
6943 return err;
6944}
6945
6946/**
6947 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6948 * netdev->dev_addrs
0365e6e4
PW		 6949 * @netdev: network interface device structure
6950 *
6951 * Returns non-zero on failure
6952 **/
6953static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6954{
6955 int err = 0;
6956 struct ixgbe_adapter *adapter = netdev_priv(dev);
6957 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6958
6959 if (is_valid_ether_addr(mac->san_addr)) {
6960 rtnl_lock();
6961 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6962 rtnl_unlock();
6963 }
6964 return err;
6965}
6966
9a799d71
AK		 6967#ifdef CONFIG_NET_POLL_CONTROLLER
6968/*
6969 * Polling 'interrupt' - used by things like netconsole to send skbs
6970 * without having to re-enable interrupts. It's not called while
6971 * the interrupt routine is executing.
6972 */
6973static void ixgbe_netpoll(struct net_device *netdev)
6974{
6975 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6976 int i;
9a799d71 6977
1a647bd2
AD		 6978 /* if interface is down do nothing */
6979 if (test_bit(__IXGBE_DOWN, &adapter->state))
6980 return;
6981
9a799d71 6982 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6983 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6984 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6985 for (i = 0; i < num_q_vectors; i++) {
6986 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6987 ixgbe_msix_clean_many(0, q_vector);
6988 }
6989 } else {
6990 ixgbe_intr(adapter->pdev->irq, netdev);
6991 }
9a799d71 6992 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6993}
6994#endif
6995
de1036b1
ED		 6996static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6997 struct rtnl_link_stats64 *stats)
6998{
6999 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7000 int i;
7001
1a51502b 7002 rcu_read_lock();
de1036b1 7003 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7004 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7005 u64 bytes, packets;
7006 unsigned int start;
7007
1a51502b
ED		 7008 if (ring) {
7009 do {
7010 start = u64_stats_fetch_begin_bh(&ring->syncp);
7011 packets = ring->stats.packets;
7012 bytes = ring->stats.bytes;
7013 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7014 stats->rx_packets += packets;
7015 stats->rx_bytes += bytes;
7016 }
de1036b1 7017 }
1ac9ad13
ED		 7018
7019 for (i = 0; i < adapter->num_tx_queues; i++) {
7020 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7021 u64 bytes, packets;
7022 unsigned int start;
7023
7024 if (ring) {
7025 do {
7026 start = u64_stats_fetch_begin_bh(&ring->syncp);
7027 packets = ring->stats.packets;
7028 bytes = ring->stats.bytes;
7029 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7030 stats->tx_packets += packets;
7031 stats->tx_bytes += bytes;
7032 }
7033 }
1a51502b 7034 rcu_read_unlock();
de1036b1
ED		 7035 /* following stats updated by ixgbe_watchdog_task() */
7036 stats->multicast = netdev->stats.multicast;
7037 stats->rx_errors = netdev->stats.rx_errors;
7038 stats->rx_length_errors = netdev->stats.rx_length_errors;
7039 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7040 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7041 return stats;
7042}
7043
7044
0edc3527 7045static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7046 .ndo_open = ixgbe_open,
0edc3527 7047 .ndo_stop = ixgbe_close,
00829823 7048 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7049 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7050 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7051 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7052 .ndo_validate_addr = eth_validate_addr,
7053 .ndo_set_mac_address = ixgbe_set_mac,
7054 .ndo_change_mtu = ixgbe_change_mtu,
7055 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7056 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7057 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7058 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7059 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7060 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7061 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7062 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7063 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3
JF		 7064#ifdef CONFIG_IXGBE_DCB
7065 .ndo_setup_tc = ixgbe_setup_tc,
7066#endif
0edc3527
SH		 7067#ifdef CONFIG_NET_POLL_CONTROLLER
7068 .ndo_poll_controller = ixgbe_netpoll,
7069#endif
332d4a7d
YZ		 7070#ifdef IXGBE_FCOE
7071 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7072 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7073 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7074 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7075 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7076 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7077#endif /* IXGBE_FCOE */
0edc3527
SH		 7078};
7079
1cdd1ec8
GR		 7080static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7081 const struct ixgbe_info *ii)
7082{
7083#ifdef CONFIG_PCI_IOV
7084 struct ixgbe_hw *hw = &adapter->hw;
7085 int err;
7086
3377eba7 7087 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7088 return;
7089
7090 /* The 82599 supports up to 64 VFs per physical function
7091 * but this implementation limits allocation to 63 so that
7092 * basic networking resources are still available to the
7093 * physical function
7094 */
7095 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7096 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7097 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7098 if (err) {
396e799c 7099 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7100 goto err_novfs;
7101 }
7102 /* If call to enable VFs succeeded then allocate memory
7103 * for per VF control structures.
7104 */
7105 adapter->vfinfo =
7106 kcalloc(adapter->num_vfs,
7107 sizeof(struct vf_data_storage), GFP_KERNEL);
7108 if (adapter->vfinfo) {
7109 /* Now that we're sure SR-IOV is enabled
7110 * and memory allocated set up the mailbox parameters
7111 */
7112 ixgbe_init_mbx_params_pf(hw);
7113 memcpy(&hw->mbx.ops, ii->mbx_ops,
7114 sizeof(hw->mbx.ops));
7115
7116 /* Disable RSC when in SR-IOV mode */
7117 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7118 IXGBE_FLAG2_RSC_ENABLED);
7119 return;
7120 }
7121
7122 /* Oh oh */
396e799c
ET		 7123 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7124 "SRIOV disabled\n");
1cdd1ec8
GR		 7125 pci_disable_sriov(adapter->pdev);
7126
7127err_novfs:
7128 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7129 adapter->num_vfs = 0;
7130#endif /* CONFIG_PCI_IOV */
7131}
7132
9a799d71
AK		 7133/**
7134 * ixgbe_probe - Device Initialization Routine
7135 * @pdev: PCI device information struct
7136 * @ent: entry in ixgbe_pci_tbl
7137 *
7138 * Returns 0 on success, negative on failure
7139 *
7140 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7141 * The OS initialization, configuring of the adapter private structure,
7142 * and a hardware reset occur.
7143 **/
7144static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7145 const struct pci_device_id *ent)
9a799d71
AK		 7146{
7147 struct net_device *netdev;
7148 struct ixgbe_adapter *adapter = NULL;
7149 struct ixgbe_hw *hw;
7150 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7151 static int cards_found;
7152 int i, err, pci_using_dac;
289700db 7153 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7154 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7155#ifdef IXGBE_FCOE
7156 u16 device_caps;
7157#endif
289700db 7158 u32 eec;
9a799d71 7159
bded64a7
AG		 7160 /* Catch broken hardware that put the wrong VF device ID in
7161 * the PCIe SR-IOV capability.
7162 */
7163 if (pdev->is_virtfn) {
7164 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7165 pci_name(pdev), pdev->vendor, pdev->device);
7166 return -EINVAL;
7167 }
7168
9ce77666 7169 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7170 if (err)
7171 return err;
7172
1b507730
NN		 7173 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7174 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7175 pci_using_dac = 1;
7176 } else {
1b507730 7177 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7178 if (err) {
1b507730
NN		 7179 err = dma_set_coherent_mask(&pdev->dev,
7180 DMA_BIT_MASK(32));
9a799d71 7181 if (err) {
b8bc0421
DC		 7182 dev_err(&pdev->dev,
7183 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7184 goto err_dma;
7185 }
7186 }
7187 pci_using_dac = 0;
7188 }
7189
9ce77666 7190 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7191 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7192 if (err) {
b8bc0421
DC		 7193 dev_err(&pdev->dev,
7194 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7195 goto err_pci_reg;
7196 }
7197
19d5afd4 7198 pci_enable_pcie_error_reporting(pdev);
6fabd715 7199
9a799d71 7200 pci_set_master(pdev);
fb3b27bc 7201 pci_save_state(pdev);
9a799d71 7202
c85a2618
JF		 7203 if (ii->mac == ixgbe_mac_82598EB)
7204 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7205 else
7206 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7207
e5b64635 7208#if defined(CONFIG_DCB)
c85a2618 7209 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
e5b64635 7210#elif defined(IXGBE_FCOE)
c85a2618
JF		 7211 indices += min_t(unsigned int, num_possible_cpus(),
7212 IXGBE_MAX_FCOE_INDICES);
7213#endif
c85a2618 7214 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7215 if (!netdev) {
7216 err = -ENOMEM;
7217 goto err_alloc_etherdev;
7218 }
7219
9a799d71
AK		 7220 SET_NETDEV_DEV(netdev, &pdev->dev);
7221
9a799d71 7222 adapter = netdev_priv(netdev);
c60fbb00 7223 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7224
7225 adapter->netdev = netdev;
7226 adapter->pdev = pdev;
7227 hw = &adapter->hw;
7228 hw->back = adapter;
7229 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7230
05857980 7231 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7232 pci_resource_len(pdev, 0));
9a799d71
AK		 7233 if (!hw->hw_addr) {
7234 err = -EIO;
7235 goto err_ioremap;
7236 }
7237
7238 for (i = 1; i <= 5; i++) {
7239 if (pci_resource_len(pdev, i) == 0)
7240 continue;
7241 }
7242
0edc3527 7243 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7244 ixgbe_set_ethtool_ops(netdev);
9a799d71 7245 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7246 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7247
9a799d71
AK		 7248 adapter->bd_number = cards_found;
7249
9a799d71
AK		 7250 /* Setup hw api */
7251 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7252 hw->mac.type = ii->mac;
9a799d71 7253
c44ade9e
JB		 7254 /* EEPROM */
7255 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7256 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7257 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7258 if (!(eec & (1 << 8)))
7259 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7260
7261 /* PHY */
7262 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7263 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7264 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7265 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7266 hw->phy.mdio.mmds = 0;
7267 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7268 hw->phy.mdio.dev = netdev;
7269 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7270 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 7271
7272 /* set up this timer and work struct before calling get_invariants
7273 * which might start the timer
7274 */
7275 init_timer(&adapter->sfp_timer);
c061b18d 7276 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 7277 adapter->sfp_timer.data = (unsigned long) adapter;
7278
7279 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 7280
e8e26350
PW		 7281 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7282 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7283
7284 /* a new SFP+ module arrival, called from GPI SDP2 context */
7285 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 7286 ixgbe_sfp_config_module_task);
e8e26350 7287
8ca783ab 7288 ii->get_invariants(hw);
9a799d71
AK		 7289
7290 /* setup the private structure */
7291 err = ixgbe_sw_init(adapter);
7292 if (err)
7293 goto err_sw_init;
7294
e86bff0e 7295 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7296 switch (adapter->hw.mac.type) {
7297 case ixgbe_mac_82599EB:
7298 case ixgbe_mac_X540:
e86bff0e 7299 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7300 break;
7301 default:
7302 break;
7303 }
e86bff0e 7304
bf069c97
DS		 7305 /*
7306 * If there is a fan on this device and it has failed log the
7307 * failure.
7308 */
7309 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7310 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7311 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7312 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7313 }
7314
c44ade9e 7315 /* reset_hw fills in the perm_addr as well */
119fc60a 7316 hw->phy.reset_if_overtemp = true;
c44ade9e 7317 err = hw->mac.ops.reset_hw(hw);
119fc60a 7318 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7319 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7320 hw->mac.type == ixgbe_mac_82598EB) {
7321 /*
7322 * Start a kernel thread to watch for a module to arrive.
7323 * Only do this for 82598, since 82599 will generate
7324 * interrupts on module arrival.
7325 */
7326 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7327 mod_timer(&adapter->sfp_timer,
7328 round_jiffies(jiffies + (2 * HZ)));
7329 err = 0;
7330 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 7331 e_dev_err("failed to initialize because an unsupported SFP+ "
7332 "module type was detected.\n");
7333 e_dev_err("Reload the driver after installing a supported "
7334 "module.\n");
04f165ef
PW		 7335 goto err_sw_init;
7336 } else if (err) {
849c4542 7337 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7338 goto err_sw_init;
7339 }
7340
1cdd1ec8
GR		 7341 ixgbe_probe_vf(adapter, ii);
7342
396e799c 7343 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7344 NETIF_F_IP_CSUM |
7345 NETIF_F_HW_VLAN_TX |
7346 NETIF_F_HW_VLAN_RX |
7347 NETIF_F_HW_VLAN_FILTER;
9a799d71 7348
e9990a9c 7349 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7350 netdev->features |= NETIF_F_TSO;
9a799d71 7351 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7352 netdev->features |= NETIF_F_GRO;
ad31c402 7353
45a5ead0
JB		 7354 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7355 netdev->features |= NETIF_F_SCTP_CSUM;
7356
ad31c402
JK		 7357 netdev->vlan_features |= NETIF_F_TSO;
7358 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7359 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7360 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7361 netdev->vlan_features |= NETIF_F_SG;
7362
1cdd1ec8
GR		 7363 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7364 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7365 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7366
7a6b6f51 7367#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7368 netdev->dcbnl_ops = &dcbnl_ops;
7369#endif
7370
eacd73f7 7371#ifdef IXGBE_FCOE
0d551589 7372 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7373 if (hw->mac.ops.get_device_caps) {
7374 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7375 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7376 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7377 }
7378 }
5e09d7f6
YZ		 7379 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7380 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7381 netdev->vlan_features |= NETIF_F_FSO;
7382 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7383 }
eacd73f7 7384#endif /* IXGBE_FCOE */
7b872a55 7385 if (pci_using_dac) {
9a799d71 7386 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7387 netdev->vlan_features |= NETIF_F_HIGHDMA;
7388 }
9a799d71 7389
0c19d6af 7390 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7391 netdev->features |= NETIF_F_LRO;
7392
9a799d71 7393 /* make sure the EEPROM is good */
c44ade9e 7394 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7395 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7396 err = -EIO;
7397 goto err_eeprom;
7398 }
7399
7400 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7401 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7402
c44ade9e 7403 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7404 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7405 err = -EIO;
7406 goto err_eeprom;
7407 }
7408
c6ecf39a
DS		 7409 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7410 if (hw->mac.ops.disable_tx_laser &&
7411 ((hw->phy.multispeed_fiber) ||
9f911707 7412 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7413 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7414 hw->mac.ops.disable_tx_laser(hw);
7415
9a799d71 7416 init_timer(&adapter->watchdog_timer);
c061b18d 7417 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 7418 adapter->watchdog_timer.data = (unsigned long)adapter;
7419
7420 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 7421 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 7422
021230d4
AV		 7423 err = ixgbe_init_interrupt_scheme(adapter);
7424 if (err)
7425 goto err_sw_init;
9a799d71 7426
e8e26350 7427 switch (pdev->device) {
0b077fea
DS		 7428 case IXGBE_DEV_ID_82599_SFP:
7429 /* Only this subdevice supports WOL */
7430 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7431 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7432 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7433 break;
50d6c681
AD		 7434 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7435 /* All except this subdevice support WOL */
0b077fea
DS		 7436 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7437 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7438 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7439 break;
e8e26350 7440 case IXGBE_DEV_ID_82599_KX4:
495dce12 7441 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7442 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7443 break;
7444 default:
7445 adapter->wol = 0;
7446 break;
7447 }
e8e26350
PW		 7448 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7449
04f165ef
PW		 7450 /* pick up the PCI bus settings for reporting later */
7451 hw->mac.ops.get_bus_info(hw);
7452
9a799d71 7453 /* print bus type/speed/width info */
849c4542 7454 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 7455 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7456 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7457 "Unknown"),
7458 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7459 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7460 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7461 "Unknown"),
7462 netdev->dev_addr);
289700db
DS		 7463
7464 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7465 if (err)
9fe93afd 7466 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7467 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7468 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7469 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7470 part_str);
e8e26350 7471 else
289700db
DS		 7472 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7473 hw->mac.type, hw->phy.type, part_str);
9a799d71 7474
e8e26350 7475 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7476 e_dev_warn("PCI-Express bandwidth available for this card is "
7477 "not sufficient for optimal performance.\n");
7478 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7479 "is required.\n");
0c254d86
AK		 7480 }
7481
34b0368c
PWJ		 7482 /* save off EEPROM version number */
7483 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7484
9a799d71 7485 /* reset the hardware with the new settings */
794caeb2 7486 err = hw->mac.ops.start_hw(hw);
c44ade9e 7487
794caeb2
PWJ		 7488 if (err == IXGBE_ERR_EEPROM_VERSION) {
7489 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7490 e_dev_warn("This device is a pre-production adapter/LOM. "
7491 "Please be aware there may be issues associated "
7492 "with your hardware. If you are experiencing "
7493 "problems please contact your Intel or hardware "
7494 "representative who provided you with this "
7495 "hardware.\n");
794caeb2 7496 }
9a799d71
AK		 7497 strcpy(netdev->name, "eth%d");
7498 err = register_netdev(netdev);
7499 if (err)
7500 goto err_register;
7501
54386467
JB		 7502 /* carrier off reporting is important to ethtool even BEFORE open */
7503 netif_carrier_off(netdev);
7504
c4cf55e5
PWJ		 7505 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7506 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7507 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7508
119fc60a 7509 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7510 INIT_WORK(&adapter->check_overtemp_task,
7511 ixgbe_check_overtemp_task);
5dd2d332 7512#ifdef CONFIG_IXGBE_DCA
652f093f 7513 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7514 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7515 ixgbe_setup_dca(adapter);
7516 }
7517#endif
1cdd1ec8 7518 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7519 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7520 for (i = 0; i < adapter->num_vfs; i++)
7521 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7522 }
7523
0365e6e4
PW		 7524 /* add san mac addr to netdev */
7525 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7526
849c4542 7527 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7528 cards_found++;
7529 return 0;
7530
7531err_register:
5eba3699 7532 ixgbe_release_hw_control(adapter);
7a921c93 7533 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7534err_sw_init:
7535err_eeprom:
1cdd1ec8
GR		 7536 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7537 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7538 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7539 del_timer_sync(&adapter->sfp_timer);
7540 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7541 cancel_work_sync(&adapter->multispeed_fiber_task);
7542 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7543 iounmap(hw->hw_addr);
7544err_ioremap:
7545 free_netdev(netdev);
7546err_alloc_etherdev:
e8e9f696
JP		 7547 pci_release_selected_regions(pdev,
7548 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7549err_pci_reg:
7550err_dma:
7551 pci_disable_device(pdev);
7552 return err;
7553}
7554
7555/**
7556 * ixgbe_remove - Device Removal Routine
7557 * @pdev: PCI device information struct
7558 *
7559 * ixgbe_remove is called by the PCI subsystem to alert the driver
7560 * that it should release a PCI device. The could be caused by a
7561 * Hot-Plug event, or because the driver is going to be removed from
7562 * memory.
7563 **/
7564static void __devexit ixgbe_remove(struct pci_dev *pdev)
7565{
c60fbb00
AD		 7566 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7567 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7568
7569 set_bit(__IXGBE_DOWN, &adapter->state);
760141a5
TH		 7570
7571 /*
7572 * The timers may be rescheduled, so explicitly disable them
7573 * from being rescheduled.
c4900be0
DS		 7574 */
7575 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71 7576 del_timer_sync(&adapter->watchdog_timer);
c4900be0 7577 del_timer_sync(&adapter->sfp_timer);
760141a5 7578
c4900be0
DS		 7579 cancel_work_sync(&adapter->watchdog_task);
7580 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7581 cancel_work_sync(&adapter->multispeed_fiber_task);
7582 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7583 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7584 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7585 cancel_work_sync(&adapter->fdir_reinit_task);
760141a5
TH		 7586 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7587 cancel_work_sync(&adapter->check_overtemp_task);
9a799d71 7588
5dd2d332 7589#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7590 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7591 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7592 dca_remove_requester(&pdev->dev);
7593 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7594 }
7595
7596#endif
332d4a7d
YZ		 7597#ifdef IXGBE_FCOE
7598 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7599 ixgbe_cleanup_fcoe(adapter);
7600
7601#endif /* IXGBE_FCOE */
0365e6e4
PW		 7602
7603 /* remove the added san mac */
7604 ixgbe_del_sanmac_netdev(netdev);
7605
c4900be0
DS		 7606 if (netdev->reg_state == NETREG_REGISTERED)
7607 unregister_netdev(netdev);
9a799d71 7608
1cdd1ec8
GR		 7609 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7610 ixgbe_disable_sriov(adapter);
7611
7a921c93 7612 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7613
021230d4 7614 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7615
7616 iounmap(adapter->hw.hw_addr);
9ce77666 7617 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7618 IORESOURCE_MEM));
9a799d71 7619
849c4542 7620 e_dev_info("complete\n");
021230d4 7621
9a799d71
AK		 7622 free_netdev(netdev);
7623
19d5afd4 7624 pci_disable_pcie_error_reporting(pdev);
6fabd715 7625
9a799d71
AK		 7626 pci_disable_device(pdev);
7627}
7628
7629/**
7630 * ixgbe_io_error_detected - called when PCI error is detected
7631 * @pdev: Pointer to PCI device
7632 * @state: The current pci connection state
7633 *
7634 * This function is called after a PCI bus error affecting
7635 * this device has been detected.
7636 */
7637static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7638 pci_channel_state_t state)
9a799d71 7639{
c60fbb00
AD		 7640 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7641 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7642
7643 netif_device_detach(netdev);
7644
3044b8d1
BL		 7645 if (state == pci_channel_io_perm_failure)
7646 return PCI_ERS_RESULT_DISCONNECT;
7647
9a799d71
AK		 7648 if (netif_running(netdev))
7649 ixgbe_down(adapter);
7650 pci_disable_device(pdev);
7651
b4617240 7652 /* Request a slot reset. */
9a799d71
AK		 7653 return PCI_ERS_RESULT_NEED_RESET;
7654}
7655
7656/**
7657 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7658 * @pdev: Pointer to PCI device
7659 *
7660 * Restart the card from scratch, as if from a cold-boot.
7661 */
7662static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7663{
c60fbb00 7664 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7665 pci_ers_result_t result;
7666 int err;
9a799d71 7667
9ce77666 7668 if (pci_enable_device_mem(pdev)) {
396e799c 7669 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7670 result = PCI_ERS_RESULT_DISCONNECT;
7671 } else {
7672 pci_set_master(pdev);
7673 pci_restore_state(pdev);
c0e1f68b 7674 pci_save_state(pdev);
9a799d71 7675
dd4d8ca6 7676 pci_wake_from_d3(pdev, false);
9a799d71 7677
6fabd715 7678 ixgbe_reset(adapter);
88512539 7679 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7680 result = PCI_ERS_RESULT_RECOVERED;
7681 }
7682
7683 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7684 if (err) {
849c4542
ET		 7685 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7686 "failed 0x%0x\n", err);
6fabd715
PWJ		 7687 /* non-fatal, continue */
7688 }
9a799d71 7689
6fabd715 7690 return result;
9a799d71
AK		 7691}
7692
7693/**
7694 * ixgbe_io_resume - called when traffic can start flowing again.
7695 * @pdev: Pointer to PCI device
7696 *
7697 * This callback is called when the error recovery driver tells us that
7698 * its OK to resume normal operation.
7699 */
7700static void ixgbe_io_resume(struct pci_dev *pdev)
7701{
c60fbb00
AD		 7702 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7703 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7704
7705 if (netif_running(netdev)) {
7706 if (ixgbe_up(adapter)) {
396e799c 7707 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7708 return;
7709 }
7710 }
7711
7712 netif_device_attach(netdev);
9a799d71
AK		 7713}
7714
7715static struct pci_error_handlers ixgbe_err_handler = {
7716 .error_detected = ixgbe_io_error_detected,
7717 .slot_reset = ixgbe_io_slot_reset,
7718 .resume = ixgbe_io_resume,
7719};
7720
7721static struct pci_driver ixgbe_driver = {
7722 .name = ixgbe_driver_name,
7723 .id_table = ixgbe_pci_tbl,
7724 .probe = ixgbe_probe,
7725 .remove = __devexit_p(ixgbe_remove),
7726#ifdef CONFIG_PM
7727 .suspend = ixgbe_suspend,
7728 .resume = ixgbe_resume,
7729#endif
7730 .shutdown = ixgbe_shutdown,
7731 .err_handler = &ixgbe_err_handler
7732};
7733
7734/**
7735 * ixgbe_init_module - Driver Registration Routine
7736 *
7737 * ixgbe_init_module is the first routine called when the driver is
7738 * loaded. All it does is register with the PCI subsystem.
7739 **/
7740static int __init ixgbe_init_module(void)
7741{
7742 int ret;
c7689578 7743 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7744 pr_info("%s\n", ixgbe_copyright);
9a799d71 7745
5dd2d332 7746#ifdef CONFIG_IXGBE_DCA
bd0362dd 7747 dca_register_notify(&dca_notifier);
bd0362dd 7748#endif
5dd2d332 7749
9a799d71
AK		 7750 ret = pci_register_driver(&ixgbe_driver);
7751 return ret;
7752}
b4617240 7753
9a799d71
AK		 7754module_init(ixgbe_init_module);
7755
7756/**
7757 * ixgbe_exit_module - Driver Exit Cleanup Routine
7758 *
7759 * ixgbe_exit_module is called just before the driver is removed
7760 * from memory.
7761 **/
7762static void __exit ixgbe_exit_module(void)
7763{
5dd2d332 7764#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7765 dca_unregister_notify(&dca_notifier);
7766#endif
9a799d71 7767 pci_unregister_driver(&ixgbe_driver);
1a51502b 7768 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7769}
bd0362dd 7770
5dd2d332 7771#ifdef CONFIG_IXGBE_DCA
bd0362dd 7772static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7773 void *p)
bd0362dd
JC		 7774{
7775 int ret_val;
7776
7777 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7778 __ixgbe_notify_dca);
bd0362dd
JC		 7779
7780 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7781}
b453368d 7782
5dd2d332 7783#endif /* CONFIG_IXGBE_DCA */
849c4542 7784
9a799d71
AK		 7785module_exit(ixgbe_exit_module);
7786
7787/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)