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ixgbe: Remove unnecessary PHY reset, properly identify multispeed fiber modules
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_82599_MAX_TX_QUEUES 128
36#define IXGBE_82599_MAX_RX_QUEUES 128
37#define IXGBE_82599_RAR_ENTRIES 128
38#define IXGBE_82599_MC_TBL_SIZE 128
39#define IXGBE_82599_VFT_TBL_SIZE 128
40
41s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg,
56 bool autoneg_wait_to_complete);
57static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
59 bool *autoneg);
60static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
63 bool autoneg,
64 bool autoneg_wait_to_complete);
65s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69 u32 vind, bool vlan_on);
70s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
71s32 ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, u32 index);
72s32 ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, u32 index);
73s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
74s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
75s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
76s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
77s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
78s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
79u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
80
81void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
82{
83 struct ixgbe_mac_info *mac = &hw->mac;
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link =
87 &ixgbe_setup_mac_link_multispeed_fiber;
88 mac->ops.setup_link_speed =
89 &ixgbe_setup_mac_link_speed_multispeed_fiber;
90 } else {
91 mac->ops.setup_link =
92 &ixgbe_setup_mac_link_82599;
93 mac->ops.setup_link_speed =
94 &ixgbe_setup_mac_link_speed_82599;
95 }
96}
97
98s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
99{
100 s32 ret_val = 0;
101 u16 list_offset, data_offset, data_value;
102
103 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
104 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 105
106 hw->phy.ops.reset = NULL;
107
11afc1b1
PW		 108 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
109 &data_offset);
110
111 if (ret_val != 0)
112 goto setup_sfp_out;
113
114 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
115 while (data_value != 0xffff) {
116 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
117 IXGBE_WRITE_FLUSH(hw);
118 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
119 }
120 /* Now restart DSP */
121 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
122 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
123 IXGBE_WRITE_FLUSH(hw);
124 }
125
126setup_sfp_out:
127 return ret_val;
128}
129
130/**
131 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
132 * @hw: pointer to hardware structure
133 *
134 * Read PCIe configuration space, and get the MSI-X vector count from
135 * the capabilities table.
136 **/
137u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
138{
139 struct ixgbe_adapter *adapter = hw->back;
140 u16 msix_count;
141 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
142 &msix_count);
143 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
144
145 /* MSI-X count is zero-based in HW, so increment to give proper value */
146 msix_count++;
147
148 return msix_count;
149}
150
151static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
152{
153 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 154
04f165ef 155 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 156
04f165ef
PW		 157 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
158 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
159 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
160 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
161 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
162 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 163
04f165ef
PW		 164 return 0;
165}
11afc1b1 166
04f165ef
PW		 167/**
168 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
169 * @hw: pointer to hardware structure
170 *
171 * Initialize any function pointers that were not able to be
172 * set during get_invariants because the PHY/SFP type was
173 * not known. Perform the SFP init if necessary.
174 *
175 **/
176s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
177{
178 struct ixgbe_mac_info *mac = &hw->mac;
179 struct ixgbe_phy_info *phy = &hw->phy;
180 s32 ret_val = 0;
11afc1b1 181
04f165ef
PW		 182 /* Identify the PHY or SFP module */
183 ret_val = phy->ops.identify(hw);
184
185 /* Setup function pointers based on detected SFP module and speeds */
186 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 187
188 /* If copper media, overwrite with copper function pointers */
189 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
190 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
191 mac->ops.setup_link_speed =
04f165ef 192 &ixgbe_setup_copper_link_speed_82599;
11afc1b1
PW		 193 mac->ops.get_link_capabilities =
194 &ixgbe_get_copper_link_capabilities_82599;
195 }
196
04f165ef 197 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 198 switch (hw->phy.type) {
199 case ixgbe_phy_tn:
200 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
201 phy->ops.get_firmware_version =
04f165ef 202 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 203 break;
204 default:
205 break;
206 }
207
11afc1b1
PW		 208 return ret_val;
209}
210
211/**
212 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
213 * @hw: pointer to hardware structure
214 * @speed: pointer to link speed
215 * @negotiation: true when autoneg or autotry is enabled
216 *
217 * Determines the link capabilities by reading the AUTOC register.
218 **/
219s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
220 ixgbe_link_speed *speed,
221 bool *negotiation)
222{
223 s32 status = 0;
224
225 switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
226 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
227 *speed = IXGBE_LINK_SPEED_1GB_FULL;
228 *negotiation = false;
229 break;
230
231 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
232 *speed = IXGBE_LINK_SPEED_10GB_FULL;
233 *negotiation = false;
234 break;
235
236 case IXGBE_AUTOC_LMS_1G_AN:
237 *speed = IXGBE_LINK_SPEED_1GB_FULL;
238 *negotiation = true;
239 break;
240
241 case IXGBE_AUTOC_LMS_10G_SERIAL:
242 *speed = IXGBE_LINK_SPEED_10GB_FULL;
243 *negotiation = false;
244 break;
245
246 case IXGBE_AUTOC_LMS_KX4_KX_KR:
247 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
248 *speed = IXGBE_LINK_SPEED_UNKNOWN;
249 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
250 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
251 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
252 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
253 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
254 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
255 *negotiation = true;
256 break;
257
258 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
259 *speed = IXGBE_LINK_SPEED_100_FULL;
260 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
261 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
262 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
263 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
264 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
265 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
266 *negotiation = true;
267 break;
268
269 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
270 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
271 *negotiation = false;
272 break;
273
274 default:
275 status = IXGBE_ERR_LINK_SETUP;
276 goto out;
277 break;
278 }
279
280 if (hw->phy.multispeed_fiber) {
281 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
282 IXGBE_LINK_SPEED_1GB_FULL;
283 *negotiation = true;
284 }
285
286out:
287 return status;
288}
289
290/**
291 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
292 * @hw: pointer to hardware structure
293 * @speed: pointer to link speed
294 * @autoneg: boolean auto-negotiation value
295 *
296 * Determines the link capabilities by reading the AUTOC register.
297 **/
298static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
299 ixgbe_link_speed *speed,
300 bool *autoneg)
301{
302 s32 status = IXGBE_ERR_LINK_SETUP;
303 u16 speed_ability;
304
305 *speed = 0;
306 *autoneg = true;
307
308 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
309 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
310 &speed_ability);
311
312 if (status == 0) {
313 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
314 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
315 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
316 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
317 }
318
319 return status;
320}
321
322/**
323 * ixgbe_get_media_type_82599 - Get media type
324 * @hw: pointer to hardware structure
325 *
326 * Returns the media type (fiber, copper, backplane)
327 **/
328enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
329{
330 enum ixgbe_media_type media_type;
331
332 /* Detect if there is a copper PHY attached. */
333 if (hw->phy.type == ixgbe_phy_cu_unknown ||
334 hw->phy.type == ixgbe_phy_tn) {
335 media_type = ixgbe_media_type_copper;
336 goto out;
337 }
338
339 switch (hw->device_id) {
340 case IXGBE_DEV_ID_82599:
341 case IXGBE_DEV_ID_82599_KX4:
342 /* Default device ID is mezzanine card KX/KX4 */
343 media_type = ixgbe_media_type_backplane;
344 break;
345 case IXGBE_DEV_ID_82599_SFP:
346 media_type = ixgbe_media_type_fiber;
347 break;
348 default:
349 media_type = ixgbe_media_type_unknown;
350 break;
351 }
352out:
353 return media_type;
354}
355
356/**
357 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
358 * @hw: pointer to hardware structure
359 *
360 * Configures link settings based on values in the ixgbe_hw struct.
361 * Restarts the link. Performs autonegotiation if needed.
362 **/
363s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
364{
365 u32 autoc_reg;
366 u32 links_reg;
367 u32 i;
368 s32 status = 0;
369
370 /* Restart link */
371 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
372 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
373 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
374
375 /* Only poll for autoneg to complete if specified to do so */
376 if (hw->phy.autoneg_wait_to_complete) {
377 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
378 IXGBE_AUTOC_LMS_KX4_KX_KR ||
379 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
380 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
381 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
382 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
383 links_reg = 0; /* Just in case Autoneg time = 0 */
384 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
385 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
386 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
387 break;
388 msleep(100);
389 }
390 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
391 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
392 hw_dbg(hw, "Autoneg did not complete.\n");
393 }
394 }
395 }
396
397 /* Set up flow control */
398 status = ixgbe_setup_fc_generic(hw, 0);
399
400 /* Add delay to filter out noises during initial link setup */
401 msleep(50);
402
403 return status;
404}
405
406/**
407 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
408 * @hw: pointer to hardware structure
409 *
410 * Configures link settings based on values in the ixgbe_hw struct.
411 * Restarts the link for multi-speed fiber at 1G speed, if link
412 * fails at 10G.
413 * Performs autonegotiation if needed.
414 **/
415s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
416{
417 s32 status = 0;
418 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
4df10466 419 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
11afc1b1
PW		 420 true, true);
421 return status;
422}
423
424/**
425 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
426 * @hw: pointer to hardware structure
427 * @speed: new link speed
428 * @autoneg: true if autonegotiation enabled
429 * @autoneg_wait_to_complete: true when waiting for completion is needed
430 *
431 * Set the link speed in the AUTOC register and restarts link.
432 **/
433s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
434 ixgbe_link_speed speed,
435 bool autoneg,
436 bool autoneg_wait_to_complete)
437{
438 s32 status = 0;
439 ixgbe_link_speed phy_link_speed;
440 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
441 u32 speedcnt = 0;
442 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
443 bool link_up = false;
444 bool negotiation;
445
446 /* Mask off requested but non-supported speeds */
447 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
448 speed &= phy_link_speed;
449
450 /*
451 * Try each speed one by one, highest priority first. We do this in
452 * software because 10gb fiber doesn't support speed autonegotiation.
453 */
454 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
455 speedcnt++;
456 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
457
458 /* Set hardware SDP's */
459 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
460 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
461
462 ixgbe_setup_mac_link_speed_82599(hw,
463 IXGBE_LINK_SPEED_10GB_FULL,
464 autoneg,
465 autoneg_wait_to_complete);
466
467 msleep(50);
468
469 /* If we have link, just jump out */
470 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
471 if (link_up)
472 goto out;
473 }
474
475 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
476 speedcnt++;
477 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
478 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
479
480 /* Set hardware SDP's */
481 esdp_reg &= ~IXGBE_ESDP_SDP5;
482 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
483 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
484
485 ixgbe_setup_mac_link_speed_82599(
486 hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
487 autoneg_wait_to_complete);
488
489 msleep(50);
490
491 /* If we have link, just jump out */
492 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
493 if (link_up)
494 goto out;
495 }
496
497 /*
498 * We didn't get link. Configure back to the highest speed we tried,
499 * (if there was more than one). We call ourselves back with just the
500 * single highest speed that the user requested.
501 */
502 if (speedcnt > 1)
503 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
504 highest_link_speed,
505 autoneg,
506 autoneg_wait_to_complete);
507
508out:
509 return status;
510}
511
512/**
513 * ixgbe_check_mac_link_82599 - Determine link and speed status
514 * @hw: pointer to hardware structure
515 * @speed: pointer to link speed
516 * @link_up: true when link is up
517 * @link_up_wait_to_complete: bool used to wait for link up or not
518 *
519 * Reads the links register to determine if link is up and the current speed
520 **/
521s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
522 bool *link_up, bool link_up_wait_to_complete)
523{
524 u32 links_reg;
525 u32 i;
526
527 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
528 if (link_up_wait_to_complete) {
529 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
530 if (links_reg & IXGBE_LINKS_UP) {
531 *link_up = true;
532 break;
533 } else {
534 *link_up = false;
535 }
536 msleep(100);
537 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
538 }
539 } else {
540 if (links_reg & IXGBE_LINKS_UP)
541 *link_up = true;
542 else
543 *link_up = false;
544 }
545
546 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
547 IXGBE_LINKS_SPEED_10G_82599)
548 *speed = IXGBE_LINK_SPEED_10GB_FULL;
549 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
550 IXGBE_LINKS_SPEED_1G_82599)
551 *speed = IXGBE_LINK_SPEED_1GB_FULL;
552 else
553 *speed = IXGBE_LINK_SPEED_100_FULL;
554
555
556 return 0;
557}
558
559/**
560 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
561 * @hw: pointer to hardware structure
562 * @speed: new link speed
563 * @autoneg: true if autonegotiation enabled
564 * @autoneg_wait_to_complete: true when waiting for completion is needed
565 *
566 * Set the link speed in the AUTOC register and restarts link.
567 **/
568s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
569 ixgbe_link_speed speed, bool autoneg,
570 bool autoneg_wait_to_complete)
571{
572 s32 status = 0;
573 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
574 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
575 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
576 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
577 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
578 u32 links_reg;
579 u32 i;
580 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
581
582 /* Check to see if speed passed in is supported. */
583 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
584 speed &= link_capabilities;
585
586 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
587 status = IXGBE_ERR_LINK_SETUP;
588 } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
589 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
590 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
591 /* Set KX4/KX/KR support according to speed requested */
592 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
593 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
594 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
595 autoc |= IXGBE_AUTOC_KX4_SUPP;
596 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
597 autoc |= IXGBE_AUTOC_KR_SUPP;
598 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
599 autoc |= IXGBE_AUTOC_KX_SUPP;
600 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
601 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
602 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
603 /* Switch from 1G SFI to 10G SFI if requested */
604 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
605 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
606 autoc &= ~IXGBE_AUTOC_LMS_MASK;
607 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
608 }
609 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
610 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
611 /* Switch from 10G SFI to 1G SFI if requested */
612 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
613 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
614 autoc &= ~IXGBE_AUTOC_LMS_MASK;
615 if (autoneg)
616 autoc |= IXGBE_AUTOC_LMS_1G_AN;
617 else
618 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
619 }
620 }
621
622 if (status == 0) {
623 /* Restart link */
624 autoc |= IXGBE_AUTOC_AN_RESTART;
625 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
626
627 /* Only poll for autoneg to complete if specified to do so */
628 if (autoneg_wait_to_complete) {
629 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
630 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
631 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
632 links_reg = 0; /*Just in case Autoneg time=0*/
633 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
634 links_reg =
635 IXGBE_READ_REG(hw, IXGBE_LINKS);
636 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
637 break;
638 msleep(100);
639 }
640 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
641 status =
642 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
643 hw_dbg(hw, "Autoneg did not "
644 "complete.\n");
645 }
646 }
647 }
648
649 /* Set up flow control */
650 status = ixgbe_setup_fc_generic(hw, 0);
651
652 /* Add delay to filter out noises during initial link setup */
653 msleep(50);
654 }
655
656 return status;
657}
658
659/**
660 * ixgbe_setup_copper_link_82599 - Setup copper link settings
661 * @hw: pointer to hardware structure
662 *
663 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
664 **/
665static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
666{
667 s32 status;
668
669 /* Restart autonegotiation on PHY */
670 status = hw->phy.ops.setup_link(hw);
671
672 /* Set up MAC */
673 ixgbe_setup_mac_link_82599(hw);
674
675 return status;
676}
677
678/**
679 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
680 * @hw: pointer to hardware structure
681 * @speed: new link speed
682 * @autoneg: true if autonegotiation enabled
683 * @autoneg_wait_to_complete: true if waiting is needed to complete
684 *
685 * Restarts link on PHY and MAC based on settings passed in.
686 **/
687static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
688 ixgbe_link_speed speed,
689 bool autoneg,
690 bool autoneg_wait_to_complete)
691{
692 s32 status;
693
694 /* Setup the PHY according to input speed */
695 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
696 autoneg_wait_to_complete);
697 /* Set up MAC */
698 ixgbe_setup_mac_link_82599(hw);
699
700 return status;
701}
702
703/**
704 * ixgbe_reset_hw_82599 - Perform hardware reset
705 * @hw: pointer to hardware structure
706 *
707 * Resets the hardware by resetting the transmit and receive units, masks
708 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
709 * reset.
710 **/
711s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
712{
713 s32 status = 0;
714 u32 ctrl, ctrl_ext;
715 u32 i;
716 u32 autoc;
717 u32 autoc2;
718
719 /* Call adapter stop to disable tx/rx and clear interrupts */
720 hw->mac.ops.stop_adapter(hw);
721
553b4497 722 /* PHY ops must be identified and initialized prior to reset */
04f165ef 723
553b4497
PW		 724 /* Init PHY and function pointers, perform SFP setup */
725 status = hw->phy.ops.init(hw);
04f165ef 726
553b4497
PW		 727 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
728 goto reset_hw_out;
04f165ef 729
553b4497
PW		 730 /* Setup SFP module if there is one present. */
731 if (hw->phy.sfp_setup_needed) {
732 status = hw->mac.ops.setup_sfp(hw);
733 hw->phy.sfp_setup_needed = false;
04f165ef 734 }
11afc1b1 735
553b4497
PW		 736 /* Reset PHY */
737 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
738 hw->phy.ops.reset(hw);
739
11afc1b1
PW		 740 /*
741 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
742 * access and verify no pending requests before reset
743 */
04f165ef
PW		 744 status = ixgbe_disable_pcie_master(hw);
745 if (status != 0) {
11afc1b1
PW		 746 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
747 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
748 }
749
750 /*
751 * Issue global reset to the MAC. This needs to be a SW reset.
752 * If link reset is used, it might reset the MAC when mng is using it
753 */
754 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
755 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
756 IXGBE_WRITE_FLUSH(hw);
757
758 /* Poll for reset bit to self-clear indicating reset is complete */
759 for (i = 0; i < 10; i++) {
760 udelay(1);
761 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
762 if (!(ctrl & IXGBE_CTRL_RST))
763 break;
764 }
765 if (ctrl & IXGBE_CTRL_RST) {
766 status = IXGBE_ERR_RESET_FAILED;
767 hw_dbg(hw, "Reset polling failed to complete.\n");
768 }
769 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
770 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
771 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
772 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
773
774 msleep(50);
775
776
777
778 /*
779 * Store the original AUTOC/AUTOC2 values if they have not been
780 * stored off yet. Otherwise restore the stored original
781 * values since the reset operation sets back to defaults.
782 */
783 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
784 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
785 if (hw->mac.orig_link_settings_stored == false) {
786 hw->mac.orig_autoc = autoc;
787 hw->mac.orig_autoc2 = autoc2;
788 hw->mac.orig_link_settings_stored = true;
4df10466 789 } else {
11afc1b1
PW		 790 if (autoc != hw->mac.orig_autoc)
791 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
792 IXGBE_AUTOC_AN_RESTART));
793
794 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
795 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
796 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
797 autoc2 |= (hw->mac.orig_autoc2 &
798 IXGBE_AUTOC2_UPPER_MASK);
799 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
800 }
801 }
802
803 /* Store the permanent mac address */
804 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
805
04f165ef 806reset_hw_out:
11afc1b1
PW		 807 return status;
808}
809
810/**
811 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
812 * @hw: pointer to hardware struct
813 * @rar: receive address register index to disassociate
814 * @vmdq: VMDq pool index to remove from the rar
815 **/
816s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
817{
818 u32 mpsar_lo, mpsar_hi;
819 u32 rar_entries = hw->mac.num_rar_entries;
820
821 if (rar < rar_entries) {
822 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
823 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
824
825 if (!mpsar_lo && !mpsar_hi)
826 goto done;
827
828 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
829 if (mpsar_lo) {
830 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
831 mpsar_lo = 0;
832 }
833 if (mpsar_hi) {
834 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
835 mpsar_hi = 0;
836 }
837 } else if (vmdq < 32) {
838 mpsar_lo &= ~(1 << vmdq);
839 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
840 } else {
841 mpsar_hi &= ~(1 << (vmdq - 32));
842 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
843 }
844
845 /* was that the last pool using this rar? */
846 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
847 hw->mac.ops.clear_rar(hw, rar);
848 } else {
849 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
850 }
851
852done:
853 return 0;
854}
855
856/**
857 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
858 * @hw: pointer to hardware struct
859 * @rar: receive address register index to associate with a VMDq index
860 * @vmdq: VMDq pool index
861 **/
862s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
863{
864 u32 mpsar;
865 u32 rar_entries = hw->mac.num_rar_entries;
866
867 if (rar < rar_entries) {
868 if (vmdq < 32) {
869 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
870 mpsar |= 1 << vmdq;
871 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
872 } else {
873 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
874 mpsar |= 1 << (vmdq - 32);
875 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
876 }
877 } else {
878 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
879 }
880 return 0;
881}
882
883/**
884 * ixgbe_set_vfta_82599 - Set VLAN filter table
885 * @hw: pointer to hardware structure
886 * @vlan: VLAN id to write to VLAN filter
887 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
888 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
889 *
890 * Turn on/off specified VLAN in the VLAN filter table.
891 **/
892s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
893 bool vlan_on)
894{
895 u32 regindex;
896 u32 bitindex;
897 u32 bits;
898 u32 first_empty_slot;
899
900 if (vlan > 4095)
901 return IXGBE_ERR_PARAM;
902
903 /*
904 * this is a 2 part operation - first the VFTA, then the
905 * VLVF and VLVFB if vind is set
906 */
907
908 /* Part 1
909 * The VFTA is a bitstring made up of 128 32-bit registers
910 * that enable the particular VLAN id, much like the MTA:
911 * bits[11-5]: which register
912 * bits[4-0]: which bit in the register
913 */
914 regindex = (vlan >> 5) & 0x7F;
915 bitindex = vlan & 0x1F;
916 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
917 if (vlan_on)
918 bits |= (1 << bitindex);
919 else
920 bits &= ~(1 << bitindex);
921 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
922
923
924 /* Part 2
925 * If the vind is set
926 * Either vlan_on
927 * make sure the vlan is in VLVF
928 * set the vind bit in the matching VLVFB
929 * Or !vlan_on
930 * clear the pool bit and possibly the vind
931 */
932 if (vind) {
933 /* find the vlanid or the first empty slot */
934 first_empty_slot = 0;
935
936 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
937 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
938 if (!bits && !first_empty_slot)
939 first_empty_slot = regindex;
940 else if ((bits & 0x0FFF) == vlan)
941 break;
942 }
943
944 if (regindex >= IXGBE_VLVF_ENTRIES) {
945 if (first_empty_slot)
946 regindex = first_empty_slot;
947 else {
948 hw_dbg(hw, "No space in VLVF.\n");
949 goto out;
950 }
951 }
952
953 if (vlan_on) {
954 /* set the pool bit */
955 if (vind < 32) {
956 bits = IXGBE_READ_REG(hw,
957 IXGBE_VLVFB(regindex * 2));
958 bits |= (1 << vind);
959 IXGBE_WRITE_REG(hw,
960 IXGBE_VLVFB(regindex * 2), bits);
961 } else {
962 bits = IXGBE_READ_REG(hw,
963 IXGBE_VLVFB((regindex * 2) + 1));
964 bits |= (1 << vind);
965 IXGBE_WRITE_REG(hw,
966 IXGBE_VLVFB((regindex * 2) + 1), bits);
967 }
968 } else {
969 /* clear the pool bit */
970 if (vind < 32) {
971 bits = IXGBE_READ_REG(hw,
972 IXGBE_VLVFB(regindex * 2));
973 bits &= ~(1 << vind);
974 IXGBE_WRITE_REG(hw,
975 IXGBE_VLVFB(regindex * 2), bits);
976 bits |= IXGBE_READ_REG(hw,
977 IXGBE_VLVFB((regindex * 2) + 1));
978 } else {
979 bits = IXGBE_READ_REG(hw,
980 IXGBE_VLVFB((regindex * 2) + 1));
981 bits &= ~(1 << vind);
982 IXGBE_WRITE_REG(hw,
983 IXGBE_VLVFB((regindex * 2) + 1), bits);
984 bits |= IXGBE_READ_REG(hw,
985 IXGBE_VLVFB(regindex * 2));
986 }
987 }
988
989 if (bits)
990 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
991 (IXGBE_VLVF_VIEN | vlan));
992 else
993 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
994 }
995
996out:
997 return 0;
998}
999
1000/**
1001 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1002 * @hw: pointer to hardware structure
1003 *
1004 * Clears the VLAN filer table, and the VMDq index associated with the filter
1005 **/
1006s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1007{
1008 u32 offset;
1009
1010 for (offset = 0; offset < hw->mac.vft_size; offset++)
1011 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1012
1013 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1014 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1015 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1016 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1017 }
1018
1019 return 0;
1020}
1021
1022/**
1023 * ixgbe_blink_led_start_82599 - Blink LED based on index.
1024 * @hw: pointer to hardware structure
1025 * @index: led number to blink
1026 **/
1027s32 ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, u32 index)
1028{
1029 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1030
1031 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1032 led_reg |= IXGBE_LED_BLINK(index);
1033 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1034 IXGBE_WRITE_FLUSH(hw);
1035
1036 return 0;
1037}
1038
1039/**
1040 * ixgbe_blink_led_stop_82599 - Stop blinking LED based on index.
1041 * @hw: pointer to hardware structure
1042 * @index: led number to stop blinking
1043 **/
1044s32 ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, u32 index)
1045{
1046 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1047
1048 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1049 led_reg &= ~IXGBE_LED_BLINK(index);
1050 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1051 IXGBE_WRITE_FLUSH(hw);
1052
1053 return 0;
1054}
1055
1056/**
1057 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1058 * @hw: pointer to hardware structure
1059 **/
1060s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1061{
1062 int i;
1063 hw_dbg(hw, " Clearing UTA\n");
1064
1065 for (i = 0; i < 128; i++)
1066 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1067
1068 return 0;
1069}
1070
1071/**
1072 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1073 * @hw: pointer to hardware structure
1074 * @reg: analog register to read
1075 * @val: read value
1076 *
1077 * Performs read operation to Omer analog register specified.
1078 **/
1079s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1080{
1081 u32 core_ctl;
1082
1083 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1084 (reg << 8));
1085 IXGBE_WRITE_FLUSH(hw);
1086 udelay(10);
1087 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1088 *val = (u8)core_ctl;
1089
1090 return 0;
1091}
1092
1093/**
1094 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1095 * @hw: pointer to hardware structure
1096 * @reg: atlas register to write
1097 * @val: value to write
1098 *
1099 * Performs write operation to Omer analog register specified.
1100 **/
1101s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1102{
1103 u32 core_ctl;
1104
1105 core_ctl = (reg << 8) | val;
1106 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1107 IXGBE_WRITE_FLUSH(hw);
1108 udelay(10);
1109
1110 return 0;
1111}
1112
1113/**
1114 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1115 * @hw: pointer to hardware structure
1116 *
1117 * Starts the hardware using the generic start_hw function.
1118 * Then performs device-specific:
1119 * Clears the rate limiter registers.
1120 **/
1121s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1122{
1123 u32 q_num;
1124
1125 ixgbe_start_hw_generic(hw);
1126
1127 /* Clear the rate limiters */
1128 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1129 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1130 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1131 }
1132 IXGBE_WRITE_FLUSH(hw);
1133
1134 return 0;
1135}
1136
1137/**
1138 * ixgbe_identify_phy_82599 - Get physical layer module
1139 * @hw: pointer to hardware structure
1140 *
1141 * Determines the physical layer module found on the current adapter.
1142 **/
1143s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1144{
1145 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1146 status = ixgbe_identify_phy_generic(hw);
1147 if (status != 0)
1148 status = ixgbe_identify_sfp_module_generic(hw);
1149 return status;
1150}
1151
1152/**
1153 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1154 * @hw: pointer to hardware structure
1155 *
1156 * Determines physical layer capabilities of the current configuration.
1157 **/
1158u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1159{
1160 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1339b9e9 1161 u8 comp_codes_10g = 0;
11afc1b1
PW		 1162
1163 switch (hw->device_id) {
1164 case IXGBE_DEV_ID_82599:
1165 case IXGBE_DEV_ID_82599_KX4:
1166 /* Default device ID is mezzanine card KX/KX4 */
1167 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1168 IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1169 break;
1170 case IXGBE_DEV_ID_82599_SFP:
1171 hw->phy.ops.identify_sfp(hw);
1172
1173 switch (hw->phy.sfp_type) {
1174 case ixgbe_sfp_type_da_cu:
1339b9e9
PW		 1175 case ixgbe_sfp_type_da_cu_core0:
1176 case ixgbe_sfp_type_da_cu_core1:
11afc1b1
PW		 1177 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1178 break;
1179 case ixgbe_sfp_type_sr:
1180 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1181 break;
1182 case ixgbe_sfp_type_lr:
1183 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1184 break;
1339b9e9
PW		 1185 case ixgbe_sfp_type_srlr_core0:
1186 case ixgbe_sfp_type_srlr_core1:
1187 hw->phy.ops.read_i2c_eeprom(hw,
1188 IXGBE_SFF_10GBE_COMP_CODES,
1189 &comp_codes_10g);
1190 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1191 physical_layer =
1192 IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1193 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1194 physical_layer =
1195 IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1196 else
1197 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
11afc1b1
PW		 1198 default:
1199 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1200 break;
1201 }
1202 break;
1203 default:
1204 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1205 break;
1206 }
1207
1208 return physical_layer;
1209}
1210
1211/**
1212 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1213 * @hw: pointer to hardware structure
1214 * @regval: register value to write to RXCTRL
1215 *
1216 * Enables the Rx DMA unit for 82599
1217 **/
1218s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1219{
1220#define IXGBE_MAX_SECRX_POLL 30
1221 int i;
1222 int secrxreg;
1223
1224 /*
1225 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1226 * If traffic is incoming before we enable the Rx unit, it could hang
1227 * the Rx DMA unit. Therefore, make sure the security engine is
1228 * completely disabled prior to enabling the Rx unit.
1229 */
1230 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1231 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1232 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1233 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1234 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1235 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1236 break;
1237 else
1238 udelay(10);
1239 }
1240
1241 /* For informational purposes only */
1242 if (i >= IXGBE_MAX_SECRX_POLL)
1243 hw_dbg(hw, "Rx unit being enabled before security "
1244 "path fully disabled. Continuing with init.\n");
1245
1246 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1247 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1248 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1249 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1250 IXGBE_WRITE_FLUSH(hw);
1251
1252 return 0;
1253}
1254
1255static struct ixgbe_mac_operations mac_ops_82599 = {
1256 .init_hw = &ixgbe_init_hw_generic,
1257 .reset_hw = &ixgbe_reset_hw_82599,
1258 .start_hw = &ixgbe_start_hw_82599,
1259 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1260 .get_media_type = &ixgbe_get_media_type_82599,
1261 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1262 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1263 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1264 .stop_adapter = &ixgbe_stop_adapter_generic,
1265 .get_bus_info = &ixgbe_get_bus_info_generic,
1266 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1267 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1268 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1269 .setup_link = &ixgbe_setup_mac_link_82599,
1270 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
1271 .check_link = &ixgbe_check_mac_link_82599,
1272 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1273 .led_on = &ixgbe_led_on_generic,
1274 .led_off = &ixgbe_led_off_generic,
1275 .blink_led_start = &ixgbe_blink_led_start_82599,
1276 .blink_led_stop = &ixgbe_blink_led_stop_82599,
1277 .set_rar = &ixgbe_set_rar_generic,
1278 .clear_rar = &ixgbe_clear_rar_generic,
1279 .set_vmdq = &ixgbe_set_vmdq_82599,
1280 .clear_vmdq = &ixgbe_clear_vmdq_82599,
1281 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1282 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1283 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1284 .enable_mc = &ixgbe_enable_mc_generic,
1285 .disable_mc = &ixgbe_disable_mc_generic,
1286 .clear_vfta = &ixgbe_clear_vfta_82599,
1287 .set_vfta = &ixgbe_set_vfta_82599,
1288 .setup_fc = &ixgbe_setup_fc_generic,
1289 .init_uta_tables = &ixgbe_init_uta_tables_82599,
1290 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
1291};
1292
1293static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1294 .init_params = &ixgbe_init_eeprom_params_generic,
1295 .read = &ixgbe_read_eeprom_generic,
1296 .write = &ixgbe_write_eeprom_generic,
1297 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1298 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1299};
1300
1301static struct ixgbe_phy_operations phy_ops_82599 = {
1302 .identify = &ixgbe_identify_phy_82599,
1303 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 1304 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 1305 .reset = &ixgbe_reset_phy_generic,
1306 .read_reg = &ixgbe_read_phy_reg_generic,
1307 .write_reg = &ixgbe_write_phy_reg_generic,
1308 .setup_link = &ixgbe_setup_phy_link_generic,
1309 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1310 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
1311 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
1312 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
1313 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
1314};
1315
1316struct ixgbe_info ixgbe_82599_info = {
1317 .mac = ixgbe_mac_82599EB,
1318 .get_invariants = &ixgbe_get_invariants_82599,
1319 .mac_ops = &mac_ops_82599,
1320 .eeprom_ops = &eeprom_ops_82599,
1321 .phy_ops = &phy_ops_82599,
1322};
Linux 6.x block layer and io_uring tree(s)