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drivers/net/stmmac/: add HAS_IOMEM dependency
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
6fabd715 34#include <linux/aer.h>
9a799d71
AK		 35
36#include "ixgbe_type.h"
37#include "ixgbe_common.h"
2f90b865 38#include "ixgbe_dcb.h"
eacd73f7
YZ		 39#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
40#define IXGBE_FCOE
41#include "ixgbe_fcoe.h"
42#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 43#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 44#include <linux/dca.h>
45#endif
9a799d71 46
849c4542
ET		 47/* common prefix used by pr_<> macros */
48#undef pr_fmt
49#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 50
51/* TX/RX descriptor defines */
6bacb300 52#define IXGBE_DEFAULT_TXD 512
9a799d71
AK		 53#define IXGBE_MAX_TXD 4096
54#define IXGBE_MIN_TXD 64
55
6bacb300 56#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 57#define IXGBE_MAX_RXD 4096
58#define IXGBE_MIN_RXD 64
59
9a799d71
AK		 60/* flow control */
61#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93 62#define IXGBE_MIN_FCRTL 0x40
9a799d71
AK		 63#define IXGBE_MAX_FCRTL 0x7FF80
64#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93 65#define IXGBE_MIN_FCRTH 0x600
9a799d71 66#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 67#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 68#define IXGBE_MIN_FCPAUSE 0
69#define IXGBE_MAX_FCPAUSE 0xFFFF
70
71/* Supported Rx Buffer Sizes */
13958070 72#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
9a799d71 73#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 74#define IXGBE_RXBUFFER_4096 4096
75#define IXGBE_RXBUFFER_8192 8192
32344a39 76#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 77
13958070
AD		 78/*
79 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
80 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
81 * this adds up to 512 bytes of extra data meaning the smallest allocation
82 * we could have is 1K.
83 * i.e. RXBUFFER_512 --> size-1024 slab
84 */
85#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 86
87#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
88
9a799d71
AK		 89/* How many Rx Buffers do we bundle into one write to the hardware ? */
90#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
91
92#define IXGBE_TX_FLAGS_CSUM (u32)(1)
93#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
94#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
95#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7
YZ		 96#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
97#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 98#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 99#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71
AK		 100#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
101
0a924578
PWJ		 102#define IXGBE_MAX_RSC_INT_RATE 162760
103
7f870475
GR		 104#define IXGBE_MAX_VF_MC_ENTRIES 30
105#define IXGBE_MAX_VF_FUNCTIONS 64
106#define IXGBE_MAX_VFTA_ENTRIES 128
107#define MAX_EMULATION_MAC_ADDRS 16
108#define VMDQ_P(p) ((p) + adapter->num_vfs)
109
110struct vf_data_storage {
111 unsigned char vf_mac_addresses[ETH_ALEN];
112 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
113 u16 num_vf_mc_hashes;
114 u16 default_vf_vlan_id;
115 u16 vlans_enabled;
7f870475 116 bool clear_to_send;
7f01648a 117 bool pf_set_mac;
7f01648a
GR		 118 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
119 u16 pf_qos;
7f870475
GR		 120};
121
9a799d71
AK		 122/* wrapper around a pointer to a socket buffer,
123 * so a DMA handle can be stored along with the buffer */
124struct ixgbe_tx_buffer {
125 struct sk_buff *skb;
126 dma_addr_t dma;
127 unsigned long time_stamp;
128 u16 length;
129 u16 next_to_watch;
e5a43549 130 u16 mapped_as_page;
9a799d71
AK		 131};
132
133struct ixgbe_rx_buffer {
134 struct sk_buff *skb;
135 dma_addr_t dma;
136 struct page *page;
137 dma_addr_t page_dma;
762f4c57 138 unsigned int page_offset;
9a799d71
AK		 139};
140
141struct ixgbe_queue_stats {
142 u64 packets;
143 u64 bytes;
144};
145
146struct ixgbe_ring {
9a799d71 147 void *desc; /* descriptor ring memory */
9a799d71
AK		 148 union {
149 struct ixgbe_tx_buffer *tx_buffer_info;
150 struct ixgbe_rx_buffer *rx_buffer_info;
151 };
ae540af1
JB		 152 u8 atr_sample_rate;
153 u8 atr_count;
154 u16 count; /* amount of descriptors */
155 u16 rx_buf_len;
156 u16 next_to_use;
157 u16 next_to_clean;
158
159 u8 queue_index; /* needed for multiqueue queue management */
9a799d71 160
6e455b89
YZ		 161#define IXGBE_RING_RX_PS_ENABLED (u8)(1)
162 u8 flags; /* per ring feature flags */
9a799d71
AK		 163 u16 head;
164 u16 tail;
165
f494e8fa
AV		 166 unsigned int total_bytes;
167 unsigned int total_packets;
9a799d71 168
5dd2d332 169#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 170 /* cpu for tx queue */
171 int cpu;
172#endif
ae540af1
JB		 173
174 u16 work_limit; /* max work per interrupt */
175 u16 reg_idx; /* holds the special value that gets
176 * the hardware register offset
177 * associated with this ring, which is
178 * different for DCB and RSS modes
179 */
180
9a799d71 181 struct ixgbe_queue_stats stats;
c4cf55e5 182 unsigned long reinit_state;
4a0b9ca0 183 int numa_node;
ae540af1 184 u64 rsc_count; /* stat for coalesced packets */
94b982b2 185 u64 rsc_flush; /* stats for flushed packets */
7ca3bc58
JB		 186 u32 restart_queue; /* track tx queue restarts */
187 u32 non_eop_descs; /* track hardware descriptor chaining */
9a799d71 188
ae540af1
JB		 189 unsigned int size; /* length in bytes */
190 dma_addr_t dma; /* phys. address of descriptor ring */
7ca3bc58 191} ____cacheline_internodealigned_in_smp;
9a799d71 192
c7e4358a
SN		 193enum ixgbe_ring_f_enum {
194 RING_F_NONE = 0,
195 RING_F_DCB,
7f870475 196 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 197 RING_F_RSS,
c4cf55e5 198 RING_F_FDIR,
0331a832
YZ		 199#ifdef IXGBE_FCOE
200 RING_F_FCOE,
201#endif /* IXGBE_FCOE */
c7e4358a
SN		 202
203 RING_F_ARRAY_SIZE /* must be last in enum set */
204};
205
2f90b865 206#define IXGBE_MAX_DCB_INDICES 8
021230d4 207#define IXGBE_MAX_RSS_INDICES 16
7f870475 208#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 209#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 210#ifdef IXGBE_FCOE
211#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 212#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
213#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
214#else
215#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
216#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 217#endif /* IXGBE_FCOE */
021230d4
AV		 218struct ixgbe_ring_feature {
219 int indices;
220 int mask;
7ca3bc58 221} ____cacheline_internodealigned_in_smp;
021230d4 222
021230d4 223
2f90b865
AD		 224#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
225 ? 8 : 1)
226#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
227
021230d4
AV		 228/* MAX_MSIX_Q_VECTORS of these are allocated,
229 * but we only use one per queue-specific vector.
230 */
231struct ixgbe_q_vector {
232 struct ixgbe_adapter *adapter;
fe49f04a
AD		 233 unsigned int v_idx; /* index of q_vector within array, also used for
234 * finding the bit in EICR and friends that
235 * represents the vector for this ring */
021230d4
AV		 236 struct napi_struct napi;
237 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
238 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
239 u8 rxr_count; /* Rx ring count assigned to this vector */
240 u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3
JB		 241 u8 tx_itr;
242 u8 rx_itr;
021230d4
AV		 243 u32 eitr;
244};
245
9a799d71 246/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 247 * And yes, it's the same math going both ways. The lowest value
248 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 249 */
250#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 251 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 252#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
253
254#define IXGBE_DESC_UNUSED(R) \
255 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
256 (R)->next_to_clean - (R)->next_to_use - 1)
257
258#define IXGBE_RX_DESC_ADV(R, i) \
31f05a2d 259 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
9a799d71 260#define IXGBE_TX_DESC_ADV(R, i) \
31f05a2d 261 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
9a799d71 262#define IXGBE_TX_CTXTDESC_ADV(R, i) \
31f05a2d 263 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 264
265#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 266#ifdef IXGBE_FCOE
267/* Use 3K as the baby jumbo frame size for FCoE */
268#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
269#endif /* IXGBE_FCOE */
9a799d71 270
021230d4
AV		 271#define OTHER_VECTOR 1
272#define NON_Q_VECTORS (OTHER_VECTOR)
273
e8e26350
PW		 274#define MAX_MSIX_VECTORS_82599 64
275#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 276#define MAX_MSIX_VECTORS_82598 18
277#define MAX_MSIX_Q_VECTORS_82598 16
278
e8e26350
PW		 279#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
280#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 281
021230d4 282#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 283#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
284
9a799d71
AK		 285/* board specific private data structure */
286struct ixgbe_adapter {
287 struct timer_list watchdog_timer;
288 struct vlan_group *vlgrp;
289 u16 bd_number;
9a799d71 290 struct work_struct reset_task;
7a921c93 291 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
e8e26350 292 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
2f90b865
AD		 293 struct ixgbe_dcb_config dcb_cfg;
294 struct ixgbe_dcb_config temp_dcb_cfg;
295 u8 dcb_set_bitmap;
264857b8 296 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 297
f494e8fa 298 /* Interrupt Throttle Rate */
f7554a2b
NS		 299 u32 rx_itr_setting;
300 u32 tx_itr_setting;
f494e8fa
AV		 301 u16 eitr_low;
302 u16 eitr_high;
303
9a799d71 304 /* TX */
4a0b9ca0 305 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 306 int num_tx_queues;
9a799d71
AK		 307 u32 tx_timeout_count;
308 bool detect_tx_hung;
309
7ca3bc58
JB		 310 u64 restart_queue;
311 u64 lsc_int;
312
9a799d71 313 /* RX */
4a0b9ca0 314 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 315 int num_rx_queues;
7f870475
GR		 316 int num_rx_pools; /* == num_rx_queues in 82598 */
317 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 318 u64 hw_csum_rx_error;
e8e26350 319 u64 hw_rx_no_dma_resources;
9a799d71 320 u64 non_eop_descs;
021230d4 321 int num_msix_vectors;
eb7f139c 322 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 323 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 324 struct msix_entry *msix_entries;
325
9a799d71
AK		 326 u32 alloc_rx_page_failed;
327 u32 alloc_rx_buff_failed;
328
021230d4
AV		 329 /* Some features need tri-state capability,
330 * thus the additional *_CAPABLE flags.
331 */
9a799d71 332 u32 flags;
96b0e0f6
JB		 333#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
334#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
335#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
336#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
337#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
338#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
339#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
340#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
341#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
342#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
343#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
344#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
345#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350 346#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6
JB		 347#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
348#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
349#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
350#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e 351#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6 352#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
10eec955
JF		 353#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
354#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
355#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
356#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
357#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
358#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
359#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
360#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
96b0e0f6 361
df647b5c
PWJ		 362 u32 flags2;
363#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
364#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
119fc60a 365#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
96b0e0f6
JB		 366/* default to trying for four seconds */
367#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 368
369 /* OS defined structs */
370 struct net_device *netdev;
371 struct pci_dev *pdev;
9a799d71 372
da4dd0f7
PWJ		 373 u32 test_icr;
374 struct ixgbe_ring test_tx_ring;
375 struct ixgbe_ring test_rx_ring;
376
9a799d71
AK		 377 /* structs defined in ixgbe_hw.h */
378 struct ixgbe_hw hw;
379 u16 msg_enable;
380 struct ixgbe_hw_stats stats;
021230d4
AV		 381
382 /* Interrupt Throttle Rate */
f7554a2b
NS		 383 u32 rx_eitr_param;
384 u32 tx_eitr_param;
9a799d71
AK		 385
386 unsigned long state;
387 u64 tx_busy;
30efa5a3
JB		 388 unsigned int tx_ring_count;
389 unsigned int rx_ring_count;
cf8280ee
JB		 390
391 u32 link_speed;
392 bool link_up;
393 unsigned long link_check_timeout;
394
395 struct work_struct watchdog_task;
c4900be0
DS		 396 struct work_struct sfp_task;
397 struct timer_list sfp_timer;
e8e26350
PW		 398 struct work_struct multispeed_fiber_task;
399 struct work_struct sfp_config_module_task;
c4cf55e5
PWJ		 400 u32 fdir_pballoc;
401 u32 atr_sample_rate;
402 spinlock_t fdir_perfect_lock;
403 struct work_struct fdir_reinit_task;
d0ed8937
YZ		 404#ifdef IXGBE_FCOE
405 struct ixgbe_fcoe fcoe;
406#endif /* IXGBE_FCOE */
94b982b2
MC		 407 u64 rsc_total_count;
408 u64 rsc_total_flush;
e8e26350 409 u32 wol;
34b0368c 410 u16 eeprom_version;
7f870475 411
1a6c14a2 412 int node;
119fc60a
MC		 413 struct work_struct check_overtemp_task;
414 u32 interrupt_event;
1a6c14a2 415
7f870475
GR		 416 /* SR-IOV */
417 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
418 unsigned int num_vfs;
419 struct vf_data_storage *vfinfo;
9a799d71
AK		 420};
421
422enum ixbge_state_t {
423 __IXGBE_TESTING,
424 __IXGBE_RESETTING,
c4900be0 425 __IXGBE_DOWN,
c4cf55e5 426 __IXGBE_FDIR_INIT_DONE,
c4900be0 427 __IXGBE_SFP_MODULE_NOT_FOUND
9a799d71
AK		 428};
429
430enum ixgbe_boards {
3957d63d 431 board_82598,
e8e26350 432 board_82599,
9a799d71
AK		 433};
434
3957d63d 435extern struct ixgbe_info ixgbe_82598_info;
e8e26350 436extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51 437#ifdef CONFIG_IXGBE_DCB
32953543 438extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865
AD		 439extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
440 struct ixgbe_dcb_config *dst_dcb_cfg,
441 int tc_max);
442#endif
9a799d71
AK		 443
444extern char ixgbe_driver_name[];
9c8eb720 445extern const char ixgbe_driver_version[];
9a799d71
AK		 446
447extern int ixgbe_up(struct ixgbe_adapter *adapter);
448extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 449extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 450extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 451extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240
PW		 452extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
453extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
454extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
455extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
84418e3b
AD		 456extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
457extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
b4617240 458extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 459extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 460extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b
AD		 461extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
462 struct net_device *,
463 struct ixgbe_adapter *,
464 struct ixgbe_ring *);
465extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *,
466 struct ixgbe_tx_buffer *);
467extern void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
468 struct ixgbe_ring *rx_ring,
469 int cleaned_count);
fe49f04a
AD		 470extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
471extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772
PWJ		 472extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
473extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
474extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
475extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
476 struct ixgbe_atr_input *input,
477 u8 queue);
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PW		 478extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
479 struct ixgbe_atr_input *input,
480 struct ixgbe_atr_input_masks *input_masks,
481 u16 soft_id, u8 queue);
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PWJ		 482extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
483 u16 vlan_id);
484extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
485 u32 src_addr);
486extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
487 u32 dst_addr);
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PWJ		 488extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
489 u16 src_port);
490extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
491 u16 dst_port);
492extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
493 u16 flex_byte);
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PWJ		 494extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
495 u8 l4type);
7f870475 496extern void ixgbe_set_rx_mode(struct net_device *netdev);
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YZ		 497#ifdef IXGBE_FCOE
498extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
499extern int ixgbe_fso(struct ixgbe_adapter *adapter,
500 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
501 u32 tx_flags, u8 *hdr_len);
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YZ		 502extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
503extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
504 union ixgbe_adv_rx_desc *rx_desc,
505 struct sk_buff *skb);
506extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
507 struct scatterlist *sgl, unsigned int sgc);
508extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
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YZ		 509extern int ixgbe_fcoe_enable(struct net_device *netdev);
510extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 511#ifdef CONFIG_IXGBE_DCB
512extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
513extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
514#endif /* CONFIG_IXGBE_DCB */
61a1fa10 515extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
eacd73f7 516#endif /* IXGBE_FCOE */
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AK		 517
518#endif /* _IXGBE_H_ */
Linux 6.x block layer and io_uring tree(s)