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ixgbe: Add one function that handles most of context descriptor setup
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
f62bbb5e 31#include <linux/bitops.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
b25ebfd2 35#include <linux/cpumask.h>
6fabd715 36#include <linux/aer.h>
f62bbb5e 37#include <linux/if_vlan.h>
9a799d71
AK		 38
39#include "ixgbe_type.h"
40#include "ixgbe_common.h"
2f90b865 41#include "ixgbe_dcb.h"
eacd73f7
YZ		 42#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
43#define IXGBE_FCOE
44#include "ixgbe_fcoe.h"
45#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 46#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 47#include <linux/dca.h>
48#endif
9a799d71 49
849c4542
ET		 50/* common prefix used by pr_<> macros */
51#undef pr_fmt
52#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 53
54/* TX/RX descriptor defines */
6bacb300 55#define IXGBE_DEFAULT_TXD 512
9a799d71
AK		 56#define IXGBE_MAX_TXD 4096
57#define IXGBE_MIN_TXD 64
58
6bacb300 59#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 60#define IXGBE_MAX_RXD 4096
61#define IXGBE_MIN_RXD 64
62
9a799d71 63/* flow control */
2b9ade93 64#define IXGBE_MIN_FCRTL 0x40
9a799d71 65#define IXGBE_MAX_FCRTL 0x7FF80
2b9ade93 66#define IXGBE_MIN_FCRTH 0x600
9a799d71 67#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 68#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 69#define IXGBE_MIN_FCPAUSE 0
70#define IXGBE_MAX_FCPAUSE 0xFFFF
71
72/* Supported Rx Buffer Sizes */
13958070 73#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
9a799d71 74#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 75#define IXGBE_RXBUFFER_4096 4096
76#define IXGBE_RXBUFFER_8192 8192
32344a39 77#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 78
13958070
AD		 79/*
80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
82 * this adds up to 512 bytes of extra data meaning the smallest allocation
83 * we could have is 1K.
84 * i.e. RXBUFFER_512 --> size-1024 slab
85 */
86#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 87
88#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
89
9a799d71
AK		 90/* How many Rx Buffers do we bundle into one write to the hardware ? */
91#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92
93#define IXGBE_TX_FLAGS_CSUM (u32)(1)
94#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7
YZ		 97#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
98#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 99#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 100#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71
AK		 101#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
102
0a924578
PWJ		 103#define IXGBE_MAX_RSC_INT_RATE 162760
104
7f870475
GR		 105#define IXGBE_MAX_VF_MC_ENTRIES 30
106#define IXGBE_MAX_VF_FUNCTIONS 64
107#define IXGBE_MAX_VFTA_ENTRIES 128
108#define MAX_EMULATION_MAC_ADDRS 16
a1cbb15c 109#define IXGBE_MAX_PF_MACVLANS 15
7f870475
GR		 110#define VMDQ_P(p) ((p) + adapter->num_vfs)
111
112struct vf_data_storage {
113 unsigned char vf_mac_addresses[ETH_ALEN];
114 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
115 u16 num_vf_mc_hashes;
116 u16 default_vf_vlan_id;
117 u16 vlans_enabled;
7f870475 118 bool clear_to_send;
7f01648a 119 bool pf_set_mac;
7f01648a
GR		 120 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
121 u16 pf_qos;
ff4ab206 122 u16 tx_rate;
7f870475
GR		 123};
124
a1cbb15c
GR		 125struct vf_macvlans {
126 struct list_head l;
127 int vf;
128 int rar_entry;
129 bool free;
130 bool is_macvlan;
131 u8 vf_macvlan[ETH_ALEN];
132};
133
9a799d71
AK		 134/* wrapper around a pointer to a socket buffer,
135 * so a DMA handle can be stored along with the buffer */
136struct ixgbe_tx_buffer {
137 struct sk_buff *skb;
138 dma_addr_t dma;
139 unsigned long time_stamp;
140 u16 length;
141 u16 next_to_watch;
8ad494b0
AD		 142 unsigned int bytecount;
143 u16 gso_segs;
144 u8 mapped_as_page;
9a799d71
AK		 145};
146
147struct ixgbe_rx_buffer {
148 struct sk_buff *skb;
149 dma_addr_t dma;
150 struct page *page;
151 dma_addr_t page_dma;
762f4c57 152 unsigned int page_offset;
9a799d71
AK		 153};
154
155struct ixgbe_queue_stats {
156 u64 packets;
157 u64 bytes;
158};
159
5b7da515
AD		 160struct ixgbe_tx_queue_stats {
161 u64 restart_queue;
162 u64 tx_busy;
c84d324c
JF		 163 u64 completed;
164 u64 tx_done_old;
5b7da515
AD		 165};
166
167struct ixgbe_rx_queue_stats {
168 u64 rsc_count;
169 u64 rsc_flush;
170 u64 non_eop_descs;
171 u64 alloc_rx_page_failed;
172 u64 alloc_rx_buff_failed;
173};
174
7d637bcc
AD		 175enum ixbge_ring_state_t {
176 __IXGBE_TX_FDIR_INIT_DONE,
177 __IXGBE_TX_DETECT_HANG,
c84d324c 178 __IXGBE_HANG_CHECK_ARMED,
7d637bcc
AD		 179 __IXGBE_RX_PS_ENABLED,
180 __IXGBE_RX_RSC_ENABLED,
181};
182
183#define ring_is_ps_enabled(ring) \
184 test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
185#define set_ring_ps_enabled(ring) \
186 set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
187#define clear_ring_ps_enabled(ring) \
188 clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
189#define check_for_tx_hang(ring) \
190 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
191#define set_check_for_tx_hang(ring) \
192 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
193#define clear_check_for_tx_hang(ring) \
194 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
195#define ring_is_rsc_enabled(ring) \
196 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
197#define set_ring_rsc_enabled(ring) \
198 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
199#define clear_ring_rsc_enabled(ring) \
200 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
9a799d71 201struct ixgbe_ring {
9a799d71 202 void *desc; /* descriptor ring memory */
b6ec895e 203 struct device *dev; /* device for DMA mapping */
fc77dc3c 204 struct net_device *netdev; /* netdev ring belongs to */
9a799d71
AK		 205 union {
206 struct ixgbe_tx_buffer *tx_buffer_info;
207 struct ixgbe_rx_buffer *rx_buffer_info;
208 };
7d637bcc 209 unsigned long state;
ae540af1
JB		 210 u8 atr_sample_rate;
211 u8 atr_count;
212 u16 count; /* amount of descriptors */
213 u16 rx_buf_len;
214 u16 next_to_use;
215 u16 next_to_clean;
216
217 u8 queue_index; /* needed for multiqueue queue management */
7d637bcc
AD		 218 u8 reg_idx; /* holds the special value that gets
219 * the hardware register offset
220 * associated with this ring, which is
221 * different for DCB and RSS modes
222 */
e5b64635 223 u8 dcb_tc;
7d637bcc
AD		 224
225 u16 work_limit; /* max work per interrupt */
9a799d71 226
84ea2591 227 u8 __iomem *tail;
9a799d71 228
f494e8fa
AV		 229 unsigned int total_bytes;
230 unsigned int total_packets;
9a799d71
AK		 231
232 struct ixgbe_queue_stats stats;
de1036b1 233 struct u64_stats_sync syncp;
5b7da515
AD		 234 union {
235 struct ixgbe_tx_queue_stats tx_stats;
236 struct ixgbe_rx_queue_stats rx_stats;
237 };
5b7da515 238 int numa_node;
ae540af1
JB		 239 unsigned int size; /* length in bytes */
240 dma_addr_t dma; /* phys. address of descriptor ring */
1a51502b 241 struct rcu_head rcu;
33cf09c9 242 struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
7ca3bc58 243} ____cacheline_internodealigned_in_smp;
9a799d71 244
c7e4358a
SN		 245enum ixgbe_ring_f_enum {
246 RING_F_NONE = 0,
7f870475 247 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 248 RING_F_RSS,
c4cf55e5 249 RING_F_FDIR,
0331a832
YZ		 250#ifdef IXGBE_FCOE
251 RING_F_FCOE,
252#endif /* IXGBE_FCOE */
c7e4358a
SN		 253
254 RING_F_ARRAY_SIZE /* must be last in enum set */
255};
256
021230d4 257#define IXGBE_MAX_RSS_INDICES 16
7f870475 258#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 259#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 260#ifdef IXGBE_FCOE
261#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 262#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
263#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
264#else
265#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
266#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 267#endif /* IXGBE_FCOE */
021230d4
AV		 268struct ixgbe_ring_feature {
269 int indices;
270 int mask;
7ca3bc58 271} ____cacheline_internodealigned_in_smp;
021230d4 272
021230d4 273
2f90b865
AD		 274#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
275 ? 8 : 1)
276#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
277
021230d4
AV		 278/* MAX_MSIX_Q_VECTORS of these are allocated,
279 * but we only use one per queue-specific vector.
280 */
281struct ixgbe_q_vector {
282 struct ixgbe_adapter *adapter;
fe49f04a
AD		 283 unsigned int v_idx; /* index of q_vector within array, also used for
284 * finding the bit in EICR and friends that
285 * represents the vector for this ring */
33cf09c9
AD		 286#ifdef CONFIG_IXGBE_DCA
287 int cpu; /* CPU for DCA */
288#endif
021230d4
AV		 289 struct napi_struct napi;
290 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
291 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
292 u8 rxr_count; /* Rx ring count assigned to this vector */
293 u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3
JB		 294 u8 tx_itr;
295 u8 rx_itr;
021230d4 296 u32 eitr;
b25ebfd2 297 cpumask_var_t affinity_mask;
d0759ebb 298 char name[IFNAMSIZ + 9];
021230d4
AV		 299};
300
9a799d71 301/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 302 * And yes, it's the same math going both ways. The lowest value
303 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 304 */
305#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 306 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 307#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
308
7d4987de
AD		 309static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
310{
311 u16 ntc = ring->next_to_clean;
312 u16 ntu = ring->next_to_use;
313
314 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
315}
9a799d71
AK		 316
317#define IXGBE_RX_DESC_ADV(R, i) \
31f05a2d 318 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
9a799d71 319#define IXGBE_TX_DESC_ADV(R, i) \
31f05a2d 320 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
9a799d71 321#define IXGBE_TX_CTXTDESC_ADV(R, i) \
31f05a2d 322 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 323
324#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 325#ifdef IXGBE_FCOE
326/* Use 3K as the baby jumbo frame size for FCoE */
327#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
328#endif /* IXGBE_FCOE */
9a799d71 329
021230d4
AV		 330#define OTHER_VECTOR 1
331#define NON_Q_VECTORS (OTHER_VECTOR)
332
e8e26350
PW		 333#define MAX_MSIX_VECTORS_82599 64
334#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 335#define MAX_MSIX_VECTORS_82598 18
336#define MAX_MSIX_Q_VECTORS_82598 16
337
e8e26350
PW		 338#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
339#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 340
021230d4 341#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 342#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
343
9a799d71
AK		 344/* board specific private data structure */
345struct ixgbe_adapter {
e606bfe7
AD		 346 unsigned long state;
347
348 /* Some features need tri-state capability,
349 * thus the additional *_CAPABLE flags.
350 */
351 u32 flags;
352#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
353#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
354#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
355#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
356#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
357#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
358#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
359#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
360#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
361#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
362#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
363#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
364#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
365#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
366#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
367#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
368#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
369#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
370#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
371#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
7086400d
AD		 372#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
373#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
374#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
375#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
376#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
377#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
378#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
e606bfe7
AD		 379
380 u32 flags2;
381#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
382#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
383#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
f0f9778d 384#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
7086400d
AD		 385#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
386#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
c83c6cbd 387#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
d034acf1 388#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
e606bfe7 389
f62bbb5e 390 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
9a799d71 391 u16 bd_number;
7a921c93 392 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
d033d526
JF		 393
394 /* DCB parameters */
395 struct ieee_pfc *ixgbe_ieee_pfc;
396 struct ieee_ets *ixgbe_ieee_ets;
2f90b865
AD		 397 struct ixgbe_dcb_config dcb_cfg;
398 struct ixgbe_dcb_config temp_dcb_cfg;
399 u8 dcb_set_bitmap;
3032309b 400 u8 dcbx_cap;
264857b8 401 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 402
f494e8fa 403 /* Interrupt Throttle Rate */
f7554a2b
NS		 404 u32 rx_itr_setting;
405 u32 tx_itr_setting;
f494e8fa
AV		 406 u16 eitr_low;
407 u16 eitr_high;
408
9a799d71 409 /* TX */
4a0b9ca0 410 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 411 int num_tx_queues;
9a799d71
AK		 412 u32 tx_timeout_count;
413 bool detect_tx_hung;
414
7ca3bc58
JB		 415 u64 restart_queue;
416 u64 lsc_int;
417
9a799d71 418 /* RX */
4a0b9ca0 419 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 420 int num_rx_queues;
7f870475
GR		 421 int num_rx_pools; /* == num_rx_queues in 82598 */
422 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 423 u64 hw_csum_rx_error;
e8e26350 424 u64 hw_rx_no_dma_resources;
9a799d71 425 u64 non_eop_descs;
021230d4 426 int num_msix_vectors;
eb7f139c 427 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 428 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 429 struct msix_entry *msix_entries;
430
9a799d71
AK		 431 u32 alloc_rx_page_failed;
432 u32 alloc_rx_buff_failed;
433
96b0e0f6
JB		 434/* default to trying for four seconds */
435#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 436
437 /* OS defined structs */
438 struct net_device *netdev;
439 struct pci_dev *pdev;
9a799d71 440
da4dd0f7
PWJ		 441 u32 test_icr;
442 struct ixgbe_ring test_tx_ring;
443 struct ixgbe_ring test_rx_ring;
444
9a799d71
AK		 445 /* structs defined in ixgbe_hw.h */
446 struct ixgbe_hw hw;
447 u16 msg_enable;
448 struct ixgbe_hw_stats stats;
021230d4
AV		 449
450 /* Interrupt Throttle Rate */
f7554a2b
NS		 451 u32 rx_eitr_param;
452 u32 tx_eitr_param;
9a799d71 453
9a799d71 454 u64 tx_busy;
30efa5a3
JB		 455 unsigned int tx_ring_count;
456 unsigned int rx_ring_count;
cf8280ee
JB		 457
458 u32 link_speed;
459 bool link_up;
460 unsigned long link_check_timeout;
461
7086400d 462 struct work_struct service_task;
7086400d 463 struct timer_list service_timer;
c4cf55e5
PWJ		 464 u32 fdir_pballoc;
465 u32 atr_sample_rate;
d034acf1 466 unsigned long fdir_overflow; /* number of times ATR was backed off */
c4cf55e5 467 spinlock_t fdir_perfect_lock;
d0ed8937
YZ		 468#ifdef IXGBE_FCOE
469 struct ixgbe_fcoe fcoe;
470#endif /* IXGBE_FCOE */
94b982b2
MC		 471 u64 rsc_total_count;
472 u64 rsc_total_flush;
e8e26350 473 u32 wol;
34b0368c 474 u16 eeprom_version;
7f870475 475
1a6c14a2 476 int node;
66e6961c 477 u32 led_reg;
119fc60a 478 u32 interrupt_event;
d0759ebb 479 char lsc_int_name[IFNAMSIZ + 9];
1a6c14a2 480
7f870475
GR		 481 /* SR-IOV */
482 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
483 unsigned int num_vfs;
484 struct vf_data_storage *vfinfo;
ff4ab206 485 int vf_rate_link_speed;
a1cbb15c
GR		 486 struct vf_macvlans vf_mvs;
487 struct vf_macvlans *mv_list;
488 bool antispoofing_enabled;
3e05334f
AD		 489
490 struct hlist_head fdir_filter_list;
491 union ixgbe_atr_input fdir_mask;
492 int fdir_filter_count;
493};
494
495struct ixgbe_fdir_filter {
496 struct hlist_node fdir_node;
497 union ixgbe_atr_input filter;
498 u16 sw_idx;
499 u16 action;
9a799d71
AK		 500};
501
502enum ixbge_state_t {
503 __IXGBE_TESTING,
504 __IXGBE_RESETTING,
c4900be0 505 __IXGBE_DOWN,
7086400d
AD		 506 __IXGBE_SERVICE_SCHED,
507 __IXGBE_IN_SFP_INIT,
9a799d71
AK		 508};
509
aa80175a
AD		 510struct ixgbe_rsc_cb {
511 dma_addr_t dma;
512 u16 skb_cnt;
513 bool delay_unmap;
514};
515#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
516
9a799d71 517enum ixgbe_boards {
3957d63d 518 board_82598,
e8e26350 519 board_82599,
fe15e8e1 520 board_X540,
9a799d71
AK		 521};
522
3957d63d 523extern struct ixgbe_info ixgbe_82598_info;
e8e26350 524extern struct ixgbe_info ixgbe_82599_info;
fe15e8e1 525extern struct ixgbe_info ixgbe_X540_info;
7a6b6f51 526#ifdef CONFIG_IXGBE_DCB
32953543 527extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865
AD		 528extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
529 struct ixgbe_dcb_config *dst_dcb_cfg,
530 int tc_max);
531#endif
9a799d71
AK		 532
533extern char ixgbe_driver_name[];
9c8eb720 534extern const char ixgbe_driver_version[];
9a799d71
AK		 535
536extern int ixgbe_up(struct ixgbe_adapter *adapter);
537extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 538extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 539extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 540extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b6ec895e
AD		 541extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
542extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
543extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
544extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
84418e3b
AD		 545extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
546extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
2d39d576
YZ		 547extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
548 struct ixgbe_ring *);
b4617240 549extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 550extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 551extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b 552extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
84418e3b
AD		 553 struct ixgbe_adapter *,
554 struct ixgbe_ring *);
b6ec895e 555extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
84418e3b 556 struct ixgbe_tx_buffer *);
fc77dc3c 557extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
fe49f04a
AD		 558extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
559extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772 560extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
c04f6ca8
AD		 561extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
562extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
ffff4772 563extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 564 union ixgbe_atr_hash_dword input,
565 union ixgbe_atr_hash_dword common,
ffff4772 566 u8 queue);
c04f6ca8
AD		 567extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
568 union ixgbe_atr_input *input_mask);
569extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
570 union ixgbe_atr_input *input,
571 u16 soft_id, u8 queue);
572extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
573 union ixgbe_atr_input *input,
574 u16 soft_id);
575extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
576 union ixgbe_atr_input *mask);
b93a2226
DS		 577extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
578 struct ixgbe_ring *ring);
579extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
580 struct ixgbe_ring *ring);
7f870475 581extern void ixgbe_set_rx_mode(struct net_device *netdev);
e5b64635 582extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
897ab156 583extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
eacd73f7
YZ		 584#ifdef IXGBE_FCOE
585extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
897ab156 586extern int ixgbe_fso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
eacd73f7 587 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ		 588extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
589extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
590 union ixgbe_adv_rx_desc *rx_desc,
591 struct sk_buff *skb);
592extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
593 struct scatterlist *sgl, unsigned int sgc);
68a683cf
YZ		 594extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
595 struct scatterlist *sgl, unsigned int sgc);
332d4a7d 596extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ		 597extern int ixgbe_fcoe_enable(struct net_device *netdev);
598extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 599#ifdef CONFIG_IXGBE_DCB
600extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
601extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
602#endif /* CONFIG_IXGBE_DCB */
61a1fa10 603extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
eacd73f7 604#endif /* IXGBE_FCOE */
9a799d71
AK		 605
606#endif /* _IXGBE_H_ */
Linux 6.x block layer and io_uring tree(s)