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bnx2: Update bnx2 to use new vlan accleration.
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
b25ebfd2 34#include <linux/cpumask.h>
6fabd715 35#include <linux/aer.h>
9a799d71
AK		 36
37#include "ixgbe_type.h"
38#include "ixgbe_common.h"
2f90b865 39#include "ixgbe_dcb.h"
eacd73f7
YZ		 40#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
41#define IXGBE_FCOE
42#include "ixgbe_fcoe.h"
43#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 44#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 45#include <linux/dca.h>
46#endif
9a799d71 47
849c4542
ET		 48/* common prefix used by pr_<> macros */
49#undef pr_fmt
50#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 51
52/* TX/RX descriptor defines */
6bacb300 53#define IXGBE_DEFAULT_TXD 512
9a799d71
AK		 54#define IXGBE_MAX_TXD 4096
55#define IXGBE_MIN_TXD 64
56
6bacb300 57#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 58#define IXGBE_MAX_RXD 4096
59#define IXGBE_MIN_RXD 64
60
9a799d71
AK		 61/* flow control */
62#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93 63#define IXGBE_MIN_FCRTL 0x40
9a799d71
AK		 64#define IXGBE_MAX_FCRTL 0x7FF80
65#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93 66#define IXGBE_MIN_FCRTH 0x600
9a799d71 67#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 68#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 69#define IXGBE_MIN_FCPAUSE 0
70#define IXGBE_MAX_FCPAUSE 0xFFFF
71
72/* Supported Rx Buffer Sizes */
13958070 73#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
9a799d71 74#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 75#define IXGBE_RXBUFFER_4096 4096
76#define IXGBE_RXBUFFER_8192 8192
32344a39 77#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 78
13958070
AD		 79/*
80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
82 * this adds up to 512 bytes of extra data meaning the smallest allocation
83 * we could have is 1K.
84 * i.e. RXBUFFER_512 --> size-1024 slab
85 */
86#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 87
88#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
89
9a799d71
AK		 90/* How many Rx Buffers do we bundle into one write to the hardware ? */
91#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92
93#define IXGBE_TX_FLAGS_CSUM (u32)(1)
94#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7
YZ		 97#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
98#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 99#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 100#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71
AK		 101#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
102
0a924578
PWJ		 103#define IXGBE_MAX_RSC_INT_RATE 162760
104
7f870475
GR		 105#define IXGBE_MAX_VF_MC_ENTRIES 30
106#define IXGBE_MAX_VF_FUNCTIONS 64
107#define IXGBE_MAX_VFTA_ENTRIES 128
108#define MAX_EMULATION_MAC_ADDRS 16
109#define VMDQ_P(p) ((p) + adapter->num_vfs)
110
111struct vf_data_storage {
112 unsigned char vf_mac_addresses[ETH_ALEN];
113 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
114 u16 num_vf_mc_hashes;
115 u16 default_vf_vlan_id;
116 u16 vlans_enabled;
7f870475 117 bool clear_to_send;
7f01648a 118 bool pf_set_mac;
7f01648a
GR		 119 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
120 u16 pf_qos;
7f870475
GR		 121};
122
9a799d71
AK		 123/* wrapper around a pointer to a socket buffer,
124 * so a DMA handle can be stored along with the buffer */
125struct ixgbe_tx_buffer {
126 struct sk_buff *skb;
127 dma_addr_t dma;
128 unsigned long time_stamp;
129 u16 length;
130 u16 next_to_watch;
e5a43549 131 u16 mapped_as_page;
9a799d71
AK		 132};
133
134struct ixgbe_rx_buffer {
135 struct sk_buff *skb;
136 dma_addr_t dma;
137 struct page *page;
138 dma_addr_t page_dma;
762f4c57 139 unsigned int page_offset;
9a799d71
AK		 140};
141
142struct ixgbe_queue_stats {
143 u64 packets;
144 u64 bytes;
145};
146
147struct ixgbe_ring {
9a799d71 148 void *desc; /* descriptor ring memory */
9a799d71
AK		 149 union {
150 struct ixgbe_tx_buffer *tx_buffer_info;
151 struct ixgbe_rx_buffer *rx_buffer_info;
152 };
ae540af1
JB		 153 u8 atr_sample_rate;
154 u8 atr_count;
155 u16 count; /* amount of descriptors */
156 u16 rx_buf_len;
157 u16 next_to_use;
158 u16 next_to_clean;
159
160 u8 queue_index; /* needed for multiqueue queue management */
9a799d71 161
6e455b89
YZ		 162#define IXGBE_RING_RX_PS_ENABLED (u8)(1)
163 u8 flags; /* per ring feature flags */
9a799d71
AK		 164 u16 head;
165 u16 tail;
166
f494e8fa
AV		 167 unsigned int total_bytes;
168 unsigned int total_packets;
9a799d71 169
5dd2d332 170#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 171 /* cpu for tx queue */
172 int cpu;
173#endif
ae540af1
JB		 174
175 u16 work_limit; /* max work per interrupt */
176 u16 reg_idx; /* holds the special value that gets
177 * the hardware register offset
178 * associated with this ring, which is
179 * different for DCB and RSS modes
180 */
181
9a799d71 182 struct ixgbe_queue_stats stats;
c4cf55e5 183 unsigned long reinit_state;
4a0b9ca0 184 int numa_node;
ae540af1 185 u64 rsc_count; /* stat for coalesced packets */
94b982b2 186 u64 rsc_flush; /* stats for flushed packets */
7ca3bc58
JB		 187 u32 restart_queue; /* track tx queue restarts */
188 u32 non_eop_descs; /* track hardware descriptor chaining */
9a799d71 189
ae540af1
JB		 190 unsigned int size; /* length in bytes */
191 dma_addr_t dma; /* phys. address of descriptor ring */
7ca3bc58 192} ____cacheline_internodealigned_in_smp;
9a799d71 193
c7e4358a
SN		 194enum ixgbe_ring_f_enum {
195 RING_F_NONE = 0,
196 RING_F_DCB,
7f870475 197 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 198 RING_F_RSS,
c4cf55e5 199 RING_F_FDIR,
0331a832
YZ		 200#ifdef IXGBE_FCOE
201 RING_F_FCOE,
202#endif /* IXGBE_FCOE */
c7e4358a
SN		 203
204 RING_F_ARRAY_SIZE /* must be last in enum set */
205};
206
2f90b865 207#define IXGBE_MAX_DCB_INDICES 8
021230d4 208#define IXGBE_MAX_RSS_INDICES 16
7f870475 209#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 210#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 211#ifdef IXGBE_FCOE
212#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 213#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
214#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
215#else
216#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
217#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 218#endif /* IXGBE_FCOE */
021230d4
AV		 219struct ixgbe_ring_feature {
220 int indices;
221 int mask;
7ca3bc58 222} ____cacheline_internodealigned_in_smp;
021230d4 223
021230d4 224
2f90b865
AD		 225#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
226 ? 8 : 1)
227#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
228
021230d4
AV		 229/* MAX_MSIX_Q_VECTORS of these are allocated,
230 * but we only use one per queue-specific vector.
231 */
232struct ixgbe_q_vector {
233 struct ixgbe_adapter *adapter;
fe49f04a
AD		 234 unsigned int v_idx; /* index of q_vector within array, also used for
235 * finding the bit in EICR and friends that
236 * represents the vector for this ring */
021230d4
AV		 237 struct napi_struct napi;
238 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
239 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
240 u8 rxr_count; /* Rx ring count assigned to this vector */
241 u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3
JB		 242 u8 tx_itr;
243 u8 rx_itr;
021230d4 244 u32 eitr;
b25ebfd2 245 cpumask_var_t affinity_mask;
021230d4
AV		 246};
247
9a799d71 248/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 249 * And yes, it's the same math going both ways. The lowest value
250 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 251 */
252#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 253 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 254#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
255
256#define IXGBE_DESC_UNUSED(R) \
257 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
258 (R)->next_to_clean - (R)->next_to_use - 1)
259
260#define IXGBE_RX_DESC_ADV(R, i) \
31f05a2d 261 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
9a799d71 262#define IXGBE_TX_DESC_ADV(R, i) \
31f05a2d 263 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
9a799d71 264#define IXGBE_TX_CTXTDESC_ADV(R, i) \
31f05a2d 265 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 266
267#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 268#ifdef IXGBE_FCOE
269/* Use 3K as the baby jumbo frame size for FCoE */
270#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
271#endif /* IXGBE_FCOE */
9a799d71 272
021230d4
AV		 273#define OTHER_VECTOR 1
274#define NON_Q_VECTORS (OTHER_VECTOR)
275
e8e26350
PW		 276#define MAX_MSIX_VECTORS_82599 64
277#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 278#define MAX_MSIX_VECTORS_82598 18
279#define MAX_MSIX_Q_VECTORS_82598 16
280
e8e26350
PW		 281#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
282#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 283
021230d4 284#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 285#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
286
9a799d71
AK		 287/* board specific private data structure */
288struct ixgbe_adapter {
289 struct timer_list watchdog_timer;
290 struct vlan_group *vlgrp;
291 u16 bd_number;
9a799d71 292 struct work_struct reset_task;
7a921c93 293 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
e8e26350 294 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
2f90b865
AD		 295 struct ixgbe_dcb_config dcb_cfg;
296 struct ixgbe_dcb_config temp_dcb_cfg;
297 u8 dcb_set_bitmap;
264857b8 298 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 299
f494e8fa 300 /* Interrupt Throttle Rate */
f7554a2b
NS		 301 u32 rx_itr_setting;
302 u32 tx_itr_setting;
f494e8fa
AV		 303 u16 eitr_low;
304 u16 eitr_high;
305
9a799d71 306 /* TX */
4a0b9ca0 307 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 308 int num_tx_queues;
9a799d71
AK		 309 u32 tx_timeout_count;
310 bool detect_tx_hung;
311
7ca3bc58
JB		 312 u64 restart_queue;
313 u64 lsc_int;
314
9a799d71 315 /* RX */
4a0b9ca0 316 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 317 int num_rx_queues;
7f870475
GR		 318 int num_rx_pools; /* == num_rx_queues in 82598 */
319 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 320 u64 hw_csum_rx_error;
e8e26350 321 u64 hw_rx_no_dma_resources;
9a799d71 322 u64 non_eop_descs;
021230d4 323 int num_msix_vectors;
eb7f139c 324 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 325 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 326 struct msix_entry *msix_entries;
327
9a799d71
AK		 328 u32 alloc_rx_page_failed;
329 u32 alloc_rx_buff_failed;
330
021230d4
AV		 331 /* Some features need tri-state capability,
332 * thus the additional *_CAPABLE flags.
333 */
9a799d71 334 u32 flags;
96b0e0f6
JB		 335#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
336#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
337#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
338#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
339#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
340#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
341#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
342#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
343#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
344#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
345#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
346#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
347#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350 348#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6
JB		 349#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
350#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
351#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
352#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e 353#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6 354#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
10eec955
JF		 355#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
356#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
357#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
358#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
359#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
360#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
361#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
362#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
96b0e0f6 363
df647b5c
PWJ		 364 u32 flags2;
365#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
366#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
119fc60a 367#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
96b0e0f6
JB		 368/* default to trying for four seconds */
369#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 370
371 /* OS defined structs */
372 struct net_device *netdev;
373 struct pci_dev *pdev;
9a799d71 374
da4dd0f7
PWJ		 375 u32 test_icr;
376 struct ixgbe_ring test_tx_ring;
377 struct ixgbe_ring test_rx_ring;
378
9a799d71
AK		 379 /* structs defined in ixgbe_hw.h */
380 struct ixgbe_hw hw;
381 u16 msg_enable;
382 struct ixgbe_hw_stats stats;
021230d4
AV		 383
384 /* Interrupt Throttle Rate */
f7554a2b
NS		 385 u32 rx_eitr_param;
386 u32 tx_eitr_param;
9a799d71
AK		 387
388 unsigned long state;
389 u64 tx_busy;
30efa5a3
JB		 390 unsigned int tx_ring_count;
391 unsigned int rx_ring_count;
cf8280ee
JB		 392
393 u32 link_speed;
394 bool link_up;
395 unsigned long link_check_timeout;
396
397 struct work_struct watchdog_task;
c4900be0
DS		 398 struct work_struct sfp_task;
399 struct timer_list sfp_timer;
e8e26350
PW		 400 struct work_struct multispeed_fiber_task;
401 struct work_struct sfp_config_module_task;
c4cf55e5
PWJ		 402 u32 fdir_pballoc;
403 u32 atr_sample_rate;
404 spinlock_t fdir_perfect_lock;
405 struct work_struct fdir_reinit_task;
d0ed8937
YZ		 406#ifdef IXGBE_FCOE
407 struct ixgbe_fcoe fcoe;
408#endif /* IXGBE_FCOE */
94b982b2
MC		 409 u64 rsc_total_count;
410 u64 rsc_total_flush;
e8e26350 411 u32 wol;
34b0368c 412 u16 eeprom_version;
7f870475 413
1a6c14a2 414 int node;
119fc60a
MC		 415 struct work_struct check_overtemp_task;
416 u32 interrupt_event;
1a6c14a2 417
7f870475
GR		 418 /* SR-IOV */
419 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
420 unsigned int num_vfs;
421 struct vf_data_storage *vfinfo;
9a799d71
AK		 422};
423
424enum ixbge_state_t {
425 __IXGBE_TESTING,
426 __IXGBE_RESETTING,
c4900be0 427 __IXGBE_DOWN,
c4cf55e5 428 __IXGBE_FDIR_INIT_DONE,
c4900be0 429 __IXGBE_SFP_MODULE_NOT_FOUND
9a799d71
AK		 430};
431
432enum ixgbe_boards {
3957d63d 433 board_82598,
e8e26350 434 board_82599,
9a799d71
AK		 435};
436
3957d63d 437extern struct ixgbe_info ixgbe_82598_info;
e8e26350 438extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51 439#ifdef CONFIG_IXGBE_DCB
32953543 440extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865
AD		 441extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
442 struct ixgbe_dcb_config *dst_dcb_cfg,
443 int tc_max);
444#endif
9a799d71
AK		 445
446extern char ixgbe_driver_name[];
9c8eb720 447extern const char ixgbe_driver_version[];
9a799d71
AK		 448
449extern int ixgbe_up(struct ixgbe_adapter *adapter);
450extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 451extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 452extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 453extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240
PW		 454extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
455extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
456extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
457extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
84418e3b
AD		 458extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
459extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
b4617240 460extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 461extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 462extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b
AD		 463extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
464 struct net_device *,
465 struct ixgbe_adapter *,
466 struct ixgbe_ring *);
467extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *,
468 struct ixgbe_tx_buffer *);
469extern void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
470 struct ixgbe_ring *rx_ring,
471 int cleaned_count);
fe49f04a
AD		 472extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
473extern int ethtool_ioctl(struct ifreq *ifr);
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PWJ		 474extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
475extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
476extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
477extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
478 struct ixgbe_atr_input *input,
479 u8 queue);
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PW		 480extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
481 struct ixgbe_atr_input *input,
482 struct ixgbe_atr_input_masks *input_masks,
483 u16 soft_id, u8 queue);
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PWJ		 484extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
485 u16 vlan_id);
486extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
487 u32 src_addr);
488extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
489 u32 dst_addr);
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PWJ		 490extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
491 u16 src_port);
492extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
493 u16 dst_port);
494extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
495 u16 flex_byte);
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PWJ		 496extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
497 u8 l4type);
7f870475 498extern void ixgbe_set_rx_mode(struct net_device *netdev);
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YZ		 499#ifdef IXGBE_FCOE
500extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
501extern int ixgbe_fso(struct ixgbe_adapter *adapter,
502 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
503 u32 tx_flags, u8 *hdr_len);
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YZ		 504extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
505extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
506 union ixgbe_adv_rx_desc *rx_desc,
507 struct sk_buff *skb);
508extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
509 struct scatterlist *sgl, unsigned int sgc);
510extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
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YZ		 511extern int ixgbe_fcoe_enable(struct net_device *netdev);
512extern int ixgbe_fcoe_disable(struct net_device *netdev);
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YZ		 513#ifdef CONFIG_IXGBE_DCB
514extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
515extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
516#endif /* CONFIG_IXGBE_DCB */
61a1fa10 517extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
eacd73f7 518#endif /* IXGBE_FCOE */
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AK		 519
520#endif /* _IXGBE_H_ */
Linux 6.x block layer and io_uring tree(s)