ixgbe: select FCoE Tx queue in ndo_select_queue
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe.h
CommitLineData
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1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
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5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
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23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
6fabd715 34#include <linux/aer.h>
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35
36#include "ixgbe_type.h"
37#include "ixgbe_common.h"
2f90b865 38#include "ixgbe_dcb.h"
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39#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
40#define IXGBE_FCOE
41#include "ixgbe_fcoe.h"
42#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 43#ifdef CONFIG_IXGBE_DCA
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44#include <linux/dca.h>
45#endif
9a799d71 46
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47#define PFX "ixgbe: "
48#define DPRINTK(nlevel, klevel, fmt, args...) \
49 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
50 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
b39d66a8 51 __func__ , ## args)))
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52
53/* TX/RX descriptor defines */
54#define IXGBE_DEFAULT_TXD 1024
55#define IXGBE_MAX_TXD 4096
56#define IXGBE_MIN_TXD 64
57
58#define IXGBE_DEFAULT_RXD 1024
59#define IXGBE_MAX_RXD 4096
60#define IXGBE_MIN_RXD 64
61
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62/* flow control */
63#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93 64#define IXGBE_MIN_FCRTL 0x40
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65#define IXGBE_MAX_FCRTL 0x7FF80
66#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93 67#define IXGBE_MIN_FCRTH 0x600
9a799d71 68#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 69#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
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70#define IXGBE_MIN_FCPAUSE 0
71#define IXGBE_MAX_FCPAUSE 0xFFFF
72
73/* Supported Rx Buffer Sizes */
74#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
75#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
76#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
77#define IXGBE_RXBUFFER_2048 2048
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78#define IXGBE_RXBUFFER_4096 4096
79#define IXGBE_RXBUFFER_8192 8192
32344a39 80#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
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81
82#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
83
84#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
85
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86/* How many Rx Buffers do we bundle into one write to the hardware ? */
87#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
88
89#define IXGBE_TX_FLAGS_CSUM (u32)(1)
90#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
91#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
92#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
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93#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
94#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 95#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 96#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
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97#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
98
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99#define IXGBE_MAX_RSC_INT_RATE 162760
100
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101/* wrapper around a pointer to a socket buffer,
102 * so a DMA handle can be stored along with the buffer */
103struct ixgbe_tx_buffer {
104 struct sk_buff *skb;
105 dma_addr_t dma;
106 unsigned long time_stamp;
107 u16 length;
108 u16 next_to_watch;
e5a43549 109 u16 mapped_as_page;
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110};
111
112struct ixgbe_rx_buffer {
113 struct sk_buff *skb;
114 dma_addr_t dma;
115 struct page *page;
116 dma_addr_t page_dma;
762f4c57 117 unsigned int page_offset;
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118};
119
120struct ixgbe_queue_stats {
121 u64 packets;
122 u64 bytes;
123};
124
125struct ixgbe_ring {
9a799d71 126 void *desc; /* descriptor ring memory */
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127 union {
128 struct ixgbe_tx_buffer *tx_buffer_info;
129 struct ixgbe_rx_buffer *rx_buffer_info;
130 };
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131 u8 atr_sample_rate;
132 u8 atr_count;
133 u16 count; /* amount of descriptors */
134 u16 rx_buf_len;
135 u16 next_to_use;
136 u16 next_to_clean;
137
138 u8 queue_index; /* needed for multiqueue queue management */
9a799d71 139
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140#define IXGBE_RING_RX_PS_ENABLED (u8)(1)
141 u8 flags; /* per ring feature flags */
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142 u16 head;
143 u16 tail;
144
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145 unsigned int total_bytes;
146 unsigned int total_packets;
9a799d71 147
5dd2d332 148#ifdef CONFIG_IXGBE_DCA
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149 /* cpu for tx queue */
150 int cpu;
151#endif
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152
153 u16 work_limit; /* max work per interrupt */
154 u16 reg_idx; /* holds the special value that gets
155 * the hardware register offset
156 * associated with this ring, which is
157 * different for DCB and RSS modes
158 */
159
9a799d71 160 struct ixgbe_queue_stats stats;
c4cf55e5 161 unsigned long reinit_state;
ae540af1 162 u64 rsc_count; /* stat for coalesced packets */
94b982b2 163 u64 rsc_flush; /* stats for flushed packets */
9a799d71 164
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165 unsigned int size; /* length in bytes */
166 dma_addr_t dma; /* phys. address of descriptor ring */
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167};
168
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169enum ixgbe_ring_f_enum {
170 RING_F_NONE = 0,
171 RING_F_DCB,
172 RING_F_VMDQ,
173 RING_F_RSS,
c4cf55e5 174 RING_F_FDIR,
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175#ifdef IXGBE_FCOE
176 RING_F_FCOE,
177#endif /* IXGBE_FCOE */
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178
179 RING_F_ARRAY_SIZE /* must be last in enum set */
180};
181
2f90b865 182#define IXGBE_MAX_DCB_INDICES 8
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183#define IXGBE_MAX_RSS_INDICES 16
184#define IXGBE_MAX_VMDQ_INDICES 16
c4cf55e5 185#define IXGBE_MAX_FDIR_INDICES 64
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186#ifdef IXGBE_FCOE
187#define IXGBE_MAX_FCOE_INDICES 8
188#endif /* IXGBE_FCOE */
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189struct ixgbe_ring_feature {
190 int indices;
191 int mask;
192};
193
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194#define MAX_RX_QUEUES 128
195#define MAX_TX_QUEUES 128
021230d4 196
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197#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
198 ? 8 : 1)
199#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
200
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201/* MAX_MSIX_Q_VECTORS of these are allocated,
202 * but we only use one per queue-specific vector.
203 */
204struct ixgbe_q_vector {
205 struct ixgbe_adapter *adapter;
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206 unsigned int v_idx; /* index of q_vector within array, also used for
207 * finding the bit in EICR and friends that
208 * represents the vector for this ring */
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209 struct napi_struct napi;
210 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
211 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
212 u8 rxr_count; /* Rx ring count assigned to this vector */
213 u8 txr_count; /* Tx ring count assigned to this vector */
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214 u8 tx_itr;
215 u8 rx_itr;
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216 u32 eitr;
217};
218
9a799d71 219/* Helper macros to switch between ints/sec and what the register uses.
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220 * And yes, it's the same math going both ways. The lowest value
221 * supported by all of the ixgbe hardware is 8.
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222 */
223#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 224 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
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225#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
226
227#define IXGBE_DESC_UNUSED(R) \
228 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
229 (R)->next_to_clean - (R)->next_to_use - 1)
230
231#define IXGBE_RX_DESC_ADV(R, i) \
232 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
233#define IXGBE_TX_DESC_ADV(R, i) \
234 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
235#define IXGBE_TX_CTXTDESC_ADV(R, i) \
236 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
237
238#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
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239#ifdef IXGBE_FCOE
240/* Use 3K as the baby jumbo frame size for FCoE */
241#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
242#endif /* IXGBE_FCOE */
9a799d71 243
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244#define OTHER_VECTOR 1
245#define NON_Q_VECTORS (OTHER_VECTOR)
246
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247#define MAX_MSIX_VECTORS_82599 64
248#define MAX_MSIX_Q_VECTORS_82599 64
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249#define MAX_MSIX_VECTORS_82598 18
250#define MAX_MSIX_Q_VECTORS_82598 16
251
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252#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
253#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 254
021230d4 255#define MIN_MSIX_Q_VECTORS 2
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256#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
257
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258/* board specific private data structure */
259struct ixgbe_adapter {
260 struct timer_list watchdog_timer;
261 struct vlan_group *vlgrp;
262 u16 bd_number;
9a799d71 263 struct work_struct reset_task;
7a921c93 264 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
e8e26350 265 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
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266 struct ixgbe_dcb_config dcb_cfg;
267 struct ixgbe_dcb_config temp_dcb_cfg;
268 u8 dcb_set_bitmap;
264857b8 269 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 270
f494e8fa 271 /* Interrupt Throttle Rate */
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272 u32 rx_itr_setting;
273 u32 tx_itr_setting;
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274 u16 eitr_low;
275 u16 eitr_high;
276
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277 /* TX */
278 struct ixgbe_ring *tx_ring; /* One per active queue */
30efa5a3 279 int num_tx_queues;
9a799d71 280 u64 restart_queue;
30efa5a3 281 u64 hw_csum_tx_good;
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282 u64 lsc_int;
283 u64 hw_tso_ctxt;
284 u64 hw_tso6_ctxt;
285 u32 tx_timeout_count;
286 bool detect_tx_hung;
287
288 /* RX */
289 struct ixgbe_ring *rx_ring; /* One per active queue */
30efa5a3 290 int num_rx_queues;
9a799d71 291 u64 hw_csum_rx_error;
e8e26350 292 u64 hw_rx_no_dma_resources;
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293 u64 hw_csum_rx_good;
294 u64 non_eop_descs;
021230d4 295 int num_msix_vectors;
eb7f139c 296 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 297 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
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298 struct msix_entry *msix_entries;
299
300 u64 rx_hdr_split;
301 u32 alloc_rx_page_failed;
302 u32 alloc_rx_buff_failed;
303
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304 /* Some features need tri-state capability,
305 * thus the additional *_CAPABLE flags.
306 */
9a799d71 307 u32 flags;
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308#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
309#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
310#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
311#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
312#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
313#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
314#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
315#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
316#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
317#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
318#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
319#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
320#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350 321#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
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322#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
323#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
324#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
325#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e 326#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
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327#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
328#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
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329#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 24)
330#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25)
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331#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 26)
332#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 27)
0d551589 333#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 28)
eacd73f7 334#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29)
96b0e0f6 335
df647b5c
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336 u32 flags2;
337#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
338#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
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339/* default to trying for four seconds */
340#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
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341
342 /* OS defined structs */
343 struct net_device *netdev;
344 struct pci_dev *pdev;
9a799d71 345
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PWJ
346 u32 test_icr;
347 struct ixgbe_ring test_tx_ring;
348 struct ixgbe_ring test_rx_ring;
349
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350 /* structs defined in ixgbe_hw.h */
351 struct ixgbe_hw hw;
352 u16 msg_enable;
353 struct ixgbe_hw_stats stats;
021230d4
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354
355 /* Interrupt Throttle Rate */
f7554a2b
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356 u32 rx_eitr_param;
357 u32 tx_eitr_param;
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358
359 unsigned long state;
360 u64 tx_busy;
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361 unsigned int tx_ring_count;
362 unsigned int rx_ring_count;
cf8280ee
JB
363
364 u32 link_speed;
365 bool link_up;
366 unsigned long link_check_timeout;
367
368 struct work_struct watchdog_task;
c4900be0
DS
369 struct work_struct sfp_task;
370 struct timer_list sfp_timer;
e8e26350
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371 struct work_struct multispeed_fiber_task;
372 struct work_struct sfp_config_module_task;
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373 u32 fdir_pballoc;
374 u32 atr_sample_rate;
375 spinlock_t fdir_perfect_lock;
376 struct work_struct fdir_reinit_task;
d0ed8937
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377#ifdef IXGBE_FCOE
378 struct ixgbe_fcoe fcoe;
379#endif /* IXGBE_FCOE */
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380 u64 rsc_total_count;
381 u64 rsc_total_flush;
e8e26350 382 u32 wol;
34b0368c 383 u16 eeprom_version;
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384};
385
386enum ixbge_state_t {
387 __IXGBE_TESTING,
388 __IXGBE_RESETTING,
c4900be0 389 __IXGBE_DOWN,
c4cf55e5 390 __IXGBE_FDIR_INIT_DONE,
c4900be0 391 __IXGBE_SFP_MODULE_NOT_FOUND
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392};
393
394enum ixgbe_boards {
3957d63d 395 board_82598,
e8e26350 396 board_82599,
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397};
398
3957d63d 399extern struct ixgbe_info ixgbe_82598_info;
e8e26350 400extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51 401#ifdef CONFIG_IXGBE_DCB
32953543 402extern const struct dcbnl_rtnl_ops dcbnl_ops;
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AD
403extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
404 struct ixgbe_dcb_config *dst_dcb_cfg,
405 int tc_max);
406#endif
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407
408extern char ixgbe_driver_name[];
9c8eb720 409extern const char ixgbe_driver_version[];
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410
411extern int ixgbe_up(struct ixgbe_adapter *adapter);
412extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 413extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 414extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 415extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240
PW
416extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
417extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
418extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
419extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
420extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 421extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 422extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
fe49f04a
AD
423extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
424extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772
PWJ
425extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
426extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
427extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
428extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
429 struct ixgbe_atr_input *input,
430 u8 queue);
ffff4772
PWJ
431extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
432 u16 vlan_id);
433extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
434 u32 src_addr);
435extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
436 u32 dst_addr);
ffff4772
PWJ
437extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
438 u16 src_port);
439extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
440 u16 dst_port);
441extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
442 u16 flex_byte);
ffff4772
PWJ
443extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
444 u8 l4type);
eacd73f7
YZ
445#ifdef IXGBE_FCOE
446extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
447extern int ixgbe_fso(struct ixgbe_adapter *adapter,
448 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
449 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ
450extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
451extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
452 union ixgbe_adv_rx_desc *rx_desc,
453 struct sk_buff *skb);
454extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
455 struct scatterlist *sgl, unsigned int sgc);
456extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ
457extern int ixgbe_fcoe_enable(struct net_device *netdev);
458extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ
459#ifdef CONFIG_IXGBE_DCB
460extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
461extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
462#endif /* CONFIG_IXGBE_DCB */
61a1fa10 463extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
eacd73f7 464#endif /* IXGBE_FCOE */
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465
466#endif /* _IXGBE_H_ */