[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBE_H_
#define _IXGBE_H_

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/aer.h>

#include "ixgbe_type.h"
#include "ixgbe_common.h"
#include "ixgbe_dcb.h"
#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
#define IXGBE_FCOE
#include "ixgbe_fcoe.h"
#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
#ifdef CONFIG_IXGBE_DCA
#include <linux/dca.h>
#endif

#define PFX "ixgbe: "
#define DPRINTK(nlevel, klevel, fmt, args...) \
	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
		__func__ , ## args)))

/* TX/RX descriptor defines */
#define IXGBE_DEFAULT_TXD		   1024
#define IXGBE_MAX_TXD			   4096
#define IXGBE_MIN_TXD			     64

#define IXGBE_DEFAULT_RXD		   1024
#define IXGBE_MAX_RXD			   4096
#define IXGBE_MIN_RXD			     64

/* flow control */
#define IXGBE_DEFAULT_FCRTL		0x10000
#define IXGBE_MIN_FCRTL			   0x40
#define IXGBE_MAX_FCRTL			0x7FF80
#define IXGBE_DEFAULT_FCRTH		0x20000
#define IXGBE_MIN_FCRTH			  0x600
#define IXGBE_MAX_FCRTH			0x7FFF0
#define IXGBE_DEFAULT_FCPAUSE		 0xFFFF
#define IXGBE_MIN_FCPAUSE		      0
#define IXGBE_MAX_FCPAUSE		 0xFFFF

/* Supported Rx Buffer Sizes */
#define IXGBE_RXBUFFER_64    64     /* Used for packet split */
#define IXGBE_RXBUFFER_128   128    /* Used for packet split */
#define IXGBE_RXBUFFER_256   256    /* Used for packet split */
#define IXGBE_RXBUFFER_2048  2048
#define IXGBE_MAX_RXBUFFER   16384  /* largest size for a single descriptor */

#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256

#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IXGBE_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define IXGBE_TX_FLAGS_CSUM		(u32)(1)
#define IXGBE_TX_FLAGS_VLAN		(u32)(1 << 1)
#define IXGBE_TX_FLAGS_TSO		(u32)(1 << 2)
#define IXGBE_TX_FLAGS_IPV4		(u32)(1 << 3)
#define IXGBE_TX_FLAGS_FCOE		(u32)(1 << 4)
#define IXGBE_TX_FLAGS_FSO		(u32)(1 << 5)
#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
#define IXGBE_TX_FLAGS_VLAN_SHIFT	16

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct ixgbe_tx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	unsigned long time_stamp;
	u16 length;
	u16 next_to_watch;
};

struct ixgbe_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
	unsigned int page_offset;
};

struct ixgbe_queue_stats {
	u64 packets;
	u64 bytes;
};

struct ixgbe_ring {
	void *desc;			/* descriptor ring memory */
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */
	unsigned int count;		/* amount of descriptors */
	unsigned int next_to_use;
	unsigned int next_to_clean;

	int queue_index; /* needed for multiqueue queue management */
	union {
		struct ixgbe_tx_buffer *tx_buffer_info;
		struct ixgbe_rx_buffer *rx_buffer_info;
	};

	u16 head;
	u16 tail;

	unsigned int total_bytes;
	unsigned int total_packets;

	u16 reg_idx; /* holds the special value that gets the hardware register
		      * offset associated with this ring, which is different
		      * for DCB and RSS modes */

#ifdef CONFIG_IXGBE_DCA
	/* cpu for tx queue */
	int cpu;
#endif
	struct ixgbe_queue_stats stats;
	u64 v_idx; /* maps directly to the index for this ring in the hardware
	            * vector array, can also be used for finding the bit in EICR
	            * and friends that represents the vector for this ring */


	u16 work_limit;                /* max work per interrupt */
	u16 rx_buf_len;
	u64 rsc_count;                 /* stat for coalesced packets */
};

enum ixgbe_ring_f_enum {
	RING_F_NONE = 0,
	RING_F_DCB,
	RING_F_VMDQ,
	RING_F_RSS,

	RING_F_ARRAY_SIZE      /* must be last in enum set */
};

#define IXGBE_MAX_DCB_INDICES   8
#define IXGBE_MAX_RSS_INDICES  16
#define IXGBE_MAX_VMDQ_INDICES 16
struct ixgbe_ring_feature {
	int indices;
	int mask;
};

#define MAX_RX_QUEUES 128
#define MAX_TX_QUEUES 128

#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
                              ? 8 : 1)
#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS

/* MAX_MSIX_Q_VECTORS of these are allocated,
 * but we only use one per queue-specific vector.
 */
struct ixgbe_q_vector {
	struct ixgbe_adapter *adapter;
	struct napi_struct napi;
	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	u8 rxr_count;     /* Rx ring count assigned to this vector */
	u8 txr_count;     /* Tx ring count assigned to this vector */
	u8 tx_itr;
	u8 rx_itr;
	u32 eitr;
	u32 v_idx;        /* vector index in list */
};

/* Helper macros to switch between ints/sec and what the register uses.
 * And yes, it's the same math going both ways.  The lowest value
 * supported by all of the ixgbe hardware is 8.
 */
#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

#define IXGBE_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define IXGBE_RX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
#define IXGBE_TX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
#define IXGBE_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))

#define IXGBE_MAX_JUMBO_FRAME_SIZE        16128

#define OTHER_VECTOR 1
#define NON_Q_VECTORS (OTHER_VECTOR)

#define MAX_MSIX_VECTORS_82599 64
#define MAX_MSIX_Q_VECTORS_82599 64
#define MAX_MSIX_VECTORS_82598 18
#define MAX_MSIX_Q_VECTORS_82598 16

#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599

#define MIN_MSIX_Q_VECTORS 2
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)

/* board specific private data structure */
struct ixgbe_adapter {
	struct timer_list watchdog_timer;
	struct vlan_group *vlgrp;
	u16 bd_number;
	struct work_struct reset_task;
	struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
	char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
	struct ixgbe_dcb_config dcb_cfg;
	struct ixgbe_dcb_config temp_dcb_cfg;
	u8 dcb_set_bitmap;

	/* Interrupt Throttle Rate */
	u32 itr_setting;
	u16 eitr_low;
	u16 eitr_high;

	/* TX */
	struct ixgbe_ring *tx_ring;	/* One per active queue */
	int num_tx_queues;
	u64 restart_queue;
	u64 hw_csum_tx_good;
	u64 lsc_int;
	u64 hw_tso_ctxt;
	u64 hw_tso6_ctxt;
	u32 tx_timeout_count;
	bool detect_tx_hung;

	/* RX */
	struct ixgbe_ring *rx_ring;	/* One per active queue */
	int num_rx_queues;
	u64 hw_csum_rx_error;
	u64 hw_rx_no_dma_resources;
	u64 hw_csum_rx_good;
	u64 non_eop_descs;
	int num_msix_vectors;
	int max_msix_q_vectors;         /* true count of q_vectors for device */
	struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
	struct msix_entry *msix_entries;

	u64 rx_hdr_split;
	u32 alloc_rx_page_failed;
	u32 alloc_rx_buff_failed;

	/* Some features need tri-state capability,
	 * thus the additional *_CAPABLE flags.
	 */
	u32 flags;
#define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
#define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
#define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
#define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
#define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
#define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
#define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
#define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
#define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
#define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
#define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
#define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
#define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
#define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
#define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
#define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
#define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
#define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
#define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
#define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
#define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)
#define IXGBE_FLAG_IN_SFP_LINK_TASK             (u32)(1 << 24)
#define IXGBE_FLAG_IN_SFP_MOD_TASK              (u32)(1 << 25)
#define IXGBE_FLAG_RSC_CAPABLE                  (u32)(1 << 26)
#define IXGBE_FLAG_RSC_ENABLED                  (u32)(1 << 27)
#define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 29)

/* default to trying for four seconds */
#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct net_device_stats net_stats;

	/* structs defined in ixgbe_hw.h */
	struct ixgbe_hw hw;
	u16 msg_enable;
	struct ixgbe_hw_stats stats;

	/* Interrupt Throttle Rate */
	u32 eitr_param;

	unsigned long state;
	u64 tx_busy;
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;

	u32 link_speed;
	bool link_up;
	unsigned long link_check_timeout;

	struct work_struct watchdog_task;
	struct work_struct sfp_task;
	struct timer_list sfp_timer;
	struct work_struct multispeed_fiber_task;
	struct work_struct sfp_config_module_task;
#ifdef IXGBE_FCOE
	struct ixgbe_fcoe fcoe;
#endif /* IXGBE_FCOE */
	u64 rsc_count;
	u32 wol;
	u16 eeprom_version;
};

enum ixbge_state_t {
	__IXGBE_TESTING,
	__IXGBE_RESETTING,
	__IXGBE_DOWN,
	__IXGBE_SFP_MODULE_NOT_FOUND
};

enum ixgbe_boards {
	board_82598,
	board_82599,
};

extern struct ixgbe_info ixgbe_82598_info;
extern struct ixgbe_info ixgbe_82599_info;
#ifdef CONFIG_IXGBE_DCB
extern struct dcbnl_rtnl_ops dcbnl_ops;
extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
                              struct ixgbe_dcb_config *dst_dcb_cfg,
                              int tc_max);
#endif

extern char ixgbe_driver_name[];
extern const char ixgbe_driver_version[];

extern int ixgbe_up(struct ixgbe_adapter *adapter);
extern void ixgbe_down(struct ixgbe_adapter *adapter);
extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
extern void ixgbe_reset(struct ixgbe_adapter *adapter);
extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
extern void ixgbe_write_eitr(struct ixgbe_adapter *, int, u32);
#ifdef IXGBE_FCOE
extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
extern int ixgbe_fso(struct ixgbe_adapter *adapter,
                     struct ixgbe_ring *tx_ring, struct sk_buff *skb,
                     u32 tx_flags, u8 *hdr_len);
extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
                          union ixgbe_adv_rx_desc *rx_desc,
                          struct sk_buff *skb);
extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
                              struct scatterlist *sgl, unsigned int sgc);
extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
#endif /* IXGBE_FCOE */

#endif /* _IXGBE_H_ */
Commit	Line	Data
9a799d71 AK	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
3efac5a0	4	Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
9a799d71 AK	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _IXGBE_H_
	29	#define _IXGBE_H_
	30
	31	#include <linux/types.h>
	32	#include <linux/pci.h>
	33	#include <linux/netdevice.h>
6fabd715	34	#include <linux/aer.h>
9a799d71 AK	35
	36	#include "ixgbe_type.h"
	37	#include "ixgbe_common.h"
2f90b865	38	#include "ixgbe_dcb.h"
eacd73f7 YZ	39	#if defined(CONFIG_FCOE) \|\| defined(CONFIG_FCOE_MODULE)
	40	#define IXGBE_FCOE
	41	#include "ixgbe_fcoe.h"
	42	#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332	43	#ifdef CONFIG_IXGBE_DCA
bd0362dd JC	44	#include <linux/dca.h>
bd0362dd JC	45	#endif
9a799d71	46
9a799d71 AK	47	#define PFX "ixgbe: "
	48	#define DPRINTK(nlevel, klevel, fmt, args...) \
	49	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	50	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
b39d66a8	51	__func__ , ## args)))
9a799d71 AK	52
	53	/* TX/RX descriptor defines */
	54	#define IXGBE_DEFAULT_TXD 1024
	55	#define IXGBE_MAX_TXD 4096
	56	#define IXGBE_MIN_TXD 64
	57
	58	#define IXGBE_DEFAULT_RXD 1024
	59	#define IXGBE_MAX_RXD 4096
	60	#define IXGBE_MIN_RXD 64
	61
9a799d71 AK	62	/* flow control */
9a799d71 AK	63	#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93	64	#define IXGBE_MIN_FCRTL 0x40
9a799d71 AK	65	#define IXGBE_MAX_FCRTL 0x7FF80
9a799d71 AK	66	#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93	67	#define IXGBE_MIN_FCRTH 0x600
9a799d71	68	#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93	69	#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71 AK	70	#define IXGBE_MIN_FCPAUSE 0
	71	#define IXGBE_MAX_FCPAUSE 0xFFFF
	72
	73	/* Supported Rx Buffer Sizes */
	74	#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
	75	#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
	76	#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
	77	#define IXGBE_RXBUFFER_2048 2048
32344a39	78	#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 AK	79
	80	#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
	81
	82	#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
	83
9a799d71 AK	84	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	85	#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	86
	87	#define IXGBE_TX_FLAGS_CSUM (u32)(1)
	88	#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
	89	#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
	90	#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7 YZ	91	#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
eacd73f7 YZ	92	#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71	93	#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865	94	#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71 AK	95	#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
	96
	97	/* wrapper around a pointer to a socket buffer,
	98	* so a DMA handle can be stored along with the buffer */
	99	struct ixgbe_tx_buffer {
	100	struct sk_buff *skb;
	101	dma_addr_t dma;
	102	unsigned long time_stamp;
	103	u16 length;
	104	u16 next_to_watch;
	105	};
	106
	107	struct ixgbe_rx_buffer {
	108	struct sk_buff *skb;
	109	dma_addr_t dma;
	110	struct page *page;
	111	dma_addr_t page_dma;
762f4c57	112	unsigned int page_offset;
9a799d71 AK	113	};
	114
	115	struct ixgbe_queue_stats {
	116	u64 packets;
	117	u64 bytes;
	118	};
	119
	120	struct ixgbe_ring {
9a799d71 AK	121	void desc; / descriptor ring memory */
	122	dma_addr_t dma; /* phys. address of descriptor ring */
	123	unsigned int size; /* length in bytes */
	124	unsigned int count; /* amount of descriptors */
	125	unsigned int next_to_use;
	126	unsigned int next_to_clean;
	127
021230d4	128	int queue_index; /* needed for multiqueue queue management */
9a799d71 AK	129	union {
	130	struct ixgbe_tx_buffer *tx_buffer_info;
	131	struct ixgbe_rx_buffer *rx_buffer_info;
	132	};
	133
	134	u16 head;
	135	u16 tail;
	136
f494e8fa AV	137	unsigned int total_bytes;
f494e8fa AV	138	unsigned int total_packets;
9a799d71	139
021230d4 AV	140	u16 reg_idx; /* holds the special value that gets the hardware register
021230d4 AV	141	* offset associated with this ring, which is different
2f90b865	142	* for DCB and RSS modes */
bd0362dd	143
5dd2d332	144	#ifdef CONFIG_IXGBE_DCA
bd0362dd JC	145	/* cpu for tx queue */
	146	int cpu;
	147	#endif
9a799d71	148	struct ixgbe_queue_stats stats;
e8e26350 PW	149	u64 v_idx; /* maps directly to the index for this ring in the hardware
	150	* vector array, can also be used for finding the bit in EICR
	151	* and friends that represents the vector for this ring */
9a799d71	152
9a799d71	153
9a799d71	154	u16 work_limit; /* max work per interrupt */
7c6e0a43	155	u16 rx_buf_len;
f8212f97	156	u64 rsc_count; /* stat for coalesced packets */
9a799d71 AK	157	};
9a799d71 AK	158
c7e4358a SN	159	enum ixgbe_ring_f_enum {
	160	RING_F_NONE = 0,
	161	RING_F_DCB,
	162	RING_F_VMDQ,
	163	RING_F_RSS,
	164
	165	RING_F_ARRAY_SIZE /* must be last in enum set */
	166	};
	167
2f90b865	168	#define IXGBE_MAX_DCB_INDICES 8
021230d4 AV	169	#define IXGBE_MAX_RSS_INDICES 16
	170	#define IXGBE_MAX_VMDQ_INDICES 16
	171	struct ixgbe_ring_feature {
	172	int indices;
	173	int mask;
	174	};
	175
e8e26350 PW	176	#define MAX_RX_QUEUES 128
e8e26350 PW	177	#define MAX_TX_QUEUES 128
021230d4	178
2f90b865 AD	179	#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
	180	? 8 : 1)
	181	#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
	182
021230d4 AV	183	/* MAX_MSIX_Q_VECTORS of these are allocated,
	184	* but we only use one per queue-specific vector.
	185	*/
	186	struct ixgbe_q_vector {
	187	struct ixgbe_adapter *adapter;
	188	struct napi_struct napi;
	189	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	190	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	191	u8 rxr_count; /* Rx ring count assigned to this vector */
	192	u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3 JB	193	u8 tx_itr;
30efa5a3 JB	194	u8 rx_itr;
021230d4	195	u32 eitr;
7a921c93	196	u32 v_idx; /* vector index in list */
021230d4 AV	197	};
021230d4 AV	198
9a799d71	199	/* Helper macros to switch between ints/sec and what the register uses.
509ee935 JB	200	* And yes, it's the same math going both ways. The lowest value
509ee935 JB	201	* supported by all of the ixgbe hardware is 8.
9a799d71 AK	202	*/
9a799d71 AK	203	#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935	204	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71 AK	205	#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
	206
	207	#define IXGBE_DESC_UNUSED(R) \
	208	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	209	(R)->next_to_clean - (R)->next_to_use - 1)
	210
	211	#define IXGBE_RX_DESC_ADV(R, i) \
	212	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
	213	#define IXGBE_TX_DESC_ADV(R, i) \
	214	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
	215	#define IXGBE_TX_CTXTDESC_ADV(R, i) \
	216	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
	217
	218	#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
	219
021230d4 AV	220	#define OTHER_VECTOR 1
	221	#define NON_Q_VECTORS (OTHER_VECTOR)
	222
e8e26350 PW	223	#define MAX_MSIX_VECTORS_82599 64
e8e26350 PW	224	#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c PWJ	225	#define MAX_MSIX_VECTORS_82598 18
	226	#define MAX_MSIX_Q_VECTORS_82598 16
	227
e8e26350 PW	228	#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
e8e26350 PW	229	#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c	230
021230d4	231	#define MIN_MSIX_Q_VECTORS 2
021230d4 AV	232	#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
021230d4 AV	233
9a799d71 AK	234	/* board specific private data structure */
	235	struct ixgbe_adapter {
	236	struct timer_list watchdog_timer;
	237	struct vlan_group *vlgrp;
	238	u16 bd_number;
9a799d71	239	struct work_struct reset_task;
7a921c93	240	struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
e8e26350	241	char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
2f90b865 AD	242	struct ixgbe_dcb_config dcb_cfg;
	243	struct ixgbe_dcb_config temp_dcb_cfg;
	244	u8 dcb_set_bitmap;
9a799d71	245
f494e8fa AV	246	/* Interrupt Throttle Rate */
	247	u32 itr_setting;
	248	u16 eitr_low;
	249	u16 eitr_high;
	250
9a799d71 AK	251	/* TX */
9a799d71 AK	252	struct ixgbe_ring tx_ring; / One per active queue */
30efa5a3	253	int num_tx_queues;
9a799d71	254	u64 restart_queue;
30efa5a3	255	u64 hw_csum_tx_good;
9a799d71 AK	256	u64 lsc_int;
	257	u64 hw_tso_ctxt;
	258	u64 hw_tso6_ctxt;
	259	u32 tx_timeout_count;
	260	bool detect_tx_hung;
	261
	262	/* RX */
	263	struct ixgbe_ring rx_ring; / One per active queue */
30efa5a3	264	int num_rx_queues;
9a799d71	265	u64 hw_csum_rx_error;
e8e26350	266	u64 hw_rx_no_dma_resources;
9a799d71 AK	267	u64 hw_csum_rx_good;
9a799d71 AK	268	u64 non_eop_descs;
021230d4	269	int num_msix_vectors;
eb7f139c	270	int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a	271	struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71 AK	272	struct msix_entry *msix_entries;
	273
	274	u64 rx_hdr_split;
	275	u32 alloc_rx_page_failed;
	276	u32 alloc_rx_buff_failed;
	277
021230d4 AV	278	/* Some features need tri-state capability,
	279	* thus the additional *_CAPABLE flags.
	280	*/
9a799d71	281	u32 flags;
96b0e0f6 JB	282	#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
	283	#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
	284	#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
	285	#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
	286	#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
	287	#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
	288	#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
	289	#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
	290	#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
	291	#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
	292	#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
	293	#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
	294	#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350	295	#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6 JB	296	#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
	297	#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
	298	#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
	299	#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e	300	#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6 JB	301	#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
96b0e0f6 JB	302	#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
e8e26350 PW	303	#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 24)
e8e26350 PW	304	#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25)
f8212f97 AD	305	#define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 26)
f8212f97 AD	306	#define IXGBE_FLAG_RSC_ENABLED (u32)(1 << 27)
eacd73f7	307	#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29)
96b0e0f6 JB	308
	309	/* default to trying for four seconds */
	310	#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71 AK	311
	312	/* OS defined structs */
	313	struct net_device *netdev;
	314	struct pci_dev *pdev;
	315	struct net_device_stats net_stats;
	316
	317	/* structs defined in ixgbe_hw.h */
	318	struct ixgbe_hw hw;
	319	u16 msg_enable;
	320	struct ixgbe_hw_stats stats;
021230d4 AV	321
021230d4 AV	322	/* Interrupt Throttle Rate */
30efa5a3	323	u32 eitr_param;
9a799d71 AK	324
	325	unsigned long state;
	326	u64 tx_busy;
30efa5a3 JB	327	unsigned int tx_ring_count;
30efa5a3 JB	328	unsigned int rx_ring_count;
cf8280ee JB	329
	330	u32 link_speed;
	331	bool link_up;
	332	unsigned long link_check_timeout;
	333
	334	struct work_struct watchdog_task;
c4900be0 DS	335	struct work_struct sfp_task;
c4900be0 DS	336	struct timer_list sfp_timer;
e8e26350 PW	337	struct work_struct multispeed_fiber_task;
e8e26350 PW	338	struct work_struct sfp_config_module_task;
d0ed8937 YZ	339	#ifdef IXGBE_FCOE
	340	struct ixgbe_fcoe fcoe;
	341	#endif /* IXGBE_FCOE */
f8212f97	342	u64 rsc_count;
e8e26350	343	u32 wol;
34b0368c	344	u16 eeprom_version;
9a799d71 AK	345	};
	346
	347	enum ixbge_state_t {
	348	__IXGBE_TESTING,
	349	__IXGBE_RESETTING,
c4900be0 DS	350	__IXGBE_DOWN,
c4900be0 DS	351	__IXGBE_SFP_MODULE_NOT_FOUND
9a799d71 AK	352	};
	353
	354	enum ixgbe_boards {
3957d63d	355	board_82598,
e8e26350	356	board_82599,
9a799d71 AK	357	};
9a799d71 AK	358
3957d63d	359	extern struct ixgbe_info ixgbe_82598_info;
e8e26350	360	extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51	361	#ifdef CONFIG_IXGBE_DCB
2f90b865 AD	362	extern struct dcbnl_rtnl_ops dcbnl_ops;
	363	extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
	364	struct ixgbe_dcb_config *dst_dcb_cfg,
	365	int tc_max);
	366	#endif
9a799d71 AK	367
9a799d71 AK	368	extern char ixgbe_driver_name[];
9c8eb720	369	extern const char ixgbe_driver_version[];
9a799d71 AK	370
	371	extern int ixgbe_up(struct ixgbe_adapter *adapter);
	372	extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882	373	extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71	374	extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71	375	extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240 PW	376	extern int ixgbe_setup_rx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	377	extern int ixgbe_setup_tx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	378	extern void ixgbe_free_rx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	379	extern void ixgbe_free_tx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	380	extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865	381	extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93	382	extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
509ee935	383	extern void ixgbe_write_eitr(struct ixgbe_adapter *, int, u32);
eacd73f7 YZ	384	#ifdef IXGBE_FCOE
	385	extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
	386	extern int ixgbe_fso(struct ixgbe_adapter *adapter,
	387	struct ixgbe_ring tx_ring, struct sk_buff skb,
	388	u32 tx_flags, u8 *hdr_len);
332d4a7d YZ	389	extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
	390	extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
	391	union ixgbe_adv_rx_desc *rx_desc,
	392	struct sk_buff *skb);
	393	extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
	394	struct scatterlist *sgl, unsigned int sgc);
	395	extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
eacd73f7	396	#endif /* IXGBE_FCOE */
9a799d71 AK	397
9a799d71 AK	398	#endif /* _IXGBE_H_ */