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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-block.git] / drivers / net / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
6fabd715 34#include <linux/aer.h>
9a799d71
AK		 35
36#include "ixgbe_type.h"
37#include "ixgbe_common.h"
2f90b865 38#include "ixgbe_dcb.h"
eacd73f7
YZ		 39#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
40#define IXGBE_FCOE
41#include "ixgbe_fcoe.h"
42#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 43#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 44#include <linux/dca.h>
45#endif
9a799d71 46
9a799d71
AK		 47#define PFX "ixgbe: "
48#define DPRINTK(nlevel, klevel, fmt, args...) \
49 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
50 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
b39d66a8 51 __func__ , ## args)))
9a799d71
AK		 52
53/* TX/RX descriptor defines */
54#define IXGBE_DEFAULT_TXD 1024
55#define IXGBE_MAX_TXD 4096
56#define IXGBE_MIN_TXD 64
57
58#define IXGBE_DEFAULT_RXD 1024
59#define IXGBE_MAX_RXD 4096
60#define IXGBE_MIN_RXD 64
61
9a799d71
AK		 62/* flow control */
63#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93 64#define IXGBE_MIN_FCRTL 0x40
9a799d71
AK		 65#define IXGBE_MAX_FCRTL 0x7FF80
66#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93 67#define IXGBE_MIN_FCRTH 0x600
9a799d71 68#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 69#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 70#define IXGBE_MIN_FCPAUSE 0
71#define IXGBE_MAX_FCPAUSE 0xFFFF
72
73/* Supported Rx Buffer Sizes */
74#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
75#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
76#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
77#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 78#define IXGBE_RXBUFFER_4096 4096
79#define IXGBE_RXBUFFER_8192 8192
32344a39 80#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71
AK		 81
82#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
83
84#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
85
9a799d71
AK		 86/* How many Rx Buffers do we bundle into one write to the hardware ? */
87#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
88
89#define IXGBE_TX_FLAGS_CSUM (u32)(1)
90#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
91#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
92#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7
YZ		 93#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
94#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 95#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 96#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71
AK		 97#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
98
0a924578
PWJ		 99#define IXGBE_MAX_RSC_INT_RATE 162760
100
9a799d71
AK		 101/* wrapper around a pointer to a socket buffer,
102 * so a DMA handle can be stored along with the buffer */
103struct ixgbe_tx_buffer {
104 struct sk_buff *skb;
105 dma_addr_t dma;
106 unsigned long time_stamp;
107 u16 length;
108 u16 next_to_watch;
109};
110
111struct ixgbe_rx_buffer {
112 struct sk_buff *skb;
113 dma_addr_t dma;
114 struct page *page;
115 dma_addr_t page_dma;
762f4c57 116 unsigned int page_offset;
9a799d71
AK		 117};
118
119struct ixgbe_queue_stats {
120 u64 packets;
121 u64 bytes;
122};
123
124struct ixgbe_ring {
9a799d71 125 void *desc; /* descriptor ring memory */
9a799d71
AK		 126 union {
127 struct ixgbe_tx_buffer *tx_buffer_info;
128 struct ixgbe_rx_buffer *rx_buffer_info;
129 };
ae540af1
JB		 130 u8 atr_sample_rate;
131 u8 atr_count;
132 u16 count; /* amount of descriptors */
133 u16 rx_buf_len;
134 u16 next_to_use;
135 u16 next_to_clean;
136
137 u8 queue_index; /* needed for multiqueue queue management */
9a799d71 138
6e455b89
YZ		 139#define IXGBE_RING_RX_PS_ENABLED (u8)(1)
140 u8 flags; /* per ring feature flags */
9a799d71
AK		 141 u16 head;
142 u16 tail;
143
f494e8fa
AV		 144 unsigned int total_bytes;
145 unsigned int total_packets;
9a799d71 146
5dd2d332 147#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 148 /* cpu for tx queue */
149 int cpu;
150#endif
ae540af1
JB		 151
152 u16 work_limit; /* max work per interrupt */
153 u16 reg_idx; /* holds the special value that gets
154 * the hardware register offset
155 * associated with this ring, which is
156 * different for DCB and RSS modes
157 */
158
9a799d71 159 struct ixgbe_queue_stats stats;
c4cf55e5 160 unsigned long reinit_state;
ae540af1 161 u64 rsc_count; /* stat for coalesced packets */
9a799d71 162
ae540af1
JB		 163 unsigned int size; /* length in bytes */
164 dma_addr_t dma; /* phys. address of descriptor ring */
9a799d71
AK		 165};
166
c7e4358a
SN		 167enum ixgbe_ring_f_enum {
168 RING_F_NONE = 0,
169 RING_F_DCB,
170 RING_F_VMDQ,
171 RING_F_RSS,
c4cf55e5 172 RING_F_FDIR,
0331a832
YZ		 173#ifdef IXGBE_FCOE
174 RING_F_FCOE,
175#endif /* IXGBE_FCOE */
c7e4358a
SN		 176
177 RING_F_ARRAY_SIZE /* must be last in enum set */
178};
179
2f90b865 180#define IXGBE_MAX_DCB_INDICES 8
021230d4
AV		 181#define IXGBE_MAX_RSS_INDICES 16
182#define IXGBE_MAX_VMDQ_INDICES 16
c4cf55e5 183#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 184#ifdef IXGBE_FCOE
185#define IXGBE_MAX_FCOE_INDICES 8
186#endif /* IXGBE_FCOE */
021230d4
AV		 187struct ixgbe_ring_feature {
188 int indices;
189 int mask;
190};
191
e8e26350
PW		 192#define MAX_RX_QUEUES 128
193#define MAX_TX_QUEUES 128
021230d4 194
2f90b865
AD		 195#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
196 ? 8 : 1)
197#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
198
021230d4
AV		 199/* MAX_MSIX_Q_VECTORS of these are allocated,
200 * but we only use one per queue-specific vector.
201 */
202struct ixgbe_q_vector {
203 struct ixgbe_adapter *adapter;
fe49f04a
AD		 204 unsigned int v_idx; /* index of q_vector within array, also used for
205 * finding the bit in EICR and friends that
206 * represents the vector for this ring */
021230d4
AV		 207 struct napi_struct napi;
208 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
209 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
210 u8 rxr_count; /* Rx ring count assigned to this vector */
211 u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3
JB		 212 u8 tx_itr;
213 u8 rx_itr;
021230d4
AV		 214 u32 eitr;
215};
216
9a799d71 217/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 218 * And yes, it's the same math going both ways. The lowest value
219 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 220 */
221#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 222 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 223#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
224
225#define IXGBE_DESC_UNUSED(R) \
226 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
227 (R)->next_to_clean - (R)->next_to_use - 1)
228
229#define IXGBE_RX_DESC_ADV(R, i) \
230 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
231#define IXGBE_TX_DESC_ADV(R, i) \
232 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
233#define IXGBE_TX_CTXTDESC_ADV(R, i) \
234 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
235
236#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 237#ifdef IXGBE_FCOE
238/* Use 3K as the baby jumbo frame size for FCoE */
239#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
240#endif /* IXGBE_FCOE */
9a799d71 241
021230d4
AV		 242#define OTHER_VECTOR 1
243#define NON_Q_VECTORS (OTHER_VECTOR)
244
e8e26350
PW		 245#define MAX_MSIX_VECTORS_82599 64
246#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 247#define MAX_MSIX_VECTORS_82598 18
248#define MAX_MSIX_Q_VECTORS_82598 16
249
e8e26350
PW		 250#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
251#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 252
021230d4 253#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 254#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
255
9a799d71
AK		 256/* board specific private data structure */
257struct ixgbe_adapter {
258 struct timer_list watchdog_timer;
259 struct vlan_group *vlgrp;
260 u16 bd_number;
9a799d71 261 struct work_struct reset_task;
7a921c93 262 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
e8e26350 263 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
2f90b865
AD		 264 struct ixgbe_dcb_config dcb_cfg;
265 struct ixgbe_dcb_config temp_dcb_cfg;
266 u8 dcb_set_bitmap;
264857b8 267 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 268
f494e8fa 269 /* Interrupt Throttle Rate */
f7554a2b
NS		 270 u32 rx_itr_setting;
271 u32 tx_itr_setting;
f494e8fa
AV		 272 u16 eitr_low;
273 u16 eitr_high;
274
9a799d71
AK		 275 /* TX */
276 struct ixgbe_ring *tx_ring; /* One per active queue */
30efa5a3 277 int num_tx_queues;
9a799d71 278 u64 restart_queue;
30efa5a3 279 u64 hw_csum_tx_good;
9a799d71
AK		 280 u64 lsc_int;
281 u64 hw_tso_ctxt;
282 u64 hw_tso6_ctxt;
283 u32 tx_timeout_count;
284 bool detect_tx_hung;
285
286 /* RX */
287 struct ixgbe_ring *rx_ring; /* One per active queue */
30efa5a3 288 int num_rx_queues;
9a799d71 289 u64 hw_csum_rx_error;
e8e26350 290 u64 hw_rx_no_dma_resources;
9a799d71
AK		 291 u64 hw_csum_rx_good;
292 u64 non_eop_descs;
021230d4 293 int num_msix_vectors;
eb7f139c 294 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 295 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 296 struct msix_entry *msix_entries;
297
298 u64 rx_hdr_split;
299 u32 alloc_rx_page_failed;
300 u32 alloc_rx_buff_failed;
301
021230d4
AV		 302 /* Some features need tri-state capability,
303 * thus the additional *_CAPABLE flags.
304 */
9a799d71 305 u32 flags;
96b0e0f6
JB		 306#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
307#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
308#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
309#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
310#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
311#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
312#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
313#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
314#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
315#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
316#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
317#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
318#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350 319#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6
JB		 320#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
321#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
322#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
323#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e 324#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6
JB		 325#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
326#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
e8e26350
PW		 327#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 24)
328#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25)
c4cf55e5
PWJ		 329#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 26)
330#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 27)
0d551589 331#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 28)
eacd73f7 332#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29)
96b0e0f6 333
df647b5c
PWJ		 334 u32 flags2;
335#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
336#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
96b0e0f6
JB		 337/* default to trying for four seconds */
338#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 339
340 /* OS defined structs */
341 struct net_device *netdev;
342 struct pci_dev *pdev;
343 struct net_device_stats net_stats;
344
da4dd0f7
PWJ		 345 u32 test_icr;
346 struct ixgbe_ring test_tx_ring;
347 struct ixgbe_ring test_rx_ring;
348
9a799d71
AK		 349 /* structs defined in ixgbe_hw.h */
350 struct ixgbe_hw hw;
351 u16 msg_enable;
352 struct ixgbe_hw_stats stats;
021230d4
AV		 353
354 /* Interrupt Throttle Rate */
f7554a2b
NS		 355 u32 rx_eitr_param;
356 u32 tx_eitr_param;
9a799d71
AK		 357
358 unsigned long state;
359 u64 tx_busy;
30efa5a3
JB		 360 unsigned int tx_ring_count;
361 unsigned int rx_ring_count;
cf8280ee
JB		 362
363 u32 link_speed;
364 bool link_up;
365 unsigned long link_check_timeout;
366
367 struct work_struct watchdog_task;
c4900be0
DS		 368 struct work_struct sfp_task;
369 struct timer_list sfp_timer;
e8e26350
PW		 370 struct work_struct multispeed_fiber_task;
371 struct work_struct sfp_config_module_task;
c4cf55e5
PWJ		 372 u32 fdir_pballoc;
373 u32 atr_sample_rate;
374 spinlock_t fdir_perfect_lock;
375 struct work_struct fdir_reinit_task;
d0ed8937
YZ		 376#ifdef IXGBE_FCOE
377 struct ixgbe_fcoe fcoe;
378#endif /* IXGBE_FCOE */
f8212f97 379 u64 rsc_count;
e8e26350 380 u32 wol;
34b0368c 381 u16 eeprom_version;
9a799d71
AK		 382};
383
384enum ixbge_state_t {
385 __IXGBE_TESTING,
386 __IXGBE_RESETTING,
c4900be0 387 __IXGBE_DOWN,
c4cf55e5 388 __IXGBE_FDIR_INIT_DONE,
c4900be0 389 __IXGBE_SFP_MODULE_NOT_FOUND
9a799d71
AK		 390};
391
392enum ixgbe_boards {
3957d63d 393 board_82598,
e8e26350 394 board_82599,
9a799d71
AK		 395};
396
3957d63d 397extern struct ixgbe_info ixgbe_82598_info;
e8e26350 398extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51 399#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 400extern struct dcbnl_rtnl_ops dcbnl_ops;
401extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
402 struct ixgbe_dcb_config *dst_dcb_cfg,
403 int tc_max);
404#endif
9a799d71
AK		 405
406extern char ixgbe_driver_name[];
9c8eb720 407extern const char ixgbe_driver_version[];
9a799d71
AK		 408
409extern int ixgbe_up(struct ixgbe_adapter *adapter);
410extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 411extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 412extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 413extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240
PW		 414extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
415extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
416extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
417extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
418extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 419extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 420extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
fe49f04a
AD		 421extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
422extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772
PWJ		 423extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
424extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
425extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
426extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
427 struct ixgbe_atr_input *input,
428 u8 queue);
ffff4772
PWJ		 429extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
430 u16 vlan_id);
431extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
432 u32 src_addr);
433extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
434 u32 dst_addr);
ffff4772
PWJ		 435extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
436 u16 src_port);
437extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
438 u16 dst_port);
439extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
440 u16 flex_byte);
ffff4772
PWJ		 441extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
442 u8 l4type);
eacd73f7
YZ		 443#ifdef IXGBE_FCOE
444extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
445extern int ixgbe_fso(struct ixgbe_adapter *adapter,
446 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
447 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ		 448extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
449extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
450 union ixgbe_adv_rx_desc *rx_desc,
451 struct sk_buff *skb);
452extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
453 struct scatterlist *sgl, unsigned int sgc);
454extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ		 455extern int ixgbe_fcoe_enable(struct net_device *netdev);
456extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 457#ifdef CONFIG_IXGBE_DCB
458extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
459extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
460#endif /* CONFIG_IXGBE_DCB */
eacd73f7 461#endif /* IXGBE_FCOE */
9a799d71
AK		 462
463#endif /* _IXGBE_H_ */
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