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Merge branch 'for-2.6.28' of git://linux-nfs.org/~bfields/linux
[linux-2.6-block.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
421e02f0 45#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 46#include <linux/dca.h>
47#endif
9d5c8243
AK		 48#include "igb.h"
49
0024fd00 50#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 51char igb_driver_name[] = "igb";
52char igb_driver_version[] = DRV_VERSION;
53static const char igb_driver_string[] =
54 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 55static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 56
9d5c8243
AK		 57static const struct e1000_info *igb_info_tbl[] = {
58 [board_82575] = &e1000_82575_info,
59};
60
61static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
68 /* required last entry */
69 {0, }
70};
71
72MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
73
74void igb_reset(struct igb_adapter *);
75static int igb_setup_all_tx_resources(struct igb_adapter *);
76static int igb_setup_all_rx_resources(struct igb_adapter *);
77static void igb_free_all_tx_resources(struct igb_adapter *);
78static void igb_free_all_rx_resources(struct igb_adapter *);
3b644cf6
MW		 79static void igb_free_tx_resources(struct igb_ring *);
80static void igb_free_rx_resources(struct igb_ring *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
109static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 110#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 111static void igb_update_rx_dca(struct igb_ring *);
112static void igb_update_tx_dca(struct igb_ring *);
113static void igb_setup_dca(struct igb_adapter *);
421e02f0 114#endif /* CONFIG_IGB_DCA */
3b644cf6 115static bool igb_clean_tx_irq(struct igb_ring *);
661086df 116static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
d3352520
AD		 119#ifdef CONFIG_IGB_LRO
120static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
121#endif
9d5c8243
AK		 122static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
123static void igb_tx_timeout(struct net_device *);
124static void igb_reset_task(struct work_struct *);
125static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
126static void igb_vlan_rx_add_vid(struct net_device *, u16);
127static void igb_vlan_rx_kill_vid(struct net_device *, u16);
128static void igb_restore_vlan(struct igb_adapter *);
129
130static int igb_suspend(struct pci_dev *, pm_message_t);
131#ifdef CONFIG_PM
132static int igb_resume(struct pci_dev *);
133#endif
134static void igb_shutdown(struct pci_dev *);
421e02f0 135#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 136static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
137static struct notifier_block dca_notifier = {
138 .notifier_call = igb_notify_dca,
139 .next = NULL,
140 .priority = 0
141};
142#endif
9d5c8243
AK		 143
144#ifdef CONFIG_NET_POLL_CONTROLLER
145/* for netdump / net console */
146static void igb_netpoll(struct net_device *);
147#endif
148
149static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
150 pci_channel_state_t);
151static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
152static void igb_io_resume(struct pci_dev *);
153
154static struct pci_error_handlers igb_err_handler = {
155 .error_detected = igb_io_error_detected,
156 .slot_reset = igb_io_slot_reset,
157 .resume = igb_io_resume,
158};
159
160
161static struct pci_driver igb_driver = {
162 .name = igb_driver_name,
163 .id_table = igb_pci_tbl,
164 .probe = igb_probe,
165 .remove = __devexit_p(igb_remove),
166#ifdef CONFIG_PM
167 /* Power Managment Hooks */
168 .suspend = igb_suspend,
169 .resume = igb_resume,
170#endif
171 .shutdown = igb_shutdown,
172 .err_handler = &igb_err_handler
173};
174
7dfc16fa
AD		 175static int global_quad_port_a; /* global quad port a indication */
176
9d5c8243
AK		 177MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
178MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
179MODULE_LICENSE("GPL");
180MODULE_VERSION(DRV_VERSION);
181
182#ifdef DEBUG
183/**
184 * igb_get_hw_dev_name - return device name string
185 * used by hardware layer to print debugging information
186 **/
187char *igb_get_hw_dev_name(struct e1000_hw *hw)
188{
189 struct igb_adapter *adapter = hw->back;
190 return adapter->netdev->name;
191}
192#endif
193
194/**
195 * igb_init_module - Driver Registration Routine
196 *
197 * igb_init_module is the first routine called when the driver is
198 * loaded. All it does is register with the PCI subsystem.
199 **/
200static int __init igb_init_module(void)
201{
202 int ret;
203 printk(KERN_INFO "%s - version %s\n",
204 igb_driver_string, igb_driver_version);
205
206 printk(KERN_INFO "%s\n", igb_copyright);
207
7dfc16fa
AD		 208 global_quad_port_a = 0;
209
9d5c8243 210 ret = pci_register_driver(&igb_driver);
421e02f0 211#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 212 dca_register_notify(&dca_notifier);
213#endif
9d5c8243
AK		 214 return ret;
215}
216
217module_init(igb_init_module);
218
219/**
220 * igb_exit_module - Driver Exit Cleanup Routine
221 *
222 * igb_exit_module is called just before the driver is removed
223 * from memory.
224 **/
225static void __exit igb_exit_module(void)
226{
421e02f0 227#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 228 dca_unregister_notify(&dca_notifier);
229#endif
9d5c8243
AK		 230 pci_unregister_driver(&igb_driver);
231}
232
233module_exit(igb_exit_module);
234
235/**
236 * igb_alloc_queues - Allocate memory for all rings
237 * @adapter: board private structure to initialize
238 *
239 * We allocate one ring per queue at run-time since we don't know the
240 * number of queues at compile-time.
241 **/
242static int igb_alloc_queues(struct igb_adapter *adapter)
243{
244 int i;
245
246 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
247 sizeof(struct igb_ring), GFP_KERNEL);
248 if (!adapter->tx_ring)
249 return -ENOMEM;
250
251 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
252 sizeof(struct igb_ring), GFP_KERNEL);
253 if (!adapter->rx_ring) {
254 kfree(adapter->tx_ring);
255 return -ENOMEM;
256 }
257
6eb5a7f1
AD		 258 adapter->rx_ring->buddy = adapter->tx_ring;
259
661086df
PWJ		 260 for (i = 0; i < adapter->num_tx_queues; i++) {
261 struct igb_ring *ring = &(adapter->tx_ring[i]);
262 ring->adapter = adapter;
263 ring->queue_index = i;
264 }
9d5c8243
AK		 265 for (i = 0; i < adapter->num_rx_queues; i++) {
266 struct igb_ring *ring = &(adapter->rx_ring[i]);
267 ring->adapter = adapter;
844290e5 268 ring->queue_index = i;
9d5c8243
AK		 269 ring->itr_register = E1000_ITR;
270
844290e5 271 /* set a default napi handler for each rx_ring */
661086df 272 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 273 }
274 return 0;
275}
276
a88f10ec
AD		 277static void igb_free_queues(struct igb_adapter *adapter)
278{
279 int i;
280
281 for (i = 0; i < adapter->num_rx_queues; i++)
282 netif_napi_del(&adapter->rx_ring[i].napi);
283
284 kfree(adapter->tx_ring);
285 kfree(adapter->rx_ring);
286}
287
9d5c8243
AK		 288#define IGB_N0_QUEUE -1
289static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
290 int tx_queue, int msix_vector)
291{
292 u32 msixbm = 0;
293 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 294 u32 ivar, index;
295
296 switch (hw->mac.type) {
297 case e1000_82575:
9d5c8243
AK		 298 /* The 82575 assigns vectors using a bitmask, which matches the
299 bitmask for the EICR/EIMS/EIMC registers. To assign one
300 or more queues to a vector, we write the appropriate bits
301 into the MSIXBM register for that vector. */
302 if (rx_queue > IGB_N0_QUEUE) {
303 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
304 adapter->rx_ring[rx_queue].eims_value = msixbm;
305 }
306 if (tx_queue > IGB_N0_QUEUE) {
307 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
308 adapter->tx_ring[tx_queue].eims_value =
309 E1000_EICR_TX_QUEUE0 << tx_queue;
310 }
311 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 312 break;
313 case e1000_82576:
106ef2fe 314 /* The 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 315 Each queue has a single entry in the table to which we write
316 a vector number along with a "valid" bit. Sadly, the layout
317 of the table is somewhat counterintuitive. */
318 if (rx_queue > IGB_N0_QUEUE) {
319 index = (rx_queue & 0x7);
320 ivar = array_rd32(E1000_IVAR0, index);
321 if (rx_queue < 8) {
322 /* vector goes into low byte of register */
323 ivar = ivar & 0xFFFFFF00;
324 ivar |= msix_vector | E1000_IVAR_VALID;
325 } else {
326 /* vector goes into third byte of register */
327 ivar = ivar & 0xFF00FFFF;
328 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
329 }
330 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
331 array_wr32(E1000_IVAR0, index, ivar);
332 }
333 if (tx_queue > IGB_N0_QUEUE) {
334 index = (tx_queue & 0x7);
335 ivar = array_rd32(E1000_IVAR0, index);
336 if (tx_queue < 8) {
337 /* vector goes into second byte of register */
338 ivar = ivar & 0xFFFF00FF;
339 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
340 } else {
341 /* vector goes into high byte of register */
342 ivar = ivar & 0x00FFFFFF;
343 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
344 }
345 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
346 array_wr32(E1000_IVAR0, index, ivar);
347 }
348 break;
349 default:
350 BUG();
351 break;
352 }
9d5c8243
AK		 353}
354
355/**
356 * igb_configure_msix - Configure MSI-X hardware
357 *
358 * igb_configure_msix sets up the hardware to properly
359 * generate MSI-X interrupts.
360 **/
361static void igb_configure_msix(struct igb_adapter *adapter)
362{
363 u32 tmp;
364 int i, vector = 0;
365 struct e1000_hw *hw = &adapter->hw;
366
367 adapter->eims_enable_mask = 0;
2d064c06
AD		 368 if (hw->mac.type == e1000_82576)
369 /* Turn on MSI-X capability first, or our settings
370 * won't stick. And it will take days to debug. */
371 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
372 E1000_GPIE_PBA | E1000_GPIE_EIAME |
373 E1000_GPIE_NSICR);
9d5c8243
AK		 374
375 for (i = 0; i < adapter->num_tx_queues; i++) {
376 struct igb_ring *tx_ring = &adapter->tx_ring[i];
377 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
378 adapter->eims_enable_mask |= tx_ring->eims_value;
379 if (tx_ring->itr_val)
6eb5a7f1 380 writel(tx_ring->itr_val,
9d5c8243
AK		 381 hw->hw_addr + tx_ring->itr_register);
382 else
383 writel(1, hw->hw_addr + tx_ring->itr_register);
384 }
385
386 for (i = 0; i < adapter->num_rx_queues; i++) {
387 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 388 rx_ring->buddy = NULL;
9d5c8243
AK		 389 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
390 adapter->eims_enable_mask |= rx_ring->eims_value;
391 if (rx_ring->itr_val)
6eb5a7f1 392 writel(rx_ring->itr_val,
9d5c8243
AK		 393 hw->hw_addr + rx_ring->itr_register);
394 else
395 writel(1, hw->hw_addr + rx_ring->itr_register);
396 }
397
398
399 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 400 switch (hw->mac.type) {
401 case e1000_82575:
9d5c8243
AK		 402 array_wr32(E1000_MSIXBM(0), vector++,
403 E1000_EIMS_OTHER);
404
9d5c8243
AK		 405 tmp = rd32(E1000_CTRL_EXT);
406 /* enable MSI-X PBA support*/
407 tmp |= E1000_CTRL_EXT_PBA_CLR;
408
409 /* Auto-Mask interrupts upon ICR read. */
410 tmp |= E1000_CTRL_EXT_EIAME;
411 tmp |= E1000_CTRL_EXT_IRCA;
412
413 wr32(E1000_CTRL_EXT, tmp);
414 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 415 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 416
2d064c06
AD		 417 break;
418
419 case e1000_82576:
420 tmp = (vector++ | E1000_IVAR_VALID) << 8;
421 wr32(E1000_IVAR_MISC, tmp);
422
423 adapter->eims_enable_mask = (1 << (vector)) - 1;
424 adapter->eims_other = 1 << (vector - 1);
425 break;
426 default:
427 /* do nothing, since nothing else supports MSI-X */
428 break;
429 } /* switch (hw->mac.type) */
9d5c8243
AK		 430 wrfl();
431}
432
433/**
434 * igb_request_msix - Initialize MSI-X interrupts
435 *
436 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
437 * kernel.
438 **/
439static int igb_request_msix(struct igb_adapter *adapter)
440{
441 struct net_device *netdev = adapter->netdev;
442 int i, err = 0, vector = 0;
443
444 vector = 0;
445
446 for (i = 0; i < adapter->num_tx_queues; i++) {
447 struct igb_ring *ring = &(adapter->tx_ring[i]);
448 sprintf(ring->name, "%s-tx%d", netdev->name, i);
449 err = request_irq(adapter->msix_entries[vector].vector,
450 &igb_msix_tx, 0, ring->name,
451 &(adapter->tx_ring[i]));
452 if (err)
453 goto out;
454 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 455 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 456 vector++;
457 }
458 for (i = 0; i < adapter->num_rx_queues; i++) {
459 struct igb_ring *ring = &(adapter->rx_ring[i]);
460 if (strlen(netdev->name) < (IFNAMSIZ - 5))
461 sprintf(ring->name, "%s-rx%d", netdev->name, i);
462 else
463 memcpy(ring->name, netdev->name, IFNAMSIZ);
464 err = request_irq(adapter->msix_entries[vector].vector,
465 &igb_msix_rx, 0, ring->name,
466 &(adapter->rx_ring[i]));
467 if (err)
468 goto out;
469 ring->itr_register = E1000_EITR(0) + (vector << 2);
470 ring->itr_val = adapter->itr;
844290e5
PW		 471 /* overwrite the poll routine for MSIX, we've already done
472 * netif_napi_add */
473 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 474 vector++;
475 }
476
477 err = request_irq(adapter->msix_entries[vector].vector,
478 &igb_msix_other, 0, netdev->name, netdev);
479 if (err)
480 goto out;
481
9d5c8243
AK		 482 igb_configure_msix(adapter);
483 return 0;
484out:
485 return err;
486}
487
488static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
489{
490 if (adapter->msix_entries) {
491 pci_disable_msix(adapter->pdev);
492 kfree(adapter->msix_entries);
493 adapter->msix_entries = NULL;
7dfc16fa 494 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 495 pci_disable_msi(adapter->pdev);
496 return;
497}
498
499
500/**
501 * igb_set_interrupt_capability - set MSI or MSI-X if supported
502 *
503 * Attempt to configure interrupts using the best available
504 * capabilities of the hardware and kernel.
505 **/
506static void igb_set_interrupt_capability(struct igb_adapter *adapter)
507{
508 int err;
509 int numvecs, i;
510
511 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
512 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
513 GFP_KERNEL);
514 if (!adapter->msix_entries)
515 goto msi_only;
516
517 for (i = 0; i < numvecs; i++)
518 adapter->msix_entries[i].entry = i;
519
520 err = pci_enable_msix(adapter->pdev,
521 adapter->msix_entries,
522 numvecs);
523 if (err == 0)
34a20e89 524 goto out;
9d5c8243
AK		 525
526 igb_reset_interrupt_capability(adapter);
527
528 /* If we can't do MSI-X, try MSI */
529msi_only:
530 adapter->num_rx_queues = 1;
661086df 531 adapter->num_tx_queues = 1;
9d5c8243 532 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 533 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 534out:
661086df 535 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 536 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 537 return;
538}
539
540/**
541 * igb_request_irq - initialize interrupts
542 *
543 * Attempts to configure interrupts using the best available
544 * capabilities of the hardware and kernel.
545 **/
546static int igb_request_irq(struct igb_adapter *adapter)
547{
548 struct net_device *netdev = adapter->netdev;
549 struct e1000_hw *hw = &adapter->hw;
550 int err = 0;
551
552 if (adapter->msix_entries) {
553 err = igb_request_msix(adapter);
844290e5 554 if (!err)
9d5c8243 555 goto request_done;
9d5c8243
AK		 556 /* fall back to MSI */
557 igb_reset_interrupt_capability(adapter);
558 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 559 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 560 igb_free_all_tx_resources(adapter);
561 igb_free_all_rx_resources(adapter);
562 adapter->num_rx_queues = 1;
563 igb_alloc_queues(adapter);
844290e5 564 } else {
2d064c06
AD		 565 switch (hw->mac.type) {
566 case e1000_82575:
567 wr32(E1000_MSIXBM(0),
568 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
569 break;
570 case e1000_82576:
571 wr32(E1000_IVAR0, E1000_IVAR_VALID);
572 break;
573 default:
574 break;
575 }
9d5c8243 576 }
844290e5 577
7dfc16fa 578 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 579 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
580 netdev->name, netdev);
581 if (!err)
582 goto request_done;
583 /* fall back to legacy interrupts */
584 igb_reset_interrupt_capability(adapter);
7dfc16fa 585 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 586 }
587
588 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
589 netdev->name, netdev);
590
6cb5e577 591 if (err)
9d5c8243
AK		 592 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
593 err);
9d5c8243
AK		 594
595request_done:
596 return err;
597}
598
599static void igb_free_irq(struct igb_adapter *adapter)
600{
601 struct net_device *netdev = adapter->netdev;
602
603 if (adapter->msix_entries) {
604 int vector = 0, i;
605
606 for (i = 0; i < adapter->num_tx_queues; i++)
607 free_irq(adapter->msix_entries[vector++].vector,
608 &(adapter->tx_ring[i]));
609 for (i = 0; i < adapter->num_rx_queues; i++)
610 free_irq(adapter->msix_entries[vector++].vector,
611 &(adapter->rx_ring[i]));
612
613 free_irq(adapter->msix_entries[vector++].vector, netdev);
614 return;
615 }
616
617 free_irq(adapter->pdev->irq, netdev);
618}
619
620/**
621 * igb_irq_disable - Mask off interrupt generation on the NIC
622 * @adapter: board private structure
623 **/
624static void igb_irq_disable(struct igb_adapter *adapter)
625{
626 struct e1000_hw *hw = &adapter->hw;
627
628 if (adapter->msix_entries) {
844290e5 629 wr32(E1000_EIAM, 0);
9d5c8243
AK		 630 wr32(E1000_EIMC, ~0);
631 wr32(E1000_EIAC, 0);
632 }
844290e5
PW		 633
634 wr32(E1000_IAM, 0);
9d5c8243
AK		 635 wr32(E1000_IMC, ~0);
636 wrfl();
637 synchronize_irq(adapter->pdev->irq);
638}
639
640/**
641 * igb_irq_enable - Enable default interrupt generation settings
642 * @adapter: board private structure
643 **/
644static void igb_irq_enable(struct igb_adapter *adapter)
645{
646 struct e1000_hw *hw = &adapter->hw;
647
648 if (adapter->msix_entries) {
844290e5
PW		 649 wr32(E1000_EIAC, adapter->eims_enable_mask);
650 wr32(E1000_EIAM, adapter->eims_enable_mask);
651 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 652 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 653 } else {
654 wr32(E1000_IMS, IMS_ENABLE_MASK);
655 wr32(E1000_IAM, IMS_ENABLE_MASK);
656 }
9d5c8243
AK		 657}
658
659static void igb_update_mng_vlan(struct igb_adapter *adapter)
660{
661 struct net_device *netdev = adapter->netdev;
662 u16 vid = adapter->hw.mng_cookie.vlan_id;
663 u16 old_vid = adapter->mng_vlan_id;
664 if (adapter->vlgrp) {
665 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
666 if (adapter->hw.mng_cookie.status &
667 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
668 igb_vlan_rx_add_vid(netdev, vid);
669 adapter->mng_vlan_id = vid;
670 } else
671 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
672
673 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
674 (vid != old_vid) &&
675 !vlan_group_get_device(adapter->vlgrp, old_vid))
676 igb_vlan_rx_kill_vid(netdev, old_vid);
677 } else
678 adapter->mng_vlan_id = vid;
679 }
680}
681
682/**
683 * igb_release_hw_control - release control of the h/w to f/w
684 * @adapter: address of board private structure
685 *
686 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
687 * For ASF and Pass Through versions of f/w this means that the
688 * driver is no longer loaded.
689 *
690 **/
691static void igb_release_hw_control(struct igb_adapter *adapter)
692{
693 struct e1000_hw *hw = &adapter->hw;
694 u32 ctrl_ext;
695
696 /* Let firmware take over control of h/w */
697 ctrl_ext = rd32(E1000_CTRL_EXT);
698 wr32(E1000_CTRL_EXT,
699 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
700}
701
702
703/**
704 * igb_get_hw_control - get control of the h/w from f/w
705 * @adapter: address of board private structure
706 *
707 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
708 * For ASF and Pass Through versions of f/w this means that
709 * the driver is loaded.
710 *
711 **/
712static void igb_get_hw_control(struct igb_adapter *adapter)
713{
714 struct e1000_hw *hw = &adapter->hw;
715 u32 ctrl_ext;
716
717 /* Let firmware know the driver has taken over */
718 ctrl_ext = rd32(E1000_CTRL_EXT);
719 wr32(E1000_CTRL_EXT,
720 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
721}
722
9d5c8243
AK		 723/**
724 * igb_configure - configure the hardware for RX and TX
725 * @adapter: private board structure
726 **/
727static void igb_configure(struct igb_adapter *adapter)
728{
729 struct net_device *netdev = adapter->netdev;
730 int i;
731
732 igb_get_hw_control(adapter);
733 igb_set_multi(netdev);
734
735 igb_restore_vlan(adapter);
9d5c8243
AK		 736
737 igb_configure_tx(adapter);
738 igb_setup_rctl(adapter);
739 igb_configure_rx(adapter);
662d7205
AD		 740
741 igb_rx_fifo_flush_82575(&adapter->hw);
742
9d5c8243
AK		 743 /* call IGB_DESC_UNUSED which always leaves
744 * at least 1 descriptor unused to make sure
745 * next_to_use != next_to_clean */
746 for (i = 0; i < adapter->num_rx_queues; i++) {
747 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 748 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 749 }
750
751
752 adapter->tx_queue_len = netdev->tx_queue_len;
753}
754
755
756/**
757 * igb_up - Open the interface and prepare it to handle traffic
758 * @adapter: board private structure
759 **/
760
761int igb_up(struct igb_adapter *adapter)
762{
763 struct e1000_hw *hw = &adapter->hw;
764 int i;
765
766 /* hardware has been reset, we need to reload some things */
767 igb_configure(adapter);
768
769 clear_bit(__IGB_DOWN, &adapter->state);
770
844290e5
PW		 771 for (i = 0; i < adapter->num_rx_queues; i++)
772 napi_enable(&adapter->rx_ring[i].napi);
773 if (adapter->msix_entries)
9d5c8243 774 igb_configure_msix(adapter);
9d5c8243
AK		 775
776 /* Clear any pending interrupts. */
777 rd32(E1000_ICR);
778 igb_irq_enable(adapter);
779
780 /* Fire a link change interrupt to start the watchdog. */
781 wr32(E1000_ICS, E1000_ICS_LSC);
782 return 0;
783}
784
785void igb_down(struct igb_adapter *adapter)
786{
787 struct e1000_hw *hw = &adapter->hw;
788 struct net_device *netdev = adapter->netdev;
789 u32 tctl, rctl;
790 int i;
791
792 /* signal that we're down so the interrupt handler does not
793 * reschedule our watchdog timer */
794 set_bit(__IGB_DOWN, &adapter->state);
795
796 /* disable receives in the hardware */
797 rctl = rd32(E1000_RCTL);
798 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
799 /* flush and sleep below */
800
fd2ea0a7 801 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 802
803 /* disable transmits in the hardware */
804 tctl = rd32(E1000_TCTL);
805 tctl &= ~E1000_TCTL_EN;
806 wr32(E1000_TCTL, tctl);
807 /* flush both disables and wait for them to finish */
808 wrfl();
809 msleep(10);
810
844290e5
PW		 811 for (i = 0; i < adapter->num_rx_queues; i++)
812 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 813
9d5c8243
AK		 814 igb_irq_disable(adapter);
815
816 del_timer_sync(&adapter->watchdog_timer);
817 del_timer_sync(&adapter->phy_info_timer);
818
819 netdev->tx_queue_len = adapter->tx_queue_len;
820 netif_carrier_off(netdev);
821 adapter->link_speed = 0;
822 adapter->link_duplex = 0;
823
3023682e
JK		 824 if (!pci_channel_offline(adapter->pdev))
825 igb_reset(adapter);
9d5c8243
AK		 826 igb_clean_all_tx_rings(adapter);
827 igb_clean_all_rx_rings(adapter);
828}
829
830void igb_reinit_locked(struct igb_adapter *adapter)
831{
832 WARN_ON(in_interrupt());
833 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
834 msleep(1);
835 igb_down(adapter);
836 igb_up(adapter);
837 clear_bit(__IGB_RESETTING, &adapter->state);
838}
839
840void igb_reset(struct igb_adapter *adapter)
841{
842 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 843 struct e1000_mac_info *mac = &hw->mac;
844 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 845 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
846 u16 hwm;
847
848 /* Repartition Pba for greater than 9k mtu
849 * To take effect CTRL.RST is required.
850 */
2d064c06 851 if (mac->type != e1000_82576) {
9d5c8243 852 pba = E1000_PBA_34K;
2d064c06
AD		 853 }
854 else {
855 pba = E1000_PBA_64K;
856 }
9d5c8243 857
2d064c06
AD		 858 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
859 (mac->type < e1000_82576)) {
9d5c8243
AK		 860 /* adjust PBA for jumbo frames */
861 wr32(E1000_PBA, pba);
862
863 /* To maintain wire speed transmits, the Tx FIFO should be
864 * large enough to accommodate two full transmit packets,
865 * rounded up to the next 1KB and expressed in KB. Likewise,
866 * the Rx FIFO should be large enough to accommodate at least
867 * one full receive packet and is similarly rounded up and
868 * expressed in KB. */
869 pba = rd32(E1000_PBA);
870 /* upper 16 bits has Tx packet buffer allocation size in KB */
871 tx_space = pba >> 16;
872 /* lower 16 bits has Rx packet buffer allocation size in KB */
873 pba &= 0xffff;
874 /* the tx fifo also stores 16 bytes of information about the tx
875 * but don't include ethernet FCS because hardware appends it */
876 min_tx_space = (adapter->max_frame_size +
877 sizeof(struct e1000_tx_desc) -
878 ETH_FCS_LEN) * 2;
879 min_tx_space = ALIGN(min_tx_space, 1024);
880 min_tx_space >>= 10;
881 /* software strips receive CRC, so leave room for it */
882 min_rx_space = adapter->max_frame_size;
883 min_rx_space = ALIGN(min_rx_space, 1024);
884 min_rx_space >>= 10;
885
886 /* If current Tx allocation is less than the min Tx FIFO size,
887 * and the min Tx FIFO size is less than the current Rx FIFO
888 * allocation, take space away from current Rx allocation */
889 if (tx_space < min_tx_space &&
890 ((min_tx_space - tx_space) < pba)) {
891 pba = pba - (min_tx_space - tx_space);
892
893 /* if short on rx space, rx wins and must trump tx
894 * adjustment */
895 if (pba < min_rx_space)
896 pba = min_rx_space;
897 }
2d064c06 898 wr32(E1000_PBA, pba);
9d5c8243 899 }
9d5c8243
AK		 900
901 /* flow control settings */
902 /* The high water mark must be low enough to fit one full frame
903 * (or the size used for early receive) above it in the Rx FIFO.
904 * Set it to the lower of:
905 * - 90% of the Rx FIFO size, or
906 * - the full Rx FIFO size minus one full frame */
907 hwm = min(((pba << 10) * 9 / 10),
2d064c06 908 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 909
2d064c06
AD		 910 if (mac->type < e1000_82576) {
911 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
912 fc->low_water = fc->high_water - 8;
913 } else {
914 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
915 fc->low_water = fc->high_water - 16;
916 }
9d5c8243
AK		 917 fc->pause_time = 0xFFFF;
918 fc->send_xon = 1;
919 fc->type = fc->original_type;
920
921 /* Allow time for pending master requests to run */
922 adapter->hw.mac.ops.reset_hw(&adapter->hw);
923 wr32(E1000_WUC, 0);
924
925 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
926 dev_err(&adapter->pdev->dev, "Hardware Error\n");
927
928 igb_update_mng_vlan(adapter);
929
930 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
931 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
932
933 igb_reset_adaptive(&adapter->hw);
68707acb
BH		 934 if (adapter->hw.phy.ops.get_phy_info)
935 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 936}
937
42bfd33a
TI		 938/**
939 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
940 * @pdev: PCI device information struct
941 *
942 * Returns true if an adapter needs ioport resources
943 **/
944static int igb_is_need_ioport(struct pci_dev *pdev)
945{
946 switch (pdev->device) {
947 /* Currently there are no adapters that need ioport resources */
948 default:
949 return false;
950 }
951}
952
9d5c8243
AK		 953/**
954 * igb_probe - Device Initialization Routine
955 * @pdev: PCI device information struct
956 * @ent: entry in igb_pci_tbl
957 *
958 * Returns 0 on success, negative on failure
959 *
960 * igb_probe initializes an adapter identified by a pci_dev structure.
961 * The OS initialization, configuring of the adapter private structure,
962 * and a hardware reset occur.
963 **/
964static int __devinit igb_probe(struct pci_dev *pdev,
965 const struct pci_device_id *ent)
966{
967 struct net_device *netdev;
968 struct igb_adapter *adapter;
969 struct e1000_hw *hw;
c54106bb 970 struct pci_dev *us_dev;
9d5c8243
AK		 971 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
972 unsigned long mmio_start, mmio_len;
c54106bb
AD		 973 int i, err, pci_using_dac, pos;
974 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 975 u16 eeprom_apme_mask = IGB_EEPROM_APME;
976 u32 part_num;
42bfd33a 977 int bars, need_ioport;
9d5c8243 978
42bfd33a
TI		 979 /* do not allocate ioport bars when not needed */
980 need_ioport = igb_is_need_ioport(pdev);
981 if (need_ioport) {
982 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
983 err = pci_enable_device(pdev);
984 } else {
985 bars = pci_select_bars(pdev, IORESOURCE_MEM);
986 err = pci_enable_device_mem(pdev);
987 }
9d5c8243
AK		 988 if (err)
989 return err;
990
991 pci_using_dac = 0;
992 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
993 if (!err) {
994 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
995 if (!err)
996 pci_using_dac = 1;
997 } else {
998 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
999 if (err) {
1000 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1001 if (err) {
1002 dev_err(&pdev->dev, "No usable DMA "
1003 "configuration, aborting\n");
1004 goto err_dma;
1005 }
1006 }
1007 }
1008
c54106bb
AD		 1009 /* 82575 requires that the pci-e link partner disable the L0s state */
1010 switch (pdev->device) {
1011 case E1000_DEV_ID_82575EB_COPPER:
1012 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1013 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1014 us_dev = pdev->bus->self;
1015 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1016 if (pos) {
1017 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1018 &state);
1019 state &= ~PCIE_LINK_STATE_L0S;
1020 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1021 state);
ac450208
BH		 1022 dev_info(&pdev->dev,
1023 "Disabling ASPM L0s upstream switch port %s\n",
1024 pci_name(us_dev));
c54106bb
AD		 1025 }
1026 default:
1027 break;
1028 }
1029
42bfd33a 1030 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1031 if (err)
1032 goto err_pci_reg;
1033
1034 pci_set_master(pdev);
c682fc23 1035 pci_save_state(pdev);
9d5c8243
AK		 1036
1037 err = -ENOMEM;
661086df 1038 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1039 if (!netdev)
1040 goto err_alloc_etherdev;
1041
1042 SET_NETDEV_DEV(netdev, &pdev->dev);
1043
1044 pci_set_drvdata(pdev, netdev);
1045 adapter = netdev_priv(netdev);
1046 adapter->netdev = netdev;
1047 adapter->pdev = pdev;
1048 hw = &adapter->hw;
1049 hw->back = adapter;
1050 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1051 adapter->bars = bars;
1052 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1053
1054 mmio_start = pci_resource_start(pdev, 0);
1055 mmio_len = pci_resource_len(pdev, 0);
1056
1057 err = -EIO;
1058 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1059 if (!adapter->hw.hw_addr)
1060 goto err_ioremap;
1061
1062 netdev->open = &igb_open;
1063 netdev->stop = &igb_close;
1064 netdev->get_stats = &igb_get_stats;
1065 netdev->set_multicast_list = &igb_set_multi;
1066 netdev->set_mac_address = &igb_set_mac;
1067 netdev->change_mtu = &igb_change_mtu;
1068 netdev->do_ioctl = &igb_ioctl;
1069 igb_set_ethtool_ops(netdev);
1070 netdev->tx_timeout = &igb_tx_timeout;
1071 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1072 netdev->vlan_rx_register = igb_vlan_rx_register;
1073 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
1074 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
1075#ifdef CONFIG_NET_POLL_CONTROLLER
1076 netdev->poll_controller = igb_netpoll;
1077#endif
1078 netdev->hard_start_xmit = &igb_xmit_frame_adv;
1079
1080 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1081
1082 netdev->mem_start = mmio_start;
1083 netdev->mem_end = mmio_start + mmio_len;
1084
9d5c8243
AK		 1085 /* PCI config space info */
1086 hw->vendor_id = pdev->vendor;
1087 hw->device_id = pdev->device;
1088 hw->revision_id = pdev->revision;
1089 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1090 hw->subsystem_device_id = pdev->subsystem_device;
1091
1092 /* setup the private structure */
1093 hw->back = adapter;
1094 /* Copy the default MAC, PHY and NVM function pointers */
1095 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1096 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1097 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1098 /* Initialize skew-specific constants */
1099 err = ei->get_invariants(hw);
1100 if (err)
1101 goto err_hw_init;
1102
1103 err = igb_sw_init(adapter);
1104 if (err)
1105 goto err_sw_init;
1106
1107 igb_get_bus_info_pcie(hw);
1108
7dfc16fa
AD		 1109 /* set flags */
1110 switch (hw->mac.type) {
1111 case e1000_82576:
1112 case e1000_82575:
1113 adapter->flags |= IGB_FLAG_HAS_DCA;
1114 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1115 break;
1116 default:
1117 break;
1118 }
1119
9d5c8243
AK		 1120 hw->phy.autoneg_wait_to_complete = false;
1121 hw->mac.adaptive_ifs = true;
1122
1123 /* Copper options */
1124 if (hw->phy.media_type == e1000_media_type_copper) {
1125 hw->phy.mdix = AUTO_ALL_MODES;
1126 hw->phy.disable_polarity_correction = false;
1127 hw->phy.ms_type = e1000_ms_hw_default;
1128 }
1129
1130 if (igb_check_reset_block(hw))
1131 dev_info(&pdev->dev,
1132 "PHY reset is blocked due to SOL/IDER session.\n");
1133
1134 netdev->features = NETIF_F_SG |
1135 NETIF_F_HW_CSUM |
1136 NETIF_F_HW_VLAN_TX |
1137 NETIF_F_HW_VLAN_RX |
1138 NETIF_F_HW_VLAN_FILTER;
1139
1140 netdev->features |= NETIF_F_TSO;
9d5c8243 1141 netdev->features |= NETIF_F_TSO6;
48f29ffc 1142
d3352520
AD		 1143#ifdef CONFIG_IGB_LRO
1144 netdev->features |= NETIF_F_LRO;
1145#endif
1146
48f29ffc
JK		 1147 netdev->vlan_features |= NETIF_F_TSO;
1148 netdev->vlan_features |= NETIF_F_TSO6;
1149 netdev->vlan_features |= NETIF_F_HW_CSUM;
1150 netdev->vlan_features |= NETIF_F_SG;
1151
9d5c8243
AK		 1152 if (pci_using_dac)
1153 netdev->features |= NETIF_F_HIGHDMA;
1154
1155 netdev->features |= NETIF_F_LLTX;
1156 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1157
1158 /* before reading the NVM, reset the controller to put the device in a
1159 * known good starting state */
1160 hw->mac.ops.reset_hw(hw);
1161
1162 /* make sure the NVM is good */
1163 if (igb_validate_nvm_checksum(hw) < 0) {
1164 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1165 err = -EIO;
1166 goto err_eeprom;
1167 }
1168
1169 /* copy the MAC address out of the NVM */
1170 if (hw->mac.ops.read_mac_addr(hw))
1171 dev_err(&pdev->dev, "NVM Read Error\n");
1172
1173 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1174 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1175
1176 if (!is_valid_ether_addr(netdev->perm_addr)) {
1177 dev_err(&pdev->dev, "Invalid MAC Address\n");
1178 err = -EIO;
1179 goto err_eeprom;
1180 }
1181
1182 init_timer(&adapter->watchdog_timer);
1183 adapter->watchdog_timer.function = &igb_watchdog;
1184 adapter->watchdog_timer.data = (unsigned long) adapter;
1185
1186 init_timer(&adapter->phy_info_timer);
1187 adapter->phy_info_timer.function = &igb_update_phy_info;
1188 adapter->phy_info_timer.data = (unsigned long) adapter;
1189
1190 INIT_WORK(&adapter->reset_task, igb_reset_task);
1191 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1192
1193 /* Initialize link & ring properties that are user-changeable */
1194 adapter->tx_ring->count = 256;
1195 for (i = 0; i < adapter->num_tx_queues; i++)
1196 adapter->tx_ring[i].count = adapter->tx_ring->count;
1197 adapter->rx_ring->count = 256;
1198 for (i = 0; i < adapter->num_rx_queues; i++)
1199 adapter->rx_ring[i].count = adapter->rx_ring->count;
1200
1201 adapter->fc_autoneg = true;
1202 hw->mac.autoneg = true;
1203 hw->phy.autoneg_advertised = 0x2f;
1204
1205 hw->fc.original_type = e1000_fc_default;
1206 hw->fc.type = e1000_fc_default;
1207
1208 adapter->itr_setting = 3;
1209 adapter->itr = IGB_START_ITR;
1210
1211 igb_validate_mdi_setting(hw);
1212
1213 adapter->rx_csum = 1;
1214
1215 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1216 * enable the ACPI Magic Packet filter
1217 */
1218
1219 if (hw->bus.func == 0 ||
1220 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1221 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1222 &eeprom_data);
1223
1224 if (eeprom_data & eeprom_apme_mask)
1225 adapter->eeprom_wol |= E1000_WUFC_MAG;
1226
1227 /* now that we have the eeprom settings, apply the special cases where
1228 * the eeprom may be wrong or the board simply won't support wake on
1229 * lan on a particular port */
1230 switch (pdev->device) {
1231 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1232 adapter->eeprom_wol = 0;
1233 break;
1234 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1235 case E1000_DEV_ID_82576_FIBER:
1236 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1237 /* Wake events only supported on port A for dual fiber
1238 * regardless of eeprom setting */
1239 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1240 adapter->eeprom_wol = 0;
1241 break;
1242 }
1243
1244 /* initialize the wol settings based on the eeprom settings */
1245 adapter->wol = adapter->eeprom_wol;
e1b86d84 1246 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1247
1248 /* reset the hardware with the new settings */
1249 igb_reset(adapter);
1250
1251 /* let the f/w know that the h/w is now under the control of the
1252 * driver. */
1253 igb_get_hw_control(adapter);
1254
1255 /* tell the stack to leave us alone until igb_open() is called */
1256 netif_carrier_off(netdev);
fd2ea0a7 1257 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1258
1259 strcpy(netdev->name, "eth%d");
1260 err = register_netdev(netdev);
1261 if (err)
1262 goto err_register;
1263
421e02f0 1264#ifdef CONFIG_IGB_DCA
7dfc16fa
AD		 1265 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1266 (dca_add_requester(&pdev->dev) == 0)) {
1267 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1268 dev_info(&pdev->dev, "DCA enabled\n");
1269 /* Always use CB2 mode, difference is masked
1270 * in the CB driver. */
1271 wr32(E1000_DCA_CTRL, 2);
1272 igb_setup_dca(adapter);
1273 }
1274#endif
1275
9d5c8243
AK		 1276 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1277 /* print bus type/speed/width info */
1278 dev_info(&pdev->dev,
1279 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1280 netdev->name,
1281 ((hw->bus.speed == e1000_bus_speed_2500)
1282 ? "2.5Gb/s" : "unknown"),
1283 ((hw->bus.width == e1000_bus_width_pcie_x4)
1284 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1285 ? "Width x1" : "unknown"),
1286 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1287 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1288
1289 igb_read_part_num(hw, &part_num);
1290 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1291 (part_num >> 8), (part_num & 0xff));
1292
1293 dev_info(&pdev->dev,
1294 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1295 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1296 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1297 adapter->num_rx_queues, adapter->num_tx_queues);
1298
9d5c8243
AK		 1299 return 0;
1300
1301err_register:
1302 igb_release_hw_control(adapter);
1303err_eeprom:
1304 if (!igb_check_reset_block(hw))
1305 hw->phy.ops.reset_phy(hw);
1306
1307 if (hw->flash_address)
1308 iounmap(hw->flash_address);
1309
1310 igb_remove_device(hw);
a88f10ec 1311 igb_free_queues(adapter);
9d5c8243
AK		 1312err_sw_init:
1313err_hw_init:
1314 iounmap(hw->hw_addr);
1315err_ioremap:
1316 free_netdev(netdev);
1317err_alloc_etherdev:
42bfd33a 1318 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1319err_pci_reg:
1320err_dma:
1321 pci_disable_device(pdev);
1322 return err;
1323}
1324
1325/**
1326 * igb_remove - Device Removal Routine
1327 * @pdev: PCI device information struct
1328 *
1329 * igb_remove is called by the PCI subsystem to alert the driver
1330 * that it should release a PCI device. The could be caused by a
1331 * Hot-Plug event, or because the driver is going to be removed from
1332 * memory.
1333 **/
1334static void __devexit igb_remove(struct pci_dev *pdev)
1335{
1336 struct net_device *netdev = pci_get_drvdata(pdev);
1337 struct igb_adapter *adapter = netdev_priv(netdev);
421e02f0 1338#ifdef CONFIG_IGB_DCA
fe4506b6 1339 struct e1000_hw *hw = &adapter->hw;
9280fa52 1340#endif
9d5c8243
AK		 1341
1342 /* flush_scheduled work may reschedule our watchdog task, so
1343 * explicitly disable watchdog tasks from being rescheduled */
1344 set_bit(__IGB_DOWN, &adapter->state);
1345 del_timer_sync(&adapter->watchdog_timer);
1346 del_timer_sync(&adapter->phy_info_timer);
1347
1348 flush_scheduled_work();
1349
421e02f0 1350#ifdef CONFIG_IGB_DCA
7dfc16fa 1351 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1352 dev_info(&pdev->dev, "DCA disabled\n");
1353 dca_remove_requester(&pdev->dev);
7dfc16fa 1354 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1355 wr32(E1000_DCA_CTRL, 1);
1356 }
1357#endif
1358
9d5c8243
AK		 1359 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1360 * would have already happened in close and is redundant. */
1361 igb_release_hw_control(adapter);
1362
1363 unregister_netdev(netdev);
1364
c743a87e
AD		 1365 if (adapter->hw.phy.ops.reset_phy &&
1366 !igb_check_reset_block(&adapter->hw))
9d5c8243
AK		 1367 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1368
1369 igb_remove_device(&adapter->hw);
1370 igb_reset_interrupt_capability(adapter);
1371
a88f10ec 1372 igb_free_queues(adapter);
9d5c8243
AK		 1373
1374 iounmap(adapter->hw.hw_addr);
1375 if (adapter->hw.flash_address)
1376 iounmap(adapter->hw.flash_address);
42bfd33a 1377 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1378
1379 free_netdev(netdev);
1380
1381 pci_disable_device(pdev);
1382}
1383
1384/**
1385 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1386 * @adapter: board private structure to initialize
1387 *
1388 * igb_sw_init initializes the Adapter private data structure.
1389 * Fields are initialized based on PCI device information and
1390 * OS network device settings (MTU size).
1391 **/
1392static int __devinit igb_sw_init(struct igb_adapter *adapter)
1393{
1394 struct e1000_hw *hw = &adapter->hw;
1395 struct net_device *netdev = adapter->netdev;
1396 struct pci_dev *pdev = adapter->pdev;
1397
1398 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1399
1400 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1401 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1402 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1403 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1404
1405 /* Number of supported queues. */
1406 /* Having more queues than CPUs doesn't make sense. */
661086df 1407 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
661086df 1408 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
9d5c8243 1409
661086df
PWJ		 1410 /* This call may decrease the number of queues depending on
1411 * interrupt mode. */
9d5c8243
AK		 1412 igb_set_interrupt_capability(adapter);
1413
1414 if (igb_alloc_queues(adapter)) {
1415 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1416 return -ENOMEM;
1417 }
1418
1419 /* Explicitly disable IRQ since the NIC can be in any state. */
1420 igb_irq_disable(adapter);
1421
1422 set_bit(__IGB_DOWN, &adapter->state);
1423 return 0;
1424}
1425
1426/**
1427 * igb_open - Called when a network interface is made active
1428 * @netdev: network interface device structure
1429 *
1430 * Returns 0 on success, negative value on failure
1431 *
1432 * The open entry point is called when a network interface is made
1433 * active by the system (IFF_UP). At this point all resources needed
1434 * for transmit and receive operations are allocated, the interrupt
1435 * handler is registered with the OS, the watchdog timer is started,
1436 * and the stack is notified that the interface is ready.
1437 **/
1438static int igb_open(struct net_device *netdev)
1439{
1440 struct igb_adapter *adapter = netdev_priv(netdev);
1441 struct e1000_hw *hw = &adapter->hw;
1442 int err;
1443 int i;
1444
1445 /* disallow open during test */
1446 if (test_bit(__IGB_TESTING, &adapter->state))
1447 return -EBUSY;
1448
1449 /* allocate transmit descriptors */
1450 err = igb_setup_all_tx_resources(adapter);
1451 if (err)
1452 goto err_setup_tx;
1453
1454 /* allocate receive descriptors */
1455 err = igb_setup_all_rx_resources(adapter);
1456 if (err)
1457 goto err_setup_rx;
1458
1459 /* e1000_power_up_phy(adapter); */
1460
1461 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1462 if ((adapter->hw.mng_cookie.status &
1463 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1464 igb_update_mng_vlan(adapter);
1465
1466 /* before we allocate an interrupt, we must be ready to handle it.
1467 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1468 * as soon as we call pci_request_irq, so we have to setup our
1469 * clean_rx handler before we do so. */
1470 igb_configure(adapter);
1471
1472 err = igb_request_irq(adapter);
1473 if (err)
1474 goto err_req_irq;
1475
1476 /* From here on the code is the same as igb_up() */
1477 clear_bit(__IGB_DOWN, &adapter->state);
1478
844290e5
PW		 1479 for (i = 0; i < adapter->num_rx_queues; i++)
1480 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1481
1482 /* Clear any pending interrupts. */
1483 rd32(E1000_ICR);
844290e5
PW		 1484
1485 igb_irq_enable(adapter);
1486
d55b53ff
JK		 1487 netif_tx_start_all_queues(netdev);
1488
9d5c8243
AK		 1489 /* Fire a link status change interrupt to start the watchdog. */
1490 wr32(E1000_ICS, E1000_ICS_LSC);
1491
1492 return 0;
1493
1494err_req_irq:
1495 igb_release_hw_control(adapter);
1496 /* e1000_power_down_phy(adapter); */
1497 igb_free_all_rx_resources(adapter);
1498err_setup_rx:
1499 igb_free_all_tx_resources(adapter);
1500err_setup_tx:
1501 igb_reset(adapter);
1502
1503 return err;
1504}
1505
1506/**
1507 * igb_close - Disables a network interface
1508 * @netdev: network interface device structure
1509 *
1510 * Returns 0, this is not allowed to fail
1511 *
1512 * The close entry point is called when an interface is de-activated
1513 * by the OS. The hardware is still under the driver's control, but
1514 * needs to be disabled. A global MAC reset is issued to stop the
1515 * hardware, and all transmit and receive resources are freed.
1516 **/
1517static int igb_close(struct net_device *netdev)
1518{
1519 struct igb_adapter *adapter = netdev_priv(netdev);
1520
1521 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1522 igb_down(adapter);
1523
1524 igb_free_irq(adapter);
1525
1526 igb_free_all_tx_resources(adapter);
1527 igb_free_all_rx_resources(adapter);
1528
1529 /* kill manageability vlan ID if supported, but not if a vlan with
1530 * the same ID is registered on the host OS (let 8021q kill it) */
1531 if ((adapter->hw.mng_cookie.status &
1532 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1533 !(adapter->vlgrp &&
1534 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1535 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1536
1537 return 0;
1538}
1539
1540/**
1541 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1542 * @adapter: board private structure
1543 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1544 *
1545 * Return 0 on success, negative on failure
1546 **/
1547
1548int igb_setup_tx_resources(struct igb_adapter *adapter,
1549 struct igb_ring *tx_ring)
1550{
1551 struct pci_dev *pdev = adapter->pdev;
1552 int size;
1553
1554 size = sizeof(struct igb_buffer) * tx_ring->count;
1555 tx_ring->buffer_info = vmalloc(size);
1556 if (!tx_ring->buffer_info)
1557 goto err;
1558 memset(tx_ring->buffer_info, 0, size);
1559
1560 /* round up to nearest 4K */
1561 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1562 + sizeof(u32);
1563 tx_ring->size = ALIGN(tx_ring->size, 4096);
1564
1565 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1566 &tx_ring->dma);
1567
1568 if (!tx_ring->desc)
1569 goto err;
1570
1571 tx_ring->adapter = adapter;
1572 tx_ring->next_to_use = 0;
1573 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1574 return 0;
1575
1576err:
1577 vfree(tx_ring->buffer_info);
1578 dev_err(&adapter->pdev->dev,
1579 "Unable to allocate memory for the transmit descriptor ring\n");
1580 return -ENOMEM;
1581}
1582
1583/**
1584 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1585 * (Descriptors) for all queues
1586 * @adapter: board private structure
1587 *
1588 * Return 0 on success, negative on failure
1589 **/
1590static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1591{
1592 int i, err = 0;
661086df 1593 int r_idx;
9d5c8243
AK		 1594
1595 for (i = 0; i < adapter->num_tx_queues; i++) {
1596 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1597 if (err) {
1598 dev_err(&adapter->pdev->dev,
1599 "Allocation for Tx Queue %u failed\n", i);
1600 for (i--; i >= 0; i--)
3b644cf6 1601 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1602 break;
1603 }
1604 }
1605
661086df
PWJ		 1606 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1607 r_idx = i % adapter->num_tx_queues;
1608 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1609 }
9d5c8243
AK		 1610 return err;
1611}
1612
1613/**
1614 * igb_configure_tx - Configure transmit Unit after Reset
1615 * @adapter: board private structure
1616 *
1617 * Configure the Tx unit of the MAC after a reset.
1618 **/
1619static void igb_configure_tx(struct igb_adapter *adapter)
1620{
1621 u64 tdba, tdwba;
1622 struct e1000_hw *hw = &adapter->hw;
1623 u32 tctl;
1624 u32 txdctl, txctrl;
1625 int i;
1626
1627 for (i = 0; i < adapter->num_tx_queues; i++) {
1628 struct igb_ring *ring = &(adapter->tx_ring[i]);
1629
1630 wr32(E1000_TDLEN(i),
1631 ring->count * sizeof(struct e1000_tx_desc));
1632 tdba = ring->dma;
1633 wr32(E1000_TDBAL(i),
1634 tdba & 0x00000000ffffffffULL);
1635 wr32(E1000_TDBAH(i), tdba >> 32);
1636
1637 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1638 tdwba |= 1; /* enable head wb */
1639 wr32(E1000_TDWBAL(i),
1640 tdwba & 0x00000000ffffffffULL);
1641 wr32(E1000_TDWBAH(i), tdwba >> 32);
1642
1643 ring->head = E1000_TDH(i);
1644 ring->tail = E1000_TDT(i);
1645 writel(0, hw->hw_addr + ring->tail);
1646 writel(0, hw->hw_addr + ring->head);
1647 txdctl = rd32(E1000_TXDCTL(i));
1648 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1649 wr32(E1000_TXDCTL(i), txdctl);
1650
1651 /* Turn off Relaxed Ordering on head write-backs. The
1652 * writebacks MUST be delivered in order or it will
1653 * completely screw up our bookeeping.
1654 */
1655 txctrl = rd32(E1000_DCA_TXCTRL(i));
1656 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1657 wr32(E1000_DCA_TXCTRL(i), txctrl);
1658 }
1659
1660
1661
1662 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1663
1664 /* Program the Transmit Control Register */
1665
1666 tctl = rd32(E1000_TCTL);
1667 tctl &= ~E1000_TCTL_CT;
1668 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1669 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1670
1671 igb_config_collision_dist(hw);
1672
1673 /* Setup Transmit Descriptor Settings for eop descriptor */
1674 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1675
1676 /* Enable transmits */
1677 tctl |= E1000_TCTL_EN;
1678
1679 wr32(E1000_TCTL, tctl);
1680}
1681
1682/**
1683 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1684 * @adapter: board private structure
1685 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1686 *
1687 * Returns 0 on success, negative on failure
1688 **/
1689
1690int igb_setup_rx_resources(struct igb_adapter *adapter,
1691 struct igb_ring *rx_ring)
1692{
1693 struct pci_dev *pdev = adapter->pdev;
1694 int size, desc_len;
1695
d3352520
AD		 1696#ifdef CONFIG_IGB_LRO
1697 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1698 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1699 if (!rx_ring->lro_mgr.lro_arr)
1700 goto err;
1701 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1702#endif
1703
9d5c8243
AK		 1704 size = sizeof(struct igb_buffer) * rx_ring->count;
1705 rx_ring->buffer_info = vmalloc(size);
1706 if (!rx_ring->buffer_info)
1707 goto err;
1708 memset(rx_ring->buffer_info, 0, size);
1709
1710 desc_len = sizeof(union e1000_adv_rx_desc);
1711
1712 /* Round up to nearest 4K */
1713 rx_ring->size = rx_ring->count * desc_len;
1714 rx_ring->size = ALIGN(rx_ring->size, 4096);
1715
1716 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1717 &rx_ring->dma);
1718
1719 if (!rx_ring->desc)
1720 goto err;
1721
1722 rx_ring->next_to_clean = 0;
1723 rx_ring->next_to_use = 0;
9d5c8243
AK		 1724
1725 rx_ring->adapter = adapter;
9d5c8243
AK		 1726
1727 return 0;
1728
1729err:
d3352520
AD		 1730#ifdef CONFIG_IGB_LRO
1731 vfree(rx_ring->lro_mgr.lro_arr);
1732 rx_ring->lro_mgr.lro_arr = NULL;
1733#endif
9d5c8243
AK		 1734 vfree(rx_ring->buffer_info);
1735 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1736 "the receive descriptor ring\n");
1737 return -ENOMEM;
1738}
1739
1740/**
1741 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1742 * (Descriptors) for all queues
1743 * @adapter: board private structure
1744 *
1745 * Return 0 on success, negative on failure
1746 **/
1747static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1748{
1749 int i, err = 0;
1750
1751 for (i = 0; i < adapter->num_rx_queues; i++) {
1752 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1753 if (err) {
1754 dev_err(&adapter->pdev->dev,
1755 "Allocation for Rx Queue %u failed\n", i);
1756 for (i--; i >= 0; i--)
3b644cf6 1757 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1758 break;
1759 }
1760 }
1761
1762 return err;
1763}
1764
1765/**
1766 * igb_setup_rctl - configure the receive control registers
1767 * @adapter: Board private structure
1768 **/
1769static void igb_setup_rctl(struct igb_adapter *adapter)
1770{
1771 struct e1000_hw *hw = &adapter->hw;
1772 u32 rctl;
1773 u32 srrctl = 0;
1774 int i;
1775
1776 rctl = rd32(E1000_RCTL);
1777
1778 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1779
1780 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1781 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1782 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1783
87cb7e8c
AK		 1784 /*
1785 * enable stripping of CRC. It's unlikely this will break BMC
1786 * redirection as it did with e1000. Newer features require
1787 * that the HW strips the CRC.
9d5c8243 1788 */
87cb7e8c 1789 rctl |= E1000_RCTL_SECRC;
9d5c8243
AK		 1790
1791 rctl &= ~E1000_RCTL_SBP;
1792
1793 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1794 rctl &= ~E1000_RCTL_LPE;
1795 else
1796 rctl |= E1000_RCTL_LPE;
1797 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1798 /* Setup buffer sizes */
1799 rctl &= ~E1000_RCTL_SZ_4096;
1800 rctl |= E1000_RCTL_BSEX;
1801 switch (adapter->rx_buffer_len) {
1802 case IGB_RXBUFFER_256:
1803 rctl |= E1000_RCTL_SZ_256;
1804 rctl &= ~E1000_RCTL_BSEX;
1805 break;
1806 case IGB_RXBUFFER_512:
1807 rctl |= E1000_RCTL_SZ_512;
1808 rctl &= ~E1000_RCTL_BSEX;
1809 break;
1810 case IGB_RXBUFFER_1024:
1811 rctl |= E1000_RCTL_SZ_1024;
1812 rctl &= ~E1000_RCTL_BSEX;
1813 break;
1814 case IGB_RXBUFFER_2048:
1815 default:
1816 rctl |= E1000_RCTL_SZ_2048;
1817 rctl &= ~E1000_RCTL_BSEX;
1818 break;
9d5c8243
AK		 1819 }
1820 } else {
1821 rctl &= ~E1000_RCTL_BSEX;
1822 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1823 }
1824
1825 /* 82575 and greater support packet-split where the protocol
1826 * header is placed in skb->data and the packet data is
1827 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1828 * In the case of a non-split, skb->data is linearly filled,
1829 * followed by the page buffers. Therefore, skb->data is
1830 * sized to hold the largest protocol header.
1831 */
1832 /* allocations using alloc_page take too long for regular MTU
1833 * so only enable packet split for jumbo frames */
1834 if (rctl & E1000_RCTL_LPE) {
1835 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1836 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1837 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1838 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1839 } else {
1840 adapter->rx_ps_hdr_size = 0;
1841 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1842 }
1843
1844 for (i = 0; i < adapter->num_rx_queues; i++)
1845 wr32(E1000_SRRCTL(i), srrctl);
1846
1847 wr32(E1000_RCTL, rctl);
1848}
1849
1850/**
1851 * igb_configure_rx - Configure receive Unit after Reset
1852 * @adapter: board private structure
1853 *
1854 * Configure the Rx unit of the MAC after a reset.
1855 **/
1856static void igb_configure_rx(struct igb_adapter *adapter)
1857{
1858 u64 rdba;
1859 struct e1000_hw *hw = &adapter->hw;
1860 u32 rctl, rxcsum;
1861 u32 rxdctl;
1862 int i;
1863
1864 /* disable receives while setting up the descriptors */
1865 rctl = rd32(E1000_RCTL);
1866 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1867 wrfl();
1868 mdelay(10);
1869
1870 if (adapter->itr_setting > 3)
6eb5a7f1 1871 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1872
1873 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1874 * the Base and Length of the Rx Descriptor Ring */
1875 for (i = 0; i < adapter->num_rx_queues; i++) {
1876 struct igb_ring *ring = &(adapter->rx_ring[i]);
1877 rdba = ring->dma;
1878 wr32(E1000_RDBAL(i),
1879 rdba & 0x00000000ffffffffULL);
1880 wr32(E1000_RDBAH(i), rdba >> 32);
1881 wr32(E1000_RDLEN(i),
1882 ring->count * sizeof(union e1000_adv_rx_desc));
1883
1884 ring->head = E1000_RDH(i);
1885 ring->tail = E1000_RDT(i);
1886 writel(0, hw->hw_addr + ring->tail);
1887 writel(0, hw->hw_addr + ring->head);
1888
1889 rxdctl = rd32(E1000_RXDCTL(i));
1890 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1891 rxdctl &= 0xFFF00000;
1892 rxdctl |= IGB_RX_PTHRESH;
1893 rxdctl |= IGB_RX_HTHRESH << 8;
1894 rxdctl |= IGB_RX_WTHRESH << 16;
1895 wr32(E1000_RXDCTL(i), rxdctl);
d3352520
AD		 1896#ifdef CONFIG_IGB_LRO
1897 /* Intitial LRO Settings */
1898 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1899 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1900 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1901 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1902 ring->lro_mgr.dev = adapter->netdev;
1903 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1904 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1905#endif
9d5c8243
AK		 1906 }
1907
1908 if (adapter->num_rx_queues > 1) {
1909 u32 random[10];
1910 u32 mrqc;
1911 u32 j, shift;
1912 union e1000_reta {
1913 u32 dword;
1914 u8 bytes[4];
1915 } reta;
1916
1917 get_random_bytes(&random[0], 40);
1918
2d064c06
AD		 1919 if (hw->mac.type >= e1000_82576)
1920 shift = 0;
1921 else
1922 shift = 6;
9d5c8243
AK		 1923 for (j = 0; j < (32 * 4); j++) {
1924 reta.bytes[j & 3] =
1925 (j % adapter->num_rx_queues) << shift;
1926 if ((j & 3) == 3)
1927 writel(reta.dword,
1928 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1929 }
1930 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1931
1932 /* Fill out hash function seeds */
1933 for (j = 0; j < 10; j++)
1934 array_wr32(E1000_RSSRK(0), j, random[j]);
1935
1936 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1937 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1938 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1939 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1940 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1941 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1942 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1943 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1944
1945
1946 wr32(E1000_MRQC, mrqc);
1947
1948 /* Multiqueue and raw packet checksumming are mutually
1949 * exclusive. Note that this not the same as TCP/IP
1950 * checksumming, which works fine. */
1951 rxcsum = rd32(E1000_RXCSUM);
1952 rxcsum |= E1000_RXCSUM_PCSD;
1953 wr32(E1000_RXCSUM, rxcsum);
1954 } else {
1955 /* Enable Receive Checksum Offload for TCP and UDP */
1956 rxcsum = rd32(E1000_RXCSUM);
1957 if (adapter->rx_csum) {
1958 rxcsum |= E1000_RXCSUM_TUOFL;
1959
1960 /* Enable IPv4 payload checksum for UDP fragments
1961 * Must be used in conjunction with packet-split. */
1962 if (adapter->rx_ps_hdr_size)
1963 rxcsum |= E1000_RXCSUM_IPPCSE;
1964 } else {
1965 rxcsum &= ~E1000_RXCSUM_TUOFL;
1966 /* don't need to clear IPPCSE as it defaults to 0 */
1967 }
1968 wr32(E1000_RXCSUM, rxcsum);
1969 }
1970
1971 if (adapter->vlgrp)
1972 wr32(E1000_RLPML,
1973 adapter->max_frame_size + VLAN_TAG_SIZE);
1974 else
1975 wr32(E1000_RLPML, adapter->max_frame_size);
1976
1977 /* Enable Receives */
1978 wr32(E1000_RCTL, rctl);
1979}
1980
1981/**
1982 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 1983 * @tx_ring: Tx descriptor ring for a specific queue
1984 *
1985 * Free all transmit software resources
1986 **/
3b644cf6 1987static void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1988{
3b644cf6 1989 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1990
3b644cf6 1991 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1992
1993 vfree(tx_ring->buffer_info);
1994 tx_ring->buffer_info = NULL;
1995
1996 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1997
1998 tx_ring->desc = NULL;
1999}
2000
2001/**
2002 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2003 * @adapter: board private structure
2004 *
2005 * Free all transmit software resources
2006 **/
2007static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2008{
2009 int i;
2010
2011 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2012 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2013}
2014
2015static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2016 struct igb_buffer *buffer_info)
2017{
2018 if (buffer_info->dma) {
2019 pci_unmap_page(adapter->pdev,
2020 buffer_info->dma,
2021 buffer_info->length,
2022 PCI_DMA_TODEVICE);
2023 buffer_info->dma = 0;
2024 }
2025 if (buffer_info->skb) {
2026 dev_kfree_skb_any(buffer_info->skb);
2027 buffer_info->skb = NULL;
2028 }
2029 buffer_info->time_stamp = 0;
2030 /* buffer_info must be completely set up in the transmit path */
2031}
2032
2033/**
2034 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2035 * @tx_ring: ring to be cleaned
2036 **/
3b644cf6 2037static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2038{
3b644cf6 2039 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2040 struct igb_buffer *buffer_info;
2041 unsigned long size;
2042 unsigned int i;
2043
2044 if (!tx_ring->buffer_info)
2045 return;
2046 /* Free all the Tx ring sk_buffs */
2047
2048 for (i = 0; i < tx_ring->count; i++) {
2049 buffer_info = &tx_ring->buffer_info[i];
2050 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2051 }
2052
2053 size = sizeof(struct igb_buffer) * tx_ring->count;
2054 memset(tx_ring->buffer_info, 0, size);
2055
2056 /* Zero out the descriptor ring */
2057
2058 memset(tx_ring->desc, 0, tx_ring->size);
2059
2060 tx_ring->next_to_use = 0;
2061 tx_ring->next_to_clean = 0;
2062
2063 writel(0, adapter->hw.hw_addr + tx_ring->head);
2064 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2065}
2066
2067/**
2068 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2069 * @adapter: board private structure
2070 **/
2071static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2072{
2073 int i;
2074
2075 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2076 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2077}
2078
2079/**
2080 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2081 * @rx_ring: ring to clean the resources from
2082 *
2083 * Free all receive software resources
2084 **/
3b644cf6 2085static void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2086{
3b644cf6 2087 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2088
3b644cf6 2089 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2090
2091 vfree(rx_ring->buffer_info);
2092 rx_ring->buffer_info = NULL;
2093
d3352520
AD		 2094#ifdef CONFIG_IGB_LRO
2095 vfree(rx_ring->lro_mgr.lro_arr);
2096 rx_ring->lro_mgr.lro_arr = NULL;
2097#endif
2098
9d5c8243
AK		 2099 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2100
2101 rx_ring->desc = NULL;
2102}
2103
2104/**
2105 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2106 * @adapter: board private structure
2107 *
2108 * Free all receive software resources
2109 **/
2110static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2111{
2112 int i;
2113
2114 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2115 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2116}
2117
2118/**
2119 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2120 * @rx_ring: ring to free buffers from
2121 **/
3b644cf6 2122static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2123{
3b644cf6 2124 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2125 struct igb_buffer *buffer_info;
2126 struct pci_dev *pdev = adapter->pdev;
2127 unsigned long size;
2128 unsigned int i;
2129
2130 if (!rx_ring->buffer_info)
2131 return;
2132 /* Free all the Rx ring sk_buffs */
2133 for (i = 0; i < rx_ring->count; i++) {
2134 buffer_info = &rx_ring->buffer_info[i];
2135 if (buffer_info->dma) {
2136 if (adapter->rx_ps_hdr_size)
2137 pci_unmap_single(pdev, buffer_info->dma,
2138 adapter->rx_ps_hdr_size,
2139 PCI_DMA_FROMDEVICE);
2140 else
2141 pci_unmap_single(pdev, buffer_info->dma,
2142 adapter->rx_buffer_len,
2143 PCI_DMA_FROMDEVICE);
2144 buffer_info->dma = 0;
2145 }
2146
2147 if (buffer_info->skb) {
2148 dev_kfree_skb(buffer_info->skb);
2149 buffer_info->skb = NULL;
2150 }
2151 if (buffer_info->page) {
bf36c1a0
AD		 2152 if (buffer_info->page_dma)
2153 pci_unmap_page(pdev, buffer_info->page_dma,
2154 PAGE_SIZE / 2,
2155 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2156 put_page(buffer_info->page);
2157 buffer_info->page = NULL;
2158 buffer_info->page_dma = 0;
bf36c1a0 2159 buffer_info->page_offset = 0;
9d5c8243
AK		 2160 }
2161 }
2162
9d5c8243
AK		 2163 size = sizeof(struct igb_buffer) * rx_ring->count;
2164 memset(rx_ring->buffer_info, 0, size);
2165
2166 /* Zero out the descriptor ring */
2167 memset(rx_ring->desc, 0, rx_ring->size);
2168
2169 rx_ring->next_to_clean = 0;
2170 rx_ring->next_to_use = 0;
2171
2172 writel(0, adapter->hw.hw_addr + rx_ring->head);
2173 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2174}
2175
2176/**
2177 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2178 * @adapter: board private structure
2179 **/
2180static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2181{
2182 int i;
2183
2184 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2185 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2186}
2187
2188/**
2189 * igb_set_mac - Change the Ethernet Address of the NIC
2190 * @netdev: network interface device structure
2191 * @p: pointer to an address structure
2192 *
2193 * Returns 0 on success, negative on failure
2194 **/
2195static int igb_set_mac(struct net_device *netdev, void *p)
2196{
2197 struct igb_adapter *adapter = netdev_priv(netdev);
2198 struct sockaddr *addr = p;
2199
2200 if (!is_valid_ether_addr(addr->sa_data))
2201 return -EADDRNOTAVAIL;
2202
2203 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2204 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2205
2206 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2207
2208 return 0;
2209}
2210
2211/**
2212 * igb_set_multi - Multicast and Promiscuous mode set
2213 * @netdev: network interface device structure
2214 *
2215 * The set_multi entry point is called whenever the multicast address
2216 * list or the network interface flags are updated. This routine is
2217 * responsible for configuring the hardware for proper multicast,
2218 * promiscuous mode, and all-multi behavior.
2219 **/
2220static void igb_set_multi(struct net_device *netdev)
2221{
2222 struct igb_adapter *adapter = netdev_priv(netdev);
2223 struct e1000_hw *hw = &adapter->hw;
2224 struct e1000_mac_info *mac = &hw->mac;
2225 struct dev_mc_list *mc_ptr;
2226 u8 *mta_list;
2227 u32 rctl;
2228 int i;
2229
2230 /* Check for Promiscuous and All Multicast modes */
2231
2232 rctl = rd32(E1000_RCTL);
2233
746b9f02 2234 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2235 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2236 rctl &= ~E1000_RCTL_VFE;
2237 } else {
2238 if (netdev->flags & IFF_ALLMULTI) {
2239 rctl |= E1000_RCTL_MPE;
2240 rctl &= ~E1000_RCTL_UPE;
2241 } else
2242 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2243 rctl |= E1000_RCTL_VFE;
746b9f02 2244 }
9d5c8243
AK		 2245 wr32(E1000_RCTL, rctl);
2246
2247 if (!netdev->mc_count) {
2248 /* nothing to program, so clear mc list */
2d064c06 2249 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2250 mac->rar_entry_count);
2251 return;
2252 }
2253
2254 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2255 if (!mta_list)
2256 return;
2257
2258 /* The shared function expects a packed array of only addresses. */
2259 mc_ptr = netdev->mc_list;
2260
2261 for (i = 0; i < netdev->mc_count; i++) {
2262 if (!mc_ptr)
2263 break;
2264 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2265 mc_ptr = mc_ptr->next;
2266 }
2d064c06
AD		 2267 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2268 mac->rar_entry_count);
9d5c8243
AK		 2269 kfree(mta_list);
2270}
2271
2272/* Need to wait a few seconds after link up to get diagnostic information from
2273 * the phy */
2274static void igb_update_phy_info(unsigned long data)
2275{
2276 struct igb_adapter *adapter = (struct igb_adapter *) data;
68707acb
BH		 2277 if (adapter->hw.phy.ops.get_phy_info)
2278 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 2279}
2280
2281/**
2282 * igb_watchdog - Timer Call-back
2283 * @data: pointer to adapter cast into an unsigned long
2284 **/
2285static void igb_watchdog(unsigned long data)
2286{
2287 struct igb_adapter *adapter = (struct igb_adapter *)data;
2288 /* Do the rest outside of interrupt context */
2289 schedule_work(&adapter->watchdog_task);
2290}
2291
2292static void igb_watchdog_task(struct work_struct *work)
2293{
2294 struct igb_adapter *adapter = container_of(work,
2295 struct igb_adapter, watchdog_task);
2296 struct e1000_hw *hw = &adapter->hw;
2297
2298 struct net_device *netdev = adapter->netdev;
2299 struct igb_ring *tx_ring = adapter->tx_ring;
2300 struct e1000_mac_info *mac = &adapter->hw.mac;
2301 u32 link;
7a6ea550 2302 u32 eics = 0;
9d5c8243 2303 s32 ret_val;
7a6ea550 2304 int i;
9d5c8243
AK		 2305
2306 if ((netif_carrier_ok(netdev)) &&
2307 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2308 goto link_up;
2309
2310 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2311 if ((ret_val == E1000_ERR_PHY) &&
2312 (hw->phy.type == e1000_phy_igp_3) &&
2313 (rd32(E1000_CTRL) &
2314 E1000_PHY_CTRL_GBE_DISABLE))
2315 dev_info(&adapter->pdev->dev,
2316 "Gigabit has been disabled, downgrading speed\n");
2317
2318 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2319 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2320 link = mac->serdes_has_link;
2321 else
2322 link = rd32(E1000_STATUS) &
2323 E1000_STATUS_LU;
2324
2325 if (link) {
2326 if (!netif_carrier_ok(netdev)) {
2327 u32 ctrl;
2328 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2329 &adapter->link_speed,
2330 &adapter->link_duplex);
2331
2332 ctrl = rd32(E1000_CTRL);
2333 dev_info(&adapter->pdev->dev,
2334 "NIC Link is Up %d Mbps %s, "
2335 "Flow Control: %s\n",
2336 adapter->link_speed,
2337 adapter->link_duplex == FULL_DUPLEX ?
2338 "Full Duplex" : "Half Duplex",
2339 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2340 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2341 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2342 E1000_CTRL_TFCE) ? "TX" : "None")));
2343
2344 /* tweak tx_queue_len according to speed/duplex and
2345 * adjust the timeout factor */
2346 netdev->tx_queue_len = adapter->tx_queue_len;
2347 adapter->tx_timeout_factor = 1;
2348 switch (adapter->link_speed) {
2349 case SPEED_10:
2350 netdev->tx_queue_len = 10;
2351 adapter->tx_timeout_factor = 14;
2352 break;
2353 case SPEED_100:
2354 netdev->tx_queue_len = 100;
2355 /* maybe add some timeout factor ? */
2356 break;
2357 }
2358
2359 netif_carrier_on(netdev);
fd2ea0a7 2360 netif_tx_wake_all_queues(netdev);
9d5c8243
AK		 2361
2362 if (!test_bit(__IGB_DOWN, &adapter->state))
2363 mod_timer(&adapter->phy_info_timer,
2364 round_jiffies(jiffies + 2 * HZ));
2365 }
2366 } else {
2367 if (netif_carrier_ok(netdev)) {
2368 adapter->link_speed = 0;
2369 adapter->link_duplex = 0;
2370 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2371 netif_carrier_off(netdev);
fd2ea0a7 2372 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 2373 if (!test_bit(__IGB_DOWN, &adapter->state))
2374 mod_timer(&adapter->phy_info_timer,
2375 round_jiffies(jiffies + 2 * HZ));
2376 }
2377 }
2378
2379link_up:
2380 igb_update_stats(adapter);
2381
2382 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2383 adapter->tpt_old = adapter->stats.tpt;
2384 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2385 adapter->colc_old = adapter->stats.colc;
2386
2387 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2388 adapter->gorc_old = adapter->stats.gorc;
2389 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2390 adapter->gotc_old = adapter->stats.gotc;
2391
2392 igb_update_adaptive(&adapter->hw);
2393
2394 if (!netif_carrier_ok(netdev)) {
2395 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2396 /* We've lost link, so the controller stops DMA,
2397 * but we've got queued Tx work that's never going
2398 * to get done, so reset controller to flush Tx.
2399 * (Do the reset outside of interrupt context). */
2400 adapter->tx_timeout_count++;
2401 schedule_work(&adapter->reset_task);
2402 }
2403 }
2404
2405 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2406 if (adapter->msix_entries) {
2407 for (i = 0; i < adapter->num_rx_queues; i++)
2408 eics |= adapter->rx_ring[i].eims_value;
2409 wr32(E1000_EICS, eics);
2410 } else {
2411 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2412 }
9d5c8243
AK		 2413
2414 /* Force detection of hung controller every watchdog period */
2415 tx_ring->detect_tx_hung = true;
2416
2417 /* Reset the timer */
2418 if (!test_bit(__IGB_DOWN, &adapter->state))
2419 mod_timer(&adapter->watchdog_timer,
2420 round_jiffies(jiffies + 2 * HZ));
2421}
2422
2423enum latency_range {
2424 lowest_latency = 0,
2425 low_latency = 1,
2426 bulk_latency = 2,
2427 latency_invalid = 255
2428};
2429
2430
6eb5a7f1
AD		 2431/**
2432 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2433 *
2434 * Stores a new ITR value based on strictly on packet size. This
2435 * algorithm is less sophisticated than that used in igb_update_itr,
2436 * due to the difficulty of synchronizing statistics across multiple
2437 * receive rings. The divisors and thresholds used by this fuction
2438 * were determined based on theoretical maximum wire speed and testing
2439 * data, in order to minimize response time while increasing bulk
2440 * throughput.
2441 * This functionality is controlled by the InterruptThrottleRate module
2442 * parameter (see igb_param.c)
2443 * NOTE: This function is called only when operating in a multiqueue
2444 * receive environment.
2445 * @rx_ring: pointer to ring
2446 **/
2447static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2448{
6eb5a7f1
AD		 2449 int new_val = rx_ring->itr_val;
2450 int avg_wire_size = 0;
2451 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2452
6eb5a7f1
AD		 2453 if (!rx_ring->total_packets)
2454 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2455
6eb5a7f1
AD		 2456 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2457 * ints/sec - ITR timer value of 120 ticks.
2458 */
2459 if (adapter->link_speed != SPEED_1000) {
2460 new_val = 120;
2461 goto set_itr_val;
9d5c8243 2462 }
6eb5a7f1 2463 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2464
6eb5a7f1
AD		 2465 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2466 avg_wire_size += 24;
2467
2468 /* Don't starve jumbo frames */
2469 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2470
6eb5a7f1
AD		 2471 /* Give a little boost to mid-size frames */
2472 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2473 new_val = avg_wire_size / 3;
2474 else
2475 new_val = avg_wire_size / 2;
9d5c8243 2476
6eb5a7f1 2477set_itr_val:
9d5c8243
AK		 2478 if (new_val != rx_ring->itr_val) {
2479 rx_ring->itr_val = new_val;
6eb5a7f1 2480 rx_ring->set_itr = 1;
9d5c8243 2481 }
6eb5a7f1
AD		 2482clear_counts:
2483 rx_ring->total_bytes = 0;
2484 rx_ring->total_packets = 0;
9d5c8243
AK		 2485}
2486
2487/**
2488 * igb_update_itr - update the dynamic ITR value based on statistics
2489 * Stores a new ITR value based on packets and byte
2490 * counts during the last interrupt. The advantage of per interrupt
2491 * computation is faster updates and more accurate ITR for the current
2492 * traffic pattern. Constants in this function were computed
2493 * based on theoretical maximum wire speed and thresholds were set based
2494 * on testing data as well as attempting to minimize response time
2495 * while increasing bulk throughput.
2496 * this functionality is controlled by the InterruptThrottleRate module
2497 * parameter (see igb_param.c)
2498 * NOTE: These calculations are only valid when operating in a single-
2499 * queue environment.
2500 * @adapter: pointer to adapter
2501 * @itr_setting: current adapter->itr
2502 * @packets: the number of packets during this measurement interval
2503 * @bytes: the number of bytes during this measurement interval
2504 **/
2505static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2506 int packets, int bytes)
2507{
2508 unsigned int retval = itr_setting;
2509
2510 if (packets == 0)
2511 goto update_itr_done;
2512
2513 switch (itr_setting) {
2514 case lowest_latency:
2515 /* handle TSO and jumbo frames */
2516 if (bytes/packets > 8000)
2517 retval = bulk_latency;
2518 else if ((packets < 5) && (bytes > 512))
2519 retval = low_latency;
2520 break;
2521 case low_latency: /* 50 usec aka 20000 ints/s */
2522 if (bytes > 10000) {
2523 /* this if handles the TSO accounting */
2524 if (bytes/packets > 8000) {
2525 retval = bulk_latency;
2526 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2527 retval = bulk_latency;
2528 } else if ((packets > 35)) {
2529 retval = lowest_latency;
2530 }
2531 } else if (bytes/packets > 2000) {
2532 retval = bulk_latency;
2533 } else if (packets <= 2 && bytes < 512) {
2534 retval = lowest_latency;
2535 }
2536 break;
2537 case bulk_latency: /* 250 usec aka 4000 ints/s */
2538 if (bytes > 25000) {
2539 if (packets > 35)
2540 retval = low_latency;
2541 } else if (bytes < 6000) {
2542 retval = low_latency;
2543 }
2544 break;
2545 }
2546
2547update_itr_done:
2548 return retval;
2549}
2550
6eb5a7f1 2551static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2552{
2553 u16 current_itr;
2554 u32 new_itr = adapter->itr;
2555
2556 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2557 if (adapter->link_speed != SPEED_1000) {
2558 current_itr = 0;
2559 new_itr = 4000;
2560 goto set_itr_now;
2561 }
2562
2563 adapter->rx_itr = igb_update_itr(adapter,
2564 adapter->rx_itr,
2565 adapter->rx_ring->total_packets,
2566 adapter->rx_ring->total_bytes);
9d5c8243 2567
6eb5a7f1 2568 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2569 adapter->tx_itr = igb_update_itr(adapter,
2570 adapter->tx_itr,
2571 adapter->tx_ring->total_packets,
2572 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2573
2574 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2575 } else {
2576 current_itr = adapter->rx_itr;
2577 }
2578
6eb5a7f1
AD		 2579 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2580 if (adapter->itr_setting == 3 &&
2581 current_itr == lowest_latency)
2582 current_itr = low_latency;
2583
9d5c8243
AK		 2584 switch (current_itr) {
2585 /* counts and packets in update_itr are dependent on these numbers */
2586 case lowest_latency:
2587 new_itr = 70000;
2588 break;
2589 case low_latency:
2590 new_itr = 20000; /* aka hwitr = ~200 */
2591 break;
2592 case bulk_latency:
2593 new_itr = 4000;
2594 break;
2595 default:
2596 break;
2597 }
2598
2599set_itr_now:
6eb5a7f1
AD		 2600 adapter->rx_ring->total_bytes = 0;
2601 adapter->rx_ring->total_packets = 0;
2602 if (adapter->rx_ring->buddy) {
2603 adapter->rx_ring->buddy->total_bytes = 0;
2604 adapter->rx_ring->buddy->total_packets = 0;
2605 }
2606
9d5c8243
AK		 2607 if (new_itr != adapter->itr) {
2608 /* this attempts to bias the interrupt rate towards Bulk
2609 * by adding intermediate steps when interrupt rate is
2610 * increasing */
2611 new_itr = new_itr > adapter->itr ?
2612 min(adapter->itr + (new_itr >> 2), new_itr) :
2613 new_itr;
2614 /* Don't write the value here; it resets the adapter's
2615 * internal timer, and causes us to delay far longer than
2616 * we should between interrupts. Instead, we write the ITR
2617 * value at the beginning of the next interrupt so the timing
2618 * ends up being correct.
2619 */
2620 adapter->itr = new_itr;
6eb5a7f1
AD		 2621 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2622 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2623 }
2624
2625 return;
2626}
2627
2628
2629#define IGB_TX_FLAGS_CSUM 0x00000001
2630#define IGB_TX_FLAGS_VLAN 0x00000002
2631#define IGB_TX_FLAGS_TSO 0x00000004
2632#define IGB_TX_FLAGS_IPV4 0x00000008
2633#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2634#define IGB_TX_FLAGS_VLAN_SHIFT 16
2635
2636static inline int igb_tso_adv(struct igb_adapter *adapter,
2637 struct igb_ring *tx_ring,
2638 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2639{
2640 struct e1000_adv_tx_context_desc *context_desc;
2641 unsigned int i;
2642 int err;
2643 struct igb_buffer *buffer_info;
2644 u32 info = 0, tu_cmd = 0;
2645 u32 mss_l4len_idx, l4len;
2646 *hdr_len = 0;
2647
2648 if (skb_header_cloned(skb)) {
2649 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2650 if (err)
2651 return err;
2652 }
2653
2654 l4len = tcp_hdrlen(skb);
2655 *hdr_len += l4len;
2656
2657 if (skb->protocol == htons(ETH_P_IP)) {
2658 struct iphdr *iph = ip_hdr(skb);
2659 iph->tot_len = 0;
2660 iph->check = 0;
2661 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2662 iph->daddr, 0,
2663 IPPROTO_TCP,
2664 0);
2665 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2666 ipv6_hdr(skb)->payload_len = 0;
2667 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2668 &ipv6_hdr(skb)->daddr,
2669 0, IPPROTO_TCP, 0);
2670 }
2671
2672 i = tx_ring->next_to_use;
2673
2674 buffer_info = &tx_ring->buffer_info[i];
2675 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2676 /* VLAN MACLEN IPLEN */
2677 if (tx_flags & IGB_TX_FLAGS_VLAN)
2678 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2679 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2680 *hdr_len += skb_network_offset(skb);
2681 info |= skb_network_header_len(skb);
2682 *hdr_len += skb_network_header_len(skb);
2683 context_desc->vlan_macip_lens = cpu_to_le32(info);
2684
2685 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2686 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2687
2688 if (skb->protocol == htons(ETH_P_IP))
2689 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2690 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2691
2692 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2693
2694 /* MSS L4LEN IDX */
2695 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2696 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2697
7dfc16fa
AD		 2698 /* Context index must be unique per ring. */
2699 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2700 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2701
2702 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2703 context_desc->seqnum_seed = 0;
2704
2705 buffer_info->time_stamp = jiffies;
2706 buffer_info->dma = 0;
2707 i++;
2708 if (i == tx_ring->count)
2709 i = 0;
2710
2711 tx_ring->next_to_use = i;
2712
2713 return true;
2714}
2715
2716static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2717 struct igb_ring *tx_ring,
2718 struct sk_buff *skb, u32 tx_flags)
2719{
2720 struct e1000_adv_tx_context_desc *context_desc;
2721 unsigned int i;
2722 struct igb_buffer *buffer_info;
2723 u32 info = 0, tu_cmd = 0;
2724
2725 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2726 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2727 i = tx_ring->next_to_use;
2728 buffer_info = &tx_ring->buffer_info[i];
2729 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2730
2731 if (tx_flags & IGB_TX_FLAGS_VLAN)
2732 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2733 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2734 if (skb->ip_summed == CHECKSUM_PARTIAL)
2735 info |= skb_network_header_len(skb);
2736
2737 context_desc->vlan_macip_lens = cpu_to_le32(info);
2738
2739 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2740
2741 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2742 switch (skb->protocol) {
2743 case __constant_htons(ETH_P_IP):
9d5c8243 2744 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2745 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2746 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2747 break;
2748 case __constant_htons(ETH_P_IPV6):
2749 /* XXX what about other V6 headers?? */
2750 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2751 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2752 break;
2753 default:
2754 if (unlikely(net_ratelimit()))
2755 dev_warn(&adapter->pdev->dev,
2756 "partial checksum but proto=%x!\n",
2757 skb->protocol);
2758 break;
2759 }
9d5c8243
AK		 2760 }
2761
2762 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2763 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2764 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2765 context_desc->mss_l4len_idx =
2766 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2767
2768 buffer_info->time_stamp = jiffies;
2769 buffer_info->dma = 0;
2770
2771 i++;
2772 if (i == tx_ring->count)
2773 i = 0;
2774 tx_ring->next_to_use = i;
2775
2776 return true;
2777 }
2778
2779
2780 return false;
2781}
2782
2783#define IGB_MAX_TXD_PWR 16
2784#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2785
2786static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2787 struct igb_ring *tx_ring,
2788 struct sk_buff *skb)
2789{
2790 struct igb_buffer *buffer_info;
2791 unsigned int len = skb_headlen(skb);
2792 unsigned int count = 0, i;
2793 unsigned int f;
2794
2795 i = tx_ring->next_to_use;
2796
2797 buffer_info = &tx_ring->buffer_info[i];
2798 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2799 buffer_info->length = len;
2800 /* set time_stamp *before* dma to help avoid a possible race */
2801 buffer_info->time_stamp = jiffies;
2802 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2803 PCI_DMA_TODEVICE);
2804 count++;
2805 i++;
2806 if (i == tx_ring->count)
2807 i = 0;
2808
2809 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2810 struct skb_frag_struct *frag;
2811
2812 frag = &skb_shinfo(skb)->frags[f];
2813 len = frag->size;
2814
2815 buffer_info = &tx_ring->buffer_info[i];
2816 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2817 buffer_info->length = len;
2818 buffer_info->time_stamp = jiffies;
2819 buffer_info->dma = pci_map_page(adapter->pdev,
2820 frag->page,
2821 frag->page_offset,
2822 len,
2823 PCI_DMA_TODEVICE);
2824
2825 count++;
2826 i++;
2827 if (i == tx_ring->count)
2828 i = 0;
2829 }
2830
2831 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2832 tx_ring->buffer_info[i].skb = skb;
2833
2834 return count;
2835}
2836
2837static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2838 struct igb_ring *tx_ring,
2839 int tx_flags, int count, u32 paylen,
2840 u8 hdr_len)
2841{
2842 union e1000_adv_tx_desc *tx_desc = NULL;
2843 struct igb_buffer *buffer_info;
2844 u32 olinfo_status = 0, cmd_type_len;
2845 unsigned int i;
2846
2847 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2848 E1000_ADVTXD_DCMD_DEXT);
2849
2850 if (tx_flags & IGB_TX_FLAGS_VLAN)
2851 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2852
2853 if (tx_flags & IGB_TX_FLAGS_TSO) {
2854 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2855
2856 /* insert tcp checksum */
2857 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2858
2859 /* insert ip checksum */
2860 if (tx_flags & IGB_TX_FLAGS_IPV4)
2861 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2862
2863 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2864 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2865 }
2866
7dfc16fa
AD		 2867 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2868 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2869 IGB_TX_FLAGS_VLAN)))
661086df 2870 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2871
2872 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2873
2874 i = tx_ring->next_to_use;
2875 while (count--) {
2876 buffer_info = &tx_ring->buffer_info[i];
2877 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2878 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2879 tx_desc->read.cmd_type_len =
2880 cpu_to_le32(cmd_type_len | buffer_info->length);
2881 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2882 i++;
2883 if (i == tx_ring->count)
2884 i = 0;
2885 }
2886
2887 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2888 /* Force memory writes to complete before letting h/w
2889 * know there are new descriptors to fetch. (Only
2890 * applicable for weak-ordered memory model archs,
2891 * such as IA-64). */
2892 wmb();
2893
2894 tx_ring->next_to_use = i;
2895 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2896 /* we need this if more than one processor can write to our tail
2897 * at a time, it syncronizes IO on IA64/Altix systems */
2898 mmiowb();
2899}
2900
2901static int __igb_maybe_stop_tx(struct net_device *netdev,
2902 struct igb_ring *tx_ring, int size)
2903{
2904 struct igb_adapter *adapter = netdev_priv(netdev);
2905
661086df 2906 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2907
9d5c8243
AK		 2908 /* Herbert's original patch had:
2909 * smp_mb__after_netif_stop_queue();
2910 * but since that doesn't exist yet, just open code it. */
2911 smp_mb();
2912
2913 /* We need to check again in a case another CPU has just
2914 * made room available. */
2915 if (IGB_DESC_UNUSED(tx_ring) < size)
2916 return -EBUSY;
2917
2918 /* A reprieve! */
661086df 2919 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2920 ++adapter->restart_queue;
2921 return 0;
2922}
2923
2924static int igb_maybe_stop_tx(struct net_device *netdev,
2925 struct igb_ring *tx_ring, int size)
2926{
2927 if (IGB_DESC_UNUSED(tx_ring) >= size)
2928 return 0;
2929 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2930}
2931
2932#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2933
2934static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2935 struct net_device *netdev,
2936 struct igb_ring *tx_ring)
2937{
2938 struct igb_adapter *adapter = netdev_priv(netdev);
2939 unsigned int tx_flags = 0;
2940 unsigned int len;
9d5c8243
AK		 2941 u8 hdr_len = 0;
2942 int tso = 0;
2943
2944 len = skb_headlen(skb);
2945
2946 if (test_bit(__IGB_DOWN, &adapter->state)) {
2947 dev_kfree_skb_any(skb);
2948 return NETDEV_TX_OK;
2949 }
2950
2951 if (skb->len <= 0) {
2952 dev_kfree_skb_any(skb);
2953 return NETDEV_TX_OK;
2954 }
2955
9d5c8243
AK		 2956 /* need: 1 descriptor per page,
2957 * + 2 desc gap to keep tail from touching head,
2958 * + 1 desc for skb->data,
2959 * + 1 desc for context descriptor,
2960 * otherwise try next time */
2961 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2962 /* this is a hard error */
9d5c8243
AK		 2963 return NETDEV_TX_BUSY;
2964 }
6eb5a7f1 2965 skb_orphan(skb);
9d5c8243
AK		 2966
2967 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2968 tx_flags |= IGB_TX_FLAGS_VLAN;
2969 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2970 }
2971
661086df
PWJ		 2972 if (skb->protocol == htons(ETH_P_IP))
2973 tx_flags |= IGB_TX_FLAGS_IPV4;
2974
9d5c8243
AK		 2975 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2976 &hdr_len) : 0;
2977
2978 if (tso < 0) {
2979 dev_kfree_skb_any(skb);
9d5c8243
AK		 2980 return NETDEV_TX_OK;
2981 }
2982
2983 if (tso)
2984 tx_flags |= IGB_TX_FLAGS_TSO;
2985 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2986 if (skb->ip_summed == CHECKSUM_PARTIAL)
2987 tx_flags |= IGB_TX_FLAGS_CSUM;
2988
9d5c8243
AK		 2989 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2990 igb_tx_map_adv(adapter, tx_ring, skb),
2991 skb->len, hdr_len);
2992
2993 netdev->trans_start = jiffies;
2994
2995 /* Make sure there is space in the ring for the next send. */
2996 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2997
9d5c8243
AK		 2998 return NETDEV_TX_OK;
2999}
3000
3001static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3002{
3003 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3004 struct igb_ring *tx_ring;
3005
661086df
PWJ		 3006 int r_idx = 0;
3007 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3008 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3009
3010 /* This goes back to the question of how to logically map a tx queue
3011 * to a flow. Right now, performance is impacted slightly negatively
3012 * if using multiple tx queues. If the stack breaks away from a
3013 * single qdisc implementation, we can look at this again. */
3014 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3015}
3016
3017/**
3018 * igb_tx_timeout - Respond to a Tx Hang
3019 * @netdev: network interface device structure
3020 **/
3021static void igb_tx_timeout(struct net_device *netdev)
3022{
3023 struct igb_adapter *adapter = netdev_priv(netdev);
3024 struct e1000_hw *hw = &adapter->hw;
3025
3026 /* Do the reset outside of interrupt context */
3027 adapter->tx_timeout_count++;
3028 schedule_work(&adapter->reset_task);
3029 wr32(E1000_EICS, adapter->eims_enable_mask &
3030 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3031}
3032
3033static void igb_reset_task(struct work_struct *work)
3034{
3035 struct igb_adapter *adapter;
3036 adapter = container_of(work, struct igb_adapter, reset_task);
3037
3038 igb_reinit_locked(adapter);
3039}
3040
3041/**
3042 * igb_get_stats - Get System Network Statistics
3043 * @netdev: network interface device structure
3044 *
3045 * Returns the address of the device statistics structure.
3046 * The statistics are actually updated from the timer callback.
3047 **/
3048static struct net_device_stats *
3049igb_get_stats(struct net_device *netdev)
3050{
3051 struct igb_adapter *adapter = netdev_priv(netdev);
3052
3053 /* only return the current stats */
3054 return &adapter->net_stats;
3055}
3056
3057/**
3058 * igb_change_mtu - Change the Maximum Transfer Unit
3059 * @netdev: network interface device structure
3060 * @new_mtu: new value for maximum frame size
3061 *
3062 * Returns 0 on success, negative on failure
3063 **/
3064static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3065{
3066 struct igb_adapter *adapter = netdev_priv(netdev);
3067 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3068
3069 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3070 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3071 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3072 return -EINVAL;
3073 }
3074
3075#define MAX_STD_JUMBO_FRAME_SIZE 9234
3076 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3077 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3078 return -EINVAL;
3079 }
3080
3081 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3082 msleep(1);
3083 /* igb_down has a dependency on max_frame_size */
3084 adapter->max_frame_size = max_frame;
3085 if (netif_running(netdev))
3086 igb_down(adapter);
3087
3088 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3089 * means we reserve 2 more, this pushes us to allocate from the next
3090 * larger slab size.
3091 * i.e. RXBUFFER_2048 --> size-4096 slab
3092 */
3093
3094 if (max_frame <= IGB_RXBUFFER_256)
3095 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3096 else if (max_frame <= IGB_RXBUFFER_512)
3097 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3098 else if (max_frame <= IGB_RXBUFFER_1024)
3099 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3100 else if (max_frame <= IGB_RXBUFFER_2048)
3101 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3102 else
bf36c1a0
AD		 3103#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3104 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3105#else
3106 adapter->rx_buffer_len = PAGE_SIZE / 2;
3107#endif
9d5c8243
AK		 3108 /* adjust allocation if LPE protects us, and we aren't using SBP */
3109 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3110 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3111 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3112
3113 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3114 netdev->mtu, new_mtu);
3115 netdev->mtu = new_mtu;
3116
3117 if (netif_running(netdev))
3118 igb_up(adapter);
3119 else
3120 igb_reset(adapter);
3121
3122 clear_bit(__IGB_RESETTING, &adapter->state);
3123
3124 return 0;
3125}
3126
3127/**
3128 * igb_update_stats - Update the board statistics counters
3129 * @adapter: board private structure
3130 **/
3131
3132void igb_update_stats(struct igb_adapter *adapter)
3133{
3134 struct e1000_hw *hw = &adapter->hw;
3135 struct pci_dev *pdev = adapter->pdev;
3136 u16 phy_tmp;
3137
3138#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3139
3140 /*
3141 * Prevent stats update while adapter is being reset, or if the pci
3142 * connection is down.
3143 */
3144 if (adapter->link_speed == 0)
3145 return;
3146 if (pci_channel_offline(pdev))
3147 return;
3148
3149 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3150 adapter->stats.gprc += rd32(E1000_GPRC);
3151 adapter->stats.gorc += rd32(E1000_GORCL);
3152 rd32(E1000_GORCH); /* clear GORCL */
3153 adapter->stats.bprc += rd32(E1000_BPRC);
3154 adapter->stats.mprc += rd32(E1000_MPRC);
3155 adapter->stats.roc += rd32(E1000_ROC);
3156
3157 adapter->stats.prc64 += rd32(E1000_PRC64);
3158 adapter->stats.prc127 += rd32(E1000_PRC127);
3159 adapter->stats.prc255 += rd32(E1000_PRC255);
3160 adapter->stats.prc511 += rd32(E1000_PRC511);
3161 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3162 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3163 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3164 adapter->stats.sec += rd32(E1000_SEC);
3165
3166 adapter->stats.mpc += rd32(E1000_MPC);
3167 adapter->stats.scc += rd32(E1000_SCC);
3168 adapter->stats.ecol += rd32(E1000_ECOL);
3169 adapter->stats.mcc += rd32(E1000_MCC);
3170 adapter->stats.latecol += rd32(E1000_LATECOL);
3171 adapter->stats.dc += rd32(E1000_DC);
3172 adapter->stats.rlec += rd32(E1000_RLEC);
3173 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3174 adapter->stats.xontxc += rd32(E1000_XONTXC);
3175 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3176 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3177 adapter->stats.fcruc += rd32(E1000_FCRUC);
3178 adapter->stats.gptc += rd32(E1000_GPTC);
3179 adapter->stats.gotc += rd32(E1000_GOTCL);
3180 rd32(E1000_GOTCH); /* clear GOTCL */
3181 adapter->stats.rnbc += rd32(E1000_RNBC);
3182 adapter->stats.ruc += rd32(E1000_RUC);
3183 adapter->stats.rfc += rd32(E1000_RFC);
3184 adapter->stats.rjc += rd32(E1000_RJC);
3185 adapter->stats.tor += rd32(E1000_TORH);
3186 adapter->stats.tot += rd32(E1000_TOTH);
3187 adapter->stats.tpr += rd32(E1000_TPR);
3188
3189 adapter->stats.ptc64 += rd32(E1000_PTC64);
3190 adapter->stats.ptc127 += rd32(E1000_PTC127);
3191 adapter->stats.ptc255 += rd32(E1000_PTC255);
3192 adapter->stats.ptc511 += rd32(E1000_PTC511);
3193 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3194 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3195
3196 adapter->stats.mptc += rd32(E1000_MPTC);
3197 adapter->stats.bptc += rd32(E1000_BPTC);
3198
3199 /* used for adaptive IFS */
3200
3201 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3202 adapter->stats.tpt += hw->mac.tx_packet_delta;
3203 hw->mac.collision_delta = rd32(E1000_COLC);
3204 adapter->stats.colc += hw->mac.collision_delta;
3205
3206 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3207 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3208 adapter->stats.tncrs += rd32(E1000_TNCRS);
3209 adapter->stats.tsctc += rd32(E1000_TSCTC);
3210 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3211
3212 adapter->stats.iac += rd32(E1000_IAC);
3213 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3214 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3215 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3216 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3217 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3218 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3219 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3220 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3221
3222 /* Fill out the OS statistics structure */
3223 adapter->net_stats.multicast = adapter->stats.mprc;
3224 adapter->net_stats.collisions = adapter->stats.colc;
3225
3226 /* Rx Errors */
3227
3228 /* RLEC on some newer hardware can be incorrect so build
3229 * our own version based on RUC and ROC */
3230 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3231 adapter->stats.crcerrs + adapter->stats.algnerrc +
3232 adapter->stats.ruc + adapter->stats.roc +
3233 adapter->stats.cexterr;
3234 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3235 adapter->stats.roc;
3236 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3237 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3238 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3239
3240 /* Tx Errors */
3241 adapter->net_stats.tx_errors = adapter->stats.ecol +
3242 adapter->stats.latecol;
3243 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3244 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3245 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3246
3247 /* Tx Dropped needs to be maintained elsewhere */
3248
3249 /* Phy Stats */
3250 if (hw->phy.media_type == e1000_media_type_copper) {
3251 if ((adapter->link_speed == SPEED_1000) &&
3252 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3253 &phy_tmp))) {
3254 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3255 adapter->phy_stats.idle_errors += phy_tmp;
3256 }
3257 }
3258
3259 /* Management Stats */
3260 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3261 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3262 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3263}
3264
3265
3266static irqreturn_t igb_msix_other(int irq, void *data)
3267{
3268 struct net_device *netdev = data;
3269 struct igb_adapter *adapter = netdev_priv(netdev);
3270 struct e1000_hw *hw = &adapter->hw;
844290e5 3271 u32 icr = rd32(E1000_ICR);
9d5c8243 3272
844290e5
PW		 3273 /* reading ICR causes bit 31 of EICR to be cleared */
3274 if (!(icr & E1000_ICR_LSC))
3275 goto no_link_interrupt;
3276 hw->mac.get_link_status = 1;
3277 /* guard against interrupt when we're going down */
3278 if (!test_bit(__IGB_DOWN, &adapter->state))
3279 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3280
9d5c8243
AK		 3281no_link_interrupt:
3282 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3283 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3284
3285 return IRQ_HANDLED;
3286}
3287
3288static irqreturn_t igb_msix_tx(int irq, void *data)
3289{
3290 struct igb_ring *tx_ring = data;
3291 struct igb_adapter *adapter = tx_ring->adapter;
3292 struct e1000_hw *hw = &adapter->hw;
3293
421e02f0 3294#ifdef CONFIG_IGB_DCA
7dfc16fa 3295 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3296 igb_update_tx_dca(tx_ring);
3297#endif
9d5c8243
AK		 3298 tx_ring->total_bytes = 0;
3299 tx_ring->total_packets = 0;
661086df
PWJ		 3300
3301 /* auto mask will automatically reenable the interrupt when we write
3302 * EICS */
3b644cf6 3303 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3304 /* Ring was not completely cleaned, so fire another interrupt */
3305 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3306 else
9d5c8243 3307 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3308
9d5c8243
AK		 3309 return IRQ_HANDLED;
3310}
3311
6eb5a7f1
AD		 3312static void igb_write_itr(struct igb_ring *ring)
3313{
3314 struct e1000_hw *hw = &ring->adapter->hw;
3315 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3316 switch (hw->mac.type) {
3317 case e1000_82576:
3318 wr32(ring->itr_register,
3319 ring->itr_val |
3320 0x80000000);
3321 break;
3322 default:
3323 wr32(ring->itr_register,
3324 ring->itr_val |
3325 (ring->itr_val << 16));
3326 break;
3327 }
3328 ring->set_itr = 0;
3329 }
3330}
3331
9d5c8243
AK		 3332static irqreturn_t igb_msix_rx(int irq, void *data)
3333{
3334 struct igb_ring *rx_ring = data;
3335 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3336
844290e5
PW		 3337 /* Write the ITR value calculated at the end of the
3338 * previous interrupt.
3339 */
9d5c8243 3340
6eb5a7f1 3341 igb_write_itr(rx_ring);
9d5c8243 3342
844290e5
PW		 3343 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3344 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3345
421e02f0 3346#ifdef CONFIG_IGB_DCA
7dfc16fa 3347 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3348 igb_update_rx_dca(rx_ring);
3349#endif
3350 return IRQ_HANDLED;
3351}
3352
421e02f0 3353#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3354static void igb_update_rx_dca(struct igb_ring *rx_ring)
3355{
3356 u32 dca_rxctrl;
3357 struct igb_adapter *adapter = rx_ring->adapter;
3358 struct e1000_hw *hw = &adapter->hw;
3359 int cpu = get_cpu();
3360 int q = rx_ring - adapter->rx_ring;
3361
3362 if (rx_ring->cpu != cpu) {
3363 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3364 if (hw->mac.type == e1000_82576) {
3365 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3366 dca_rxctrl |= dca_get_tag(cpu) <<
3367 E1000_DCA_RXCTRL_CPUID_SHIFT;
3368 } else {
3369 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3370 dca_rxctrl |= dca_get_tag(cpu);
3371 }
fe4506b6
JC		 3372 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3373 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3374 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3375 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3376 rx_ring->cpu = cpu;
3377 }
3378 put_cpu();
3379}
3380
3381static void igb_update_tx_dca(struct igb_ring *tx_ring)
3382{
3383 u32 dca_txctrl;
3384 struct igb_adapter *adapter = tx_ring->adapter;
3385 struct e1000_hw *hw = &adapter->hw;
3386 int cpu = get_cpu();
3387 int q = tx_ring - adapter->tx_ring;
3388
3389 if (tx_ring->cpu != cpu) {
3390 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3391 if (hw->mac.type == e1000_82576) {
3392 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3393 dca_txctrl |= dca_get_tag(cpu) <<
3394 E1000_DCA_TXCTRL_CPUID_SHIFT;
3395 } else {
3396 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3397 dca_txctrl |= dca_get_tag(cpu);
3398 }
fe4506b6
JC		 3399 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3400 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3401 tx_ring->cpu = cpu;
3402 }
3403 put_cpu();
3404}
3405
3406static void igb_setup_dca(struct igb_adapter *adapter)
3407{
3408 int i;
3409
7dfc16fa 3410 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3411 return;
3412
3413 for (i = 0; i < adapter->num_tx_queues; i++) {
3414 adapter->tx_ring[i].cpu = -1;
3415 igb_update_tx_dca(&adapter->tx_ring[i]);
3416 }
3417 for (i = 0; i < adapter->num_rx_queues; i++) {
3418 adapter->rx_ring[i].cpu = -1;
3419 igb_update_rx_dca(&adapter->rx_ring[i]);
3420 }
3421}
3422
3423static int __igb_notify_dca(struct device *dev, void *data)
3424{
3425 struct net_device *netdev = dev_get_drvdata(dev);
3426 struct igb_adapter *adapter = netdev_priv(netdev);
3427 struct e1000_hw *hw = &adapter->hw;
3428 unsigned long event = *(unsigned long *)data;
3429
7dfc16fa
AD		 3430 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3431 goto out;
3432
fe4506b6
JC		 3433 switch (event) {
3434 case DCA_PROVIDER_ADD:
3435 /* if already enabled, don't do it again */
7dfc16fa 3436 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3437 break;
7dfc16fa 3438 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3439 /* Always use CB2 mode, difference is masked
3440 * in the CB driver. */
3441 wr32(E1000_DCA_CTRL, 2);
3442 if (dca_add_requester(dev) == 0) {
3443 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3444 igb_setup_dca(adapter);
3445 break;
3446 }
3447 /* Fall Through since DCA is disabled. */
3448 case DCA_PROVIDER_REMOVE:
7dfc16fa 3449 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3450 /* without this a class_device is left
3451 * hanging around in the sysfs model */
3452 dca_remove_requester(dev);
3453 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3454 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3455 wr32(E1000_DCA_CTRL, 1);
3456 }
3457 break;
3458 }
7dfc16fa 3459out:
fe4506b6 3460 return 0;
9d5c8243
AK		 3461}
3462
fe4506b6
JC		 3463static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3464 void *p)
3465{
3466 int ret_val;
3467
3468 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3469 __igb_notify_dca);
3470
3471 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3472}
421e02f0 3473#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3474
3475/**
3476 * igb_intr_msi - Interrupt Handler
3477 * @irq: interrupt number
3478 * @data: pointer to a network interface device structure
3479 **/
3480static irqreturn_t igb_intr_msi(int irq, void *data)
3481{
3482 struct net_device *netdev = data;
3483 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3484 struct e1000_hw *hw = &adapter->hw;
3485 /* read ICR disables interrupts using IAM */
3486 u32 icr = rd32(E1000_ICR);
3487
6eb5a7f1 3488 igb_write_itr(adapter->rx_ring);
9d5c8243 3489
9d5c8243
AK		 3490 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3491 hw->mac.get_link_status = 1;
3492 if (!test_bit(__IGB_DOWN, &adapter->state))
3493 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3494 }
3495
844290e5 3496 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3497
3498 return IRQ_HANDLED;
3499}
3500
3501/**
3502 * igb_intr - Interrupt Handler
3503 * @irq: interrupt number
3504 * @data: pointer to a network interface device structure
3505 **/
3506static irqreturn_t igb_intr(int irq, void *data)
3507{
3508 struct net_device *netdev = data;
3509 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3510 struct e1000_hw *hw = &adapter->hw;
3511 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3512 * need for the IMC write */
3513 u32 icr = rd32(E1000_ICR);
3514 u32 eicr = 0;
3515 if (!icr)
3516 return IRQ_NONE; /* Not our interrupt */
3517
6eb5a7f1 3518 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3519
3520 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3521 * not set, then the adapter didn't send an interrupt */
3522 if (!(icr & E1000_ICR_INT_ASSERTED))
3523 return IRQ_NONE;
3524
3525 eicr = rd32(E1000_EICR);
3526
3527 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3528 hw->mac.get_link_status = 1;
3529 /* guard against interrupt when we're going down */
3530 if (!test_bit(__IGB_DOWN, &adapter->state))
3531 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3532 }
3533
844290e5 3534 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3535
3536 return IRQ_HANDLED;
3537}
3538
3539/**
661086df
PWJ		 3540 * igb_poll - NAPI Rx polling callback
3541 * @napi: napi polling structure
3542 * @budget: count of how many packets we should handle
9d5c8243 3543 **/
661086df 3544static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3545{
661086df
PWJ		 3546 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3547 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3548 struct net_device *netdev = adapter->netdev;
661086df 3549 int tx_clean_complete, work_done = 0;
9d5c8243 3550
661086df 3551 /* this poll routine only supports one tx and one rx queue */
421e02f0 3552#ifdef CONFIG_IGB_DCA
7dfc16fa 3553 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3554 igb_update_tx_dca(&adapter->tx_ring[0]);
3555#endif
661086df 3556 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3557
421e02f0 3558#ifdef CONFIG_IGB_DCA
7dfc16fa 3559 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3560 igb_update_rx_dca(&adapter->rx_ring[0]);
3561#endif
661086df 3562 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3563
3564 /* If no Tx and not enough Rx work done, exit the polling mode */
3565 if ((tx_clean_complete && (work_done < budget)) ||
3566 !netif_running(netdev)) {
9d5c8243 3567 if (adapter->itr_setting & 3)
6eb5a7f1 3568 igb_set_itr(adapter);
9d5c8243
AK		 3569 netif_rx_complete(netdev, napi);
3570 if (!test_bit(__IGB_DOWN, &adapter->state))
3571 igb_irq_enable(adapter);
3572 return 0;
3573 }
3574
3575 return 1;
3576}
3577
3578static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3579{
3580 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3581 struct igb_adapter *adapter = rx_ring->adapter;
3582 struct e1000_hw *hw = &adapter->hw;
3583 struct net_device *netdev = adapter->netdev;
3584 int work_done = 0;
3585
421e02f0 3586#ifdef CONFIG_IGB_DCA
7dfc16fa 3587 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3588 igb_update_rx_dca(rx_ring);
3589#endif
3b644cf6 3590 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3591
3592
3593 /* If not enough Rx work done, exit the polling mode */
3594 if ((work_done == 0) || !netif_running(netdev)) {
9d5c8243
AK		 3595 netif_rx_complete(netdev, napi);
3596
6eb5a7f1
AD		 3597 if (adapter->itr_setting & 3) {
3598 if (adapter->num_rx_queues == 1)
3599 igb_set_itr(adapter);
3600 else
3601 igb_update_ring_itr(rx_ring);
9d5c8243 3602 }
844290e5
PW		 3603
3604 if (!test_bit(__IGB_DOWN, &adapter->state))
3605 wr32(E1000_EIMS, rx_ring->eims_value);
3606
9d5c8243
AK		 3607 return 0;
3608 }
3609
3610 return 1;
3611}
6d8126f9
AV		 3612
3613static inline u32 get_head(struct igb_ring *tx_ring)
3614{
3615 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3616 return le32_to_cpu(*(volatile __le32 *)end);
3617}
3618
9d5c8243
AK		 3619/**
3620 * igb_clean_tx_irq - Reclaim resources after transmit completes
3621 * @adapter: board private structure
3622 * returns true if ring is completely cleaned
3623 **/
3b644cf6 3624static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3625{
3b644cf6 3626 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3627 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3628 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3629 struct e1000_tx_desc *tx_desc;
3630 struct igb_buffer *buffer_info;
3631 struct sk_buff *skb;
3632 unsigned int i;
3633 u32 head, oldhead;
3634 unsigned int count = 0;
9d5c8243 3635 unsigned int total_bytes = 0, total_packets = 0;
fc7d345d 3636 bool retval = true;
9d5c8243
AK		 3637
3638 rmb();
6d8126f9 3639 head = get_head(tx_ring);
9d5c8243
AK		 3640 i = tx_ring->next_to_clean;
3641 while (1) {
3642 while (i != head) {
9d5c8243
AK		 3643 tx_desc = E1000_TX_DESC(*tx_ring, i);
3644 buffer_info = &tx_ring->buffer_info[i];
3645 skb = buffer_info->skb;
3646
3647 if (skb) {
3648 unsigned int segs, bytecount;
3649 /* gso_segs is currently only valid for tcp */
3650 segs = skb_shinfo(skb)->gso_segs ?: 1;
3651 /* multiply data chunks by size of headers */
3652 bytecount = ((segs - 1) * skb_headlen(skb)) +
3653 skb->len;
3654 total_packets += segs;
3655 total_bytes += bytecount;
3656 }
3657
3658 igb_unmap_and_free_tx_resource(adapter, buffer_info);
9d5c8243
AK		 3659
3660 i++;
3661 if (i == tx_ring->count)
3662 i = 0;
3663
3664 count++;
3665 if (count == IGB_MAX_TX_CLEAN) {
3666 retval = false;
3667 goto done_cleaning;
3668 }
3669 }
3670 oldhead = head;
3671 rmb();
6d8126f9 3672 head = get_head(tx_ring);
9d5c8243
AK		 3673 if (head == oldhead)
3674 goto done_cleaning;
3675 } /* while (1) */
3676
3677done_cleaning:
3678 tx_ring->next_to_clean = i;
3679
fc7d345d 3680 if (unlikely(count &&
9d5c8243
AK		 3681 netif_carrier_ok(netdev) &&
3682 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3683 /* Make sure that anybody stopping the queue after this
3684 * sees the new next_to_clean.
3685 */
3686 smp_mb();
661086df
PWJ		 3687 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3688 !(test_bit(__IGB_DOWN, &adapter->state))) {
3689 netif_wake_subqueue(netdev, tx_ring->queue_index);
3690 ++adapter->restart_queue;
3691 }
9d5c8243
AK		 3692 }
3693
3694 if (tx_ring->detect_tx_hung) {
3695 /* Detect a transmit hang in hardware, this serializes the
3696 * check with the clearing of time_stamp and movement of i */
3697 tx_ring->detect_tx_hung = false;
3698 if (tx_ring->buffer_info[i].time_stamp &&
3699 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3700 (adapter->tx_timeout_factor * HZ))
3701 && !(rd32(E1000_STATUS) &
3702 E1000_STATUS_TXOFF)) {
3703
3704 tx_desc = E1000_TX_DESC(*tx_ring, i);
3705 /* detected Tx unit hang */
3706 dev_err(&adapter->pdev->dev,
3707 "Detected Tx Unit Hang\n"
2d064c06 3708 " Tx Queue <%d>\n"
9d5c8243
AK		 3709 " TDH <%x>\n"
3710 " TDT <%x>\n"
3711 " next_to_use <%x>\n"
3712 " next_to_clean <%x>\n"
3713 " head (WB) <%x>\n"
3714 "buffer_info[next_to_clean]\n"
3715 " time_stamp <%lx>\n"
3716 " jiffies <%lx>\n"
3717 " desc.status <%x>\n",
2d064c06 3718 tx_ring->queue_index,
9d5c8243
AK		 3719 readl(adapter->hw.hw_addr + tx_ring->head),
3720 readl(adapter->hw.hw_addr + tx_ring->tail),
3721 tx_ring->next_to_use,
3722 tx_ring->next_to_clean,
3723 head,
3724 tx_ring->buffer_info[i].time_stamp,
3725 jiffies,
3726 tx_desc->upper.fields.status);
661086df 3727 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3728 }
3729 }
3730 tx_ring->total_bytes += total_bytes;
3731 tx_ring->total_packets += total_packets;
e21ed353
AD		 3732 tx_ring->tx_stats.bytes += total_bytes;
3733 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3734 adapter->net_stats.tx_bytes += total_bytes;
3735 adapter->net_stats.tx_packets += total_packets;
3736 return retval;
3737}
3738
d3352520
AD		 3739#ifdef CONFIG_IGB_LRO
3740 /**
3741 * igb_get_skb_hdr - helper function for LRO header processing
3742 * @skb: pointer to sk_buff to be added to LRO packet
3743 * @iphdr: pointer to ip header structure
3744 * @tcph: pointer to tcp header structure
3745 * @hdr_flags: pointer to header flags
3746 * @priv: pointer to the receive descriptor for the current sk_buff
3747 **/
3748static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3749 u64 *hdr_flags, void *priv)
3750{
3751 union e1000_adv_rx_desc *rx_desc = priv;
3752 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3753 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3754
3755 /* Verify that this is a valid IPv4 TCP packet */
3756 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3757 E1000_RXDADV_PKTTYPE_TCP))
3758 return -1;
3759
3760 /* Set network headers */
3761 skb_reset_network_header(skb);
3762 skb_set_transport_header(skb, ip_hdrlen(skb));
3763 *iphdr = ip_hdr(skb);
3764 *tcph = tcp_hdr(skb);
3765 *hdr_flags = LRO_IPV4 | LRO_TCP;
3766
3767 return 0;
3768
3769}
3770#endif /* CONFIG_IGB_LRO */
9d5c8243
AK		 3771
3772/**
3773 * igb_receive_skb - helper function to handle rx indications
d3352520 3774 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3775 * @status: descriptor status field as written by hardware
3776 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3777 * @skb: pointer to sk_buff to be indicated to stack
3778 **/
d3352520
AD		 3779static void igb_receive_skb(struct igb_ring *ring, u8 status,
3780 union e1000_adv_rx_desc * rx_desc,
3781 struct sk_buff *skb)
3782{
3783 struct igb_adapter * adapter = ring->adapter;
3784 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3785
3786#ifdef CONFIG_IGB_LRO
3787 if (adapter->netdev->features & NETIF_F_LRO &&
3788 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3789 if (vlan_extracted)
3790 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3791 adapter->vlgrp,
3792 le16_to_cpu(rx_desc->wb.upper.vlan),
3793 rx_desc);
3794 else
3795 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3796 ring->lro_used = 1;
3797 } else {
3798#endif
3799 if (vlan_extracted)
3800 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3801 le16_to_cpu(rx_desc->wb.upper.vlan));
3802 else
3803
3804 netif_receive_skb(skb);
3805#ifdef CONFIG_IGB_LRO
3806 }
3807#endif
9d5c8243
AK		 3808}
3809
3810
3811static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3812 u32 status_err, struct sk_buff *skb)
3813{
3814 skb->ip_summed = CHECKSUM_NONE;
3815
3816 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3817 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3818 return;
3819 /* TCP/UDP checksum error bit is set */
3820 if (status_err &
3821 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3822 /* let the stack verify checksum errors */
3823 adapter->hw_csum_err++;
3824 return;
3825 }
3826 /* It must be a TCP or UDP packet with a valid checksum */
3827 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3828 skb->ip_summed = CHECKSUM_UNNECESSARY;
3829
3830 adapter->hw_csum_good++;
3831}
3832
3b644cf6
MW		 3833static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3834 int *work_done, int budget)
9d5c8243 3835{
3b644cf6 3836 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3837 struct net_device *netdev = adapter->netdev;
3838 struct pci_dev *pdev = adapter->pdev;
3839 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3840 struct igb_buffer *buffer_info , *next_buffer;
3841 struct sk_buff *skb;
bf36c1a0 3842 unsigned int i;
9d5c8243
AK		 3843 u32 length, hlen, staterr;
3844 bool cleaned = false;
3845 int cleaned_count = 0;
3846 unsigned int total_bytes = 0, total_packets = 0;
3847
3848 i = rx_ring->next_to_clean;
3849 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3850 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3851
3852 while (staterr & E1000_RXD_STAT_DD) {
3853 if (*work_done >= budget)
3854 break;
3855 (*work_done)++;
3856 buffer_info = &rx_ring->buffer_info[i];
3857
3858 /* HW will not DMA in data larger than the given buffer, even
3859 * if it parses the (NFS, of course) header to be larger. In
3860 * that case, it fills the header buffer and spills the rest
3861 * into the page.
3862 */
7deb07b1
AV		 3863 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3864 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3865 if (hlen > adapter->rx_ps_hdr_size)
3866 hlen = adapter->rx_ps_hdr_size;
3867
3868 length = le16_to_cpu(rx_desc->wb.upper.length);
3869 cleaned = true;
3870 cleaned_count++;
3871
bf36c1a0
AD		 3872 skb = buffer_info->skb;
3873 prefetch(skb->data - NET_IP_ALIGN);
3874 buffer_info->skb = NULL;
3875 if (!adapter->rx_ps_hdr_size) {
3876 pci_unmap_single(pdev, buffer_info->dma,
3877 adapter->rx_buffer_len +
3878 NET_IP_ALIGN,
3879 PCI_DMA_FROMDEVICE);
3880 skb_put(skb, length);
3881 goto send_up;
9d5c8243
AK		 3882 }
3883
bf36c1a0
AD		 3884 if (!skb_shinfo(skb)->nr_frags) {
3885 pci_unmap_single(pdev, buffer_info->dma,
3886 adapter->rx_ps_hdr_size +
3887 NET_IP_ALIGN,
3888 PCI_DMA_FROMDEVICE);
3889 skb_put(skb, hlen);
3890 }
3891
3892 if (length) {
9d5c8243 3893 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3894 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3895 buffer_info->page_dma = 0;
bf36c1a0
AD		 3896
3897 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3898 buffer_info->page,
3899 buffer_info->page_offset,
3900 length);
3901
3902 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3903 (page_count(buffer_info->page) != 1))
3904 buffer_info->page = NULL;
3905 else
3906 get_page(buffer_info->page);
9d5c8243
AK		 3907
3908 skb->len += length;
3909 skb->data_len += length;
9d5c8243 3910
bf36c1a0 3911 skb->truesize += length;
9d5c8243
AK		 3912 }
3913send_up:
9d5c8243
AK		 3914 i++;
3915 if (i == rx_ring->count)
3916 i = 0;
3917 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3918 prefetch(next_rxd);
3919 next_buffer = &rx_ring->buffer_info[i];
3920
bf36c1a0
AD		 3921 if (!(staterr & E1000_RXD_STAT_EOP)) {
3922 buffer_info->skb = xchg(&next_buffer->skb, skb);
3923 buffer_info->dma = xchg(&next_buffer->dma, 0);
3924 goto next_desc;
3925 }
3926
9d5c8243
AK		 3927 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3928 dev_kfree_skb_irq(skb);
3929 goto next_desc;
3930 }
9d5c8243
AK		 3931
3932 total_bytes += skb->len;
3933 total_packets++;
3934
3935 igb_rx_checksum_adv(adapter, staterr, skb);
3936
3937 skb->protocol = eth_type_trans(skb, netdev);
3938
d3352520 3939 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243
AK		 3940
3941 netdev->last_rx = jiffies;
3942
3943next_desc:
3944 rx_desc->wb.upper.status_error = 0;
3945
3946 /* return some buffers to hardware, one at a time is too slow */
3947 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3948 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3949 cleaned_count = 0;
3950 }
3951
3952 /* use prefetched values */
3953 rx_desc = next_rxd;
3954 buffer_info = next_buffer;
3955
3956 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3957 }
bf36c1a0 3958
9d5c8243
AK		 3959 rx_ring->next_to_clean = i;
3960 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3961
d3352520
AD		 3962#ifdef CONFIG_IGB_LRO
3963 if (rx_ring->lro_used) {
3964 lro_flush_all(&rx_ring->lro_mgr);
3965 rx_ring->lro_used = 0;
3966 }
3967#endif
3968
9d5c8243 3969 if (cleaned_count)
3b644cf6 3970 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3971
3972 rx_ring->total_packets += total_packets;
3973 rx_ring->total_bytes += total_bytes;
3974 rx_ring->rx_stats.packets += total_packets;
3975 rx_ring->rx_stats.bytes += total_bytes;
3976 adapter->net_stats.rx_bytes += total_bytes;
3977 adapter->net_stats.rx_packets += total_packets;
3978 return cleaned;
3979}
3980
3981
3982/**
3983 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3984 * @adapter: address of board private structure
3985 **/
3b644cf6 3986static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3987 int cleaned_count)
3988{
3b644cf6 3989 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3990 struct net_device *netdev = adapter->netdev;
3991 struct pci_dev *pdev = adapter->pdev;
3992 union e1000_adv_rx_desc *rx_desc;
3993 struct igb_buffer *buffer_info;
3994 struct sk_buff *skb;
3995 unsigned int i;
3996
3997 i = rx_ring->next_to_use;
3998 buffer_info = &rx_ring->buffer_info[i];
3999
4000 while (cleaned_count--) {
4001 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4002
bf36c1a0 4003 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4004 if (!buffer_info->page) {
bf36c1a0
AD		 4005 buffer_info->page = alloc_page(GFP_ATOMIC);
4006 if (!buffer_info->page) {
4007 adapter->alloc_rx_buff_failed++;
4008 goto no_buffers;
4009 }
4010 buffer_info->page_offset = 0;
4011 } else {
4012 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4013 }
4014 buffer_info->page_dma =
4015 pci_map_page(pdev,
4016 buffer_info->page,
bf36c1a0
AD		 4017 buffer_info->page_offset,
4018 PAGE_SIZE / 2,
9d5c8243
AK		 4019 PCI_DMA_FROMDEVICE);
4020 }
4021
4022 if (!buffer_info->skb) {
4023 int bufsz;
4024
4025 if (adapter->rx_ps_hdr_size)
4026 bufsz = adapter->rx_ps_hdr_size;
4027 else
4028 bufsz = adapter->rx_buffer_len;
4029 bufsz += NET_IP_ALIGN;
4030 skb = netdev_alloc_skb(netdev, bufsz);
4031
4032 if (!skb) {
4033 adapter->alloc_rx_buff_failed++;
4034 goto no_buffers;
4035 }
4036
4037 /* Make buffer alignment 2 beyond a 16 byte boundary
4038 * this will result in a 16 byte aligned IP header after
4039 * the 14 byte MAC header is removed
4040 */
4041 skb_reserve(skb, NET_IP_ALIGN);
4042
4043 buffer_info->skb = skb;
4044 buffer_info->dma = pci_map_single(pdev, skb->data,
4045 bufsz,
4046 PCI_DMA_FROMDEVICE);
4047
4048 }
4049 /* Refresh the desc even if buffer_addrs didn't change because
4050 * each write-back erases this info. */
4051 if (adapter->rx_ps_hdr_size) {
4052 rx_desc->read.pkt_addr =
4053 cpu_to_le64(buffer_info->page_dma);
4054 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4055 } else {
4056 rx_desc->read.pkt_addr =
4057 cpu_to_le64(buffer_info->dma);
4058 rx_desc->read.hdr_addr = 0;
4059 }
4060
4061 i++;
4062 if (i == rx_ring->count)
4063 i = 0;
4064 buffer_info = &rx_ring->buffer_info[i];
4065 }
4066
4067no_buffers:
4068 if (rx_ring->next_to_use != i) {
4069 rx_ring->next_to_use = i;
4070 if (i == 0)
4071 i = (rx_ring->count - 1);
4072 else
4073 i--;
4074
4075 /* Force memory writes to complete before letting h/w
4076 * know there are new descriptors to fetch. (Only
4077 * applicable for weak-ordered memory model archs,
4078 * such as IA-64). */
4079 wmb();
4080 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4081 }
4082}
4083
4084/**
4085 * igb_mii_ioctl -
4086 * @netdev:
4087 * @ifreq:
4088 * @cmd:
4089 **/
4090static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4091{
4092 struct igb_adapter *adapter = netdev_priv(netdev);
4093 struct mii_ioctl_data *data = if_mii(ifr);
4094
4095 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4096 return -EOPNOTSUPP;
4097
4098 switch (cmd) {
4099 case SIOCGMIIPHY:
4100 data->phy_id = adapter->hw.phy.addr;
4101 break;
4102 case SIOCGMIIREG:
4103 if (!capable(CAP_NET_ADMIN))
4104 return -EPERM;
4105 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
4106 data->reg_num
4107 & 0x1F, &data->val_out))
4108 return -EIO;
4109 break;
4110 case SIOCSMIIREG:
4111 default:
4112 return -EOPNOTSUPP;
4113 }
4114 return 0;
4115}
4116
4117/**
4118 * igb_ioctl -
4119 * @netdev:
4120 * @ifreq:
4121 * @cmd:
4122 **/
4123static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4124{
4125 switch (cmd) {
4126 case SIOCGMIIPHY:
4127 case SIOCGMIIREG:
4128 case SIOCSMIIREG:
4129 return igb_mii_ioctl(netdev, ifr, cmd);
4130 default:
4131 return -EOPNOTSUPP;
4132 }
4133}
4134
4135static void igb_vlan_rx_register(struct net_device *netdev,
4136 struct vlan_group *grp)
4137{
4138 struct igb_adapter *adapter = netdev_priv(netdev);
4139 struct e1000_hw *hw = &adapter->hw;
4140 u32 ctrl, rctl;
4141
4142 igb_irq_disable(adapter);
4143 adapter->vlgrp = grp;
4144
4145 if (grp) {
4146 /* enable VLAN tag insert/strip */
4147 ctrl = rd32(E1000_CTRL);
4148 ctrl |= E1000_CTRL_VME;
4149 wr32(E1000_CTRL, ctrl);
4150
4151 /* enable VLAN receive filtering */
4152 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4153 rctl &= ~E1000_RCTL_CFIEN;
4154 wr32(E1000_RCTL, rctl);
4155 igb_update_mng_vlan(adapter);
4156 wr32(E1000_RLPML,
4157 adapter->max_frame_size + VLAN_TAG_SIZE);
4158 } else {
4159 /* disable VLAN tag insert/strip */
4160 ctrl = rd32(E1000_CTRL);
4161 ctrl &= ~E1000_CTRL_VME;
4162 wr32(E1000_CTRL, ctrl);
4163
9d5c8243
AK		 4164 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4165 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4166 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4167 }
4168 wr32(E1000_RLPML,
4169 adapter->max_frame_size);
4170 }
4171
4172 if (!test_bit(__IGB_DOWN, &adapter->state))
4173 igb_irq_enable(adapter);
4174}
4175
4176static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4177{
4178 struct igb_adapter *adapter = netdev_priv(netdev);
4179 struct e1000_hw *hw = &adapter->hw;
4180 u32 vfta, index;
4181
4182 if ((adapter->hw.mng_cookie.status &
4183 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4184 (vid == adapter->mng_vlan_id))
4185 return;
4186 /* add VID to filter table */
4187 index = (vid >> 5) & 0x7F;
4188 vfta = array_rd32(E1000_VFTA, index);
4189 vfta |= (1 << (vid & 0x1F));
4190 igb_write_vfta(&adapter->hw, index, vfta);
4191}
4192
4193static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4194{
4195 struct igb_adapter *adapter = netdev_priv(netdev);
4196 struct e1000_hw *hw = &adapter->hw;
4197 u32 vfta, index;
4198
4199 igb_irq_disable(adapter);
4200 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4201
4202 if (!test_bit(__IGB_DOWN, &adapter->state))
4203 igb_irq_enable(adapter);
4204
4205 if ((adapter->hw.mng_cookie.status &
4206 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4207 (vid == adapter->mng_vlan_id)) {
4208 /* release control to f/w */
4209 igb_release_hw_control(adapter);
4210 return;
4211 }
4212
4213 /* remove VID from filter table */
4214 index = (vid >> 5) & 0x7F;
4215 vfta = array_rd32(E1000_VFTA, index);
4216 vfta &= ~(1 << (vid & 0x1F));
4217 igb_write_vfta(&adapter->hw, index, vfta);
4218}
4219
4220static void igb_restore_vlan(struct igb_adapter *adapter)
4221{
4222 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4223
4224 if (adapter->vlgrp) {
4225 u16 vid;
4226 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4227 if (!vlan_group_get_device(adapter->vlgrp, vid))
4228 continue;
4229 igb_vlan_rx_add_vid(adapter->netdev, vid);
4230 }
4231 }
4232}
4233
4234int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4235{
4236 struct e1000_mac_info *mac = &adapter->hw.mac;
4237
4238 mac->autoneg = 0;
4239
4240 /* Fiber NICs only allow 1000 gbps Full duplex */
4241 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4242 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4243 dev_err(&adapter->pdev->dev,
4244 "Unsupported Speed/Duplex configuration\n");
4245 return -EINVAL;
4246 }
4247
4248 switch (spddplx) {
4249 case SPEED_10 + DUPLEX_HALF:
4250 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4251 break;
4252 case SPEED_10 + DUPLEX_FULL:
4253 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4254 break;
4255 case SPEED_100 + DUPLEX_HALF:
4256 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4257 break;
4258 case SPEED_100 + DUPLEX_FULL:
4259 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4260 break;
4261 case SPEED_1000 + DUPLEX_FULL:
4262 mac->autoneg = 1;
4263 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4264 break;
4265 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4266 default:
4267 dev_err(&adapter->pdev->dev,
4268 "Unsupported Speed/Duplex configuration\n");
4269 return -EINVAL;
4270 }
4271 return 0;
4272}
4273
4274
4275static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4276{
4277 struct net_device *netdev = pci_get_drvdata(pdev);
4278 struct igb_adapter *adapter = netdev_priv(netdev);
4279 struct e1000_hw *hw = &adapter->hw;
2d064c06 4280 u32 ctrl, rctl, status;
9d5c8243
AK		 4281 u32 wufc = adapter->wol;
4282#ifdef CONFIG_PM
4283 int retval = 0;
4284#endif
4285
4286 netif_device_detach(netdev);
4287
a88f10ec
AD		 4288 if (netif_running(netdev))
4289 igb_close(netdev);
4290
4291 igb_reset_interrupt_capability(adapter);
4292
4293 igb_free_queues(adapter);
9d5c8243
AK		 4294
4295#ifdef CONFIG_PM
4296 retval = pci_save_state(pdev);
4297 if (retval)
4298 return retval;
4299#endif
4300
4301 status = rd32(E1000_STATUS);
4302 if (status & E1000_STATUS_LU)
4303 wufc &= ~E1000_WUFC_LNKC;
4304
4305 if (wufc) {
4306 igb_setup_rctl(adapter);
4307 igb_set_multi(netdev);
4308
4309 /* turn on all-multi mode if wake on multicast is enabled */
4310 if (wufc & E1000_WUFC_MC) {
4311 rctl = rd32(E1000_RCTL);
4312 rctl |= E1000_RCTL_MPE;
4313 wr32(E1000_RCTL, rctl);
4314 }
4315
4316 ctrl = rd32(E1000_CTRL);
4317 /* advertise wake from D3Cold */
4318 #define E1000_CTRL_ADVD3WUC 0x00100000
4319 /* phy power management enable */
4320 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4321 ctrl |= E1000_CTRL_ADVD3WUC;
4322 wr32(E1000_CTRL, ctrl);
4323
9d5c8243
AK		 4324 /* Allow time for pending master requests to run */
4325 igb_disable_pcie_master(&adapter->hw);
4326
4327 wr32(E1000_WUC, E1000_WUC_PME_EN);
4328 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4329 } else {
4330 wr32(E1000_WUC, 0);
4331 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4332 }
4333
2d064c06
AD		 4334 /* make sure adapter isn't asleep if manageability/wol is enabled */
4335 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4336 pci_enable_wake(pdev, PCI_D3hot, 1);
4337 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4338 } else {
4339 igb_shutdown_fiber_serdes_link_82575(hw);
4340 pci_enable_wake(pdev, PCI_D3hot, 0);
4341 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4342 }
4343
4344 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4345 * would have already happened in close and is redundant. */
4346 igb_release_hw_control(adapter);
4347
4348 pci_disable_device(pdev);
4349
4350 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4351
4352 return 0;
4353}
4354
4355#ifdef CONFIG_PM
4356static int igb_resume(struct pci_dev *pdev)
4357{
4358 struct net_device *netdev = pci_get_drvdata(pdev);
4359 struct igb_adapter *adapter = netdev_priv(netdev);
4360 struct e1000_hw *hw = &adapter->hw;
4361 u32 err;
4362
4363 pci_set_power_state(pdev, PCI_D0);
4364 pci_restore_state(pdev);
42bfd33a
TI		 4365
4366 if (adapter->need_ioport)
4367 err = pci_enable_device(pdev);
4368 else
4369 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4370 if (err) {
4371 dev_err(&pdev->dev,
4372 "igb: Cannot enable PCI device from suspend\n");
4373 return err;
4374 }
4375 pci_set_master(pdev);
4376
4377 pci_enable_wake(pdev, PCI_D3hot, 0);
4378 pci_enable_wake(pdev, PCI_D3cold, 0);
4379
a88f10ec
AD		 4380 igb_set_interrupt_capability(adapter);
4381
4382 if (igb_alloc_queues(adapter)) {
4383 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4384 return -ENOMEM;
9d5c8243
AK		 4385 }
4386
4387 /* e1000_power_up_phy(adapter); */
4388
4389 igb_reset(adapter);
4390 wr32(E1000_WUS, ~0);
4391
a88f10ec
AD		 4392 if (netif_running(netdev)) {
4393 err = igb_open(netdev);
4394 if (err)
4395 return err;
4396 }
9d5c8243
AK		 4397
4398 netif_device_attach(netdev);
4399
4400 /* let the f/w know that the h/w is now under the control of the
4401 * driver. */
4402 igb_get_hw_control(adapter);
4403
4404 return 0;
4405}
4406#endif
4407
4408static void igb_shutdown(struct pci_dev *pdev)
4409{
4410 igb_suspend(pdev, PMSG_SUSPEND);
4411}
4412
4413#ifdef CONFIG_NET_POLL_CONTROLLER
4414/*
4415 * Polling 'interrupt' - used by things like netconsole to send skbs
4416 * without having to re-enable interrupts. It's not called while
4417 * the interrupt routine is executing.
4418 */
4419static void igb_netpoll(struct net_device *netdev)
4420{
4421 struct igb_adapter *adapter = netdev_priv(netdev);
4422 int i;
4423 int work_done = 0;
4424
4425 igb_irq_disable(adapter);
7dfc16fa
AD		 4426 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4427
9d5c8243 4428 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4429 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4430
4431 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4432 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4433 &work_done,
4434 adapter->rx_ring[i].napi.weight);
4435
7dfc16fa 4436 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4437 igb_irq_enable(adapter);
4438}
4439#endif /* CONFIG_NET_POLL_CONTROLLER */
4440
4441/**
4442 * igb_io_error_detected - called when PCI error is detected
4443 * @pdev: Pointer to PCI device
4444 * @state: The current pci connection state
4445 *
4446 * This function is called after a PCI bus error affecting
4447 * this device has been detected.
4448 */
4449static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4450 pci_channel_state_t state)
4451{
4452 struct net_device *netdev = pci_get_drvdata(pdev);
4453 struct igb_adapter *adapter = netdev_priv(netdev);
4454
4455 netif_device_detach(netdev);
4456
4457 if (netif_running(netdev))
4458 igb_down(adapter);
4459 pci_disable_device(pdev);
4460
4461 /* Request a slot slot reset. */
4462 return PCI_ERS_RESULT_NEED_RESET;
4463}
4464
4465/**
4466 * igb_io_slot_reset - called after the pci bus has been reset.
4467 * @pdev: Pointer to PCI device
4468 *
4469 * Restart the card from scratch, as if from a cold-boot. Implementation
4470 * resembles the first-half of the igb_resume routine.
4471 */
4472static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4473{
4474 struct net_device *netdev = pci_get_drvdata(pdev);
4475 struct igb_adapter *adapter = netdev_priv(netdev);
4476 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4477 int err;
9d5c8243 4478
42bfd33a
TI		 4479 if (adapter->need_ioport)
4480 err = pci_enable_device(pdev);
4481 else
4482 err = pci_enable_device_mem(pdev);
4483 if (err) {
9d5c8243
AK		 4484 dev_err(&pdev->dev,
4485 "Cannot re-enable PCI device after reset.\n");
4486 return PCI_ERS_RESULT_DISCONNECT;
4487 }
4488 pci_set_master(pdev);
c682fc23 4489 pci_restore_state(pdev);
9d5c8243
AK		 4490
4491 pci_enable_wake(pdev, PCI_D3hot, 0);
4492 pci_enable_wake(pdev, PCI_D3cold, 0);
4493
4494 igb_reset(adapter);
4495 wr32(E1000_WUS, ~0);
4496
4497 return PCI_ERS_RESULT_RECOVERED;
4498}
4499
4500/**
4501 * igb_io_resume - called when traffic can start flowing again.
4502 * @pdev: Pointer to PCI device
4503 *
4504 * This callback is called when the error recovery driver tells us that
4505 * its OK to resume normal operation. Implementation resembles the
4506 * second-half of the igb_resume routine.
4507 */
4508static void igb_io_resume(struct pci_dev *pdev)
4509{
4510 struct net_device *netdev = pci_get_drvdata(pdev);
4511 struct igb_adapter *adapter = netdev_priv(netdev);
4512
9d5c8243
AK		 4513 if (netif_running(netdev)) {
4514 if (igb_up(adapter)) {
4515 dev_err(&pdev->dev, "igb_up failed after reset\n");
4516 return;
4517 }
4518 }
4519
4520 netif_device_attach(netdev);
4521
4522 /* let the f/w know that the h/w is now under the control of the
4523 * driver. */
4524 igb_get_hw_control(adapter);
4525
4526}
4527
4528/* igb_main.c */
Linux 6.x block layer and io_uring tree(s)