Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. | |
3 | * | |
4 | * Note: This driver is a cleanroom reimplementation based on reverse | |
5 | * engineered documentation written by Carl-Daniel Hailfinger | |
87046e50 | 6 | * and Andrew de Quincey. |
1da177e4 LT |
7 | * |
8 | * NVIDIA, nForce and other NVIDIA marks are trademarks or registered | |
9 | * trademarks of NVIDIA Corporation in the United States and other | |
10 | * countries. | |
11 | * | |
1836098f | 12 | * Copyright (C) 2003,4,5 Manfred Spraul |
1da177e4 LT |
13 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
14 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane | |
15 | * IRQ rate fixes, bigendian fixes, cleanups, verification) | |
f1405d32 | 16 | * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
31 | * | |
1da177e4 LT |
32 | * Known bugs: |
33 | * We suspect that on some hardware no TX done interrupts are generated. | |
34 | * This means recovery from netif_stop_queue only happens if the hw timer | |
35 | * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) | |
36 | * and the timer is active in the IRQMask, or if a rx packet arrives by chance. | |
37 | * If your hardware reliably generates tx done interrupts, then you can remove | |
38 | * DEV_NEED_TIMERIRQ from the driver_data flags. | |
39 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | |
40 | * superfluous timer interrupts from the nic. | |
41 | */ | |
294a554e JP |
42 | |
43 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
44 | ||
3e1a3ce2 | 45 | #define FORCEDETH_VERSION "0.64" |
1da177e4 LT |
46 | #define DRV_NAME "forcedeth" |
47 | ||
48 | #include <linux/module.h> | |
49 | #include <linux/types.h> | |
50 | #include <linux/pci.h> | |
51 | #include <linux/interrupt.h> | |
52 | #include <linux/netdevice.h> | |
53 | #include <linux/etherdevice.h> | |
54 | #include <linux/delay.h> | |
d43c36dc | 55 | #include <linux/sched.h> |
1da177e4 LT |
56 | #include <linux/spinlock.h> |
57 | #include <linux/ethtool.h> | |
58 | #include <linux/timer.h> | |
59 | #include <linux/skbuff.h> | |
60 | #include <linux/mii.h> | |
61 | #include <linux/random.h> | |
62 | #include <linux/init.h> | |
22c6d143 | 63 | #include <linux/if_vlan.h> |
910638ae | 64 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 65 | #include <linux/slab.h> |
5504e139 SJ |
66 | #include <linux/uaccess.h> |
67 | #include <linux/io.h> | |
1da177e4 LT |
68 | |
69 | #include <asm/irq.h> | |
1da177e4 LT |
70 | #include <asm/system.h> |
71 | ||
bea3348e SH |
72 | #define TX_WORK_PER_LOOP 64 |
73 | #define RX_WORK_PER_LOOP 64 | |
1da177e4 LT |
74 | |
75 | /* | |
76 | * Hardware access: | |
77 | */ | |
78 | ||
3c2e1c11 AA |
79 | #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */ |
80 | #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */ | |
81 | #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */ | |
82 | #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */ | |
83 | #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */ | |
84 | #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */ | |
85 | #define DEV_HAS_MSI 0x0000040 /* device supports MSI */ | |
86 | #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */ | |
87 | #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */ | |
88 | #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */ | |
7b5e078c MD |
89 | #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */ |
90 | #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */ | |
91 | #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */ | |
92 | #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */ | |
3c2e1c11 AA |
93 | #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */ |
94 | #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */ | |
95 | #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */ | |
96 | #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */ | |
97 | #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */ | |
98 | #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */ | |
99 | #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */ | |
100 | #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */ | |
101 | #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */ | |
102 | #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */ | |
103 | #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */ | |
104 | #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */ | |
105 | #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */ | |
1da177e4 LT |
106 | |
107 | enum { | |
108 | NvRegIrqStatus = 0x000, | |
109 | #define NVREG_IRQSTAT_MIIEVENT 0x040 | |
daa91a9d | 110 | #define NVREG_IRQSTAT_MASK 0x83ff |
1da177e4 LT |
111 | NvRegIrqMask = 0x004, |
112 | #define NVREG_IRQ_RX_ERROR 0x0001 | |
113 | #define NVREG_IRQ_RX 0x0002 | |
114 | #define NVREG_IRQ_RX_NOBUF 0x0004 | |
115 | #define NVREG_IRQ_TX_ERR 0x0008 | |
c2dba06d | 116 | #define NVREG_IRQ_TX_OK 0x0010 |
1da177e4 LT |
117 | #define NVREG_IRQ_TIMER 0x0020 |
118 | #define NVREG_IRQ_LINK 0x0040 | |
d33a73c8 AA |
119 | #define NVREG_IRQ_RX_FORCED 0x0080 |
120 | #define NVREG_IRQ_TX_FORCED 0x0100 | |
daa91a9d | 121 | #define NVREG_IRQ_RECOVER_ERROR 0x8200 |
a971c324 | 122 | #define NVREG_IRQMASK_THROUGHPUT 0x00df |
096a458c | 123 | #define NVREG_IRQMASK_CPU 0x0060 |
d33a73c8 AA |
124 | #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
125 | #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) | |
c5cf9101 | 126 | #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) |
c2dba06d | 127 | |
1da177e4 LT |
128 | NvRegUnknownSetupReg6 = 0x008, |
129 | #define NVREG_UNKSETUP6_VAL 3 | |
130 | ||
131 | /* | |
132 | * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic | |
133 | * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms | |
134 | */ | |
135 | NvRegPollingInterval = 0x00c, | |
6cef67a0 | 136 | #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */ |
a971c324 | 137 | #define NVREG_POLL_DEFAULT_CPU 13 |
d33a73c8 AA |
138 | NvRegMSIMap0 = 0x020, |
139 | NvRegMSIMap1 = 0x024, | |
140 | NvRegMSIIrqMask = 0x030, | |
141 | #define NVREG_MSI_VECTOR_0_ENABLED 0x01 | |
1da177e4 | 142 | NvRegMisc1 = 0x080, |
eb91f61b | 143 | #define NVREG_MISC1_PAUSE_TX 0x01 |
1da177e4 LT |
144 | #define NVREG_MISC1_HD 0x02 |
145 | #define NVREG_MISC1_FORCE 0x3b0f3c | |
146 | ||
0a62677b | 147 | NvRegMacReset = 0x34, |
86a0f043 | 148 | #define NVREG_MAC_RESET_ASSERT 0x0F3 |
1da177e4 LT |
149 | NvRegTransmitterControl = 0x084, |
150 | #define NVREG_XMITCTL_START 0x01 | |
7e680c22 AA |
151 | #define NVREG_XMITCTL_MGMT_ST 0x40000000 |
152 | #define NVREG_XMITCTL_SYNC_MASK 0x000f0000 | |
153 | #define NVREG_XMITCTL_SYNC_NOT_READY 0x0 | |
154 | #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 | |
155 | #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 | |
156 | #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 | |
157 | #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 | |
158 | #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 | |
159 | #define NVREG_XMITCTL_HOST_LOADED 0x00004000 | |
f35723ec | 160 | #define NVREG_XMITCTL_TX_PATH_EN 0x01000000 |
cac1c52c AA |
161 | #define NVREG_XMITCTL_DATA_START 0x00100000 |
162 | #define NVREG_XMITCTL_DATA_READY 0x00010000 | |
163 | #define NVREG_XMITCTL_DATA_ERROR 0x00020000 | |
1da177e4 LT |
164 | NvRegTransmitterStatus = 0x088, |
165 | #define NVREG_XMITSTAT_BUSY 0x01 | |
166 | ||
167 | NvRegPacketFilterFlags = 0x8c, | |
eb91f61b AA |
168 | #define NVREG_PFF_PAUSE_RX 0x08 |
169 | #define NVREG_PFF_ALWAYS 0x7F0000 | |
1da177e4 LT |
170 | #define NVREG_PFF_PROMISC 0x80 |
171 | #define NVREG_PFF_MYADDR 0x20 | |
9589c77a | 172 | #define NVREG_PFF_LOOPBACK 0x10 |
1da177e4 LT |
173 | |
174 | NvRegOffloadConfig = 0x90, | |
175 | #define NVREG_OFFLOAD_HOMEPHY 0x601 | |
176 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE | |
177 | NvRegReceiverControl = 0x094, | |
178 | #define NVREG_RCVCTL_START 0x01 | |
f35723ec | 179 | #define NVREG_RCVCTL_RX_PATH_EN 0x01000000 |
1da177e4 LT |
180 | NvRegReceiverStatus = 0x98, |
181 | #define NVREG_RCVSTAT_BUSY 0x01 | |
182 | ||
a433686c AA |
183 | NvRegSlotTime = 0x9c, |
184 | #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 | |
185 | #define NVREG_SLOTTIME_10_100_FULL 0x00007f00 | |
78aea4fc | 186 | #define NVREG_SLOTTIME_1000_FULL 0x0003ff00 |
a433686c | 187 | #define NVREG_SLOTTIME_HALF 0x0000ff00 |
78aea4fc | 188 | #define NVREG_SLOTTIME_DEFAULT 0x00007f00 |
a433686c | 189 | #define NVREG_SLOTTIME_MASK 0x000000ff |
1da177e4 | 190 | |
9744e218 | 191 | NvRegTxDeferral = 0xA0, |
fd9b558c AA |
192 | #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
193 | #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f | |
194 | #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f | |
195 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f | |
196 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f | |
197 | #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000 | |
9744e218 AA |
198 | NvRegRxDeferral = 0xA4, |
199 | #define NVREG_RX_DEFERRAL_DEFAULT 0x16 | |
1da177e4 LT |
200 | NvRegMacAddrA = 0xA8, |
201 | NvRegMacAddrB = 0xAC, | |
202 | NvRegMulticastAddrA = 0xB0, | |
203 | #define NVREG_MCASTADDRA_FORCE 0x01 | |
204 | NvRegMulticastAddrB = 0xB4, | |
205 | NvRegMulticastMaskA = 0xB8, | |
bb9a4fd1 | 206 | #define NVREG_MCASTMASKA_NONE 0xffffffff |
1da177e4 | 207 | NvRegMulticastMaskB = 0xBC, |
bb9a4fd1 | 208 | #define NVREG_MCASTMASKB_NONE 0xffff |
1da177e4 LT |
209 | |
210 | NvRegPhyInterface = 0xC0, | |
211 | #define PHY_RGMII 0x10000000 | |
a433686c AA |
212 | NvRegBackOffControl = 0xC4, |
213 | #define NVREG_BKOFFCTRL_DEFAULT 0x70000000 | |
214 | #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff | |
215 | #define NVREG_BKOFFCTRL_SELECT 24 | |
216 | #define NVREG_BKOFFCTRL_GEAR 12 | |
1da177e4 LT |
217 | |
218 | NvRegTxRingPhysAddr = 0x100, | |
219 | NvRegRxRingPhysAddr = 0x104, | |
220 | NvRegRingSizes = 0x108, | |
221 | #define NVREG_RINGSZ_TXSHIFT 0 | |
222 | #define NVREG_RINGSZ_RXSHIFT 16 | |
5070d340 AA |
223 | NvRegTransmitPoll = 0x10c, |
224 | #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 | |
1da177e4 LT |
225 | NvRegLinkSpeed = 0x110, |
226 | #define NVREG_LINKSPEED_FORCE 0x10000 | |
227 | #define NVREG_LINKSPEED_10 1000 | |
228 | #define NVREG_LINKSPEED_100 100 | |
229 | #define NVREG_LINKSPEED_1000 50 | |
230 | #define NVREG_LINKSPEED_MASK (0xFFF) | |
231 | NvRegUnknownSetupReg5 = 0x130, | |
232 | #define NVREG_UNKSETUP5_BIT31 (1<<31) | |
95d161cb AA |
233 | NvRegTxWatermark = 0x13c, |
234 | #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 | |
235 | #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 | |
236 | #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 | |
1da177e4 LT |
237 | NvRegTxRxControl = 0x144, |
238 | #define NVREG_TXRXCTL_KICK 0x0001 | |
239 | #define NVREG_TXRXCTL_BIT1 0x0002 | |
240 | #define NVREG_TXRXCTL_BIT2 0x0004 | |
241 | #define NVREG_TXRXCTL_IDLE 0x0008 | |
242 | #define NVREG_TXRXCTL_RESET 0x0010 | |
243 | #define NVREG_TXRXCTL_RXCHECK 0x0400 | |
8a4ae7f2 | 244 | #define NVREG_TXRXCTL_DESC_1 0 |
d2f78412 AA |
245 | #define NVREG_TXRXCTL_DESC_2 0x002100 |
246 | #define NVREG_TXRXCTL_DESC_3 0xc02200 | |
ee407b02 AA |
247 | #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
248 | #define NVREG_TXRXCTL_VLANINS 0x00080 | |
0832b25a AA |
249 | NvRegTxRingPhysAddrHigh = 0x148, |
250 | NvRegRxRingPhysAddrHigh = 0x14C, | |
eb91f61b | 251 | NvRegTxPauseFrame = 0x170, |
5289b4c4 AA |
252 | #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080 |
253 | #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 | |
254 | #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 | |
255 | #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 | |
9a33e883 AA |
256 | NvRegTxPauseFrameLimit = 0x174, |
257 | #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000 | |
1da177e4 LT |
258 | NvRegMIIStatus = 0x180, |
259 | #define NVREG_MIISTAT_ERROR 0x0001 | |
260 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | |
eb798428 AA |
261 | #define NVREG_MIISTAT_MASK_RW 0x0007 |
262 | #define NVREG_MIISTAT_MASK_ALL 0x000f | |
7e680c22 AA |
263 | NvRegMIIMask = 0x184, |
264 | #define NVREG_MII_LINKCHANGE 0x0008 | |
1da177e4 LT |
265 | |
266 | NvRegAdapterControl = 0x188, | |
267 | #define NVREG_ADAPTCTL_START 0x02 | |
268 | #define NVREG_ADAPTCTL_LINKUP 0x04 | |
269 | #define NVREG_ADAPTCTL_PHYVALID 0x40000 | |
270 | #define NVREG_ADAPTCTL_RUNNING 0x100000 | |
271 | #define NVREG_ADAPTCTL_PHYSHIFT 24 | |
272 | NvRegMIISpeed = 0x18c, | |
273 | #define NVREG_MIISPEED_BIT8 (1<<8) | |
274 | #define NVREG_MIIDELAY 5 | |
275 | NvRegMIIControl = 0x190, | |
276 | #define NVREG_MIICTL_INUSE 0x08000 | |
277 | #define NVREG_MIICTL_WRITE 0x00400 | |
278 | #define NVREG_MIICTL_ADDRSHIFT 5 | |
279 | NvRegMIIData = 0x194, | |
9c662435 AA |
280 | NvRegTxUnicast = 0x1a0, |
281 | NvRegTxMulticast = 0x1a4, | |
282 | NvRegTxBroadcast = 0x1a8, | |
1da177e4 LT |
283 | NvRegWakeUpFlags = 0x200, |
284 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 | |
285 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 | |
286 | #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 | |
287 | #define NVREG_WAKEUPFLAGS_D3SHIFT 12 | |
288 | #define NVREG_WAKEUPFLAGS_D2SHIFT 8 | |
289 | #define NVREG_WAKEUPFLAGS_D1SHIFT 4 | |
290 | #define NVREG_WAKEUPFLAGS_D0SHIFT 0 | |
291 | #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 | |
292 | #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 | |
293 | #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 | |
294 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 | |
295 | ||
cac1c52c | 296 | NvRegMgmtUnitGetVersion = 0x204, |
78aea4fc | 297 | #define NVREG_MGMTUNITGETVERSION 0x01 |
cac1c52c AA |
298 | NvRegMgmtUnitVersion = 0x208, |
299 | #define NVREG_MGMTUNITVERSION 0x08 | |
1da177e4 LT |
300 | NvRegPowerCap = 0x268, |
301 | #define NVREG_POWERCAP_D3SUPP (1<<30) | |
302 | #define NVREG_POWERCAP_D2SUPP (1<<26) | |
303 | #define NVREG_POWERCAP_D1SUPP (1<<25) | |
304 | NvRegPowerState = 0x26c, | |
305 | #define NVREG_POWERSTATE_POWEREDUP 0x8000 | |
306 | #define NVREG_POWERSTATE_VALID 0x0100 | |
307 | #define NVREG_POWERSTATE_MASK 0x0003 | |
308 | #define NVREG_POWERSTATE_D0 0x0000 | |
309 | #define NVREG_POWERSTATE_D1 0x0001 | |
310 | #define NVREG_POWERSTATE_D2 0x0002 | |
311 | #define NVREG_POWERSTATE_D3 0x0003 | |
cac1c52c AA |
312 | NvRegMgmtUnitControl = 0x278, |
313 | #define NVREG_MGMTUNITCONTROL_INUSE 0x20000 | |
52da3578 AA |
314 | NvRegTxCnt = 0x280, |
315 | NvRegTxZeroReXmt = 0x284, | |
316 | NvRegTxOneReXmt = 0x288, | |
317 | NvRegTxManyReXmt = 0x28c, | |
318 | NvRegTxLateCol = 0x290, | |
319 | NvRegTxUnderflow = 0x294, | |
320 | NvRegTxLossCarrier = 0x298, | |
321 | NvRegTxExcessDef = 0x29c, | |
322 | NvRegTxRetryErr = 0x2a0, | |
323 | NvRegRxFrameErr = 0x2a4, | |
324 | NvRegRxExtraByte = 0x2a8, | |
325 | NvRegRxLateCol = 0x2ac, | |
326 | NvRegRxRunt = 0x2b0, | |
327 | NvRegRxFrameTooLong = 0x2b4, | |
328 | NvRegRxOverflow = 0x2b8, | |
329 | NvRegRxFCSErr = 0x2bc, | |
330 | NvRegRxFrameAlignErr = 0x2c0, | |
331 | NvRegRxLenErr = 0x2c4, | |
332 | NvRegRxUnicast = 0x2c8, | |
333 | NvRegRxMulticast = 0x2cc, | |
334 | NvRegRxBroadcast = 0x2d0, | |
335 | NvRegTxDef = 0x2d4, | |
336 | NvRegTxFrame = 0x2d8, | |
337 | NvRegRxCnt = 0x2dc, | |
338 | NvRegTxPause = 0x2e0, | |
339 | NvRegRxPause = 0x2e4, | |
340 | NvRegRxDropFrame = 0x2e8, | |
ee407b02 AA |
341 | NvRegVlanControl = 0x300, |
342 | #define NVREG_VLANCONTROL_ENABLE 0x2000 | |
d33a73c8 AA |
343 | NvRegMSIXMap0 = 0x3e0, |
344 | NvRegMSIXMap1 = 0x3e4, | |
345 | NvRegMSIXIrqStatus = 0x3f0, | |
86a0f043 AA |
346 | |
347 | NvRegPowerState2 = 0x600, | |
1545e205 | 348 | #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15 |
86a0f043 | 349 | #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 |
22ae03a1 | 350 | #define NVREG_POWERSTATE2_PHY_RESET 0x0004 |
88d7d8b0 | 351 | #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00 |
1da177e4 LT |
352 | }; |
353 | ||
354 | /* Big endian: should work, but is untested */ | |
355 | struct ring_desc { | |
a8bed49e SH |
356 | __le32 buf; |
357 | __le32 flaglen; | |
1da177e4 LT |
358 | }; |
359 | ||
ee73362c | 360 | struct ring_desc_ex { |
a8bed49e SH |
361 | __le32 bufhigh; |
362 | __le32 buflow; | |
363 | __le32 txvlan; | |
364 | __le32 flaglen; | |
ee73362c MS |
365 | }; |
366 | ||
f82a9352 | 367 | union ring_type { |
78aea4fc SJ |
368 | struct ring_desc *orig; |
369 | struct ring_desc_ex *ex; | |
f82a9352 | 370 | }; |
ee73362c | 371 | |
1da177e4 LT |
372 | #define FLAG_MASK_V1 0xffff0000 |
373 | #define FLAG_MASK_V2 0xffffc000 | |
374 | #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) | |
375 | #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) | |
376 | ||
377 | #define NV_TX_LASTPACKET (1<<16) | |
378 | #define NV_TX_RETRYERROR (1<<19) | |
a433686c | 379 | #define NV_TX_RETRYCOUNT_MASK (0xF<<20) |
c2dba06d | 380 | #define NV_TX_FORCED_INTERRUPT (1<<24) |
1da177e4 LT |
381 | #define NV_TX_DEFERRED (1<<26) |
382 | #define NV_TX_CARRIERLOST (1<<27) | |
383 | #define NV_TX_LATECOLLISION (1<<28) | |
384 | #define NV_TX_UNDERFLOW (1<<29) | |
385 | #define NV_TX_ERROR (1<<30) | |
386 | #define NV_TX_VALID (1<<31) | |
387 | ||
388 | #define NV_TX2_LASTPACKET (1<<29) | |
389 | #define NV_TX2_RETRYERROR (1<<18) | |
a433686c | 390 | #define NV_TX2_RETRYCOUNT_MASK (0xF<<19) |
c2dba06d | 391 | #define NV_TX2_FORCED_INTERRUPT (1<<30) |
1da177e4 LT |
392 | #define NV_TX2_DEFERRED (1<<25) |
393 | #define NV_TX2_CARRIERLOST (1<<26) | |
394 | #define NV_TX2_LATECOLLISION (1<<27) | |
395 | #define NV_TX2_UNDERFLOW (1<<28) | |
396 | /* error and valid are the same for both */ | |
397 | #define NV_TX2_ERROR (1<<30) | |
398 | #define NV_TX2_VALID (1<<31) | |
ac9c1897 AA |
399 | #define NV_TX2_TSO (1<<28) |
400 | #define NV_TX2_TSO_SHIFT 14 | |
fa45459e AA |
401 | #define NV_TX2_TSO_MAX_SHIFT 14 |
402 | #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) | |
8a4ae7f2 MS |
403 | #define NV_TX2_CHECKSUM_L3 (1<<27) |
404 | #define NV_TX2_CHECKSUM_L4 (1<<26) | |
1da177e4 | 405 | |
ee407b02 AA |
406 | #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
407 | ||
1da177e4 LT |
408 | #define NV_RX_DESCRIPTORVALID (1<<16) |
409 | #define NV_RX_MISSEDFRAME (1<<17) | |
410 | #define NV_RX_SUBSTRACT1 (1<<18) | |
411 | #define NV_RX_ERROR1 (1<<23) | |
412 | #define NV_RX_ERROR2 (1<<24) | |
413 | #define NV_RX_ERROR3 (1<<25) | |
414 | #define NV_RX_ERROR4 (1<<26) | |
415 | #define NV_RX_CRCERR (1<<27) | |
416 | #define NV_RX_OVERFLOW (1<<28) | |
417 | #define NV_RX_FRAMINGERR (1<<29) | |
418 | #define NV_RX_ERROR (1<<30) | |
419 | #define NV_RX_AVAIL (1<<31) | |
1ef6841b | 420 | #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR) |
1da177e4 LT |
421 | |
422 | #define NV_RX2_CHECKSUMMASK (0x1C000000) | |
bfaffe8f AA |
423 | #define NV_RX2_CHECKSUM_IP (0x10000000) |
424 | #define NV_RX2_CHECKSUM_IP_TCP (0x14000000) | |
425 | #define NV_RX2_CHECKSUM_IP_UDP (0x18000000) | |
1da177e4 LT |
426 | #define NV_RX2_DESCRIPTORVALID (1<<29) |
427 | #define NV_RX2_SUBSTRACT1 (1<<25) | |
428 | #define NV_RX2_ERROR1 (1<<18) | |
429 | #define NV_RX2_ERROR2 (1<<19) | |
430 | #define NV_RX2_ERROR3 (1<<20) | |
431 | #define NV_RX2_ERROR4 (1<<21) | |
432 | #define NV_RX2_CRCERR (1<<22) | |
433 | #define NV_RX2_OVERFLOW (1<<23) | |
434 | #define NV_RX2_FRAMINGERR (1<<24) | |
435 | /* error and avail are the same for both */ | |
436 | #define NV_RX2_ERROR (1<<30) | |
437 | #define NV_RX2_AVAIL (1<<31) | |
1ef6841b | 438 | #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR) |
1da177e4 | 439 | |
ee407b02 AA |
440 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
441 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | |
442 | ||
1da177e4 | 443 | /* Miscelaneous hardware related defines: */ |
78aea4fc SJ |
444 | #define NV_PCI_REGSZ_VER1 0x270 |
445 | #define NV_PCI_REGSZ_VER2 0x2d4 | |
446 | #define NV_PCI_REGSZ_VER3 0x604 | |
447 | #define NV_PCI_REGSZ_MAX 0x604 | |
1da177e4 LT |
448 | |
449 | /* various timeout delays: all in usec */ | |
450 | #define NV_TXRX_RESET_DELAY 4 | |
451 | #define NV_TXSTOP_DELAY1 10 | |
452 | #define NV_TXSTOP_DELAY1MAX 500000 | |
453 | #define NV_TXSTOP_DELAY2 100 | |
454 | #define NV_RXSTOP_DELAY1 10 | |
455 | #define NV_RXSTOP_DELAY1MAX 500000 | |
456 | #define NV_RXSTOP_DELAY2 100 | |
457 | #define NV_SETUP5_DELAY 5 | |
458 | #define NV_SETUP5_DELAYMAX 50000 | |
459 | #define NV_POWERUP_DELAY 5 | |
460 | #define NV_POWERUP_DELAYMAX 5000 | |
461 | #define NV_MIIBUSY_DELAY 50 | |
462 | #define NV_MIIPHY_DELAY 10 | |
463 | #define NV_MIIPHY_DELAYMAX 10000 | |
86a0f043 | 464 | #define NV_MAC_RESET_DELAY 64 |
1da177e4 LT |
465 | |
466 | #define NV_WAKEUPPATTERNS 5 | |
467 | #define NV_WAKEUPMASKENTRIES 4 | |
468 | ||
469 | /* General driver defaults */ | |
470 | #define NV_WATCHDOG_TIMEO (5*HZ) | |
471 | ||
6cef67a0 | 472 | #define RX_RING_DEFAULT 512 |
eafa59f6 AA |
473 | #define TX_RING_DEFAULT 256 |
474 | #define RX_RING_MIN 128 | |
475 | #define TX_RING_MIN 64 | |
476 | #define RING_MAX_DESC_VER_1 1024 | |
477 | #define RING_MAX_DESC_VER_2_3 16384 | |
1da177e4 LT |
478 | |
479 | /* rx/tx mac addr + type + vlan + align + slack*/ | |
d81c0983 MS |
480 | #define NV_RX_HEADERS (64) |
481 | /* even more slack. */ | |
482 | #define NV_RX_ALLOC_PAD (64) | |
483 | ||
484 | /* maximum mtu size */ | |
485 | #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ | |
486 | #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ | |
1da177e4 LT |
487 | |
488 | #define OOM_REFILL (1+HZ/20) | |
489 | #define POLL_WAIT (1+HZ/100) | |
490 | #define LINK_TIMEOUT (3*HZ) | |
52da3578 | 491 | #define STATS_INTERVAL (10*HZ) |
1da177e4 | 492 | |
f3b197ac | 493 | /* |
1da177e4 | 494 | * desc_ver values: |
8a4ae7f2 MS |
495 | * The nic supports three different descriptor types: |
496 | * - DESC_VER_1: Original | |
497 | * - DESC_VER_2: support for jumbo frames. | |
498 | * - DESC_VER_3: 64-bit format. | |
1da177e4 | 499 | */ |
8a4ae7f2 MS |
500 | #define DESC_VER_1 1 |
501 | #define DESC_VER_2 2 | |
502 | #define DESC_VER_3 3 | |
1da177e4 LT |
503 | |
504 | /* PHY defines */ | |
9f3f7910 AA |
505 | #define PHY_OUI_MARVELL 0x5043 |
506 | #define PHY_OUI_CICADA 0x03f1 | |
507 | #define PHY_OUI_VITESSE 0x01c1 | |
508 | #define PHY_OUI_REALTEK 0x0732 | |
509 | #define PHY_OUI_REALTEK2 0x0020 | |
1da177e4 LT |
510 | #define PHYID1_OUI_MASK 0x03ff |
511 | #define PHYID1_OUI_SHFT 6 | |
512 | #define PHYID2_OUI_MASK 0xfc00 | |
513 | #define PHYID2_OUI_SHFT 10 | |
edf7e5ec | 514 | #define PHYID2_MODEL_MASK 0x03f0 |
9f3f7910 AA |
515 | #define PHY_MODEL_REALTEK_8211 0x0110 |
516 | #define PHY_REV_MASK 0x0001 | |
517 | #define PHY_REV_REALTEK_8211B 0x0000 | |
518 | #define PHY_REV_REALTEK_8211C 0x0001 | |
519 | #define PHY_MODEL_REALTEK_8201 0x0200 | |
520 | #define PHY_MODEL_MARVELL_E3016 0x0220 | |
edf7e5ec | 521 | #define PHY_MARVELL_E3016_INITMASK 0x0300 |
14a67f3c AA |
522 | #define PHY_CICADA_INIT1 0x0f000 |
523 | #define PHY_CICADA_INIT2 0x0e00 | |
524 | #define PHY_CICADA_INIT3 0x01000 | |
525 | #define PHY_CICADA_INIT4 0x0200 | |
526 | #define PHY_CICADA_INIT5 0x0004 | |
527 | #define PHY_CICADA_INIT6 0x02000 | |
d215d8a2 AA |
528 | #define PHY_VITESSE_INIT_REG1 0x1f |
529 | #define PHY_VITESSE_INIT_REG2 0x10 | |
530 | #define PHY_VITESSE_INIT_REG3 0x11 | |
531 | #define PHY_VITESSE_INIT_REG4 0x12 | |
532 | #define PHY_VITESSE_INIT_MSK1 0xc | |
533 | #define PHY_VITESSE_INIT_MSK2 0x0180 | |
534 | #define PHY_VITESSE_INIT1 0x52b5 | |
535 | #define PHY_VITESSE_INIT2 0xaf8a | |
536 | #define PHY_VITESSE_INIT3 0x8 | |
537 | #define PHY_VITESSE_INIT4 0x8f8a | |
538 | #define PHY_VITESSE_INIT5 0xaf86 | |
539 | #define PHY_VITESSE_INIT6 0x8f86 | |
540 | #define PHY_VITESSE_INIT7 0xaf82 | |
541 | #define PHY_VITESSE_INIT8 0x0100 | |
542 | #define PHY_VITESSE_INIT9 0x8f82 | |
543 | #define PHY_VITESSE_INIT10 0x0 | |
c5e3ae88 AA |
544 | #define PHY_REALTEK_INIT_REG1 0x1f |
545 | #define PHY_REALTEK_INIT_REG2 0x19 | |
546 | #define PHY_REALTEK_INIT_REG3 0x13 | |
9f3f7910 AA |
547 | #define PHY_REALTEK_INIT_REG4 0x14 |
548 | #define PHY_REALTEK_INIT_REG5 0x18 | |
549 | #define PHY_REALTEK_INIT_REG6 0x11 | |
22ae03a1 | 550 | #define PHY_REALTEK_INIT_REG7 0x01 |
c5e3ae88 AA |
551 | #define PHY_REALTEK_INIT1 0x0000 |
552 | #define PHY_REALTEK_INIT2 0x8e00 | |
553 | #define PHY_REALTEK_INIT3 0x0001 | |
554 | #define PHY_REALTEK_INIT4 0xad17 | |
9f3f7910 AA |
555 | #define PHY_REALTEK_INIT5 0xfb54 |
556 | #define PHY_REALTEK_INIT6 0xf5c7 | |
557 | #define PHY_REALTEK_INIT7 0x1000 | |
558 | #define PHY_REALTEK_INIT8 0x0003 | |
22ae03a1 AA |
559 | #define PHY_REALTEK_INIT9 0x0008 |
560 | #define PHY_REALTEK_INIT10 0x0005 | |
561 | #define PHY_REALTEK_INIT11 0x0200 | |
9f3f7910 | 562 | #define PHY_REALTEK_INIT_MSK1 0x0003 |
d215d8a2 | 563 | |
1da177e4 LT |
564 | #define PHY_GIGABIT 0x0100 |
565 | ||
566 | #define PHY_TIMEOUT 0x1 | |
567 | #define PHY_ERROR 0x2 | |
568 | ||
569 | #define PHY_100 0x1 | |
570 | #define PHY_1000 0x2 | |
571 | #define PHY_HALF 0x100 | |
572 | ||
eb91f61b AA |
573 | #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 |
574 | #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 | |
575 | #define NV_PAUSEFRAME_RX_ENABLE 0x0004 | |
576 | #define NV_PAUSEFRAME_TX_ENABLE 0x0008 | |
b6d0773f AA |
577 | #define NV_PAUSEFRAME_RX_REQ 0x0010 |
578 | #define NV_PAUSEFRAME_TX_REQ 0x0020 | |
579 | #define NV_PAUSEFRAME_AUTONEG 0x0040 | |
1da177e4 | 580 | |
d33a73c8 AA |
581 | /* MSI/MSI-X defines */ |
582 | #define NV_MSI_X_MAX_VECTORS 8 | |
583 | #define NV_MSI_X_VECTORS_MASK 0x000f | |
584 | #define NV_MSI_CAPABLE 0x0010 | |
585 | #define NV_MSI_X_CAPABLE 0x0020 | |
586 | #define NV_MSI_ENABLED 0x0040 | |
587 | #define NV_MSI_X_ENABLED 0x0080 | |
588 | ||
589 | #define NV_MSI_X_VECTOR_ALL 0x0 | |
590 | #define NV_MSI_X_VECTOR_RX 0x0 | |
591 | #define NV_MSI_X_VECTOR_TX 0x1 | |
592 | #define NV_MSI_X_VECTOR_OTHER 0x2 | |
1da177e4 | 593 | |
b6e4405b AA |
594 | #define NV_MSI_PRIV_OFFSET 0x68 |
595 | #define NV_MSI_PRIV_VALUE 0xffffffff | |
596 | ||
b2976d23 AA |
597 | #define NV_RESTART_TX 0x1 |
598 | #define NV_RESTART_RX 0x2 | |
599 | ||
3b446c3e AA |
600 | #define NV_TX_LIMIT_COUNT 16 |
601 | ||
4145ade2 AA |
602 | #define NV_DYNAMIC_THRESHOLD 4 |
603 | #define NV_DYNAMIC_MAX_QUIET_COUNT 2048 | |
604 | ||
52da3578 AA |
605 | /* statistics */ |
606 | struct nv_ethtool_str { | |
607 | char name[ETH_GSTRING_LEN]; | |
608 | }; | |
609 | ||
610 | static const struct nv_ethtool_str nv_estats_str[] = { | |
611 | { "tx_bytes" }, | |
612 | { "tx_zero_rexmt" }, | |
613 | { "tx_one_rexmt" }, | |
614 | { "tx_many_rexmt" }, | |
615 | { "tx_late_collision" }, | |
616 | { "tx_fifo_errors" }, | |
617 | { "tx_carrier_errors" }, | |
618 | { "tx_excess_deferral" }, | |
619 | { "tx_retry_error" }, | |
52da3578 AA |
620 | { "rx_frame_error" }, |
621 | { "rx_extra_byte" }, | |
622 | { "rx_late_collision" }, | |
623 | { "rx_runt" }, | |
624 | { "rx_frame_too_long" }, | |
625 | { "rx_over_errors" }, | |
626 | { "rx_crc_errors" }, | |
627 | { "rx_frame_align_error" }, | |
628 | { "rx_length_error" }, | |
629 | { "rx_unicast" }, | |
630 | { "rx_multicast" }, | |
631 | { "rx_broadcast" }, | |
57fff698 AA |
632 | { "rx_packets" }, |
633 | { "rx_errors_total" }, | |
634 | { "tx_errors_total" }, | |
635 | ||
636 | /* version 2 stats */ | |
637 | { "tx_deferral" }, | |
638 | { "tx_packets" }, | |
52da3578 | 639 | { "rx_bytes" }, |
57fff698 | 640 | { "tx_pause" }, |
52da3578 | 641 | { "rx_pause" }, |
9c662435 AA |
642 | { "rx_drop_frame" }, |
643 | ||
644 | /* version 3 stats */ | |
645 | { "tx_unicast" }, | |
646 | { "tx_multicast" }, | |
647 | { "tx_broadcast" } | |
52da3578 AA |
648 | }; |
649 | ||
650 | struct nv_ethtool_stats { | |
651 | u64 tx_bytes; | |
652 | u64 tx_zero_rexmt; | |
653 | u64 tx_one_rexmt; | |
654 | u64 tx_many_rexmt; | |
655 | u64 tx_late_collision; | |
656 | u64 tx_fifo_errors; | |
657 | u64 tx_carrier_errors; | |
658 | u64 tx_excess_deferral; | |
659 | u64 tx_retry_error; | |
52da3578 AA |
660 | u64 rx_frame_error; |
661 | u64 rx_extra_byte; | |
662 | u64 rx_late_collision; | |
663 | u64 rx_runt; | |
664 | u64 rx_frame_too_long; | |
665 | u64 rx_over_errors; | |
666 | u64 rx_crc_errors; | |
667 | u64 rx_frame_align_error; | |
668 | u64 rx_length_error; | |
669 | u64 rx_unicast; | |
670 | u64 rx_multicast; | |
671 | u64 rx_broadcast; | |
57fff698 AA |
672 | u64 rx_packets; |
673 | u64 rx_errors_total; | |
674 | u64 tx_errors_total; | |
675 | ||
676 | /* version 2 stats */ | |
677 | u64 tx_deferral; | |
678 | u64 tx_packets; | |
52da3578 | 679 | u64 rx_bytes; |
57fff698 | 680 | u64 tx_pause; |
52da3578 AA |
681 | u64 rx_pause; |
682 | u64 rx_drop_frame; | |
9c662435 AA |
683 | |
684 | /* version 3 stats */ | |
685 | u64 tx_unicast; | |
686 | u64 tx_multicast; | |
687 | u64 tx_broadcast; | |
52da3578 AA |
688 | }; |
689 | ||
9c662435 AA |
690 | #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) |
691 | #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3) | |
57fff698 AA |
692 | #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) |
693 | ||
9589c77a AA |
694 | /* diagnostics */ |
695 | #define NV_TEST_COUNT_BASE 3 | |
696 | #define NV_TEST_COUNT_EXTENDED 4 | |
697 | ||
698 | static const struct nv_ethtool_str nv_etests_str[] = { | |
699 | { "link (online/offline)" }, | |
700 | { "register (offline) " }, | |
701 | { "interrupt (offline) " }, | |
702 | { "loopback (offline) " } | |
703 | }; | |
704 | ||
705 | struct register_test { | |
5bb7ea26 AV |
706 | __u32 reg; |
707 | __u32 mask; | |
9589c77a AA |
708 | }; |
709 | ||
710 | static const struct register_test nv_registers_test[] = { | |
711 | { NvRegUnknownSetupReg6, 0x01 }, | |
712 | { NvRegMisc1, 0x03c }, | |
713 | { NvRegOffloadConfig, 0x03ff }, | |
714 | { NvRegMulticastAddrA, 0xffffffff }, | |
95d161cb | 715 | { NvRegTxWatermark, 0x0ff }, |
9589c77a | 716 | { NvRegWakeUpFlags, 0x07777 }, |
78aea4fc | 717 | { 0, 0 } |
9589c77a AA |
718 | }; |
719 | ||
761fcd9e AA |
720 | struct nv_skb_map { |
721 | struct sk_buff *skb; | |
722 | dma_addr_t dma; | |
73a37079 ED |
723 | unsigned int dma_len:31; |
724 | unsigned int dma_single:1; | |
3b446c3e AA |
725 | struct ring_desc_ex *first_tx_desc; |
726 | struct nv_skb_map *next_tx_ctx; | |
761fcd9e AA |
727 | }; |
728 | ||
1da177e4 LT |
729 | /* |
730 | * SMP locking: | |
b74ca3a8 | 731 | * All hardware access under netdev_priv(dev)->lock, except the performance |
1da177e4 LT |
732 | * critical parts: |
733 | * - rx is (pseudo-) lockless: it relies on the single-threading provided | |
734 | * by the arch code for interrupts. | |
932ff279 | 735 | * - tx setup is lockless: it relies on netif_tx_lock. Actual submission |
b74ca3a8 | 736 | * needs netdev_priv(dev)->lock :-( |
932ff279 | 737 | * - set_multicast_list: preparation lockless, relies on netif_tx_lock. |
1da177e4 LT |
738 | */ |
739 | ||
740 | /* in dev: base, irq */ | |
741 | struct fe_priv { | |
742 | spinlock_t lock; | |
743 | ||
bea3348e SH |
744 | struct net_device *dev; |
745 | struct napi_struct napi; | |
746 | ||
1da177e4 LT |
747 | /* General data: |
748 | * Locking: spin_lock(&np->lock); */ | |
52da3578 | 749 | struct nv_ethtool_stats estats; |
1da177e4 LT |
750 | int in_shutdown; |
751 | u32 linkspeed; | |
752 | int duplex; | |
753 | int autoneg; | |
754 | int fixed_mode; | |
755 | int phyaddr; | |
756 | int wolenabled; | |
757 | unsigned int phy_oui; | |
edf7e5ec | 758 | unsigned int phy_model; |
9f3f7910 | 759 | unsigned int phy_rev; |
1da177e4 | 760 | u16 gigabit; |
9589c77a | 761 | int intr_test; |
c5cf9101 | 762 | int recover_error; |
4145ade2 | 763 | int quiet_count; |
1da177e4 LT |
764 | |
765 | /* General data: RO fields */ | |
766 | dma_addr_t ring_addr; | |
767 | struct pci_dev *pci_dev; | |
768 | u32 orig_mac[2]; | |
582806be | 769 | u32 events; |
1da177e4 LT |
770 | u32 irqmask; |
771 | u32 desc_ver; | |
8a4ae7f2 | 772 | u32 txrxctl_bits; |
ee407b02 | 773 | u32 vlanctl_bits; |
86a0f043 | 774 | u32 driver_data; |
9f3f7910 | 775 | u32 device_id; |
86a0f043 | 776 | u32 register_size; |
f2ad2d9b | 777 | int rx_csum; |
7e680c22 | 778 | u32 mac_in_use; |
cac1c52c AA |
779 | int mgmt_version; |
780 | int mgmt_sema; | |
1da177e4 LT |
781 | |
782 | void __iomem *base; | |
783 | ||
784 | /* rx specific fields. | |
785 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
786 | */ | |
761fcd9e AA |
787 | union ring_type get_rx, put_rx, first_rx, last_rx; |
788 | struct nv_skb_map *get_rx_ctx, *put_rx_ctx; | |
789 | struct nv_skb_map *first_rx_ctx, *last_rx_ctx; | |
790 | struct nv_skb_map *rx_skb; | |
791 | ||
f82a9352 | 792 | union ring_type rx_ring; |
1da177e4 | 793 | unsigned int rx_buf_sz; |
d81c0983 | 794 | unsigned int pkt_limit; |
1da177e4 LT |
795 | struct timer_list oom_kick; |
796 | struct timer_list nic_poll; | |
52da3578 | 797 | struct timer_list stats_poll; |
d33a73c8 | 798 | u32 nic_poll_irq; |
eafa59f6 | 799 | int rx_ring_size; |
1da177e4 LT |
800 | |
801 | /* media detection workaround. | |
802 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
803 | */ | |
804 | int need_linktimer; | |
805 | unsigned long link_timeout; | |
806 | /* | |
807 | * tx specific fields. | |
808 | */ | |
761fcd9e AA |
809 | union ring_type get_tx, put_tx, first_tx, last_tx; |
810 | struct nv_skb_map *get_tx_ctx, *put_tx_ctx; | |
811 | struct nv_skb_map *first_tx_ctx, *last_tx_ctx; | |
812 | struct nv_skb_map *tx_skb; | |
813 | ||
f82a9352 | 814 | union ring_type tx_ring; |
1da177e4 | 815 | u32 tx_flags; |
eafa59f6 | 816 | int tx_ring_size; |
3b446c3e AA |
817 | int tx_limit; |
818 | u32 tx_pkts_in_progress; | |
819 | struct nv_skb_map *tx_change_owner; | |
820 | struct nv_skb_map *tx_end_flip; | |
aaa37d2d | 821 | int tx_stop; |
ee407b02 AA |
822 | |
823 | /* vlan fields */ | |
824 | struct vlan_group *vlangrp; | |
d33a73c8 AA |
825 | |
826 | /* msi/msi-x fields */ | |
827 | u32 msi_flags; | |
828 | struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; | |
eb91f61b AA |
829 | |
830 | /* flow control */ | |
831 | u32 pause_flags; | |
1a1ca861 TD |
832 | |
833 | /* power saved state */ | |
834 | u32 saved_config_space[NV_PCI_REGSZ_MAX/4]; | |
ddb213f0 YL |
835 | |
836 | /* for different msi-x irq type */ | |
837 | char name_rx[IFNAMSIZ + 3]; /* -rx */ | |
838 | char name_tx[IFNAMSIZ + 3]; /* -tx */ | |
839 | char name_other[IFNAMSIZ + 6]; /* -other */ | |
1da177e4 LT |
840 | }; |
841 | ||
842 | /* | |
843 | * Maximum number of loops until we assume that a bit in the irq mask | |
844 | * is stuck. Overridable with module param. | |
845 | */ | |
4145ade2 | 846 | static int max_interrupt_work = 4; |
1da177e4 | 847 | |
a971c324 AA |
848 | /* |
849 | * Optimization can be either throuput mode or cpu mode | |
f3b197ac | 850 | * |
a971c324 AA |
851 | * Throughput Mode: Every tx and rx packet will generate an interrupt. |
852 | * CPU Mode: Interrupts are controlled by a timer. | |
853 | */ | |
69fe3fd7 AA |
854 | enum { |
855 | NV_OPTIMIZATION_MODE_THROUGHPUT, | |
9e184767 AA |
856 | NV_OPTIMIZATION_MODE_CPU, |
857 | NV_OPTIMIZATION_MODE_DYNAMIC | |
69fe3fd7 | 858 | }; |
9e184767 | 859 | static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC; |
a971c324 AA |
860 | |
861 | /* | |
862 | * Poll interval for timer irq | |
863 | * | |
864 | * This interval determines how frequent an interrupt is generated. | |
865 | * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] | |
866 | * Min = 0, and Max = 65535 | |
867 | */ | |
868 | static int poll_interval = -1; | |
869 | ||
d33a73c8 | 870 | /* |
69fe3fd7 | 871 | * MSI interrupts |
d33a73c8 | 872 | */ |
69fe3fd7 AA |
873 | enum { |
874 | NV_MSI_INT_DISABLED, | |
875 | NV_MSI_INT_ENABLED | |
876 | }; | |
877 | static int msi = NV_MSI_INT_ENABLED; | |
d33a73c8 AA |
878 | |
879 | /* | |
69fe3fd7 | 880 | * MSIX interrupts |
d33a73c8 | 881 | */ |
69fe3fd7 AA |
882 | enum { |
883 | NV_MSIX_INT_DISABLED, | |
884 | NV_MSIX_INT_ENABLED | |
885 | }; | |
39482791 | 886 | static int msix = NV_MSIX_INT_ENABLED; |
69fe3fd7 AA |
887 | |
888 | /* | |
889 | * DMA 64bit | |
890 | */ | |
891 | enum { | |
892 | NV_DMA_64BIT_DISABLED, | |
893 | NV_DMA_64BIT_ENABLED | |
894 | }; | |
895 | static int dma_64bit = NV_DMA_64BIT_ENABLED; | |
d33a73c8 | 896 | |
9f3f7910 AA |
897 | /* |
898 | * Crossover Detection | |
899 | * Realtek 8201 phy + some OEM boards do not work properly. | |
900 | */ | |
901 | enum { | |
902 | NV_CROSSOVER_DETECTION_DISABLED, | |
903 | NV_CROSSOVER_DETECTION_ENABLED | |
904 | }; | |
905 | static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED; | |
906 | ||
5a9a8e32 ES |
907 | /* |
908 | * Power down phy when interface is down (persists through reboot; | |
909 | * older Linux and other OSes may not power it up again) | |
910 | */ | |
78aea4fc | 911 | static int phy_power_down; |
5a9a8e32 | 912 | |
1da177e4 LT |
913 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
914 | { | |
915 | return netdev_priv(dev); | |
916 | } | |
917 | ||
918 | static inline u8 __iomem *get_hwbase(struct net_device *dev) | |
919 | { | |
ac9c1897 | 920 | return ((struct fe_priv *)netdev_priv(dev))->base; |
1da177e4 LT |
921 | } |
922 | ||
923 | static inline void pci_push(u8 __iomem *base) | |
924 | { | |
925 | /* force out pending posted writes */ | |
926 | readl(base); | |
927 | } | |
928 | ||
929 | static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) | |
930 | { | |
f82a9352 | 931 | return le32_to_cpu(prd->flaglen) |
1da177e4 LT |
932 | & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
933 | } | |
934 | ||
ee73362c MS |
935 | static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
936 | { | |
f82a9352 | 937 | return le32_to_cpu(prd->flaglen) & LEN_MASK_V2; |
ee73362c MS |
938 | } |
939 | ||
36b30ea9 JG |
940 | static bool nv_optimized(struct fe_priv *np) |
941 | { | |
942 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | |
943 | return false; | |
944 | return true; | |
945 | } | |
946 | ||
1da177e4 | 947 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
344d0dce | 948 | int delay, int delaymax) |
1da177e4 LT |
949 | { |
950 | u8 __iomem *base = get_hwbase(dev); | |
951 | ||
952 | pci_push(base); | |
953 | do { | |
954 | udelay(delay); | |
955 | delaymax -= delay; | |
344d0dce | 956 | if (delaymax < 0) |
1da177e4 | 957 | return 1; |
1da177e4 LT |
958 | } while ((readl(base + offset) & mask) != target); |
959 | return 0; | |
960 | } | |
961 | ||
0832b25a AA |
962 | #define NV_SETUP_RX_RING 0x01 |
963 | #define NV_SETUP_TX_RING 0x02 | |
964 | ||
5bb7ea26 AV |
965 | static inline u32 dma_low(dma_addr_t addr) |
966 | { | |
967 | return addr; | |
968 | } | |
969 | ||
970 | static inline u32 dma_high(dma_addr_t addr) | |
971 | { | |
972 | return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */ | |
973 | } | |
974 | ||
0832b25a AA |
975 | static void setup_hw_rings(struct net_device *dev, int rxtx_flags) |
976 | { | |
977 | struct fe_priv *np = get_nvpriv(dev); | |
978 | u8 __iomem *base = get_hwbase(dev); | |
979 | ||
36b30ea9 | 980 | if (!nv_optimized(np)) { |
78aea4fc | 981 | if (rxtx_flags & NV_SETUP_RX_RING) |
5bb7ea26 | 982 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
78aea4fc | 983 | if (rxtx_flags & NV_SETUP_TX_RING) |
5bb7ea26 | 984 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
0832b25a AA |
985 | } else { |
986 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
5bb7ea26 AV |
987 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
988 | writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); | |
0832b25a AA |
989 | } |
990 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
5bb7ea26 AV |
991 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
992 | writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh); | |
0832b25a AA |
993 | } |
994 | } | |
995 | } | |
996 | ||
eafa59f6 AA |
997 | static void free_rings(struct net_device *dev) |
998 | { | |
999 | struct fe_priv *np = get_nvpriv(dev); | |
1000 | ||
36b30ea9 | 1001 | if (!nv_optimized(np)) { |
f82a9352 | 1002 | if (np->rx_ring.orig) |
eafa59f6 AA |
1003 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
1004 | np->rx_ring.orig, np->ring_addr); | |
1005 | } else { | |
1006 | if (np->rx_ring.ex) | |
1007 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), | |
1008 | np->rx_ring.ex, np->ring_addr); | |
1009 | } | |
9b03b06b SJ |
1010 | kfree(np->rx_skb); |
1011 | kfree(np->tx_skb); | |
eafa59f6 AA |
1012 | } |
1013 | ||
84b3932b AA |
1014 | static int using_multi_irqs(struct net_device *dev) |
1015 | { | |
1016 | struct fe_priv *np = get_nvpriv(dev); | |
1017 | ||
1018 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || | |
1019 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
1020 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) | |
1021 | return 0; | |
1022 | else | |
1023 | return 1; | |
1024 | } | |
1025 | ||
88d7d8b0 AA |
1026 | static void nv_txrx_gate(struct net_device *dev, bool gate) |
1027 | { | |
1028 | struct fe_priv *np = get_nvpriv(dev); | |
1029 | u8 __iomem *base = get_hwbase(dev); | |
1030 | u32 powerstate; | |
1031 | ||
1032 | if (!np->mac_in_use && | |
1033 | (np->driver_data & DEV_HAS_POWER_CNTRL)) { | |
1034 | powerstate = readl(base + NvRegPowerState2); | |
1035 | if (gate) | |
1036 | powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS; | |
1037 | else | |
1038 | powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS; | |
1039 | writel(powerstate, base + NvRegPowerState2); | |
1040 | } | |
1041 | } | |
1042 | ||
84b3932b AA |
1043 | static void nv_enable_irq(struct net_device *dev) |
1044 | { | |
1045 | struct fe_priv *np = get_nvpriv(dev); | |
1046 | ||
1047 | if (!using_multi_irqs(dev)) { | |
1048 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1049 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1050 | else | |
a7475906 | 1051 | enable_irq(np->pci_dev->irq); |
84b3932b AA |
1052 | } else { |
1053 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1054 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1055 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | static void nv_disable_irq(struct net_device *dev) | |
1060 | { | |
1061 | struct fe_priv *np = get_nvpriv(dev); | |
1062 | ||
1063 | if (!using_multi_irqs(dev)) { | |
1064 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1065 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1066 | else | |
a7475906 | 1067 | disable_irq(np->pci_dev->irq); |
84b3932b AA |
1068 | } else { |
1069 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1070 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1071 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1072 | } | |
1073 | } | |
1074 | ||
1075 | /* In MSIX mode, a write to irqmask behaves as XOR */ | |
1076 | static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) | |
1077 | { | |
1078 | u8 __iomem *base = get_hwbase(dev); | |
1079 | ||
1080 | writel(mask, base + NvRegIrqMask); | |
1081 | } | |
1082 | ||
1083 | static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) | |
1084 | { | |
1085 | struct fe_priv *np = get_nvpriv(dev); | |
1086 | u8 __iomem *base = get_hwbase(dev); | |
1087 | ||
1088 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
1089 | writel(mask, base + NvRegIrqMask); | |
1090 | } else { | |
1091 | if (np->msi_flags & NV_MSI_ENABLED) | |
1092 | writel(0, base + NvRegMSIIrqMask); | |
1093 | writel(0, base + NvRegIrqMask); | |
1094 | } | |
1095 | } | |
1096 | ||
08d93575 AA |
1097 | static void nv_napi_enable(struct net_device *dev) |
1098 | { | |
08d93575 AA |
1099 | struct fe_priv *np = get_nvpriv(dev); |
1100 | ||
1101 | napi_enable(&np->napi); | |
08d93575 AA |
1102 | } |
1103 | ||
1104 | static void nv_napi_disable(struct net_device *dev) | |
1105 | { | |
08d93575 AA |
1106 | struct fe_priv *np = get_nvpriv(dev); |
1107 | ||
1108 | napi_disable(&np->napi); | |
08d93575 AA |
1109 | } |
1110 | ||
1da177e4 LT |
1111 | #define MII_READ (-1) |
1112 | /* mii_rw: read/write a register on the PHY. | |
1113 | * | |
1114 | * Caller must guarantee serialization | |
1115 | */ | |
1116 | static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |
1117 | { | |
1118 | u8 __iomem *base = get_hwbase(dev); | |
1119 | u32 reg; | |
1120 | int retval; | |
1121 | ||
eb798428 | 1122 | writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus); |
1da177e4 LT |
1123 | |
1124 | reg = readl(base + NvRegMIIControl); | |
1125 | if (reg & NVREG_MIICTL_INUSE) { | |
1126 | writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); | |
1127 | udelay(NV_MIIBUSY_DELAY); | |
1128 | } | |
1129 | ||
1130 | reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; | |
1131 | if (value != MII_READ) { | |
1132 | writel(value, base + NvRegMIIData); | |
1133 | reg |= NVREG_MIICTL_WRITE; | |
1134 | } | |
1135 | writel(reg, base + NvRegMIIControl); | |
1136 | ||
1137 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, | |
344d0dce | 1138 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) { |
6b80858d JP |
1139 | netdev_dbg(dev, "mii_rw of reg %d at PHY %d timed out\n", |
1140 | miireg, addr); | |
1da177e4 LT |
1141 | retval = -1; |
1142 | } else if (value != MII_READ) { | |
1143 | /* it was a write operation - fewer failures are detectable */ | |
6b80858d JP |
1144 | netdev_dbg(dev, "mii_rw wrote 0x%x to reg %d at PHY %d\n", |
1145 | value, miireg, addr); | |
1da177e4 LT |
1146 | retval = 0; |
1147 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { | |
6b80858d JP |
1148 | netdev_dbg(dev, "mii_rw of reg %d at PHY %d failed\n", |
1149 | miireg, addr); | |
1da177e4 LT |
1150 | retval = -1; |
1151 | } else { | |
1152 | retval = readl(base + NvRegMIIData); | |
6b80858d JP |
1153 | netdev_dbg(dev, "mii_rw read from reg %d at PHY %d: 0x%x\n", |
1154 | miireg, addr, retval); | |
1da177e4 LT |
1155 | } |
1156 | ||
1157 | return retval; | |
1158 | } | |
1159 | ||
edf7e5ec | 1160 | static int phy_reset(struct net_device *dev, u32 bmcr_setup) |
1da177e4 | 1161 | { |
ac9c1897 | 1162 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1163 | u32 miicontrol; |
1164 | unsigned int tries = 0; | |
1165 | ||
edf7e5ec | 1166 | miicontrol = BMCR_RESET | bmcr_setup; |
78aea4fc | 1167 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) |
1da177e4 | 1168 | return -1; |
1da177e4 LT |
1169 | |
1170 | /* wait for 500ms */ | |
1171 | msleep(500); | |
1172 | ||
1173 | /* must wait till reset is deasserted */ | |
1174 | while (miicontrol & BMCR_RESET) { | |
de855b99 | 1175 | usleep_range(10000, 20000); |
1da177e4 LT |
1176 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1177 | /* FIXME: 100 tries seem excessive */ | |
1178 | if (tries++ > 100) | |
1179 | return -1; | |
1180 | } | |
1181 | return 0; | |
1182 | } | |
1183 | ||
c41d41e1 JP |
1184 | static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np) |
1185 | { | |
1186 | static const struct { | |
1187 | int reg; | |
1188 | int init; | |
1189 | } ri[] = { | |
1190 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 }, | |
1191 | { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 }, | |
1192 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 }, | |
1193 | { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 }, | |
1194 | { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 }, | |
1195 | { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 }, | |
1196 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 }, | |
1197 | }; | |
1198 | int i; | |
1199 | ||
1200 | for (i = 0; i < ARRAY_SIZE(ri); i++) { | |
1201 | if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) { | |
1202 | netdev_info(dev, "%s: phy init failed\n", | |
1203 | pci_name(np->pci_dev)); | |
1204 | return PHY_ERROR; | |
1205 | } | |
1206 | } | |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
1da177e4 LT |
1211 | static int phy_init(struct net_device *dev) |
1212 | { | |
1213 | struct fe_priv *np = get_nvpriv(dev); | |
1214 | u8 __iomem *base = get_hwbase(dev); | |
78aea4fc | 1215 | u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000, reg; |
1da177e4 | 1216 | |
edf7e5ec AA |
1217 | /* phy errata for E3016 phy */ |
1218 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | |
1219 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1220 | reg &= ~PHY_MARVELL_E3016_INITMASK; | |
1221 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { | |
1d397f36 JP |
1222 | netdev_info(dev, "%s: phy write to errata reg failed\n", |
1223 | pci_name(np->pci_dev)); | |
edf7e5ec AA |
1224 | return PHY_ERROR; |
1225 | } | |
1226 | } | |
c5e3ae88 | 1227 | if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1228 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1229 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
c41d41e1 | 1230 | if (init_realtek_8211b(dev, np)) |
9f3f7910 | 1231 | return PHY_ERROR; |
c41d41e1 JP |
1232 | } else if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1233 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
22ae03a1 AA |
1234 | u32 powerstate = readl(base + NvRegPowerState2); |
1235 | ||
1236 | /* need to perform hw phy reset */ | |
1237 | powerstate |= NVREG_POWERSTATE2_PHY_RESET; | |
1238 | writel(powerstate, base + NvRegPowerState2); | |
1239 | msleep(25); | |
1240 | ||
1241 | powerstate &= ~NVREG_POWERSTATE2_PHY_RESET; | |
1242 | writel(powerstate, base + NvRegPowerState2); | |
1243 | msleep(25); | |
1244 | ||
1245 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | |
1246 | reg |= PHY_REALTEK_INIT9; | |
1247 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) { | |
1d397f36 JP |
1248 | netdev_info(dev, "%s: phy init failed\n", |
1249 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1250 | return PHY_ERROR; |
1251 | } | |
1252 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) { | |
1d397f36 JP |
1253 | netdev_info(dev, "%s: phy init failed\n", |
1254 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1255 | return PHY_ERROR; |
1256 | } | |
1257 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); | |
1258 | if (!(reg & PHY_REALTEK_INIT11)) { | |
1259 | reg |= PHY_REALTEK_INIT11; | |
1260 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) { | |
1d397f36 JP |
1261 | netdev_info(dev, "%s: phy init failed\n", |
1262 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1263 | return PHY_ERROR; |
1264 | } | |
1265 | } | |
1266 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1d397f36 JP |
1267 | netdev_info(dev, "%s: phy init failed\n", |
1268 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1269 | return PHY_ERROR; |
1270 | } | |
1271 | } | |
9f3f7910 | 1272 | if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
3c2e1c11 | 1273 | if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { |
9f3f7910 AA |
1274 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); |
1275 | phy_reserved |= PHY_REALTEK_INIT7; | |
1276 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { | |
1d397f36 JP |
1277 | netdev_info(dev, "%s: phy init failed\n", |
1278 | pci_name(np->pci_dev)); | |
9f3f7910 AA |
1279 | return PHY_ERROR; |
1280 | } | |
1281 | } | |
c5e3ae88 AA |
1282 | } |
1283 | } | |
edf7e5ec | 1284 | |
1da177e4 LT |
1285 | /* set advertise register */ |
1286 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 1287 | reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); |
1da177e4 | 1288 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1d397f36 JP |
1289 | netdev_info(dev, "%s: phy write to advertise failed\n", |
1290 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1291 | return PHY_ERROR; |
1292 | } | |
1293 | ||
1294 | /* get phy interface type */ | |
1295 | phyinterface = readl(base + NvRegPhyInterface); | |
1296 | ||
1297 | /* see if gigabit phy */ | |
1298 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
1299 | if (mii_status & PHY_GIGABIT) { | |
1300 | np->gigabit = PHY_GIGABIT; | |
eb91f61b | 1301 | mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
1302 | mii_control_1000 &= ~ADVERTISE_1000HALF; |
1303 | if (phyinterface & PHY_RGMII) | |
1304 | mii_control_1000 |= ADVERTISE_1000FULL; | |
1305 | else | |
1306 | mii_control_1000 &= ~ADVERTISE_1000FULL; | |
1307 | ||
eb91f61b | 1308 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1d397f36 JP |
1309 | netdev_info(dev, "%s: phy init failed\n", |
1310 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1311 | return PHY_ERROR; |
1312 | } | |
78aea4fc | 1313 | } else |
1da177e4 LT |
1314 | np->gigabit = 0; |
1315 | ||
edf7e5ec AA |
1316 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1317 | mii_control |= BMCR_ANENABLE; | |
1318 | ||
22ae03a1 AA |
1319 | if (np->phy_oui == PHY_OUI_REALTEK && |
1320 | np->phy_model == PHY_MODEL_REALTEK_8211 && | |
1321 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1322 | /* start autoneg since we already performed hw reset above */ | |
1323 | mii_control |= BMCR_ANRESTART; | |
1324 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | |
1d397f36 JP |
1325 | netdev_info(dev, "%s: phy init failed\n", |
1326 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1327 | return PHY_ERROR; |
1328 | } | |
1329 | } else { | |
1330 | /* reset the phy | |
1331 | * (certain phys need bmcr to be setup with reset) | |
1332 | */ | |
1333 | if (phy_reset(dev, mii_control)) { | |
1d397f36 JP |
1334 | netdev_info(dev, "%s: phy reset failed\n", |
1335 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1336 | return PHY_ERROR; |
1337 | } | |
1da177e4 LT |
1338 | } |
1339 | ||
1340 | /* phy vendor specific configuration */ | |
78aea4fc | 1341 | if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) { |
1da177e4 | 1342 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); |
14a67f3c AA |
1343 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); |
1344 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); | |
1da177e4 | 1345 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
1d397f36 JP |
1346 | netdev_info(dev, "%s: phy init failed\n", |
1347 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1348 | return PHY_ERROR; |
1349 | } | |
1350 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
14a67f3c | 1351 | phy_reserved |= PHY_CICADA_INIT5; |
1da177e4 | 1352 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
1d397f36 JP |
1353 | netdev_info(dev, "%s: phy init failed\n", |
1354 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1355 | return PHY_ERROR; |
1356 | } | |
1357 | } | |
1358 | if (np->phy_oui == PHY_OUI_CICADA) { | |
1359 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | |
14a67f3c | 1360 | phy_reserved |= PHY_CICADA_INIT6; |
1da177e4 | 1361 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
1d397f36 JP |
1362 | netdev_info(dev, "%s: phy init failed\n", |
1363 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1364 | return PHY_ERROR; |
1365 | } | |
1366 | } | |
d215d8a2 AA |
1367 | if (np->phy_oui == PHY_OUI_VITESSE) { |
1368 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) { | |
1d397f36 JP |
1369 | netdev_info(dev, "%s: phy init failed\n", |
1370 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1371 | return PHY_ERROR; |
1372 | } | |
1373 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) { | |
1d397f36 JP |
1374 | netdev_info(dev, "%s: phy init failed\n", |
1375 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1376 | return PHY_ERROR; |
1377 | } | |
1378 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1379 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1d397f36 JP |
1380 | netdev_info(dev, "%s: phy init failed\n", |
1381 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1382 | return PHY_ERROR; |
1383 | } | |
1384 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1385 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1386 | phy_reserved |= PHY_VITESSE_INIT3; | |
1387 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1d397f36 JP |
1388 | netdev_info(dev, "%s: phy init failed\n", |
1389 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1390 | return PHY_ERROR; |
1391 | } | |
1392 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) { | |
1d397f36 JP |
1393 | netdev_info(dev, "%s: phy init failed\n", |
1394 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1395 | return PHY_ERROR; |
1396 | } | |
1397 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { | |
1d397f36 JP |
1398 | netdev_info(dev, "%s: phy init failed\n", |
1399 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1400 | return PHY_ERROR; |
1401 | } | |
1402 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1403 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1404 | phy_reserved |= PHY_VITESSE_INIT3; | |
1405 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1d397f36 JP |
1406 | netdev_info(dev, "%s: phy init failed\n", |
1407 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1408 | return PHY_ERROR; |
1409 | } | |
1410 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1411 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1d397f36 JP |
1412 | netdev_info(dev, "%s: phy init failed\n", |
1413 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1414 | return PHY_ERROR; |
1415 | } | |
1416 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) { | |
1d397f36 JP |
1417 | netdev_info(dev, "%s: phy init failed\n", |
1418 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1419 | return PHY_ERROR; |
1420 | } | |
1421 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) { | |
1d397f36 JP |
1422 | netdev_info(dev, "%s: phy init failed\n", |
1423 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1424 | return PHY_ERROR; |
1425 | } | |
1426 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1427 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1d397f36 JP |
1428 | netdev_info(dev, "%s: phy init failed\n", |
1429 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1430 | return PHY_ERROR; |
1431 | } | |
1432 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1433 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; | |
1434 | phy_reserved |= PHY_VITESSE_INIT8; | |
1435 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1d397f36 JP |
1436 | netdev_info(dev, "%s: phy init failed\n", |
1437 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1438 | return PHY_ERROR; |
1439 | } | |
1440 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) { | |
1d397f36 JP |
1441 | netdev_info(dev, "%s: phy init failed\n", |
1442 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1443 | return PHY_ERROR; |
1444 | } | |
1445 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) { | |
1d397f36 JP |
1446 | netdev_info(dev, "%s: phy init failed\n", |
1447 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1448 | return PHY_ERROR; |
1449 | } | |
1450 | } | |
c5e3ae88 | 1451 | if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1452 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1453 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
1454 | /* reset could have cleared these out, set them back */ | |
c41d41e1 | 1455 | if (init_realtek_8211b(dev, np)) |
9f3f7910 | 1456 | return PHY_ERROR; |
c41d41e1 | 1457 | } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
3c2e1c11 | 1458 | if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { |
9f3f7910 AA |
1459 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); |
1460 | phy_reserved |= PHY_REALTEK_INIT7; | |
1461 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { | |
1d397f36 JP |
1462 | netdev_info(dev, "%s: phy init failed\n", |
1463 | pci_name(np->pci_dev)); | |
9f3f7910 AA |
1464 | return PHY_ERROR; |
1465 | } | |
1466 | } | |
1467 | if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
1468 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | |
1d397f36 JP |
1469 | netdev_info(dev, "%s: phy init failed\n", |
1470 | pci_name(np->pci_dev)); | |
9f3f7910 AA |
1471 | return PHY_ERROR; |
1472 | } | |
1473 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | |
1474 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
1475 | phy_reserved |= PHY_REALTEK_INIT3; | |
1476 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) { | |
1d397f36 JP |
1477 | netdev_info(dev, "%s: phy init failed\n", |
1478 | pci_name(np->pci_dev)); | |
9f3f7910 AA |
1479 | return PHY_ERROR; |
1480 | } | |
1481 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1d397f36 JP |
1482 | netdev_info(dev, "%s: phy init failed\n", |
1483 | pci_name(np->pci_dev)); | |
9f3f7910 AA |
1484 | return PHY_ERROR; |
1485 | } | |
1486 | } | |
c5e3ae88 AA |
1487 | } |
1488 | } | |
1489 | ||
eb91f61b AA |
1490 | /* some phys clear out pause advertisment on reset, set it back */ |
1491 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); | |
1da177e4 | 1492 | |
cb52deba | 1493 | /* restart auto negotiation, power down phy */ |
1da177e4 | 1494 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
5a9a8e32 | 1495 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
78aea4fc | 1496 | if (phy_power_down) |
5a9a8e32 | 1497 | mii_control |= BMCR_PDOWN; |
78aea4fc | 1498 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) |
1da177e4 | 1499 | return PHY_ERROR; |
1da177e4 LT |
1500 | |
1501 | return 0; | |
1502 | } | |
1503 | ||
1504 | static void nv_start_rx(struct net_device *dev) | |
1505 | { | |
ac9c1897 | 1506 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1507 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1508 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 | 1509 | |
6b80858d | 1510 | netdev_dbg(dev, "%s\n", __func__); |
1da177e4 | 1511 | /* Already running? Stop it. */ |
f35723ec AA |
1512 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1513 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1514 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1515 | pci_push(base); |
1516 | } | |
1517 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
1518 | pci_push(base); | |
78aea4fc SJ |
1519 | rx_ctrl |= NVREG_RCVCTL_START; |
1520 | if (np->mac_in_use) | |
f35723ec AA |
1521 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; |
1522 | writel(rx_ctrl, base + NvRegReceiverControl); | |
6b80858d JP |
1523 | netdev_dbg(dev, "%s: duplex %d, speed 0x%08x\n", |
1524 | __func__, np->duplex, np->linkspeed); | |
1da177e4 LT |
1525 | pci_push(base); |
1526 | } | |
1527 | ||
1528 | static void nv_stop_rx(struct net_device *dev) | |
1529 | { | |
f35723ec | 1530 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1531 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1532 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 | 1533 | |
6b80858d | 1534 | netdev_dbg(dev, "%s\n", __func__); |
f35723ec AA |
1535 | if (!np->mac_in_use) |
1536 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1537 | else | |
1538 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; | |
1539 | writel(rx_ctrl, base + NvRegReceiverControl); | |
344d0dce JP |
1540 | if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1541 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX)) | |
1d397f36 JP |
1542 | netdev_info(dev, "%s: ReceiverStatus remained busy\n", |
1543 | __func__); | |
1da177e4 LT |
1544 | |
1545 | udelay(NV_RXSTOP_DELAY2); | |
f35723ec AA |
1546 | if (!np->mac_in_use) |
1547 | writel(0, base + NvRegLinkSpeed); | |
1da177e4 LT |
1548 | } |
1549 | ||
1550 | static void nv_start_tx(struct net_device *dev) | |
1551 | { | |
f35723ec | 1552 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1553 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1554 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 | 1555 | |
6b80858d | 1556 | netdev_dbg(dev, "%s\n", __func__); |
f35723ec AA |
1557 | tx_ctrl |= NVREG_XMITCTL_START; |
1558 | if (np->mac_in_use) | |
1559 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; | |
1560 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1561 | pci_push(base); |
1562 | } | |
1563 | ||
1564 | static void nv_stop_tx(struct net_device *dev) | |
1565 | { | |
f35723ec | 1566 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1567 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1568 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 | 1569 | |
6b80858d | 1570 | netdev_dbg(dev, "%s\n", __func__); |
f35723ec AA |
1571 | if (!np->mac_in_use) |
1572 | tx_ctrl &= ~NVREG_XMITCTL_START; | |
1573 | else | |
1574 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; | |
1575 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
344d0dce JP |
1576 | if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1577 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX)) | |
1d397f36 JP |
1578 | netdev_info(dev, "%s: TransmitterStatus remained busy\n", |
1579 | __func__); | |
1da177e4 LT |
1580 | |
1581 | udelay(NV_TXSTOP_DELAY2); | |
f35723ec AA |
1582 | if (!np->mac_in_use) |
1583 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, | |
1584 | base + NvRegTransmitPoll); | |
1da177e4 LT |
1585 | } |
1586 | ||
36b30ea9 JG |
1587 | static void nv_start_rxtx(struct net_device *dev) |
1588 | { | |
1589 | nv_start_rx(dev); | |
1590 | nv_start_tx(dev); | |
1591 | } | |
1592 | ||
1593 | static void nv_stop_rxtx(struct net_device *dev) | |
1594 | { | |
1595 | nv_stop_rx(dev); | |
1596 | nv_stop_tx(dev); | |
1597 | } | |
1598 | ||
1da177e4 LT |
1599 | static void nv_txrx_reset(struct net_device *dev) |
1600 | { | |
ac9c1897 | 1601 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1602 | u8 __iomem *base = get_hwbase(dev); |
1603 | ||
6b80858d | 1604 | netdev_dbg(dev, "%s\n", __func__); |
8a4ae7f2 | 1605 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1606 | pci_push(base); |
1607 | udelay(NV_TXRX_RESET_DELAY); | |
8a4ae7f2 | 1608 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1609 | pci_push(base); |
1610 | } | |
1611 | ||
86a0f043 AA |
1612 | static void nv_mac_reset(struct net_device *dev) |
1613 | { | |
1614 | struct fe_priv *np = netdev_priv(dev); | |
1615 | u8 __iomem *base = get_hwbase(dev); | |
4e84f9b1 | 1616 | u32 temp1, temp2, temp3; |
86a0f043 | 1617 | |
6b80858d | 1618 | netdev_dbg(dev, "%s\n", __func__); |
4e84f9b1 | 1619 | |
86a0f043 AA |
1620 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1621 | pci_push(base); | |
4e84f9b1 AA |
1622 | |
1623 | /* save registers since they will be cleared on reset */ | |
1624 | temp1 = readl(base + NvRegMacAddrA); | |
1625 | temp2 = readl(base + NvRegMacAddrB); | |
1626 | temp3 = readl(base + NvRegTransmitPoll); | |
1627 | ||
86a0f043 AA |
1628 | writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); |
1629 | pci_push(base); | |
1630 | udelay(NV_MAC_RESET_DELAY); | |
1631 | writel(0, base + NvRegMacReset); | |
1632 | pci_push(base); | |
1633 | udelay(NV_MAC_RESET_DELAY); | |
4e84f9b1 AA |
1634 | |
1635 | /* restore saved registers */ | |
1636 | writel(temp1, base + NvRegMacAddrA); | |
1637 | writel(temp2, base + NvRegMacAddrB); | |
1638 | writel(temp3, base + NvRegTransmitPoll); | |
1639 | ||
86a0f043 AA |
1640 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1641 | pci_push(base); | |
1642 | } | |
1643 | ||
57fff698 AA |
1644 | static void nv_get_hw_stats(struct net_device *dev) |
1645 | { | |
1646 | struct fe_priv *np = netdev_priv(dev); | |
1647 | u8 __iomem *base = get_hwbase(dev); | |
1648 | ||
1649 | np->estats.tx_bytes += readl(base + NvRegTxCnt); | |
1650 | np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); | |
1651 | np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); | |
1652 | np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); | |
1653 | np->estats.tx_late_collision += readl(base + NvRegTxLateCol); | |
1654 | np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); | |
1655 | np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); | |
1656 | np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); | |
1657 | np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); | |
1658 | np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); | |
1659 | np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); | |
1660 | np->estats.rx_late_collision += readl(base + NvRegRxLateCol); | |
1661 | np->estats.rx_runt += readl(base + NvRegRxRunt); | |
1662 | np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); | |
1663 | np->estats.rx_over_errors += readl(base + NvRegRxOverflow); | |
1664 | np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); | |
1665 | np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); | |
1666 | np->estats.rx_length_error += readl(base + NvRegRxLenErr); | |
1667 | np->estats.rx_unicast += readl(base + NvRegRxUnicast); | |
1668 | np->estats.rx_multicast += readl(base + NvRegRxMulticast); | |
1669 | np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); | |
1670 | np->estats.rx_packets = | |
1671 | np->estats.rx_unicast + | |
1672 | np->estats.rx_multicast + | |
1673 | np->estats.rx_broadcast; | |
1674 | np->estats.rx_errors_total = | |
1675 | np->estats.rx_crc_errors + | |
1676 | np->estats.rx_over_errors + | |
1677 | np->estats.rx_frame_error + | |
1678 | (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + | |
1679 | np->estats.rx_late_collision + | |
1680 | np->estats.rx_runt + | |
1681 | np->estats.rx_frame_too_long; | |
1682 | np->estats.tx_errors_total = | |
1683 | np->estats.tx_late_collision + | |
1684 | np->estats.tx_fifo_errors + | |
1685 | np->estats.tx_carrier_errors + | |
1686 | np->estats.tx_excess_deferral + | |
1687 | np->estats.tx_retry_error; | |
1688 | ||
1689 | if (np->driver_data & DEV_HAS_STATISTICS_V2) { | |
1690 | np->estats.tx_deferral += readl(base + NvRegTxDef); | |
1691 | np->estats.tx_packets += readl(base + NvRegTxFrame); | |
1692 | np->estats.rx_bytes += readl(base + NvRegRxCnt); | |
1693 | np->estats.tx_pause += readl(base + NvRegTxPause); | |
1694 | np->estats.rx_pause += readl(base + NvRegRxPause); | |
1695 | np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); | |
1696 | } | |
9c662435 AA |
1697 | |
1698 | if (np->driver_data & DEV_HAS_STATISTICS_V3) { | |
1699 | np->estats.tx_unicast += readl(base + NvRegTxUnicast); | |
1700 | np->estats.tx_multicast += readl(base + NvRegTxMulticast); | |
1701 | np->estats.tx_broadcast += readl(base + NvRegTxBroadcast); | |
1702 | } | |
57fff698 AA |
1703 | } |
1704 | ||
1da177e4 LT |
1705 | /* |
1706 | * nv_get_stats: dev->get_stats function | |
1707 | * Get latest stats value from the nic. | |
1708 | * Called with read_lock(&dev_base_lock) held for read - | |
1709 | * only synchronized against unregister_netdevice. | |
1710 | */ | |
1711 | static struct net_device_stats *nv_get_stats(struct net_device *dev) | |
1712 | { | |
ac9c1897 | 1713 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1714 | |
21828163 | 1715 | /* If the nic supports hw counters then retrieve latest values */ |
9c662435 | 1716 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) { |
21828163 AA |
1717 | nv_get_hw_stats(dev); |
1718 | ||
1719 | /* copy to net_device stats */ | |
8148ff45 JG |
1720 | dev->stats.tx_bytes = np->estats.tx_bytes; |
1721 | dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors; | |
1722 | dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors; | |
1723 | dev->stats.rx_crc_errors = np->estats.rx_crc_errors; | |
1724 | dev->stats.rx_over_errors = np->estats.rx_over_errors; | |
1725 | dev->stats.rx_errors = np->estats.rx_errors_total; | |
1726 | dev->stats.tx_errors = np->estats.tx_errors_total; | |
21828163 | 1727 | } |
8148ff45 JG |
1728 | |
1729 | return &dev->stats; | |
1da177e4 LT |
1730 | } |
1731 | ||
1732 | /* | |
1733 | * nv_alloc_rx: fill rx ring entries. | |
1734 | * Return 1 if the allocations for the skbs failed and the | |
1735 | * rx engine is without Available descriptors | |
1736 | */ | |
1737 | static int nv_alloc_rx(struct net_device *dev) | |
1738 | { | |
ac9c1897 | 1739 | struct fe_priv *np = netdev_priv(dev); |
78aea4fc | 1740 | struct ring_desc *less_rx; |
1da177e4 | 1741 | |
86b22b0d AA |
1742 | less_rx = np->get_rx.orig; |
1743 | if (less_rx-- == np->first_rx.orig) | |
1744 | less_rx = np->last_rx.orig; | |
761fcd9e | 1745 | |
86b22b0d AA |
1746 | while (np->put_rx.orig != less_rx) { |
1747 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
1748 | if (skb) { | |
86b22b0d | 1749 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1750 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1751 | skb->data, | |
8b5be268 | 1752 | skb_tailroom(skb), |
4305b541 | 1753 | PCI_DMA_FROMDEVICE); |
8b5be268 | 1754 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
86b22b0d AA |
1755 | np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma); |
1756 | wmb(); | |
1757 | np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); | |
b01867cb | 1758 | if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 1759 | np->put_rx.orig = np->first_rx.orig; |
b01867cb | 1760 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 1761 | np->put_rx_ctx = np->first_rx_ctx; |
78aea4fc | 1762 | } else |
86b22b0d | 1763 | return 1; |
86b22b0d AA |
1764 | } |
1765 | return 0; | |
1766 | } | |
1767 | ||
1768 | static int nv_alloc_rx_optimized(struct net_device *dev) | |
1769 | { | |
1770 | struct fe_priv *np = netdev_priv(dev); | |
78aea4fc | 1771 | struct ring_desc_ex *less_rx; |
86b22b0d AA |
1772 | |
1773 | less_rx = np->get_rx.ex; | |
1774 | if (less_rx-- == np->first_rx.ex) | |
1775 | less_rx = np->last_rx.ex; | |
761fcd9e | 1776 | |
86b22b0d AA |
1777 | while (np->put_rx.ex != less_rx) { |
1778 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
0d63fb32 | 1779 | if (skb) { |
761fcd9e | 1780 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1781 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1782 | skb->data, | |
8b5be268 | 1783 | skb_tailroom(skb), |
4305b541 | 1784 | PCI_DMA_FROMDEVICE); |
8b5be268 | 1785 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
5bb7ea26 AV |
1786 | np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma)); |
1787 | np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma)); | |
86b22b0d AA |
1788 | wmb(); |
1789 | np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); | |
b01867cb | 1790 | if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 1791 | np->put_rx.ex = np->first_rx.ex; |
b01867cb | 1792 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
0d63fb32 | 1793 | np->put_rx_ctx = np->first_rx_ctx; |
78aea4fc | 1794 | } else |
0d63fb32 | 1795 | return 1; |
1da177e4 | 1796 | } |
1da177e4 LT |
1797 | return 0; |
1798 | } | |
1799 | ||
e27cdba5 | 1800 | /* If rx bufs are exhausted called after 50ms to attempt to refresh */ |
e27cdba5 SH |
1801 | static void nv_do_rx_refill(unsigned long data) |
1802 | { | |
1803 | struct net_device *dev = (struct net_device *) data; | |
bea3348e | 1804 | struct fe_priv *np = netdev_priv(dev); |
e27cdba5 SH |
1805 | |
1806 | /* Just reschedule NAPI rx processing */ | |
288379f0 | 1807 | napi_schedule(&np->napi); |
e27cdba5 | 1808 | } |
1da177e4 | 1809 | |
f3b197ac | 1810 | static void nv_init_rx(struct net_device *dev) |
1da177e4 | 1811 | { |
ac9c1897 | 1812 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1813 | int i; |
36b30ea9 | 1814 | |
761fcd9e | 1815 | np->get_rx = np->put_rx = np->first_rx = np->rx_ring; |
36b30ea9 JG |
1816 | |
1817 | if (!nv_optimized(np)) | |
761fcd9e AA |
1818 | np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; |
1819 | else | |
1820 | np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; | |
1821 | np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb; | |
1822 | np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; | |
1da177e4 | 1823 | |
761fcd9e | 1824 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1825 | if (!nv_optimized(np)) { |
f82a9352 | 1826 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1827 | np->rx_ring.orig[i].buf = 0; |
1828 | } else { | |
f82a9352 | 1829 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1830 | np->rx_ring.ex[i].txvlan = 0; |
1831 | np->rx_ring.ex[i].bufhigh = 0; | |
1832 | np->rx_ring.ex[i].buflow = 0; | |
1833 | } | |
1834 | np->rx_skb[i].skb = NULL; | |
1835 | np->rx_skb[i].dma = 0; | |
1836 | } | |
d81c0983 MS |
1837 | } |
1838 | ||
1839 | static void nv_init_tx(struct net_device *dev) | |
1840 | { | |
ac9c1897 | 1841 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 | 1842 | int i; |
36b30ea9 | 1843 | |
761fcd9e | 1844 | np->get_tx = np->put_tx = np->first_tx = np->tx_ring; |
36b30ea9 JG |
1845 | |
1846 | if (!nv_optimized(np)) | |
761fcd9e AA |
1847 | np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; |
1848 | else | |
1849 | np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; | |
1850 | np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb; | |
1851 | np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; | |
3b446c3e AA |
1852 | np->tx_pkts_in_progress = 0; |
1853 | np->tx_change_owner = NULL; | |
1854 | np->tx_end_flip = NULL; | |
8f955d7f | 1855 | np->tx_stop = 0; |
d81c0983 | 1856 | |
eafa59f6 | 1857 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1858 | if (!nv_optimized(np)) { |
f82a9352 | 1859 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1860 | np->tx_ring.orig[i].buf = 0; |
1861 | } else { | |
f82a9352 | 1862 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1863 | np->tx_ring.ex[i].txvlan = 0; |
1864 | np->tx_ring.ex[i].bufhigh = 0; | |
1865 | np->tx_ring.ex[i].buflow = 0; | |
1866 | } | |
1867 | np->tx_skb[i].skb = NULL; | |
1868 | np->tx_skb[i].dma = 0; | |
3b446c3e | 1869 | np->tx_skb[i].dma_len = 0; |
73a37079 | 1870 | np->tx_skb[i].dma_single = 0; |
3b446c3e AA |
1871 | np->tx_skb[i].first_tx_desc = NULL; |
1872 | np->tx_skb[i].next_tx_ctx = NULL; | |
ac9c1897 | 1873 | } |
d81c0983 MS |
1874 | } |
1875 | ||
1876 | static int nv_init_ring(struct net_device *dev) | |
1877 | { | |
86b22b0d AA |
1878 | struct fe_priv *np = netdev_priv(dev); |
1879 | ||
d81c0983 MS |
1880 | nv_init_tx(dev); |
1881 | nv_init_rx(dev); | |
36b30ea9 JG |
1882 | |
1883 | if (!nv_optimized(np)) | |
86b22b0d AA |
1884 | return nv_alloc_rx(dev); |
1885 | else | |
1886 | return nv_alloc_rx_optimized(dev); | |
1da177e4 LT |
1887 | } |
1888 | ||
73a37079 | 1889 | static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) |
ac9c1897 | 1890 | { |
761fcd9e | 1891 | if (tx_skb->dma) { |
73a37079 ED |
1892 | if (tx_skb->dma_single) |
1893 | pci_unmap_single(np->pci_dev, tx_skb->dma, | |
1894 | tx_skb->dma_len, | |
1895 | PCI_DMA_TODEVICE); | |
1896 | else | |
1897 | pci_unmap_page(np->pci_dev, tx_skb->dma, | |
1898 | tx_skb->dma_len, | |
1899 | PCI_DMA_TODEVICE); | |
761fcd9e | 1900 | tx_skb->dma = 0; |
fa45459e | 1901 | } |
73a37079 ED |
1902 | } |
1903 | ||
1904 | static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) | |
1905 | { | |
1906 | nv_unmap_txskb(np, tx_skb); | |
761fcd9e AA |
1907 | if (tx_skb->skb) { |
1908 | dev_kfree_skb_any(tx_skb->skb); | |
1909 | tx_skb->skb = NULL; | |
fa45459e | 1910 | return 1; |
ac9c1897 | 1911 | } |
73a37079 | 1912 | return 0; |
ac9c1897 AA |
1913 | } |
1914 | ||
1da177e4 LT |
1915 | static void nv_drain_tx(struct net_device *dev) |
1916 | { | |
ac9c1897 AA |
1917 | struct fe_priv *np = netdev_priv(dev); |
1918 | unsigned int i; | |
f3b197ac | 1919 | |
eafa59f6 | 1920 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1921 | if (!nv_optimized(np)) { |
f82a9352 | 1922 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1923 | np->tx_ring.orig[i].buf = 0; |
1924 | } else { | |
f82a9352 | 1925 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1926 | np->tx_ring.ex[i].txvlan = 0; |
1927 | np->tx_ring.ex[i].bufhigh = 0; | |
1928 | np->tx_ring.ex[i].buflow = 0; | |
1929 | } | |
73a37079 | 1930 | if (nv_release_txskb(np, &np->tx_skb[i])) |
8148ff45 | 1931 | dev->stats.tx_dropped++; |
3b446c3e AA |
1932 | np->tx_skb[i].dma = 0; |
1933 | np->tx_skb[i].dma_len = 0; | |
73a37079 | 1934 | np->tx_skb[i].dma_single = 0; |
3b446c3e AA |
1935 | np->tx_skb[i].first_tx_desc = NULL; |
1936 | np->tx_skb[i].next_tx_ctx = NULL; | |
1da177e4 | 1937 | } |
3b446c3e AA |
1938 | np->tx_pkts_in_progress = 0; |
1939 | np->tx_change_owner = NULL; | |
1940 | np->tx_end_flip = NULL; | |
1da177e4 LT |
1941 | } |
1942 | ||
1943 | static void nv_drain_rx(struct net_device *dev) | |
1944 | { | |
ac9c1897 | 1945 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1946 | int i; |
761fcd9e | 1947 | |
eafa59f6 | 1948 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1949 | if (!nv_optimized(np)) { |
f82a9352 | 1950 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1951 | np->rx_ring.orig[i].buf = 0; |
1952 | } else { | |
f82a9352 | 1953 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1954 | np->rx_ring.ex[i].txvlan = 0; |
1955 | np->rx_ring.ex[i].bufhigh = 0; | |
1956 | np->rx_ring.ex[i].buflow = 0; | |
1957 | } | |
1da177e4 | 1958 | wmb(); |
761fcd9e AA |
1959 | if (np->rx_skb[i].skb) { |
1960 | pci_unmap_single(np->pci_dev, np->rx_skb[i].dma, | |
4305b541 ACM |
1961 | (skb_end_pointer(np->rx_skb[i].skb) - |
1962 | np->rx_skb[i].skb->data), | |
1963 | PCI_DMA_FROMDEVICE); | |
761fcd9e AA |
1964 | dev_kfree_skb(np->rx_skb[i].skb); |
1965 | np->rx_skb[i].skb = NULL; | |
1da177e4 LT |
1966 | } |
1967 | } | |
1968 | } | |
1969 | ||
36b30ea9 | 1970 | static void nv_drain_rxtx(struct net_device *dev) |
1da177e4 LT |
1971 | { |
1972 | nv_drain_tx(dev); | |
1973 | nv_drain_rx(dev); | |
1974 | } | |
1975 | ||
761fcd9e AA |
1976 | static inline u32 nv_get_empty_tx_slots(struct fe_priv *np) |
1977 | { | |
1978 | return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); | |
1979 | } | |
1980 | ||
a433686c AA |
1981 | static void nv_legacybackoff_reseed(struct net_device *dev) |
1982 | { | |
1983 | u8 __iomem *base = get_hwbase(dev); | |
1984 | u32 reg; | |
1985 | u32 low; | |
1986 | int tx_status = 0; | |
1987 | ||
1988 | reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK; | |
1989 | get_random_bytes(&low, sizeof(low)); | |
1990 | reg |= low & NVREG_SLOTTIME_MASK; | |
1991 | ||
1992 | /* Need to stop tx before change takes effect. | |
1993 | * Caller has already gained np->lock. | |
1994 | */ | |
1995 | tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START; | |
1996 | if (tx_status) | |
1997 | nv_stop_tx(dev); | |
1998 | nv_stop_rx(dev); | |
1999 | writel(reg, base + NvRegSlotTime); | |
2000 | if (tx_status) | |
2001 | nv_start_tx(dev); | |
2002 | nv_start_rx(dev); | |
2003 | } | |
2004 | ||
2005 | /* Gear Backoff Seeds */ | |
2006 | #define BACKOFF_SEEDSET_ROWS 8 | |
2007 | #define BACKOFF_SEEDSET_LFSRS 15 | |
2008 | ||
2009 | /* Known Good seed sets */ | |
2010 | static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
78aea4fc SJ |
2011 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, |
2012 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974}, | |
2013 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | |
2014 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974}, | |
2015 | {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984}, | |
2016 | {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984}, | |
2017 | {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84}, | |
2018 | {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} }; | |
a433686c AA |
2019 | |
2020 | static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
78aea4fc SJ |
2021 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, |
2022 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2023 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397}, | |
2024 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2025 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2026 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2027 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2028 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} }; | |
a433686c AA |
2029 | |
2030 | static void nv_gear_backoff_reseed(struct net_device *dev) | |
2031 | { | |
2032 | u8 __iomem *base = get_hwbase(dev); | |
2033 | u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed; | |
2034 | u32 temp, seedset, combinedSeed; | |
2035 | int i; | |
2036 | ||
2037 | /* Setup seed for free running LFSR */ | |
2038 | /* We are going to read the time stamp counter 3 times | |
2039 | and swizzle bits around to increase randomness */ | |
2040 | get_random_bytes(&miniseed1, sizeof(miniseed1)); | |
2041 | miniseed1 &= 0x0fff; | |
2042 | if (miniseed1 == 0) | |
2043 | miniseed1 = 0xabc; | |
2044 | ||
2045 | get_random_bytes(&miniseed2, sizeof(miniseed2)); | |
2046 | miniseed2 &= 0x0fff; | |
2047 | if (miniseed2 == 0) | |
2048 | miniseed2 = 0xabc; | |
2049 | miniseed2_reversed = | |
2050 | ((miniseed2 & 0xF00) >> 8) | | |
2051 | (miniseed2 & 0x0F0) | | |
2052 | ((miniseed2 & 0x00F) << 8); | |
2053 | ||
2054 | get_random_bytes(&miniseed3, sizeof(miniseed3)); | |
2055 | miniseed3 &= 0x0fff; | |
2056 | if (miniseed3 == 0) | |
2057 | miniseed3 = 0xabc; | |
2058 | miniseed3_reversed = | |
2059 | ((miniseed3 & 0xF00) >> 8) | | |
2060 | (miniseed3 & 0x0F0) | | |
2061 | ((miniseed3 & 0x00F) << 8); | |
2062 | ||
2063 | combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) | | |
2064 | (miniseed2 ^ miniseed3_reversed); | |
2065 | ||
2066 | /* Seeds can not be zero */ | |
2067 | if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0) | |
2068 | combinedSeed |= 0x08; | |
2069 | if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0) | |
2070 | combinedSeed |= 0x8000; | |
2071 | ||
2072 | /* No need to disable tx here */ | |
2073 | temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); | |
2074 | temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK; | |
2075 | temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR; | |
78aea4fc | 2076 | writel(temp, base + NvRegBackOffControl); |
a433686c | 2077 | |
78aea4fc | 2078 | /* Setup seeds for all gear LFSRs. */ |
a433686c AA |
2079 | get_random_bytes(&seedset, sizeof(seedset)); |
2080 | seedset = seedset % BACKOFF_SEEDSET_ROWS; | |
78aea4fc | 2081 | for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) { |
a433686c AA |
2082 | temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT); |
2083 | temp |= main_seedset[seedset][i-1] & 0x3ff; | |
2084 | temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); | |
2085 | writel(temp, base + NvRegBackOffControl); | |
2086 | } | |
2087 | } | |
2088 | ||
1da177e4 LT |
2089 | /* |
2090 | * nv_start_xmit: dev->hard_start_xmit function | |
932ff279 | 2091 | * Called with netif_tx_lock held. |
1da177e4 | 2092 | */ |
61357325 | 2093 | static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 2094 | { |
ac9c1897 | 2095 | struct fe_priv *np = netdev_priv(dev); |
fa45459e | 2096 | u32 tx_flags = 0; |
ac9c1897 AA |
2097 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
2098 | unsigned int fragments = skb_shinfo(skb)->nr_frags; | |
ac9c1897 | 2099 | unsigned int i; |
fa45459e AA |
2100 | u32 offset = 0; |
2101 | u32 bcnt; | |
e743d313 | 2102 | u32 size = skb_headlen(skb); |
fa45459e | 2103 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
761fcd9e | 2104 | u32 empty_slots; |
78aea4fc SJ |
2105 | struct ring_desc *put_tx; |
2106 | struct ring_desc *start_tx; | |
2107 | struct ring_desc *prev_tx; | |
2108 | struct nv_skb_map *prev_tx_ctx; | |
bd6ca637 | 2109 | unsigned long flags; |
fa45459e AA |
2110 | |
2111 | /* add fragments to entries count */ | |
2112 | for (i = 0; i < fragments; i++) { | |
2113 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
2114 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2115 | } | |
ac9c1897 | 2116 | |
001eb84b | 2117 | spin_lock_irqsave(&np->lock, flags); |
761fcd9e | 2118 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2119 | if (unlikely(empty_slots <= entries)) { |
ac9c1897 | 2120 | netif_stop_queue(dev); |
aaa37d2d | 2121 | np->tx_stop = 1; |
bd6ca637 | 2122 | spin_unlock_irqrestore(&np->lock, flags); |
ac9c1897 AA |
2123 | return NETDEV_TX_BUSY; |
2124 | } | |
001eb84b | 2125 | spin_unlock_irqrestore(&np->lock, flags); |
1da177e4 | 2126 | |
86b22b0d | 2127 | start_tx = put_tx = np->put_tx.orig; |
761fcd9e | 2128 | |
fa45459e AA |
2129 | /* setup the header buffer */ |
2130 | do { | |
761fcd9e AA |
2131 | prev_tx = put_tx; |
2132 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 2133 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e | 2134 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
fa45459e | 2135 | PCI_DMA_TODEVICE); |
761fcd9e | 2136 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2137 | np->put_tx_ctx->dma_single = 1; |
86b22b0d AA |
2138 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2139 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2140 | |
fa45459e AA |
2141 | tx_flags = np->tx_flags; |
2142 | offset += bcnt; | |
2143 | size -= bcnt; | |
445583b8 | 2144 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 2145 | put_tx = np->first_tx.orig; |
445583b8 | 2146 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2147 | np->put_tx_ctx = np->first_tx_ctx; |
f82a9352 | 2148 | } while (size); |
fa45459e AA |
2149 | |
2150 | /* setup the fragments */ | |
2151 | for (i = 0; i < fragments; i++) { | |
2152 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2153 | u32 size = frag->size; | |
2154 | offset = 0; | |
2155 | ||
2156 | do { | |
761fcd9e AA |
2157 | prev_tx = put_tx; |
2158 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 2159 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e AA |
2160 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
2161 | PCI_DMA_TODEVICE); | |
2162 | np->put_tx_ctx->dma_len = bcnt; | |
73a37079 | 2163 | np->put_tx_ctx->dma_single = 0; |
86b22b0d AA |
2164 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2165 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2166 | |
fa45459e AA |
2167 | offset += bcnt; |
2168 | size -= bcnt; | |
445583b8 | 2169 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 2170 | put_tx = np->first_tx.orig; |
445583b8 | 2171 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2172 | np->put_tx_ctx = np->first_tx_ctx; |
fa45459e AA |
2173 | } while (size); |
2174 | } | |
ac9c1897 | 2175 | |
fa45459e | 2176 | /* set last fragment flag */ |
86b22b0d | 2177 | prev_tx->flaglen |= cpu_to_le32(tx_flags_extra); |
ac9c1897 | 2178 | |
761fcd9e AA |
2179 | /* save skb in this slot's context area */ |
2180 | prev_tx_ctx->skb = skb; | |
fa45459e | 2181 | |
89114afd | 2182 | if (skb_is_gso(skb)) |
7967168c | 2183 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
ac9c1897 | 2184 | else |
1d39ed56 | 2185 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? |
84fa7933 | 2186 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; |
ac9c1897 | 2187 | |
bd6ca637 | 2188 | spin_lock_irqsave(&np->lock, flags); |
164a86e4 | 2189 | |
fa45459e | 2190 | /* set tx flags */ |
86b22b0d AA |
2191 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2192 | np->put_tx.orig = put_tx; | |
1da177e4 | 2193 | |
bd6ca637 | 2194 | spin_unlock_irqrestore(&np->lock, flags); |
761fcd9e | 2195 | |
6b80858d JP |
2196 | netdev_dbg(dev, "%s: entries %d queued for transmission. tx_flags_extra: %x\n", |
2197 | __func__, entries, tx_flags_extra); | |
e649985b JP |
2198 | #ifdef DEBUG |
2199 | print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1, | |
2200 | skb->data, 64, true); | |
2201 | #endif | |
1da177e4 | 2202 | |
8a4ae7f2 | 2203 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
ac9c1897 | 2204 | return NETDEV_TX_OK; |
1da177e4 LT |
2205 | } |
2206 | ||
61357325 SH |
2207 | static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb, |
2208 | struct net_device *dev) | |
86b22b0d AA |
2209 | { |
2210 | struct fe_priv *np = netdev_priv(dev); | |
2211 | u32 tx_flags = 0; | |
445583b8 | 2212 | u32 tx_flags_extra; |
86b22b0d AA |
2213 | unsigned int fragments = skb_shinfo(skb)->nr_frags; |
2214 | unsigned int i; | |
2215 | u32 offset = 0; | |
2216 | u32 bcnt; | |
e743d313 | 2217 | u32 size = skb_headlen(skb); |
86b22b0d AA |
2218 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
2219 | u32 empty_slots; | |
78aea4fc SJ |
2220 | struct ring_desc_ex *put_tx; |
2221 | struct ring_desc_ex *start_tx; | |
2222 | struct ring_desc_ex *prev_tx; | |
2223 | struct nv_skb_map *prev_tx_ctx; | |
2224 | struct nv_skb_map *start_tx_ctx; | |
bd6ca637 | 2225 | unsigned long flags; |
86b22b0d AA |
2226 | |
2227 | /* add fragments to entries count */ | |
2228 | for (i = 0; i < fragments; i++) { | |
2229 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
2230 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2231 | } | |
2232 | ||
001eb84b | 2233 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2234 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2235 | if (unlikely(empty_slots <= entries)) { |
86b22b0d | 2236 | netif_stop_queue(dev); |
aaa37d2d | 2237 | np->tx_stop = 1; |
bd6ca637 | 2238 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2239 | return NETDEV_TX_BUSY; |
2240 | } | |
001eb84b | 2241 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2242 | |
2243 | start_tx = put_tx = np->put_tx.ex; | |
3b446c3e | 2244 | start_tx_ctx = np->put_tx_ctx; |
86b22b0d AA |
2245 | |
2246 | /* setup the header buffer */ | |
2247 | do { | |
2248 | prev_tx = put_tx; | |
2249 | prev_tx_ctx = np->put_tx_ctx; | |
2250 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2251 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, | |
2252 | PCI_DMA_TODEVICE); | |
2253 | np->put_tx_ctx->dma_len = bcnt; | |
73a37079 | 2254 | np->put_tx_ctx->dma_single = 1; |
5bb7ea26 AV |
2255 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2256 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2257 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 AA |
2258 | |
2259 | tx_flags = NV_TX2_VALID; | |
86b22b0d AA |
2260 | offset += bcnt; |
2261 | size -= bcnt; | |
445583b8 | 2262 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2263 | put_tx = np->first_tx.ex; |
445583b8 | 2264 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2265 | np->put_tx_ctx = np->first_tx_ctx; |
2266 | } while (size); | |
2267 | ||
2268 | /* setup the fragments */ | |
2269 | for (i = 0; i < fragments; i++) { | |
2270 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2271 | u32 size = frag->size; | |
2272 | offset = 0; | |
2273 | ||
2274 | do { | |
2275 | prev_tx = put_tx; | |
2276 | prev_tx_ctx = np->put_tx_ctx; | |
2277 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2278 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, | |
2279 | PCI_DMA_TODEVICE); | |
2280 | np->put_tx_ctx->dma_len = bcnt; | |
73a37079 | 2281 | np->put_tx_ctx->dma_single = 0; |
5bb7ea26 AV |
2282 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2283 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2284 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 | 2285 | |
86b22b0d AA |
2286 | offset += bcnt; |
2287 | size -= bcnt; | |
445583b8 | 2288 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2289 | put_tx = np->first_tx.ex; |
445583b8 | 2290 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2291 | np->put_tx_ctx = np->first_tx_ctx; |
2292 | } while (size); | |
2293 | } | |
2294 | ||
2295 | /* set last fragment flag */ | |
445583b8 | 2296 | prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET); |
86b22b0d AA |
2297 | |
2298 | /* save skb in this slot's context area */ | |
2299 | prev_tx_ctx->skb = skb; | |
2300 | ||
2301 | if (skb_is_gso(skb)) | |
2302 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); | |
2303 | else | |
2304 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? | |
2305 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; | |
2306 | ||
2307 | /* vlan tag */ | |
eab6d18d JG |
2308 | if (vlan_tx_tag_present(skb)) |
2309 | start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | | |
2310 | vlan_tx_tag_get(skb)); | |
2311 | else | |
445583b8 | 2312 | start_tx->txvlan = 0; |
86b22b0d | 2313 | |
bd6ca637 | 2314 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2315 | |
3b446c3e AA |
2316 | if (np->tx_limit) { |
2317 | /* Limit the number of outstanding tx. Setup all fragments, but | |
2318 | * do not set the VALID bit on the first descriptor. Save a pointer | |
2319 | * to that descriptor and also for next skb_map element. | |
2320 | */ | |
2321 | ||
2322 | if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) { | |
2323 | if (!np->tx_change_owner) | |
2324 | np->tx_change_owner = start_tx_ctx; | |
2325 | ||
2326 | /* remove VALID bit */ | |
2327 | tx_flags &= ~NV_TX2_VALID; | |
2328 | start_tx_ctx->first_tx_desc = start_tx; | |
2329 | start_tx_ctx->next_tx_ctx = np->put_tx_ctx; | |
2330 | np->tx_end_flip = np->put_tx_ctx; | |
2331 | } else { | |
2332 | np->tx_pkts_in_progress++; | |
2333 | } | |
2334 | } | |
2335 | ||
86b22b0d | 2336 | /* set tx flags */ |
86b22b0d AA |
2337 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2338 | np->put_tx.ex = put_tx; | |
2339 | ||
bd6ca637 | 2340 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d | 2341 | |
6b80858d JP |
2342 | netdev_dbg(dev, "%s: entries %d queued for transmission. tx_flags_extra: %x\n", |
2343 | __func__, entries, tx_flags_extra); | |
e649985b JP |
2344 | #ifdef DEBUG |
2345 | print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1, | |
2346 | skb->data, 64, true); | |
2347 | #endif | |
86b22b0d | 2348 | |
86b22b0d | 2349 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
86b22b0d AA |
2350 | return NETDEV_TX_OK; |
2351 | } | |
2352 | ||
3b446c3e AA |
2353 | static inline void nv_tx_flip_ownership(struct net_device *dev) |
2354 | { | |
2355 | struct fe_priv *np = netdev_priv(dev); | |
2356 | ||
2357 | np->tx_pkts_in_progress--; | |
2358 | if (np->tx_change_owner) { | |
30ecce90 AV |
2359 | np->tx_change_owner->first_tx_desc->flaglen |= |
2360 | cpu_to_le32(NV_TX2_VALID); | |
3b446c3e AA |
2361 | np->tx_pkts_in_progress++; |
2362 | ||
2363 | np->tx_change_owner = np->tx_change_owner->next_tx_ctx; | |
2364 | if (np->tx_change_owner == np->tx_end_flip) | |
2365 | np->tx_change_owner = NULL; | |
2366 | ||
2367 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
2368 | } | |
2369 | } | |
2370 | ||
1da177e4 LT |
2371 | /* |
2372 | * nv_tx_done: check for completed packets, release the skbs. | |
2373 | * | |
2374 | * Caller must own np->lock. | |
2375 | */ | |
33912e72 | 2376 | static int nv_tx_done(struct net_device *dev, int limit) |
1da177e4 | 2377 | { |
ac9c1897 | 2378 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2379 | u32 flags; |
33912e72 | 2380 | int tx_work = 0; |
78aea4fc | 2381 | struct ring_desc *orig_get_tx = np->get_tx.orig; |
1da177e4 | 2382 | |
445583b8 | 2383 | while ((np->get_tx.orig != np->put_tx.orig) && |
33912e72 AA |
2384 | !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) && |
2385 | (tx_work < limit)) { | |
1da177e4 | 2386 | |
6b80858d | 2387 | netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags); |
445583b8 | 2388 | |
73a37079 | 2389 | nv_unmap_txskb(np, np->get_tx_ctx); |
445583b8 | 2390 | |
1da177e4 | 2391 | if (np->desc_ver == DESC_VER_1) { |
f82a9352 | 2392 | if (flags & NV_TX_LASTPACKET) { |
445583b8 | 2393 | if (flags & NV_TX_ERROR) { |
f82a9352 | 2394 | if (flags & NV_TX_UNDERFLOW) |
8148ff45 | 2395 | dev->stats.tx_fifo_errors++; |
f82a9352 | 2396 | if (flags & NV_TX_CARRIERLOST) |
8148ff45 | 2397 | dev->stats.tx_carrier_errors++; |
a433686c AA |
2398 | if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK)) |
2399 | nv_legacybackoff_reseed(dev); | |
8148ff45 | 2400 | dev->stats.tx_errors++; |
ac9c1897 | 2401 | } else { |
8148ff45 JG |
2402 | dev->stats.tx_packets++; |
2403 | dev->stats.tx_bytes += np->get_tx_ctx->skb->len; | |
ac9c1897 | 2404 | } |
445583b8 AA |
2405 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2406 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2407 | tx_work++; |
1da177e4 LT |
2408 | } |
2409 | } else { | |
f82a9352 | 2410 | if (flags & NV_TX2_LASTPACKET) { |
445583b8 | 2411 | if (flags & NV_TX2_ERROR) { |
f82a9352 | 2412 | if (flags & NV_TX2_UNDERFLOW) |
8148ff45 | 2413 | dev->stats.tx_fifo_errors++; |
f82a9352 | 2414 | if (flags & NV_TX2_CARRIERLOST) |
8148ff45 | 2415 | dev->stats.tx_carrier_errors++; |
a433686c AA |
2416 | if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) |
2417 | nv_legacybackoff_reseed(dev); | |
8148ff45 | 2418 | dev->stats.tx_errors++; |
ac9c1897 | 2419 | } else { |
8148ff45 JG |
2420 | dev->stats.tx_packets++; |
2421 | dev->stats.tx_bytes += np->get_tx_ctx->skb->len; | |
f3b197ac | 2422 | } |
445583b8 AA |
2423 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2424 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2425 | tx_work++; |
1da177e4 LT |
2426 | } |
2427 | } | |
445583b8 | 2428 | if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) |
86b22b0d | 2429 | np->get_tx.orig = np->first_tx.orig; |
445583b8 | 2430 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2431 | np->get_tx_ctx = np->first_tx_ctx; |
2432 | } | |
445583b8 | 2433 | if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) { |
aaa37d2d | 2434 | np->tx_stop = 0; |
86b22b0d | 2435 | netif_wake_queue(dev); |
aaa37d2d | 2436 | } |
33912e72 | 2437 | return tx_work; |
86b22b0d AA |
2438 | } |
2439 | ||
33912e72 | 2440 | static int nv_tx_done_optimized(struct net_device *dev, int limit) |
86b22b0d AA |
2441 | { |
2442 | struct fe_priv *np = netdev_priv(dev); | |
2443 | u32 flags; | |
33912e72 | 2444 | int tx_work = 0; |
78aea4fc | 2445 | struct ring_desc_ex *orig_get_tx = np->get_tx.ex; |
86b22b0d | 2446 | |
445583b8 | 2447 | while ((np->get_tx.ex != np->put_tx.ex) && |
217d32dc | 2448 | !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) && |
33912e72 | 2449 | (tx_work < limit)) { |
86b22b0d | 2450 | |
6b80858d | 2451 | netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags); |
445583b8 | 2452 | |
73a37079 | 2453 | nv_unmap_txskb(np, np->get_tx_ctx); |
445583b8 | 2454 | |
86b22b0d | 2455 | if (flags & NV_TX2_LASTPACKET) { |
21828163 | 2456 | if (!(flags & NV_TX2_ERROR)) |
8148ff45 | 2457 | dev->stats.tx_packets++; |
a433686c AA |
2458 | else { |
2459 | if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) { | |
2460 | if (np->driver_data & DEV_HAS_GEAR_MODE) | |
2461 | nv_gear_backoff_reseed(dev); | |
2462 | else | |
2463 | nv_legacybackoff_reseed(dev); | |
2464 | } | |
2465 | } | |
2466 | ||
445583b8 AA |
2467 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2468 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2469 | tx_work++; |
3b446c3e | 2470 | |
78aea4fc | 2471 | if (np->tx_limit) |
3b446c3e | 2472 | nv_tx_flip_ownership(dev); |
761fcd9e | 2473 | } |
445583b8 | 2474 | if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) |
86b22b0d | 2475 | np->get_tx.ex = np->first_tx.ex; |
445583b8 | 2476 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2477 | np->get_tx_ctx = np->first_tx_ctx; |
1da177e4 | 2478 | } |
445583b8 | 2479 | if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) { |
aaa37d2d | 2480 | np->tx_stop = 0; |
1da177e4 | 2481 | netif_wake_queue(dev); |
aaa37d2d | 2482 | } |
33912e72 | 2483 | return tx_work; |
1da177e4 LT |
2484 | } |
2485 | ||
2486 | /* | |
2487 | * nv_tx_timeout: dev->tx_timeout function | |
932ff279 | 2488 | * Called with netif_tx_lock held. |
1da177e4 LT |
2489 | */ |
2490 | static void nv_tx_timeout(struct net_device *dev) | |
2491 | { | |
ac9c1897 | 2492 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2493 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 2494 | u32 status; |
8f955d7f AA |
2495 | union ring_type put_tx; |
2496 | int saved_tx_limit; | |
294a554e | 2497 | int i; |
d33a73c8 AA |
2498 | |
2499 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
2500 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2501 | else | |
2502 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
1da177e4 | 2503 | |
1d397f36 | 2504 | netdev_info(dev, "Got tx_timeout. irq: %08x\n", status); |
1da177e4 | 2505 | |
1d397f36 JP |
2506 | netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr); |
2507 | netdev_info(dev, "Dumping tx registers\n"); | |
294a554e | 2508 | for (i = 0; i <= np->register_size; i += 32) { |
1d397f36 JP |
2509 | netdev_info(dev, |
2510 | "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
2511 | i, | |
2512 | readl(base + i + 0), readl(base + i + 4), | |
2513 | readl(base + i + 8), readl(base + i + 12), | |
2514 | readl(base + i + 16), readl(base + i + 20), | |
2515 | readl(base + i + 24), readl(base + i + 28)); | |
2516 | } | |
2517 | netdev_info(dev, "Dumping tx ring\n"); | |
294a554e JP |
2518 | for (i = 0; i < np->tx_ring_size; i += 4) { |
2519 | if (!nv_optimized(np)) { | |
1d397f36 JP |
2520 | netdev_info(dev, |
2521 | "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", | |
2522 | i, | |
2523 | le32_to_cpu(np->tx_ring.orig[i].buf), | |
2524 | le32_to_cpu(np->tx_ring.orig[i].flaglen), | |
2525 | le32_to_cpu(np->tx_ring.orig[i+1].buf), | |
2526 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), | |
2527 | le32_to_cpu(np->tx_ring.orig[i+2].buf), | |
2528 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), | |
2529 | le32_to_cpu(np->tx_ring.orig[i+3].buf), | |
2530 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | |
294a554e | 2531 | } else { |
1d397f36 JP |
2532 | netdev_info(dev, |
2533 | "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", | |
2534 | i, | |
2535 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), | |
2536 | le32_to_cpu(np->tx_ring.ex[i].buflow), | |
2537 | le32_to_cpu(np->tx_ring.ex[i].flaglen), | |
2538 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), | |
2539 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), | |
2540 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), | |
2541 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), | |
2542 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), | |
2543 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), | |
2544 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), | |
2545 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), | |
2546 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | |
c2dba06d MS |
2547 | } |
2548 | } | |
2549 | ||
1da177e4 LT |
2550 | spin_lock_irq(&np->lock); |
2551 | ||
2552 | /* 1) stop tx engine */ | |
2553 | nv_stop_tx(dev); | |
2554 | ||
8f955d7f AA |
2555 | /* 2) complete any outstanding tx and do not give HW any limited tx pkts */ |
2556 | saved_tx_limit = np->tx_limit; | |
2557 | np->tx_limit = 0; /* prevent giving HW any limited pkts */ | |
2558 | np->tx_stop = 0; /* prevent waking tx queue */ | |
36b30ea9 | 2559 | if (!nv_optimized(np)) |
33912e72 | 2560 | nv_tx_done(dev, np->tx_ring_size); |
86b22b0d | 2561 | else |
4e16ed1b | 2562 | nv_tx_done_optimized(dev, np->tx_ring_size); |
1da177e4 | 2563 | |
8f955d7f AA |
2564 | /* save current HW postion */ |
2565 | if (np->tx_change_owner) | |
2566 | put_tx.ex = np->tx_change_owner->first_tx_desc; | |
2567 | else | |
2568 | put_tx = np->put_tx; | |
1da177e4 | 2569 | |
8f955d7f AA |
2570 | /* 3) clear all tx state */ |
2571 | nv_drain_tx(dev); | |
2572 | nv_init_tx(dev); | |
2573 | ||
2574 | /* 4) restore state to current HW position */ | |
2575 | np->get_tx = np->put_tx = put_tx; | |
2576 | np->tx_limit = saved_tx_limit; | |
3ba4d093 | 2577 | |
8f955d7f | 2578 | /* 5) restart tx engine */ |
1da177e4 | 2579 | nv_start_tx(dev); |
8f955d7f | 2580 | netif_wake_queue(dev); |
1da177e4 LT |
2581 | spin_unlock_irq(&np->lock); |
2582 | } | |
2583 | ||
22c6d143 MS |
2584 | /* |
2585 | * Called when the nic notices a mismatch between the actual data len on the | |
2586 | * wire and the len indicated in the 802 header | |
2587 | */ | |
2588 | static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |
2589 | { | |
2590 | int hdrlen; /* length of the 802 header */ | |
2591 | int protolen; /* length as stored in the proto field */ | |
2592 | ||
2593 | /* 1) calculate len according to header */ | |
78aea4fc SJ |
2594 | if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { |
2595 | protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto); | |
22c6d143 MS |
2596 | hdrlen = VLAN_HLEN; |
2597 | } else { | |
78aea4fc | 2598 | protolen = ntohs(((struct ethhdr *)packet)->h_proto); |
22c6d143 MS |
2599 | hdrlen = ETH_HLEN; |
2600 | } | |
6b80858d JP |
2601 | netdev_dbg(dev, "%s: datalen %d, protolen %d, hdrlen %d\n", |
2602 | __func__, datalen, protolen, hdrlen); | |
22c6d143 MS |
2603 | if (protolen > ETH_DATA_LEN) |
2604 | return datalen; /* Value in proto field not a len, no checks possible */ | |
2605 | ||
2606 | protolen += hdrlen; | |
2607 | /* consistency checks: */ | |
2608 | if (datalen > ETH_ZLEN) { | |
2609 | if (datalen >= protolen) { | |
2610 | /* more data on wire than in 802 header, trim of | |
2611 | * additional data. | |
2612 | */ | |
6b80858d JP |
2613 | netdev_dbg(dev, "%s: accepting %d bytes\n", |
2614 | __func__, protolen); | |
22c6d143 MS |
2615 | return protolen; |
2616 | } else { | |
2617 | /* less data on wire than mentioned in header. | |
2618 | * Discard the packet. | |
2619 | */ | |
6b80858d JP |
2620 | netdev_dbg(dev, "%s: discarding long packet\n", |
2621 | __func__); | |
22c6d143 MS |
2622 | return -1; |
2623 | } | |
2624 | } else { | |
2625 | /* short packet. Accept only if 802 values are also short */ | |
2626 | if (protolen > ETH_ZLEN) { | |
6b80858d JP |
2627 | netdev_dbg(dev, "%s: discarding short packet\n", |
2628 | __func__); | |
22c6d143 MS |
2629 | return -1; |
2630 | } | |
6b80858d | 2631 | netdev_dbg(dev, "%s: accepting %d bytes\n", __func__, datalen); |
22c6d143 MS |
2632 | return datalen; |
2633 | } | |
2634 | } | |
2635 | ||
e27cdba5 | 2636 | static int nv_rx_process(struct net_device *dev, int limit) |
1da177e4 | 2637 | { |
ac9c1897 | 2638 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2639 | u32 flags; |
bcb5febb | 2640 | int rx_work = 0; |
b01867cb AA |
2641 | struct sk_buff *skb; |
2642 | int len; | |
1da177e4 | 2643 | |
78aea4fc | 2644 | while ((np->get_rx.orig != np->put_rx.orig) && |
b01867cb | 2645 | !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && |
bcb5febb | 2646 | (rx_work < limit)) { |
1da177e4 | 2647 | |
6b80858d | 2648 | netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags); |
1da177e4 | 2649 | |
1da177e4 LT |
2650 | /* |
2651 | * the packet is for us - immediately tear down the pci mapping. | |
2652 | * TODO: check if a prefetch of the first cacheline improves | |
2653 | * the performance. | |
2654 | */ | |
761fcd9e AA |
2655 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, |
2656 | np->get_rx_ctx->dma_len, | |
1da177e4 | 2657 | PCI_DMA_FROMDEVICE); |
0d63fb32 AA |
2658 | skb = np->get_rx_ctx->skb; |
2659 | np->get_rx_ctx->skb = NULL; | |
1da177e4 | 2660 | |
6b80858d | 2661 | netdev_dbg(dev, "Dumping packet (flags 0x%x)\n", flags); |
e649985b JP |
2662 | #ifdef DEBUG |
2663 | print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, | |
2664 | 16, 1, skb->data, 64, true); | |
2665 | #endif | |
1da177e4 LT |
2666 | /* look at what we actually got: */ |
2667 | if (np->desc_ver == DESC_VER_1) { | |
b01867cb AA |
2668 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { |
2669 | len = flags & LEN_MASK_V1; | |
2670 | if (unlikely(flags & NV_RX_ERROR)) { | |
1ef6841b | 2671 | if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) { |
b01867cb AA |
2672 | len = nv_getlen(dev, skb->data, len); |
2673 | if (len < 0) { | |
8148ff45 | 2674 | dev->stats.rx_errors++; |
b01867cb AA |
2675 | dev_kfree_skb(skb); |
2676 | goto next_pkt; | |
2677 | } | |
2678 | } | |
2679 | /* framing errors are soft errors */ | |
1ef6841b | 2680 | else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) { |
78aea4fc | 2681 | if (flags & NV_RX_SUBSTRACT1) |
b01867cb | 2682 | len--; |
b01867cb AA |
2683 | } |
2684 | /* the rest are hard errors */ | |
2685 | else { | |
2686 | if (flags & NV_RX_MISSEDFRAME) | |
8148ff45 | 2687 | dev->stats.rx_missed_errors++; |
b01867cb | 2688 | if (flags & NV_RX_CRCERR) |
8148ff45 | 2689 | dev->stats.rx_crc_errors++; |
b01867cb | 2690 | if (flags & NV_RX_OVERFLOW) |
8148ff45 JG |
2691 | dev->stats.rx_over_errors++; |
2692 | dev->stats.rx_errors++; | |
0d63fb32 | 2693 | dev_kfree_skb(skb); |
a971c324 AA |
2694 | goto next_pkt; |
2695 | } | |
2696 | } | |
b01867cb | 2697 | } else { |
0d63fb32 | 2698 | dev_kfree_skb(skb); |
1da177e4 | 2699 | goto next_pkt; |
0d63fb32 | 2700 | } |
b01867cb AA |
2701 | } else { |
2702 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | |
2703 | len = flags & LEN_MASK_V2; | |
2704 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2705 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2706 | len = nv_getlen(dev, skb->data, len); |
2707 | if (len < 0) { | |
8148ff45 | 2708 | dev->stats.rx_errors++; |
b01867cb AA |
2709 | dev_kfree_skb(skb); |
2710 | goto next_pkt; | |
2711 | } | |
2712 | } | |
2713 | /* framing errors are soft errors */ | |
1ef6841b | 2714 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
78aea4fc | 2715 | if (flags & NV_RX2_SUBSTRACT1) |
b01867cb | 2716 | len--; |
b01867cb AA |
2717 | } |
2718 | /* the rest are hard errors */ | |
2719 | else { | |
2720 | if (flags & NV_RX2_CRCERR) | |
8148ff45 | 2721 | dev->stats.rx_crc_errors++; |
b01867cb | 2722 | if (flags & NV_RX2_OVERFLOW) |
8148ff45 JG |
2723 | dev->stats.rx_over_errors++; |
2724 | dev->stats.rx_errors++; | |
0d63fb32 | 2725 | dev_kfree_skb(skb); |
a971c324 AA |
2726 | goto next_pkt; |
2727 | } | |
2728 | } | |
bfaffe8f AA |
2729 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2730 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
0d63fb32 | 2731 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2732 | } else { |
2733 | dev_kfree_skb(skb); | |
2734 | goto next_pkt; | |
1da177e4 LT |
2735 | } |
2736 | } | |
2737 | /* got a valid packet - forward it to the network core */ | |
1da177e4 LT |
2738 | skb_put(skb, len); |
2739 | skb->protocol = eth_type_trans(skb, dev); | |
6b80858d JP |
2740 | netdev_dbg(dev, "%s: %d bytes, proto %d accepted\n", |
2741 | __func__, len, skb->protocol); | |
53f224cc | 2742 | napi_gro_receive(&np->napi, skb); |
8148ff45 JG |
2743 | dev->stats.rx_packets++; |
2744 | dev->stats.rx_bytes += len; | |
1da177e4 | 2745 | next_pkt: |
b01867cb | 2746 | if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 2747 | np->get_rx.orig = np->first_rx.orig; |
b01867cb | 2748 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 2749 | np->get_rx_ctx = np->first_rx_ctx; |
bcb5febb IM |
2750 | |
2751 | rx_work++; | |
86b22b0d AA |
2752 | } |
2753 | ||
bcb5febb | 2754 | return rx_work; |
86b22b0d AA |
2755 | } |
2756 | ||
2757 | static int nv_rx_process_optimized(struct net_device *dev, int limit) | |
2758 | { | |
2759 | struct fe_priv *np = netdev_priv(dev); | |
2760 | u32 flags; | |
2761 | u32 vlanflags = 0; | |
c1b7151a | 2762 | int rx_work = 0; |
b01867cb AA |
2763 | struct sk_buff *skb; |
2764 | int len; | |
86b22b0d | 2765 | |
78aea4fc | 2766 | while ((np->get_rx.ex != np->put_rx.ex) && |
b01867cb | 2767 | !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && |
c1b7151a | 2768 | (rx_work < limit)) { |
86b22b0d | 2769 | |
6b80858d | 2770 | netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags); |
86b22b0d | 2771 | |
86b22b0d AA |
2772 | /* |
2773 | * the packet is for us - immediately tear down the pci mapping. | |
2774 | * TODO: check if a prefetch of the first cacheline improves | |
2775 | * the performance. | |
2776 | */ | |
2777 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, | |
2778 | np->get_rx_ctx->dma_len, | |
2779 | PCI_DMA_FROMDEVICE); | |
2780 | skb = np->get_rx_ctx->skb; | |
2781 | np->get_rx_ctx->skb = NULL; | |
2782 | ||
e649985b JP |
2783 | netdev_dbg(dev, "Dumping packet (flags 0x%x)\n", flags); |
2784 | #ifdef DEBUG | |
2785 | print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1, | |
2786 | skb->data, 64, true); | |
2787 | #endif | |
86b22b0d | 2788 | /* look at what we actually got: */ |
b01867cb AA |
2789 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
2790 | len = flags & LEN_MASK_V2; | |
2791 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2792 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2793 | len = nv_getlen(dev, skb->data, len); |
2794 | if (len < 0) { | |
b01867cb AA |
2795 | dev_kfree_skb(skb); |
2796 | goto next_pkt; | |
2797 | } | |
2798 | } | |
2799 | /* framing errors are soft errors */ | |
1ef6841b | 2800 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
78aea4fc | 2801 | if (flags & NV_RX2_SUBSTRACT1) |
b01867cb | 2802 | len--; |
b01867cb AA |
2803 | } |
2804 | /* the rest are hard errors */ | |
2805 | else { | |
86b22b0d AA |
2806 | dev_kfree_skb(skb); |
2807 | goto next_pkt; | |
2808 | } | |
2809 | } | |
b01867cb | 2810 | |
bfaffe8f AA |
2811 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2812 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
86b22b0d | 2813 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2814 | |
2815 | /* got a valid packet - forward it to the network core */ | |
2816 | skb_put(skb, len); | |
2817 | skb->protocol = eth_type_trans(skb, dev); | |
2818 | prefetch(skb->data); | |
2819 | ||
6b80858d JP |
2820 | netdev_dbg(dev, "%s: %d bytes, proto %d accepted\n", |
2821 | __func__, len, skb->protocol); | |
b01867cb AA |
2822 | |
2823 | if (likely(!np->vlangrp)) { | |
53f224cc | 2824 | napi_gro_receive(&np->napi, skb); |
b01867cb AA |
2825 | } else { |
2826 | vlanflags = le32_to_cpu(np->get_rx.ex->buflow); | |
2827 | if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) { | |
53f224cc TH |
2828 | vlan_gro_receive(&np->napi, np->vlangrp, |
2829 | vlanflags & NV_RX3_VLAN_TAG_MASK, skb); | |
b01867cb | 2830 | } else { |
53f224cc | 2831 | napi_gro_receive(&np->napi, skb); |
b01867cb AA |
2832 | } |
2833 | } | |
2834 | ||
8148ff45 JG |
2835 | dev->stats.rx_packets++; |
2836 | dev->stats.rx_bytes += len; | |
b01867cb AA |
2837 | } else { |
2838 | dev_kfree_skb(skb); | |
2839 | } | |
86b22b0d | 2840 | next_pkt: |
b01867cb | 2841 | if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 2842 | np->get_rx.ex = np->first_rx.ex; |
b01867cb | 2843 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
761fcd9e | 2844 | np->get_rx_ctx = np->first_rx_ctx; |
c1b7151a IM |
2845 | |
2846 | rx_work++; | |
1da177e4 | 2847 | } |
e27cdba5 | 2848 | |
c1b7151a | 2849 | return rx_work; |
1da177e4 LT |
2850 | } |
2851 | ||
d81c0983 MS |
2852 | static void set_bufsize(struct net_device *dev) |
2853 | { | |
2854 | struct fe_priv *np = netdev_priv(dev); | |
2855 | ||
2856 | if (dev->mtu <= ETH_DATA_LEN) | |
2857 | np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; | |
2858 | else | |
2859 | np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; | |
2860 | } | |
2861 | ||
1da177e4 LT |
2862 | /* |
2863 | * nv_change_mtu: dev->change_mtu function | |
2864 | * Called with dev_base_lock held for read. | |
2865 | */ | |
2866 | static int nv_change_mtu(struct net_device *dev, int new_mtu) | |
2867 | { | |
ac9c1897 | 2868 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 MS |
2869 | int old_mtu; |
2870 | ||
2871 | if (new_mtu < 64 || new_mtu > np->pkt_limit) | |
1da177e4 | 2872 | return -EINVAL; |
d81c0983 MS |
2873 | |
2874 | old_mtu = dev->mtu; | |
1da177e4 | 2875 | dev->mtu = new_mtu; |
d81c0983 MS |
2876 | |
2877 | /* return early if the buffer sizes will not change */ | |
2878 | if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) | |
2879 | return 0; | |
2880 | if (old_mtu == new_mtu) | |
2881 | return 0; | |
2882 | ||
2883 | /* synchronized against open : rtnl_lock() held by caller */ | |
2884 | if (netif_running(dev)) { | |
25097d4b | 2885 | u8 __iomem *base = get_hwbase(dev); |
d81c0983 MS |
2886 | /* |
2887 | * It seems that the nic preloads valid ring entries into an | |
2888 | * internal buffer. The procedure for flushing everything is | |
2889 | * guessed, there is probably a simpler approach. | |
2890 | * Changing the MTU is a rare event, it shouldn't matter. | |
2891 | */ | |
84b3932b | 2892 | nv_disable_irq(dev); |
08d93575 | 2893 | nv_napi_disable(dev); |
932ff279 | 2894 | netif_tx_lock_bh(dev); |
e308a5d8 | 2895 | netif_addr_lock(dev); |
d81c0983 MS |
2896 | spin_lock(&np->lock); |
2897 | /* stop engines */ | |
36b30ea9 | 2898 | nv_stop_rxtx(dev); |
d81c0983 MS |
2899 | nv_txrx_reset(dev); |
2900 | /* drain rx queue */ | |
36b30ea9 | 2901 | nv_drain_rxtx(dev); |
d81c0983 | 2902 | /* reinit driver view of the rx queue */ |
d81c0983 | 2903 | set_bufsize(dev); |
eafa59f6 | 2904 | if (nv_init_ring(dev)) { |
d81c0983 MS |
2905 | if (!np->in_shutdown) |
2906 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
2907 | } | |
2908 | /* reinit nic view of the rx queue */ | |
2909 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
0832b25a | 2910 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
78aea4fc | 2911 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
d81c0983 MS |
2912 | base + NvRegRingSizes); |
2913 | pci_push(base); | |
8a4ae7f2 | 2914 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
d81c0983 MS |
2915 | pci_push(base); |
2916 | ||
2917 | /* restart rx engine */ | |
36b30ea9 | 2918 | nv_start_rxtx(dev); |
d81c0983 | 2919 | spin_unlock(&np->lock); |
e308a5d8 | 2920 | netif_addr_unlock(dev); |
932ff279 | 2921 | netif_tx_unlock_bh(dev); |
08d93575 | 2922 | nv_napi_enable(dev); |
84b3932b | 2923 | nv_enable_irq(dev); |
d81c0983 | 2924 | } |
1da177e4 LT |
2925 | return 0; |
2926 | } | |
2927 | ||
72b31782 MS |
2928 | static void nv_copy_mac_to_hw(struct net_device *dev) |
2929 | { | |
25097d4b | 2930 | u8 __iomem *base = get_hwbase(dev); |
72b31782 MS |
2931 | u32 mac[2]; |
2932 | ||
2933 | mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + | |
2934 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); | |
2935 | mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); | |
2936 | ||
2937 | writel(mac[0], base + NvRegMacAddrA); | |
2938 | writel(mac[1], base + NvRegMacAddrB); | |
2939 | } | |
2940 | ||
2941 | /* | |
2942 | * nv_set_mac_address: dev->set_mac_address function | |
2943 | * Called with rtnl_lock() held. | |
2944 | */ | |
2945 | static int nv_set_mac_address(struct net_device *dev, void *addr) | |
2946 | { | |
ac9c1897 | 2947 | struct fe_priv *np = netdev_priv(dev); |
78aea4fc | 2948 | struct sockaddr *macaddr = (struct sockaddr *)addr; |
72b31782 | 2949 | |
f82a9352 | 2950 | if (!is_valid_ether_addr(macaddr->sa_data)) |
72b31782 MS |
2951 | return -EADDRNOTAVAIL; |
2952 | ||
2953 | /* synchronized against open : rtnl_lock() held by caller */ | |
2954 | memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); | |
2955 | ||
2956 | if (netif_running(dev)) { | |
932ff279 | 2957 | netif_tx_lock_bh(dev); |
e308a5d8 | 2958 | netif_addr_lock(dev); |
72b31782 MS |
2959 | spin_lock_irq(&np->lock); |
2960 | ||
2961 | /* stop rx engine */ | |
2962 | nv_stop_rx(dev); | |
2963 | ||
2964 | /* set mac address */ | |
2965 | nv_copy_mac_to_hw(dev); | |
2966 | ||
2967 | /* restart rx engine */ | |
2968 | nv_start_rx(dev); | |
2969 | spin_unlock_irq(&np->lock); | |
e308a5d8 | 2970 | netif_addr_unlock(dev); |
932ff279 | 2971 | netif_tx_unlock_bh(dev); |
72b31782 MS |
2972 | } else { |
2973 | nv_copy_mac_to_hw(dev); | |
2974 | } | |
2975 | return 0; | |
2976 | } | |
2977 | ||
1da177e4 LT |
2978 | /* |
2979 | * nv_set_multicast: dev->set_multicast function | |
932ff279 | 2980 | * Called with netif_tx_lock held. |
1da177e4 LT |
2981 | */ |
2982 | static void nv_set_multicast(struct net_device *dev) | |
2983 | { | |
ac9c1897 | 2984 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
2985 | u8 __iomem *base = get_hwbase(dev); |
2986 | u32 addr[2]; | |
2987 | u32 mask[2]; | |
b6d0773f | 2988 | u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; |
1da177e4 LT |
2989 | |
2990 | memset(addr, 0, sizeof(addr)); | |
2991 | memset(mask, 0, sizeof(mask)); | |
2992 | ||
2993 | if (dev->flags & IFF_PROMISC) { | |
b6d0773f | 2994 | pff |= NVREG_PFF_PROMISC; |
1da177e4 | 2995 | } else { |
b6d0773f | 2996 | pff |= NVREG_PFF_MYADDR; |
1da177e4 | 2997 | |
48e2f183 | 2998 | if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) { |
1da177e4 LT |
2999 | u32 alwaysOff[2]; |
3000 | u32 alwaysOn[2]; | |
3001 | ||
3002 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; | |
3003 | if (dev->flags & IFF_ALLMULTI) { | |
3004 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; | |
3005 | } else { | |
22bedad3 | 3006 | struct netdev_hw_addr *ha; |
1da177e4 | 3007 | |
22bedad3 JP |
3008 | netdev_for_each_mc_addr(ha, dev) { |
3009 | unsigned char *addr = ha->addr; | |
1da177e4 | 3010 | u32 a, b; |
22bedad3 JP |
3011 | |
3012 | a = le32_to_cpu(*(__le32 *) addr); | |
3013 | b = le16_to_cpu(*(__le16 *) (&addr[4])); | |
1da177e4 LT |
3014 | alwaysOn[0] &= a; |
3015 | alwaysOff[0] &= ~a; | |
3016 | alwaysOn[1] &= b; | |
3017 | alwaysOff[1] &= ~b; | |
1da177e4 LT |
3018 | } |
3019 | } | |
3020 | addr[0] = alwaysOn[0]; | |
3021 | addr[1] = alwaysOn[1]; | |
3022 | mask[0] = alwaysOn[0] | alwaysOff[0]; | |
3023 | mask[1] = alwaysOn[1] | alwaysOff[1]; | |
bb9a4fd1 AA |
3024 | } else { |
3025 | mask[0] = NVREG_MCASTMASKA_NONE; | |
3026 | mask[1] = NVREG_MCASTMASKB_NONE; | |
1da177e4 LT |
3027 | } |
3028 | } | |
3029 | addr[0] |= NVREG_MCASTADDRA_FORCE; | |
3030 | pff |= NVREG_PFF_ALWAYS; | |
3031 | spin_lock_irq(&np->lock); | |
3032 | nv_stop_rx(dev); | |
3033 | writel(addr[0], base + NvRegMulticastAddrA); | |
3034 | writel(addr[1], base + NvRegMulticastAddrB); | |
3035 | writel(mask[0], base + NvRegMulticastMaskA); | |
3036 | writel(mask[1], base + NvRegMulticastMaskB); | |
3037 | writel(pff, base + NvRegPacketFilterFlags); | |
f52dafc1 | 3038 | netdev_dbg(dev, "reconfiguration for multicast lists\n"); |
1da177e4 LT |
3039 | nv_start_rx(dev); |
3040 | spin_unlock_irq(&np->lock); | |
3041 | } | |
3042 | ||
c7985051 | 3043 | static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
b6d0773f AA |
3044 | { |
3045 | struct fe_priv *np = netdev_priv(dev); | |
3046 | u8 __iomem *base = get_hwbase(dev); | |
3047 | ||
3048 | np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); | |
3049 | ||
3050 | if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { | |
3051 | u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; | |
3052 | if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) { | |
3053 | writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); | |
3054 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3055 | } else { | |
3056 | writel(pff, base + NvRegPacketFilterFlags); | |
3057 | } | |
3058 | } | |
3059 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { | |
3060 | u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; | |
3061 | if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) { | |
5289b4c4 AA |
3062 | u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; |
3063 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) | |
3064 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; | |
9a33e883 | 3065 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) { |
5289b4c4 | 3066 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; |
9a33e883 AA |
3067 | /* limit the number of tx pause frames to a default of 8 */ |
3068 | writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit); | |
3069 | } | |
5289b4c4 | 3070 | writel(pause_enable, base + NvRegTxPauseFrame); |
b6d0773f AA |
3071 | writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); |
3072 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3073 | } else { | |
3074 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
3075 | writel(regmisc, base + NvRegMisc1); | |
3076 | } | |
3077 | } | |
3078 | } | |
3079 | ||
4ea7f299 AA |
3080 | /** |
3081 | * nv_update_linkspeed: Setup the MAC according to the link partner | |
3082 | * @dev: Network device to be configured | |
3083 | * | |
3084 | * The function queries the PHY and checks if there is a link partner. | |
3085 | * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is | |
3086 | * set to 10 MBit HD. | |
3087 | * | |
3088 | * The function returns 0 if there is no link partner and 1 if there is | |
3089 | * a good link partner. | |
3090 | */ | |
1da177e4 LT |
3091 | static int nv_update_linkspeed(struct net_device *dev) |
3092 | { | |
ac9c1897 | 3093 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3094 | u8 __iomem *base = get_hwbase(dev); |
eb91f61b AA |
3095 | int adv = 0; |
3096 | int lpa = 0; | |
3097 | int adv_lpa, adv_pause, lpa_pause; | |
1da177e4 LT |
3098 | int newls = np->linkspeed; |
3099 | int newdup = np->duplex; | |
3100 | int mii_status; | |
3101 | int retval = 0; | |
9744e218 | 3102 | u32 control_1000, status_1000, phyreg, pause_flags, txreg; |
b2976d23 | 3103 | u32 txrxFlags = 0; |
fd9b558c | 3104 | u32 phy_exp; |
1da177e4 LT |
3105 | |
3106 | /* BMSR_LSTATUS is latched, read it twice: | |
3107 | * we want the current value. | |
3108 | */ | |
3109 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3110 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3111 | ||
3112 | if (!(mii_status & BMSR_LSTATUS)) { | |
6b80858d JP |
3113 | netdev_dbg(dev, |
3114 | "no link detected by phy - falling back to 10HD\n"); | |
1da177e4 LT |
3115 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3116 | newdup = 0; | |
3117 | retval = 0; | |
3118 | goto set_speed; | |
3119 | } | |
3120 | ||
3121 | if (np->autoneg == 0) { | |
6b80858d JP |
3122 | netdev_dbg(dev, "%s: autoneg off, PHY set to 0x%04x\n", |
3123 | __func__, np->fixed_mode); | |
1da177e4 LT |
3124 | if (np->fixed_mode & LPA_100FULL) { |
3125 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3126 | newdup = 1; | |
3127 | } else if (np->fixed_mode & LPA_100HALF) { | |
3128 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3129 | newdup = 0; | |
3130 | } else if (np->fixed_mode & LPA_10FULL) { | |
3131 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3132 | newdup = 1; | |
3133 | } else { | |
3134 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3135 | newdup = 0; | |
3136 | } | |
3137 | retval = 1; | |
3138 | goto set_speed; | |
3139 | } | |
3140 | /* check auto negotiation is complete */ | |
3141 | if (!(mii_status & BMSR_ANEGCOMPLETE)) { | |
3142 | /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ | |
3143 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3144 | newdup = 0; | |
3145 | retval = 0; | |
6b80858d JP |
3146 | netdev_dbg(dev, |
3147 | "autoneg not completed - falling back to 10HD\n"); | |
1da177e4 LT |
3148 | goto set_speed; |
3149 | } | |
3150 | ||
b6d0773f AA |
3151 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
3152 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); | |
6b80858d JP |
3153 | netdev_dbg(dev, "%s: PHY advertises 0x%04x, lpa 0x%04x\n", |
3154 | __func__, adv, lpa); | |
b6d0773f | 3155 | |
1da177e4 LT |
3156 | retval = 1; |
3157 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b AA |
3158 | control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
3159 | status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); | |
1da177e4 LT |
3160 | |
3161 | if ((control_1000 & ADVERTISE_1000FULL) && | |
3162 | (status_1000 & LPA_1000FULL)) { | |
6b80858d JP |
3163 | netdev_dbg(dev, "%s: GBit ethernet detected\n", |
3164 | __func__); | |
1da177e4 LT |
3165 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; |
3166 | newdup = 1; | |
3167 | goto set_speed; | |
3168 | } | |
3169 | } | |
3170 | ||
1da177e4 | 3171 | /* FIXME: handle parallel detection properly */ |
eb91f61b AA |
3172 | adv_lpa = lpa & adv; |
3173 | if (adv_lpa & LPA_100FULL) { | |
1da177e4 LT |
3174 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3175 | newdup = 1; | |
eb91f61b | 3176 | } else if (adv_lpa & LPA_100HALF) { |
1da177e4 LT |
3177 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3178 | newdup = 0; | |
eb91f61b | 3179 | } else if (adv_lpa & LPA_10FULL) { |
1da177e4 LT |
3180 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3181 | newdup = 1; | |
eb91f61b | 3182 | } else if (adv_lpa & LPA_10HALF) { |
1da177e4 LT |
3183 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3184 | newdup = 0; | |
3185 | } else { | |
6b80858d JP |
3186 | netdev_dbg(dev, "bad ability %04x - falling back to 10HD\n", |
3187 | adv_lpa); | |
1da177e4 LT |
3188 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3189 | newdup = 0; | |
3190 | } | |
3191 | ||
3192 | set_speed: | |
3193 | if (np->duplex == newdup && np->linkspeed == newls) | |
3194 | return retval; | |
3195 | ||
f52dafc1 JP |
3196 | netdev_dbg(dev, "changing link setting from %d/%d to %d/%d\n", |
3197 | np->linkspeed, np->duplex, newls, newdup); | |
1da177e4 LT |
3198 | |
3199 | np->duplex = newdup; | |
3200 | np->linkspeed = newls; | |
3201 | ||
b2976d23 AA |
3202 | /* The transmitter and receiver must be restarted for safe update */ |
3203 | if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) { | |
3204 | txrxFlags |= NV_RESTART_TX; | |
3205 | nv_stop_tx(dev); | |
3206 | } | |
3207 | if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { | |
3208 | txrxFlags |= NV_RESTART_RX; | |
3209 | nv_stop_rx(dev); | |
3210 | } | |
3211 | ||
1da177e4 | 3212 | if (np->gigabit == PHY_GIGABIT) { |
a433686c | 3213 | phyreg = readl(base + NvRegSlotTime); |
1da177e4 | 3214 | phyreg &= ~(0x3FF00); |
a433686c AA |
3215 | if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) || |
3216 | ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)) | |
3217 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
1da177e4 | 3218 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
a433686c AA |
3219 | phyreg |= NVREG_SLOTTIME_1000_FULL; |
3220 | writel(phyreg, base + NvRegSlotTime); | |
1da177e4 LT |
3221 | } |
3222 | ||
3223 | phyreg = readl(base + NvRegPhyInterface); | |
3224 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
3225 | if (np->duplex == 0) | |
3226 | phyreg |= PHY_HALF; | |
3227 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
3228 | phyreg |= PHY_100; | |
3229 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3230 | phyreg |= PHY_1000; | |
3231 | writel(phyreg, base + NvRegPhyInterface); | |
3232 | ||
fd9b558c | 3233 | phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ |
9744e218 | 3234 | if (phyreg & PHY_RGMII) { |
fd9b558c | 3235 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) { |
9744e218 | 3236 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; |
fd9b558c AA |
3237 | } else { |
3238 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) { | |
3239 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10) | |
3240 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10; | |
3241 | else | |
3242 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100; | |
3243 | } else { | |
3244 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | |
3245 | } | |
3246 | } | |
9744e218 | 3247 | } else { |
fd9b558c AA |
3248 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) |
3249 | txreg = NVREG_TX_DEFERRAL_MII_STRETCH; | |
3250 | else | |
3251 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | |
9744e218 AA |
3252 | } |
3253 | writel(txreg, base + NvRegTxDeferral); | |
3254 | ||
95d161cb AA |
3255 | if (np->desc_ver == DESC_VER_1) { |
3256 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | |
3257 | } else { | |
3258 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3259 | txreg = NVREG_TX_WM_DESC2_3_1000; | |
3260 | else | |
3261 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | |
3262 | } | |
3263 | writel(txreg, base + NvRegTxWatermark); | |
3264 | ||
78aea4fc | 3265 | writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), |
1da177e4 LT |
3266 | base + NvRegMisc1); |
3267 | pci_push(base); | |
3268 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
3269 | pci_push(base); | |
3270 | ||
b6d0773f AA |
3271 | pause_flags = 0; |
3272 | /* setup pause frame */ | |
eb91f61b | 3273 | if (np->duplex != 0) { |
b6d0773f | 3274 | if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { |
78aea4fc SJ |
3275 | adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
3276 | lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM); | |
b6d0773f AA |
3277 | |
3278 | switch (adv_pause) { | |
f82a9352 | 3279 | case ADVERTISE_PAUSE_CAP: |
b6d0773f AA |
3280 | if (lpa_pause & LPA_PAUSE_CAP) { |
3281 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3282 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3283 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3284 | } | |
3285 | break; | |
f82a9352 | 3286 | case ADVERTISE_PAUSE_ASYM: |
78aea4fc | 3287 | if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM)) |
b6d0773f | 3288 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
b6d0773f | 3289 | break; |
78aea4fc SJ |
3290 | case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM: |
3291 | if (lpa_pause & LPA_PAUSE_CAP) { | |
b6d0773f AA |
3292 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
3293 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3294 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3295 | } | |
3296 | if (lpa_pause == LPA_PAUSE_ASYM) | |
b6d0773f | 3297 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
b6d0773f | 3298 | break; |
f3b197ac | 3299 | } |
eb91f61b | 3300 | } else { |
b6d0773f | 3301 | pause_flags = np->pause_flags; |
eb91f61b AA |
3302 | } |
3303 | } | |
b6d0773f | 3304 | nv_update_pause(dev, pause_flags); |
eb91f61b | 3305 | |
b2976d23 AA |
3306 | if (txrxFlags & NV_RESTART_TX) |
3307 | nv_start_tx(dev); | |
3308 | if (txrxFlags & NV_RESTART_RX) | |
3309 | nv_start_rx(dev); | |
3310 | ||
1da177e4 LT |
3311 | return retval; |
3312 | } | |
3313 | ||
3314 | static void nv_linkchange(struct net_device *dev) | |
3315 | { | |
3316 | if (nv_update_linkspeed(dev)) { | |
4ea7f299 | 3317 | if (!netif_carrier_ok(dev)) { |
1da177e4 | 3318 | netif_carrier_on(dev); |
1d397f36 | 3319 | netdev_info(dev, "link up\n"); |
88d7d8b0 | 3320 | nv_txrx_gate(dev, false); |
4ea7f299 | 3321 | nv_start_rx(dev); |
1da177e4 | 3322 | } |
1da177e4 LT |
3323 | } else { |
3324 | if (netif_carrier_ok(dev)) { | |
3325 | netif_carrier_off(dev); | |
1d397f36 | 3326 | netdev_info(dev, "link down\n"); |
88d7d8b0 | 3327 | nv_txrx_gate(dev, true); |
1da177e4 LT |
3328 | nv_stop_rx(dev); |
3329 | } | |
3330 | } | |
3331 | } | |
3332 | ||
3333 | static void nv_link_irq(struct net_device *dev) | |
3334 | { | |
3335 | u8 __iomem *base = get_hwbase(dev); | |
3336 | u32 miistat; | |
3337 | ||
3338 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 3339 | writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); |
f52dafc1 | 3340 | netdev_dbg(dev, "link change irq, status 0x%x\n", miistat); |
1da177e4 LT |
3341 | |
3342 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) | |
3343 | nv_linkchange(dev); | |
6b80858d | 3344 | netdev_dbg(dev, "link change notification done\n"); |
1da177e4 LT |
3345 | } |
3346 | ||
4db0ee17 AA |
3347 | static void nv_msi_workaround(struct fe_priv *np) |
3348 | { | |
3349 | ||
3350 | /* Need to toggle the msi irq mask within the ethernet device, | |
3351 | * otherwise, future interrupts will not be detected. | |
3352 | */ | |
3353 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3354 | u8 __iomem *base = np->base; | |
3355 | ||
3356 | writel(0, base + NvRegMSIIrqMask); | |
3357 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3358 | } | |
3359 | } | |
3360 | ||
4145ade2 AA |
3361 | static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work) |
3362 | { | |
3363 | struct fe_priv *np = netdev_priv(dev); | |
3364 | ||
3365 | if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) { | |
3366 | if (total_work > NV_DYNAMIC_THRESHOLD) { | |
3367 | /* transition to poll based interrupts */ | |
3368 | np->quiet_count = 0; | |
3369 | if (np->irqmask != NVREG_IRQMASK_CPU) { | |
3370 | np->irqmask = NVREG_IRQMASK_CPU; | |
3371 | return 1; | |
3372 | } | |
3373 | } else { | |
3374 | if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) { | |
3375 | np->quiet_count++; | |
3376 | } else { | |
3377 | /* reached a period of low activity, switch | |
3378 | to per tx/rx packet interrupts */ | |
3379 | if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { | |
3380 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
3381 | return 1; | |
3382 | } | |
3383 | } | |
3384 | } | |
3385 | } | |
3386 | return 0; | |
3387 | } | |
3388 | ||
7d12e780 | 3389 | static irqreturn_t nv_nic_irq(int foo, void *data) |
1da177e4 LT |
3390 | { |
3391 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3392 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3393 | u8 __iomem *base = get_hwbase(dev); |
1da177e4 | 3394 | |
6b80858d | 3395 | netdev_dbg(dev, "%s\n", __func__); |
1da177e4 | 3396 | |
b67874ac AA |
3397 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3398 | np->events = readl(base + NvRegIrqStatus); | |
1b2bb76f | 3399 | writel(np->events, base + NvRegIrqStatus); |
b67874ac AA |
3400 | } else { |
3401 | np->events = readl(base + NvRegMSIXIrqStatus); | |
1b2bb76f | 3402 | writel(np->events, base + NvRegMSIXIrqStatus); |
b67874ac | 3403 | } |
6b80858d | 3404 | netdev_dbg(dev, "irq: %08x\n", np->events); |
b67874ac AA |
3405 | if (!(np->events & np->irqmask)) |
3406 | return IRQ_NONE; | |
1da177e4 | 3407 | |
b67874ac | 3408 | nv_msi_workaround(np); |
4db0ee17 | 3409 | |
78c29bd9 ED |
3410 | if (napi_schedule_prep(&np->napi)) { |
3411 | /* | |
3412 | * Disable further irq's (msix not enabled with napi) | |
3413 | */ | |
3414 | writel(0, base + NvRegIrqMask); | |
3415 | __napi_schedule(&np->napi); | |
3416 | } | |
f0734ab6 | 3417 | |
6b80858d | 3418 | netdev_dbg(dev, "%s: completed\n", __func__); |
1da177e4 | 3419 | |
b67874ac | 3420 | return IRQ_HANDLED; |
1da177e4 LT |
3421 | } |
3422 | ||
f0734ab6 AA |
3423 | /** |
3424 | * All _optimized functions are used to help increase performance | |
3425 | * (reduce CPU and increase throughput). They use descripter version 3, | |
3426 | * compiler directives, and reduce memory accesses. | |
3427 | */ | |
86b22b0d AA |
3428 | static irqreturn_t nv_nic_irq_optimized(int foo, void *data) |
3429 | { | |
3430 | struct net_device *dev = (struct net_device *) data; | |
3431 | struct fe_priv *np = netdev_priv(dev); | |
3432 | u8 __iomem *base = get_hwbase(dev); | |
86b22b0d | 3433 | |
6b80858d | 3434 | netdev_dbg(dev, "%s\n", __func__); |
86b22b0d | 3435 | |
b67874ac AA |
3436 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3437 | np->events = readl(base + NvRegIrqStatus); | |
1b2bb76f | 3438 | writel(np->events, base + NvRegIrqStatus); |
b67874ac AA |
3439 | } else { |
3440 | np->events = readl(base + NvRegMSIXIrqStatus); | |
1b2bb76f | 3441 | writel(np->events, base + NvRegMSIXIrqStatus); |
b67874ac | 3442 | } |
6b80858d | 3443 | netdev_dbg(dev, "irq: %08x\n", np->events); |
b67874ac AA |
3444 | if (!(np->events & np->irqmask)) |
3445 | return IRQ_NONE; | |
86b22b0d | 3446 | |
b67874ac | 3447 | nv_msi_workaround(np); |
4db0ee17 | 3448 | |
78c29bd9 ED |
3449 | if (napi_schedule_prep(&np->napi)) { |
3450 | /* | |
3451 | * Disable further irq's (msix not enabled with napi) | |
3452 | */ | |
3453 | writel(0, base + NvRegIrqMask); | |
3454 | __napi_schedule(&np->napi); | |
3455 | } | |
6b80858d | 3456 | netdev_dbg(dev, "%s: completed\n", __func__); |
86b22b0d | 3457 | |
b67874ac | 3458 | return IRQ_HANDLED; |
86b22b0d AA |
3459 | } |
3460 | ||
7d12e780 | 3461 | static irqreturn_t nv_nic_irq_tx(int foo, void *data) |
d33a73c8 AA |
3462 | { |
3463 | struct net_device *dev = (struct net_device *) data; | |
3464 | struct fe_priv *np = netdev_priv(dev); | |
3465 | u8 __iomem *base = get_hwbase(dev); | |
3466 | u32 events; | |
3467 | int i; | |
0a07bc64 | 3468 | unsigned long flags; |
d33a73c8 | 3469 | |
6b80858d | 3470 | netdev_dbg(dev, "%s\n", __func__); |
d33a73c8 | 3471 | |
78aea4fc | 3472 | for (i = 0;; i++) { |
d33a73c8 AA |
3473 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
3474 | writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); | |
6b80858d | 3475 | netdev_dbg(dev, "tx irq: %08x\n", events); |
d33a73c8 AA |
3476 | if (!(events & np->irqmask)) |
3477 | break; | |
3478 | ||
0a07bc64 | 3479 | spin_lock_irqsave(&np->lock, flags); |
4e16ed1b | 3480 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
0a07bc64 | 3481 | spin_unlock_irqrestore(&np->lock, flags); |
f3b197ac | 3482 | |
f0734ab6 | 3483 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3484 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3485 | /* disable interrupts on the nic */ |
3486 | writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); | |
3487 | pci_push(base); | |
3488 | ||
3489 | if (!np->in_shutdown) { | |
3490 | np->nic_poll_irq |= NVREG_IRQ_TX_ALL; | |
3491 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3492 | } | |
0a07bc64 | 3493 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3494 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); |
d33a73c8 AA |
3495 | break; |
3496 | } | |
3497 | ||
3498 | } | |
6b80858d | 3499 | netdev_dbg(dev, "%s: completed\n", __func__); |
d33a73c8 AA |
3500 | |
3501 | return IRQ_RETVAL(i); | |
3502 | } | |
3503 | ||
bea3348e | 3504 | static int nv_napi_poll(struct napi_struct *napi, int budget) |
e27cdba5 | 3505 | { |
bea3348e SH |
3506 | struct fe_priv *np = container_of(napi, struct fe_priv, napi); |
3507 | struct net_device *dev = np->dev; | |
e27cdba5 | 3508 | u8 __iomem *base = get_hwbase(dev); |
d15e9c4d | 3509 | unsigned long flags; |
4145ade2 | 3510 | int retcode; |
78aea4fc | 3511 | int rx_count, tx_work = 0, rx_work = 0; |
e27cdba5 | 3512 | |
81a2e36d | 3513 | do { |
3514 | if (!nv_optimized(np)) { | |
3515 | spin_lock_irqsave(&np->lock, flags); | |
3516 | tx_work += nv_tx_done(dev, np->tx_ring_size); | |
3517 | spin_unlock_irqrestore(&np->lock, flags); | |
f27e6f39 | 3518 | |
d951f725 | 3519 | rx_count = nv_rx_process(dev, budget - rx_work); |
81a2e36d | 3520 | retcode = nv_alloc_rx(dev); |
3521 | } else { | |
3522 | spin_lock_irqsave(&np->lock, flags); | |
3523 | tx_work += nv_tx_done_optimized(dev, np->tx_ring_size); | |
3524 | spin_unlock_irqrestore(&np->lock, flags); | |
f27e6f39 | 3525 | |
d951f725 TH |
3526 | rx_count = nv_rx_process_optimized(dev, |
3527 | budget - rx_work); | |
81a2e36d | 3528 | retcode = nv_alloc_rx_optimized(dev); |
3529 | } | |
3530 | } while (retcode == 0 && | |
3531 | rx_count > 0 && (rx_work += rx_count) < budget); | |
e27cdba5 | 3532 | |
e0379a14 | 3533 | if (retcode) { |
d15e9c4d | 3534 | spin_lock_irqsave(&np->lock, flags); |
e27cdba5 SH |
3535 | if (!np->in_shutdown) |
3536 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
d15e9c4d | 3537 | spin_unlock_irqrestore(&np->lock, flags); |
e27cdba5 SH |
3538 | } |
3539 | ||
4145ade2 AA |
3540 | nv_change_interrupt_mode(dev, tx_work + rx_work); |
3541 | ||
f27e6f39 AA |
3542 | if (unlikely(np->events & NVREG_IRQ_LINK)) { |
3543 | spin_lock_irqsave(&np->lock, flags); | |
3544 | nv_link_irq(dev); | |
3545 | spin_unlock_irqrestore(&np->lock, flags); | |
3546 | } | |
3547 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { | |
3548 | spin_lock_irqsave(&np->lock, flags); | |
3549 | nv_linkchange(dev); | |
3550 | spin_unlock_irqrestore(&np->lock, flags); | |
3551 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
3552 | } | |
3553 | if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) { | |
3554 | spin_lock_irqsave(&np->lock, flags); | |
3555 | if (!np->in_shutdown) { | |
3556 | np->nic_poll_irq = np->irqmask; | |
3557 | np->recover_error = 1; | |
3558 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3559 | } | |
3560 | spin_unlock_irqrestore(&np->lock, flags); | |
6c2da9c2 | 3561 | napi_complete(napi); |
4145ade2 | 3562 | return rx_work; |
f27e6f39 AA |
3563 | } |
3564 | ||
4145ade2 | 3565 | if (rx_work < budget) { |
f27e6f39 AA |
3566 | /* re-enable interrupts |
3567 | (msix not enabled in napi) */ | |
6c2da9c2 | 3568 | napi_complete(napi); |
bea3348e | 3569 | |
f27e6f39 | 3570 | writel(np->irqmask, base + NvRegIrqMask); |
e27cdba5 | 3571 | } |
4145ade2 | 3572 | return rx_work; |
e27cdba5 | 3573 | } |
e27cdba5 | 3574 | |
7d12e780 | 3575 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
d33a73c8 AA |
3576 | { |
3577 | struct net_device *dev = (struct net_device *) data; | |
3578 | struct fe_priv *np = netdev_priv(dev); | |
3579 | u8 __iomem *base = get_hwbase(dev); | |
3580 | u32 events; | |
3581 | int i; | |
0a07bc64 | 3582 | unsigned long flags; |
d33a73c8 | 3583 | |
6b80858d | 3584 | netdev_dbg(dev, "%s\n", __func__); |
d33a73c8 | 3585 | |
78aea4fc | 3586 | for (i = 0;; i++) { |
d33a73c8 AA |
3587 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
3588 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); | |
6b80858d | 3589 | netdev_dbg(dev, "rx irq: %08x\n", events); |
d33a73c8 AA |
3590 | if (!(events & np->irqmask)) |
3591 | break; | |
f3b197ac | 3592 | |
bea3348e | 3593 | if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3594 | if (unlikely(nv_alloc_rx_optimized(dev))) { |
3595 | spin_lock_irqsave(&np->lock, flags); | |
3596 | if (!np->in_shutdown) | |
3597 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3598 | spin_unlock_irqrestore(&np->lock, flags); | |
3599 | } | |
d33a73c8 | 3600 | } |
f3b197ac | 3601 | |
f0734ab6 | 3602 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3603 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3604 | /* disable interrupts on the nic */ |
3605 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3606 | pci_push(base); | |
3607 | ||
3608 | if (!np->in_shutdown) { | |
3609 | np->nic_poll_irq |= NVREG_IRQ_RX_ALL; | |
3610 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3611 | } | |
0a07bc64 | 3612 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3613 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); |
d33a73c8 AA |
3614 | break; |
3615 | } | |
d33a73c8 | 3616 | } |
6b80858d | 3617 | netdev_dbg(dev, "%s: completed\n", __func__); |
d33a73c8 AA |
3618 | |
3619 | return IRQ_RETVAL(i); | |
3620 | } | |
3621 | ||
7d12e780 | 3622 | static irqreturn_t nv_nic_irq_other(int foo, void *data) |
d33a73c8 AA |
3623 | { |
3624 | struct net_device *dev = (struct net_device *) data; | |
3625 | struct fe_priv *np = netdev_priv(dev); | |
3626 | u8 __iomem *base = get_hwbase(dev); | |
3627 | u32 events; | |
3628 | int i; | |
0a07bc64 | 3629 | unsigned long flags; |
d33a73c8 | 3630 | |
6b80858d | 3631 | netdev_dbg(dev, "%s\n", __func__); |
d33a73c8 | 3632 | |
78aea4fc | 3633 | for (i = 0;; i++) { |
d33a73c8 AA |
3634 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
3635 | writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); | |
6b80858d | 3636 | netdev_dbg(dev, "irq: %08x\n", events); |
d33a73c8 AA |
3637 | if (!(events & np->irqmask)) |
3638 | break; | |
f3b197ac | 3639 | |
4e16ed1b AA |
3640 | /* check tx in case we reached max loop limit in tx isr */ |
3641 | spin_lock_irqsave(&np->lock, flags); | |
3642 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); | |
3643 | spin_unlock_irqrestore(&np->lock, flags); | |
3644 | ||
d33a73c8 | 3645 | if (events & NVREG_IRQ_LINK) { |
0a07bc64 | 3646 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3647 | nv_link_irq(dev); |
0a07bc64 | 3648 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3649 | } |
3650 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { | |
0a07bc64 | 3651 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3652 | nv_linkchange(dev); |
0a07bc64 | 3653 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3654 | np->link_timeout = jiffies + LINK_TIMEOUT; |
3655 | } | |
c5cf9101 AA |
3656 | if (events & NVREG_IRQ_RECOVER_ERROR) { |
3657 | spin_lock_irq(&np->lock); | |
3658 | /* disable interrupts on the nic */ | |
3659 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3660 | pci_push(base); | |
3661 | ||
3662 | if (!np->in_shutdown) { | |
3663 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3664 | np->recover_error = 1; | |
3665 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3666 | } | |
3667 | spin_unlock_irq(&np->lock); | |
3668 | break; | |
3669 | } | |
f0734ab6 | 3670 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3671 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3672 | /* disable interrupts on the nic */ |
3673 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3674 | pci_push(base); | |
3675 | ||
3676 | if (!np->in_shutdown) { | |
3677 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3678 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3679 | } | |
0a07bc64 | 3680 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3681 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); |
d33a73c8 AA |
3682 | break; |
3683 | } | |
3684 | ||
3685 | } | |
6b80858d | 3686 | netdev_dbg(dev, "%s: completed\n", __func__); |
d33a73c8 AA |
3687 | |
3688 | return IRQ_RETVAL(i); | |
3689 | } | |
3690 | ||
7d12e780 | 3691 | static irqreturn_t nv_nic_irq_test(int foo, void *data) |
9589c77a AA |
3692 | { |
3693 | struct net_device *dev = (struct net_device *) data; | |
3694 | struct fe_priv *np = netdev_priv(dev); | |
3695 | u8 __iomem *base = get_hwbase(dev); | |
3696 | u32 events; | |
3697 | ||
6b80858d | 3698 | netdev_dbg(dev, "%s\n", __func__); |
9589c77a AA |
3699 | |
3700 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
3701 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
3702 | writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); | |
3703 | } else { | |
3704 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
3705 | writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); | |
3706 | } | |
3707 | pci_push(base); | |
6b80858d | 3708 | netdev_dbg(dev, "irq: %08x\n", events); |
9589c77a AA |
3709 | if (!(events & NVREG_IRQ_TIMER)) |
3710 | return IRQ_RETVAL(0); | |
3711 | ||
4db0ee17 AA |
3712 | nv_msi_workaround(np); |
3713 | ||
9589c77a AA |
3714 | spin_lock(&np->lock); |
3715 | np->intr_test = 1; | |
3716 | spin_unlock(&np->lock); | |
3717 | ||
6b80858d | 3718 | netdev_dbg(dev, "%s: completed\n", __func__); |
9589c77a AA |
3719 | |
3720 | return IRQ_RETVAL(1); | |
3721 | } | |
3722 | ||
7a1854b7 AA |
3723 | static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
3724 | { | |
3725 | u8 __iomem *base = get_hwbase(dev); | |
3726 | int i; | |
3727 | u32 msixmap = 0; | |
3728 | ||
3729 | /* Each interrupt bit can be mapped to a MSIX vector (4 bits). | |
3730 | * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents | |
3731 | * the remaining 8 interrupts. | |
3732 | */ | |
3733 | for (i = 0; i < 8; i++) { | |
78aea4fc | 3734 | if ((irqmask >> i) & 0x1) |
7a1854b7 | 3735 | msixmap |= vector << (i << 2); |
7a1854b7 AA |
3736 | } |
3737 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); | |
3738 | ||
3739 | msixmap = 0; | |
3740 | for (i = 0; i < 8; i++) { | |
78aea4fc | 3741 | if ((irqmask >> (i + 8)) & 0x1) |
7a1854b7 | 3742 | msixmap |= vector << (i << 2); |
7a1854b7 AA |
3743 | } |
3744 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); | |
3745 | } | |
3746 | ||
9589c77a | 3747 | static int nv_request_irq(struct net_device *dev, int intr_test) |
7a1854b7 AA |
3748 | { |
3749 | struct fe_priv *np = get_nvpriv(dev); | |
3750 | u8 __iomem *base = get_hwbase(dev); | |
3751 | int ret = 1; | |
3752 | int i; | |
86b22b0d AA |
3753 | irqreturn_t (*handler)(int foo, void *data); |
3754 | ||
3755 | if (intr_test) { | |
3756 | handler = nv_nic_irq_test; | |
3757 | } else { | |
36b30ea9 | 3758 | if (nv_optimized(np)) |
86b22b0d AA |
3759 | handler = nv_nic_irq_optimized; |
3760 | else | |
3761 | handler = nv_nic_irq; | |
3762 | } | |
7a1854b7 AA |
3763 | |
3764 | if (np->msi_flags & NV_MSI_X_CAPABLE) { | |
78aea4fc | 3765 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
7a1854b7 | 3766 | np->msi_x_entry[i].entry = i; |
34cf97eb SJ |
3767 | ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK)); |
3768 | if (ret == 0) { | |
7a1854b7 | 3769 | np->msi_flags |= NV_MSI_X_ENABLED; |
9589c77a | 3770 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
7a1854b7 | 3771 | /* Request irq for rx handling */ |
ddb213f0 YL |
3772 | sprintf(np->name_rx, "%s-rx", dev->name); |
3773 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, | |
a0607fd3 | 3774 | nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) { |
1d397f36 JP |
3775 | netdev_info(dev, |
3776 | "request_irq failed for rx %d\n", | |
3777 | ret); | |
7a1854b7 AA |
3778 | pci_disable_msix(np->pci_dev); |
3779 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3780 | goto out_err; | |
3781 | } | |
3782 | /* Request irq for tx handling */ | |
ddb213f0 YL |
3783 | sprintf(np->name_tx, "%s-tx", dev->name); |
3784 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, | |
a0607fd3 | 3785 | nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) { |
1d397f36 JP |
3786 | netdev_info(dev, |
3787 | "request_irq failed for tx %d\n", | |
3788 | ret); | |
7a1854b7 AA |
3789 | pci_disable_msix(np->pci_dev); |
3790 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3791 | goto out_free_rx; | |
3792 | } | |
3793 | /* Request irq for link and timer handling */ | |
ddb213f0 YL |
3794 | sprintf(np->name_other, "%s-other", dev->name); |
3795 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, | |
a0607fd3 | 3796 | nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) { |
1d397f36 JP |
3797 | netdev_info(dev, |
3798 | "request_irq failed for link %d\n", | |
3799 | ret); | |
7a1854b7 AA |
3800 | pci_disable_msix(np->pci_dev); |
3801 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3802 | goto out_free_tx; | |
3803 | } | |
3804 | /* map interrupts to their respective vector */ | |
3805 | writel(0, base + NvRegMSIXMap0); | |
3806 | writel(0, base + NvRegMSIXMap1); | |
3807 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); | |
3808 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); | |
3809 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); | |
3810 | } else { | |
3811 | /* Request irq for all interrupts */ | |
86b22b0d | 3812 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { |
1d397f36 JP |
3813 | netdev_info(dev, |
3814 | "request_irq failed %d\n", | |
3815 | ret); | |
7a1854b7 AA |
3816 | pci_disable_msix(np->pci_dev); |
3817 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3818 | goto out_err; | |
3819 | } | |
3820 | ||
3821 | /* map interrupts to vector 0 */ | |
3822 | writel(0, base + NvRegMSIXMap0); | |
3823 | writel(0, base + NvRegMSIXMap1); | |
3824 | } | |
3825 | } | |
3826 | } | |
3827 | if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { | |
34cf97eb SJ |
3828 | ret = pci_enable_msi(np->pci_dev); |
3829 | if (ret == 0) { | |
7a1854b7 | 3830 | np->msi_flags |= NV_MSI_ENABLED; |
a7475906 | 3831 | dev->irq = np->pci_dev->irq; |
86b22b0d | 3832 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { |
1d397f36 JP |
3833 | netdev_info(dev, "request_irq failed %d\n", |
3834 | ret); | |
7a1854b7 AA |
3835 | pci_disable_msi(np->pci_dev); |
3836 | np->msi_flags &= ~NV_MSI_ENABLED; | |
a7475906 | 3837 | dev->irq = np->pci_dev->irq; |
7a1854b7 AA |
3838 | goto out_err; |
3839 | } | |
3840 | ||
3841 | /* map interrupts to vector 0 */ | |
3842 | writel(0, base + NvRegMSIMap0); | |
3843 | writel(0, base + NvRegMSIMap1); | |
3844 | /* enable msi vector 0 */ | |
3845 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3846 | } | |
3847 | } | |
3848 | if (ret != 0) { | |
86b22b0d | 3849 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) |
7a1854b7 | 3850 | goto out_err; |
9589c77a | 3851 | |
7a1854b7 AA |
3852 | } |
3853 | ||
3854 | return 0; | |
3855 | out_free_tx: | |
3856 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); | |
3857 | out_free_rx: | |
3858 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); | |
3859 | out_err: | |
3860 | return 1; | |
3861 | } | |
3862 | ||
3863 | static void nv_free_irq(struct net_device *dev) | |
3864 | { | |
3865 | struct fe_priv *np = get_nvpriv(dev); | |
3866 | int i; | |
3867 | ||
3868 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
78aea4fc | 3869 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
7a1854b7 | 3870 | free_irq(np->msi_x_entry[i].vector, dev); |
7a1854b7 AA |
3871 | pci_disable_msix(np->pci_dev); |
3872 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3873 | } else { | |
3874 | free_irq(np->pci_dev->irq, dev); | |
3875 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3876 | pci_disable_msi(np->pci_dev); | |
3877 | np->msi_flags &= ~NV_MSI_ENABLED; | |
3878 | } | |
3879 | } | |
3880 | } | |
3881 | ||
1da177e4 LT |
3882 | static void nv_do_nic_poll(unsigned long data) |
3883 | { | |
3884 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3885 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3886 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 3887 | u32 mask = 0; |
1da177e4 | 3888 | |
1da177e4 | 3889 | /* |
d33a73c8 | 3890 | * First disable irq(s) and then |
1da177e4 LT |
3891 | * reenable interrupts on the nic, we have to do this before calling |
3892 | * nv_nic_irq because that may decide to do otherwise | |
3893 | */ | |
d33a73c8 | 3894 | |
84b3932b AA |
3895 | if (!using_multi_irqs(dev)) { |
3896 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
8688cfce | 3897 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 3898 | else |
a7475906 | 3899 | disable_irq_lockdep(np->pci_dev->irq); |
d33a73c8 AA |
3900 | mask = np->irqmask; |
3901 | } else { | |
3902 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
8688cfce | 3903 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
3904 | mask |= NVREG_IRQ_RX_ALL; |
3905 | } | |
3906 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
8688cfce | 3907 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
3908 | mask |= NVREG_IRQ_TX_ALL; |
3909 | } | |
3910 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
8688cfce | 3911 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
3912 | mask |= NVREG_IRQ_OTHER; |
3913 | } | |
3914 | } | |
a7475906 MS |
3915 | /* disable_irq() contains synchronize_irq, thus no irq handler can run now */ |
3916 | ||
c5cf9101 AA |
3917 | if (np->recover_error) { |
3918 | np->recover_error = 0; | |
1d397f36 | 3919 | netdev_info(dev, "MAC in recoverable error state\n"); |
c5cf9101 AA |
3920 | if (netif_running(dev)) { |
3921 | netif_tx_lock_bh(dev); | |
e308a5d8 | 3922 | netif_addr_lock(dev); |
c5cf9101 AA |
3923 | spin_lock(&np->lock); |
3924 | /* stop engines */ | |
36b30ea9 | 3925 | nv_stop_rxtx(dev); |
daa91a9d AA |
3926 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
3927 | nv_mac_reset(dev); | |
c5cf9101 AA |
3928 | nv_txrx_reset(dev); |
3929 | /* drain rx queue */ | |
36b30ea9 | 3930 | nv_drain_rxtx(dev); |
c5cf9101 AA |
3931 | /* reinit driver view of the rx queue */ |
3932 | set_bufsize(dev); | |
3933 | if (nv_init_ring(dev)) { | |
3934 | if (!np->in_shutdown) | |
3935 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3936 | } | |
3937 | /* reinit nic view of the rx queue */ | |
3938 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
3939 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 3940 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
c5cf9101 AA |
3941 | base + NvRegRingSizes); |
3942 | pci_push(base); | |
3943 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
3944 | pci_push(base); | |
daa91a9d AA |
3945 | /* clear interrupts */ |
3946 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
3947 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
3948 | else | |
3949 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
c5cf9101 AA |
3950 | |
3951 | /* restart rx engine */ | |
36b30ea9 | 3952 | nv_start_rxtx(dev); |
c5cf9101 | 3953 | spin_unlock(&np->lock); |
e308a5d8 | 3954 | netif_addr_unlock(dev); |
c5cf9101 AA |
3955 | netif_tx_unlock_bh(dev); |
3956 | } | |
3957 | } | |
3958 | ||
d33a73c8 | 3959 | writel(mask, base + NvRegIrqMask); |
1da177e4 | 3960 | pci_push(base); |
d33a73c8 | 3961 | |
84b3932b | 3962 | if (!using_multi_irqs(dev)) { |
79d30a58 | 3963 | np->nic_poll_irq = 0; |
36b30ea9 | 3964 | if (nv_optimized(np)) |
fcc5f266 AA |
3965 | nv_nic_irq_optimized(0, dev); |
3966 | else | |
3967 | nv_nic_irq(0, dev); | |
84b3932b | 3968 | if (np->msi_flags & NV_MSI_X_ENABLED) |
8688cfce | 3969 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 3970 | else |
a7475906 | 3971 | enable_irq_lockdep(np->pci_dev->irq); |
d33a73c8 AA |
3972 | } else { |
3973 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
79d30a58 | 3974 | np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL; |
7d12e780 | 3975 | nv_nic_irq_rx(0, dev); |
8688cfce | 3976 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
3977 | } |
3978 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
79d30a58 | 3979 | np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL; |
7d12e780 | 3980 | nv_nic_irq_tx(0, dev); |
8688cfce | 3981 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
3982 | } |
3983 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
79d30a58 | 3984 | np->nic_poll_irq &= ~NVREG_IRQ_OTHER; |
7d12e780 | 3985 | nv_nic_irq_other(0, dev); |
8688cfce | 3986 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
3987 | } |
3988 | } | |
79d30a58 | 3989 | |
1da177e4 LT |
3990 | } |
3991 | ||
2918c35d MS |
3992 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3993 | static void nv_poll_controller(struct net_device *dev) | |
3994 | { | |
3995 | nv_do_nic_poll((unsigned long) dev); | |
3996 | } | |
3997 | #endif | |
3998 | ||
52da3578 AA |
3999 | static void nv_do_stats_poll(unsigned long data) |
4000 | { | |
4001 | struct net_device *dev = (struct net_device *) data; | |
4002 | struct fe_priv *np = netdev_priv(dev); | |
52da3578 | 4003 | |
57fff698 | 4004 | nv_get_hw_stats(dev); |
52da3578 AA |
4005 | |
4006 | if (!np->in_shutdown) | |
bfebbb88 DD |
4007 | mod_timer(&np->stats_poll, |
4008 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 AA |
4009 | } |
4010 | ||
1da177e4 LT |
4011 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
4012 | { | |
ac9c1897 | 4013 | struct fe_priv *np = netdev_priv(dev); |
3f88ce49 | 4014 | strcpy(info->driver, DRV_NAME); |
1da177e4 LT |
4015 | strcpy(info->version, FORCEDETH_VERSION); |
4016 | strcpy(info->bus_info, pci_name(np->pci_dev)); | |
4017 | } | |
4018 | ||
4019 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
4020 | { | |
ac9c1897 | 4021 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
4022 | wolinfo->supported = WAKE_MAGIC; |
4023 | ||
4024 | spin_lock_irq(&np->lock); | |
4025 | if (np->wolenabled) | |
4026 | wolinfo->wolopts = WAKE_MAGIC; | |
4027 | spin_unlock_irq(&np->lock); | |
4028 | } | |
4029 | ||
4030 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
4031 | { | |
ac9c1897 | 4032 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 4033 | u8 __iomem *base = get_hwbase(dev); |
c42d9df9 | 4034 | u32 flags = 0; |
1da177e4 | 4035 | |
1da177e4 | 4036 | if (wolinfo->wolopts == 0) { |
1da177e4 | 4037 | np->wolenabled = 0; |
c42d9df9 | 4038 | } else if (wolinfo->wolopts & WAKE_MAGIC) { |
1da177e4 | 4039 | np->wolenabled = 1; |
c42d9df9 AA |
4040 | flags = NVREG_WAKEUPFLAGS_ENABLE; |
4041 | } | |
4042 | if (netif_running(dev)) { | |
4043 | spin_lock_irq(&np->lock); | |
4044 | writel(flags, base + NvRegWakeUpFlags); | |
4045 | spin_unlock_irq(&np->lock); | |
1da177e4 | 4046 | } |
1da177e4 LT |
4047 | return 0; |
4048 | } | |
4049 | ||
4050 | static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
4051 | { | |
4052 | struct fe_priv *np = netdev_priv(dev); | |
4053 | int adv; | |
4054 | ||
4055 | spin_lock_irq(&np->lock); | |
4056 | ecmd->port = PORT_MII; | |
4057 | if (!netif_running(dev)) { | |
4058 | /* We do not track link speed / duplex setting if the | |
4059 | * interface is disabled. Force a link check */ | |
f9430a01 AA |
4060 | if (nv_update_linkspeed(dev)) { |
4061 | if (!netif_carrier_ok(dev)) | |
4062 | netif_carrier_on(dev); | |
4063 | } else { | |
4064 | if (netif_carrier_ok(dev)) | |
4065 | netif_carrier_off(dev); | |
4066 | } | |
1da177e4 | 4067 | } |
f9430a01 AA |
4068 | |
4069 | if (netif_carrier_ok(dev)) { | |
78aea4fc | 4070 | switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) { |
1da177e4 LT |
4071 | case NVREG_LINKSPEED_10: |
4072 | ecmd->speed = SPEED_10; | |
4073 | break; | |
4074 | case NVREG_LINKSPEED_100: | |
4075 | ecmd->speed = SPEED_100; | |
4076 | break; | |
4077 | case NVREG_LINKSPEED_1000: | |
4078 | ecmd->speed = SPEED_1000; | |
4079 | break; | |
f9430a01 AA |
4080 | } |
4081 | ecmd->duplex = DUPLEX_HALF; | |
4082 | if (np->duplex) | |
4083 | ecmd->duplex = DUPLEX_FULL; | |
4084 | } else { | |
4085 | ecmd->speed = -1; | |
4086 | ecmd->duplex = -1; | |
1da177e4 | 4087 | } |
1da177e4 LT |
4088 | |
4089 | ecmd->autoneg = np->autoneg; | |
4090 | ||
4091 | ecmd->advertising = ADVERTISED_MII; | |
4092 | if (np->autoneg) { | |
4093 | ecmd->advertising |= ADVERTISED_Autoneg; | |
4094 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
f9430a01 AA |
4095 | if (adv & ADVERTISE_10HALF) |
4096 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
4097 | if (adv & ADVERTISE_10FULL) | |
4098 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
4099 | if (adv & ADVERTISE_100HALF) | |
4100 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
4101 | if (adv & ADVERTISE_100FULL) | |
4102 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
4103 | if (np->gigabit == PHY_GIGABIT) { | |
4104 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); | |
4105 | if (adv & ADVERTISE_1000FULL) | |
4106 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
4107 | } | |
1da177e4 | 4108 | } |
1da177e4 LT |
4109 | ecmd->supported = (SUPPORTED_Autoneg | |
4110 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | | |
4111 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
4112 | SUPPORTED_MII); | |
4113 | if (np->gigabit == PHY_GIGABIT) | |
4114 | ecmd->supported |= SUPPORTED_1000baseT_Full; | |
4115 | ||
4116 | ecmd->phy_address = np->phyaddr; | |
4117 | ecmd->transceiver = XCVR_EXTERNAL; | |
4118 | ||
4119 | /* ignore maxtxpkt, maxrxpkt for now */ | |
4120 | spin_unlock_irq(&np->lock); | |
4121 | return 0; | |
4122 | } | |
4123 | ||
4124 | static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
4125 | { | |
4126 | struct fe_priv *np = netdev_priv(dev); | |
4127 | ||
4128 | if (ecmd->port != PORT_MII) | |
4129 | return -EINVAL; | |
4130 | if (ecmd->transceiver != XCVR_EXTERNAL) | |
4131 | return -EINVAL; | |
4132 | if (ecmd->phy_address != np->phyaddr) { | |
4133 | /* TODO: support switching between multiple phys. Should be | |
4134 | * trivial, but not enabled due to lack of test hardware. */ | |
4135 | return -EINVAL; | |
4136 | } | |
4137 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
4138 | u32 mask; | |
4139 | ||
4140 | mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4141 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4142 | if (np->gigabit == PHY_GIGABIT) | |
4143 | mask |= ADVERTISED_1000baseT_Full; | |
4144 | ||
4145 | if ((ecmd->advertising & mask) == 0) | |
4146 | return -EINVAL; | |
4147 | ||
4148 | } else if (ecmd->autoneg == AUTONEG_DISABLE) { | |
4149 | /* Note: autonegotiation disable, speed 1000 intentionally | |
4150 | * forbidden - noone should need that. */ | |
4151 | ||
4152 | if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) | |
4153 | return -EINVAL; | |
4154 | if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) | |
4155 | return -EINVAL; | |
4156 | } else { | |
4157 | return -EINVAL; | |
4158 | } | |
4159 | ||
f9430a01 AA |
4160 | netif_carrier_off(dev); |
4161 | if (netif_running(dev)) { | |
97bff095 TD |
4162 | unsigned long flags; |
4163 | ||
f9430a01 | 4164 | nv_disable_irq(dev); |
58dfd9c1 | 4165 | netif_tx_lock_bh(dev); |
e308a5d8 | 4166 | netif_addr_lock(dev); |
97bff095 TD |
4167 | /* with plain spinlock lockdep complains */ |
4168 | spin_lock_irqsave(&np->lock, flags); | |
f9430a01 | 4169 | /* stop engines */ |
97bff095 TD |
4170 | /* FIXME: |
4171 | * this can take some time, and interrupts are disabled | |
4172 | * due to spin_lock_irqsave, but let's hope no daemon | |
4173 | * is going to change the settings very often... | |
4174 | * Worst case: | |
4175 | * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX | |
4176 | * + some minor delays, which is up to a second approximately | |
4177 | */ | |
36b30ea9 | 4178 | nv_stop_rxtx(dev); |
97bff095 | 4179 | spin_unlock_irqrestore(&np->lock, flags); |
e308a5d8 | 4180 | netif_addr_unlock(dev); |
58dfd9c1 | 4181 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
4182 | } |
4183 | ||
1da177e4 LT |
4184 | if (ecmd->autoneg == AUTONEG_ENABLE) { |
4185 | int adv, bmcr; | |
4186 | ||
4187 | np->autoneg = 1; | |
4188 | ||
4189 | /* advertise only what has been requested */ | |
4190 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4191 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
4192 | if (ecmd->advertising & ADVERTISED_10baseT_Half) |
4193 | adv |= ADVERTISE_10HALF; | |
4194 | if (ecmd->advertising & ADVERTISED_10baseT_Full) | |
b6d0773f | 4195 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
4196 | if (ecmd->advertising & ADVERTISED_100baseT_Half) |
4197 | adv |= ADVERTISE_100HALF; | |
4198 | if (ecmd->advertising & ADVERTISED_100baseT_Full) | |
b6d0773f AA |
4199 | adv |= ADVERTISE_100FULL; |
4200 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ | |
4201 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4202 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4203 | adv |= ADVERTISE_PAUSE_ASYM; | |
1da177e4 LT |
4204 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4205 | ||
4206 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4207 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
4208 | adv &= ~ADVERTISE_1000FULL; |
4209 | if (ecmd->advertising & ADVERTISED_1000baseT_Full) | |
4210 | adv |= ADVERTISE_1000FULL; | |
eb91f61b | 4211 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4212 | } |
4213 | ||
f9430a01 | 4214 | if (netif_running(dev)) |
1d397f36 | 4215 | netdev_info(dev, "link down\n"); |
1da177e4 | 4216 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4217 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4218 | bmcr |= BMCR_ANENABLE; | |
4219 | /* reset the phy in order for settings to stick, | |
4220 | * and cause autoneg to start */ | |
4221 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4222 | netdev_info(dev, "phy reset failed\n"); |
edf7e5ec AA |
4223 | return -EINVAL; |
4224 | } | |
4225 | } else { | |
4226 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4227 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4228 | } | |
1da177e4 LT |
4229 | } else { |
4230 | int adv, bmcr; | |
4231 | ||
4232 | np->autoneg = 0; | |
4233 | ||
4234 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4235 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
4236 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) |
4237 | adv |= ADVERTISE_10HALF; | |
4238 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) | |
b6d0773f | 4239 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
4240 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) |
4241 | adv |= ADVERTISE_100HALF; | |
4242 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) | |
b6d0773f AA |
4243 | adv |= ADVERTISE_100FULL; |
4244 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4245 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */ | |
4246 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4247 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4248 | } | |
4249 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { | |
4250 | adv |= ADVERTISE_PAUSE_ASYM; | |
4251 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4252 | } | |
1da177e4 LT |
4253 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4254 | np->fixed_mode = adv; | |
4255 | ||
4256 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4257 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 | 4258 | adv &= ~ADVERTISE_1000FULL; |
eb91f61b | 4259 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4260 | } |
4261 | ||
4262 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
f9430a01 AA |
4263 | bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX); |
4264 | if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) | |
1da177e4 | 4265 | bmcr |= BMCR_FULLDPLX; |
f9430a01 | 4266 | if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
1da177e4 | 4267 | bmcr |= BMCR_SPEED100; |
f9430a01 | 4268 | if (np->phy_oui == PHY_OUI_MARVELL) { |
edf7e5ec AA |
4269 | /* reset the phy in order for forced mode settings to stick */ |
4270 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4271 | netdev_info(dev, "phy reset failed\n"); |
f9430a01 AA |
4272 | return -EINVAL; |
4273 | } | |
edf7e5ec AA |
4274 | } else { |
4275 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4276 | if (netif_running(dev)) { | |
4277 | /* Wait a bit and then reconfigure the nic. */ | |
4278 | udelay(10); | |
4279 | nv_linkchange(dev); | |
4280 | } | |
1da177e4 LT |
4281 | } |
4282 | } | |
f9430a01 AA |
4283 | |
4284 | if (netif_running(dev)) { | |
36b30ea9 | 4285 | nv_start_rxtx(dev); |
f9430a01 AA |
4286 | nv_enable_irq(dev); |
4287 | } | |
1da177e4 LT |
4288 | |
4289 | return 0; | |
4290 | } | |
4291 | ||
dc8216c1 | 4292 | #define FORCEDETH_REGS_VER 1 |
dc8216c1 MS |
4293 | |
4294 | static int nv_get_regs_len(struct net_device *dev) | |
4295 | { | |
86a0f043 AA |
4296 | struct fe_priv *np = netdev_priv(dev); |
4297 | return np->register_size; | |
dc8216c1 MS |
4298 | } |
4299 | ||
4300 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
4301 | { | |
ac9c1897 | 4302 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4303 | u8 __iomem *base = get_hwbase(dev); |
4304 | u32 *rbuf = buf; | |
4305 | int i; | |
4306 | ||
4307 | regs->version = FORCEDETH_REGS_VER; | |
4308 | spin_lock_irq(&np->lock); | |
78aea4fc | 4309 | for (i = 0; i <= np->register_size/sizeof(u32); i++) |
dc8216c1 MS |
4310 | rbuf[i] = readl(base + i*sizeof(u32)); |
4311 | spin_unlock_irq(&np->lock); | |
4312 | } | |
4313 | ||
4314 | static int nv_nway_reset(struct net_device *dev) | |
4315 | { | |
ac9c1897 | 4316 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4317 | int ret; |
4318 | ||
dc8216c1 MS |
4319 | if (np->autoneg) { |
4320 | int bmcr; | |
4321 | ||
f9430a01 AA |
4322 | netif_carrier_off(dev); |
4323 | if (netif_running(dev)) { | |
4324 | nv_disable_irq(dev); | |
58dfd9c1 | 4325 | netif_tx_lock_bh(dev); |
e308a5d8 | 4326 | netif_addr_lock(dev); |
f9430a01 AA |
4327 | spin_lock(&np->lock); |
4328 | /* stop engines */ | |
36b30ea9 | 4329 | nv_stop_rxtx(dev); |
f9430a01 | 4330 | spin_unlock(&np->lock); |
e308a5d8 | 4331 | netif_addr_unlock(dev); |
58dfd9c1 | 4332 | netif_tx_unlock_bh(dev); |
1d397f36 | 4333 | netdev_info(dev, "link down\n"); |
f9430a01 AA |
4334 | } |
4335 | ||
dc8216c1 | 4336 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4337 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4338 | bmcr |= BMCR_ANENABLE; | |
4339 | /* reset the phy in order for settings to stick*/ | |
4340 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4341 | netdev_info(dev, "phy reset failed\n"); |
edf7e5ec AA |
4342 | return -EINVAL; |
4343 | } | |
4344 | } else { | |
4345 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4346 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4347 | } | |
dc8216c1 | 4348 | |
f9430a01 | 4349 | if (netif_running(dev)) { |
36b30ea9 | 4350 | nv_start_rxtx(dev); |
f9430a01 AA |
4351 | nv_enable_irq(dev); |
4352 | } | |
dc8216c1 MS |
4353 | ret = 0; |
4354 | } else { | |
4355 | ret = -EINVAL; | |
4356 | } | |
dc8216c1 MS |
4357 | |
4358 | return ret; | |
4359 | } | |
4360 | ||
0674d594 ZA |
4361 | static int nv_set_tso(struct net_device *dev, u32 value) |
4362 | { | |
4363 | struct fe_priv *np = netdev_priv(dev); | |
4364 | ||
4365 | if ((np->driver_data & DEV_HAS_CHECKSUM)) | |
4366 | return ethtool_op_set_tso(dev, value); | |
4367 | else | |
6a78814f | 4368 | return -EOPNOTSUPP; |
0674d594 | 4369 | } |
0674d594 | 4370 | |
eafa59f6 AA |
4371 | static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
4372 | { | |
4373 | struct fe_priv *np = netdev_priv(dev); | |
4374 | ||
4375 | ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
4376 | ring->rx_mini_max_pending = 0; | |
4377 | ring->rx_jumbo_max_pending = 0; | |
4378 | ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
4379 | ||
4380 | ring->rx_pending = np->rx_ring_size; | |
4381 | ring->rx_mini_pending = 0; | |
4382 | ring->rx_jumbo_pending = 0; | |
4383 | ring->tx_pending = np->tx_ring_size; | |
4384 | } | |
4385 | ||
4386 | static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) | |
4387 | { | |
4388 | struct fe_priv *np = netdev_priv(dev); | |
4389 | u8 __iomem *base = get_hwbase(dev); | |
761fcd9e | 4390 | u8 *rxtx_ring, *rx_skbuff, *tx_skbuff; |
eafa59f6 AA |
4391 | dma_addr_t ring_addr; |
4392 | ||
4393 | if (ring->rx_pending < RX_RING_MIN || | |
4394 | ring->tx_pending < TX_RING_MIN || | |
4395 | ring->rx_mini_pending != 0 || | |
4396 | ring->rx_jumbo_pending != 0 || | |
4397 | (np->desc_ver == DESC_VER_1 && | |
4398 | (ring->rx_pending > RING_MAX_DESC_VER_1 || | |
4399 | ring->tx_pending > RING_MAX_DESC_VER_1)) || | |
4400 | (np->desc_ver != DESC_VER_1 && | |
4401 | (ring->rx_pending > RING_MAX_DESC_VER_2_3 || | |
4402 | ring->tx_pending > RING_MAX_DESC_VER_2_3))) { | |
4403 | return -EINVAL; | |
4404 | } | |
4405 | ||
4406 | /* allocate new rings */ | |
36b30ea9 | 4407 | if (!nv_optimized(np)) { |
eafa59f6 AA |
4408 | rxtx_ring = pci_alloc_consistent(np->pci_dev, |
4409 | sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), | |
4410 | &ring_addr); | |
4411 | } else { | |
4412 | rxtx_ring = pci_alloc_consistent(np->pci_dev, | |
4413 | sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4414 | &ring_addr); | |
4415 | } | |
761fcd9e AA |
4416 | rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL); |
4417 | tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL); | |
4418 | if (!rxtx_ring || !rx_skbuff || !tx_skbuff) { | |
eafa59f6 | 4419 | /* fall back to old rings */ |
36b30ea9 | 4420 | if (!nv_optimized(np)) { |
f82a9352 | 4421 | if (rxtx_ring) |
eafa59f6 AA |
4422 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), |
4423 | rxtx_ring, ring_addr); | |
4424 | } else { | |
4425 | if (rxtx_ring) | |
4426 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4427 | rxtx_ring, ring_addr); | |
4428 | } | |
9b03b06b SJ |
4429 | |
4430 | kfree(rx_skbuff); | |
4431 | kfree(tx_skbuff); | |
eafa59f6 AA |
4432 | goto exit; |
4433 | } | |
4434 | ||
4435 | if (netif_running(dev)) { | |
4436 | nv_disable_irq(dev); | |
08d93575 | 4437 | nv_napi_disable(dev); |
58dfd9c1 | 4438 | netif_tx_lock_bh(dev); |
e308a5d8 | 4439 | netif_addr_lock(dev); |
eafa59f6 AA |
4440 | spin_lock(&np->lock); |
4441 | /* stop engines */ | |
36b30ea9 | 4442 | nv_stop_rxtx(dev); |
eafa59f6 AA |
4443 | nv_txrx_reset(dev); |
4444 | /* drain queues */ | |
36b30ea9 | 4445 | nv_drain_rxtx(dev); |
eafa59f6 AA |
4446 | /* delete queues */ |
4447 | free_rings(dev); | |
4448 | } | |
4449 | ||
4450 | /* set new values */ | |
4451 | np->rx_ring_size = ring->rx_pending; | |
4452 | np->tx_ring_size = ring->tx_pending; | |
36b30ea9 JG |
4453 | |
4454 | if (!nv_optimized(np)) { | |
78aea4fc | 4455 | np->rx_ring.orig = (struct ring_desc *)rxtx_ring; |
eafa59f6 AA |
4456 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
4457 | } else { | |
78aea4fc | 4458 | np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring; |
eafa59f6 AA |
4459 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
4460 | } | |
78aea4fc SJ |
4461 | np->rx_skb = (struct nv_skb_map *)rx_skbuff; |
4462 | np->tx_skb = (struct nv_skb_map *)tx_skbuff; | |
eafa59f6 AA |
4463 | np->ring_addr = ring_addr; |
4464 | ||
761fcd9e AA |
4465 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
4466 | memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); | |
eafa59f6 AA |
4467 | |
4468 | if (netif_running(dev)) { | |
4469 | /* reinit driver view of the queues */ | |
4470 | set_bufsize(dev); | |
4471 | if (nv_init_ring(dev)) { | |
4472 | if (!np->in_shutdown) | |
4473 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4474 | } | |
4475 | ||
4476 | /* reinit nic view of the queues */ | |
4477 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4478 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4479 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
eafa59f6 AA |
4480 | base + NvRegRingSizes); |
4481 | pci_push(base); | |
4482 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4483 | pci_push(base); | |
4484 | ||
4485 | /* restart engines */ | |
36b30ea9 | 4486 | nv_start_rxtx(dev); |
eafa59f6 | 4487 | spin_unlock(&np->lock); |
e308a5d8 | 4488 | netif_addr_unlock(dev); |
58dfd9c1 | 4489 | netif_tx_unlock_bh(dev); |
08d93575 | 4490 | nv_napi_enable(dev); |
eafa59f6 AA |
4491 | nv_enable_irq(dev); |
4492 | } | |
4493 | return 0; | |
4494 | exit: | |
4495 | return -ENOMEM; | |
4496 | } | |
4497 | ||
b6d0773f AA |
4498 | static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
4499 | { | |
4500 | struct fe_priv *np = netdev_priv(dev); | |
4501 | ||
4502 | pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; | |
4503 | pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; | |
4504 | pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; | |
4505 | } | |
4506 | ||
4507 | static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) | |
4508 | { | |
4509 | struct fe_priv *np = netdev_priv(dev); | |
4510 | int adv, bmcr; | |
4511 | ||
4512 | if ((!np->autoneg && np->duplex == 0) || | |
4513 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { | |
1d397f36 | 4514 | netdev_info(dev, "can not set pause settings when forced link is in half duplex\n"); |
b6d0773f AA |
4515 | return -EINVAL; |
4516 | } | |
4517 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { | |
1d397f36 | 4518 | netdev_info(dev, "hardware does not support tx pause frames\n"); |
b6d0773f AA |
4519 | return -EINVAL; |
4520 | } | |
4521 | ||
4522 | netif_carrier_off(dev); | |
4523 | if (netif_running(dev)) { | |
4524 | nv_disable_irq(dev); | |
58dfd9c1 | 4525 | netif_tx_lock_bh(dev); |
e308a5d8 | 4526 | netif_addr_lock(dev); |
b6d0773f AA |
4527 | spin_lock(&np->lock); |
4528 | /* stop engines */ | |
36b30ea9 | 4529 | nv_stop_rxtx(dev); |
b6d0773f | 4530 | spin_unlock(&np->lock); |
e308a5d8 | 4531 | netif_addr_unlock(dev); |
58dfd9c1 | 4532 | netif_tx_unlock_bh(dev); |
b6d0773f AA |
4533 | } |
4534 | ||
4535 | np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); | |
4536 | if (pause->rx_pause) | |
4537 | np->pause_flags |= NV_PAUSEFRAME_RX_REQ; | |
4538 | if (pause->tx_pause) | |
4539 | np->pause_flags |= NV_PAUSEFRAME_TX_REQ; | |
4540 | ||
4541 | if (np->autoneg && pause->autoneg) { | |
4542 | np->pause_flags |= NV_PAUSEFRAME_AUTONEG; | |
4543 | ||
4544 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
4545 | adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
4546 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ | |
4547 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4548 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4549 | adv |= ADVERTISE_PAUSE_ASYM; | |
4550 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | |
4551 | ||
4552 | if (netif_running(dev)) | |
1d397f36 | 4553 | netdev_info(dev, "link down\n"); |
b6d0773f AA |
4554 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
4555 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4556 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4557 | } else { | |
4558 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4559 | if (pause->rx_pause) | |
4560 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4561 | if (pause->tx_pause) | |
4562 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4563 | ||
4564 | if (!netif_running(dev)) | |
4565 | nv_update_linkspeed(dev); | |
4566 | else | |
4567 | nv_update_pause(dev, np->pause_flags); | |
4568 | } | |
4569 | ||
4570 | if (netif_running(dev)) { | |
36b30ea9 | 4571 | nv_start_rxtx(dev); |
b6d0773f AA |
4572 | nv_enable_irq(dev); |
4573 | } | |
4574 | return 0; | |
4575 | } | |
4576 | ||
5ed2616f AA |
4577 | static u32 nv_get_rx_csum(struct net_device *dev) |
4578 | { | |
4579 | struct fe_priv *np = netdev_priv(dev); | |
807540ba | 4580 | return np->rx_csum != 0; |
5ed2616f AA |
4581 | } |
4582 | ||
4583 | static int nv_set_rx_csum(struct net_device *dev, u32 data) | |
4584 | { | |
4585 | struct fe_priv *np = netdev_priv(dev); | |
4586 | u8 __iomem *base = get_hwbase(dev); | |
4587 | int retcode = 0; | |
4588 | ||
4589 | if (np->driver_data & DEV_HAS_CHECKSUM) { | |
5ed2616f | 4590 | if (data) { |
f2ad2d9b | 4591 | np->rx_csum = 1; |
5ed2616f | 4592 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
5ed2616f | 4593 | } else { |
f2ad2d9b AA |
4594 | np->rx_csum = 0; |
4595 | /* vlan is dependent on rx checksum offload */ | |
4596 | if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) | |
4597 | np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; | |
5ed2616f | 4598 | } |
5ed2616f AA |
4599 | if (netif_running(dev)) { |
4600 | spin_lock_irq(&np->lock); | |
4601 | writel(np->txrxctl_bits, base + NvRegTxRxControl); | |
4602 | spin_unlock_irq(&np->lock); | |
4603 | } | |
4604 | } else { | |
4605 | return -EINVAL; | |
4606 | } | |
4607 | ||
4608 | return retcode; | |
4609 | } | |
4610 | ||
4611 | static int nv_set_tx_csum(struct net_device *dev, u32 data) | |
4612 | { | |
4613 | struct fe_priv *np = netdev_priv(dev); | |
4614 | ||
4615 | if (np->driver_data & DEV_HAS_CHECKSUM) | |
c1086cda | 4616 | return ethtool_op_set_tx_csum(dev, data); |
5ed2616f AA |
4617 | else |
4618 | return -EOPNOTSUPP; | |
4619 | } | |
4620 | ||
4621 | static int nv_set_sg(struct net_device *dev, u32 data) | |
4622 | { | |
4623 | struct fe_priv *np = netdev_priv(dev); | |
4624 | ||
4625 | if (np->driver_data & DEV_HAS_CHECKSUM) | |
4626 | return ethtool_op_set_sg(dev, data); | |
4627 | else | |
4628 | return -EOPNOTSUPP; | |
4629 | } | |
4630 | ||
b9f2c044 | 4631 | static int nv_get_sset_count(struct net_device *dev, int sset) |
52da3578 AA |
4632 | { |
4633 | struct fe_priv *np = netdev_priv(dev); | |
4634 | ||
b9f2c044 JG |
4635 | switch (sset) { |
4636 | case ETH_SS_TEST: | |
4637 | if (np->driver_data & DEV_HAS_TEST_EXTENDED) | |
4638 | return NV_TEST_COUNT_EXTENDED; | |
4639 | else | |
4640 | return NV_TEST_COUNT_BASE; | |
4641 | case ETH_SS_STATS: | |
8ed1454a AA |
4642 | if (np->driver_data & DEV_HAS_STATISTICS_V3) |
4643 | return NV_DEV_STATISTICS_V3_COUNT; | |
b9f2c044 JG |
4644 | else if (np->driver_data & DEV_HAS_STATISTICS_V2) |
4645 | return NV_DEV_STATISTICS_V2_COUNT; | |
8ed1454a AA |
4646 | else if (np->driver_data & DEV_HAS_STATISTICS_V1) |
4647 | return NV_DEV_STATISTICS_V1_COUNT; | |
b9f2c044 JG |
4648 | else |
4649 | return 0; | |
4650 | default: | |
4651 | return -EOPNOTSUPP; | |
4652 | } | |
52da3578 AA |
4653 | } |
4654 | ||
4655 | static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer) | |
4656 | { | |
4657 | struct fe_priv *np = netdev_priv(dev); | |
4658 | ||
4659 | /* update stats */ | |
4660 | nv_do_stats_poll((unsigned long)dev); | |
4661 | ||
b9f2c044 | 4662 | memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64)); |
9589c77a AA |
4663 | } |
4664 | ||
4665 | static int nv_link_test(struct net_device *dev) | |
4666 | { | |
4667 | struct fe_priv *np = netdev_priv(dev); | |
4668 | int mii_status; | |
4669 | ||
4670 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4671 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4672 | ||
4673 | /* check phy link status */ | |
4674 | if (!(mii_status & BMSR_LSTATUS)) | |
4675 | return 0; | |
4676 | else | |
4677 | return 1; | |
4678 | } | |
4679 | ||
4680 | static int nv_register_test(struct net_device *dev) | |
4681 | { | |
4682 | u8 __iomem *base = get_hwbase(dev); | |
4683 | int i = 0; | |
4684 | u32 orig_read, new_read; | |
4685 | ||
4686 | do { | |
4687 | orig_read = readl(base + nv_registers_test[i].reg); | |
4688 | ||
4689 | /* xor with mask to toggle bits */ | |
4690 | orig_read ^= nv_registers_test[i].mask; | |
4691 | ||
4692 | writel(orig_read, base + nv_registers_test[i].reg); | |
4693 | ||
4694 | new_read = readl(base + nv_registers_test[i].reg); | |
4695 | ||
4696 | if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask)) | |
4697 | return 0; | |
4698 | ||
4699 | /* restore original value */ | |
4700 | orig_read ^= nv_registers_test[i].mask; | |
4701 | writel(orig_read, base + nv_registers_test[i].reg); | |
4702 | ||
4703 | } while (nv_registers_test[++i].reg != 0); | |
4704 | ||
4705 | return 1; | |
4706 | } | |
4707 | ||
4708 | static int nv_interrupt_test(struct net_device *dev) | |
4709 | { | |
4710 | struct fe_priv *np = netdev_priv(dev); | |
4711 | u8 __iomem *base = get_hwbase(dev); | |
4712 | int ret = 1; | |
4713 | int testcnt; | |
4714 | u32 save_msi_flags, save_poll_interval = 0; | |
4715 | ||
4716 | if (netif_running(dev)) { | |
4717 | /* free current irq */ | |
4718 | nv_free_irq(dev); | |
4719 | save_poll_interval = readl(base+NvRegPollingInterval); | |
4720 | } | |
4721 | ||
4722 | /* flag to test interrupt handler */ | |
4723 | np->intr_test = 0; | |
4724 | ||
4725 | /* setup test irq */ | |
4726 | save_msi_flags = np->msi_flags; | |
4727 | np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; | |
4728 | np->msi_flags |= 0x001; /* setup 1 vector */ | |
4729 | if (nv_request_irq(dev, 1)) | |
4730 | return 0; | |
4731 | ||
4732 | /* setup timer interrupt */ | |
4733 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
4734 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4735 | ||
4736 | nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4737 | ||
4738 | /* wait for at least one interrupt */ | |
4739 | msleep(100); | |
4740 | ||
4741 | spin_lock_irq(&np->lock); | |
4742 | ||
4743 | /* flag should be set within ISR */ | |
4744 | testcnt = np->intr_test; | |
4745 | if (!testcnt) | |
4746 | ret = 2; | |
4747 | ||
4748 | nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4749 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
4750 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4751 | else | |
4752 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
4753 | ||
4754 | spin_unlock_irq(&np->lock); | |
4755 | ||
4756 | nv_free_irq(dev); | |
4757 | ||
4758 | np->msi_flags = save_msi_flags; | |
4759 | ||
4760 | if (netif_running(dev)) { | |
4761 | writel(save_poll_interval, base + NvRegPollingInterval); | |
4762 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4763 | /* restore original irq */ | |
4764 | if (nv_request_irq(dev, 0)) | |
4765 | return 0; | |
4766 | } | |
4767 | ||
4768 | return ret; | |
4769 | } | |
4770 | ||
4771 | static int nv_loopback_test(struct net_device *dev) | |
4772 | { | |
4773 | struct fe_priv *np = netdev_priv(dev); | |
4774 | u8 __iomem *base = get_hwbase(dev); | |
4775 | struct sk_buff *tx_skb, *rx_skb; | |
4776 | dma_addr_t test_dma_addr; | |
4777 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); | |
f82a9352 | 4778 | u32 flags; |
9589c77a AA |
4779 | int len, i, pkt_len; |
4780 | u8 *pkt_data; | |
4781 | u32 filter_flags = 0; | |
4782 | u32 misc1_flags = 0; | |
4783 | int ret = 1; | |
4784 | ||
4785 | if (netif_running(dev)) { | |
4786 | nv_disable_irq(dev); | |
4787 | filter_flags = readl(base + NvRegPacketFilterFlags); | |
4788 | misc1_flags = readl(base + NvRegMisc1); | |
4789 | } else { | |
4790 | nv_txrx_reset(dev); | |
4791 | } | |
4792 | ||
4793 | /* reinit driver view of the rx queue */ | |
4794 | set_bufsize(dev); | |
4795 | nv_init_ring(dev); | |
4796 | ||
4797 | /* setup hardware for loopback */ | |
4798 | writel(NVREG_MISC1_FORCE, base + NvRegMisc1); | |
4799 | writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); | |
4800 | ||
4801 | /* reinit nic view of the rx queue */ | |
4802 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4803 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4804 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
9589c77a AA |
4805 | base + NvRegRingSizes); |
4806 | pci_push(base); | |
4807 | ||
4808 | /* restart rx engine */ | |
36b30ea9 | 4809 | nv_start_rxtx(dev); |
9589c77a AA |
4810 | |
4811 | /* setup packet for tx */ | |
4812 | pkt_len = ETH_DATA_LEN; | |
4813 | tx_skb = dev_alloc_skb(pkt_len); | |
46798c89 | 4814 | if (!tx_skb) { |
1d397f36 | 4815 | netdev_err(dev, "dev_alloc_skb() failed during loopback test\n"); |
46798c89 JJ |
4816 | ret = 0; |
4817 | goto out; | |
4818 | } | |
8b5be268 ACM |
4819 | test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data, |
4820 | skb_tailroom(tx_skb), | |
4821 | PCI_DMA_FROMDEVICE); | |
9589c77a AA |
4822 | pkt_data = skb_put(tx_skb, pkt_len); |
4823 | for (i = 0; i < pkt_len; i++) | |
4824 | pkt_data[i] = (u8)(i & 0xff); | |
9589c77a | 4825 | |
36b30ea9 | 4826 | if (!nv_optimized(np)) { |
f82a9352 SH |
4827 | np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); |
4828 | np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); | |
9589c77a | 4829 | } else { |
5bb7ea26 AV |
4830 | np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr)); |
4831 | np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr)); | |
f82a9352 | 4832 | np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); |
9589c77a AA |
4833 | } |
4834 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4835 | pci_push(get_hwbase(dev)); | |
4836 | ||
4837 | msleep(500); | |
4838 | ||
4839 | /* check for rx of the packet */ | |
36b30ea9 | 4840 | if (!nv_optimized(np)) { |
f82a9352 | 4841 | flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); |
9589c77a AA |
4842 | len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
4843 | ||
4844 | } else { | |
f82a9352 | 4845 | flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); |
9589c77a AA |
4846 | len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
4847 | } | |
4848 | ||
f82a9352 | 4849 | if (flags & NV_RX_AVAIL) { |
9589c77a AA |
4850 | ret = 0; |
4851 | } else if (np->desc_ver == DESC_VER_1) { | |
f82a9352 | 4852 | if (flags & NV_RX_ERROR) |
9589c77a AA |
4853 | ret = 0; |
4854 | } else { | |
78aea4fc | 4855 | if (flags & NV_RX2_ERROR) |
9589c77a | 4856 | ret = 0; |
9589c77a AA |
4857 | } |
4858 | ||
4859 | if (ret) { | |
4860 | if (len != pkt_len) { | |
4861 | ret = 0; | |
6b80858d JP |
4862 | netdev_dbg(dev, "loopback len mismatch %d vs %d\n", |
4863 | len, pkt_len); | |
9589c77a | 4864 | } else { |
761fcd9e | 4865 | rx_skb = np->rx_skb[0].skb; |
9589c77a AA |
4866 | for (i = 0; i < pkt_len; i++) { |
4867 | if (rx_skb->data[i] != (u8)(i & 0xff)) { | |
4868 | ret = 0; | |
6b80858d JP |
4869 | netdev_dbg(dev, "loopback pattern check failed on byte %d\n", |
4870 | i); | |
9589c77a AA |
4871 | break; |
4872 | } | |
4873 | } | |
4874 | } | |
4875 | } else { | |
6b80858d | 4876 | netdev_dbg(dev, "loopback - did not receive test packet\n"); |
9589c77a AA |
4877 | } |
4878 | ||
73a37079 | 4879 | pci_unmap_single(np->pci_dev, test_dma_addr, |
4305b541 | 4880 | (skb_end_pointer(tx_skb) - tx_skb->data), |
9589c77a AA |
4881 | PCI_DMA_TODEVICE); |
4882 | dev_kfree_skb_any(tx_skb); | |
46798c89 | 4883 | out: |
9589c77a | 4884 | /* stop engines */ |
36b30ea9 | 4885 | nv_stop_rxtx(dev); |
9589c77a AA |
4886 | nv_txrx_reset(dev); |
4887 | /* drain rx queue */ | |
36b30ea9 | 4888 | nv_drain_rxtx(dev); |
9589c77a AA |
4889 | |
4890 | if (netif_running(dev)) { | |
4891 | writel(misc1_flags, base + NvRegMisc1); | |
4892 | writel(filter_flags, base + NvRegPacketFilterFlags); | |
4893 | nv_enable_irq(dev); | |
4894 | } | |
4895 | ||
4896 | return ret; | |
4897 | } | |
4898 | ||
4899 | static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) | |
4900 | { | |
4901 | struct fe_priv *np = netdev_priv(dev); | |
4902 | u8 __iomem *base = get_hwbase(dev); | |
4903 | int result; | |
b9f2c044 | 4904 | memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64)); |
9589c77a AA |
4905 | |
4906 | if (!nv_link_test(dev)) { | |
4907 | test->flags |= ETH_TEST_FL_FAILED; | |
4908 | buffer[0] = 1; | |
4909 | } | |
4910 | ||
4911 | if (test->flags & ETH_TEST_FL_OFFLINE) { | |
4912 | if (netif_running(dev)) { | |
4913 | netif_stop_queue(dev); | |
08d93575 | 4914 | nv_napi_disable(dev); |
58dfd9c1 | 4915 | netif_tx_lock_bh(dev); |
e308a5d8 | 4916 | netif_addr_lock(dev); |
9589c77a AA |
4917 | spin_lock_irq(&np->lock); |
4918 | nv_disable_hw_interrupts(dev, np->irqmask); | |
78aea4fc | 4919 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
9589c77a | 4920 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
78aea4fc | 4921 | else |
9589c77a | 4922 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
9589c77a | 4923 | /* stop engines */ |
36b30ea9 | 4924 | nv_stop_rxtx(dev); |
9589c77a AA |
4925 | nv_txrx_reset(dev); |
4926 | /* drain rx queue */ | |
36b30ea9 | 4927 | nv_drain_rxtx(dev); |
9589c77a | 4928 | spin_unlock_irq(&np->lock); |
e308a5d8 | 4929 | netif_addr_unlock(dev); |
58dfd9c1 | 4930 | netif_tx_unlock_bh(dev); |
9589c77a AA |
4931 | } |
4932 | ||
4933 | if (!nv_register_test(dev)) { | |
4934 | test->flags |= ETH_TEST_FL_FAILED; | |
4935 | buffer[1] = 1; | |
4936 | } | |
4937 | ||
4938 | result = nv_interrupt_test(dev); | |
4939 | if (result != 1) { | |
4940 | test->flags |= ETH_TEST_FL_FAILED; | |
4941 | buffer[2] = 1; | |
4942 | } | |
4943 | if (result == 0) { | |
4944 | /* bail out */ | |
4945 | return; | |
4946 | } | |
4947 | ||
4948 | if (!nv_loopback_test(dev)) { | |
4949 | test->flags |= ETH_TEST_FL_FAILED; | |
4950 | buffer[3] = 1; | |
4951 | } | |
4952 | ||
4953 | if (netif_running(dev)) { | |
4954 | /* reinit driver view of the rx queue */ | |
4955 | set_bufsize(dev); | |
4956 | if (nv_init_ring(dev)) { | |
4957 | if (!np->in_shutdown) | |
4958 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4959 | } | |
4960 | /* reinit nic view of the rx queue */ | |
4961 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4962 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4963 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
9589c77a AA |
4964 | base + NvRegRingSizes); |
4965 | pci_push(base); | |
4966 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4967 | pci_push(base); | |
4968 | /* restart rx engine */ | |
36b30ea9 | 4969 | nv_start_rxtx(dev); |
9589c77a | 4970 | netif_start_queue(dev); |
08d93575 | 4971 | nv_napi_enable(dev); |
9589c77a AA |
4972 | nv_enable_hw_interrupts(dev, np->irqmask); |
4973 | } | |
4974 | } | |
4975 | } | |
4976 | ||
52da3578 AA |
4977 | static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer) |
4978 | { | |
4979 | switch (stringset) { | |
4980 | case ETH_SS_STATS: | |
b9f2c044 | 4981 | memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str)); |
52da3578 | 4982 | break; |
9589c77a | 4983 | case ETH_SS_TEST: |
b9f2c044 | 4984 | memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str)); |
9589c77a | 4985 | break; |
52da3578 AA |
4986 | } |
4987 | } | |
4988 | ||
7282d491 | 4989 | static const struct ethtool_ops ops = { |
1da177e4 LT |
4990 | .get_drvinfo = nv_get_drvinfo, |
4991 | .get_link = ethtool_op_get_link, | |
4992 | .get_wol = nv_get_wol, | |
4993 | .set_wol = nv_set_wol, | |
4994 | .get_settings = nv_get_settings, | |
4995 | .set_settings = nv_set_settings, | |
dc8216c1 MS |
4996 | .get_regs_len = nv_get_regs_len, |
4997 | .get_regs = nv_get_regs, | |
4998 | .nway_reset = nv_nway_reset, | |
6a78814f | 4999 | .set_tso = nv_set_tso, |
eafa59f6 AA |
5000 | .get_ringparam = nv_get_ringparam, |
5001 | .set_ringparam = nv_set_ringparam, | |
b6d0773f AA |
5002 | .get_pauseparam = nv_get_pauseparam, |
5003 | .set_pauseparam = nv_set_pauseparam, | |
5ed2616f AA |
5004 | .get_rx_csum = nv_get_rx_csum, |
5005 | .set_rx_csum = nv_set_rx_csum, | |
5ed2616f | 5006 | .set_tx_csum = nv_set_tx_csum, |
5ed2616f | 5007 | .set_sg = nv_set_sg, |
52da3578 | 5008 | .get_strings = nv_get_strings, |
52da3578 | 5009 | .get_ethtool_stats = nv_get_ethtool_stats, |
b9f2c044 | 5010 | .get_sset_count = nv_get_sset_count, |
9589c77a | 5011 | .self_test = nv_self_test, |
1da177e4 LT |
5012 | }; |
5013 | ||
ee407b02 AA |
5014 | static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
5015 | { | |
5016 | struct fe_priv *np = get_nvpriv(dev); | |
5017 | ||
5018 | spin_lock_irq(&np->lock); | |
5019 | ||
5020 | /* save vlan group */ | |
5021 | np->vlangrp = grp; | |
5022 | ||
5023 | if (grp) { | |
5024 | /* enable vlan on MAC */ | |
5025 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; | |
5026 | } else { | |
5027 | /* disable vlan on MAC */ | |
5028 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; | |
5029 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; | |
5030 | } | |
5031 | ||
5032 | writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
5033 | ||
5034 | spin_unlock_irq(&np->lock); | |
25805dcf | 5035 | } |
ee407b02 | 5036 | |
7e680c22 AA |
5037 | /* The mgmt unit and driver use a semaphore to access the phy during init */ |
5038 | static int nv_mgmt_acquire_sema(struct net_device *dev) | |
5039 | { | |
cac1c52c | 5040 | struct fe_priv *np = netdev_priv(dev); |
7e680c22 AA |
5041 | u8 __iomem *base = get_hwbase(dev); |
5042 | int i; | |
5043 | u32 tx_ctrl, mgmt_sema; | |
5044 | ||
5045 | for (i = 0; i < 10; i++) { | |
5046 | mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; | |
5047 | if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) | |
5048 | break; | |
5049 | msleep(500); | |
5050 | } | |
5051 | ||
5052 | if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) | |
5053 | return 0; | |
5054 | ||
5055 | for (i = 0; i < 2; i++) { | |
5056 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5057 | tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; | |
5058 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
5059 | ||
5060 | /* verify that semaphore was acquired */ | |
5061 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5062 | if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && | |
cac1c52c AA |
5063 | ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { |
5064 | np->mgmt_sema = 1; | |
7e680c22 | 5065 | return 1; |
78aea4fc | 5066 | } else |
7e680c22 AA |
5067 | udelay(50); |
5068 | } | |
5069 | ||
5070 | return 0; | |
5071 | } | |
5072 | ||
cac1c52c AA |
5073 | static void nv_mgmt_release_sema(struct net_device *dev) |
5074 | { | |
5075 | struct fe_priv *np = netdev_priv(dev); | |
5076 | u8 __iomem *base = get_hwbase(dev); | |
5077 | u32 tx_ctrl; | |
5078 | ||
5079 | if (np->driver_data & DEV_HAS_MGMT_UNIT) { | |
5080 | if (np->mgmt_sema) { | |
5081 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5082 | tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ; | |
5083 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
5084 | } | |
5085 | } | |
5086 | } | |
5087 | ||
5088 | ||
5089 | static int nv_mgmt_get_version(struct net_device *dev) | |
5090 | { | |
5091 | struct fe_priv *np = netdev_priv(dev); | |
5092 | u8 __iomem *base = get_hwbase(dev); | |
5093 | u32 data_ready = readl(base + NvRegTransmitterControl); | |
5094 | u32 data_ready2 = 0; | |
5095 | unsigned long start; | |
5096 | int ready = 0; | |
5097 | ||
5098 | writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion); | |
5099 | writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl); | |
5100 | start = jiffies; | |
5101 | while (time_before(jiffies, start + 5*HZ)) { | |
5102 | data_ready2 = readl(base + NvRegTransmitterControl); | |
5103 | if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) { | |
5104 | ready = 1; | |
5105 | break; | |
5106 | } | |
5107 | schedule_timeout_uninterruptible(1); | |
5108 | } | |
5109 | ||
5110 | if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR)) | |
5111 | return 0; | |
5112 | ||
5113 | np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION; | |
5114 | ||
5115 | return 1; | |
5116 | } | |
5117 | ||
1da177e4 LT |
5118 | static int nv_open(struct net_device *dev) |
5119 | { | |
ac9c1897 | 5120 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 5121 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
5122 | int ret = 1; |
5123 | int oom, i; | |
a433686c | 5124 | u32 low; |
1da177e4 | 5125 | |
6b80858d | 5126 | netdev_dbg(dev, "%s\n", __func__); |
1da177e4 | 5127 | |
cb52deba ES |
5128 | /* power up phy */ |
5129 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5130 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); | |
5131 | ||
88d7d8b0 | 5132 | nv_txrx_gate(dev, false); |
f1489653 | 5133 | /* erase previous misconfiguration */ |
86a0f043 AA |
5134 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
5135 | nv_mac_reset(dev); | |
1da177e4 LT |
5136 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
5137 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5138 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5139 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5140 | writel(0, base + NvRegPacketFilterFlags); |
5141 | ||
5142 | writel(0, base + NvRegTransmitterControl); | |
5143 | writel(0, base + NvRegReceiverControl); | |
5144 | ||
5145 | writel(0, base + NvRegAdapterControl); | |
5146 | ||
eb91f61b AA |
5147 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
5148 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
5149 | ||
f1489653 | 5150 | /* initialize descriptor rings */ |
d81c0983 | 5151 | set_bufsize(dev); |
1da177e4 LT |
5152 | oom = nv_init_ring(dev); |
5153 | ||
5154 | writel(0, base + NvRegLinkSpeed); | |
5070d340 | 5155 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
1da177e4 LT |
5156 | nv_txrx_reset(dev); |
5157 | writel(0, base + NvRegUnknownSetupReg6); | |
5158 | ||
5159 | np->in_shutdown = 0; | |
5160 | ||
f1489653 | 5161 | /* give hw rings */ |
0832b25a | 5162 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
78aea4fc | 5163 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
1da177e4 LT |
5164 | base + NvRegRingSizes); |
5165 | ||
1da177e4 | 5166 | writel(np->linkspeed, base + NvRegLinkSpeed); |
95d161cb AA |
5167 | if (np->desc_ver == DESC_VER_1) |
5168 | writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); | |
5169 | else | |
5170 | writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); | |
8a4ae7f2 | 5171 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
ee407b02 | 5172 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
1da177e4 | 5173 | pci_push(base); |
8a4ae7f2 | 5174 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
344d0dce JP |
5175 | if (reg_delay(dev, NvRegUnknownSetupReg5, |
5176 | NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, | |
5177 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX)) | |
1d397f36 JP |
5178 | netdev_info(dev, |
5179 | "%s: SetupReg5, Bit 31 remained off\n", __func__); | |
1da177e4 | 5180 | |
7e680c22 | 5181 | writel(0, base + NvRegMIIMask); |
1da177e4 | 5182 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
eb798428 | 5183 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 | 5184 | |
1da177e4 LT |
5185 | writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
5186 | writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); | |
5187 | writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); | |
d81c0983 | 5188 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
1da177e4 LT |
5189 | |
5190 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); | |
a433686c AA |
5191 | |
5192 | get_random_bytes(&low, sizeof(low)); | |
5193 | low &= NVREG_SLOTTIME_MASK; | |
5194 | if (np->desc_ver == DESC_VER_1) { | |
5195 | writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime); | |
5196 | } else { | |
5197 | if (!(np->driver_data & DEV_HAS_GEAR_MODE)) { | |
5198 | /* setup legacy backoff */ | |
5199 | writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime); | |
5200 | } else { | |
5201 | writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime); | |
5202 | nv_gear_backoff_reseed(dev); | |
5203 | } | |
5204 | } | |
9744e218 AA |
5205 | writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); |
5206 | writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); | |
a971c324 AA |
5207 | if (poll_interval == -1) { |
5208 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) | |
5209 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | |
5210 | else | |
5211 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
78aea4fc | 5212 | } else |
a971c324 | 5213 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); |
1da177e4 LT |
5214 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
5215 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, | |
5216 | base + NvRegAdapterControl); | |
5217 | writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); | |
7e680c22 | 5218 | writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); |
c42d9df9 AA |
5219 | if (np->wolenabled) |
5220 | writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); | |
1da177e4 LT |
5221 | |
5222 | i = readl(base + NvRegPowerState); | |
78aea4fc | 5223 | if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) |
1da177e4 LT |
5224 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); |
5225 | ||
5226 | pci_push(base); | |
5227 | udelay(10); | |
5228 | writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); | |
5229 | ||
84b3932b | 5230 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5231 | pci_push(base); |
eb798428 | 5232 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 LT |
5233 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
5234 | pci_push(base); | |
5235 | ||
78aea4fc | 5236 | if (nv_request_irq(dev, 0)) |
84b3932b | 5237 | goto out_drain; |
1da177e4 LT |
5238 | |
5239 | /* ask for interrupts */ | |
84b3932b | 5240 | nv_enable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
5241 | |
5242 | spin_lock_irq(&np->lock); | |
5243 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); | |
5244 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5245 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5246 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5247 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
5248 | /* One manual link speed update: Interrupts are enabled, future link | |
5249 | * speed changes cause interrupts and are handled by nv_link_irq(). | |
5250 | */ | |
5251 | { | |
5252 | u32 miistat; | |
5253 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 5254 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
f52dafc1 | 5255 | netdev_dbg(dev, "startup: got 0x%08x\n", miistat); |
1da177e4 | 5256 | } |
1b1b3c9b MS |
5257 | /* set linkspeed to invalid value, thus force nv_update_linkspeed |
5258 | * to init hw */ | |
5259 | np->linkspeed = 0; | |
1da177e4 | 5260 | ret = nv_update_linkspeed(dev); |
36b30ea9 | 5261 | nv_start_rxtx(dev); |
1da177e4 | 5262 | netif_start_queue(dev); |
08d93575 | 5263 | nv_napi_enable(dev); |
e27cdba5 | 5264 | |
1da177e4 LT |
5265 | if (ret) { |
5266 | netif_carrier_on(dev); | |
5267 | } else { | |
1d397f36 | 5268 | netdev_info(dev, "no link during initialization\n"); |
1da177e4 LT |
5269 | netif_carrier_off(dev); |
5270 | } | |
5271 | if (oom) | |
5272 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
52da3578 AA |
5273 | |
5274 | /* start statistics timer */ | |
9c662435 | 5275 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
bfebbb88 DD |
5276 | mod_timer(&np->stats_poll, |
5277 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 | 5278 | |
1da177e4 LT |
5279 | spin_unlock_irq(&np->lock); |
5280 | ||
5281 | return 0; | |
5282 | out_drain: | |
36b30ea9 | 5283 | nv_drain_rxtx(dev); |
1da177e4 LT |
5284 | return ret; |
5285 | } | |
5286 | ||
5287 | static int nv_close(struct net_device *dev) | |
5288 | { | |
ac9c1897 | 5289 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
5290 | u8 __iomem *base; |
5291 | ||
5292 | spin_lock_irq(&np->lock); | |
5293 | np->in_shutdown = 1; | |
5294 | spin_unlock_irq(&np->lock); | |
08d93575 | 5295 | nv_napi_disable(dev); |
a7475906 | 5296 | synchronize_irq(np->pci_dev->irq); |
1da177e4 LT |
5297 | |
5298 | del_timer_sync(&np->oom_kick); | |
5299 | del_timer_sync(&np->nic_poll); | |
52da3578 | 5300 | del_timer_sync(&np->stats_poll); |
1da177e4 LT |
5301 | |
5302 | netif_stop_queue(dev); | |
5303 | spin_lock_irq(&np->lock); | |
36b30ea9 | 5304 | nv_stop_rxtx(dev); |
1da177e4 LT |
5305 | nv_txrx_reset(dev); |
5306 | ||
5307 | /* disable interrupts on the nic or we will lock up */ | |
5308 | base = get_hwbase(dev); | |
84b3932b | 5309 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5310 | pci_push(base); |
f52dafc1 | 5311 | netdev_dbg(dev, "Irqmask is zero again\n"); |
1da177e4 LT |
5312 | |
5313 | spin_unlock_irq(&np->lock); | |
5314 | ||
84b3932b | 5315 | nv_free_irq(dev); |
1da177e4 | 5316 | |
36b30ea9 | 5317 | nv_drain_rxtx(dev); |
1da177e4 | 5318 | |
5a9a8e32 | 5319 | if (np->wolenabled || !phy_power_down) { |
88d7d8b0 | 5320 | nv_txrx_gate(dev, false); |
2cc49a5c | 5321 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
1da177e4 | 5322 | nv_start_rx(dev); |
cb52deba ES |
5323 | } else { |
5324 | /* power down phy */ | |
5325 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5326 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); | |
88d7d8b0 | 5327 | nv_txrx_gate(dev, true); |
2cc49a5c | 5328 | } |
1da177e4 LT |
5329 | |
5330 | /* FIXME: power down nic */ | |
5331 | ||
5332 | return 0; | |
5333 | } | |
5334 | ||
b94426bd SH |
5335 | static const struct net_device_ops nv_netdev_ops = { |
5336 | .ndo_open = nv_open, | |
5337 | .ndo_stop = nv_close, | |
5338 | .ndo_get_stats = nv_get_stats, | |
00829823 SH |
5339 | .ndo_start_xmit = nv_start_xmit, |
5340 | .ndo_tx_timeout = nv_tx_timeout, | |
5341 | .ndo_change_mtu = nv_change_mtu, | |
5342 | .ndo_validate_addr = eth_validate_addr, | |
5343 | .ndo_set_mac_address = nv_set_mac_address, | |
5344 | .ndo_set_multicast_list = nv_set_multicast, | |
5345 | .ndo_vlan_rx_register = nv_vlan_rx_register, | |
5346 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5347 | .ndo_poll_controller = nv_poll_controller, | |
5348 | #endif | |
5349 | }; | |
5350 | ||
5351 | static const struct net_device_ops nv_netdev_ops_optimized = { | |
5352 | .ndo_open = nv_open, | |
5353 | .ndo_stop = nv_close, | |
5354 | .ndo_get_stats = nv_get_stats, | |
5355 | .ndo_start_xmit = nv_start_xmit_optimized, | |
b94426bd SH |
5356 | .ndo_tx_timeout = nv_tx_timeout, |
5357 | .ndo_change_mtu = nv_change_mtu, | |
5358 | .ndo_validate_addr = eth_validate_addr, | |
5359 | .ndo_set_mac_address = nv_set_mac_address, | |
5360 | .ndo_set_multicast_list = nv_set_multicast, | |
5361 | .ndo_vlan_rx_register = nv_vlan_rx_register, | |
5362 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5363 | .ndo_poll_controller = nv_poll_controller, | |
5364 | #endif | |
5365 | }; | |
5366 | ||
1da177e4 LT |
5367 | static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) |
5368 | { | |
5369 | struct net_device *dev; | |
5370 | struct fe_priv *np; | |
5371 | unsigned long addr; | |
5372 | u8 __iomem *base; | |
5373 | int err, i; | |
5070d340 | 5374 | u32 powerstate, txreg; |
7e680c22 AA |
5375 | u32 phystate_orig = 0, phystate; |
5376 | int phyinitialized = 0; | |
3f88ce49 JG |
5377 | static int printed_version; |
5378 | ||
5379 | if (!printed_version++) | |
294a554e JP |
5380 | pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n", |
5381 | FORCEDETH_VERSION); | |
1da177e4 LT |
5382 | |
5383 | dev = alloc_etherdev(sizeof(struct fe_priv)); | |
5384 | err = -ENOMEM; | |
5385 | if (!dev) | |
5386 | goto out; | |
5387 | ||
ac9c1897 | 5388 | np = netdev_priv(dev); |
bea3348e | 5389 | np->dev = dev; |
1da177e4 LT |
5390 | np->pci_dev = pci_dev; |
5391 | spin_lock_init(&np->lock); | |
1da177e4 LT |
5392 | SET_NETDEV_DEV(dev, &pci_dev->dev); |
5393 | ||
5394 | init_timer(&np->oom_kick); | |
5395 | np->oom_kick.data = (unsigned long) dev; | |
c061b18d | 5396 | np->oom_kick.function = nv_do_rx_refill; /* timer handler */ |
1da177e4 LT |
5397 | init_timer(&np->nic_poll); |
5398 | np->nic_poll.data = (unsigned long) dev; | |
c061b18d | 5399 | np->nic_poll.function = nv_do_nic_poll; /* timer handler */ |
52da3578 AA |
5400 | init_timer(&np->stats_poll); |
5401 | np->stats_poll.data = (unsigned long) dev; | |
c061b18d | 5402 | np->stats_poll.function = nv_do_stats_poll; /* timer handler */ |
1da177e4 LT |
5403 | |
5404 | err = pci_enable_device(pci_dev); | |
3f88ce49 | 5405 | if (err) |
1da177e4 | 5406 | goto out_free; |
1da177e4 LT |
5407 | |
5408 | pci_set_master(pci_dev); | |
5409 | ||
5410 | err = pci_request_regions(pci_dev, DRV_NAME); | |
5411 | if (err < 0) | |
5412 | goto out_disable; | |
5413 | ||
9c662435 | 5414 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
57fff698 AA |
5415 | np->register_size = NV_PCI_REGSZ_VER3; |
5416 | else if (id->driver_data & DEV_HAS_STATISTICS_V1) | |
86a0f043 AA |
5417 | np->register_size = NV_PCI_REGSZ_VER2; |
5418 | else | |
5419 | np->register_size = NV_PCI_REGSZ_VER1; | |
5420 | ||
1da177e4 LT |
5421 | err = -EINVAL; |
5422 | addr = 0; | |
5423 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
6b80858d JP |
5424 | netdev_dbg(dev, "%s: resource %d start %p len %lld flags 0x%08lx\n", |
5425 | pci_name(pci_dev), i, | |
5426 | (void *)(unsigned long)pci_resource_start(pci_dev, i), | |
5427 | (long long)pci_resource_len(pci_dev, i), | |
5428 | pci_resource_flags(pci_dev, i)); | |
1da177e4 | 5429 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && |
86a0f043 | 5430 | pci_resource_len(pci_dev, i) >= np->register_size) { |
1da177e4 LT |
5431 | addr = pci_resource_start(pci_dev, i); |
5432 | break; | |
5433 | } | |
5434 | } | |
5435 | if (i == DEVICE_COUNT_RESOURCE) { | |
3f88ce49 JG |
5436 | dev_printk(KERN_INFO, &pci_dev->dev, |
5437 | "Couldn't find register window\n"); | |
1da177e4 LT |
5438 | goto out_relreg; |
5439 | } | |
5440 | ||
86a0f043 AA |
5441 | /* copy of driver data */ |
5442 | np->driver_data = id->driver_data; | |
9f3f7910 AA |
5443 | /* copy of device id */ |
5444 | np->device_id = id->device; | |
86a0f043 | 5445 | |
1da177e4 | 5446 | /* handle different descriptor versions */ |
ee73362c MS |
5447 | if (id->driver_data & DEV_HAS_HIGH_DMA) { |
5448 | /* packet format 3: supports 40-bit addressing */ | |
5449 | np->desc_ver = DESC_VER_3; | |
84b3932b | 5450 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
69fe3fd7 | 5451 | if (dma_64bit) { |
6afd142f | 5452 | if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39))) |
3f88ce49 JG |
5453 | dev_printk(KERN_INFO, &pci_dev->dev, |
5454 | "64-bit DMA failed, using 32-bit addressing\n"); | |
5455 | else | |
69fe3fd7 | 5456 | dev->features |= NETIF_F_HIGHDMA; |
6afd142f | 5457 | if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) { |
3f88ce49 JG |
5458 | dev_printk(KERN_INFO, &pci_dev->dev, |
5459 | "64-bit DMA (consistent) failed, using 32-bit ring buffers\n"); | |
69fe3fd7 | 5460 | } |
ee73362c MS |
5461 | } |
5462 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { | |
5463 | /* packet format 2: supports jumbo frames */ | |
1da177e4 | 5464 | np->desc_ver = DESC_VER_2; |
8a4ae7f2 | 5465 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
ee73362c MS |
5466 | } else { |
5467 | /* original packet format */ | |
5468 | np->desc_ver = DESC_VER_1; | |
8a4ae7f2 | 5469 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
d81c0983 | 5470 | } |
ee73362c MS |
5471 | |
5472 | np->pkt_limit = NV_PKTLIMIT_1; | |
5473 | if (id->driver_data & DEV_HAS_LARGEDESC) | |
5474 | np->pkt_limit = NV_PKTLIMIT_2; | |
5475 | ||
8a4ae7f2 | 5476 | if (id->driver_data & DEV_HAS_CHECKSUM) { |
f2ad2d9b | 5477 | np->rx_csum = 1; |
8a4ae7f2 | 5478 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
edcfe5f7 | 5479 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
fa45459e | 5480 | dev->features |= NETIF_F_TSO; |
53f224cc | 5481 | dev->features |= NETIF_F_GRO; |
21828163 | 5482 | } |
8a4ae7f2 | 5483 | |
ee407b02 AA |
5484 | np->vlanctl_bits = 0; |
5485 | if (id->driver_data & DEV_HAS_VLAN) { | |
5486 | np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; | |
5487 | dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; | |
ee407b02 AA |
5488 | } |
5489 | ||
b6d0773f | 5490 | np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; |
5289b4c4 AA |
5491 | if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) || |
5492 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) || | |
5493 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) { | |
b6d0773f | 5494 | np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; |
eb91f61b | 5495 | } |
f3b197ac | 5496 | |
eb91f61b | 5497 | |
1da177e4 | 5498 | err = -ENOMEM; |
86a0f043 | 5499 | np->base = ioremap(addr, np->register_size); |
1da177e4 LT |
5500 | if (!np->base) |
5501 | goto out_relreg; | |
5502 | dev->base_addr = (unsigned long)np->base; | |
ee73362c | 5503 | |
1da177e4 | 5504 | dev->irq = pci_dev->irq; |
ee73362c | 5505 | |
eafa59f6 AA |
5506 | np->rx_ring_size = RX_RING_DEFAULT; |
5507 | np->tx_ring_size = TX_RING_DEFAULT; | |
eafa59f6 | 5508 | |
36b30ea9 | 5509 | if (!nv_optimized(np)) { |
ee73362c | 5510 | np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
eafa59f6 | 5511 | sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5512 | &np->ring_addr); |
5513 | if (!np->rx_ring.orig) | |
5514 | goto out_unmap; | |
eafa59f6 | 5515 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
ee73362c MS |
5516 | } else { |
5517 | np->rx_ring.ex = pci_alloc_consistent(pci_dev, | |
eafa59f6 | 5518 | sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5519 | &np->ring_addr); |
5520 | if (!np->rx_ring.ex) | |
5521 | goto out_unmap; | |
eafa59f6 AA |
5522 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
5523 | } | |
dd00cc48 YP |
5524 | np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); |
5525 | np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); | |
761fcd9e | 5526 | if (!np->rx_skb || !np->tx_skb) |
eafa59f6 | 5527 | goto out_freering; |
1da177e4 | 5528 | |
36b30ea9 | 5529 | if (!nv_optimized(np)) |
00829823 | 5530 | dev->netdev_ops = &nv_netdev_ops; |
86b22b0d | 5531 | else |
00829823 | 5532 | dev->netdev_ops = &nv_netdev_ops_optimized; |
b94426bd | 5533 | |
bea3348e | 5534 | netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP); |
1da177e4 | 5535 | SET_ETHTOOL_OPS(dev, &ops); |
1da177e4 LT |
5536 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
5537 | ||
5538 | pci_set_drvdata(pci_dev, dev); | |
5539 | ||
5540 | /* read the mac address */ | |
5541 | base = get_hwbase(dev); | |
5542 | np->orig_mac[0] = readl(base + NvRegMacAddrA); | |
5543 | np->orig_mac[1] = readl(base + NvRegMacAddrB); | |
5544 | ||
5070d340 AA |
5545 | /* check the workaround bit for correct mac address order */ |
5546 | txreg = readl(base + NvRegTransmitPoll); | |
a376e79c | 5547 | if (id->driver_data & DEV_HAS_CORRECT_MACADDR) { |
5070d340 AA |
5548 | /* mac address is already in correct order */ |
5549 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5550 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5551 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5552 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5553 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5554 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
a376e79c AA |
5555 | } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { |
5556 | /* mac address is already in correct order */ | |
5557 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5558 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5559 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5560 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5561 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5562 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
5563 | /* | |
5564 | * Set orig mac address back to the reversed version. | |
5565 | * This flag will be cleared during low power transition. | |
5566 | * Therefore, we should always put back the reversed address. | |
5567 | */ | |
5568 | np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) + | |
5569 | (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24); | |
5570 | np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8); | |
5070d340 AA |
5571 | } else { |
5572 | /* need to reverse mac address to correct order */ | |
5573 | dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; | |
5574 | dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; | |
5575 | dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; | |
5576 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; | |
5577 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | |
5578 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | |
5070d340 | 5579 | writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
f55c21fd | 5580 | printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n"); |
5070d340 | 5581 | } |
c704b856 | 5582 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 5583 | |
c704b856 | 5584 | if (!is_valid_ether_addr(dev->perm_addr)) { |
1da177e4 LT |
5585 | /* |
5586 | * Bad mac address. At least one bios sets the mac address | |
5587 | * to 01:23:45:67:89:ab | |
5588 | */ | |
3f88ce49 | 5589 | dev_printk(KERN_ERR, &pci_dev->dev, |
e174961c | 5590 | "Invalid Mac address detected: %pM\n", |
78aea4fc | 5591 | dev->dev_addr); |
3f88ce49 JG |
5592 | dev_printk(KERN_ERR, &pci_dev->dev, |
5593 | "Please complain to your hardware vendor. Switching to a random MAC.\n"); | |
655a6595 | 5594 | random_ether_addr(dev->dev_addr); |
1da177e4 LT |
5595 | } |
5596 | ||
6b80858d JP |
5597 | netdev_dbg(dev, "%s: MAC Address %pM\n", |
5598 | pci_name(pci_dev), dev->dev_addr); | |
1da177e4 | 5599 | |
f1489653 AA |
5600 | /* set mac address */ |
5601 | nv_copy_mac_to_hw(dev); | |
5602 | ||
9a60a826 TD |
5603 | /* Workaround current PCI init glitch: wakeup bits aren't |
5604 | * being set from PCI PM capability. | |
5605 | */ | |
5606 | device_init_wakeup(&pci_dev->dev, 1); | |
5607 | ||
1da177e4 LT |
5608 | /* disable WOL */ |
5609 | writel(0, base + NvRegWakeUpFlags); | |
5610 | np->wolenabled = 0; | |
5611 | ||
86a0f043 | 5612 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
86a0f043 AA |
5613 | |
5614 | /* take phy and nic out of low power mode */ | |
5615 | powerstate = readl(base + NvRegPowerState2); | |
5616 | powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; | |
3c2e1c11 | 5617 | if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) && |
44c10138 | 5618 | pci_dev->revision >= 0xA3) |
86a0f043 AA |
5619 | powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; |
5620 | writel(powerstate, base + NvRegPowerState2); | |
5621 | } | |
5622 | ||
78aea4fc | 5623 | if (np->desc_ver == DESC_VER_1) |
ac9c1897 | 5624 | np->tx_flags = NV_TX_VALID; |
78aea4fc | 5625 | else |
ac9c1897 | 5626 | np->tx_flags = NV_TX2_VALID; |
9e184767 AA |
5627 | |
5628 | np->msi_flags = 0; | |
78aea4fc | 5629 | if ((id->driver_data & DEV_HAS_MSI) && msi) |
9e184767 | 5630 | np->msi_flags |= NV_MSI_CAPABLE; |
78aea4fc | 5631 | |
9e184767 AA |
5632 | if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
5633 | /* msix has had reported issues when modifying irqmask | |
5634 | as in the case of napi, therefore, disable for now | |
5635 | */ | |
0a12761b | 5636 | #if 0 |
9e184767 AA |
5637 | np->msi_flags |= NV_MSI_X_CAPABLE; |
5638 | #endif | |
5639 | } | |
5640 | ||
5641 | if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) { | |
a971c324 | 5642 | np->irqmask = NVREG_IRQMASK_CPU; |
d33a73c8 AA |
5643 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5644 | np->msi_flags |= 0x0001; | |
9e184767 AA |
5645 | } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC && |
5646 | !(id->driver_data & DEV_NEED_TIMERIRQ)) { | |
5647 | /* start off in throughput mode */ | |
5648 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
5649 | /* remove support for msix mode */ | |
5650 | np->msi_flags &= ~NV_MSI_X_CAPABLE; | |
5651 | } else { | |
5652 | optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; | |
5653 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
5654 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ | |
5655 | np->msi_flags |= 0x0003; | |
d33a73c8 | 5656 | } |
a971c324 | 5657 | |
1da177e4 LT |
5658 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
5659 | np->irqmask |= NVREG_IRQ_TIMER; | |
5660 | if (id->driver_data & DEV_NEED_LINKTIMER) { | |
f52dafc1 | 5661 | netdev_dbg(dev, "%s: link timer on\n", pci_name(pci_dev)); |
1da177e4 LT |
5662 | np->need_linktimer = 1; |
5663 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
5664 | } else { | |
f52dafc1 | 5665 | netdev_dbg(dev, "%s: link timer off\n", pci_name(pci_dev)); |
1da177e4 LT |
5666 | np->need_linktimer = 0; |
5667 | } | |
5668 | ||
3b446c3e AA |
5669 | /* Limit the number of tx's outstanding for hw bug */ |
5670 | if (id->driver_data & DEV_NEED_TX_LIMIT) { | |
5671 | np->tx_limit = 1; | |
5c659322 | 5672 | if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) && |
3b446c3e AA |
5673 | pci_dev->revision >= 0xA2) |
5674 | np->tx_limit = 0; | |
5675 | } | |
5676 | ||
7e680c22 AA |
5677 | /* clear phy state and temporarily halt phy interrupts */ |
5678 | writel(0, base + NvRegMIIMask); | |
5679 | phystate = readl(base + NvRegAdapterControl); | |
5680 | if (phystate & NVREG_ADAPTCTL_RUNNING) { | |
5681 | phystate_orig = 1; | |
5682 | phystate &= ~NVREG_ADAPTCTL_RUNNING; | |
5683 | writel(phystate, base + NvRegAdapterControl); | |
5684 | } | |
eb798428 | 5685 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
7e680c22 AA |
5686 | |
5687 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { | |
7e680c22 | 5688 | /* management unit running on the mac? */ |
cac1c52c AA |
5689 | if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) && |
5690 | (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) && | |
5691 | nv_mgmt_acquire_sema(dev) && | |
5692 | nv_mgmt_get_version(dev)) { | |
5693 | np->mac_in_use = 1; | |
78aea4fc | 5694 | if (np->mgmt_version > 0) |
cac1c52c | 5695 | np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; |
f52dafc1 JP |
5696 | netdev_dbg(dev, "%s: mgmt unit is running. mac in use %x\n", |
5697 | pci_name(pci_dev), np->mac_in_use); | |
cac1c52c AA |
5698 | /* management unit setup the phy already? */ |
5699 | if (np->mac_in_use && | |
5700 | ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == | |
5701 | NVREG_XMITCTL_SYNC_PHY_INIT)) { | |
5702 | /* phy is inited by mgmt unit */ | |
5703 | phyinitialized = 1; | |
f52dafc1 JP |
5704 | netdev_dbg(dev, "%s: Phy already initialized by mgmt unit\n", |
5705 | pci_name(pci_dev)); | |
cac1c52c AA |
5706 | } else { |
5707 | /* we need to init the phy */ | |
7e680c22 AA |
5708 | } |
5709 | } | |
5710 | } | |
5711 | ||
1da177e4 | 5712 | /* find a suitable phy */ |
7a33e45a | 5713 | for (i = 1; i <= 32; i++) { |
1da177e4 | 5714 | int id1, id2; |
7a33e45a | 5715 | int phyaddr = i & 0x1F; |
1da177e4 LT |
5716 | |
5717 | spin_lock_irq(&np->lock); | |
7a33e45a | 5718 | id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
1da177e4 LT |
5719 | spin_unlock_irq(&np->lock); |
5720 | if (id1 < 0 || id1 == 0xffff) | |
5721 | continue; | |
5722 | spin_lock_irq(&np->lock); | |
7a33e45a | 5723 | id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
1da177e4 LT |
5724 | spin_unlock_irq(&np->lock); |
5725 | if (id2 < 0 || id2 == 0xffff) | |
5726 | continue; | |
5727 | ||
edf7e5ec | 5728 | np->phy_model = id2 & PHYID2_MODEL_MASK; |
1da177e4 LT |
5729 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
5730 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; | |
6b80858d JP |
5731 | netdev_dbg(dev, "%s: %s: Found PHY %04x:%04x at address %d\n", |
5732 | pci_name(pci_dev), __func__, id1, id2, phyaddr); | |
7a33e45a | 5733 | np->phyaddr = phyaddr; |
1da177e4 | 5734 | np->phy_oui = id1 | id2; |
9f3f7910 AA |
5735 | |
5736 | /* Realtek hardcoded phy id1 to all zero's on certain phys */ | |
5737 | if (np->phy_oui == PHY_OUI_REALTEK2) | |
5738 | np->phy_oui = PHY_OUI_REALTEK; | |
5739 | /* Setup phy revision for Realtek */ | |
5740 | if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211) | |
5741 | np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; | |
5742 | ||
1da177e4 LT |
5743 | break; |
5744 | } | |
7a33e45a | 5745 | if (i == 33) { |
3f88ce49 JG |
5746 | dev_printk(KERN_INFO, &pci_dev->dev, |
5747 | "open: Could not find a valid PHY.\n"); | |
eafa59f6 | 5748 | goto out_error; |
1da177e4 | 5749 | } |
f3b197ac | 5750 | |
7e680c22 AA |
5751 | if (!phyinitialized) { |
5752 | /* reset it */ | |
5753 | phy_init(dev); | |
f35723ec AA |
5754 | } else { |
5755 | /* see if it is a gigabit phy */ | |
5756 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
78aea4fc | 5757 | if (mii_status & PHY_GIGABIT) |
f35723ec | 5758 | np->gigabit = PHY_GIGABIT; |
7e680c22 | 5759 | } |
1da177e4 LT |
5760 | |
5761 | /* set default link speed settings */ | |
5762 | np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
5763 | np->duplex = 0; | |
5764 | np->autoneg = 1; | |
5765 | ||
5766 | err = register_netdev(dev); | |
5767 | if (err) { | |
3f88ce49 JG |
5768 | dev_printk(KERN_INFO, &pci_dev->dev, |
5769 | "unable to register netdev: %d\n", err); | |
eafa59f6 | 5770 | goto out_error; |
1da177e4 | 5771 | } |
3f88ce49 JG |
5772 | |
5773 | dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, " | |
5774 | "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", | |
5775 | dev->name, | |
5776 | np->phy_oui, | |
5777 | np->phyaddr, | |
5778 | dev->dev_addr[0], | |
5779 | dev->dev_addr[1], | |
5780 | dev->dev_addr[2], | |
5781 | dev->dev_addr[3], | |
5782 | dev->dev_addr[4], | |
5783 | dev->dev_addr[5]); | |
5784 | ||
5785 | dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", | |
78aea4fc SJ |
5786 | dev->features & NETIF_F_HIGHDMA ? "highdma " : "", |
5787 | dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? | |
5788 | "csum " : "", | |
5789 | dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ? | |
5790 | "vlan " : "", | |
5791 | id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", | |
5792 | id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "", | |
5793 | id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "", | |
5794 | np->gigabit == PHY_GIGABIT ? "gbit " : "", | |
5795 | np->need_linktimer ? "lnktim " : "", | |
5796 | np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", | |
5797 | np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", | |
5798 | np->desc_ver); | |
1da177e4 LT |
5799 | |
5800 | return 0; | |
5801 | ||
eafa59f6 | 5802 | out_error: |
7e680c22 AA |
5803 | if (phystate_orig) |
5804 | writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); | |
1da177e4 | 5805 | pci_set_drvdata(pci_dev, NULL); |
eafa59f6 AA |
5806 | out_freering: |
5807 | free_rings(dev); | |
1da177e4 LT |
5808 | out_unmap: |
5809 | iounmap(get_hwbase(dev)); | |
5810 | out_relreg: | |
5811 | pci_release_regions(pci_dev); | |
5812 | out_disable: | |
5813 | pci_disable_device(pci_dev); | |
5814 | out_free: | |
5815 | free_netdev(dev); | |
5816 | out: | |
5817 | return err; | |
5818 | } | |
5819 | ||
9f3f7910 AA |
5820 | static void nv_restore_phy(struct net_device *dev) |
5821 | { | |
5822 | struct fe_priv *np = netdev_priv(dev); | |
5823 | u16 phy_reserved, mii_control; | |
5824 | ||
5825 | if (np->phy_oui == PHY_OUI_REALTEK && | |
5826 | np->phy_model == PHY_MODEL_REALTEK_8201 && | |
5827 | phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
5828 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); | |
5829 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | |
5830 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
5831 | phy_reserved |= PHY_REALTEK_INIT8; | |
5832 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); | |
5833 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); | |
5834 | ||
5835 | /* restart auto negotiation */ | |
5836 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
5837 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); | |
5838 | mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); | |
5839 | } | |
5840 | } | |
5841 | ||
f55c21fd | 5842 | static void nv_restore_mac_addr(struct pci_dev *pci_dev) |
1da177e4 LT |
5843 | { |
5844 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
f1489653 AA |
5845 | struct fe_priv *np = netdev_priv(dev); |
5846 | u8 __iomem *base = get_hwbase(dev); | |
1da177e4 | 5847 | |
f1489653 AA |
5848 | /* special op: write back the misordered MAC address - otherwise |
5849 | * the next nv_probe would see a wrong address. | |
5850 | */ | |
5851 | writel(np->orig_mac[0], base + NvRegMacAddrA); | |
5852 | writel(np->orig_mac[1], base + NvRegMacAddrB); | |