Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. | |
3 | * | |
4 | * Note: This driver is a cleanroom reimplementation based on reverse | |
5 | * engineered documentation written by Carl-Daniel Hailfinger | |
87046e50 | 6 | * and Andrew de Quincey. |
1da177e4 LT |
7 | * |
8 | * NVIDIA, nForce and other NVIDIA marks are trademarks or registered | |
9 | * trademarks of NVIDIA Corporation in the United States and other | |
10 | * countries. | |
11 | * | |
1836098f | 12 | * Copyright (C) 2003,4,5 Manfred Spraul |
1da177e4 LT |
13 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
14 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane | |
15 | * IRQ rate fixes, bigendian fixes, cleanups, verification) | |
f1405d32 | 16 | * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
31 | * | |
1da177e4 LT |
32 | * Known bugs: |
33 | * We suspect that on some hardware no TX done interrupts are generated. | |
34 | * This means recovery from netif_stop_queue only happens if the hw timer | |
35 | * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) | |
36 | * and the timer is active in the IRQMask, or if a rx packet arrives by chance. | |
37 | * If your hardware reliably generates tx done interrupts, then you can remove | |
38 | * DEV_NEED_TIMERIRQ from the driver_data flags. | |
39 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | |
40 | * superfluous timer interrupts from the nic. | |
41 | */ | |
3e1a3ce2 | 42 | #define FORCEDETH_VERSION "0.64" |
1da177e4 LT |
43 | #define DRV_NAME "forcedeth" |
44 | ||
45 | #include <linux/module.h> | |
46 | #include <linux/types.h> | |
47 | #include <linux/pci.h> | |
48 | #include <linux/interrupt.h> | |
49 | #include <linux/netdevice.h> | |
50 | #include <linux/etherdevice.h> | |
51 | #include <linux/delay.h> | |
d43c36dc | 52 | #include <linux/sched.h> |
1da177e4 LT |
53 | #include <linux/spinlock.h> |
54 | #include <linux/ethtool.h> | |
55 | #include <linux/timer.h> | |
56 | #include <linux/skbuff.h> | |
57 | #include <linux/mii.h> | |
58 | #include <linux/random.h> | |
59 | #include <linux/init.h> | |
22c6d143 | 60 | #include <linux/if_vlan.h> |
910638ae | 61 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 62 | #include <linux/slab.h> |
1da177e4 LT |
63 | |
64 | #include <asm/irq.h> | |
65 | #include <asm/io.h> | |
66 | #include <asm/uaccess.h> | |
67 | #include <asm/system.h> | |
68 | ||
69 | #if 0 | |
70 | #define dprintk printk | |
71 | #else | |
72 | #define dprintk(x...) do { } while (0) | |
73 | #endif | |
74 | ||
bea3348e SH |
75 | #define TX_WORK_PER_LOOP 64 |
76 | #define RX_WORK_PER_LOOP 64 | |
1da177e4 LT |
77 | |
78 | /* | |
79 | * Hardware access: | |
80 | */ | |
81 | ||
3c2e1c11 AA |
82 | #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */ |
83 | #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */ | |
84 | #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */ | |
85 | #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */ | |
86 | #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */ | |
87 | #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */ | |
88 | #define DEV_HAS_MSI 0x0000040 /* device supports MSI */ | |
89 | #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */ | |
90 | #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */ | |
91 | #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */ | |
7b5e078c MD |
92 | #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */ |
93 | #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */ | |
94 | #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */ | |
95 | #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */ | |
3c2e1c11 AA |
96 | #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */ |
97 | #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */ | |
98 | #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */ | |
99 | #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */ | |
100 | #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */ | |
101 | #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */ | |
102 | #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */ | |
103 | #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */ | |
104 | #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */ | |
105 | #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */ | |
106 | #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */ | |
107 | #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */ | |
108 | #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */ | |
1da177e4 LT |
109 | |
110 | enum { | |
111 | NvRegIrqStatus = 0x000, | |
112 | #define NVREG_IRQSTAT_MIIEVENT 0x040 | |
daa91a9d | 113 | #define NVREG_IRQSTAT_MASK 0x83ff |
1da177e4 LT |
114 | NvRegIrqMask = 0x004, |
115 | #define NVREG_IRQ_RX_ERROR 0x0001 | |
116 | #define NVREG_IRQ_RX 0x0002 | |
117 | #define NVREG_IRQ_RX_NOBUF 0x0004 | |
118 | #define NVREG_IRQ_TX_ERR 0x0008 | |
c2dba06d | 119 | #define NVREG_IRQ_TX_OK 0x0010 |
1da177e4 LT |
120 | #define NVREG_IRQ_TIMER 0x0020 |
121 | #define NVREG_IRQ_LINK 0x0040 | |
d33a73c8 AA |
122 | #define NVREG_IRQ_RX_FORCED 0x0080 |
123 | #define NVREG_IRQ_TX_FORCED 0x0100 | |
daa91a9d | 124 | #define NVREG_IRQ_RECOVER_ERROR 0x8200 |
a971c324 | 125 | #define NVREG_IRQMASK_THROUGHPUT 0x00df |
096a458c | 126 | #define NVREG_IRQMASK_CPU 0x0060 |
d33a73c8 AA |
127 | #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
128 | #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) | |
c5cf9101 | 129 | #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) |
c2dba06d | 130 | |
1da177e4 LT |
131 | NvRegUnknownSetupReg6 = 0x008, |
132 | #define NVREG_UNKSETUP6_VAL 3 | |
133 | ||
134 | /* | |
135 | * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic | |
136 | * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms | |
137 | */ | |
138 | NvRegPollingInterval = 0x00c, | |
6cef67a0 | 139 | #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */ |
a971c324 | 140 | #define NVREG_POLL_DEFAULT_CPU 13 |
d33a73c8 AA |
141 | NvRegMSIMap0 = 0x020, |
142 | NvRegMSIMap1 = 0x024, | |
143 | NvRegMSIIrqMask = 0x030, | |
144 | #define NVREG_MSI_VECTOR_0_ENABLED 0x01 | |
1da177e4 | 145 | NvRegMisc1 = 0x080, |
eb91f61b | 146 | #define NVREG_MISC1_PAUSE_TX 0x01 |
1da177e4 LT |
147 | #define NVREG_MISC1_HD 0x02 |
148 | #define NVREG_MISC1_FORCE 0x3b0f3c | |
149 | ||
0a62677b | 150 | NvRegMacReset = 0x34, |
86a0f043 | 151 | #define NVREG_MAC_RESET_ASSERT 0x0F3 |
1da177e4 LT |
152 | NvRegTransmitterControl = 0x084, |
153 | #define NVREG_XMITCTL_START 0x01 | |
7e680c22 AA |
154 | #define NVREG_XMITCTL_MGMT_ST 0x40000000 |
155 | #define NVREG_XMITCTL_SYNC_MASK 0x000f0000 | |
156 | #define NVREG_XMITCTL_SYNC_NOT_READY 0x0 | |
157 | #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 | |
158 | #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 | |
159 | #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 | |
160 | #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 | |
161 | #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 | |
162 | #define NVREG_XMITCTL_HOST_LOADED 0x00004000 | |
f35723ec | 163 | #define NVREG_XMITCTL_TX_PATH_EN 0x01000000 |
cac1c52c AA |
164 | #define NVREG_XMITCTL_DATA_START 0x00100000 |
165 | #define NVREG_XMITCTL_DATA_READY 0x00010000 | |
166 | #define NVREG_XMITCTL_DATA_ERROR 0x00020000 | |
1da177e4 LT |
167 | NvRegTransmitterStatus = 0x088, |
168 | #define NVREG_XMITSTAT_BUSY 0x01 | |
169 | ||
170 | NvRegPacketFilterFlags = 0x8c, | |
eb91f61b AA |
171 | #define NVREG_PFF_PAUSE_RX 0x08 |
172 | #define NVREG_PFF_ALWAYS 0x7F0000 | |
1da177e4 LT |
173 | #define NVREG_PFF_PROMISC 0x80 |
174 | #define NVREG_PFF_MYADDR 0x20 | |
9589c77a | 175 | #define NVREG_PFF_LOOPBACK 0x10 |
1da177e4 LT |
176 | |
177 | NvRegOffloadConfig = 0x90, | |
178 | #define NVREG_OFFLOAD_HOMEPHY 0x601 | |
179 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE | |
180 | NvRegReceiverControl = 0x094, | |
181 | #define NVREG_RCVCTL_START 0x01 | |
f35723ec | 182 | #define NVREG_RCVCTL_RX_PATH_EN 0x01000000 |
1da177e4 LT |
183 | NvRegReceiverStatus = 0x98, |
184 | #define NVREG_RCVSTAT_BUSY 0x01 | |
185 | ||
a433686c AA |
186 | NvRegSlotTime = 0x9c, |
187 | #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 | |
188 | #define NVREG_SLOTTIME_10_100_FULL 0x00007f00 | |
78aea4fc | 189 | #define NVREG_SLOTTIME_1000_FULL 0x0003ff00 |
a433686c | 190 | #define NVREG_SLOTTIME_HALF 0x0000ff00 |
78aea4fc | 191 | #define NVREG_SLOTTIME_DEFAULT 0x00007f00 |
a433686c | 192 | #define NVREG_SLOTTIME_MASK 0x000000ff |
1da177e4 | 193 | |
9744e218 | 194 | NvRegTxDeferral = 0xA0, |
fd9b558c AA |
195 | #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
196 | #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f | |
197 | #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f | |
198 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f | |
199 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f | |
200 | #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000 | |
9744e218 AA |
201 | NvRegRxDeferral = 0xA4, |
202 | #define NVREG_RX_DEFERRAL_DEFAULT 0x16 | |
1da177e4 LT |
203 | NvRegMacAddrA = 0xA8, |
204 | NvRegMacAddrB = 0xAC, | |
205 | NvRegMulticastAddrA = 0xB0, | |
206 | #define NVREG_MCASTADDRA_FORCE 0x01 | |
207 | NvRegMulticastAddrB = 0xB4, | |
208 | NvRegMulticastMaskA = 0xB8, | |
bb9a4fd1 | 209 | #define NVREG_MCASTMASKA_NONE 0xffffffff |
1da177e4 | 210 | NvRegMulticastMaskB = 0xBC, |
bb9a4fd1 | 211 | #define NVREG_MCASTMASKB_NONE 0xffff |
1da177e4 LT |
212 | |
213 | NvRegPhyInterface = 0xC0, | |
214 | #define PHY_RGMII 0x10000000 | |
a433686c AA |
215 | NvRegBackOffControl = 0xC4, |
216 | #define NVREG_BKOFFCTRL_DEFAULT 0x70000000 | |
217 | #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff | |
218 | #define NVREG_BKOFFCTRL_SELECT 24 | |
219 | #define NVREG_BKOFFCTRL_GEAR 12 | |
1da177e4 LT |
220 | |
221 | NvRegTxRingPhysAddr = 0x100, | |
222 | NvRegRxRingPhysAddr = 0x104, | |
223 | NvRegRingSizes = 0x108, | |
224 | #define NVREG_RINGSZ_TXSHIFT 0 | |
225 | #define NVREG_RINGSZ_RXSHIFT 16 | |
5070d340 AA |
226 | NvRegTransmitPoll = 0x10c, |
227 | #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 | |
1da177e4 LT |
228 | NvRegLinkSpeed = 0x110, |
229 | #define NVREG_LINKSPEED_FORCE 0x10000 | |
230 | #define NVREG_LINKSPEED_10 1000 | |
231 | #define NVREG_LINKSPEED_100 100 | |
232 | #define NVREG_LINKSPEED_1000 50 | |
233 | #define NVREG_LINKSPEED_MASK (0xFFF) | |
234 | NvRegUnknownSetupReg5 = 0x130, | |
235 | #define NVREG_UNKSETUP5_BIT31 (1<<31) | |
95d161cb AA |
236 | NvRegTxWatermark = 0x13c, |
237 | #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 | |
238 | #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 | |
239 | #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 | |
1da177e4 LT |
240 | NvRegTxRxControl = 0x144, |
241 | #define NVREG_TXRXCTL_KICK 0x0001 | |
242 | #define NVREG_TXRXCTL_BIT1 0x0002 | |
243 | #define NVREG_TXRXCTL_BIT2 0x0004 | |
244 | #define NVREG_TXRXCTL_IDLE 0x0008 | |
245 | #define NVREG_TXRXCTL_RESET 0x0010 | |
246 | #define NVREG_TXRXCTL_RXCHECK 0x0400 | |
8a4ae7f2 | 247 | #define NVREG_TXRXCTL_DESC_1 0 |
d2f78412 AA |
248 | #define NVREG_TXRXCTL_DESC_2 0x002100 |
249 | #define NVREG_TXRXCTL_DESC_3 0xc02200 | |
ee407b02 AA |
250 | #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
251 | #define NVREG_TXRXCTL_VLANINS 0x00080 | |
0832b25a AA |
252 | NvRegTxRingPhysAddrHigh = 0x148, |
253 | NvRegRxRingPhysAddrHigh = 0x14C, | |
eb91f61b | 254 | NvRegTxPauseFrame = 0x170, |
5289b4c4 AA |
255 | #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080 |
256 | #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 | |
257 | #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 | |
258 | #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 | |
9a33e883 AA |
259 | NvRegTxPauseFrameLimit = 0x174, |
260 | #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000 | |
1da177e4 LT |
261 | NvRegMIIStatus = 0x180, |
262 | #define NVREG_MIISTAT_ERROR 0x0001 | |
263 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | |
eb798428 AA |
264 | #define NVREG_MIISTAT_MASK_RW 0x0007 |
265 | #define NVREG_MIISTAT_MASK_ALL 0x000f | |
7e680c22 AA |
266 | NvRegMIIMask = 0x184, |
267 | #define NVREG_MII_LINKCHANGE 0x0008 | |
1da177e4 LT |
268 | |
269 | NvRegAdapterControl = 0x188, | |
270 | #define NVREG_ADAPTCTL_START 0x02 | |
271 | #define NVREG_ADAPTCTL_LINKUP 0x04 | |
272 | #define NVREG_ADAPTCTL_PHYVALID 0x40000 | |
273 | #define NVREG_ADAPTCTL_RUNNING 0x100000 | |
274 | #define NVREG_ADAPTCTL_PHYSHIFT 24 | |
275 | NvRegMIISpeed = 0x18c, | |
276 | #define NVREG_MIISPEED_BIT8 (1<<8) | |
277 | #define NVREG_MIIDELAY 5 | |
278 | NvRegMIIControl = 0x190, | |
279 | #define NVREG_MIICTL_INUSE 0x08000 | |
280 | #define NVREG_MIICTL_WRITE 0x00400 | |
281 | #define NVREG_MIICTL_ADDRSHIFT 5 | |
282 | NvRegMIIData = 0x194, | |
9c662435 AA |
283 | NvRegTxUnicast = 0x1a0, |
284 | NvRegTxMulticast = 0x1a4, | |
285 | NvRegTxBroadcast = 0x1a8, | |
1da177e4 LT |
286 | NvRegWakeUpFlags = 0x200, |
287 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 | |
288 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 | |
289 | #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 | |
290 | #define NVREG_WAKEUPFLAGS_D3SHIFT 12 | |
291 | #define NVREG_WAKEUPFLAGS_D2SHIFT 8 | |
292 | #define NVREG_WAKEUPFLAGS_D1SHIFT 4 | |
293 | #define NVREG_WAKEUPFLAGS_D0SHIFT 0 | |
294 | #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 | |
295 | #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 | |
296 | #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 | |
297 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 | |
298 | ||
cac1c52c | 299 | NvRegMgmtUnitGetVersion = 0x204, |
78aea4fc | 300 | #define NVREG_MGMTUNITGETVERSION 0x01 |
cac1c52c AA |
301 | NvRegMgmtUnitVersion = 0x208, |
302 | #define NVREG_MGMTUNITVERSION 0x08 | |
1da177e4 LT |
303 | NvRegPowerCap = 0x268, |
304 | #define NVREG_POWERCAP_D3SUPP (1<<30) | |
305 | #define NVREG_POWERCAP_D2SUPP (1<<26) | |
306 | #define NVREG_POWERCAP_D1SUPP (1<<25) | |
307 | NvRegPowerState = 0x26c, | |
308 | #define NVREG_POWERSTATE_POWEREDUP 0x8000 | |
309 | #define NVREG_POWERSTATE_VALID 0x0100 | |
310 | #define NVREG_POWERSTATE_MASK 0x0003 | |
311 | #define NVREG_POWERSTATE_D0 0x0000 | |
312 | #define NVREG_POWERSTATE_D1 0x0001 | |
313 | #define NVREG_POWERSTATE_D2 0x0002 | |
314 | #define NVREG_POWERSTATE_D3 0x0003 | |
cac1c52c AA |
315 | NvRegMgmtUnitControl = 0x278, |
316 | #define NVREG_MGMTUNITCONTROL_INUSE 0x20000 | |
52da3578 AA |
317 | NvRegTxCnt = 0x280, |
318 | NvRegTxZeroReXmt = 0x284, | |
319 | NvRegTxOneReXmt = 0x288, | |
320 | NvRegTxManyReXmt = 0x28c, | |
321 | NvRegTxLateCol = 0x290, | |
322 | NvRegTxUnderflow = 0x294, | |
323 | NvRegTxLossCarrier = 0x298, | |
324 | NvRegTxExcessDef = 0x29c, | |
325 | NvRegTxRetryErr = 0x2a0, | |
326 | NvRegRxFrameErr = 0x2a4, | |
327 | NvRegRxExtraByte = 0x2a8, | |
328 | NvRegRxLateCol = 0x2ac, | |
329 | NvRegRxRunt = 0x2b0, | |
330 | NvRegRxFrameTooLong = 0x2b4, | |
331 | NvRegRxOverflow = 0x2b8, | |
332 | NvRegRxFCSErr = 0x2bc, | |
333 | NvRegRxFrameAlignErr = 0x2c0, | |
334 | NvRegRxLenErr = 0x2c4, | |
335 | NvRegRxUnicast = 0x2c8, | |
336 | NvRegRxMulticast = 0x2cc, | |
337 | NvRegRxBroadcast = 0x2d0, | |
338 | NvRegTxDef = 0x2d4, | |
339 | NvRegTxFrame = 0x2d8, | |
340 | NvRegRxCnt = 0x2dc, | |
341 | NvRegTxPause = 0x2e0, | |
342 | NvRegRxPause = 0x2e4, | |
343 | NvRegRxDropFrame = 0x2e8, | |
ee407b02 AA |
344 | NvRegVlanControl = 0x300, |
345 | #define NVREG_VLANCONTROL_ENABLE 0x2000 | |
d33a73c8 AA |
346 | NvRegMSIXMap0 = 0x3e0, |
347 | NvRegMSIXMap1 = 0x3e4, | |
348 | NvRegMSIXIrqStatus = 0x3f0, | |
86a0f043 AA |
349 | |
350 | NvRegPowerState2 = 0x600, | |
1545e205 | 351 | #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15 |
86a0f043 | 352 | #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 |
22ae03a1 | 353 | #define NVREG_POWERSTATE2_PHY_RESET 0x0004 |
88d7d8b0 | 354 | #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00 |
1da177e4 LT |
355 | }; |
356 | ||
357 | /* Big endian: should work, but is untested */ | |
358 | struct ring_desc { | |
a8bed49e SH |
359 | __le32 buf; |
360 | __le32 flaglen; | |
1da177e4 LT |
361 | }; |
362 | ||
ee73362c | 363 | struct ring_desc_ex { |
a8bed49e SH |
364 | __le32 bufhigh; |
365 | __le32 buflow; | |
366 | __le32 txvlan; | |
367 | __le32 flaglen; | |
ee73362c MS |
368 | }; |
369 | ||
f82a9352 | 370 | union ring_type { |
78aea4fc SJ |
371 | struct ring_desc *orig; |
372 | struct ring_desc_ex *ex; | |
f82a9352 | 373 | }; |
ee73362c | 374 | |
1da177e4 LT |
375 | #define FLAG_MASK_V1 0xffff0000 |
376 | #define FLAG_MASK_V2 0xffffc000 | |
377 | #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) | |
378 | #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) | |
379 | ||
380 | #define NV_TX_LASTPACKET (1<<16) | |
381 | #define NV_TX_RETRYERROR (1<<19) | |
a433686c | 382 | #define NV_TX_RETRYCOUNT_MASK (0xF<<20) |
c2dba06d | 383 | #define NV_TX_FORCED_INTERRUPT (1<<24) |
1da177e4 LT |
384 | #define NV_TX_DEFERRED (1<<26) |
385 | #define NV_TX_CARRIERLOST (1<<27) | |
386 | #define NV_TX_LATECOLLISION (1<<28) | |
387 | #define NV_TX_UNDERFLOW (1<<29) | |
388 | #define NV_TX_ERROR (1<<30) | |
389 | #define NV_TX_VALID (1<<31) | |
390 | ||
391 | #define NV_TX2_LASTPACKET (1<<29) | |
392 | #define NV_TX2_RETRYERROR (1<<18) | |
a433686c | 393 | #define NV_TX2_RETRYCOUNT_MASK (0xF<<19) |
c2dba06d | 394 | #define NV_TX2_FORCED_INTERRUPT (1<<30) |
1da177e4 LT |
395 | #define NV_TX2_DEFERRED (1<<25) |
396 | #define NV_TX2_CARRIERLOST (1<<26) | |
397 | #define NV_TX2_LATECOLLISION (1<<27) | |
398 | #define NV_TX2_UNDERFLOW (1<<28) | |
399 | /* error and valid are the same for both */ | |
400 | #define NV_TX2_ERROR (1<<30) | |
401 | #define NV_TX2_VALID (1<<31) | |
ac9c1897 AA |
402 | #define NV_TX2_TSO (1<<28) |
403 | #define NV_TX2_TSO_SHIFT 14 | |
fa45459e AA |
404 | #define NV_TX2_TSO_MAX_SHIFT 14 |
405 | #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) | |
8a4ae7f2 MS |
406 | #define NV_TX2_CHECKSUM_L3 (1<<27) |
407 | #define NV_TX2_CHECKSUM_L4 (1<<26) | |
1da177e4 | 408 | |
ee407b02 AA |
409 | #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
410 | ||
1da177e4 LT |
411 | #define NV_RX_DESCRIPTORVALID (1<<16) |
412 | #define NV_RX_MISSEDFRAME (1<<17) | |
413 | #define NV_RX_SUBSTRACT1 (1<<18) | |
414 | #define NV_RX_ERROR1 (1<<23) | |
415 | #define NV_RX_ERROR2 (1<<24) | |
416 | #define NV_RX_ERROR3 (1<<25) | |
417 | #define NV_RX_ERROR4 (1<<26) | |
418 | #define NV_RX_CRCERR (1<<27) | |
419 | #define NV_RX_OVERFLOW (1<<28) | |
420 | #define NV_RX_FRAMINGERR (1<<29) | |
421 | #define NV_RX_ERROR (1<<30) | |
422 | #define NV_RX_AVAIL (1<<31) | |
1ef6841b | 423 | #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR) |
1da177e4 LT |
424 | |
425 | #define NV_RX2_CHECKSUMMASK (0x1C000000) | |
bfaffe8f AA |
426 | #define NV_RX2_CHECKSUM_IP (0x10000000) |
427 | #define NV_RX2_CHECKSUM_IP_TCP (0x14000000) | |
428 | #define NV_RX2_CHECKSUM_IP_UDP (0x18000000) | |
1da177e4 LT |
429 | #define NV_RX2_DESCRIPTORVALID (1<<29) |
430 | #define NV_RX2_SUBSTRACT1 (1<<25) | |
431 | #define NV_RX2_ERROR1 (1<<18) | |
432 | #define NV_RX2_ERROR2 (1<<19) | |
433 | #define NV_RX2_ERROR3 (1<<20) | |
434 | #define NV_RX2_ERROR4 (1<<21) | |
435 | #define NV_RX2_CRCERR (1<<22) | |
436 | #define NV_RX2_OVERFLOW (1<<23) | |
437 | #define NV_RX2_FRAMINGERR (1<<24) | |
438 | /* error and avail are the same for both */ | |
439 | #define NV_RX2_ERROR (1<<30) | |
440 | #define NV_RX2_AVAIL (1<<31) | |
1ef6841b | 441 | #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR) |
1da177e4 | 442 | |
ee407b02 AA |
443 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
444 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | |
445 | ||
1da177e4 | 446 | /* Miscelaneous hardware related defines: */ |
78aea4fc SJ |
447 | #define NV_PCI_REGSZ_VER1 0x270 |
448 | #define NV_PCI_REGSZ_VER2 0x2d4 | |
449 | #define NV_PCI_REGSZ_VER3 0x604 | |
450 | #define NV_PCI_REGSZ_MAX 0x604 | |
1da177e4 LT |
451 | |
452 | /* various timeout delays: all in usec */ | |
453 | #define NV_TXRX_RESET_DELAY 4 | |
454 | #define NV_TXSTOP_DELAY1 10 | |
455 | #define NV_TXSTOP_DELAY1MAX 500000 | |
456 | #define NV_TXSTOP_DELAY2 100 | |
457 | #define NV_RXSTOP_DELAY1 10 | |
458 | #define NV_RXSTOP_DELAY1MAX 500000 | |
459 | #define NV_RXSTOP_DELAY2 100 | |
460 | #define NV_SETUP5_DELAY 5 | |
461 | #define NV_SETUP5_DELAYMAX 50000 | |
462 | #define NV_POWERUP_DELAY 5 | |
463 | #define NV_POWERUP_DELAYMAX 5000 | |
464 | #define NV_MIIBUSY_DELAY 50 | |
465 | #define NV_MIIPHY_DELAY 10 | |
466 | #define NV_MIIPHY_DELAYMAX 10000 | |
86a0f043 | 467 | #define NV_MAC_RESET_DELAY 64 |
1da177e4 LT |
468 | |
469 | #define NV_WAKEUPPATTERNS 5 | |
470 | #define NV_WAKEUPMASKENTRIES 4 | |
471 | ||
472 | /* General driver defaults */ | |
473 | #define NV_WATCHDOG_TIMEO (5*HZ) | |
474 | ||
6cef67a0 | 475 | #define RX_RING_DEFAULT 512 |
eafa59f6 AA |
476 | #define TX_RING_DEFAULT 256 |
477 | #define RX_RING_MIN 128 | |
478 | #define TX_RING_MIN 64 | |
479 | #define RING_MAX_DESC_VER_1 1024 | |
480 | #define RING_MAX_DESC_VER_2_3 16384 | |
1da177e4 LT |
481 | |
482 | /* rx/tx mac addr + type + vlan + align + slack*/ | |
d81c0983 MS |
483 | #define NV_RX_HEADERS (64) |
484 | /* even more slack. */ | |
485 | #define NV_RX_ALLOC_PAD (64) | |
486 | ||
487 | /* maximum mtu size */ | |
488 | #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ | |
489 | #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ | |
1da177e4 LT |
490 | |
491 | #define OOM_REFILL (1+HZ/20) | |
492 | #define POLL_WAIT (1+HZ/100) | |
493 | #define LINK_TIMEOUT (3*HZ) | |
52da3578 | 494 | #define STATS_INTERVAL (10*HZ) |
1da177e4 | 495 | |
f3b197ac | 496 | /* |
1da177e4 | 497 | * desc_ver values: |
8a4ae7f2 MS |
498 | * The nic supports three different descriptor types: |
499 | * - DESC_VER_1: Original | |
500 | * - DESC_VER_2: support for jumbo frames. | |
501 | * - DESC_VER_3: 64-bit format. | |
1da177e4 | 502 | */ |
8a4ae7f2 MS |
503 | #define DESC_VER_1 1 |
504 | #define DESC_VER_2 2 | |
505 | #define DESC_VER_3 3 | |
1da177e4 LT |
506 | |
507 | /* PHY defines */ | |
9f3f7910 AA |
508 | #define PHY_OUI_MARVELL 0x5043 |
509 | #define PHY_OUI_CICADA 0x03f1 | |
510 | #define PHY_OUI_VITESSE 0x01c1 | |
511 | #define PHY_OUI_REALTEK 0x0732 | |
512 | #define PHY_OUI_REALTEK2 0x0020 | |
1da177e4 LT |
513 | #define PHYID1_OUI_MASK 0x03ff |
514 | #define PHYID1_OUI_SHFT 6 | |
515 | #define PHYID2_OUI_MASK 0xfc00 | |
516 | #define PHYID2_OUI_SHFT 10 | |
edf7e5ec | 517 | #define PHYID2_MODEL_MASK 0x03f0 |
9f3f7910 AA |
518 | #define PHY_MODEL_REALTEK_8211 0x0110 |
519 | #define PHY_REV_MASK 0x0001 | |
520 | #define PHY_REV_REALTEK_8211B 0x0000 | |
521 | #define PHY_REV_REALTEK_8211C 0x0001 | |
522 | #define PHY_MODEL_REALTEK_8201 0x0200 | |
523 | #define PHY_MODEL_MARVELL_E3016 0x0220 | |
edf7e5ec | 524 | #define PHY_MARVELL_E3016_INITMASK 0x0300 |
14a67f3c AA |
525 | #define PHY_CICADA_INIT1 0x0f000 |
526 | #define PHY_CICADA_INIT2 0x0e00 | |
527 | #define PHY_CICADA_INIT3 0x01000 | |
528 | #define PHY_CICADA_INIT4 0x0200 | |
529 | #define PHY_CICADA_INIT5 0x0004 | |
530 | #define PHY_CICADA_INIT6 0x02000 | |
d215d8a2 AA |
531 | #define PHY_VITESSE_INIT_REG1 0x1f |
532 | #define PHY_VITESSE_INIT_REG2 0x10 | |
533 | #define PHY_VITESSE_INIT_REG3 0x11 | |
534 | #define PHY_VITESSE_INIT_REG4 0x12 | |
535 | #define PHY_VITESSE_INIT_MSK1 0xc | |
536 | #define PHY_VITESSE_INIT_MSK2 0x0180 | |
537 | #define PHY_VITESSE_INIT1 0x52b5 | |
538 | #define PHY_VITESSE_INIT2 0xaf8a | |
539 | #define PHY_VITESSE_INIT3 0x8 | |
540 | #define PHY_VITESSE_INIT4 0x8f8a | |
541 | #define PHY_VITESSE_INIT5 0xaf86 | |
542 | #define PHY_VITESSE_INIT6 0x8f86 | |
543 | #define PHY_VITESSE_INIT7 0xaf82 | |
544 | #define PHY_VITESSE_INIT8 0x0100 | |
545 | #define PHY_VITESSE_INIT9 0x8f82 | |
546 | #define PHY_VITESSE_INIT10 0x0 | |
c5e3ae88 AA |
547 | #define PHY_REALTEK_INIT_REG1 0x1f |
548 | #define PHY_REALTEK_INIT_REG2 0x19 | |
549 | #define PHY_REALTEK_INIT_REG3 0x13 | |
9f3f7910 AA |
550 | #define PHY_REALTEK_INIT_REG4 0x14 |
551 | #define PHY_REALTEK_INIT_REG5 0x18 | |
552 | #define PHY_REALTEK_INIT_REG6 0x11 | |
22ae03a1 | 553 | #define PHY_REALTEK_INIT_REG7 0x01 |
c5e3ae88 AA |
554 | #define PHY_REALTEK_INIT1 0x0000 |
555 | #define PHY_REALTEK_INIT2 0x8e00 | |
556 | #define PHY_REALTEK_INIT3 0x0001 | |
557 | #define PHY_REALTEK_INIT4 0xad17 | |
9f3f7910 AA |
558 | #define PHY_REALTEK_INIT5 0xfb54 |
559 | #define PHY_REALTEK_INIT6 0xf5c7 | |
560 | #define PHY_REALTEK_INIT7 0x1000 | |
561 | #define PHY_REALTEK_INIT8 0x0003 | |
22ae03a1 AA |
562 | #define PHY_REALTEK_INIT9 0x0008 |
563 | #define PHY_REALTEK_INIT10 0x0005 | |
564 | #define PHY_REALTEK_INIT11 0x0200 | |
9f3f7910 | 565 | #define PHY_REALTEK_INIT_MSK1 0x0003 |
d215d8a2 | 566 | |
1da177e4 LT |
567 | #define PHY_GIGABIT 0x0100 |
568 | ||
569 | #define PHY_TIMEOUT 0x1 | |
570 | #define PHY_ERROR 0x2 | |
571 | ||
572 | #define PHY_100 0x1 | |
573 | #define PHY_1000 0x2 | |
574 | #define PHY_HALF 0x100 | |
575 | ||
eb91f61b AA |
576 | #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 |
577 | #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 | |
578 | #define NV_PAUSEFRAME_RX_ENABLE 0x0004 | |
579 | #define NV_PAUSEFRAME_TX_ENABLE 0x0008 | |
b6d0773f AA |
580 | #define NV_PAUSEFRAME_RX_REQ 0x0010 |
581 | #define NV_PAUSEFRAME_TX_REQ 0x0020 | |
582 | #define NV_PAUSEFRAME_AUTONEG 0x0040 | |
1da177e4 | 583 | |
d33a73c8 AA |
584 | /* MSI/MSI-X defines */ |
585 | #define NV_MSI_X_MAX_VECTORS 8 | |
586 | #define NV_MSI_X_VECTORS_MASK 0x000f | |
587 | #define NV_MSI_CAPABLE 0x0010 | |
588 | #define NV_MSI_X_CAPABLE 0x0020 | |
589 | #define NV_MSI_ENABLED 0x0040 | |
590 | #define NV_MSI_X_ENABLED 0x0080 | |
591 | ||
592 | #define NV_MSI_X_VECTOR_ALL 0x0 | |
593 | #define NV_MSI_X_VECTOR_RX 0x0 | |
594 | #define NV_MSI_X_VECTOR_TX 0x1 | |
595 | #define NV_MSI_X_VECTOR_OTHER 0x2 | |
1da177e4 | 596 | |
b6e4405b AA |
597 | #define NV_MSI_PRIV_OFFSET 0x68 |
598 | #define NV_MSI_PRIV_VALUE 0xffffffff | |
599 | ||
b2976d23 AA |
600 | #define NV_RESTART_TX 0x1 |
601 | #define NV_RESTART_RX 0x2 | |
602 | ||
3b446c3e AA |
603 | #define NV_TX_LIMIT_COUNT 16 |
604 | ||
4145ade2 AA |
605 | #define NV_DYNAMIC_THRESHOLD 4 |
606 | #define NV_DYNAMIC_MAX_QUIET_COUNT 2048 | |
607 | ||
52da3578 AA |
608 | /* statistics */ |
609 | struct nv_ethtool_str { | |
610 | char name[ETH_GSTRING_LEN]; | |
611 | }; | |
612 | ||
613 | static const struct nv_ethtool_str nv_estats_str[] = { | |
614 | { "tx_bytes" }, | |
615 | { "tx_zero_rexmt" }, | |
616 | { "tx_one_rexmt" }, | |
617 | { "tx_many_rexmt" }, | |
618 | { "tx_late_collision" }, | |
619 | { "tx_fifo_errors" }, | |
620 | { "tx_carrier_errors" }, | |
621 | { "tx_excess_deferral" }, | |
622 | { "tx_retry_error" }, | |
52da3578 AA |
623 | { "rx_frame_error" }, |
624 | { "rx_extra_byte" }, | |
625 | { "rx_late_collision" }, | |
626 | { "rx_runt" }, | |
627 | { "rx_frame_too_long" }, | |
628 | { "rx_over_errors" }, | |
629 | { "rx_crc_errors" }, | |
630 | { "rx_frame_align_error" }, | |
631 | { "rx_length_error" }, | |
632 | { "rx_unicast" }, | |
633 | { "rx_multicast" }, | |
634 | { "rx_broadcast" }, | |
57fff698 AA |
635 | { "rx_packets" }, |
636 | { "rx_errors_total" }, | |
637 | { "tx_errors_total" }, | |
638 | ||
639 | /* version 2 stats */ | |
640 | { "tx_deferral" }, | |
641 | { "tx_packets" }, | |
52da3578 | 642 | { "rx_bytes" }, |
57fff698 | 643 | { "tx_pause" }, |
52da3578 | 644 | { "rx_pause" }, |
9c662435 AA |
645 | { "rx_drop_frame" }, |
646 | ||
647 | /* version 3 stats */ | |
648 | { "tx_unicast" }, | |
649 | { "tx_multicast" }, | |
650 | { "tx_broadcast" } | |
52da3578 AA |
651 | }; |
652 | ||
653 | struct nv_ethtool_stats { | |
654 | u64 tx_bytes; | |
655 | u64 tx_zero_rexmt; | |
656 | u64 tx_one_rexmt; | |
657 | u64 tx_many_rexmt; | |
658 | u64 tx_late_collision; | |
659 | u64 tx_fifo_errors; | |
660 | u64 tx_carrier_errors; | |
661 | u64 tx_excess_deferral; | |
662 | u64 tx_retry_error; | |
52da3578 AA |
663 | u64 rx_frame_error; |
664 | u64 rx_extra_byte; | |
665 | u64 rx_late_collision; | |
666 | u64 rx_runt; | |
667 | u64 rx_frame_too_long; | |
668 | u64 rx_over_errors; | |
669 | u64 rx_crc_errors; | |
670 | u64 rx_frame_align_error; | |
671 | u64 rx_length_error; | |
672 | u64 rx_unicast; | |
673 | u64 rx_multicast; | |
674 | u64 rx_broadcast; | |
57fff698 AA |
675 | u64 rx_packets; |
676 | u64 rx_errors_total; | |
677 | u64 tx_errors_total; | |
678 | ||
679 | /* version 2 stats */ | |
680 | u64 tx_deferral; | |
681 | u64 tx_packets; | |
52da3578 | 682 | u64 rx_bytes; |
57fff698 | 683 | u64 tx_pause; |
52da3578 AA |
684 | u64 rx_pause; |
685 | u64 rx_drop_frame; | |
9c662435 AA |
686 | |
687 | /* version 3 stats */ | |
688 | u64 tx_unicast; | |
689 | u64 tx_multicast; | |
690 | u64 tx_broadcast; | |
52da3578 AA |
691 | }; |
692 | ||
9c662435 AA |
693 | #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) |
694 | #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3) | |
57fff698 AA |
695 | #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) |
696 | ||
9589c77a AA |
697 | /* diagnostics */ |
698 | #define NV_TEST_COUNT_BASE 3 | |
699 | #define NV_TEST_COUNT_EXTENDED 4 | |
700 | ||
701 | static const struct nv_ethtool_str nv_etests_str[] = { | |
702 | { "link (online/offline)" }, | |
703 | { "register (offline) " }, | |
704 | { "interrupt (offline) " }, | |
705 | { "loopback (offline) " } | |
706 | }; | |
707 | ||
708 | struct register_test { | |
5bb7ea26 AV |
709 | __u32 reg; |
710 | __u32 mask; | |
9589c77a AA |
711 | }; |
712 | ||
713 | static const struct register_test nv_registers_test[] = { | |
714 | { NvRegUnknownSetupReg6, 0x01 }, | |
715 | { NvRegMisc1, 0x03c }, | |
716 | { NvRegOffloadConfig, 0x03ff }, | |
717 | { NvRegMulticastAddrA, 0xffffffff }, | |
95d161cb | 718 | { NvRegTxWatermark, 0x0ff }, |
9589c77a | 719 | { NvRegWakeUpFlags, 0x07777 }, |
78aea4fc | 720 | { 0, 0 } |
9589c77a AA |
721 | }; |
722 | ||
761fcd9e AA |
723 | struct nv_skb_map { |
724 | struct sk_buff *skb; | |
725 | dma_addr_t dma; | |
73a37079 ED |
726 | unsigned int dma_len:31; |
727 | unsigned int dma_single:1; | |
3b446c3e AA |
728 | struct ring_desc_ex *first_tx_desc; |
729 | struct nv_skb_map *next_tx_ctx; | |
761fcd9e AA |
730 | }; |
731 | ||
1da177e4 LT |
732 | /* |
733 | * SMP locking: | |
b74ca3a8 | 734 | * All hardware access under netdev_priv(dev)->lock, except the performance |
1da177e4 LT |
735 | * critical parts: |
736 | * - rx is (pseudo-) lockless: it relies on the single-threading provided | |
737 | * by the arch code for interrupts. | |
932ff279 | 738 | * - tx setup is lockless: it relies on netif_tx_lock. Actual submission |
b74ca3a8 | 739 | * needs netdev_priv(dev)->lock :-( |
932ff279 | 740 | * - set_multicast_list: preparation lockless, relies on netif_tx_lock. |
1da177e4 LT |
741 | */ |
742 | ||
743 | /* in dev: base, irq */ | |
744 | struct fe_priv { | |
745 | spinlock_t lock; | |
746 | ||
bea3348e SH |
747 | struct net_device *dev; |
748 | struct napi_struct napi; | |
749 | ||
1da177e4 LT |
750 | /* General data: |
751 | * Locking: spin_lock(&np->lock); */ | |
52da3578 | 752 | struct nv_ethtool_stats estats; |
1da177e4 LT |
753 | int in_shutdown; |
754 | u32 linkspeed; | |
755 | int duplex; | |
756 | int autoneg; | |
757 | int fixed_mode; | |
758 | int phyaddr; | |
759 | int wolenabled; | |
760 | unsigned int phy_oui; | |
edf7e5ec | 761 | unsigned int phy_model; |
9f3f7910 | 762 | unsigned int phy_rev; |
1da177e4 | 763 | u16 gigabit; |
9589c77a | 764 | int intr_test; |
c5cf9101 | 765 | int recover_error; |
4145ade2 | 766 | int quiet_count; |
1da177e4 LT |
767 | |
768 | /* General data: RO fields */ | |
769 | dma_addr_t ring_addr; | |
770 | struct pci_dev *pci_dev; | |
771 | u32 orig_mac[2]; | |
582806be | 772 | u32 events; |
1da177e4 LT |
773 | u32 irqmask; |
774 | u32 desc_ver; | |
8a4ae7f2 | 775 | u32 txrxctl_bits; |
ee407b02 | 776 | u32 vlanctl_bits; |
86a0f043 | 777 | u32 driver_data; |
9f3f7910 | 778 | u32 device_id; |
86a0f043 | 779 | u32 register_size; |
f2ad2d9b | 780 | int rx_csum; |
7e680c22 | 781 | u32 mac_in_use; |
cac1c52c AA |
782 | int mgmt_version; |
783 | int mgmt_sema; | |
1da177e4 LT |
784 | |
785 | void __iomem *base; | |
786 | ||
787 | /* rx specific fields. | |
788 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
789 | */ | |
761fcd9e AA |
790 | union ring_type get_rx, put_rx, first_rx, last_rx; |
791 | struct nv_skb_map *get_rx_ctx, *put_rx_ctx; | |
792 | struct nv_skb_map *first_rx_ctx, *last_rx_ctx; | |
793 | struct nv_skb_map *rx_skb; | |
794 | ||
f82a9352 | 795 | union ring_type rx_ring; |
1da177e4 | 796 | unsigned int rx_buf_sz; |
d81c0983 | 797 | unsigned int pkt_limit; |
1da177e4 LT |
798 | struct timer_list oom_kick; |
799 | struct timer_list nic_poll; | |
52da3578 | 800 | struct timer_list stats_poll; |
d33a73c8 | 801 | u32 nic_poll_irq; |
eafa59f6 | 802 | int rx_ring_size; |
1da177e4 LT |
803 | |
804 | /* media detection workaround. | |
805 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
806 | */ | |
807 | int need_linktimer; | |
808 | unsigned long link_timeout; | |
809 | /* | |
810 | * tx specific fields. | |
811 | */ | |
761fcd9e AA |
812 | union ring_type get_tx, put_tx, first_tx, last_tx; |
813 | struct nv_skb_map *get_tx_ctx, *put_tx_ctx; | |
814 | struct nv_skb_map *first_tx_ctx, *last_tx_ctx; | |
815 | struct nv_skb_map *tx_skb; | |
816 | ||
f82a9352 | 817 | union ring_type tx_ring; |
1da177e4 | 818 | u32 tx_flags; |
eafa59f6 | 819 | int tx_ring_size; |
3b446c3e AA |
820 | int tx_limit; |
821 | u32 tx_pkts_in_progress; | |
822 | struct nv_skb_map *tx_change_owner; | |
823 | struct nv_skb_map *tx_end_flip; | |
aaa37d2d | 824 | int tx_stop; |
ee407b02 AA |
825 | |
826 | /* vlan fields */ | |
827 | struct vlan_group *vlangrp; | |
d33a73c8 AA |
828 | |
829 | /* msi/msi-x fields */ | |
830 | u32 msi_flags; | |
831 | struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; | |
eb91f61b AA |
832 | |
833 | /* flow control */ | |
834 | u32 pause_flags; | |
1a1ca861 TD |
835 | |
836 | /* power saved state */ | |
837 | u32 saved_config_space[NV_PCI_REGSZ_MAX/4]; | |
ddb213f0 YL |
838 | |
839 | /* for different msi-x irq type */ | |
840 | char name_rx[IFNAMSIZ + 3]; /* -rx */ | |
841 | char name_tx[IFNAMSIZ + 3]; /* -tx */ | |
842 | char name_other[IFNAMSIZ + 6]; /* -other */ | |
1da177e4 LT |
843 | }; |
844 | ||
845 | /* | |
846 | * Maximum number of loops until we assume that a bit in the irq mask | |
847 | * is stuck. Overridable with module param. | |
848 | */ | |
4145ade2 | 849 | static int max_interrupt_work = 4; |
1da177e4 | 850 | |
a971c324 AA |
851 | /* |
852 | * Optimization can be either throuput mode or cpu mode | |
f3b197ac | 853 | * |
a971c324 AA |
854 | * Throughput Mode: Every tx and rx packet will generate an interrupt. |
855 | * CPU Mode: Interrupts are controlled by a timer. | |
856 | */ | |
69fe3fd7 AA |
857 | enum { |
858 | NV_OPTIMIZATION_MODE_THROUGHPUT, | |
9e184767 AA |
859 | NV_OPTIMIZATION_MODE_CPU, |
860 | NV_OPTIMIZATION_MODE_DYNAMIC | |
69fe3fd7 | 861 | }; |
9e184767 | 862 | static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC; |
a971c324 AA |
863 | |
864 | /* | |
865 | * Poll interval for timer irq | |
866 | * | |
867 | * This interval determines how frequent an interrupt is generated. | |
868 | * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] | |
869 | * Min = 0, and Max = 65535 | |
870 | */ | |
871 | static int poll_interval = -1; | |
872 | ||
d33a73c8 | 873 | /* |
69fe3fd7 | 874 | * MSI interrupts |
d33a73c8 | 875 | */ |
69fe3fd7 AA |
876 | enum { |
877 | NV_MSI_INT_DISABLED, | |
878 | NV_MSI_INT_ENABLED | |
879 | }; | |
880 | static int msi = NV_MSI_INT_ENABLED; | |
d33a73c8 AA |
881 | |
882 | /* | |
69fe3fd7 | 883 | * MSIX interrupts |
d33a73c8 | 884 | */ |
69fe3fd7 AA |
885 | enum { |
886 | NV_MSIX_INT_DISABLED, | |
887 | NV_MSIX_INT_ENABLED | |
888 | }; | |
39482791 | 889 | static int msix = NV_MSIX_INT_ENABLED; |
69fe3fd7 AA |
890 | |
891 | /* | |
892 | * DMA 64bit | |
893 | */ | |
894 | enum { | |
895 | NV_DMA_64BIT_DISABLED, | |
896 | NV_DMA_64BIT_ENABLED | |
897 | }; | |
898 | static int dma_64bit = NV_DMA_64BIT_ENABLED; | |
d33a73c8 | 899 | |
9f3f7910 AA |
900 | /* |
901 | * Crossover Detection | |
902 | * Realtek 8201 phy + some OEM boards do not work properly. | |
903 | */ | |
904 | enum { | |
905 | NV_CROSSOVER_DETECTION_DISABLED, | |
906 | NV_CROSSOVER_DETECTION_ENABLED | |
907 | }; | |
908 | static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED; | |
909 | ||
5a9a8e32 ES |
910 | /* |
911 | * Power down phy when interface is down (persists through reboot; | |
912 | * older Linux and other OSes may not power it up again) | |
913 | */ | |
78aea4fc | 914 | static int phy_power_down; |
5a9a8e32 | 915 | |
1da177e4 LT |
916 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
917 | { | |
918 | return netdev_priv(dev); | |
919 | } | |
920 | ||
921 | static inline u8 __iomem *get_hwbase(struct net_device *dev) | |
922 | { | |
ac9c1897 | 923 | return ((struct fe_priv *)netdev_priv(dev))->base; |
1da177e4 LT |
924 | } |
925 | ||
926 | static inline void pci_push(u8 __iomem *base) | |
927 | { | |
928 | /* force out pending posted writes */ | |
929 | readl(base); | |
930 | } | |
931 | ||
932 | static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) | |
933 | { | |
f82a9352 | 934 | return le32_to_cpu(prd->flaglen) |
1da177e4 LT |
935 | & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
936 | } | |
937 | ||
ee73362c MS |
938 | static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
939 | { | |
f82a9352 | 940 | return le32_to_cpu(prd->flaglen) & LEN_MASK_V2; |
ee73362c MS |
941 | } |
942 | ||
36b30ea9 JG |
943 | static bool nv_optimized(struct fe_priv *np) |
944 | { | |
945 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | |
946 | return false; | |
947 | return true; | |
948 | } | |
949 | ||
1da177e4 LT |
950 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
951 | int delay, int delaymax, const char *msg) | |
952 | { | |
953 | u8 __iomem *base = get_hwbase(dev); | |
954 | ||
955 | pci_push(base); | |
956 | do { | |
957 | udelay(delay); | |
958 | delaymax -= delay; | |
959 | if (delaymax < 0) { | |
960 | if (msg) | |
6a64cd64 | 961 | printk("%s", msg); |
1da177e4 LT |
962 | return 1; |
963 | } | |
964 | } while ((readl(base + offset) & mask) != target); | |
965 | return 0; | |
966 | } | |
967 | ||
0832b25a AA |
968 | #define NV_SETUP_RX_RING 0x01 |
969 | #define NV_SETUP_TX_RING 0x02 | |
970 | ||
5bb7ea26 AV |
971 | static inline u32 dma_low(dma_addr_t addr) |
972 | { | |
973 | return addr; | |
974 | } | |
975 | ||
976 | static inline u32 dma_high(dma_addr_t addr) | |
977 | { | |
978 | return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */ | |
979 | } | |
980 | ||
0832b25a AA |
981 | static void setup_hw_rings(struct net_device *dev, int rxtx_flags) |
982 | { | |
983 | struct fe_priv *np = get_nvpriv(dev); | |
984 | u8 __iomem *base = get_hwbase(dev); | |
985 | ||
36b30ea9 | 986 | if (!nv_optimized(np)) { |
78aea4fc | 987 | if (rxtx_flags & NV_SETUP_RX_RING) |
5bb7ea26 | 988 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
78aea4fc | 989 | if (rxtx_flags & NV_SETUP_TX_RING) |
5bb7ea26 | 990 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
0832b25a AA |
991 | } else { |
992 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
5bb7ea26 AV |
993 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
994 | writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); | |
0832b25a AA |
995 | } |
996 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
5bb7ea26 AV |
997 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
998 | writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh); | |
0832b25a AA |
999 | } |
1000 | } | |
1001 | } | |
1002 | ||
eafa59f6 AA |
1003 | static void free_rings(struct net_device *dev) |
1004 | { | |
1005 | struct fe_priv *np = get_nvpriv(dev); | |
1006 | ||
36b30ea9 | 1007 | if (!nv_optimized(np)) { |
f82a9352 | 1008 | if (np->rx_ring.orig) |
eafa59f6 AA |
1009 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
1010 | np->rx_ring.orig, np->ring_addr); | |
1011 | } else { | |
1012 | if (np->rx_ring.ex) | |
1013 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), | |
1014 | np->rx_ring.ex, np->ring_addr); | |
1015 | } | |
9b03b06b SJ |
1016 | kfree(np->rx_skb); |
1017 | kfree(np->tx_skb); | |
eafa59f6 AA |
1018 | } |
1019 | ||
84b3932b AA |
1020 | static int using_multi_irqs(struct net_device *dev) |
1021 | { | |
1022 | struct fe_priv *np = get_nvpriv(dev); | |
1023 | ||
1024 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || | |
1025 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
1026 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) | |
1027 | return 0; | |
1028 | else | |
1029 | return 1; | |
1030 | } | |
1031 | ||
88d7d8b0 AA |
1032 | static void nv_txrx_gate(struct net_device *dev, bool gate) |
1033 | { | |
1034 | struct fe_priv *np = get_nvpriv(dev); | |
1035 | u8 __iomem *base = get_hwbase(dev); | |
1036 | u32 powerstate; | |
1037 | ||
1038 | if (!np->mac_in_use && | |
1039 | (np->driver_data & DEV_HAS_POWER_CNTRL)) { | |
1040 | powerstate = readl(base + NvRegPowerState2); | |
1041 | if (gate) | |
1042 | powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS; | |
1043 | else | |
1044 | powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS; | |
1045 | writel(powerstate, base + NvRegPowerState2); | |
1046 | } | |
1047 | } | |
1048 | ||
84b3932b AA |
1049 | static void nv_enable_irq(struct net_device *dev) |
1050 | { | |
1051 | struct fe_priv *np = get_nvpriv(dev); | |
1052 | ||
1053 | if (!using_multi_irqs(dev)) { | |
1054 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1055 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1056 | else | |
a7475906 | 1057 | enable_irq(np->pci_dev->irq); |
84b3932b AA |
1058 | } else { |
1059 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1060 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1061 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1062 | } | |
1063 | } | |
1064 | ||
1065 | static void nv_disable_irq(struct net_device *dev) | |
1066 | { | |
1067 | struct fe_priv *np = get_nvpriv(dev); | |
1068 | ||
1069 | if (!using_multi_irqs(dev)) { | |
1070 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1071 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1072 | else | |
a7475906 | 1073 | disable_irq(np->pci_dev->irq); |
84b3932b AA |
1074 | } else { |
1075 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1076 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1077 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1078 | } | |
1079 | } | |
1080 | ||
1081 | /* In MSIX mode, a write to irqmask behaves as XOR */ | |
1082 | static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) | |
1083 | { | |
1084 | u8 __iomem *base = get_hwbase(dev); | |
1085 | ||
1086 | writel(mask, base + NvRegIrqMask); | |
1087 | } | |
1088 | ||
1089 | static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) | |
1090 | { | |
1091 | struct fe_priv *np = get_nvpriv(dev); | |
1092 | u8 __iomem *base = get_hwbase(dev); | |
1093 | ||
1094 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
1095 | writel(mask, base + NvRegIrqMask); | |
1096 | } else { | |
1097 | if (np->msi_flags & NV_MSI_ENABLED) | |
1098 | writel(0, base + NvRegMSIIrqMask); | |
1099 | writel(0, base + NvRegIrqMask); | |
1100 | } | |
1101 | } | |
1102 | ||
08d93575 AA |
1103 | static void nv_napi_enable(struct net_device *dev) |
1104 | { | |
08d93575 AA |
1105 | struct fe_priv *np = get_nvpriv(dev); |
1106 | ||
1107 | napi_enable(&np->napi); | |
08d93575 AA |
1108 | } |
1109 | ||
1110 | static void nv_napi_disable(struct net_device *dev) | |
1111 | { | |
08d93575 AA |
1112 | struct fe_priv *np = get_nvpriv(dev); |
1113 | ||
1114 | napi_disable(&np->napi); | |
08d93575 AA |
1115 | } |
1116 | ||
1da177e4 LT |
1117 | #define MII_READ (-1) |
1118 | /* mii_rw: read/write a register on the PHY. | |
1119 | * | |
1120 | * Caller must guarantee serialization | |
1121 | */ | |
1122 | static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |
1123 | { | |
1124 | u8 __iomem *base = get_hwbase(dev); | |
1125 | u32 reg; | |
1126 | int retval; | |
1127 | ||
eb798428 | 1128 | writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus); |
1da177e4 LT |
1129 | |
1130 | reg = readl(base + NvRegMIIControl); | |
1131 | if (reg & NVREG_MIICTL_INUSE) { | |
1132 | writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); | |
1133 | udelay(NV_MIIBUSY_DELAY); | |
1134 | } | |
1135 | ||
1136 | reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; | |
1137 | if (value != MII_READ) { | |
1138 | writel(value, base + NvRegMIIData); | |
1139 | reg |= NVREG_MIICTL_WRITE; | |
1140 | } | |
1141 | writel(reg, base + NvRegMIIControl); | |
1142 | ||
1143 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, | |
1144 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { | |
1145 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n", | |
1146 | dev->name, miireg, addr); | |
1147 | retval = -1; | |
1148 | } else if (value != MII_READ) { | |
1149 | /* it was a write operation - fewer failures are detectable */ | |
1150 | dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n", | |
1151 | dev->name, value, miireg, addr); | |
1152 | retval = 0; | |
1153 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { | |
1154 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n", | |
1155 | dev->name, miireg, addr); | |
1156 | retval = -1; | |
1157 | } else { | |
1158 | retval = readl(base + NvRegMIIData); | |
1159 | dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n", | |
1160 | dev->name, miireg, addr, retval); | |
1161 | } | |
1162 | ||
1163 | return retval; | |
1164 | } | |
1165 | ||
edf7e5ec | 1166 | static int phy_reset(struct net_device *dev, u32 bmcr_setup) |
1da177e4 | 1167 | { |
ac9c1897 | 1168 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1169 | u32 miicontrol; |
1170 | unsigned int tries = 0; | |
1171 | ||
edf7e5ec | 1172 | miicontrol = BMCR_RESET | bmcr_setup; |
78aea4fc | 1173 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) |
1da177e4 | 1174 | return -1; |
1da177e4 LT |
1175 | |
1176 | /* wait for 500ms */ | |
1177 | msleep(500); | |
1178 | ||
1179 | /* must wait till reset is deasserted */ | |
1180 | while (miicontrol & BMCR_RESET) { | |
1181 | msleep(10); | |
1182 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
1183 | /* FIXME: 100 tries seem excessive */ | |
1184 | if (tries++ > 100) | |
1185 | return -1; | |
1186 | } | |
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | static int phy_init(struct net_device *dev) | |
1191 | { | |
1192 | struct fe_priv *np = get_nvpriv(dev); | |
1193 | u8 __iomem *base = get_hwbase(dev); | |
78aea4fc | 1194 | u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000, reg; |
1da177e4 | 1195 | |
edf7e5ec AA |
1196 | /* phy errata for E3016 phy */ |
1197 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | |
1198 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1199 | reg &= ~PHY_MARVELL_E3016_INITMASK; | |
1200 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { | |
1201 | printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev)); | |
1202 | return PHY_ERROR; | |
1203 | } | |
1204 | } | |
c5e3ae88 | 1205 | if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1206 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1207 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
1208 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1209 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1210 | return PHY_ERROR; | |
1211 | } | |
1212 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { | |
1213 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1214 | return PHY_ERROR; | |
1215 | } | |
1216 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | |
1217 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1218 | return PHY_ERROR; | |
1219 | } | |
1220 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { | |
1221 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1222 | return PHY_ERROR; | |
1223 | } | |
1224 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { | |
1225 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1226 | return PHY_ERROR; | |
1227 | } | |
1228 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { | |
1229 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1230 | return PHY_ERROR; | |
1231 | } | |
1232 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1233 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1234 | return PHY_ERROR; | |
1235 | } | |
c5e3ae88 | 1236 | } |
22ae03a1 AA |
1237 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1238 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1239 | u32 powerstate = readl(base + NvRegPowerState2); | |
1240 | ||
1241 | /* need to perform hw phy reset */ | |
1242 | powerstate |= NVREG_POWERSTATE2_PHY_RESET; | |
1243 | writel(powerstate, base + NvRegPowerState2); | |
1244 | msleep(25); | |
1245 | ||
1246 | powerstate &= ~NVREG_POWERSTATE2_PHY_RESET; | |
1247 | writel(powerstate, base + NvRegPowerState2); | |
1248 | msleep(25); | |
1249 | ||
1250 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | |
1251 | reg |= PHY_REALTEK_INIT9; | |
1252 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) { | |
1253 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1254 | return PHY_ERROR; | |
1255 | } | |
1256 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) { | |
1257 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1258 | return PHY_ERROR; | |
1259 | } | |
1260 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); | |
1261 | if (!(reg & PHY_REALTEK_INIT11)) { | |
1262 | reg |= PHY_REALTEK_INIT11; | |
1263 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) { | |
1264 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1265 | return PHY_ERROR; | |
1266 | } | |
1267 | } | |
1268 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1269 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1270 | return PHY_ERROR; | |
1271 | } | |
1272 | } | |
9f3f7910 | 1273 | if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
3c2e1c11 | 1274 | if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { |
9f3f7910 AA |
1275 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); |
1276 | phy_reserved |= PHY_REALTEK_INIT7; | |
1277 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { | |
1278 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1279 | return PHY_ERROR; | |
1280 | } | |
1281 | } | |
c5e3ae88 AA |
1282 | } |
1283 | } | |
edf7e5ec | 1284 | |
1da177e4 LT |
1285 | /* set advertise register */ |
1286 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 1287 | reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); |
1da177e4 LT |
1288 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1289 | printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); | |
1290 | return PHY_ERROR; | |
1291 | } | |
1292 | ||
1293 | /* get phy interface type */ | |
1294 | phyinterface = readl(base + NvRegPhyInterface); | |
1295 | ||
1296 | /* see if gigabit phy */ | |
1297 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
1298 | if (mii_status & PHY_GIGABIT) { | |
1299 | np->gigabit = PHY_GIGABIT; | |
eb91f61b | 1300 | mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
1301 | mii_control_1000 &= ~ADVERTISE_1000HALF; |
1302 | if (phyinterface & PHY_RGMII) | |
1303 | mii_control_1000 |= ADVERTISE_1000FULL; | |
1304 | else | |
1305 | mii_control_1000 &= ~ADVERTISE_1000FULL; | |
1306 | ||
eb91f61b | 1307 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1da177e4 LT |
1308 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1309 | return PHY_ERROR; | |
1310 | } | |
78aea4fc | 1311 | } else |
1da177e4 LT |
1312 | np->gigabit = 0; |
1313 | ||
edf7e5ec AA |
1314 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1315 | mii_control |= BMCR_ANENABLE; | |
1316 | ||
22ae03a1 AA |
1317 | if (np->phy_oui == PHY_OUI_REALTEK && |
1318 | np->phy_model == PHY_MODEL_REALTEK_8211 && | |
1319 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1320 | /* start autoneg since we already performed hw reset above */ | |
1321 | mii_control |= BMCR_ANRESTART; | |
1322 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | |
1323 | printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev)); | |
1324 | return PHY_ERROR; | |
1325 | } | |
1326 | } else { | |
1327 | /* reset the phy | |
1328 | * (certain phys need bmcr to be setup with reset) | |
1329 | */ | |
1330 | if (phy_reset(dev, mii_control)) { | |
1331 | printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); | |
1332 | return PHY_ERROR; | |
1333 | } | |
1da177e4 LT |
1334 | } |
1335 | ||
1336 | /* phy vendor specific configuration */ | |
78aea4fc | 1337 | if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) { |
1da177e4 | 1338 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); |
14a67f3c AA |
1339 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); |
1340 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); | |
1da177e4 LT |
1341 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
1342 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1343 | return PHY_ERROR; | |
1344 | } | |
1345 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
14a67f3c | 1346 | phy_reserved |= PHY_CICADA_INIT5; |
1da177e4 LT |
1347 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
1348 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1349 | return PHY_ERROR; | |
1350 | } | |
1351 | } | |
1352 | if (np->phy_oui == PHY_OUI_CICADA) { | |
1353 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | |
14a67f3c | 1354 | phy_reserved |= PHY_CICADA_INIT6; |
1da177e4 LT |
1355 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
1356 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1357 | return PHY_ERROR; | |
1358 | } | |
1359 | } | |
d215d8a2 AA |
1360 | if (np->phy_oui == PHY_OUI_VITESSE) { |
1361 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) { | |
1362 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1363 | return PHY_ERROR; | |
1364 | } | |
1365 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) { | |
1366 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1367 | return PHY_ERROR; | |
1368 | } | |
1369 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1370 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1371 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1372 | return PHY_ERROR; | |
1373 | } | |
1374 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1375 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1376 | phy_reserved |= PHY_VITESSE_INIT3; | |
1377 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1378 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1379 | return PHY_ERROR; | |
1380 | } | |
1381 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) { | |
1382 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1383 | return PHY_ERROR; | |
1384 | } | |
1385 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { | |
1386 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1387 | return PHY_ERROR; | |
1388 | } | |
1389 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1390 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1391 | phy_reserved |= PHY_VITESSE_INIT3; | |
1392 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1393 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1394 | return PHY_ERROR; | |
1395 | } | |
1396 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1397 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1398 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1399 | return PHY_ERROR; | |
1400 | } | |
1401 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) { | |
1402 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1403 | return PHY_ERROR; | |
1404 | } | |
1405 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) { | |
1406 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1407 | return PHY_ERROR; | |
1408 | } | |
1409 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1410 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1411 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1412 | return PHY_ERROR; | |
1413 | } | |
1414 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1415 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; | |
1416 | phy_reserved |= PHY_VITESSE_INIT8; | |
1417 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1418 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1419 | return PHY_ERROR; | |
1420 | } | |
1421 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) { | |
1422 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1423 | return PHY_ERROR; | |
1424 | } | |
1425 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) { | |
1426 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1427 | return PHY_ERROR; | |
1428 | } | |
1429 | } | |
c5e3ae88 | 1430 | if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1431 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1432 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
1433 | /* reset could have cleared these out, set them back */ | |
1434 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1435 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1436 | return PHY_ERROR; | |
1437 | } | |
1438 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { | |
1439 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1440 | return PHY_ERROR; | |
1441 | } | |
1442 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | |
1443 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1444 | return PHY_ERROR; | |
1445 | } | |
1446 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { | |
1447 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1448 | return PHY_ERROR; | |
1449 | } | |
1450 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { | |
1451 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1452 | return PHY_ERROR; | |
1453 | } | |
1454 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { | |
1455 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1456 | return PHY_ERROR; | |
1457 | } | |
1458 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1459 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1460 | return PHY_ERROR; | |
1461 | } | |
c5e3ae88 | 1462 | } |
9f3f7910 | 1463 | if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
3c2e1c11 | 1464 | if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { |
9f3f7910 AA |
1465 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); |
1466 | phy_reserved |= PHY_REALTEK_INIT7; | |
1467 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { | |
1468 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1469 | return PHY_ERROR; | |
1470 | } | |
1471 | } | |
1472 | if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
1473 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | |
1474 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1475 | return PHY_ERROR; | |
1476 | } | |
1477 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | |
1478 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
1479 | phy_reserved |= PHY_REALTEK_INIT3; | |
1480 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) { | |
1481 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1482 | return PHY_ERROR; | |
1483 | } | |
1484 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1485 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1486 | return PHY_ERROR; | |
1487 | } | |
1488 | } | |
c5e3ae88 AA |
1489 | } |
1490 | } | |
1491 | ||
eb91f61b AA |
1492 | /* some phys clear out pause advertisment on reset, set it back */ |
1493 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); | |
1da177e4 | 1494 | |
cb52deba | 1495 | /* restart auto negotiation, power down phy */ |
1da177e4 | 1496 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
5a9a8e32 | 1497 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
78aea4fc | 1498 | if (phy_power_down) |
5a9a8e32 | 1499 | mii_control |= BMCR_PDOWN; |
78aea4fc | 1500 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) |
1da177e4 | 1501 | return PHY_ERROR; |
1da177e4 LT |
1502 | |
1503 | return 0; | |
1504 | } | |
1505 | ||
1506 | static void nv_start_rx(struct net_device *dev) | |
1507 | { | |
ac9c1897 | 1508 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1509 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1510 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 LT |
1511 | |
1512 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); | |
1513 | /* Already running? Stop it. */ | |
f35723ec AA |
1514 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1515 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1516 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1517 | pci_push(base); |
1518 | } | |
1519 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
1520 | pci_push(base); | |
78aea4fc SJ |
1521 | rx_ctrl |= NVREG_RCVCTL_START; |
1522 | if (np->mac_in_use) | |
f35723ec AA |
1523 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; |
1524 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1525 | dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
1526 | dev->name, np->duplex, np->linkspeed); | |
1527 | pci_push(base); | |
1528 | } | |
1529 | ||
1530 | static void nv_stop_rx(struct net_device *dev) | |
1531 | { | |
f35723ec | 1532 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1533 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1534 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 LT |
1535 | |
1536 | dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); | |
f35723ec AA |
1537 | if (!np->mac_in_use) |
1538 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1539 | else | |
1540 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; | |
1541 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1542 | reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1543 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, | |
1544 | KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); | |
1545 | ||
1546 | udelay(NV_RXSTOP_DELAY2); | |
f35723ec AA |
1547 | if (!np->mac_in_use) |
1548 | writel(0, base + NvRegLinkSpeed); | |
1da177e4 LT |
1549 | } |
1550 | ||
1551 | static void nv_start_tx(struct net_device *dev) | |
1552 | { | |
f35723ec | 1553 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1554 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1555 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 LT |
1556 | |
1557 | dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); | |
f35723ec AA |
1558 | tx_ctrl |= NVREG_XMITCTL_START; |
1559 | if (np->mac_in_use) | |
1560 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; | |
1561 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1562 | pci_push(base); |
1563 | } | |
1564 | ||
1565 | static void nv_stop_tx(struct net_device *dev) | |
1566 | { | |
f35723ec | 1567 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1568 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1569 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 LT |
1570 | |
1571 | dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); | |
f35723ec AA |
1572 | if (!np->mac_in_use) |
1573 | tx_ctrl &= ~NVREG_XMITCTL_START; | |
1574 | else | |
1575 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; | |
1576 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1577 | reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1578 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, | |
1579 | KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); | |
1580 | ||
1581 | udelay(NV_TXSTOP_DELAY2); | |
f35723ec AA |
1582 | if (!np->mac_in_use) |
1583 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, | |
1584 | base + NvRegTransmitPoll); | |
1da177e4 LT |
1585 | } |
1586 | ||
36b30ea9 JG |
1587 | static void nv_start_rxtx(struct net_device *dev) |
1588 | { | |
1589 | nv_start_rx(dev); | |
1590 | nv_start_tx(dev); | |
1591 | } | |
1592 | ||
1593 | static void nv_stop_rxtx(struct net_device *dev) | |
1594 | { | |
1595 | nv_stop_rx(dev); | |
1596 | nv_stop_tx(dev); | |
1597 | } | |
1598 | ||
1da177e4 LT |
1599 | static void nv_txrx_reset(struct net_device *dev) |
1600 | { | |
ac9c1897 | 1601 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1602 | u8 __iomem *base = get_hwbase(dev); |
1603 | ||
1604 | dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); | |
8a4ae7f2 | 1605 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1606 | pci_push(base); |
1607 | udelay(NV_TXRX_RESET_DELAY); | |
8a4ae7f2 | 1608 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1609 | pci_push(base); |
1610 | } | |
1611 | ||
86a0f043 AA |
1612 | static void nv_mac_reset(struct net_device *dev) |
1613 | { | |
1614 | struct fe_priv *np = netdev_priv(dev); | |
1615 | u8 __iomem *base = get_hwbase(dev); | |
4e84f9b1 | 1616 | u32 temp1, temp2, temp3; |
86a0f043 AA |
1617 | |
1618 | dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); | |
4e84f9b1 | 1619 | |
86a0f043 AA |
1620 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1621 | pci_push(base); | |
4e84f9b1 AA |
1622 | |
1623 | /* save registers since they will be cleared on reset */ | |
1624 | temp1 = readl(base + NvRegMacAddrA); | |
1625 | temp2 = readl(base + NvRegMacAddrB); | |
1626 | temp3 = readl(base + NvRegTransmitPoll); | |
1627 | ||
86a0f043 AA |
1628 | writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); |
1629 | pci_push(base); | |
1630 | udelay(NV_MAC_RESET_DELAY); | |
1631 | writel(0, base + NvRegMacReset); | |
1632 | pci_push(base); | |
1633 | udelay(NV_MAC_RESET_DELAY); | |
4e84f9b1 AA |
1634 | |
1635 | /* restore saved registers */ | |
1636 | writel(temp1, base + NvRegMacAddrA); | |
1637 | writel(temp2, base + NvRegMacAddrB); | |
1638 | writel(temp3, base + NvRegTransmitPoll); | |
1639 | ||
86a0f043 AA |
1640 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1641 | pci_push(base); | |
1642 | } | |
1643 | ||
57fff698 AA |
1644 | static void nv_get_hw_stats(struct net_device *dev) |
1645 | { | |
1646 | struct fe_priv *np = netdev_priv(dev); | |
1647 | u8 __iomem *base = get_hwbase(dev); | |
1648 | ||
1649 | np->estats.tx_bytes += readl(base + NvRegTxCnt); | |
1650 | np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); | |
1651 | np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); | |
1652 | np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); | |
1653 | np->estats.tx_late_collision += readl(base + NvRegTxLateCol); | |
1654 | np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); | |
1655 | np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); | |
1656 | np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); | |
1657 | np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); | |
1658 | np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); | |
1659 | np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); | |
1660 | np->estats.rx_late_collision += readl(base + NvRegRxLateCol); | |
1661 | np->estats.rx_runt += readl(base + NvRegRxRunt); | |
1662 | np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); | |
1663 | np->estats.rx_over_errors += readl(base + NvRegRxOverflow); | |
1664 | np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); | |
1665 | np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); | |
1666 | np->estats.rx_length_error += readl(base + NvRegRxLenErr); | |
1667 | np->estats.rx_unicast += readl(base + NvRegRxUnicast); | |
1668 | np->estats.rx_multicast += readl(base + NvRegRxMulticast); | |
1669 | np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); | |
1670 | np->estats.rx_packets = | |
1671 | np->estats.rx_unicast + | |
1672 | np->estats.rx_multicast + | |
1673 | np->estats.rx_broadcast; | |
1674 | np->estats.rx_errors_total = | |
1675 | np->estats.rx_crc_errors + | |
1676 | np->estats.rx_over_errors + | |
1677 | np->estats.rx_frame_error + | |
1678 | (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + | |
1679 | np->estats.rx_late_collision + | |
1680 | np->estats.rx_runt + | |
1681 | np->estats.rx_frame_too_long; | |
1682 | np->estats.tx_errors_total = | |
1683 | np->estats.tx_late_collision + | |
1684 | np->estats.tx_fifo_errors + | |
1685 | np->estats.tx_carrier_errors + | |
1686 | np->estats.tx_excess_deferral + | |
1687 | np->estats.tx_retry_error; | |
1688 | ||
1689 | if (np->driver_data & DEV_HAS_STATISTICS_V2) { | |
1690 | np->estats.tx_deferral += readl(base + NvRegTxDef); | |
1691 | np->estats.tx_packets += readl(base + NvRegTxFrame); | |
1692 | np->estats.rx_bytes += readl(base + NvRegRxCnt); | |
1693 | np->estats.tx_pause += readl(base + NvRegTxPause); | |
1694 | np->estats.rx_pause += readl(base + NvRegRxPause); | |
1695 | np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); | |
1696 | } | |
9c662435 AA |
1697 | |
1698 | if (np->driver_data & DEV_HAS_STATISTICS_V3) { | |
1699 | np->estats.tx_unicast += readl(base + NvRegTxUnicast); | |
1700 | np->estats.tx_multicast += readl(base + NvRegTxMulticast); | |
1701 | np->estats.tx_broadcast += readl(base + NvRegTxBroadcast); | |
1702 | } | |
57fff698 AA |
1703 | } |
1704 | ||
1da177e4 LT |
1705 | /* |
1706 | * nv_get_stats: dev->get_stats function | |
1707 | * Get latest stats value from the nic. | |
1708 | * Called with read_lock(&dev_base_lock) held for read - | |
1709 | * only synchronized against unregister_netdevice. | |
1710 | */ | |
1711 | static struct net_device_stats *nv_get_stats(struct net_device *dev) | |
1712 | { | |
ac9c1897 | 1713 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1714 | |
21828163 | 1715 | /* If the nic supports hw counters then retrieve latest values */ |
9c662435 | 1716 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) { |
21828163 AA |
1717 | nv_get_hw_stats(dev); |
1718 | ||
1719 | /* copy to net_device stats */ | |
8148ff45 JG |
1720 | dev->stats.tx_bytes = np->estats.tx_bytes; |
1721 | dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors; | |
1722 | dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors; | |
1723 | dev->stats.rx_crc_errors = np->estats.rx_crc_errors; | |
1724 | dev->stats.rx_over_errors = np->estats.rx_over_errors; | |
1725 | dev->stats.rx_errors = np->estats.rx_errors_total; | |
1726 | dev->stats.tx_errors = np->estats.tx_errors_total; | |
21828163 | 1727 | } |
8148ff45 JG |
1728 | |
1729 | return &dev->stats; | |
1da177e4 LT |
1730 | } |
1731 | ||
1732 | /* | |
1733 | * nv_alloc_rx: fill rx ring entries. | |
1734 | * Return 1 if the allocations for the skbs failed and the | |
1735 | * rx engine is without Available descriptors | |
1736 | */ | |
1737 | static int nv_alloc_rx(struct net_device *dev) | |
1738 | { | |
ac9c1897 | 1739 | struct fe_priv *np = netdev_priv(dev); |
78aea4fc | 1740 | struct ring_desc *less_rx; |
1da177e4 | 1741 | |
86b22b0d AA |
1742 | less_rx = np->get_rx.orig; |
1743 | if (less_rx-- == np->first_rx.orig) | |
1744 | less_rx = np->last_rx.orig; | |
761fcd9e | 1745 | |
86b22b0d AA |
1746 | while (np->put_rx.orig != less_rx) { |
1747 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
1748 | if (skb) { | |
86b22b0d | 1749 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1750 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1751 | skb->data, | |
8b5be268 | 1752 | skb_tailroom(skb), |
4305b541 | 1753 | PCI_DMA_FROMDEVICE); |
8b5be268 | 1754 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
86b22b0d AA |
1755 | np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma); |
1756 | wmb(); | |
1757 | np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); | |
b01867cb | 1758 | if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 1759 | np->put_rx.orig = np->first_rx.orig; |
b01867cb | 1760 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 1761 | np->put_rx_ctx = np->first_rx_ctx; |
78aea4fc | 1762 | } else |
86b22b0d | 1763 | return 1; |
86b22b0d AA |
1764 | } |
1765 | return 0; | |
1766 | } | |
1767 | ||
1768 | static int nv_alloc_rx_optimized(struct net_device *dev) | |
1769 | { | |
1770 | struct fe_priv *np = netdev_priv(dev); | |
78aea4fc | 1771 | struct ring_desc_ex *less_rx; |
86b22b0d AA |
1772 | |
1773 | less_rx = np->get_rx.ex; | |
1774 | if (less_rx-- == np->first_rx.ex) | |
1775 | less_rx = np->last_rx.ex; | |
761fcd9e | 1776 | |
86b22b0d AA |
1777 | while (np->put_rx.ex != less_rx) { |
1778 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
0d63fb32 | 1779 | if (skb) { |
761fcd9e | 1780 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1781 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1782 | skb->data, | |
8b5be268 | 1783 | skb_tailroom(skb), |
4305b541 | 1784 | PCI_DMA_FROMDEVICE); |
8b5be268 | 1785 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
5bb7ea26 AV |
1786 | np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma)); |
1787 | np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma)); | |
86b22b0d AA |
1788 | wmb(); |
1789 | np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); | |
b01867cb | 1790 | if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 1791 | np->put_rx.ex = np->first_rx.ex; |
b01867cb | 1792 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
0d63fb32 | 1793 | np->put_rx_ctx = np->first_rx_ctx; |
78aea4fc | 1794 | } else |
0d63fb32 | 1795 | return 1; |
1da177e4 | 1796 | } |
1da177e4 LT |
1797 | return 0; |
1798 | } | |
1799 | ||
e27cdba5 | 1800 | /* If rx bufs are exhausted called after 50ms to attempt to refresh */ |
e27cdba5 SH |
1801 | static void nv_do_rx_refill(unsigned long data) |
1802 | { | |
1803 | struct net_device *dev = (struct net_device *) data; | |
bea3348e | 1804 | struct fe_priv *np = netdev_priv(dev); |
e27cdba5 SH |
1805 | |
1806 | /* Just reschedule NAPI rx processing */ | |
288379f0 | 1807 | napi_schedule(&np->napi); |
e27cdba5 | 1808 | } |
1da177e4 | 1809 | |
f3b197ac | 1810 | static void nv_init_rx(struct net_device *dev) |
1da177e4 | 1811 | { |
ac9c1897 | 1812 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1813 | int i; |
36b30ea9 | 1814 | |
761fcd9e | 1815 | np->get_rx = np->put_rx = np->first_rx = np->rx_ring; |
36b30ea9 JG |
1816 | |
1817 | if (!nv_optimized(np)) | |
761fcd9e AA |
1818 | np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; |
1819 | else | |
1820 | np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; | |
1821 | np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb; | |
1822 | np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; | |
1da177e4 | 1823 | |
761fcd9e | 1824 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1825 | if (!nv_optimized(np)) { |
f82a9352 | 1826 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1827 | np->rx_ring.orig[i].buf = 0; |
1828 | } else { | |
f82a9352 | 1829 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1830 | np->rx_ring.ex[i].txvlan = 0; |
1831 | np->rx_ring.ex[i].bufhigh = 0; | |
1832 | np->rx_ring.ex[i].buflow = 0; | |
1833 | } | |
1834 | np->rx_skb[i].skb = NULL; | |
1835 | np->rx_skb[i].dma = 0; | |
1836 | } | |
d81c0983 MS |
1837 | } |
1838 | ||
1839 | static void nv_init_tx(struct net_device *dev) | |
1840 | { | |
ac9c1897 | 1841 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 | 1842 | int i; |
36b30ea9 | 1843 | |
761fcd9e | 1844 | np->get_tx = np->put_tx = np->first_tx = np->tx_ring; |
36b30ea9 JG |
1845 | |
1846 | if (!nv_optimized(np)) | |
761fcd9e AA |
1847 | np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; |
1848 | else | |
1849 | np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; | |
1850 | np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb; | |
1851 | np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; | |
3b446c3e AA |
1852 | np->tx_pkts_in_progress = 0; |
1853 | np->tx_change_owner = NULL; | |
1854 | np->tx_end_flip = NULL; | |
8f955d7f | 1855 | np->tx_stop = 0; |
d81c0983 | 1856 | |
eafa59f6 | 1857 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1858 | if (!nv_optimized(np)) { |
f82a9352 | 1859 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1860 | np->tx_ring.orig[i].buf = 0; |
1861 | } else { | |
f82a9352 | 1862 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1863 | np->tx_ring.ex[i].txvlan = 0; |
1864 | np->tx_ring.ex[i].bufhigh = 0; | |
1865 | np->tx_ring.ex[i].buflow = 0; | |
1866 | } | |
1867 | np->tx_skb[i].skb = NULL; | |
1868 | np->tx_skb[i].dma = 0; | |
3b446c3e | 1869 | np->tx_skb[i].dma_len = 0; |
73a37079 | 1870 | np->tx_skb[i].dma_single = 0; |
3b446c3e AA |
1871 | np->tx_skb[i].first_tx_desc = NULL; |
1872 | np->tx_skb[i].next_tx_ctx = NULL; | |
ac9c1897 | 1873 | } |
d81c0983 MS |
1874 | } |
1875 | ||
1876 | static int nv_init_ring(struct net_device *dev) | |
1877 | { | |
86b22b0d AA |
1878 | struct fe_priv *np = netdev_priv(dev); |
1879 | ||
d81c0983 MS |
1880 | nv_init_tx(dev); |
1881 | nv_init_rx(dev); | |
36b30ea9 JG |
1882 | |
1883 | if (!nv_optimized(np)) | |
86b22b0d AA |
1884 | return nv_alloc_rx(dev); |
1885 | else | |
1886 | return nv_alloc_rx_optimized(dev); | |
1da177e4 LT |
1887 | } |
1888 | ||
73a37079 | 1889 | static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) |
ac9c1897 | 1890 | { |
761fcd9e | 1891 | if (tx_skb->dma) { |
73a37079 ED |
1892 | if (tx_skb->dma_single) |
1893 | pci_unmap_single(np->pci_dev, tx_skb->dma, | |
1894 | tx_skb->dma_len, | |
1895 | PCI_DMA_TODEVICE); | |
1896 | else | |
1897 | pci_unmap_page(np->pci_dev, tx_skb->dma, | |
1898 | tx_skb->dma_len, | |
1899 | PCI_DMA_TODEVICE); | |
761fcd9e | 1900 | tx_skb->dma = 0; |
fa45459e | 1901 | } |
73a37079 ED |
1902 | } |
1903 | ||
1904 | static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) | |
1905 | { | |
1906 | nv_unmap_txskb(np, tx_skb); | |
761fcd9e AA |
1907 | if (tx_skb->skb) { |
1908 | dev_kfree_skb_any(tx_skb->skb); | |
1909 | tx_skb->skb = NULL; | |
fa45459e | 1910 | return 1; |
ac9c1897 | 1911 | } |
73a37079 | 1912 | return 0; |
ac9c1897 AA |
1913 | } |
1914 | ||
1da177e4 LT |
1915 | static void nv_drain_tx(struct net_device *dev) |
1916 | { | |
ac9c1897 AA |
1917 | struct fe_priv *np = netdev_priv(dev); |
1918 | unsigned int i; | |
f3b197ac | 1919 | |
eafa59f6 | 1920 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1921 | if (!nv_optimized(np)) { |
f82a9352 | 1922 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1923 | np->tx_ring.orig[i].buf = 0; |
1924 | } else { | |
f82a9352 | 1925 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1926 | np->tx_ring.ex[i].txvlan = 0; |
1927 | np->tx_ring.ex[i].bufhigh = 0; | |
1928 | np->tx_ring.ex[i].buflow = 0; | |
1929 | } | |
73a37079 | 1930 | if (nv_release_txskb(np, &np->tx_skb[i])) |
8148ff45 | 1931 | dev->stats.tx_dropped++; |
3b446c3e AA |
1932 | np->tx_skb[i].dma = 0; |
1933 | np->tx_skb[i].dma_len = 0; | |
73a37079 | 1934 | np->tx_skb[i].dma_single = 0; |
3b446c3e AA |
1935 | np->tx_skb[i].first_tx_desc = NULL; |
1936 | np->tx_skb[i].next_tx_ctx = NULL; | |
1da177e4 | 1937 | } |
3b446c3e AA |
1938 | np->tx_pkts_in_progress = 0; |
1939 | np->tx_change_owner = NULL; | |
1940 | np->tx_end_flip = NULL; | |
1da177e4 LT |
1941 | } |
1942 | ||
1943 | static void nv_drain_rx(struct net_device *dev) | |
1944 | { | |
ac9c1897 | 1945 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1946 | int i; |
761fcd9e | 1947 | |
eafa59f6 | 1948 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1949 | if (!nv_optimized(np)) { |
f82a9352 | 1950 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1951 | np->rx_ring.orig[i].buf = 0; |
1952 | } else { | |
f82a9352 | 1953 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1954 | np->rx_ring.ex[i].txvlan = 0; |
1955 | np->rx_ring.ex[i].bufhigh = 0; | |
1956 | np->rx_ring.ex[i].buflow = 0; | |
1957 | } | |
1da177e4 | 1958 | wmb(); |
761fcd9e AA |
1959 | if (np->rx_skb[i].skb) { |
1960 | pci_unmap_single(np->pci_dev, np->rx_skb[i].dma, | |
4305b541 ACM |
1961 | (skb_end_pointer(np->rx_skb[i].skb) - |
1962 | np->rx_skb[i].skb->data), | |
1963 | PCI_DMA_FROMDEVICE); | |
761fcd9e AA |
1964 | dev_kfree_skb(np->rx_skb[i].skb); |
1965 | np->rx_skb[i].skb = NULL; | |
1da177e4 LT |
1966 | } |
1967 | } | |
1968 | } | |
1969 | ||
36b30ea9 | 1970 | static void nv_drain_rxtx(struct net_device *dev) |
1da177e4 LT |
1971 | { |
1972 | nv_drain_tx(dev); | |
1973 | nv_drain_rx(dev); | |
1974 | } | |
1975 | ||
761fcd9e AA |
1976 | static inline u32 nv_get_empty_tx_slots(struct fe_priv *np) |
1977 | { | |
1978 | return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); | |
1979 | } | |
1980 | ||
a433686c AA |
1981 | static void nv_legacybackoff_reseed(struct net_device *dev) |
1982 | { | |
1983 | u8 __iomem *base = get_hwbase(dev); | |
1984 | u32 reg; | |
1985 | u32 low; | |
1986 | int tx_status = 0; | |
1987 | ||
1988 | reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK; | |
1989 | get_random_bytes(&low, sizeof(low)); | |
1990 | reg |= low & NVREG_SLOTTIME_MASK; | |
1991 | ||
1992 | /* Need to stop tx before change takes effect. | |
1993 | * Caller has already gained np->lock. | |
1994 | */ | |
1995 | tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START; | |
1996 | if (tx_status) | |
1997 | nv_stop_tx(dev); | |
1998 | nv_stop_rx(dev); | |
1999 | writel(reg, base + NvRegSlotTime); | |
2000 | if (tx_status) | |
2001 | nv_start_tx(dev); | |
2002 | nv_start_rx(dev); | |
2003 | } | |
2004 | ||
2005 | /* Gear Backoff Seeds */ | |
2006 | #define BACKOFF_SEEDSET_ROWS 8 | |
2007 | #define BACKOFF_SEEDSET_LFSRS 15 | |
2008 | ||
2009 | /* Known Good seed sets */ | |
2010 | static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
78aea4fc SJ |
2011 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, |
2012 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974}, | |
2013 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | |
2014 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974}, | |
2015 | {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984}, | |
2016 | {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984}, | |
2017 | {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84}, | |
2018 | {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} }; | |
a433686c AA |
2019 | |
2020 | static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
78aea4fc SJ |
2021 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, |
2022 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2023 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397}, | |
2024 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2025 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2026 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2027 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2028 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} }; | |
a433686c AA |
2029 | |
2030 | static void nv_gear_backoff_reseed(struct net_device *dev) | |
2031 | { | |
2032 | u8 __iomem *base = get_hwbase(dev); | |
2033 | u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed; | |
2034 | u32 temp, seedset, combinedSeed; | |
2035 | int i; | |
2036 | ||
2037 | /* Setup seed for free running LFSR */ | |
2038 | /* We are going to read the time stamp counter 3 times | |
2039 | and swizzle bits around to increase randomness */ | |
2040 | get_random_bytes(&miniseed1, sizeof(miniseed1)); | |
2041 | miniseed1 &= 0x0fff; | |
2042 | if (miniseed1 == 0) | |
2043 | miniseed1 = 0xabc; | |
2044 | ||
2045 | get_random_bytes(&miniseed2, sizeof(miniseed2)); | |
2046 | miniseed2 &= 0x0fff; | |
2047 | if (miniseed2 == 0) | |
2048 | miniseed2 = 0xabc; | |
2049 | miniseed2_reversed = | |
2050 | ((miniseed2 & 0xF00) >> 8) | | |
2051 | (miniseed2 & 0x0F0) | | |
2052 | ((miniseed2 & 0x00F) << 8); | |
2053 | ||
2054 | get_random_bytes(&miniseed3, sizeof(miniseed3)); | |
2055 | miniseed3 &= 0x0fff; | |
2056 | if (miniseed3 == 0) | |
2057 | miniseed3 = 0xabc; | |
2058 | miniseed3_reversed = | |
2059 | ((miniseed3 & 0xF00) >> 8) | | |
2060 | (miniseed3 & 0x0F0) | | |
2061 | ((miniseed3 & 0x00F) << 8); | |
2062 | ||
2063 | combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) | | |
2064 | (miniseed2 ^ miniseed3_reversed); | |
2065 | ||
2066 | /* Seeds can not be zero */ | |
2067 | if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0) | |
2068 | combinedSeed |= 0x08; | |
2069 | if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0) | |
2070 | combinedSeed |= 0x8000; | |
2071 | ||
2072 | /* No need to disable tx here */ | |
2073 | temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); | |
2074 | temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK; | |
2075 | temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR; | |
78aea4fc | 2076 | writel(temp, base + NvRegBackOffControl); |
a433686c | 2077 | |
78aea4fc | 2078 | /* Setup seeds for all gear LFSRs. */ |
a433686c AA |
2079 | get_random_bytes(&seedset, sizeof(seedset)); |
2080 | seedset = seedset % BACKOFF_SEEDSET_ROWS; | |
78aea4fc | 2081 | for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) { |
a433686c AA |
2082 | temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT); |
2083 | temp |= main_seedset[seedset][i-1] & 0x3ff; | |
2084 | temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); | |
2085 | writel(temp, base + NvRegBackOffControl); | |
2086 | } | |
2087 | } | |
2088 | ||
1da177e4 LT |
2089 | /* |
2090 | * nv_start_xmit: dev->hard_start_xmit function | |
932ff279 | 2091 | * Called with netif_tx_lock held. |
1da177e4 | 2092 | */ |
61357325 | 2093 | static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 2094 | { |
ac9c1897 | 2095 | struct fe_priv *np = netdev_priv(dev); |
fa45459e | 2096 | u32 tx_flags = 0; |
ac9c1897 AA |
2097 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
2098 | unsigned int fragments = skb_shinfo(skb)->nr_frags; | |
ac9c1897 | 2099 | unsigned int i; |
fa45459e AA |
2100 | u32 offset = 0; |
2101 | u32 bcnt; | |
e743d313 | 2102 | u32 size = skb_headlen(skb); |
fa45459e | 2103 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
761fcd9e | 2104 | u32 empty_slots; |
78aea4fc SJ |
2105 | struct ring_desc *put_tx; |
2106 | struct ring_desc *start_tx; | |
2107 | struct ring_desc *prev_tx; | |
2108 | struct nv_skb_map *prev_tx_ctx; | |
bd6ca637 | 2109 | unsigned long flags; |
fa45459e AA |
2110 | |
2111 | /* add fragments to entries count */ | |
2112 | for (i = 0; i < fragments; i++) { | |
2113 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
2114 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2115 | } | |
ac9c1897 | 2116 | |
001eb84b | 2117 | spin_lock_irqsave(&np->lock, flags); |
761fcd9e | 2118 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2119 | if (unlikely(empty_slots <= entries)) { |
ac9c1897 | 2120 | netif_stop_queue(dev); |
aaa37d2d | 2121 | np->tx_stop = 1; |
bd6ca637 | 2122 | spin_unlock_irqrestore(&np->lock, flags); |
ac9c1897 AA |
2123 | return NETDEV_TX_BUSY; |
2124 | } | |
001eb84b | 2125 | spin_unlock_irqrestore(&np->lock, flags); |
1da177e4 | 2126 | |
86b22b0d | 2127 | start_tx = put_tx = np->put_tx.orig; |
761fcd9e | 2128 | |
fa45459e AA |
2129 | /* setup the header buffer */ |
2130 | do { | |
761fcd9e AA |
2131 | prev_tx = put_tx; |
2132 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 2133 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e | 2134 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
fa45459e | 2135 | PCI_DMA_TODEVICE); |
761fcd9e | 2136 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2137 | np->put_tx_ctx->dma_single = 1; |
86b22b0d AA |
2138 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2139 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2140 | |
fa45459e AA |
2141 | tx_flags = np->tx_flags; |
2142 | offset += bcnt; | |
2143 | size -= bcnt; | |
445583b8 | 2144 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 2145 | put_tx = np->first_tx.orig; |
445583b8 | 2146 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2147 | np->put_tx_ctx = np->first_tx_ctx; |
f82a9352 | 2148 | } while (size); |
fa45459e AA |
2149 | |
2150 | /* setup the fragments */ | |
2151 | for (i = 0; i < fragments; i++) { | |
2152 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2153 | u32 size = frag->size; | |
2154 | offset = 0; | |
2155 | ||
2156 | do { | |
761fcd9e AA |
2157 | prev_tx = put_tx; |
2158 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 2159 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e AA |
2160 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
2161 | PCI_DMA_TODEVICE); | |
2162 | np->put_tx_ctx->dma_len = bcnt; | |
73a37079 | 2163 | np->put_tx_ctx->dma_single = 0; |
86b22b0d AA |
2164 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2165 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2166 | |
fa45459e AA |
2167 | offset += bcnt; |
2168 | size -= bcnt; | |
445583b8 | 2169 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 2170 | put_tx = np->first_tx.orig; |
445583b8 | 2171 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2172 | np->put_tx_ctx = np->first_tx_ctx; |
fa45459e AA |
2173 | } while (size); |
2174 | } | |
ac9c1897 | 2175 | |
fa45459e | 2176 | /* set last fragment flag */ |
86b22b0d | 2177 | prev_tx->flaglen |= cpu_to_le32(tx_flags_extra); |
ac9c1897 | 2178 | |
761fcd9e AA |
2179 | /* save skb in this slot's context area */ |
2180 | prev_tx_ctx->skb = skb; | |
fa45459e | 2181 | |
89114afd | 2182 | if (skb_is_gso(skb)) |
7967168c | 2183 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
ac9c1897 | 2184 | else |
1d39ed56 | 2185 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? |
84fa7933 | 2186 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; |
ac9c1897 | 2187 | |
bd6ca637 | 2188 | spin_lock_irqsave(&np->lock, flags); |
164a86e4 | 2189 | |
fa45459e | 2190 | /* set tx flags */ |
86b22b0d AA |
2191 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2192 | np->put_tx.orig = put_tx; | |
1da177e4 | 2193 | |
bd6ca637 | 2194 | spin_unlock_irqrestore(&np->lock, flags); |
761fcd9e AA |
2195 | |
2196 | dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n", | |
2197 | dev->name, entries, tx_flags_extra); | |
1da177e4 LT |
2198 | { |
2199 | int j; | |
78aea4fc | 2200 | for (j = 0; j < 64; j++) { |
1da177e4 LT |
2201 | if ((j%16) == 0) |
2202 | dprintk("\n%03x:", j); | |
78aea4fc | 2203 | dprintk(" %02x", ((unsigned char *)skb->data)[j]); |
1da177e4 LT |
2204 | } |
2205 | dprintk("\n"); | |
2206 | } | |
2207 | ||
8a4ae7f2 | 2208 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
ac9c1897 | 2209 | return NETDEV_TX_OK; |
1da177e4 LT |
2210 | } |
2211 | ||
61357325 SH |
2212 | static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb, |
2213 | struct net_device *dev) | |
86b22b0d AA |
2214 | { |
2215 | struct fe_priv *np = netdev_priv(dev); | |
2216 | u32 tx_flags = 0; | |
445583b8 | 2217 | u32 tx_flags_extra; |
86b22b0d AA |
2218 | unsigned int fragments = skb_shinfo(skb)->nr_frags; |
2219 | unsigned int i; | |
2220 | u32 offset = 0; | |
2221 | u32 bcnt; | |
e743d313 | 2222 | u32 size = skb_headlen(skb); |
86b22b0d AA |
2223 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
2224 | u32 empty_slots; | |
78aea4fc SJ |
2225 | struct ring_desc_ex *put_tx; |
2226 | struct ring_desc_ex *start_tx; | |
2227 | struct ring_desc_ex *prev_tx; | |
2228 | struct nv_skb_map *prev_tx_ctx; | |
2229 | struct nv_skb_map *start_tx_ctx; | |
bd6ca637 | 2230 | unsigned long flags; |
86b22b0d AA |
2231 | |
2232 | /* add fragments to entries count */ | |
2233 | for (i = 0; i < fragments; i++) { | |
2234 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
2235 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2236 | } | |
2237 | ||
001eb84b | 2238 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2239 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2240 | if (unlikely(empty_slots <= entries)) { |
86b22b0d | 2241 | netif_stop_queue(dev); |
aaa37d2d | 2242 | np->tx_stop = 1; |
bd6ca637 | 2243 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2244 | return NETDEV_TX_BUSY; |
2245 | } | |
001eb84b | 2246 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2247 | |
2248 | start_tx = put_tx = np->put_tx.ex; | |
3b446c3e | 2249 | start_tx_ctx = np->put_tx_ctx; |
86b22b0d AA |
2250 | |
2251 | /* setup the header buffer */ | |
2252 | do { | |
2253 | prev_tx = put_tx; | |
2254 | prev_tx_ctx = np->put_tx_ctx; | |
2255 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2256 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, | |
2257 | PCI_DMA_TODEVICE); | |
2258 | np->put_tx_ctx->dma_len = bcnt; | |
73a37079 | 2259 | np->put_tx_ctx->dma_single = 1; |
5bb7ea26 AV |
2260 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2261 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2262 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 AA |
2263 | |
2264 | tx_flags = NV_TX2_VALID; | |
86b22b0d AA |
2265 | offset += bcnt; |
2266 | size -= bcnt; | |
445583b8 | 2267 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2268 | put_tx = np->first_tx.ex; |
445583b8 | 2269 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2270 | np->put_tx_ctx = np->first_tx_ctx; |
2271 | } while (size); | |
2272 | ||
2273 | /* setup the fragments */ | |
2274 | for (i = 0; i < fragments; i++) { | |
2275 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2276 | u32 size = frag->size; | |
2277 | offset = 0; | |
2278 | ||
2279 | do { | |
2280 | prev_tx = put_tx; | |
2281 | prev_tx_ctx = np->put_tx_ctx; | |
2282 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2283 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, | |
2284 | PCI_DMA_TODEVICE); | |
2285 | np->put_tx_ctx->dma_len = bcnt; | |
73a37079 | 2286 | np->put_tx_ctx->dma_single = 0; |
5bb7ea26 AV |
2287 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2288 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2289 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 | 2290 | |
86b22b0d AA |
2291 | offset += bcnt; |
2292 | size -= bcnt; | |
445583b8 | 2293 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2294 | put_tx = np->first_tx.ex; |
445583b8 | 2295 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2296 | np->put_tx_ctx = np->first_tx_ctx; |
2297 | } while (size); | |
2298 | } | |
2299 | ||
2300 | /* set last fragment flag */ | |
445583b8 | 2301 | prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET); |
86b22b0d AA |
2302 | |
2303 | /* save skb in this slot's context area */ | |
2304 | prev_tx_ctx->skb = skb; | |
2305 | ||
2306 | if (skb_is_gso(skb)) | |
2307 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); | |
2308 | else | |
2309 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? | |
2310 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; | |
2311 | ||
2312 | /* vlan tag */ | |
eab6d18d JG |
2313 | if (vlan_tx_tag_present(skb)) |
2314 | start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | | |
2315 | vlan_tx_tag_get(skb)); | |
2316 | else | |
445583b8 | 2317 | start_tx->txvlan = 0; |
86b22b0d | 2318 | |
bd6ca637 | 2319 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2320 | |
3b446c3e AA |
2321 | if (np->tx_limit) { |
2322 | /* Limit the number of outstanding tx. Setup all fragments, but | |
2323 | * do not set the VALID bit on the first descriptor. Save a pointer | |
2324 | * to that descriptor and also for next skb_map element. | |
2325 | */ | |
2326 | ||
2327 | if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) { | |
2328 | if (!np->tx_change_owner) | |
2329 | np->tx_change_owner = start_tx_ctx; | |
2330 | ||
2331 | /* remove VALID bit */ | |
2332 | tx_flags &= ~NV_TX2_VALID; | |
2333 | start_tx_ctx->first_tx_desc = start_tx; | |
2334 | start_tx_ctx->next_tx_ctx = np->put_tx_ctx; | |
2335 | np->tx_end_flip = np->put_tx_ctx; | |
2336 | } else { | |
2337 | np->tx_pkts_in_progress++; | |
2338 | } | |
2339 | } | |
2340 | ||
86b22b0d | 2341 | /* set tx flags */ |
86b22b0d AA |
2342 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2343 | np->put_tx.ex = put_tx; | |
2344 | ||
bd6ca637 | 2345 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2346 | |
2347 | dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n", | |
2348 | dev->name, entries, tx_flags_extra); | |
2349 | { | |
2350 | int j; | |
78aea4fc | 2351 | for (j = 0; j < 64; j++) { |
86b22b0d AA |
2352 | if ((j%16) == 0) |
2353 | dprintk("\n%03x:", j); | |
78aea4fc | 2354 | dprintk(" %02x", ((unsigned char *)skb->data)[j]); |
86b22b0d AA |
2355 | } |
2356 | dprintk("\n"); | |
2357 | } | |
2358 | ||
86b22b0d | 2359 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
86b22b0d AA |
2360 | return NETDEV_TX_OK; |
2361 | } | |
2362 | ||
3b446c3e AA |
2363 | static inline void nv_tx_flip_ownership(struct net_device *dev) |
2364 | { | |
2365 | struct fe_priv *np = netdev_priv(dev); | |
2366 | ||
2367 | np->tx_pkts_in_progress--; | |
2368 | if (np->tx_change_owner) { | |
30ecce90 AV |
2369 | np->tx_change_owner->first_tx_desc->flaglen |= |
2370 | cpu_to_le32(NV_TX2_VALID); | |
3b446c3e AA |
2371 | np->tx_pkts_in_progress++; |
2372 | ||
2373 | np->tx_change_owner = np->tx_change_owner->next_tx_ctx; | |
2374 | if (np->tx_change_owner == np->tx_end_flip) | |
2375 | np->tx_change_owner = NULL; | |
2376 | ||
2377 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
2378 | } | |
2379 | } | |
2380 | ||
1da177e4 LT |
2381 | /* |
2382 | * nv_tx_done: check for completed packets, release the skbs. | |
2383 | * | |
2384 | * Caller must own np->lock. | |
2385 | */ | |
33912e72 | 2386 | static int nv_tx_done(struct net_device *dev, int limit) |
1da177e4 | 2387 | { |
ac9c1897 | 2388 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2389 | u32 flags; |
33912e72 | 2390 | int tx_work = 0; |
78aea4fc | 2391 | struct ring_desc *orig_get_tx = np->get_tx.orig; |
1da177e4 | 2392 | |
445583b8 | 2393 | while ((np->get_tx.orig != np->put_tx.orig) && |
33912e72 AA |
2394 | !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) && |
2395 | (tx_work < limit)) { | |
1da177e4 | 2396 | |
761fcd9e AA |
2397 | dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n", |
2398 | dev->name, flags); | |
445583b8 | 2399 | |
73a37079 | 2400 | nv_unmap_txskb(np, np->get_tx_ctx); |
445583b8 | 2401 | |
1da177e4 | 2402 | if (np->desc_ver == DESC_VER_1) { |
f82a9352 | 2403 | if (flags & NV_TX_LASTPACKET) { |
445583b8 | 2404 | if (flags & NV_TX_ERROR) { |
f82a9352 | 2405 | if (flags & NV_TX_UNDERFLOW) |
8148ff45 | 2406 | dev->stats.tx_fifo_errors++; |
f82a9352 | 2407 | if (flags & NV_TX_CARRIERLOST) |
8148ff45 | 2408 | dev->stats.tx_carrier_errors++; |
a433686c AA |
2409 | if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK)) |
2410 | nv_legacybackoff_reseed(dev); | |
8148ff45 | 2411 | dev->stats.tx_errors++; |
ac9c1897 | 2412 | } else { |
8148ff45 JG |
2413 | dev->stats.tx_packets++; |
2414 | dev->stats.tx_bytes += np->get_tx_ctx->skb->len; | |
ac9c1897 | 2415 | } |
445583b8 AA |
2416 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2417 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2418 | tx_work++; |
1da177e4 LT |
2419 | } |
2420 | } else { | |
f82a9352 | 2421 | if (flags & NV_TX2_LASTPACKET) { |
445583b8 | 2422 | if (flags & NV_TX2_ERROR) { |
f82a9352 | 2423 | if (flags & NV_TX2_UNDERFLOW) |
8148ff45 | 2424 | dev->stats.tx_fifo_errors++; |
f82a9352 | 2425 | if (flags & NV_TX2_CARRIERLOST) |
8148ff45 | 2426 | dev->stats.tx_carrier_errors++; |
a433686c AA |
2427 | if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) |
2428 | nv_legacybackoff_reseed(dev); | |
8148ff45 | 2429 | dev->stats.tx_errors++; |
ac9c1897 | 2430 | } else { |
8148ff45 JG |
2431 | dev->stats.tx_packets++; |
2432 | dev->stats.tx_bytes += np->get_tx_ctx->skb->len; | |
f3b197ac | 2433 | } |
445583b8 AA |
2434 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2435 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2436 | tx_work++; |
1da177e4 LT |
2437 | } |
2438 | } | |
445583b8 | 2439 | if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) |
86b22b0d | 2440 | np->get_tx.orig = np->first_tx.orig; |
445583b8 | 2441 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2442 | np->get_tx_ctx = np->first_tx_ctx; |
2443 | } | |
445583b8 | 2444 | if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) { |
aaa37d2d | 2445 | np->tx_stop = 0; |
86b22b0d | 2446 | netif_wake_queue(dev); |
aaa37d2d | 2447 | } |
33912e72 | 2448 | return tx_work; |
86b22b0d AA |
2449 | } |
2450 | ||
33912e72 | 2451 | static int nv_tx_done_optimized(struct net_device *dev, int limit) |
86b22b0d AA |
2452 | { |
2453 | struct fe_priv *np = netdev_priv(dev); | |
2454 | u32 flags; | |
33912e72 | 2455 | int tx_work = 0; |
78aea4fc | 2456 | struct ring_desc_ex *orig_get_tx = np->get_tx.ex; |
86b22b0d | 2457 | |
445583b8 | 2458 | while ((np->get_tx.ex != np->put_tx.ex) && |
217d32dc | 2459 | !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) && |
33912e72 | 2460 | (tx_work < limit)) { |
86b22b0d AA |
2461 | |
2462 | dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n", | |
2463 | dev->name, flags); | |
445583b8 | 2464 | |
73a37079 | 2465 | nv_unmap_txskb(np, np->get_tx_ctx); |
445583b8 | 2466 | |
86b22b0d | 2467 | if (flags & NV_TX2_LASTPACKET) { |
21828163 | 2468 | if (!(flags & NV_TX2_ERROR)) |
8148ff45 | 2469 | dev->stats.tx_packets++; |
a433686c AA |
2470 | else { |
2471 | if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) { | |
2472 | if (np->driver_data & DEV_HAS_GEAR_MODE) | |
2473 | nv_gear_backoff_reseed(dev); | |
2474 | else | |
2475 | nv_legacybackoff_reseed(dev); | |
2476 | } | |
2477 | } | |
2478 | ||
445583b8 AA |
2479 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2480 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2481 | tx_work++; |
3b446c3e | 2482 | |
78aea4fc | 2483 | if (np->tx_limit) |
3b446c3e | 2484 | nv_tx_flip_ownership(dev); |
761fcd9e | 2485 | } |
445583b8 | 2486 | if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) |
86b22b0d | 2487 | np->get_tx.ex = np->first_tx.ex; |
445583b8 | 2488 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2489 | np->get_tx_ctx = np->first_tx_ctx; |
1da177e4 | 2490 | } |
445583b8 | 2491 | if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) { |
aaa37d2d | 2492 | np->tx_stop = 0; |
1da177e4 | 2493 | netif_wake_queue(dev); |
aaa37d2d | 2494 | } |
33912e72 | 2495 | return tx_work; |
1da177e4 LT |
2496 | } |
2497 | ||
2498 | /* | |
2499 | * nv_tx_timeout: dev->tx_timeout function | |
932ff279 | 2500 | * Called with netif_tx_lock held. |
1da177e4 LT |
2501 | */ |
2502 | static void nv_tx_timeout(struct net_device *dev) | |
2503 | { | |
ac9c1897 | 2504 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2505 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 2506 | u32 status; |
8f955d7f AA |
2507 | union ring_type put_tx; |
2508 | int saved_tx_limit; | |
d33a73c8 AA |
2509 | |
2510 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
2511 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2512 | else | |
2513 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
1da177e4 | 2514 | |
d33a73c8 | 2515 | printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); |
1da177e4 | 2516 | |
c2dba06d MS |
2517 | { |
2518 | int i; | |
2519 | ||
761fcd9e AA |
2520 | printk(KERN_INFO "%s: Ring at %lx\n", |
2521 | dev->name, (unsigned long)np->ring_addr); | |
c2dba06d | 2522 | printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); |
78aea4fc | 2523 | for (i = 0; i <= np->register_size; i += 32) { |
c2dba06d MS |
2524 | printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
2525 | i, | |
2526 | readl(base + i + 0), readl(base + i + 4), | |
2527 | readl(base + i + 8), readl(base + i + 12), | |
2528 | readl(base + i + 16), readl(base + i + 20), | |
2529 | readl(base + i + 24), readl(base + i + 28)); | |
2530 | } | |
2531 | printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); | |
78aea4fc | 2532 | for (i = 0; i < np->tx_ring_size; i += 4) { |
36b30ea9 | 2533 | if (!nv_optimized(np)) { |
ee73362c | 2534 | printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", |
f3b197ac | 2535 | i, |
f82a9352 SH |
2536 | le32_to_cpu(np->tx_ring.orig[i].buf), |
2537 | le32_to_cpu(np->tx_ring.orig[i].flaglen), | |
2538 | le32_to_cpu(np->tx_ring.orig[i+1].buf), | |
2539 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), | |
2540 | le32_to_cpu(np->tx_ring.orig[i+2].buf), | |
2541 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), | |
2542 | le32_to_cpu(np->tx_ring.orig[i+3].buf), | |
2543 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | |
ee73362c MS |
2544 | } else { |
2545 | printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", | |
f3b197ac | 2546 | i, |
f82a9352 SH |
2547 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), |
2548 | le32_to_cpu(np->tx_ring.ex[i].buflow), | |
2549 | le32_to_cpu(np->tx_ring.ex[i].flaglen), | |
2550 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), | |
2551 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), | |
2552 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), | |
2553 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), | |
2554 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), | |
2555 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), | |
2556 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), | |
2557 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), | |
2558 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | |
ee73362c | 2559 | } |
c2dba06d MS |
2560 | } |
2561 | } | |
2562 | ||
1da177e4 LT |
2563 | spin_lock_irq(&np->lock); |
2564 | ||
2565 | /* 1) stop tx engine */ | |
2566 | nv_stop_tx(dev); | |
2567 | ||
8f955d7f AA |
2568 | /* 2) complete any outstanding tx and do not give HW any limited tx pkts */ |
2569 | saved_tx_limit = np->tx_limit; | |
2570 | np->tx_limit = 0; /* prevent giving HW any limited pkts */ | |
2571 | np->tx_stop = 0; /* prevent waking tx queue */ | |
36b30ea9 | 2572 | if (!nv_optimized(np)) |
33912e72 | 2573 | nv_tx_done(dev, np->tx_ring_size); |
86b22b0d | 2574 | else |
4e16ed1b | 2575 | nv_tx_done_optimized(dev, np->tx_ring_size); |
1da177e4 | 2576 | |
8f955d7f AA |
2577 | /* save current HW postion */ |
2578 | if (np->tx_change_owner) | |
2579 | put_tx.ex = np->tx_change_owner->first_tx_desc; | |
2580 | else | |
2581 | put_tx = np->put_tx; | |
1da177e4 | 2582 | |
8f955d7f AA |
2583 | /* 3) clear all tx state */ |
2584 | nv_drain_tx(dev); | |
2585 | nv_init_tx(dev); | |
2586 | ||
2587 | /* 4) restore state to current HW position */ | |
2588 | np->get_tx = np->put_tx = put_tx; | |
2589 | np->tx_limit = saved_tx_limit; | |
3ba4d093 | 2590 | |
8f955d7f | 2591 | /* 5) restart tx engine */ |
1da177e4 | 2592 | nv_start_tx(dev); |
8f955d7f | 2593 | netif_wake_queue(dev); |
1da177e4 LT |
2594 | spin_unlock_irq(&np->lock); |
2595 | } | |
2596 | ||
22c6d143 MS |
2597 | /* |
2598 | * Called when the nic notices a mismatch between the actual data len on the | |
2599 | * wire and the len indicated in the 802 header | |
2600 | */ | |
2601 | static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |
2602 | { | |
2603 | int hdrlen; /* length of the 802 header */ | |
2604 | int protolen; /* length as stored in the proto field */ | |
2605 | ||
2606 | /* 1) calculate len according to header */ | |
78aea4fc SJ |
2607 | if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { |
2608 | protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto); | |
22c6d143 MS |
2609 | hdrlen = VLAN_HLEN; |
2610 | } else { | |
78aea4fc | 2611 | protolen = ntohs(((struct ethhdr *)packet)->h_proto); |
22c6d143 MS |
2612 | hdrlen = ETH_HLEN; |
2613 | } | |
2614 | dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n", | |
2615 | dev->name, datalen, protolen, hdrlen); | |
2616 | if (protolen > ETH_DATA_LEN) | |
2617 | return datalen; /* Value in proto field not a len, no checks possible */ | |
2618 | ||
2619 | protolen += hdrlen; | |
2620 | /* consistency checks: */ | |
2621 | if (datalen > ETH_ZLEN) { | |
2622 | if (datalen >= protolen) { | |
2623 | /* more data on wire than in 802 header, trim of | |
2624 | * additional data. | |
2625 | */ | |
2626 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | |
2627 | dev->name, protolen); | |
2628 | return protolen; | |
2629 | } else { | |
2630 | /* less data on wire than mentioned in header. | |
2631 | * Discard the packet. | |
2632 | */ | |
2633 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n", | |
2634 | dev->name); | |
2635 | return -1; | |
2636 | } | |
2637 | } else { | |
2638 | /* short packet. Accept only if 802 values are also short */ | |
2639 | if (protolen > ETH_ZLEN) { | |
2640 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n", | |
2641 | dev->name); | |
2642 | return -1; | |
2643 | } | |
2644 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | |
2645 | dev->name, datalen); | |
2646 | return datalen; | |
2647 | } | |
2648 | } | |
2649 | ||
e27cdba5 | 2650 | static int nv_rx_process(struct net_device *dev, int limit) |
1da177e4 | 2651 | { |
ac9c1897 | 2652 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2653 | u32 flags; |
bcb5febb | 2654 | int rx_work = 0; |
b01867cb AA |
2655 | struct sk_buff *skb; |
2656 | int len; | |
1da177e4 | 2657 | |
78aea4fc | 2658 | while ((np->get_rx.orig != np->put_rx.orig) && |
b01867cb | 2659 | !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && |
bcb5febb | 2660 | (rx_work < limit)) { |
1da177e4 | 2661 | |
761fcd9e AA |
2662 | dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n", |
2663 | dev->name, flags); | |
1da177e4 | 2664 | |
1da177e4 LT |
2665 | /* |
2666 | * the packet is for us - immediately tear down the pci mapping. | |
2667 | * TODO: check if a prefetch of the first cacheline improves | |
2668 | * the performance. | |
2669 | */ | |
761fcd9e AA |
2670 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, |
2671 | np->get_rx_ctx->dma_len, | |
1da177e4 | 2672 | PCI_DMA_FROMDEVICE); |
0d63fb32 AA |
2673 | skb = np->get_rx_ctx->skb; |
2674 | np->get_rx_ctx->skb = NULL; | |
1da177e4 LT |
2675 | |
2676 | { | |
2677 | int j; | |
78aea4fc SJ |
2678 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).", flags); |
2679 | for (j = 0; j < 64; j++) { | |
1da177e4 LT |
2680 | if ((j%16) == 0) |
2681 | dprintk("\n%03x:", j); | |
78aea4fc | 2682 | dprintk(" %02x", ((unsigned char *)skb->data)[j]); |
1da177e4 LT |
2683 | } |
2684 | dprintk("\n"); | |
2685 | } | |
2686 | /* look at what we actually got: */ | |
2687 | if (np->desc_ver == DESC_VER_1) { | |
b01867cb AA |
2688 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { |
2689 | len = flags & LEN_MASK_V1; | |
2690 | if (unlikely(flags & NV_RX_ERROR)) { | |
1ef6841b | 2691 | if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) { |
b01867cb AA |
2692 | len = nv_getlen(dev, skb->data, len); |
2693 | if (len < 0) { | |
8148ff45 | 2694 | dev->stats.rx_errors++; |
b01867cb AA |
2695 | dev_kfree_skb(skb); |
2696 | goto next_pkt; | |
2697 | } | |
2698 | } | |
2699 | /* framing errors are soft errors */ | |
1ef6841b | 2700 | else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) { |
78aea4fc | 2701 | if (flags & NV_RX_SUBSTRACT1) |
b01867cb | 2702 | len--; |
b01867cb AA |
2703 | } |
2704 | /* the rest are hard errors */ | |
2705 | else { | |
2706 | if (flags & NV_RX_MISSEDFRAME) | |
8148ff45 | 2707 | dev->stats.rx_missed_errors++; |
b01867cb | 2708 | if (flags & NV_RX_CRCERR) |
8148ff45 | 2709 | dev->stats.rx_crc_errors++; |
b01867cb | 2710 | if (flags & NV_RX_OVERFLOW) |
8148ff45 JG |
2711 | dev->stats.rx_over_errors++; |
2712 | dev->stats.rx_errors++; | |
0d63fb32 | 2713 | dev_kfree_skb(skb); |
a971c324 AA |
2714 | goto next_pkt; |
2715 | } | |
2716 | } | |
b01867cb | 2717 | } else { |
0d63fb32 | 2718 | dev_kfree_skb(skb); |
1da177e4 | 2719 | goto next_pkt; |
0d63fb32 | 2720 | } |
b01867cb AA |
2721 | } else { |
2722 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | |
2723 | len = flags & LEN_MASK_V2; | |
2724 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2725 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2726 | len = nv_getlen(dev, skb->data, len); |
2727 | if (len < 0) { | |
8148ff45 | 2728 | dev->stats.rx_errors++; |
b01867cb AA |
2729 | dev_kfree_skb(skb); |
2730 | goto next_pkt; | |
2731 | } | |
2732 | } | |
2733 | /* framing errors are soft errors */ | |
1ef6841b | 2734 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
78aea4fc | 2735 | if (flags & NV_RX2_SUBSTRACT1) |
b01867cb | 2736 | len--; |
b01867cb AA |
2737 | } |
2738 | /* the rest are hard errors */ | |
2739 | else { | |
2740 | if (flags & NV_RX2_CRCERR) | |
8148ff45 | 2741 | dev->stats.rx_crc_errors++; |
b01867cb | 2742 | if (flags & NV_RX2_OVERFLOW) |
8148ff45 JG |
2743 | dev->stats.rx_over_errors++; |
2744 | dev->stats.rx_errors++; | |
0d63fb32 | 2745 | dev_kfree_skb(skb); |
a971c324 AA |
2746 | goto next_pkt; |
2747 | } | |
2748 | } | |
bfaffe8f AA |
2749 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2750 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
0d63fb32 | 2751 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2752 | } else { |
2753 | dev_kfree_skb(skb); | |
2754 | goto next_pkt; | |
1da177e4 LT |
2755 | } |
2756 | } | |
2757 | /* got a valid packet - forward it to the network core */ | |
1da177e4 LT |
2758 | skb_put(skb, len); |
2759 | skb->protocol = eth_type_trans(skb, dev); | |
761fcd9e AA |
2760 | dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n", |
2761 | dev->name, len, skb->protocol); | |
53f224cc | 2762 | napi_gro_receive(&np->napi, skb); |
8148ff45 JG |
2763 | dev->stats.rx_packets++; |
2764 | dev->stats.rx_bytes += len; | |
1da177e4 | 2765 | next_pkt: |
b01867cb | 2766 | if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 2767 | np->get_rx.orig = np->first_rx.orig; |
b01867cb | 2768 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 2769 | np->get_rx_ctx = np->first_rx_ctx; |
bcb5febb IM |
2770 | |
2771 | rx_work++; | |
86b22b0d AA |
2772 | } |
2773 | ||
bcb5febb | 2774 | return rx_work; |
86b22b0d AA |
2775 | } |
2776 | ||
2777 | static int nv_rx_process_optimized(struct net_device *dev, int limit) | |
2778 | { | |
2779 | struct fe_priv *np = netdev_priv(dev); | |
2780 | u32 flags; | |
2781 | u32 vlanflags = 0; | |
c1b7151a | 2782 | int rx_work = 0; |
b01867cb AA |
2783 | struct sk_buff *skb; |
2784 | int len; | |
86b22b0d | 2785 | |
78aea4fc | 2786 | while ((np->get_rx.ex != np->put_rx.ex) && |
b01867cb | 2787 | !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && |
c1b7151a | 2788 | (rx_work < limit)) { |
86b22b0d AA |
2789 | |
2790 | dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n", | |
2791 | dev->name, flags); | |
2792 | ||
86b22b0d AA |
2793 | /* |
2794 | * the packet is for us - immediately tear down the pci mapping. | |
2795 | * TODO: check if a prefetch of the first cacheline improves | |
2796 | * the performance. | |
2797 | */ | |
2798 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, | |
2799 | np->get_rx_ctx->dma_len, | |
2800 | PCI_DMA_FROMDEVICE); | |
2801 | skb = np->get_rx_ctx->skb; | |
2802 | np->get_rx_ctx->skb = NULL; | |
2803 | ||
2804 | { | |
2805 | int j; | |
78aea4fc SJ |
2806 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).", flags); |
2807 | for (j = 0; j < 64; j++) { | |
86b22b0d AA |
2808 | if ((j%16) == 0) |
2809 | dprintk("\n%03x:", j); | |
78aea4fc | 2810 | dprintk(" %02x", ((unsigned char *)skb->data)[j]); |
86b22b0d AA |
2811 | } |
2812 | dprintk("\n"); | |
761fcd9e | 2813 | } |
86b22b0d | 2814 | /* look at what we actually got: */ |
b01867cb AA |
2815 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
2816 | len = flags & LEN_MASK_V2; | |
2817 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2818 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2819 | len = nv_getlen(dev, skb->data, len); |
2820 | if (len < 0) { | |
b01867cb AA |
2821 | dev_kfree_skb(skb); |
2822 | goto next_pkt; | |
2823 | } | |
2824 | } | |
2825 | /* framing errors are soft errors */ | |
1ef6841b | 2826 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
78aea4fc | 2827 | if (flags & NV_RX2_SUBSTRACT1) |
b01867cb | 2828 | len--; |
b01867cb AA |
2829 | } |
2830 | /* the rest are hard errors */ | |
2831 | else { | |
86b22b0d AA |
2832 | dev_kfree_skb(skb); |
2833 | goto next_pkt; | |
2834 | } | |
2835 | } | |
b01867cb | 2836 | |
bfaffe8f AA |
2837 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2838 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
86b22b0d | 2839 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2840 | |
2841 | /* got a valid packet - forward it to the network core */ | |
2842 | skb_put(skb, len); | |
2843 | skb->protocol = eth_type_trans(skb, dev); | |
2844 | prefetch(skb->data); | |
2845 | ||
2846 | dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n", | |
2847 | dev->name, len, skb->protocol); | |
2848 | ||
2849 | if (likely(!np->vlangrp)) { | |
53f224cc | 2850 | napi_gro_receive(&np->napi, skb); |
b01867cb AA |
2851 | } else { |
2852 | vlanflags = le32_to_cpu(np->get_rx.ex->buflow); | |
2853 | if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) { | |
53f224cc TH |
2854 | vlan_gro_receive(&np->napi, np->vlangrp, |
2855 | vlanflags & NV_RX3_VLAN_TAG_MASK, skb); | |
b01867cb | 2856 | } else { |
53f224cc | 2857 | napi_gro_receive(&np->napi, skb); |
b01867cb AA |
2858 | } |
2859 | } | |
2860 | ||
8148ff45 JG |
2861 | dev->stats.rx_packets++; |
2862 | dev->stats.rx_bytes += len; | |
b01867cb AA |
2863 | } else { |
2864 | dev_kfree_skb(skb); | |
2865 | } | |
86b22b0d | 2866 | next_pkt: |
b01867cb | 2867 | if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 2868 | np->get_rx.ex = np->first_rx.ex; |
b01867cb | 2869 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
761fcd9e | 2870 | np->get_rx_ctx = np->first_rx_ctx; |
c1b7151a IM |
2871 | |
2872 | rx_work++; | |
1da177e4 | 2873 | } |
e27cdba5 | 2874 | |
c1b7151a | 2875 | return rx_work; |
1da177e4 LT |
2876 | } |
2877 | ||
d81c0983 MS |
2878 | static void set_bufsize(struct net_device *dev) |
2879 | { | |
2880 | struct fe_priv *np = netdev_priv(dev); | |
2881 | ||
2882 | if (dev->mtu <= ETH_DATA_LEN) | |
2883 | np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; | |
2884 | else | |
2885 | np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; | |
2886 | } | |
2887 | ||
1da177e4 LT |
2888 | /* |
2889 | * nv_change_mtu: dev->change_mtu function | |
2890 | * Called with dev_base_lock held for read. | |
2891 | */ | |
2892 | static int nv_change_mtu(struct net_device *dev, int new_mtu) | |
2893 | { | |
ac9c1897 | 2894 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 MS |
2895 | int old_mtu; |
2896 | ||
2897 | if (new_mtu < 64 || new_mtu > np->pkt_limit) | |
1da177e4 | 2898 | return -EINVAL; |
d81c0983 MS |
2899 | |
2900 | old_mtu = dev->mtu; | |
1da177e4 | 2901 | dev->mtu = new_mtu; |
d81c0983 MS |
2902 | |
2903 | /* return early if the buffer sizes will not change */ | |
2904 | if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) | |
2905 | return 0; | |
2906 | if (old_mtu == new_mtu) | |
2907 | return 0; | |
2908 | ||
2909 | /* synchronized against open : rtnl_lock() held by caller */ | |
2910 | if (netif_running(dev)) { | |
25097d4b | 2911 | u8 __iomem *base = get_hwbase(dev); |
d81c0983 MS |
2912 | /* |
2913 | * It seems that the nic preloads valid ring entries into an | |
2914 | * internal buffer. The procedure for flushing everything is | |
2915 | * guessed, there is probably a simpler approach. | |
2916 | * Changing the MTU is a rare event, it shouldn't matter. | |
2917 | */ | |
84b3932b | 2918 | nv_disable_irq(dev); |
08d93575 | 2919 | nv_napi_disable(dev); |
932ff279 | 2920 | netif_tx_lock_bh(dev); |
e308a5d8 | 2921 | netif_addr_lock(dev); |
d81c0983 MS |
2922 | spin_lock(&np->lock); |
2923 | /* stop engines */ | |
36b30ea9 | 2924 | nv_stop_rxtx(dev); |
d81c0983 MS |
2925 | nv_txrx_reset(dev); |
2926 | /* drain rx queue */ | |
36b30ea9 | 2927 | nv_drain_rxtx(dev); |
d81c0983 | 2928 | /* reinit driver view of the rx queue */ |
d81c0983 | 2929 | set_bufsize(dev); |
eafa59f6 | 2930 | if (nv_init_ring(dev)) { |
d81c0983 MS |
2931 | if (!np->in_shutdown) |
2932 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
2933 | } | |
2934 | /* reinit nic view of the rx queue */ | |
2935 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
0832b25a | 2936 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
78aea4fc | 2937 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
d81c0983 MS |
2938 | base + NvRegRingSizes); |
2939 | pci_push(base); | |
8a4ae7f2 | 2940 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
d81c0983 MS |
2941 | pci_push(base); |
2942 | ||
2943 | /* restart rx engine */ | |
36b30ea9 | 2944 | nv_start_rxtx(dev); |
d81c0983 | 2945 | spin_unlock(&np->lock); |
e308a5d8 | 2946 | netif_addr_unlock(dev); |
932ff279 | 2947 | netif_tx_unlock_bh(dev); |
08d93575 | 2948 | nv_napi_enable(dev); |
84b3932b | 2949 | nv_enable_irq(dev); |
d81c0983 | 2950 | } |
1da177e4 LT |
2951 | return 0; |
2952 | } | |
2953 | ||
72b31782 MS |
2954 | static void nv_copy_mac_to_hw(struct net_device *dev) |
2955 | { | |
25097d4b | 2956 | u8 __iomem *base = get_hwbase(dev); |
72b31782 MS |
2957 | u32 mac[2]; |
2958 | ||
2959 | mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + | |
2960 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); | |
2961 | mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); | |
2962 | ||
2963 | writel(mac[0], base + NvRegMacAddrA); | |
2964 | writel(mac[1], base + NvRegMacAddrB); | |
2965 | } | |
2966 | ||
2967 | /* | |
2968 | * nv_set_mac_address: dev->set_mac_address function | |
2969 | * Called with rtnl_lock() held. | |
2970 | */ | |
2971 | static int nv_set_mac_address(struct net_device *dev, void *addr) | |
2972 | { | |
ac9c1897 | 2973 | struct fe_priv *np = netdev_priv(dev); |
78aea4fc | 2974 | struct sockaddr *macaddr = (struct sockaddr *)addr; |
72b31782 | 2975 | |
f82a9352 | 2976 | if (!is_valid_ether_addr(macaddr->sa_data)) |
72b31782 MS |
2977 | return -EADDRNOTAVAIL; |
2978 | ||
2979 | /* synchronized against open : rtnl_lock() held by caller */ | |
2980 | memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); | |
2981 | ||
2982 | if (netif_running(dev)) { | |
932ff279 | 2983 | netif_tx_lock_bh(dev); |
e308a5d8 | 2984 | netif_addr_lock(dev); |
72b31782 MS |
2985 | spin_lock_irq(&np->lock); |
2986 | ||
2987 | /* stop rx engine */ | |
2988 | nv_stop_rx(dev); | |
2989 | ||
2990 | /* set mac address */ | |
2991 | nv_copy_mac_to_hw(dev); | |
2992 | ||
2993 | /* restart rx engine */ | |
2994 | nv_start_rx(dev); | |
2995 | spin_unlock_irq(&np->lock); | |
e308a5d8 | 2996 | netif_addr_unlock(dev); |
932ff279 | 2997 | netif_tx_unlock_bh(dev); |
72b31782 MS |
2998 | } else { |
2999 | nv_copy_mac_to_hw(dev); | |
3000 | } | |
3001 | return 0; | |
3002 | } | |
3003 | ||
1da177e4 LT |
3004 | /* |
3005 | * nv_set_multicast: dev->set_multicast function | |
932ff279 | 3006 | * Called with netif_tx_lock held. |
1da177e4 LT |
3007 | */ |
3008 | static void nv_set_multicast(struct net_device *dev) | |
3009 | { | |
ac9c1897 | 3010 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3011 | u8 __iomem *base = get_hwbase(dev); |
3012 | u32 addr[2]; | |
3013 | u32 mask[2]; | |
b6d0773f | 3014 | u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; |
1da177e4 LT |
3015 | |
3016 | memset(addr, 0, sizeof(addr)); | |
3017 | memset(mask, 0, sizeof(mask)); | |
3018 | ||
3019 | if (dev->flags & IFF_PROMISC) { | |
b6d0773f | 3020 | pff |= NVREG_PFF_PROMISC; |
1da177e4 | 3021 | } else { |
b6d0773f | 3022 | pff |= NVREG_PFF_MYADDR; |
1da177e4 | 3023 | |
48e2f183 | 3024 | if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) { |
1da177e4 LT |
3025 | u32 alwaysOff[2]; |
3026 | u32 alwaysOn[2]; | |
3027 | ||
3028 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; | |
3029 | if (dev->flags & IFF_ALLMULTI) { | |
3030 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; | |
3031 | } else { | |
22bedad3 | 3032 | struct netdev_hw_addr *ha; |
1da177e4 | 3033 | |
22bedad3 JP |
3034 | netdev_for_each_mc_addr(ha, dev) { |
3035 | unsigned char *addr = ha->addr; | |
1da177e4 | 3036 | u32 a, b; |
22bedad3 JP |
3037 | |
3038 | a = le32_to_cpu(*(__le32 *) addr); | |
3039 | b = le16_to_cpu(*(__le16 *) (&addr[4])); | |
1da177e4 LT |
3040 | alwaysOn[0] &= a; |
3041 | alwaysOff[0] &= ~a; | |
3042 | alwaysOn[1] &= b; | |
3043 | alwaysOff[1] &= ~b; | |
1da177e4 LT |
3044 | } |
3045 | } | |
3046 | addr[0] = alwaysOn[0]; | |
3047 | addr[1] = alwaysOn[1]; | |
3048 | mask[0] = alwaysOn[0] | alwaysOff[0]; | |
3049 | mask[1] = alwaysOn[1] | alwaysOff[1]; | |
bb9a4fd1 AA |
3050 | } else { |
3051 | mask[0] = NVREG_MCASTMASKA_NONE; | |
3052 | mask[1] = NVREG_MCASTMASKB_NONE; | |
1da177e4 LT |
3053 | } |
3054 | } | |
3055 | addr[0] |= NVREG_MCASTADDRA_FORCE; | |
3056 | pff |= NVREG_PFF_ALWAYS; | |
3057 | spin_lock_irq(&np->lock); | |
3058 | nv_stop_rx(dev); | |
3059 | writel(addr[0], base + NvRegMulticastAddrA); | |
3060 | writel(addr[1], base + NvRegMulticastAddrB); | |
3061 | writel(mask[0], base + NvRegMulticastMaskA); | |
3062 | writel(mask[1], base + NvRegMulticastMaskB); | |
3063 | writel(pff, base + NvRegPacketFilterFlags); | |
3064 | dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n", | |
3065 | dev->name); | |
3066 | nv_start_rx(dev); | |
3067 | spin_unlock_irq(&np->lock); | |
3068 | } | |
3069 | ||
c7985051 | 3070 | static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
b6d0773f AA |
3071 | { |
3072 | struct fe_priv *np = netdev_priv(dev); | |
3073 | u8 __iomem *base = get_hwbase(dev); | |
3074 | ||
3075 | np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); | |
3076 | ||
3077 | if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { | |
3078 | u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; | |
3079 | if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) { | |
3080 | writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); | |
3081 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3082 | } else { | |
3083 | writel(pff, base + NvRegPacketFilterFlags); | |
3084 | } | |
3085 | } | |
3086 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { | |
3087 | u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; | |
3088 | if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) { | |
5289b4c4 AA |
3089 | u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; |
3090 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) | |
3091 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; | |
9a33e883 | 3092 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) { |
5289b4c4 | 3093 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; |
9a33e883 AA |
3094 | /* limit the number of tx pause frames to a default of 8 */ |
3095 | writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit); | |
3096 | } | |
5289b4c4 | 3097 | writel(pause_enable, base + NvRegTxPauseFrame); |
b6d0773f AA |
3098 | writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); |
3099 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3100 | } else { | |
3101 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
3102 | writel(regmisc, base + NvRegMisc1); | |
3103 | } | |
3104 | } | |
3105 | } | |
3106 | ||
4ea7f299 AA |
3107 | /** |
3108 | * nv_update_linkspeed: Setup the MAC according to the link partner | |
3109 | * @dev: Network device to be configured | |
3110 | * | |
3111 | * The function queries the PHY and checks if there is a link partner. | |
3112 | * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is | |
3113 | * set to 10 MBit HD. | |
3114 | * | |
3115 | * The function returns 0 if there is no link partner and 1 if there is | |
3116 | * a good link partner. | |
3117 | */ | |
1da177e4 LT |
3118 | static int nv_update_linkspeed(struct net_device *dev) |
3119 | { | |
ac9c1897 | 3120 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3121 | u8 __iomem *base = get_hwbase(dev); |
eb91f61b AA |
3122 | int adv = 0; |
3123 | int lpa = 0; | |
3124 | int adv_lpa, adv_pause, lpa_pause; | |
1da177e4 LT |
3125 | int newls = np->linkspeed; |
3126 | int newdup = np->duplex; | |
3127 | int mii_status; | |
3128 | int retval = 0; | |
9744e218 | 3129 | u32 control_1000, status_1000, phyreg, pause_flags, txreg; |
b2976d23 | 3130 | u32 txrxFlags = 0; |
fd9b558c | 3131 | u32 phy_exp; |
1da177e4 LT |
3132 | |
3133 | /* BMSR_LSTATUS is latched, read it twice: | |
3134 | * we want the current value. | |
3135 | */ | |
3136 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3137 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3138 | ||
3139 | if (!(mii_status & BMSR_LSTATUS)) { | |
3140 | dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n", | |
3141 | dev->name); | |
3142 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3143 | newdup = 0; | |
3144 | retval = 0; | |
3145 | goto set_speed; | |
3146 | } | |
3147 | ||
3148 | if (np->autoneg == 0) { | |
3149 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", | |
3150 | dev->name, np->fixed_mode); | |
3151 | if (np->fixed_mode & LPA_100FULL) { | |
3152 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3153 | newdup = 1; | |
3154 | } else if (np->fixed_mode & LPA_100HALF) { | |
3155 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3156 | newdup = 0; | |
3157 | } else if (np->fixed_mode & LPA_10FULL) { | |
3158 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3159 | newdup = 1; | |
3160 | } else { | |
3161 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3162 | newdup = 0; | |
3163 | } | |
3164 | retval = 1; | |
3165 | goto set_speed; | |
3166 | } | |
3167 | /* check auto negotiation is complete */ | |
3168 | if (!(mii_status & BMSR_ANEGCOMPLETE)) { | |
3169 | /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ | |
3170 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3171 | newdup = 0; | |
3172 | retval = 0; | |
3173 | dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name); | |
3174 | goto set_speed; | |
3175 | } | |
3176 | ||
b6d0773f AA |
3177 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
3178 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); | |
3179 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", | |
3180 | dev->name, adv, lpa); | |
3181 | ||
1da177e4 LT |
3182 | retval = 1; |
3183 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b AA |
3184 | control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
3185 | status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); | |
1da177e4 LT |
3186 | |
3187 | if ((control_1000 & ADVERTISE_1000FULL) && | |
3188 | (status_1000 & LPA_1000FULL)) { | |
3189 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n", | |
3190 | dev->name); | |
3191 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; | |
3192 | newdup = 1; | |
3193 | goto set_speed; | |
3194 | } | |
3195 | } | |
3196 | ||
1da177e4 | 3197 | /* FIXME: handle parallel detection properly */ |
eb91f61b AA |
3198 | adv_lpa = lpa & adv; |
3199 | if (adv_lpa & LPA_100FULL) { | |
1da177e4 LT |
3200 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3201 | newdup = 1; | |
eb91f61b | 3202 | } else if (adv_lpa & LPA_100HALF) { |
1da177e4 LT |
3203 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3204 | newdup = 0; | |
eb91f61b | 3205 | } else if (adv_lpa & LPA_10FULL) { |
1da177e4 LT |
3206 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3207 | newdup = 1; | |
eb91f61b | 3208 | } else if (adv_lpa & LPA_10HALF) { |
1da177e4 LT |
3209 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3210 | newdup = 0; | |
3211 | } else { | |
eb91f61b | 3212 | dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa); |
1da177e4 LT |
3213 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3214 | newdup = 0; | |
3215 | } | |
3216 | ||
3217 | set_speed: | |
3218 | if (np->duplex == newdup && np->linkspeed == newls) | |
3219 | return retval; | |
3220 | ||
3221 | dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n", | |
3222 | dev->name, np->linkspeed, np->duplex, newls, newdup); | |
3223 | ||
3224 | np->duplex = newdup; | |
3225 | np->linkspeed = newls; | |
3226 | ||
b2976d23 AA |
3227 | /* The transmitter and receiver must be restarted for safe update */ |
3228 | if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) { | |
3229 | txrxFlags |= NV_RESTART_TX; | |
3230 | nv_stop_tx(dev); | |
3231 | } | |
3232 | if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { | |
3233 | txrxFlags |= NV_RESTART_RX; | |
3234 | nv_stop_rx(dev); | |
3235 | } | |
3236 | ||
1da177e4 | 3237 | if (np->gigabit == PHY_GIGABIT) { |
a433686c | 3238 | phyreg = readl(base + NvRegSlotTime); |
1da177e4 | 3239 | phyreg &= ~(0x3FF00); |
a433686c AA |
3240 | if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) || |
3241 | ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)) | |
3242 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
1da177e4 | 3243 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
a433686c AA |
3244 | phyreg |= NVREG_SLOTTIME_1000_FULL; |
3245 | writel(phyreg, base + NvRegSlotTime); | |
1da177e4 LT |
3246 | } |
3247 | ||
3248 | phyreg = readl(base + NvRegPhyInterface); | |
3249 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
3250 | if (np->duplex == 0) | |
3251 | phyreg |= PHY_HALF; | |
3252 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
3253 | phyreg |= PHY_100; | |
3254 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3255 | phyreg |= PHY_1000; | |
3256 | writel(phyreg, base + NvRegPhyInterface); | |
3257 | ||
fd9b558c | 3258 | phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ |
9744e218 | 3259 | if (phyreg & PHY_RGMII) { |
fd9b558c | 3260 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) { |
9744e218 | 3261 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; |
fd9b558c AA |
3262 | } else { |
3263 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) { | |
3264 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10) | |
3265 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10; | |
3266 | else | |
3267 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100; | |
3268 | } else { | |
3269 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | |
3270 | } | |
3271 | } | |
9744e218 | 3272 | } else { |
fd9b558c AA |
3273 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) |
3274 | txreg = NVREG_TX_DEFERRAL_MII_STRETCH; | |
3275 | else | |
3276 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | |
9744e218 AA |
3277 | } |
3278 | writel(txreg, base + NvRegTxDeferral); | |
3279 | ||
95d161cb AA |
3280 | if (np->desc_ver == DESC_VER_1) { |
3281 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | |
3282 | } else { | |
3283 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3284 | txreg = NVREG_TX_WM_DESC2_3_1000; | |
3285 | else | |
3286 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | |
3287 | } | |
3288 | writel(txreg, base + NvRegTxWatermark); | |
3289 | ||
78aea4fc | 3290 | writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), |
1da177e4 LT |
3291 | base + NvRegMisc1); |
3292 | pci_push(base); | |
3293 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
3294 | pci_push(base); | |
3295 | ||
b6d0773f AA |
3296 | pause_flags = 0; |
3297 | /* setup pause frame */ | |
eb91f61b | 3298 | if (np->duplex != 0) { |
b6d0773f | 3299 | if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { |
78aea4fc SJ |
3300 | adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
3301 | lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM); | |
b6d0773f AA |
3302 | |
3303 | switch (adv_pause) { | |
f82a9352 | 3304 | case ADVERTISE_PAUSE_CAP: |
b6d0773f AA |
3305 | if (lpa_pause & LPA_PAUSE_CAP) { |
3306 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3307 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3308 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3309 | } | |
3310 | break; | |
f82a9352 | 3311 | case ADVERTISE_PAUSE_ASYM: |
78aea4fc | 3312 | if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM)) |
b6d0773f | 3313 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
b6d0773f | 3314 | break; |
78aea4fc SJ |
3315 | case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM: |
3316 | if (lpa_pause & LPA_PAUSE_CAP) { | |
b6d0773f AA |
3317 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
3318 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3319 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3320 | } | |
3321 | if (lpa_pause == LPA_PAUSE_ASYM) | |
b6d0773f | 3322 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
b6d0773f | 3323 | break; |
f3b197ac | 3324 | } |
eb91f61b | 3325 | } else { |
b6d0773f | 3326 | pause_flags = np->pause_flags; |
eb91f61b AA |
3327 | } |
3328 | } | |
b6d0773f | 3329 | nv_update_pause(dev, pause_flags); |
eb91f61b | 3330 | |
b2976d23 AA |
3331 | if (txrxFlags & NV_RESTART_TX) |
3332 | nv_start_tx(dev); | |
3333 | if (txrxFlags & NV_RESTART_RX) | |
3334 | nv_start_rx(dev); | |
3335 | ||
1da177e4 LT |
3336 | return retval; |
3337 | } | |
3338 | ||
3339 | static void nv_linkchange(struct net_device *dev) | |
3340 | { | |
3341 | if (nv_update_linkspeed(dev)) { | |
4ea7f299 | 3342 | if (!netif_carrier_ok(dev)) { |
1da177e4 LT |
3343 | netif_carrier_on(dev); |
3344 | printk(KERN_INFO "%s: link up.\n", dev->name); | |
88d7d8b0 | 3345 | nv_txrx_gate(dev, false); |
4ea7f299 | 3346 | nv_start_rx(dev); |
1da177e4 | 3347 | } |
1da177e4 LT |
3348 | } else { |
3349 | if (netif_carrier_ok(dev)) { | |
3350 | netif_carrier_off(dev); | |
3351 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
88d7d8b0 | 3352 | nv_txrx_gate(dev, true); |
1da177e4 LT |
3353 | nv_stop_rx(dev); |
3354 | } | |
3355 | } | |
3356 | } | |
3357 | ||
3358 | static void nv_link_irq(struct net_device *dev) | |
3359 | { | |
3360 | u8 __iomem *base = get_hwbase(dev); | |
3361 | u32 miistat; | |
3362 | ||
3363 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 3364 | writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); |
1da177e4 LT |
3365 | dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat); |
3366 | ||
3367 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) | |
3368 | nv_linkchange(dev); | |
3369 | dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name); | |
3370 | } | |
3371 | ||
4db0ee17 AA |
3372 | static void nv_msi_workaround(struct fe_priv *np) |
3373 | { | |
3374 | ||
3375 | /* Need to toggle the msi irq mask within the ethernet device, | |
3376 | * otherwise, future interrupts will not be detected. | |
3377 | */ | |
3378 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3379 | u8 __iomem *base = np->base; | |
3380 | ||
3381 | writel(0, base + NvRegMSIIrqMask); | |
3382 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3383 | } | |
3384 | } | |
3385 | ||
4145ade2 AA |
3386 | static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work) |
3387 | { | |
3388 | struct fe_priv *np = netdev_priv(dev); | |
3389 | ||
3390 | if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) { | |
3391 | if (total_work > NV_DYNAMIC_THRESHOLD) { | |
3392 | /* transition to poll based interrupts */ | |
3393 | np->quiet_count = 0; | |
3394 | if (np->irqmask != NVREG_IRQMASK_CPU) { | |
3395 | np->irqmask = NVREG_IRQMASK_CPU; | |
3396 | return 1; | |
3397 | } | |
3398 | } else { | |
3399 | if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) { | |
3400 | np->quiet_count++; | |
3401 | } else { | |
3402 | /* reached a period of low activity, switch | |
3403 | to per tx/rx packet interrupts */ | |
3404 | if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { | |
3405 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
3406 | return 1; | |
3407 | } | |
3408 | } | |
3409 | } | |
3410 | } | |
3411 | return 0; | |
3412 | } | |
3413 | ||
7d12e780 | 3414 | static irqreturn_t nv_nic_irq(int foo, void *data) |
1da177e4 LT |
3415 | { |
3416 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3417 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3418 | u8 __iomem *base = get_hwbase(dev); |
1da177e4 LT |
3419 | |
3420 | dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name); | |
3421 | ||
b67874ac AA |
3422 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3423 | np->events = readl(base + NvRegIrqStatus); | |
1b2bb76f | 3424 | writel(np->events, base + NvRegIrqStatus); |
b67874ac AA |
3425 | } else { |
3426 | np->events = readl(base + NvRegMSIXIrqStatus); | |
1b2bb76f | 3427 | writel(np->events, base + NvRegMSIXIrqStatus); |
b67874ac AA |
3428 | } |
3429 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events); | |
3430 | if (!(np->events & np->irqmask)) | |
3431 | return IRQ_NONE; | |
1da177e4 | 3432 | |
b67874ac | 3433 | nv_msi_workaround(np); |
4db0ee17 | 3434 | |
78c29bd9 ED |
3435 | if (napi_schedule_prep(&np->napi)) { |
3436 | /* | |
3437 | * Disable further irq's (msix not enabled with napi) | |
3438 | */ | |
3439 | writel(0, base + NvRegIrqMask); | |
3440 | __napi_schedule(&np->napi); | |
3441 | } | |
f0734ab6 | 3442 | |
1da177e4 LT |
3443 | dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name); |
3444 | ||
b67874ac | 3445 | return IRQ_HANDLED; |
1da177e4 LT |
3446 | } |
3447 | ||
f0734ab6 AA |
3448 | /** |
3449 | * All _optimized functions are used to help increase performance | |
3450 | * (reduce CPU and increase throughput). They use descripter version 3, | |
3451 | * compiler directives, and reduce memory accesses. | |
3452 | */ | |
86b22b0d AA |
3453 | static irqreturn_t nv_nic_irq_optimized(int foo, void *data) |
3454 | { | |
3455 | struct net_device *dev = (struct net_device *) data; | |
3456 | struct fe_priv *np = netdev_priv(dev); | |
3457 | u8 __iomem *base = get_hwbase(dev); | |
86b22b0d AA |
3458 | |
3459 | dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name); | |
3460 | ||
b67874ac AA |
3461 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3462 | np->events = readl(base + NvRegIrqStatus); | |
1b2bb76f | 3463 | writel(np->events, base + NvRegIrqStatus); |
b67874ac AA |
3464 | } else { |
3465 | np->events = readl(base + NvRegMSIXIrqStatus); | |
1b2bb76f | 3466 | writel(np->events, base + NvRegMSIXIrqStatus); |
b67874ac AA |
3467 | } |
3468 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events); | |
3469 | if (!(np->events & np->irqmask)) | |
3470 | return IRQ_NONE; | |
86b22b0d | 3471 | |
b67874ac | 3472 | nv_msi_workaround(np); |
4db0ee17 | 3473 | |
78c29bd9 ED |
3474 | if (napi_schedule_prep(&np->napi)) { |
3475 | /* | |
3476 | * Disable further irq's (msix not enabled with napi) | |
3477 | */ | |
3478 | writel(0, base + NvRegIrqMask); | |
3479 | __napi_schedule(&np->napi); | |
3480 | } | |
86b22b0d AA |
3481 | dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name); |
3482 | ||
b67874ac | 3483 | return IRQ_HANDLED; |
86b22b0d AA |
3484 | } |
3485 | ||
7d12e780 | 3486 | static irqreturn_t nv_nic_irq_tx(int foo, void *data) |
d33a73c8 AA |
3487 | { |
3488 | struct net_device *dev = (struct net_device *) data; | |
3489 | struct fe_priv *np = netdev_priv(dev); | |
3490 | u8 __iomem *base = get_hwbase(dev); | |
3491 | u32 events; | |
3492 | int i; | |
0a07bc64 | 3493 | unsigned long flags; |
d33a73c8 AA |
3494 | |
3495 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name); | |
3496 | ||
78aea4fc | 3497 | for (i = 0;; i++) { |
d33a73c8 AA |
3498 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
3499 | writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3500 | dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); |
3501 | if (!(events & np->irqmask)) | |
3502 | break; | |
3503 | ||
0a07bc64 | 3504 | spin_lock_irqsave(&np->lock, flags); |
4e16ed1b | 3505 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
0a07bc64 | 3506 | spin_unlock_irqrestore(&np->lock, flags); |
f3b197ac | 3507 | |
f0734ab6 | 3508 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3509 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3510 | /* disable interrupts on the nic */ |
3511 | writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); | |
3512 | pci_push(base); | |
3513 | ||
3514 | if (!np->in_shutdown) { | |
3515 | np->nic_poll_irq |= NVREG_IRQ_TX_ALL; | |
3516 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3517 | } | |
0a07bc64 | 3518 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3519 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); |
d33a73c8 AA |
3520 | break; |
3521 | } | |
3522 | ||
3523 | } | |
3524 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name); | |
3525 | ||
3526 | return IRQ_RETVAL(i); | |
3527 | } | |
3528 | ||
bea3348e | 3529 | static int nv_napi_poll(struct napi_struct *napi, int budget) |
e27cdba5 | 3530 | { |
bea3348e SH |
3531 | struct fe_priv *np = container_of(napi, struct fe_priv, napi); |
3532 | struct net_device *dev = np->dev; | |
e27cdba5 | 3533 | u8 __iomem *base = get_hwbase(dev); |
d15e9c4d | 3534 | unsigned long flags; |
4145ade2 | 3535 | int retcode; |
78aea4fc | 3536 | int rx_count, tx_work = 0, rx_work = 0; |
e27cdba5 | 3537 | |
81a2e36d | 3538 | do { |
3539 | if (!nv_optimized(np)) { | |
3540 | spin_lock_irqsave(&np->lock, flags); | |
3541 | tx_work += nv_tx_done(dev, np->tx_ring_size); | |
3542 | spin_unlock_irqrestore(&np->lock, flags); | |
f27e6f39 | 3543 | |
d951f725 | 3544 | rx_count = nv_rx_process(dev, budget - rx_work); |
81a2e36d | 3545 | retcode = nv_alloc_rx(dev); |
3546 | } else { | |
3547 | spin_lock_irqsave(&np->lock, flags); | |
3548 | tx_work += nv_tx_done_optimized(dev, np->tx_ring_size); | |
3549 | spin_unlock_irqrestore(&np->lock, flags); | |
f27e6f39 | 3550 | |
d951f725 TH |
3551 | rx_count = nv_rx_process_optimized(dev, |
3552 | budget - rx_work); | |
81a2e36d | 3553 | retcode = nv_alloc_rx_optimized(dev); |
3554 | } | |
3555 | } while (retcode == 0 && | |
3556 | rx_count > 0 && (rx_work += rx_count) < budget); | |
e27cdba5 | 3557 | |
e0379a14 | 3558 | if (retcode) { |
d15e9c4d | 3559 | spin_lock_irqsave(&np->lock, flags); |
e27cdba5 SH |
3560 | if (!np->in_shutdown) |
3561 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
d15e9c4d | 3562 | spin_unlock_irqrestore(&np->lock, flags); |
e27cdba5 SH |
3563 | } |
3564 | ||
4145ade2 AA |
3565 | nv_change_interrupt_mode(dev, tx_work + rx_work); |
3566 | ||
f27e6f39 AA |
3567 | if (unlikely(np->events & NVREG_IRQ_LINK)) { |
3568 | spin_lock_irqsave(&np->lock, flags); | |
3569 | nv_link_irq(dev); | |
3570 | spin_unlock_irqrestore(&np->lock, flags); | |
3571 | } | |
3572 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { | |
3573 | spin_lock_irqsave(&np->lock, flags); | |
3574 | nv_linkchange(dev); | |
3575 | spin_unlock_irqrestore(&np->lock, flags); | |
3576 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
3577 | } | |
3578 | if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) { | |
3579 | spin_lock_irqsave(&np->lock, flags); | |
3580 | if (!np->in_shutdown) { | |
3581 | np->nic_poll_irq = np->irqmask; | |
3582 | np->recover_error = 1; | |
3583 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3584 | } | |
3585 | spin_unlock_irqrestore(&np->lock, flags); | |
6c2da9c2 | 3586 | napi_complete(napi); |
4145ade2 | 3587 | return rx_work; |
f27e6f39 AA |
3588 | } |
3589 | ||
4145ade2 | 3590 | if (rx_work < budget) { |
f27e6f39 AA |
3591 | /* re-enable interrupts |
3592 | (msix not enabled in napi) */ | |
6c2da9c2 | 3593 | napi_complete(napi); |
bea3348e | 3594 | |
f27e6f39 | 3595 | writel(np->irqmask, base + NvRegIrqMask); |
e27cdba5 | 3596 | } |
4145ade2 | 3597 | return rx_work; |
e27cdba5 | 3598 | } |
e27cdba5 | 3599 | |
7d12e780 | 3600 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
d33a73c8 AA |
3601 | { |
3602 | struct net_device *dev = (struct net_device *) data; | |
3603 | struct fe_priv *np = netdev_priv(dev); | |
3604 | u8 __iomem *base = get_hwbase(dev); | |
3605 | u32 events; | |
3606 | int i; | |
0a07bc64 | 3607 | unsigned long flags; |
d33a73c8 AA |
3608 | |
3609 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name); | |
3610 | ||
78aea4fc | 3611 | for (i = 0;; i++) { |
d33a73c8 AA |
3612 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
3613 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3614 | dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); |
3615 | if (!(events & np->irqmask)) | |
3616 | break; | |
f3b197ac | 3617 | |
bea3348e | 3618 | if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3619 | if (unlikely(nv_alloc_rx_optimized(dev))) { |
3620 | spin_lock_irqsave(&np->lock, flags); | |
3621 | if (!np->in_shutdown) | |
3622 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3623 | spin_unlock_irqrestore(&np->lock, flags); | |
3624 | } | |
d33a73c8 | 3625 | } |
f3b197ac | 3626 | |
f0734ab6 | 3627 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3628 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3629 | /* disable interrupts on the nic */ |
3630 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3631 | pci_push(base); | |
3632 | ||
3633 | if (!np->in_shutdown) { | |
3634 | np->nic_poll_irq |= NVREG_IRQ_RX_ALL; | |
3635 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3636 | } | |
0a07bc64 | 3637 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3638 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); |
d33a73c8 AA |
3639 | break; |
3640 | } | |
d33a73c8 AA |
3641 | } |
3642 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name); | |
3643 | ||
3644 | return IRQ_RETVAL(i); | |
3645 | } | |
3646 | ||
7d12e780 | 3647 | static irqreturn_t nv_nic_irq_other(int foo, void *data) |
d33a73c8 AA |
3648 | { |
3649 | struct net_device *dev = (struct net_device *) data; | |
3650 | struct fe_priv *np = netdev_priv(dev); | |
3651 | u8 __iomem *base = get_hwbase(dev); | |
3652 | u32 events; | |
3653 | int i; | |
0a07bc64 | 3654 | unsigned long flags; |
d33a73c8 AA |
3655 | |
3656 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name); | |
3657 | ||
78aea4fc | 3658 | for (i = 0;; i++) { |
d33a73c8 AA |
3659 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
3660 | writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3661 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
3662 | if (!(events & np->irqmask)) | |
3663 | break; | |
f3b197ac | 3664 | |
4e16ed1b AA |
3665 | /* check tx in case we reached max loop limit in tx isr */ |
3666 | spin_lock_irqsave(&np->lock, flags); | |
3667 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); | |
3668 | spin_unlock_irqrestore(&np->lock, flags); | |
3669 | ||
d33a73c8 | 3670 | if (events & NVREG_IRQ_LINK) { |
0a07bc64 | 3671 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3672 | nv_link_irq(dev); |
0a07bc64 | 3673 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3674 | } |
3675 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { | |
0a07bc64 | 3676 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3677 | nv_linkchange(dev); |
0a07bc64 | 3678 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3679 | np->link_timeout = jiffies + LINK_TIMEOUT; |
3680 | } | |
c5cf9101 AA |
3681 | if (events & NVREG_IRQ_RECOVER_ERROR) { |
3682 | spin_lock_irq(&np->lock); | |
3683 | /* disable interrupts on the nic */ | |
3684 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3685 | pci_push(base); | |
3686 | ||
3687 | if (!np->in_shutdown) { | |
3688 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3689 | np->recover_error = 1; | |
3690 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3691 | } | |
3692 | spin_unlock_irq(&np->lock); | |
3693 | break; | |
3694 | } | |
f0734ab6 | 3695 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3696 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3697 | /* disable interrupts on the nic */ |
3698 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3699 | pci_push(base); | |
3700 | ||
3701 | if (!np->in_shutdown) { | |
3702 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3703 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3704 | } | |
0a07bc64 | 3705 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3706 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); |
d33a73c8 AA |
3707 | break; |
3708 | } | |
3709 | ||
3710 | } | |
3711 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name); | |
3712 | ||
3713 | return IRQ_RETVAL(i); | |
3714 | } | |
3715 | ||
7d12e780 | 3716 | static irqreturn_t nv_nic_irq_test(int foo, void *data) |
9589c77a AA |
3717 | { |
3718 | struct net_device *dev = (struct net_device *) data; | |
3719 | struct fe_priv *np = netdev_priv(dev); | |
3720 | u8 __iomem *base = get_hwbase(dev); | |
3721 | u32 events; | |
3722 | ||
3723 | dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name); | |
3724 | ||
3725 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
3726 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
3727 | writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); | |
3728 | } else { | |
3729 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
3730 | writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); | |
3731 | } | |
3732 | pci_push(base); | |
3733 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); | |
3734 | if (!(events & NVREG_IRQ_TIMER)) | |
3735 | return IRQ_RETVAL(0); | |
3736 | ||
4db0ee17 AA |
3737 | nv_msi_workaround(np); |
3738 | ||
9589c77a AA |
3739 | spin_lock(&np->lock); |
3740 | np->intr_test = 1; | |
3741 | spin_unlock(&np->lock); | |
3742 | ||
3743 | dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name); | |
3744 | ||
3745 | return IRQ_RETVAL(1); | |
3746 | } | |
3747 | ||
7a1854b7 AA |
3748 | static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
3749 | { | |
3750 | u8 __iomem *base = get_hwbase(dev); | |
3751 | int i; | |
3752 | u32 msixmap = 0; | |
3753 | ||
3754 | /* Each interrupt bit can be mapped to a MSIX vector (4 bits). | |
3755 | * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents | |
3756 | * the remaining 8 interrupts. | |
3757 | */ | |
3758 | for (i = 0; i < 8; i++) { | |
78aea4fc | 3759 | if ((irqmask >> i) & 0x1) |
7a1854b7 | 3760 | msixmap |= vector << (i << 2); |
7a1854b7 AA |
3761 | } |
3762 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); | |
3763 | ||
3764 | msixmap = 0; | |
3765 | for (i = 0; i < 8; i++) { | |
78aea4fc | 3766 | if ((irqmask >> (i + 8)) & 0x1) |
7a1854b7 | 3767 | msixmap |= vector << (i << 2); |
7a1854b7 AA |
3768 | } |
3769 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); | |
3770 | } | |
3771 | ||
9589c77a | 3772 | static int nv_request_irq(struct net_device *dev, int intr_test) |
7a1854b7 AA |
3773 | { |
3774 | struct fe_priv *np = get_nvpriv(dev); | |
3775 | u8 __iomem *base = get_hwbase(dev); | |
3776 | int ret = 1; | |
3777 | int i; | |
86b22b0d AA |
3778 | irqreturn_t (*handler)(int foo, void *data); |
3779 | ||
3780 | if (intr_test) { | |
3781 | handler = nv_nic_irq_test; | |
3782 | } else { | |
36b30ea9 | 3783 | if (nv_optimized(np)) |
86b22b0d AA |
3784 | handler = nv_nic_irq_optimized; |
3785 | else | |
3786 | handler = nv_nic_irq; | |
3787 | } | |
7a1854b7 AA |
3788 | |
3789 | if (np->msi_flags & NV_MSI_X_CAPABLE) { | |
78aea4fc | 3790 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
7a1854b7 | 3791 | np->msi_x_entry[i].entry = i; |
7a1854b7 AA |
3792 | if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) { |
3793 | np->msi_flags |= NV_MSI_X_ENABLED; | |
9589c77a | 3794 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
7a1854b7 | 3795 | /* Request irq for rx handling */ |
ddb213f0 YL |
3796 | sprintf(np->name_rx, "%s-rx", dev->name); |
3797 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, | |
a0607fd3 | 3798 | nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) { |
7a1854b7 AA |
3799 | printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); |
3800 | pci_disable_msix(np->pci_dev); | |
3801 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3802 | goto out_err; | |
3803 | } | |
3804 | /* Request irq for tx handling */ | |
ddb213f0 YL |
3805 | sprintf(np->name_tx, "%s-tx", dev->name); |
3806 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, | |
a0607fd3 | 3807 | nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) { |
7a1854b7 AA |
3808 | printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); |
3809 | pci_disable_msix(np->pci_dev); | |
3810 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3811 | goto out_free_rx; | |
3812 | } | |
3813 | /* Request irq for link and timer handling */ | |
ddb213f0 YL |
3814 | sprintf(np->name_other, "%s-other", dev->name); |
3815 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, | |
a0607fd3 | 3816 | nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) { |
7a1854b7 AA |
3817 | printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); |
3818 | pci_disable_msix(np->pci_dev); | |
3819 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3820 | goto out_free_tx; | |
3821 | } | |
3822 | /* map interrupts to their respective vector */ | |
3823 | writel(0, base + NvRegMSIXMap0); | |
3824 | writel(0, base + NvRegMSIXMap1); | |
3825 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); | |
3826 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); | |
3827 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); | |
3828 | } else { | |
3829 | /* Request irq for all interrupts */ | |
86b22b0d | 3830 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3831 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3832 | pci_disable_msix(np->pci_dev); | |
3833 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3834 | goto out_err; | |
3835 | } | |
3836 | ||
3837 | /* map interrupts to vector 0 */ | |
3838 | writel(0, base + NvRegMSIXMap0); | |
3839 | writel(0, base + NvRegMSIXMap1); | |
3840 | } | |
3841 | } | |
3842 | } | |
3843 | if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { | |
3844 | if ((ret = pci_enable_msi(np->pci_dev)) == 0) { | |
3845 | np->msi_flags |= NV_MSI_ENABLED; | |
a7475906 | 3846 | dev->irq = np->pci_dev->irq; |
86b22b0d | 3847 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3848 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3849 | pci_disable_msi(np->pci_dev); | |
3850 | np->msi_flags &= ~NV_MSI_ENABLED; | |
a7475906 | 3851 | dev->irq = np->pci_dev->irq; |
7a1854b7 AA |
3852 | goto out_err; |
3853 | } | |
3854 | ||
3855 | /* map interrupts to vector 0 */ | |
3856 | writel(0, base + NvRegMSIMap0); | |
3857 | writel(0, base + NvRegMSIMap1); | |
3858 | /* enable msi vector 0 */ | |
3859 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3860 | } | |
3861 | } | |
3862 | if (ret != 0) { | |
86b22b0d | 3863 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) |
7a1854b7 | 3864 | goto out_err; |
9589c77a | 3865 | |
7a1854b7 AA |
3866 | } |
3867 | ||
3868 | return 0; | |
3869 | out_free_tx: | |
3870 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); | |
3871 | out_free_rx: | |
3872 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); | |
3873 | out_err: | |
3874 | return 1; | |
3875 | } | |
3876 | ||
3877 | static void nv_free_irq(struct net_device *dev) | |
3878 | { | |
3879 | struct fe_priv *np = get_nvpriv(dev); | |
3880 | int i; | |
3881 | ||
3882 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
78aea4fc | 3883 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
7a1854b7 | 3884 | free_irq(np->msi_x_entry[i].vector, dev); |
7a1854b7 AA |
3885 | pci_disable_msix(np->pci_dev); |
3886 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3887 | } else { | |
3888 | free_irq(np->pci_dev->irq, dev); | |
3889 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3890 | pci_disable_msi(np->pci_dev); | |
3891 | np->msi_flags &= ~NV_MSI_ENABLED; | |
3892 | } | |
3893 | } | |
3894 | } | |
3895 | ||
1da177e4 LT |
3896 | static void nv_do_nic_poll(unsigned long data) |
3897 | { | |
3898 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3899 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3900 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 3901 | u32 mask = 0; |
1da177e4 | 3902 | |
1da177e4 | 3903 | /* |
d33a73c8 | 3904 | * First disable irq(s) and then |
1da177e4 LT |
3905 | * reenable interrupts on the nic, we have to do this before calling |
3906 | * nv_nic_irq because that may decide to do otherwise | |
3907 | */ | |
d33a73c8 | 3908 | |
84b3932b AA |
3909 | if (!using_multi_irqs(dev)) { |
3910 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
8688cfce | 3911 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 3912 | else |
a7475906 | 3913 | disable_irq_lockdep(np->pci_dev->irq); |
d33a73c8 AA |
3914 | mask = np->irqmask; |
3915 | } else { | |
3916 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
8688cfce | 3917 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
3918 | mask |= NVREG_IRQ_RX_ALL; |
3919 | } | |
3920 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
8688cfce | 3921 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
3922 | mask |= NVREG_IRQ_TX_ALL; |
3923 | } | |
3924 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
8688cfce | 3925 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
3926 | mask |= NVREG_IRQ_OTHER; |
3927 | } | |
3928 | } | |
a7475906 MS |
3929 | /* disable_irq() contains synchronize_irq, thus no irq handler can run now */ |
3930 | ||
c5cf9101 AA |
3931 | if (np->recover_error) { |
3932 | np->recover_error = 0; | |
daa91a9d | 3933 | printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name); |
c5cf9101 AA |
3934 | if (netif_running(dev)) { |
3935 | netif_tx_lock_bh(dev); | |
e308a5d8 | 3936 | netif_addr_lock(dev); |
c5cf9101 AA |
3937 | spin_lock(&np->lock); |
3938 | /* stop engines */ | |
36b30ea9 | 3939 | nv_stop_rxtx(dev); |
daa91a9d AA |
3940 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
3941 | nv_mac_reset(dev); | |
c5cf9101 AA |
3942 | nv_txrx_reset(dev); |
3943 | /* drain rx queue */ | |
36b30ea9 | 3944 | nv_drain_rxtx(dev); |
c5cf9101 AA |
3945 | /* reinit driver view of the rx queue */ |
3946 | set_bufsize(dev); | |
3947 | if (nv_init_ring(dev)) { | |
3948 | if (!np->in_shutdown) | |
3949 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3950 | } | |
3951 | /* reinit nic view of the rx queue */ | |
3952 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
3953 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 3954 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
c5cf9101 AA |
3955 | base + NvRegRingSizes); |
3956 | pci_push(base); | |
3957 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
3958 | pci_push(base); | |
daa91a9d AA |
3959 | /* clear interrupts */ |
3960 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
3961 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
3962 | else | |
3963 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
c5cf9101 AA |
3964 | |
3965 | /* restart rx engine */ | |
36b30ea9 | 3966 | nv_start_rxtx(dev); |
c5cf9101 | 3967 | spin_unlock(&np->lock); |
e308a5d8 | 3968 | netif_addr_unlock(dev); |
c5cf9101 AA |
3969 | netif_tx_unlock_bh(dev); |
3970 | } | |
3971 | } | |
3972 | ||
d33a73c8 | 3973 | writel(mask, base + NvRegIrqMask); |
1da177e4 | 3974 | pci_push(base); |
d33a73c8 | 3975 | |
84b3932b | 3976 | if (!using_multi_irqs(dev)) { |
79d30a58 | 3977 | np->nic_poll_irq = 0; |
36b30ea9 | 3978 | if (nv_optimized(np)) |
fcc5f266 AA |
3979 | nv_nic_irq_optimized(0, dev); |
3980 | else | |
3981 | nv_nic_irq(0, dev); | |
84b3932b | 3982 | if (np->msi_flags & NV_MSI_X_ENABLED) |
8688cfce | 3983 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 3984 | else |
a7475906 | 3985 | enable_irq_lockdep(np->pci_dev->irq); |
d33a73c8 AA |
3986 | } else { |
3987 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
79d30a58 | 3988 | np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL; |
7d12e780 | 3989 | nv_nic_irq_rx(0, dev); |
8688cfce | 3990 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
3991 | } |
3992 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
79d30a58 | 3993 | np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL; |
7d12e780 | 3994 | nv_nic_irq_tx(0, dev); |
8688cfce | 3995 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
3996 | } |
3997 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
79d30a58 | 3998 | np->nic_poll_irq &= ~NVREG_IRQ_OTHER; |
7d12e780 | 3999 | nv_nic_irq_other(0, dev); |
8688cfce | 4000 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
4001 | } |
4002 | } | |
79d30a58 | 4003 | |
1da177e4 LT |
4004 | } |
4005 | ||
2918c35d MS |
4006 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4007 | static void nv_poll_controller(struct net_device *dev) | |
4008 | { | |
4009 | nv_do_nic_poll((unsigned long) dev); | |
4010 | } | |
4011 | #endif | |
4012 | ||
52da3578 AA |
4013 | static void nv_do_stats_poll(unsigned long data) |
4014 | { | |
4015 | struct net_device *dev = (struct net_device *) data; | |
4016 | struct fe_priv *np = netdev_priv(dev); | |
52da3578 | 4017 | |
57fff698 | 4018 | nv_get_hw_stats(dev); |
52da3578 AA |
4019 | |
4020 | if (!np->in_shutdown) | |
bfebbb88 DD |
4021 | mod_timer(&np->stats_poll, |
4022 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 AA |
4023 | } |
4024 | ||
1da177e4 LT |
4025 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
4026 | { | |
ac9c1897 | 4027 | struct fe_priv *np = netdev_priv(dev); |
3f88ce49 | 4028 | strcpy(info->driver, DRV_NAME); |
1da177e4 LT |
4029 | strcpy(info->version, FORCEDETH_VERSION); |
4030 | strcpy(info->bus_info, pci_name(np->pci_dev)); | |
4031 | } | |
4032 | ||
4033 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
4034 | { | |
ac9c1897 | 4035 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
4036 | wolinfo->supported = WAKE_MAGIC; |
4037 | ||
4038 | spin_lock_irq(&np->lock); | |
4039 | if (np->wolenabled) | |
4040 | wolinfo->wolopts = WAKE_MAGIC; | |
4041 | spin_unlock_irq(&np->lock); | |
4042 | } | |
4043 | ||
4044 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
4045 | { | |
ac9c1897 | 4046 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 4047 | u8 __iomem *base = get_hwbase(dev); |
c42d9df9 | 4048 | u32 flags = 0; |
1da177e4 | 4049 | |
1da177e4 | 4050 | if (wolinfo->wolopts == 0) { |
1da177e4 | 4051 | np->wolenabled = 0; |
c42d9df9 | 4052 | } else if (wolinfo->wolopts & WAKE_MAGIC) { |
1da177e4 | 4053 | np->wolenabled = 1; |
c42d9df9 AA |
4054 | flags = NVREG_WAKEUPFLAGS_ENABLE; |
4055 | } | |
4056 | if (netif_running(dev)) { | |
4057 | spin_lock_irq(&np->lock); | |
4058 | writel(flags, base + NvRegWakeUpFlags); | |
4059 | spin_unlock_irq(&np->lock); | |
1da177e4 | 4060 | } |
1da177e4 LT |
4061 | return 0; |
4062 | } | |
4063 | ||
4064 | static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
4065 | { | |
4066 | struct fe_priv *np = netdev_priv(dev); | |
4067 | int adv; | |
4068 | ||
4069 | spin_lock_irq(&np->lock); | |
4070 | ecmd->port = PORT_MII; | |
4071 | if (!netif_running(dev)) { | |
4072 | /* We do not track link speed / duplex setting if the | |
4073 | * interface is disabled. Force a link check */ | |
f9430a01 AA |
4074 | if (nv_update_linkspeed(dev)) { |
4075 | if (!netif_carrier_ok(dev)) | |
4076 | netif_carrier_on(dev); | |
4077 | } else { | |
4078 | if (netif_carrier_ok(dev)) | |
4079 | netif_carrier_off(dev); | |
4080 | } | |
1da177e4 | 4081 | } |
f9430a01 AA |
4082 | |
4083 | if (netif_carrier_ok(dev)) { | |
78aea4fc | 4084 | switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) { |
1da177e4 LT |
4085 | case NVREG_LINKSPEED_10: |
4086 | ecmd->speed = SPEED_10; | |
4087 | break; | |
4088 | case NVREG_LINKSPEED_100: | |
4089 | ecmd->speed = SPEED_100; | |
4090 | break; | |
4091 | case NVREG_LINKSPEED_1000: | |
4092 | ecmd->speed = SPEED_1000; | |
4093 | break; | |
f9430a01 AA |
4094 | } |
4095 | ecmd->duplex = DUPLEX_HALF; | |
4096 | if (np->duplex) | |
4097 | ecmd->duplex = DUPLEX_FULL; | |
4098 | } else { | |
4099 | ecmd->speed = -1; | |
4100 | ecmd->duplex = -1; | |
1da177e4 | 4101 | } |
1da177e4 LT |
4102 | |
4103 | ecmd->autoneg = np->autoneg; | |
4104 | ||
4105 | ecmd->advertising = ADVERTISED_MII; | |
4106 | if (np->autoneg) { | |
4107 | ecmd->advertising |= ADVERTISED_Autoneg; | |
4108 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
f9430a01 AA |
4109 | if (adv & ADVERTISE_10HALF) |
4110 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
4111 | if (adv & ADVERTISE_10FULL) | |
4112 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
4113 | if (adv & ADVERTISE_100HALF) | |
4114 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
4115 | if (adv & ADVERTISE_100FULL) | |
4116 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
4117 | if (np->gigabit == PHY_GIGABIT) { | |
4118 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); | |
4119 | if (adv & ADVERTISE_1000FULL) | |
4120 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
4121 | } | |
1da177e4 | 4122 | } |
1da177e4 LT |
4123 | ecmd->supported = (SUPPORTED_Autoneg | |
4124 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | | |
4125 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
4126 | SUPPORTED_MII); | |
4127 | if (np->gigabit == PHY_GIGABIT) | |
4128 | ecmd->supported |= SUPPORTED_1000baseT_Full; | |
4129 | ||
4130 | ecmd->phy_address = np->phyaddr; | |
4131 | ecmd->transceiver = XCVR_EXTERNAL; | |
4132 | ||
4133 | /* ignore maxtxpkt, maxrxpkt for now */ | |
4134 | spin_unlock_irq(&np->lock); | |
4135 | return 0; | |
4136 | } | |
4137 | ||
4138 | static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
4139 | { | |
4140 | struct fe_priv *np = netdev_priv(dev); | |
4141 | ||
4142 | if (ecmd->port != PORT_MII) | |
4143 | return -EINVAL; | |
4144 | if (ecmd->transceiver != XCVR_EXTERNAL) | |
4145 | return -EINVAL; | |
4146 | if (ecmd->phy_address != np->phyaddr) { | |
4147 | /* TODO: support switching between multiple phys. Should be | |
4148 | * trivial, but not enabled due to lack of test hardware. */ | |
4149 | return -EINVAL; | |
4150 | } | |
4151 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
4152 | u32 mask; | |
4153 | ||
4154 | mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4155 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4156 | if (np->gigabit == PHY_GIGABIT) | |
4157 | mask |= ADVERTISED_1000baseT_Full; | |
4158 | ||
4159 | if ((ecmd->advertising & mask) == 0) | |
4160 | return -EINVAL; | |
4161 | ||
4162 | } else if (ecmd->autoneg == AUTONEG_DISABLE) { | |
4163 | /* Note: autonegotiation disable, speed 1000 intentionally | |
4164 | * forbidden - noone should need that. */ | |
4165 | ||
4166 | if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) | |
4167 | return -EINVAL; | |
4168 | if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) | |
4169 | return -EINVAL; | |
4170 | } else { | |
4171 | return -EINVAL; | |
4172 | } | |
4173 | ||
f9430a01 AA |
4174 | netif_carrier_off(dev); |
4175 | if (netif_running(dev)) { | |
97bff095 TD |
4176 | unsigned long flags; |
4177 | ||
f9430a01 | 4178 | nv_disable_irq(dev); |
58dfd9c1 | 4179 | netif_tx_lock_bh(dev); |
e308a5d8 | 4180 | netif_addr_lock(dev); |
97bff095 TD |
4181 | /* with plain spinlock lockdep complains */ |
4182 | spin_lock_irqsave(&np->lock, flags); | |
f9430a01 | 4183 | /* stop engines */ |
97bff095 TD |
4184 | /* FIXME: |
4185 | * this can take some time, and interrupts are disabled | |
4186 | * due to spin_lock_irqsave, but let's hope no daemon | |
4187 | * is going to change the settings very often... | |
4188 | * Worst case: | |
4189 | * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX | |
4190 | * + some minor delays, which is up to a second approximately | |
4191 | */ | |
36b30ea9 | 4192 | nv_stop_rxtx(dev); |
97bff095 | 4193 | spin_unlock_irqrestore(&np->lock, flags); |
e308a5d8 | 4194 | netif_addr_unlock(dev); |
58dfd9c1 | 4195 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
4196 | } |
4197 | ||
1da177e4 LT |
4198 | if (ecmd->autoneg == AUTONEG_ENABLE) { |
4199 | int adv, bmcr; | |
4200 | ||
4201 | np->autoneg = 1; | |
4202 | ||
4203 | /* advertise only what has been requested */ | |
4204 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4205 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
4206 | if (ecmd->advertising & ADVERTISED_10baseT_Half) |
4207 | adv |= ADVERTISE_10HALF; | |
4208 | if (ecmd->advertising & ADVERTISED_10baseT_Full) | |
b6d0773f | 4209 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
4210 | if (ecmd->advertising & ADVERTISED_100baseT_Half) |
4211 | adv |= ADVERTISE_100HALF; | |
4212 | if (ecmd->advertising & ADVERTISED_100baseT_Full) | |
b6d0773f AA |
4213 | adv |= ADVERTISE_100FULL; |
4214 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ | |
4215 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4216 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4217 | adv |= ADVERTISE_PAUSE_ASYM; | |
1da177e4 LT |
4218 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4219 | ||
4220 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4221 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
4222 | adv &= ~ADVERTISE_1000FULL; |
4223 | if (ecmd->advertising & ADVERTISED_1000baseT_Full) | |
4224 | adv |= ADVERTISE_1000FULL; | |
eb91f61b | 4225 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4226 | } |
4227 | ||
f9430a01 AA |
4228 | if (netif_running(dev)) |
4229 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
1da177e4 | 4230 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4231 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4232 | bmcr |= BMCR_ANENABLE; | |
4233 | /* reset the phy in order for settings to stick, | |
4234 | * and cause autoneg to start */ | |
4235 | if (phy_reset(dev, bmcr)) { | |
4236 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | |
4237 | return -EINVAL; | |
4238 | } | |
4239 | } else { | |
4240 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4241 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4242 | } | |
1da177e4 LT |
4243 | } else { |
4244 | int adv, bmcr; | |
4245 | ||
4246 | np->autoneg = 0; | |
4247 | ||
4248 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4249 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
4250 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) |
4251 | adv |= ADVERTISE_10HALF; | |
4252 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) | |
b6d0773f | 4253 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
4254 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) |
4255 | adv |= ADVERTISE_100HALF; | |
4256 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) | |
b6d0773f AA |
4257 | adv |= ADVERTISE_100FULL; |
4258 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4259 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */ | |
4260 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4261 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4262 | } | |
4263 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { | |
4264 | adv |= ADVERTISE_PAUSE_ASYM; | |
4265 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4266 | } | |
1da177e4 LT |
4267 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4268 | np->fixed_mode = adv; | |
4269 | ||
4270 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4271 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 | 4272 | adv &= ~ADVERTISE_1000FULL; |
eb91f61b | 4273 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4274 | } |
4275 | ||
4276 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
f9430a01 AA |
4277 | bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX); |
4278 | if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) | |
1da177e4 | 4279 | bmcr |= BMCR_FULLDPLX; |
f9430a01 | 4280 | if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
1da177e4 | 4281 | bmcr |= BMCR_SPEED100; |
f9430a01 | 4282 | if (np->phy_oui == PHY_OUI_MARVELL) { |
edf7e5ec AA |
4283 | /* reset the phy in order for forced mode settings to stick */ |
4284 | if (phy_reset(dev, bmcr)) { | |
f9430a01 AA |
4285 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
4286 | return -EINVAL; | |
4287 | } | |
edf7e5ec AA |
4288 | } else { |
4289 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4290 | if (netif_running(dev)) { | |
4291 | /* Wait a bit and then reconfigure the nic. */ | |
4292 | udelay(10); | |
4293 | nv_linkchange(dev); | |
4294 | } | |
1da177e4 LT |
4295 | } |
4296 | } | |
f9430a01 AA |
4297 | |
4298 | if (netif_running(dev)) { | |
36b30ea9 | 4299 | nv_start_rxtx(dev); |
f9430a01 AA |
4300 | nv_enable_irq(dev); |
4301 | } | |
1da177e4 LT |
4302 | |
4303 | return 0; | |
4304 | } | |
4305 | ||
dc8216c1 | 4306 | #define FORCEDETH_REGS_VER 1 |
dc8216c1 MS |
4307 | |
4308 | static int nv_get_regs_len(struct net_device *dev) | |
4309 | { | |
86a0f043 AA |
4310 | struct fe_priv *np = netdev_priv(dev); |
4311 | return np->register_size; | |
dc8216c1 MS |
4312 | } |
4313 | ||
4314 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
4315 | { | |
ac9c1897 | 4316 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4317 | u8 __iomem *base = get_hwbase(dev); |
4318 | u32 *rbuf = buf; | |
4319 | int i; | |
4320 | ||
4321 | regs->version = FORCEDETH_REGS_VER; | |
4322 | spin_lock_irq(&np->lock); | |
78aea4fc | 4323 | for (i = 0; i <= np->register_size/sizeof(u32); i++) |
dc8216c1 MS |
4324 | rbuf[i] = readl(base + i*sizeof(u32)); |
4325 | spin_unlock_irq(&np->lock); | |
4326 | } | |
4327 | ||
4328 | static int nv_nway_reset(struct net_device *dev) | |
4329 | { | |
ac9c1897 | 4330 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4331 | int ret; |
4332 | ||
dc8216c1 MS |
4333 | if (np->autoneg) { |
4334 | int bmcr; | |
4335 | ||
f9430a01 AA |
4336 | netif_carrier_off(dev); |
4337 | if (netif_running(dev)) { | |
4338 | nv_disable_irq(dev); | |
58dfd9c1 | 4339 | netif_tx_lock_bh(dev); |
e308a5d8 | 4340 | netif_addr_lock(dev); |
f9430a01 AA |
4341 | spin_lock(&np->lock); |
4342 | /* stop engines */ | |
36b30ea9 | 4343 | nv_stop_rxtx(dev); |
f9430a01 | 4344 | spin_unlock(&np->lock); |
e308a5d8 | 4345 | netif_addr_unlock(dev); |
58dfd9c1 | 4346 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
4347 | printk(KERN_INFO "%s: link down.\n", dev->name); |
4348 | } | |
4349 | ||
dc8216c1 | 4350 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4351 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4352 | bmcr |= BMCR_ANENABLE; | |
4353 | /* reset the phy in order for settings to stick*/ | |
4354 | if (phy_reset(dev, bmcr)) { | |
4355 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | |
4356 | return -EINVAL; | |
4357 | } | |
4358 | } else { | |
4359 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4360 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4361 | } | |
dc8216c1 | 4362 | |
f9430a01 | 4363 | if (netif_running(dev)) { |
36b30ea9 | 4364 | nv_start_rxtx(dev); |
f9430a01 AA |
4365 | nv_enable_irq(dev); |
4366 | } | |
dc8216c1 MS |
4367 | ret = 0; |
4368 | } else { | |
4369 | ret = -EINVAL; | |
4370 | } | |
dc8216c1 MS |
4371 | |
4372 | return ret; | |
4373 | } | |
4374 | ||
0674d594 ZA |
4375 | static int nv_set_tso(struct net_device *dev, u32 value) |
4376 | { | |
4377 | struct fe_priv *np = netdev_priv(dev); | |
4378 | ||
4379 | if ((np->driver_data & DEV_HAS_CHECKSUM)) | |
4380 | return ethtool_op_set_tso(dev, value); | |
4381 | else | |
6a78814f | 4382 | return -EOPNOTSUPP; |
0674d594 | 4383 | } |
0674d594 | 4384 | |
eafa59f6 AA |
4385 | static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
4386 | { | |
4387 | struct fe_priv *np = netdev_priv(dev); | |
4388 | ||
4389 | ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
4390 | ring->rx_mini_max_pending = 0; | |
4391 | ring->rx_jumbo_max_pending = 0; | |
4392 | ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
4393 | ||
4394 | ring->rx_pending = np->rx_ring_size; | |
4395 | ring->rx_mini_pending = 0; | |
4396 | ring->rx_jumbo_pending = 0; | |
4397 | ring->tx_pending = np->tx_ring_size; | |
4398 | } | |
4399 | ||
4400 | static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) | |
4401 | { | |
4402 | struct fe_priv *np = netdev_priv(dev); | |
4403 | u8 __iomem *base = get_hwbase(dev); | |
761fcd9e | 4404 | u8 *rxtx_ring, *rx_skbuff, *tx_skbuff; |
eafa59f6 AA |
4405 | dma_addr_t ring_addr; |
4406 | ||
4407 | if (ring->rx_pending < RX_RING_MIN || | |
4408 | ring->tx_pending < TX_RING_MIN || | |
4409 | ring->rx_mini_pending != 0 || | |
4410 | ring->rx_jumbo_pending != 0 || | |
4411 | (np->desc_ver == DESC_VER_1 && | |
4412 | (ring->rx_pending > RING_MAX_DESC_VER_1 || | |
4413 | ring->tx_pending > RING_MAX_DESC_VER_1)) || | |
4414 | (np->desc_ver != DESC_VER_1 && | |
4415 | (ring->rx_pending > RING_MAX_DESC_VER_2_3 || | |
4416 | ring->tx_pending > RING_MAX_DESC_VER_2_3))) { | |
4417 | return -EINVAL; | |
4418 | } | |
4419 | ||
4420 | /* allocate new rings */ | |
36b30ea9 | 4421 | if (!nv_optimized(np)) { |
eafa59f6 AA |
4422 | rxtx_ring = pci_alloc_consistent(np->pci_dev, |
4423 | sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), | |
4424 | &ring_addr); | |
4425 | } else { | |
4426 | rxtx_ring = pci_alloc_consistent(np->pci_dev, | |
4427 | sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4428 | &ring_addr); | |
4429 | } | |
761fcd9e AA |
4430 | rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL); |
4431 | tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL); | |
4432 | if (!rxtx_ring || !rx_skbuff || !tx_skbuff) { | |
eafa59f6 | 4433 | /* fall back to old rings */ |
36b30ea9 | 4434 | if (!nv_optimized(np)) { |
f82a9352 | 4435 | if (rxtx_ring) |
eafa59f6 AA |
4436 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), |
4437 | rxtx_ring, ring_addr); | |
4438 | } else { | |
4439 | if (rxtx_ring) | |
4440 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4441 | rxtx_ring, ring_addr); | |
4442 | } | |
9b03b06b SJ |
4443 | |
4444 | kfree(rx_skbuff); | |
4445 | kfree(tx_skbuff); | |
eafa59f6 AA |
4446 | goto exit; |
4447 | } | |
4448 | ||
4449 | if (netif_running(dev)) { | |
4450 | nv_disable_irq(dev); | |
08d93575 | 4451 | nv_napi_disable(dev); |
58dfd9c1 | 4452 | netif_tx_lock_bh(dev); |
e308a5d8 | 4453 | netif_addr_lock(dev); |
eafa59f6 AA |
4454 | spin_lock(&np->lock); |
4455 | /* stop engines */ | |
36b30ea9 | 4456 | nv_stop_rxtx(dev); |
eafa59f6 AA |
4457 | nv_txrx_reset(dev); |
4458 | /* drain queues */ | |
36b30ea9 | 4459 | nv_drain_rxtx(dev); |
eafa59f6 AA |
4460 | /* delete queues */ |
4461 | free_rings(dev); | |
4462 | } | |
4463 | ||
4464 | /* set new values */ | |
4465 | np->rx_ring_size = ring->rx_pending; | |
4466 | np->tx_ring_size = ring->tx_pending; | |
36b30ea9 JG |
4467 | |
4468 | if (!nv_optimized(np)) { | |
78aea4fc | 4469 | np->rx_ring.orig = (struct ring_desc *)rxtx_ring; |
eafa59f6 AA |
4470 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
4471 | } else { | |
78aea4fc | 4472 | np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring; |
eafa59f6 AA |
4473 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
4474 | } | |
78aea4fc SJ |
4475 | np->rx_skb = (struct nv_skb_map *)rx_skbuff; |
4476 | np->tx_skb = (struct nv_skb_map *)tx_skbuff; | |
eafa59f6 AA |
4477 | np->ring_addr = ring_addr; |
4478 | ||
761fcd9e AA |
4479 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
4480 | memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); | |
eafa59f6 AA |
4481 | |
4482 | if (netif_running(dev)) { | |
4483 | /* reinit driver view of the queues */ | |
4484 | set_bufsize(dev); | |
4485 | if (nv_init_ring(dev)) { | |
4486 | if (!np->in_shutdown) | |
4487 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4488 | } | |
4489 | ||
4490 | /* reinit nic view of the queues */ | |
4491 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4492 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4493 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
eafa59f6 AA |
4494 | base + NvRegRingSizes); |
4495 | pci_push(base); | |
4496 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4497 | pci_push(base); | |
4498 | ||
4499 | /* restart engines */ | |
36b30ea9 | 4500 | nv_start_rxtx(dev); |
eafa59f6 | 4501 | spin_unlock(&np->lock); |
e308a5d8 | 4502 | netif_addr_unlock(dev); |
58dfd9c1 | 4503 | netif_tx_unlock_bh(dev); |
08d93575 | 4504 | nv_napi_enable(dev); |
eafa59f6 AA |
4505 | nv_enable_irq(dev); |
4506 | } | |
4507 | return 0; | |
4508 | exit: | |
4509 | return -ENOMEM; | |
4510 | } | |
4511 | ||
b6d0773f AA |
4512 | static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
4513 | { | |
4514 | struct fe_priv *np = netdev_priv(dev); | |
4515 | ||
4516 | pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; | |
4517 | pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; | |
4518 | pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; | |
4519 | } | |
4520 | ||
4521 | static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) | |
4522 | { | |
4523 | struct fe_priv *np = netdev_priv(dev); | |
4524 | int adv, bmcr; | |
4525 | ||
4526 | if ((!np->autoneg && np->duplex == 0) || | |
4527 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { | |
4528 | printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n", | |
4529 | dev->name); | |
4530 | return -EINVAL; | |
4531 | } | |
4532 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { | |
4533 | printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name); | |
4534 | return -EINVAL; | |
4535 | } | |
4536 | ||
4537 | netif_carrier_off(dev); | |
4538 | if (netif_running(dev)) { | |
4539 | nv_disable_irq(dev); | |
58dfd9c1 | 4540 | netif_tx_lock_bh(dev); |
e308a5d8 | 4541 | netif_addr_lock(dev); |
b6d0773f AA |
4542 | spin_lock(&np->lock); |
4543 | /* stop engines */ | |
36b30ea9 | 4544 | nv_stop_rxtx(dev); |
b6d0773f | 4545 | spin_unlock(&np->lock); |
e308a5d8 | 4546 | netif_addr_unlock(dev); |
58dfd9c1 | 4547 | netif_tx_unlock_bh(dev); |
b6d0773f AA |
4548 | } |
4549 | ||
4550 | np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); | |
4551 | if (pause->rx_pause) | |
4552 | np->pause_flags |= NV_PAUSEFRAME_RX_REQ; | |
4553 | if (pause->tx_pause) | |
4554 | np->pause_flags |= NV_PAUSEFRAME_TX_REQ; | |
4555 | ||
4556 | if (np->autoneg && pause->autoneg) { | |
4557 | np->pause_flags |= NV_PAUSEFRAME_AUTONEG; | |
4558 | ||
4559 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
4560 | adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
4561 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ | |
4562 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4563 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4564 | adv |= ADVERTISE_PAUSE_ASYM; | |
4565 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | |
4566 | ||
4567 | if (netif_running(dev)) | |
4568 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
4569 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
4570 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4571 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4572 | } else { | |
4573 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4574 | if (pause->rx_pause) | |
4575 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4576 | if (pause->tx_pause) | |
4577 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4578 | ||
4579 | if (!netif_running(dev)) | |
4580 | nv_update_linkspeed(dev); | |
4581 | else | |
4582 | nv_update_pause(dev, np->pause_flags); | |
4583 | } | |
4584 | ||
4585 | if (netif_running(dev)) { | |
36b30ea9 | 4586 | nv_start_rxtx(dev); |
b6d0773f AA |
4587 | nv_enable_irq(dev); |
4588 | } | |
4589 | return 0; | |
4590 | } | |
4591 | ||
5ed2616f AA |
4592 | static u32 nv_get_rx_csum(struct net_device *dev) |
4593 | { | |
4594 | struct fe_priv *np = netdev_priv(dev); | |
807540ba | 4595 | return np->rx_csum != 0; |
5ed2616f AA |
4596 | } |
4597 | ||
4598 | static int nv_set_rx_csum(struct net_device *dev, u32 data) | |
4599 | { | |
4600 | struct fe_priv *np = netdev_priv(dev); | |
4601 | u8 __iomem *base = get_hwbase(dev); | |
4602 | int retcode = 0; | |
4603 | ||
4604 | if (np->driver_data & DEV_HAS_CHECKSUM) { | |
5ed2616f | 4605 | if (data) { |
f2ad2d9b | 4606 | np->rx_csum = 1; |
5ed2616f | 4607 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
5ed2616f | 4608 | } else { |
f2ad2d9b AA |
4609 | np->rx_csum = 0; |
4610 | /* vlan is dependent on rx checksum offload */ | |
4611 | if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) | |
4612 | np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; | |
5ed2616f | 4613 | } |
5ed2616f AA |
4614 | if (netif_running(dev)) { |
4615 | spin_lock_irq(&np->lock); | |
4616 | writel(np->txrxctl_bits, base + NvRegTxRxControl); | |
4617 | spin_unlock_irq(&np->lock); | |
4618 | } | |
4619 | } else { | |
4620 | return -EINVAL; | |
4621 | } | |
4622 | ||
4623 | return retcode; | |
4624 | } | |
4625 | ||
4626 | static int nv_set_tx_csum(struct net_device *dev, u32 data) | |
4627 | { | |
4628 | struct fe_priv *np = netdev_priv(dev); | |
4629 | ||
4630 | if (np->driver_data & DEV_HAS_CHECKSUM) | |
c1086cda | 4631 | return ethtool_op_set_tx_csum(dev, data); |
5ed2616f AA |
4632 | else |
4633 | return -EOPNOTSUPP; | |
4634 | } | |
4635 | ||
4636 | static int nv_set_sg(struct net_device *dev, u32 data) | |
4637 | { | |
4638 | struct fe_priv *np = netdev_priv(dev); | |
4639 | ||
4640 | if (np->driver_data & DEV_HAS_CHECKSUM) | |
4641 | return ethtool_op_set_sg(dev, data); | |
4642 | else | |
4643 | return -EOPNOTSUPP; | |
4644 | } | |
4645 | ||
b9f2c044 | 4646 | static int nv_get_sset_count(struct net_device *dev, int sset) |
52da3578 AA |
4647 | { |
4648 | struct fe_priv *np = netdev_priv(dev); | |
4649 | ||
b9f2c044 JG |
4650 | switch (sset) { |
4651 | case ETH_SS_TEST: | |
4652 | if (np->driver_data & DEV_HAS_TEST_EXTENDED) | |
4653 | return NV_TEST_COUNT_EXTENDED; | |
4654 | else | |
4655 | return NV_TEST_COUNT_BASE; | |
4656 | case ETH_SS_STATS: | |
8ed1454a AA |
4657 | if (np->driver_data & DEV_HAS_STATISTICS_V3) |
4658 | return NV_DEV_STATISTICS_V3_COUNT; | |
b9f2c044 JG |
4659 | else if (np->driver_data & DEV_HAS_STATISTICS_V2) |
4660 | return NV_DEV_STATISTICS_V2_COUNT; | |
8ed1454a AA |
4661 | else if (np->driver_data & DEV_HAS_STATISTICS_V1) |
4662 | return NV_DEV_STATISTICS_V1_COUNT; | |
b9f2c044 JG |
4663 | else |
4664 | return 0; | |
4665 | default: | |
4666 | return -EOPNOTSUPP; | |
4667 | } | |
52da3578 AA |
4668 | } |
4669 | ||
4670 | static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer) | |
4671 | { | |
4672 | struct fe_priv *np = netdev_priv(dev); | |
4673 | ||
4674 | /* update stats */ | |
4675 | nv_do_stats_poll((unsigned long)dev); | |
4676 | ||
b9f2c044 | 4677 | memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64)); |
9589c77a AA |
4678 | } |
4679 | ||
4680 | static int nv_link_test(struct net_device *dev) | |
4681 | { | |
4682 | struct fe_priv *np = netdev_priv(dev); | |
4683 | int mii_status; | |
4684 | ||
4685 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4686 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4687 | ||
4688 | /* check phy link status */ | |
4689 | if (!(mii_status & BMSR_LSTATUS)) | |
4690 | return 0; | |
4691 | else | |
4692 | return 1; | |
4693 | } | |
4694 | ||
4695 | static int nv_register_test(struct net_device *dev) | |
4696 | { | |
4697 | u8 __iomem *base = get_hwbase(dev); | |
4698 | int i = 0; | |
4699 | u32 orig_read, new_read; | |
4700 | ||
4701 | do { | |
4702 | orig_read = readl(base + nv_registers_test[i].reg); | |
4703 | ||
4704 | /* xor with mask to toggle bits */ | |
4705 | orig_read ^= nv_registers_test[i].mask; | |
4706 | ||
4707 | writel(orig_read, base + nv_registers_test[i].reg); | |
4708 | ||
4709 | new_read = readl(base + nv_registers_test[i].reg); | |
4710 | ||
4711 | if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask)) | |
4712 | return 0; | |
4713 | ||
4714 | /* restore original value */ | |
4715 | orig_read ^= nv_registers_test[i].mask; | |
4716 | writel(orig_read, base + nv_registers_test[i].reg); | |
4717 | ||
4718 | } while (nv_registers_test[++i].reg != 0); | |
4719 | ||
4720 | return 1; | |
4721 | } | |
4722 | ||
4723 | static int nv_interrupt_test(struct net_device *dev) | |
4724 | { | |
4725 | struct fe_priv *np = netdev_priv(dev); | |
4726 | u8 __iomem *base = get_hwbase(dev); | |
4727 | int ret = 1; | |
4728 | int testcnt; | |
4729 | u32 save_msi_flags, save_poll_interval = 0; | |
4730 | ||
4731 | if (netif_running(dev)) { | |
4732 | /* free current irq */ | |
4733 | nv_free_irq(dev); | |
4734 | save_poll_interval = readl(base+NvRegPollingInterval); | |
4735 | } | |
4736 | ||
4737 | /* flag to test interrupt handler */ | |
4738 | np->intr_test = 0; | |
4739 | ||
4740 | /* setup test irq */ | |
4741 | save_msi_flags = np->msi_flags; | |
4742 | np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; | |
4743 | np->msi_flags |= 0x001; /* setup 1 vector */ | |
4744 | if (nv_request_irq(dev, 1)) | |
4745 | return 0; | |
4746 | ||
4747 | /* setup timer interrupt */ | |
4748 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
4749 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4750 | ||
4751 | nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4752 | ||
4753 | /* wait for at least one interrupt */ | |
4754 | msleep(100); | |
4755 | ||
4756 | spin_lock_irq(&np->lock); | |
4757 | ||
4758 | /* flag should be set within ISR */ | |
4759 | testcnt = np->intr_test; | |
4760 | if (!testcnt) | |
4761 | ret = 2; | |
4762 | ||
4763 | nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4764 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
4765 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4766 | else | |
4767 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
4768 | ||
4769 | spin_unlock_irq(&np->lock); | |
4770 | ||
4771 | nv_free_irq(dev); | |
4772 | ||
4773 | np->msi_flags = save_msi_flags; | |
4774 | ||
4775 | if (netif_running(dev)) { | |
4776 | writel(save_poll_interval, base + NvRegPollingInterval); | |
4777 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4778 | /* restore original irq */ | |
4779 | if (nv_request_irq(dev, 0)) | |
4780 | return 0; | |
4781 | } | |
4782 | ||
4783 | return ret; | |
4784 | } | |
4785 | ||
4786 | static int nv_loopback_test(struct net_device *dev) | |
4787 | { | |
4788 | struct fe_priv *np = netdev_priv(dev); | |
4789 | u8 __iomem *base = get_hwbase(dev); | |
4790 | struct sk_buff *tx_skb, *rx_skb; | |
4791 | dma_addr_t test_dma_addr; | |
4792 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); | |
f82a9352 | 4793 | u32 flags; |
9589c77a AA |
4794 | int len, i, pkt_len; |
4795 | u8 *pkt_data; | |
4796 | u32 filter_flags = 0; | |
4797 | u32 misc1_flags = 0; | |
4798 | int ret = 1; | |
4799 | ||
4800 | if (netif_running(dev)) { | |
4801 | nv_disable_irq(dev); | |
4802 | filter_flags = readl(base + NvRegPacketFilterFlags); | |
4803 | misc1_flags = readl(base + NvRegMisc1); | |
4804 | } else { | |
4805 | nv_txrx_reset(dev); | |
4806 | } | |
4807 | ||
4808 | /* reinit driver view of the rx queue */ | |
4809 | set_bufsize(dev); | |
4810 | nv_init_ring(dev); | |
4811 | ||
4812 | /* setup hardware for loopback */ | |
4813 | writel(NVREG_MISC1_FORCE, base + NvRegMisc1); | |
4814 | writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); | |
4815 | ||
4816 | /* reinit nic view of the rx queue */ | |
4817 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4818 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4819 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
9589c77a AA |
4820 | base + NvRegRingSizes); |
4821 | pci_push(base); | |
4822 | ||
4823 | /* restart rx engine */ | |
36b30ea9 | 4824 | nv_start_rxtx(dev); |
9589c77a AA |
4825 | |
4826 | /* setup packet for tx */ | |
4827 | pkt_len = ETH_DATA_LEN; | |
4828 | tx_skb = dev_alloc_skb(pkt_len); | |
46798c89 JJ |
4829 | if (!tx_skb) { |
4830 | printk(KERN_ERR "dev_alloc_skb() failed during loopback test" | |
4831 | " of %s\n", dev->name); | |
4832 | ret = 0; | |
4833 | goto out; | |
4834 | } | |
8b5be268 ACM |
4835 | test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data, |
4836 | skb_tailroom(tx_skb), | |
4837 | PCI_DMA_FROMDEVICE); | |
9589c77a AA |
4838 | pkt_data = skb_put(tx_skb, pkt_len); |
4839 | for (i = 0; i < pkt_len; i++) | |
4840 | pkt_data[i] = (u8)(i & 0xff); | |
9589c77a | 4841 | |
36b30ea9 | 4842 | if (!nv_optimized(np)) { |
f82a9352 SH |
4843 | np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); |
4844 | np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); | |
9589c77a | 4845 | } else { |
5bb7ea26 AV |
4846 | np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr)); |
4847 | np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr)); | |
f82a9352 | 4848 | np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); |
9589c77a AA |
4849 | } |
4850 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4851 | pci_push(get_hwbase(dev)); | |
4852 | ||
4853 | msleep(500); | |
4854 | ||
4855 | /* check for rx of the packet */ | |
36b30ea9 | 4856 | if (!nv_optimized(np)) { |
f82a9352 | 4857 | flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); |
9589c77a AA |
4858 | len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
4859 | ||
4860 | } else { | |
f82a9352 | 4861 | flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); |
9589c77a AA |
4862 | len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
4863 | } | |
4864 | ||
f82a9352 | 4865 | if (flags & NV_RX_AVAIL) { |
9589c77a AA |
4866 | ret = 0; |
4867 | } else if (np->desc_ver == DESC_VER_1) { | |
f82a9352 | 4868 | if (flags & NV_RX_ERROR) |
9589c77a AA |
4869 | ret = 0; |
4870 | } else { | |
78aea4fc | 4871 | if (flags & NV_RX2_ERROR) |
9589c77a | 4872 | ret = 0; |
9589c77a AA |
4873 | } |
4874 | ||
4875 | if (ret) { | |
4876 | if (len != pkt_len) { | |
4877 | ret = 0; | |
4878 | dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n", | |
4879 | dev->name, len, pkt_len); | |
4880 | } else { | |
761fcd9e | 4881 | rx_skb = np->rx_skb[0].skb; |
9589c77a AA |
4882 | for (i = 0; i < pkt_len; i++) { |
4883 | if (rx_skb->data[i] != (u8)(i & 0xff)) { | |
4884 | ret = 0; | |
4885 | dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n", | |
4886 | dev->name, i); | |
4887 | break; | |
4888 | } | |
4889 | } | |
4890 | } | |
4891 | } else { | |
4892 | dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name); | |
4893 | } | |
4894 | ||
73a37079 | 4895 | pci_unmap_single(np->pci_dev, test_dma_addr, |
4305b541 | 4896 | (skb_end_pointer(tx_skb) - tx_skb->data), |
9589c77a AA |
4897 | PCI_DMA_TODEVICE); |
4898 | dev_kfree_skb_any(tx_skb); | |
46798c89 | 4899 | out: |
9589c77a | 4900 | /* stop engines */ |
36b30ea9 | 4901 | nv_stop_rxtx(dev); |
9589c77a AA |
4902 | nv_txrx_reset(dev); |
4903 | /* drain rx queue */ | |
36b30ea9 | 4904 | nv_drain_rxtx(dev); |
9589c77a AA |
4905 | |
4906 | if (netif_running(dev)) { | |
4907 | writel(misc1_flags, base + NvRegMisc1); | |
4908 | writel(filter_flags, base + NvRegPacketFilterFlags); | |
4909 | nv_enable_irq(dev); | |
4910 | } | |
4911 | ||
4912 | return ret; | |
4913 | } | |
4914 | ||
4915 | static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) | |
4916 | { | |
4917 | struct fe_priv *np = netdev_priv(dev); | |
4918 | u8 __iomem *base = get_hwbase(dev); | |
4919 | int result; | |
b9f2c044 | 4920 | memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64)); |
9589c77a AA |
4921 | |
4922 | if (!nv_link_test(dev)) { | |
4923 | test->flags |= ETH_TEST_FL_FAILED; | |
4924 | buffer[0] = 1; | |
4925 | } | |
4926 | ||
4927 | if (test->flags & ETH_TEST_FL_OFFLINE) { | |
4928 | if (netif_running(dev)) { | |
4929 | netif_stop_queue(dev); | |
08d93575 | 4930 | nv_napi_disable(dev); |
58dfd9c1 | 4931 | netif_tx_lock_bh(dev); |
e308a5d8 | 4932 | netif_addr_lock(dev); |
9589c77a AA |
4933 | spin_lock_irq(&np->lock); |
4934 | nv_disable_hw_interrupts(dev, np->irqmask); | |
78aea4fc | 4935 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
9589c77a | 4936 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
78aea4fc | 4937 | else |
9589c77a | 4938 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
9589c77a | 4939 | /* stop engines */ |
36b30ea9 | 4940 | nv_stop_rxtx(dev); |
9589c77a AA |
4941 | nv_txrx_reset(dev); |
4942 | /* drain rx queue */ | |
36b30ea9 | 4943 | nv_drain_rxtx(dev); |
9589c77a | 4944 | spin_unlock_irq(&np->lock); |
e308a5d8 | 4945 | netif_addr_unlock(dev); |
58dfd9c1 | 4946 | netif_tx_unlock_bh(dev); |
9589c77a AA |
4947 | } |
4948 | ||
4949 | if (!nv_register_test(dev)) { | |
4950 | test->flags |= ETH_TEST_FL_FAILED; | |
4951 | buffer[1] = 1; | |
4952 | } | |
4953 | ||
4954 | result = nv_interrupt_test(dev); | |
4955 | if (result != 1) { | |
4956 | test->flags |= ETH_TEST_FL_FAILED; | |
4957 | buffer[2] = 1; | |
4958 | } | |
4959 | if (result == 0) { | |
4960 | /* bail out */ | |
4961 | return; | |
4962 | } | |
4963 | ||
4964 | if (!nv_loopback_test(dev)) { | |
4965 | test->flags |= ETH_TEST_FL_FAILED; | |
4966 | buffer[3] = 1; | |
4967 | } | |
4968 | ||
4969 | if (netif_running(dev)) { | |
4970 | /* reinit driver view of the rx queue */ | |
4971 | set_bufsize(dev); | |
4972 | if (nv_init_ring(dev)) { | |
4973 | if (!np->in_shutdown) | |
4974 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4975 | } | |
4976 | /* reinit nic view of the rx queue */ | |
4977 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4978 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4979 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
9589c77a AA |
4980 | base + NvRegRingSizes); |
4981 | pci_push(base); | |
4982 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4983 | pci_push(base); | |
4984 | /* restart rx engine */ | |
36b30ea9 | 4985 | nv_start_rxtx(dev); |
9589c77a | 4986 | netif_start_queue(dev); |
08d93575 | 4987 | nv_napi_enable(dev); |
9589c77a AA |
4988 | nv_enable_hw_interrupts(dev, np->irqmask); |
4989 | } | |
4990 | } | |
4991 | } | |
4992 | ||
52da3578 AA |
4993 | static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer) |
4994 | { | |
4995 | switch (stringset) { | |
4996 | case ETH_SS_STATS: | |
b9f2c044 | 4997 | memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str)); |
52da3578 | 4998 | break; |
9589c77a | 4999 | case ETH_SS_TEST: |
b9f2c044 | 5000 | memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str)); |
9589c77a | 5001 | break; |
52da3578 AA |
5002 | } |
5003 | } | |
5004 | ||
7282d491 | 5005 | static const struct ethtool_ops ops = { |
1da177e4 LT |
5006 | .get_drvinfo = nv_get_drvinfo, |
5007 | .get_link = ethtool_op_get_link, | |
5008 | .get_wol = nv_get_wol, | |
5009 | .set_wol = nv_set_wol, | |
5010 | .get_settings = nv_get_settings, | |
5011 | .set_settings = nv_set_settings, | |
dc8216c1 MS |
5012 | .get_regs_len = nv_get_regs_len, |
5013 | .get_regs = nv_get_regs, | |
5014 | .nway_reset = nv_nway_reset, | |
6a78814f | 5015 | .set_tso = nv_set_tso, |
eafa59f6 AA |
5016 | .get_ringparam = nv_get_ringparam, |
5017 | .set_ringparam = nv_set_ringparam, | |
b6d0773f AA |
5018 | .get_pauseparam = nv_get_pauseparam, |
5019 | .set_pauseparam = nv_set_pauseparam, | |
5ed2616f AA |
5020 | .get_rx_csum = nv_get_rx_csum, |
5021 | .set_rx_csum = nv_set_rx_csum, | |
5ed2616f | 5022 | .set_tx_csum = nv_set_tx_csum, |
5ed2616f | 5023 | .set_sg = nv_set_sg, |
52da3578 | 5024 | .get_strings = nv_get_strings, |
52da3578 | 5025 | .get_ethtool_stats = nv_get_ethtool_stats, |
b9f2c044 | 5026 | .get_sset_count = nv_get_sset_count, |
9589c77a | 5027 | .self_test = nv_self_test, |
1da177e4 LT |
5028 | }; |
5029 | ||
ee407b02 AA |
5030 | static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
5031 | { | |
5032 | struct fe_priv *np = get_nvpriv(dev); | |
5033 | ||
5034 | spin_lock_irq(&np->lock); | |
5035 | ||
5036 | /* save vlan group */ | |
5037 | np->vlangrp = grp; | |
5038 | ||
5039 | if (grp) { | |
5040 | /* enable vlan on MAC */ | |
5041 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; | |
5042 | } else { | |
5043 | /* disable vlan on MAC */ | |
5044 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; | |
5045 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; | |
5046 | } | |
5047 | ||
5048 | writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
5049 | ||
5050 | spin_unlock_irq(&np->lock); | |
25805dcf | 5051 | } |
ee407b02 | 5052 | |
7e680c22 AA |
5053 | /* The mgmt unit and driver use a semaphore to access the phy during init */ |
5054 | static int nv_mgmt_acquire_sema(struct net_device *dev) | |
5055 | { | |
cac1c52c | 5056 | struct fe_priv *np = netdev_priv(dev); |
7e680c22 AA |
5057 | u8 __iomem *base = get_hwbase(dev); |
5058 | int i; | |
5059 | u32 tx_ctrl, mgmt_sema; | |
5060 | ||
5061 | for (i = 0; i < 10; i++) { | |
5062 | mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; | |
5063 | if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) | |
5064 | break; | |
5065 | msleep(500); | |
5066 | } | |
5067 | ||
5068 | if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) | |
5069 | return 0; | |
5070 | ||
5071 | for (i = 0; i < 2; i++) { | |
5072 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5073 | tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; | |
5074 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
5075 | ||
5076 | /* verify that semaphore was acquired */ | |
5077 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5078 | if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && | |
cac1c52c AA |
5079 | ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { |
5080 | np->mgmt_sema = 1; | |
7e680c22 | 5081 | return 1; |
78aea4fc | 5082 | } else |
7e680c22 AA |
5083 | udelay(50); |
5084 | } | |
5085 | ||
5086 | return 0; | |
5087 | } | |
5088 | ||
cac1c52c AA |
5089 | static void nv_mgmt_release_sema(struct net_device *dev) |
5090 | { | |
5091 | struct fe_priv *np = netdev_priv(dev); | |
5092 | u8 __iomem *base = get_hwbase(dev); | |
5093 | u32 tx_ctrl; | |
5094 | ||
5095 | if (np->driver_data & DEV_HAS_MGMT_UNIT) { | |
5096 | if (np->mgmt_sema) { | |
5097 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5098 | tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ; | |
5099 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
5100 | } | |
5101 | } | |
5102 | } | |
5103 | ||
5104 | ||
5105 | static int nv_mgmt_get_version(struct net_device *dev) | |
5106 | { | |
5107 | struct fe_priv *np = netdev_priv(dev); | |
5108 | u8 __iomem *base = get_hwbase(dev); | |
5109 | u32 data_ready = readl(base + NvRegTransmitterControl); | |
5110 | u32 data_ready2 = 0; | |
5111 | unsigned long start; | |
5112 | int ready = 0; | |
5113 | ||
5114 | writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion); | |
5115 | writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl); | |
5116 | start = jiffies; | |
5117 | while (time_before(jiffies, start + 5*HZ)) { | |
5118 | data_ready2 = readl(base + NvRegTransmitterControl); | |
5119 | if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) { | |
5120 | ready = 1; | |
5121 | break; | |
5122 | } | |
5123 | schedule_timeout_uninterruptible(1); | |
5124 | } | |
5125 | ||
5126 | if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR)) | |
5127 | return 0; | |
5128 | ||
5129 | np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION; | |
5130 | ||
5131 | return 1; | |
5132 | } | |
5133 | ||
1da177e4 LT |
5134 | static int nv_open(struct net_device *dev) |
5135 | { | |
ac9c1897 | 5136 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 5137 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
5138 | int ret = 1; |
5139 | int oom, i; | |
a433686c | 5140 | u32 low; |
1da177e4 LT |
5141 | |
5142 | dprintk(KERN_DEBUG "nv_open: begin\n"); | |
5143 | ||
cb52deba ES |
5144 | /* power up phy */ |
5145 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5146 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); | |
5147 | ||
88d7d8b0 | 5148 | nv_txrx_gate(dev, false); |
f1489653 | 5149 | /* erase previous misconfiguration */ |
86a0f043 AA |
5150 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
5151 | nv_mac_reset(dev); | |
1da177e4 LT |
5152 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
5153 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5154 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5155 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5156 | writel(0, base + NvRegPacketFilterFlags); |
5157 | ||
5158 | writel(0, base + NvRegTransmitterControl); | |
5159 | writel(0, base + NvRegReceiverControl); | |
5160 | ||
5161 | writel(0, base + NvRegAdapterControl); | |
5162 | ||
eb91f61b AA |
5163 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
5164 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
5165 | ||
f1489653 | 5166 | /* initialize descriptor rings */ |
d81c0983 | 5167 | set_bufsize(dev); |
1da177e4 LT |
5168 | oom = nv_init_ring(dev); |
5169 | ||
5170 | writel(0, base + NvRegLinkSpeed); | |
5070d340 | 5171 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
1da177e4 LT |
5172 | nv_txrx_reset(dev); |
5173 | writel(0, base + NvRegUnknownSetupReg6); | |
5174 | ||
5175 | np->in_shutdown = 0; | |
5176 | ||
f1489653 | 5177 | /* give hw rings */ |
0832b25a | 5178 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
78aea4fc | 5179 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
1da177e4 LT |
5180 | base + NvRegRingSizes); |
5181 | ||
1da177e4 | 5182 | writel(np->linkspeed, base + NvRegLinkSpeed); |
95d161cb AA |
5183 | if (np->desc_ver == DESC_VER_1) |
5184 | writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); | |
5185 | else | |
5186 | writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); | |
8a4ae7f2 | 5187 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
ee407b02 | 5188 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
1da177e4 | 5189 | pci_push(base); |
8a4ae7f2 | 5190 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
5191 | reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
5192 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, | |
5193 | KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); | |
5194 | ||
7e680c22 | 5195 | writel(0, base + NvRegMIIMask); |
1da177e4 | 5196 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
eb798428 | 5197 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 | 5198 | |
1da177e4 LT |
5199 | writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
5200 | writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); | |
5201 | writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); | |
d81c0983 | 5202 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
1da177e4 LT |
5203 | |
5204 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); | |
a433686c AA |
5205 | |
5206 | get_random_bytes(&low, sizeof(low)); | |
5207 | low &= NVREG_SLOTTIME_MASK; | |
5208 | if (np->desc_ver == DESC_VER_1) { | |
5209 | writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime); | |
5210 | } else { | |
5211 | if (!(np->driver_data & DEV_HAS_GEAR_MODE)) { | |
5212 | /* setup legacy backoff */ | |
5213 | writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime); | |
5214 | } else { | |
5215 | writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime); | |
5216 | nv_gear_backoff_reseed(dev); | |
5217 | } | |
5218 | } | |
9744e218 AA |
5219 | writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); |
5220 | writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); | |
a971c324 AA |
5221 | if (poll_interval == -1) { |
5222 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) | |
5223 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | |
5224 | else | |
5225 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
78aea4fc | 5226 | } else |
a971c324 | 5227 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); |
1da177e4 LT |
5228 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
5229 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, | |
5230 | base + NvRegAdapterControl); | |
5231 | writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); | |
7e680c22 | 5232 | writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); |
c42d9df9 AA |
5233 | if (np->wolenabled) |
5234 | writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); | |
1da177e4 LT |
5235 | |
5236 | i = readl(base + NvRegPowerState); | |
78aea4fc | 5237 | if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) |
1da177e4 LT |
5238 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); |
5239 | ||
5240 | pci_push(base); | |
5241 | udelay(10); | |
5242 | writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); | |
5243 | ||
84b3932b | 5244 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5245 | pci_push(base); |
eb798428 | 5246 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 LT |
5247 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
5248 | pci_push(base); | |
5249 | ||
78aea4fc | 5250 | if (nv_request_irq(dev, 0)) |
84b3932b | 5251 | goto out_drain; |
1da177e4 LT |
5252 | |
5253 | /* ask for interrupts */ | |
84b3932b | 5254 | nv_enable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
5255 | |
5256 | spin_lock_irq(&np->lock); | |
5257 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); | |
5258 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5259 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5260 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5261 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
5262 | /* One manual link speed update: Interrupts are enabled, future link | |
5263 | * speed changes cause interrupts and are handled by nv_link_irq(). | |
5264 | */ | |
5265 | { | |
5266 | u32 miistat; | |
5267 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 5268 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 LT |
5269 | dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat); |
5270 | } | |
1b1b3c9b MS |
5271 | /* set linkspeed to invalid value, thus force nv_update_linkspeed |
5272 | * to init hw */ | |
5273 | np->linkspeed = 0; | |
1da177e4 | 5274 | ret = nv_update_linkspeed(dev); |
36b30ea9 | 5275 | nv_start_rxtx(dev); |
1da177e4 | 5276 | netif_start_queue(dev); |
08d93575 | 5277 | nv_napi_enable(dev); |
e27cdba5 | 5278 | |
1da177e4 LT |
5279 | if (ret) { |
5280 | netif_carrier_on(dev); | |
5281 | } else { | |
f7ab697d | 5282 | printk(KERN_INFO "%s: no link during initialization.\n", dev->name); |
1da177e4 LT |
5283 | netif_carrier_off(dev); |
5284 | } | |
5285 | if (oom) | |
5286 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
52da3578 AA |
5287 | |
5288 | /* start statistics timer */ | |
9c662435 | 5289 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
bfebbb88 DD |
5290 | mod_timer(&np->stats_poll, |
5291 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 | 5292 | |
1da177e4 LT |
5293 | spin_unlock_irq(&np->lock); |
5294 | ||
5295 | return 0; | |
5296 | out_drain: | |
36b30ea9 | 5297 | nv_drain_rxtx(dev); |
1da177e4 LT |
5298 | return ret; |
5299 | } | |
5300 | ||
5301 | static int nv_close(struct net_device *dev) | |
5302 | { | |
ac9c1897 | 5303 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
5304 | u8 __iomem *base; |
5305 | ||
5306 | spin_lock_irq(&np->lock); | |
5307 | np->in_shutdown = 1; | |
5308 | spin_unlock_irq(&np->lock); | |
08d93575 | 5309 | nv_napi_disable(dev); |
a7475906 | 5310 | synchronize_irq(np->pci_dev->irq); |
1da177e4 LT |
5311 | |
5312 | del_timer_sync(&np->oom_kick); | |
5313 | del_timer_sync(&np->nic_poll); | |
52da3578 | 5314 | del_timer_sync(&np->stats_poll); |
1da177e4 LT |
5315 | |
5316 | netif_stop_queue(dev); | |
5317 | spin_lock_irq(&np->lock); | |
36b30ea9 | 5318 | nv_stop_rxtx(dev); |
1da177e4 LT |
5319 | nv_txrx_reset(dev); |
5320 | ||
5321 | /* disable interrupts on the nic or we will lock up */ | |
5322 | base = get_hwbase(dev); | |
84b3932b | 5323 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
5324 | pci_push(base); |
5325 | dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); | |
5326 | ||
5327 | spin_unlock_irq(&np->lock); | |
5328 | ||
84b3932b | 5329 | nv_free_irq(dev); |
1da177e4 | 5330 | |
36b30ea9 | 5331 | nv_drain_rxtx(dev); |
1da177e4 | 5332 | |
5a9a8e32 | 5333 | if (np->wolenabled || !phy_power_down) { |
88d7d8b0 | 5334 | nv_txrx_gate(dev, false); |
2cc49a5c | 5335 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
1da177e4 | 5336 | nv_start_rx(dev); |
cb52deba ES |
5337 | } else { |
5338 | /* power down phy */ | |
5339 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5340 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); | |
88d7d8b0 | 5341 | nv_txrx_gate(dev, true); |
2cc49a5c | 5342 | } |
1da177e4 LT |
5343 | |
5344 | /* FIXME: power down nic */ | |
5345 | ||
5346 | return 0; | |
5347 | } | |
5348 | ||
b94426bd SH |
5349 | static const struct net_device_ops nv_netdev_ops = { |
5350 | .ndo_open = nv_open, | |
5351 | .ndo_stop = nv_close, | |
5352 | .ndo_get_stats = nv_get_stats, | |
00829823 SH |
5353 | .ndo_start_xmit = nv_start_xmit, |
5354 | .ndo_tx_timeout = nv_tx_timeout, | |
5355 | .ndo_change_mtu = nv_change_mtu, | |
5356 | .ndo_validate_addr = eth_validate_addr, | |
5357 | .ndo_set_mac_address = nv_set_mac_address, | |
5358 | .ndo_set_multicast_list = nv_set_multicast, | |
5359 | .ndo_vlan_rx_register = nv_vlan_rx_register, | |
5360 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5361 | .ndo_poll_controller = nv_poll_controller, | |
5362 | #endif | |
5363 | }; | |
5364 | ||
5365 | static const struct net_device_ops nv_netdev_ops_optimized = { | |
5366 | .ndo_open = nv_open, | |
5367 | .ndo_stop = nv_close, | |
5368 | .ndo_get_stats = nv_get_stats, | |
5369 | .ndo_start_xmit = nv_start_xmit_optimized, | |
b94426bd SH |
5370 | .ndo_tx_timeout = nv_tx_timeout, |
5371 | .ndo_change_mtu = nv_change_mtu, | |
5372 | .ndo_validate_addr = eth_validate_addr, | |
5373 | .ndo_set_mac_address = nv_set_mac_address, | |
5374 | .ndo_set_multicast_list = nv_set_multicast, | |
5375 | .ndo_vlan_rx_register = nv_vlan_rx_register, | |
5376 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5377 | .ndo_poll_controller = nv_poll_controller, | |
5378 | #endif | |
5379 | }; | |
5380 | ||
1da177e4 LT |
5381 | static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) |
5382 | { | |
5383 | struct net_device *dev; | |
5384 | struct fe_priv *np; | |
5385 | unsigned long addr; | |
5386 | u8 __iomem *base; | |
5387 | int err, i; | |
5070d340 | 5388 | u32 powerstate, txreg; |
7e680c22 AA |
5389 | u32 phystate_orig = 0, phystate; |
5390 | int phyinitialized = 0; | |
3f88ce49 JG |
5391 | static int printed_version; |
5392 | ||
5393 | if (!printed_version++) | |
5394 | printk(KERN_INFO "%s: Reverse Engineered nForce ethernet" | |
5395 | " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION); | |
1da177e4 LT |
5396 | |
5397 | dev = alloc_etherdev(sizeof(struct fe_priv)); | |
5398 | err = -ENOMEM; | |
5399 | if (!dev) | |
5400 | goto out; | |
5401 | ||
ac9c1897 | 5402 | np = netdev_priv(dev); |
bea3348e | 5403 | np->dev = dev; |
1da177e4 LT |
5404 | np->pci_dev = pci_dev; |
5405 | spin_lock_init(&np->lock); | |
1da177e4 LT |
5406 | SET_NETDEV_DEV(dev, &pci_dev->dev); |
5407 | ||
5408 | init_timer(&np->oom_kick); | |
5409 | np->oom_kick.data = (unsigned long) dev; | |
c061b18d | 5410 | np->oom_kick.function = nv_do_rx_refill; /* timer handler */ |
1da177e4 LT |
5411 | init_timer(&np->nic_poll); |
5412 | np->nic_poll.data = (unsigned long) dev; | |
c061b18d | 5413 | np->nic_poll.function = nv_do_nic_poll; /* timer handler */ |
52da3578 AA |
5414 | init_timer(&np->stats_poll); |
5415 | np->stats_poll.data = (unsigned long) dev; | |
c061b18d | 5416 | np->stats_poll.function = nv_do_stats_poll; /* timer handler */ |
1da177e4 LT |
5417 | |
5418 | err = pci_enable_device(pci_dev); | |
3f88ce49 | 5419 | if (err) |
1da177e4 | 5420 | goto out_free; |
1da177e4 LT |
5421 | |
5422 | pci_set_master(pci_dev); | |
5423 | ||
5424 | err = pci_request_regions(pci_dev, DRV_NAME); | |
5425 | if (err < 0) | |
5426 | goto out_disable; | |
5427 | ||
9c662435 | 5428 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
57fff698 AA |
5429 | np->register_size = NV_PCI_REGSZ_VER3; |
5430 | else if (id->driver_data & DEV_HAS_STATISTICS_V1) | |
86a0f043 AA |
5431 | np->register_size = NV_PCI_REGSZ_VER2; |
5432 | else | |
5433 | np->register_size = NV_PCI_REGSZ_VER1; | |
5434 | ||
1da177e4 LT |
5435 | err = -EINVAL; |
5436 | addr = 0; | |
5437 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
5438 | dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n", | |
78aea4fc | 5439 | pci_name(pci_dev), i, (void *)pci_resource_start(pci_dev, i), |
1da177e4 LT |
5440 | pci_resource_len(pci_dev, i), |
5441 | pci_resource_flags(pci_dev, i)); | |
5442 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && | |
86a0f043 | 5443 | pci_resource_len(pci_dev, i) >= np->register_size) { |
1da177e4 LT |
5444 | addr = pci_resource_start(pci_dev, i); |
5445 | break; | |
5446 | } | |
5447 | } | |
5448 | if (i == DEVICE_COUNT_RESOURCE) { | |
3f88ce49 JG |
5449 | dev_printk(KERN_INFO, &pci_dev->dev, |
5450 | "Couldn't find register window\n"); | |
1da177e4 LT |
5451 | goto out_relreg; |
5452 | } | |
5453 | ||
86a0f043 AA |
5454 | /* copy of driver data */ |
5455 | np->driver_data = id->driver_data; | |
9f3f7910 AA |
5456 | /* copy of device id */ |
5457 | np->device_id = id->device; | |
86a0f043 | 5458 | |
1da177e4 | 5459 | /* handle different descriptor versions */ |
ee73362c MS |
5460 | if (id->driver_data & DEV_HAS_HIGH_DMA) { |
5461 | /* packet format 3: supports 40-bit addressing */ | |
5462 | np->desc_ver = DESC_VER_3; | |
84b3932b | 5463 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
69fe3fd7 | 5464 | if (dma_64bit) { |
6afd142f | 5465 | if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39))) |
3f88ce49 JG |
5466 | dev_printk(KERN_INFO, &pci_dev->dev, |
5467 | "64-bit DMA failed, using 32-bit addressing\n"); | |
5468 | else | |
69fe3fd7 | 5469 | dev->features |= NETIF_F_HIGHDMA; |
6afd142f | 5470 | if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) { |
3f88ce49 JG |
5471 | dev_printk(KERN_INFO, &pci_dev->dev, |
5472 | "64-bit DMA (consistent) failed, using 32-bit ring buffers\n"); | |
69fe3fd7 | 5473 | } |
ee73362c MS |
5474 | } |
5475 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { | |
5476 | /* packet format 2: supports jumbo frames */ | |
1da177e4 | 5477 | np->desc_ver = DESC_VER_2; |
8a4ae7f2 | 5478 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
ee73362c MS |
5479 | } else { |
5480 | /* original packet format */ | |
5481 | np->desc_ver = DESC_VER_1; | |
8a4ae7f2 | 5482 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
d81c0983 | 5483 | } |
ee73362c MS |
5484 | |
5485 | np->pkt_limit = NV_PKTLIMIT_1; | |
5486 | if (id->driver_data & DEV_HAS_LARGEDESC) | |
5487 | np->pkt_limit = NV_PKTLIMIT_2; | |
5488 | ||
8a4ae7f2 | 5489 | if (id->driver_data & DEV_HAS_CHECKSUM) { |
f2ad2d9b | 5490 | np->rx_csum = 1; |
8a4ae7f2 | 5491 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
edcfe5f7 | 5492 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
fa45459e | 5493 | dev->features |= NETIF_F_TSO; |
53f224cc | 5494 | dev->features |= NETIF_F_GRO; |
21828163 | 5495 | } |
8a4ae7f2 | 5496 | |
ee407b02 AA |
5497 | np->vlanctl_bits = 0; |
5498 | if (id->driver_data & DEV_HAS_VLAN) { | |
5499 | np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; | |
5500 | dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; | |
ee407b02 AA |
5501 | } |
5502 | ||
b6d0773f | 5503 | np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; |
5289b4c4 AA |
5504 | if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) || |
5505 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) || | |
5506 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) { | |
b6d0773f | 5507 | np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; |
eb91f61b | 5508 | } |
f3b197ac | 5509 | |
eb91f61b | 5510 | |
1da177e4 | 5511 | err = -ENOMEM; |
86a0f043 | 5512 | np->base = ioremap(addr, np->register_size); |
1da177e4 LT |
5513 | if (!np->base) |
5514 | goto out_relreg; | |
5515 | dev->base_addr = (unsigned long)np->base; | |
ee73362c | 5516 | |
1da177e4 | 5517 | dev->irq = pci_dev->irq; |
ee73362c | 5518 | |
eafa59f6 AA |
5519 | np->rx_ring_size = RX_RING_DEFAULT; |
5520 | np->tx_ring_size = TX_RING_DEFAULT; | |
eafa59f6 | 5521 | |
36b30ea9 | 5522 | if (!nv_optimized(np)) { |
ee73362c | 5523 | np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
eafa59f6 | 5524 | sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5525 | &np->ring_addr); |
5526 | if (!np->rx_ring.orig) | |
5527 | goto out_unmap; | |
eafa59f6 | 5528 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
ee73362c MS |
5529 | } else { |
5530 | np->rx_ring.ex = pci_alloc_consistent(pci_dev, | |
eafa59f6 | 5531 | sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5532 | &np->ring_addr); |
5533 | if (!np->rx_ring.ex) | |
5534 | goto out_unmap; | |
eafa59f6 AA |
5535 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
5536 | } | |
dd00cc48 YP |
5537 | np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); |
5538 | np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); | |
761fcd9e | 5539 | if (!np->rx_skb || !np->tx_skb) |
eafa59f6 | 5540 | goto out_freering; |
1da177e4 | 5541 | |
36b30ea9 | 5542 | if (!nv_optimized(np)) |
00829823 | 5543 | dev->netdev_ops = &nv_netdev_ops; |
86b22b0d | 5544 | else |
00829823 | 5545 | dev->netdev_ops = &nv_netdev_ops_optimized; |
b94426bd | 5546 | |
bea3348e | 5547 | netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP); |
1da177e4 | 5548 | SET_ETHTOOL_OPS(dev, &ops); |
1da177e4 LT |
5549 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
5550 | ||
5551 | pci_set_drvdata(pci_dev, dev); | |
5552 | ||
5553 | /* read the mac address */ | |
5554 | base = get_hwbase(dev); | |
5555 | np->orig_mac[0] = readl(base + NvRegMacAddrA); | |
5556 | np->orig_mac[1] = readl(base + NvRegMacAddrB); | |
5557 | ||
5070d340 AA |
5558 | /* check the workaround bit for correct mac address order */ |
5559 | txreg = readl(base + NvRegTransmitPoll); | |
a376e79c | 5560 | if (id->driver_data & DEV_HAS_CORRECT_MACADDR) { |
5070d340 AA |
5561 | /* mac address is already in correct order */ |
5562 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5563 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5564 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5565 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5566 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5567 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
a376e79c AA |
5568 | } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { |
5569 | /* mac address is already in correct order */ | |
5570 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5571 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5572 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5573 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5574 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5575 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
5576 | /* | |
5577 | * Set orig mac address back to the reversed version. | |
5578 | * This flag will be cleared during low power transition. | |
5579 | * Therefore, we should always put back the reversed address. | |
5580 | */ | |
5581 | np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) + | |
5582 | (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24); | |
5583 | np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8); | |
5070d340 AA |
5584 | } else { |
5585 | /* need to reverse mac address to correct order */ | |
5586 | dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; | |
5587 | dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; | |
5588 | dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; | |
5589 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; | |
5590 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | |
5591 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | |
5070d340 | 5592 | writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
f55c21fd | 5593 | printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n"); |
5070d340 | 5594 | } |
c704b856 | 5595 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 5596 | |
c704b856 | 5597 | if (!is_valid_ether_addr(dev->perm_addr)) { |
1da177e4 LT |
5598 | /* |
5599 | * Bad mac address. At least one bios sets the mac address | |
5600 | * to 01:23:45:67:89:ab | |
5601 | */ | |
3f88ce49 | 5602 | dev_printk(KERN_ERR, &pci_dev->dev, |
e174961c | 5603 | "Invalid Mac address detected: %pM\n", |
78aea4fc | 5604 | dev->dev_addr); |
3f88ce49 JG |
5605 | dev_printk(KERN_ERR, &pci_dev->dev, |
5606 | "Please complain to your hardware vendor. Switching to a random MAC.\n"); | |
655a6595 | 5607 | random_ether_addr(dev->dev_addr); |
1da177e4 LT |
5608 | } |
5609 | ||
e174961c JB |
5610 | dprintk(KERN_DEBUG "%s: MAC Address %pM\n", |
5611 | pci_name(pci_dev), dev->dev_addr); | |
1da177e4 | 5612 | |
f1489653 AA |
5613 | /* set mac address */ |
5614 | nv_copy_mac_to_hw(dev); | |
5615 | ||
9a60a826 TD |
5616 | /* Workaround current PCI init glitch: wakeup bits aren't |
5617 | * being set from PCI PM capability. | |
5618 | */ | |
5619 | device_init_wakeup(&pci_dev->dev, 1); | |
5620 | ||
1da177e4 LT |
5621 | /* disable WOL */ |
5622 | writel(0, base + NvRegWakeUpFlags); | |
5623 | np->wolenabled = 0; | |
5624 | ||
86a0f043 | 5625 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
86a0f043 AA |
5626 | |
5627 | /* take phy and nic out of low power mode */ | |
5628 | powerstate = readl(base + NvRegPowerState2); | |
5629 | powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; | |
3c2e1c11 | 5630 | if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) && |
44c10138 | 5631 | pci_dev->revision >= 0xA3) |
86a0f043 AA |
5632 | powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; |
5633 | writel(powerstate, base + NvRegPowerState2); | |
5634 | } | |
5635 | ||
78aea4fc | 5636 | if (np->desc_ver == DESC_VER_1) |
ac9c1897 | 5637 | np->tx_flags = NV_TX_VALID; |
78aea4fc | 5638 | else |
ac9c1897 | 5639 | np->tx_flags = NV_TX2_VALID; |
9e184767 AA |
5640 | |
5641 | np->msi_flags = 0; | |
78aea4fc | 5642 | if ((id->driver_data & DEV_HAS_MSI) && msi) |
9e184767 | 5643 | np->msi_flags |= NV_MSI_CAPABLE; |
78aea4fc | 5644 | |
9e184767 AA |
5645 | if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
5646 | /* msix has had reported issues when modifying irqmask | |
5647 | as in the case of napi, therefore, disable for now | |
5648 | */ | |
0a12761b | 5649 | #if 0 |
9e184767 AA |
5650 | np->msi_flags |= NV_MSI_X_CAPABLE; |
5651 | #endif | |
5652 | } | |
5653 | ||
5654 | if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) { | |
a971c324 | 5655 | np->irqmask = NVREG_IRQMASK_CPU; |
d33a73c8 AA |
5656 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5657 | np->msi_flags |= 0x0001; | |
9e184767 AA |
5658 | } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC && |
5659 | !(id->driver_data & DEV_NEED_TIMERIRQ)) { | |
5660 | /* start off in throughput mode */ | |
5661 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
5662 | /* remove support for msix mode */ | |
5663 | np->msi_flags &= ~NV_MSI_X_CAPABLE; | |
5664 | } else { | |
5665 | optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; | |
5666 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
5667 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ | |
5668 | np->msi_flags |= 0x0003; | |
d33a73c8 | 5669 | } |
a971c324 | 5670 | |
1da177e4 LT |
5671 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
5672 | np->irqmask |= NVREG_IRQ_TIMER; | |
5673 | if (id->driver_data & DEV_NEED_LINKTIMER) { | |
5674 | dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev)); | |
5675 | np->need_linktimer = 1; | |
5676 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
5677 | } else { | |
5678 | dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev)); | |
5679 | np->need_linktimer = 0; | |
5680 | } | |
5681 | ||
3b446c3e AA |
5682 | /* Limit the number of tx's outstanding for hw bug */ |
5683 | if (id->driver_data & DEV_NEED_TX_LIMIT) { | |
5684 | np->tx_limit = 1; | |
5c659322 | 5685 | if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) && |
3b446c3e AA |
5686 | pci_dev->revision >= 0xA2) |
5687 | np->tx_limit = 0; | |
5688 | } | |
5689 | ||
7e680c22 AA |
5690 | /* clear phy state and temporarily halt phy interrupts */ |
5691 | writel(0, base + NvRegMIIMask); | |
5692 | phystate = readl(base + NvRegAdapterControl); | |
5693 | if (phystate & NVREG_ADAPTCTL_RUNNING) { | |
5694 | phystate_orig = 1; | |
5695 | phystate &= ~NVREG_ADAPTCTL_RUNNING; | |
5696 | writel(phystate, base + NvRegAdapterControl); | |
5697 | } | |
eb798428 | 5698 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
7e680c22 AA |
5699 | |
5700 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { | |
7e680c22 | 5701 | /* management unit running on the mac? */ |
cac1c52c AA |
5702 | if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) && |
5703 | (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) && | |
5704 | nv_mgmt_acquire_sema(dev) && | |
5705 | nv_mgmt_get_version(dev)) { | |
5706 | np->mac_in_use = 1; | |
78aea4fc | 5707 | if (np->mgmt_version > 0) |
cac1c52c | 5708 | np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; |
cac1c52c AA |
5709 | dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", |
5710 | pci_name(pci_dev), np->mac_in_use); | |
5711 | /* management unit setup the phy already? */ | |
5712 | if (np->mac_in_use && | |
5713 | ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == | |
5714 | NVREG_XMITCTL_SYNC_PHY_INIT)) { | |
5715 | /* phy is inited by mgmt unit */ | |
5716 | phyinitialized = 1; | |
5717 | dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", | |
5718 | pci_name(pci_dev)); | |
5719 | } else { | |
5720 | /* we need to init the phy */ | |
7e680c22 AA |
5721 | } |
5722 | } | |
5723 | } | |
5724 | ||
1da177e4 | 5725 | /* find a suitable phy */ |
7a33e45a | 5726 | for (i = 1; i <= 32; i++) { |
1da177e4 | 5727 | int id1, id2; |
7a33e45a | 5728 | int phyaddr = i & 0x1F; |
1da177e4 LT |
5729 | |
5730 | spin_lock_irq(&np->lock); | |
7a33e45a | 5731 | id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
1da177e4 LT |
5732 | spin_unlock_irq(&np->lock); |
5733 | if (id1 < 0 || id1 == 0xffff) | |
5734 | continue; | |
5735 | spin_lock_irq(&np->lock); | |
7a33e45a | 5736 | id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
1da177e4 LT |
5737 | spin_unlock_irq(&np->lock); |
5738 | if (id2 < 0 || id2 == 0xffff) | |
5739 | continue; | |
5740 | ||
edf7e5ec | 5741 | np->phy_model = id2 & PHYID2_MODEL_MASK; |
1da177e4 LT |
5742 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
5743 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; | |
5744 | dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", | |
7a33e45a AA |
5745 | pci_name(pci_dev), id1, id2, phyaddr); |
5746 | np->phyaddr = phyaddr; | |
1da177e4 | 5747 | np->phy_oui = id1 | id2; |
9f3f7910 AA |
5748 | |
5749 | /* Realtek hardcoded phy id1 to all zero's on certain phys */ | |
5750 | if (np->phy_oui == PHY_OUI_REALTEK2) | |
5751 | np->phy_oui = PHY_OUI_REALTEK; | |
5752 | /* Setup phy revision for Realtek */ | |
5753 | if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211) | |
5754 | np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; | |
5755 | ||
1da177e4 LT |
5756 | break; |
5757 | } | |
7a33e45a | 5758 | if (i == 33) { |
3f88ce49 JG |
5759 | dev_printk(KERN_INFO, &pci_dev->dev, |
5760 | "open: Could not find a valid PHY.\n"); | |
eafa59f6 | 5761 | goto out_error; |
1da177e4 | 5762 | } |
f3b197ac | 5763 | |
7e680c22 AA |
5764 | if (!phyinitialized) { |
5765 | /* reset it */ | |
5766 | phy_init(dev); | |
f35723ec AA |
5767 | } else { |
5768 | /* see if it is a gigabit phy */ | |
5769 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
78aea4fc | 5770 | if (mii_status & PHY_GIGABIT) |
f35723ec | 5771 | np->gigabit = PHY_GIGABIT; |
7e680c22 | 5772 | } |
1da177e4 LT |
5773 | |
5774 | /* set default link speed settings */ | |
5775 | np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
5776 | np->duplex = 0; | |
5777 | np->autoneg = 1; | |
5778 | ||
5779 | err = register_netdev(dev); | |
5780 | if (err) { | |
3f88ce49 JG |
5781 | dev_printk(KERN_INFO, &pci_dev->dev, |
5782 | "unable to register netdev: %d\n", err); | |
eafa59f6 | 5783 | goto out_error; |
1da177e4 | 5784 | } |
3f88ce49 JG |
5785 | |
5786 | dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, " | |
5787 | "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", | |
5788 | dev->name, | |
5789 | np->phy_oui, | |
5790 | np->phyaddr, | |
5791 | dev->dev_addr[0], | |
5792 | dev->dev_addr[1], | |
5793 | dev->dev_addr[2], | |
5794 | dev->dev_addr[3], | |
5795 | dev->dev_addr[4], | |
5796 | dev->dev_addr[5]); | |
5797 | ||
5798 | dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", | |
78aea4fc SJ |
5799 | dev->features & NETIF_F_HIGHDMA ? "highdma " : "", |
5800 | dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? | |
5801 | "csum " : "", | |
5802 | dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ? | |
5803 | "vlan " : "", | |
5804 | id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", | |
5805 | id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "", | |
5806 | id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "", | |
5807 | np->gigabit == PHY_GIGABIT ? "gbit " : "", | |
5808 | np->need_linktimer ? "lnktim " : "", | |
5809 | np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", | |
5810 | np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", | |
5811 | np->desc_ver); | |
1da177e4 LT |
5812 | |
5813 | return 0; | |
5814 | ||
eafa59f6 | 5815 | out_error: |
7e680c22 AA |
5816 | if (phystate_orig) |
5817 | writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); | |
1da177e4 | 5818 | pci_set_drvdata(pci_dev, NULL); |
eafa59f6 AA |
5819 | out_freering: |
5820 | free_rings(dev); | |
1da177e4 LT |
5821 | out_unmap: |
5822 | iounmap(get_hwbase(dev)); | |
5823 | out_relreg: | |
5824 | pci_release_regions(pci_dev); | |
5825 | out_disable: | |
5826 | pci_disable_device(pci_dev); | |
5827 | out_free: | |
5828 | free_netdev(dev); | |
5829 | out: | |
5830 | return err; | |
5831 | } | |
5832 | ||
9f3f7910 AA |
5833 | static void nv_restore_phy(struct net_device *dev) |
5834 | { | |
5835 | struct fe_priv *np = netdev_priv(dev); | |
5836 | u16 phy_reserved, mii_control; | |
5837 | ||
5838 | if (np->phy_oui == PHY_OUI_REALTEK && | |
5839 | np->phy_model == PHY_MODEL_REALTEK_8201 && | |
5840 | phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
5841 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); | |
5842 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | |
5843 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
5844 | phy_reserved |= PHY_REALTEK_INIT8; | |
5845 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); | |
5846 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); | |
5847 | ||
5848 | /* restart auto negotiation */ | |
5849 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
5850 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); | |
5851 | mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); | |
5852 | } | |
5853 | } | |
5854 | ||
f55c21fd | 5855 | static void nv_restore_mac_addr(struct pci_dev *pci_dev) |
1da177e4 LT |
5856 | { |
5857 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
f1489653 AA |
5858 | struct fe_priv *np = netdev_priv(dev); |
5859 | u8 __iomem *base = get_hwbase(dev); | |
1da177e4 | 5860 | |
f1489653 AA |
5861 | /* special op: write back the misordered MAC address - otherwise |
5862 | * the next nv_probe would see a wrong address. | |
5863 | */ | |
5864 | writel(np->orig_mac[0], base + NvRegMacAddrA); | |
5865 | writel(np->orig_mac[1], base + NvRegMacAddrB); | |