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Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
4fa9c49f 1// SPDX-License-Identifier: GPL-2.0-only
47dd7a54
GC		 2/*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
5
286a8372 6 Copyright(C) 2007-2011 STMicroelectronics Ltd
47dd7a54 7
47dd7a54
GC		 8
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10
11 Documentation available at:
12 http://www.stlinux.com
13 Support available at:
14 https://bugzilla.stlinux.com/
15*******************************************************************************/
16
6a81c26f 17#include <linux/clk.h>
47dd7a54
GC		 18#include <linux/kernel.h>
19#include <linux/interrupt.h>
47dd7a54
GC		 20#include <linux/ip.h>
21#include <linux/tcp.h>
22#include <linux/skbuff.h>
23#include <linux/ethtool.h>
24#include <linux/if_ether.h>
25#include <linux/crc32.h>
26#include <linux/mii.h>
01789349 27#include <linux/if.h>
47dd7a54
GC		 28#include <linux/if_vlan.h>
29#include <linux/dma-mapping.h>
5a0e3ad6 30#include <linux/slab.h>
70c71606 31#include <linux/prefetch.h>
db88f10a 32#include <linux/pinctrl/consumer.h>
50fb4f74 33#ifdef CONFIG_DEBUG_FS
7ac29055
GC		 34#include <linux/debugfs.h>
35#include <linux/seq_file.h>
50fb4f74 36#endif /* CONFIG_DEBUG_FS */
891434b1 37#include <linux/net_tstamp.h>
eeef2f6b 38#include <linux/phylink.h>
b7766206 39#include <linux/udp.h>
4dbbe8dd 40#include <net/pkt_cls.h>
891434b1 41#include "stmmac_ptp.h"
286a8372 42#include "stmmac.h"
c5e4ddbd 43#include <linux/reset.h>
5790cf3c 44#include <linux/of_mdio.h>
19d857c9 45#include "dwmac1000.h"
7d9e6c5a 46#include "dwxgmac2.h"
42de047d 47#include "hwif.h"
47dd7a54 48
9939a46d 49#define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
f748be53 50#define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
47dd7a54
GC		 51
52/* Module parameters */
32ceabca 53#define TX_TIMEO 5000
47dd7a54 54static int watchdog = TX_TIMEO;
d3757ba4 55module_param(watchdog, int, 0644);
32ceabca 56MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
47dd7a54 57
32ceabca 58static int debug = -1;
d3757ba4 59module_param(debug, int, 0644);
32ceabca 60MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
47dd7a54 61
47d1f71f 62static int phyaddr = -1;
d3757ba4 63module_param(phyaddr, int, 0444);
47dd7a54
GC		 64MODULE_PARM_DESC(phyaddr, "Physical device address");
65
e3ad57c9 66#define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
120e87f9 67#define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
47dd7a54 68
e9989339 69static int flow_ctrl = FLOW_AUTO;
d3757ba4 70module_param(flow_ctrl, int, 0644);
47dd7a54
GC		 71MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
72
73static int pause = PAUSE_TIME;
d3757ba4 74module_param(pause, int, 0644);
47dd7a54
GC		 75MODULE_PARM_DESC(pause, "Flow Control Pause Time");
76
77#define TC_DEFAULT 64
78static int tc = TC_DEFAULT;
d3757ba4 79module_param(tc, int, 0644);
47dd7a54
GC		 80MODULE_PARM_DESC(tc, "DMA threshold control value");
81
d916701c
GC		 82#define DEFAULT_BUFSIZE 1536
83static int buf_sz = DEFAULT_BUFSIZE;
d3757ba4 84module_param(buf_sz, int, 0644);
47dd7a54
GC		 85MODULE_PARM_DESC(buf_sz, "DMA buffer size");
86
22ad3838
GC		 87#define STMMAC_RX_COPYBREAK 256
88
47dd7a54
GC		 89static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
90 NETIF_MSG_LINK | NETIF_MSG_IFUP |
91 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
92
d765955d
GC		 93#define STMMAC_DEFAULT_LPI_TIMER 1000
94static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
d3757ba4 95module_param(eee_timer, int, 0644);
d765955d 96MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
f5351ef7 97#define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
d765955d 98
22d3efe5
PM		 99/* By default the driver will use the ring mode to manage tx and rx descriptors,
100 * but allow user to force to use the chain instead of the ring
4a7d666a
GC		 101 */
102static unsigned int chain_mode;
d3757ba4 103module_param(chain_mode, int, 0444);
4a7d666a
GC		 104MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
105
47dd7a54 106static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54 107
50fb4f74 108#ifdef CONFIG_DEBUG_FS
8d72ab11 109static void stmmac_init_fs(struct net_device *dev);
466c5ac8 110static void stmmac_exit_fs(struct net_device *dev);
bfab27a1
GC		 111#endif
112
9125cdd1
GC		 113#define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
114
47dd7a54
GC		 115/**
116 * stmmac_verify_args - verify the driver parameters.
732fdf0e
GC		 117 * Description: it checks the driver parameters and set a default in case of
118 * errors.
47dd7a54
GC		 119 */
120static void stmmac_verify_args(void)
121{
122 if (unlikely(watchdog < 0))
123 watchdog = TX_TIMEO;
d916701c
GC		 124 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
125 buf_sz = DEFAULT_BUFSIZE;
47dd7a54
GC		 126 if (unlikely(flow_ctrl > 1))
127 flow_ctrl = FLOW_AUTO;
128 else if (likely(flow_ctrl < 0))
129 flow_ctrl = FLOW_OFF;
130 if (unlikely((pause < 0) || (pause > 0xffff)))
131 pause = PAUSE_TIME;
d765955d
GC		 132 if (eee_timer < 0)
133 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
47dd7a54
GC		 134}
135
c22a3f48
JP		 136/**
137 * stmmac_disable_all_queues - Disable all queues
138 * @priv: driver private structure
139 */
140static void stmmac_disable_all_queues(struct stmmac_priv *priv)
141{
142 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
8fce3331
JA		 143 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
144 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
c22a3f48
JP		 145 u32 queue;
146
8fce3331
JA		 147 for (queue = 0; queue < maxq; queue++) {
148 struct stmmac_channel *ch = &priv->channel[queue];
c22a3f48 149
4ccb4585
JA		 150 if (queue < rx_queues_cnt)
151 napi_disable(&ch->rx_napi);
152 if (queue < tx_queues_cnt)
153 napi_disable(&ch->tx_napi);
c22a3f48
JP		 154 }
155}
156
157/**
158 * stmmac_enable_all_queues - Enable all queues
159 * @priv: driver private structure
160 */
161static void stmmac_enable_all_queues(struct stmmac_priv *priv)
162{
163 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
8fce3331
JA		 164 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
165 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
c22a3f48
JP		 166 u32 queue;
167
8fce3331
JA		 168 for (queue = 0; queue < maxq; queue++) {
169 struct stmmac_channel *ch = &priv->channel[queue];
c22a3f48 170
4ccb4585
JA		 171 if (queue < rx_queues_cnt)
172 napi_enable(&ch->rx_napi);
173 if (queue < tx_queues_cnt)
174 napi_enable(&ch->tx_napi);
c22a3f48
JP		 175 }
176}
177
178/**
179 * stmmac_stop_all_queues - Stop all queues
180 * @priv: driver private structure
181 */
182static void stmmac_stop_all_queues(struct stmmac_priv *priv)
183{
184 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
185 u32 queue;
186
187 for (queue = 0; queue < tx_queues_cnt; queue++)
188 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
189}
190
191/**
192 * stmmac_start_all_queues - Start all queues
193 * @priv: driver private structure
194 */
195static void stmmac_start_all_queues(struct stmmac_priv *priv)
196{
197 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
198 u32 queue;
199
200 for (queue = 0; queue < tx_queues_cnt; queue++)
201 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
202}
203
34877a15
JA		 204static void stmmac_service_event_schedule(struct stmmac_priv *priv)
205{
206 if (!test_bit(STMMAC_DOWN, &priv->state) &&
207 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
208 queue_work(priv->wq, &priv->service_task);
209}
210
211static void stmmac_global_err(struct stmmac_priv *priv)
212{
213 netif_carrier_off(priv->dev);
214 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
215 stmmac_service_event_schedule(priv);
216}
217
32ceabca
GC		 218/**
219 * stmmac_clk_csr_set - dynamically set the MDC clock
220 * @priv: driver private structure
221 * Description: this is to dynamically set the MDC clock according to the csr
222 * clock input.
223 * Note:
224 * If a specific clk_csr value is passed from the platform
225 * this means that the CSR Clock Range selection cannot be
226 * changed at run-time and it is fixed (as reported in the driver
227 * documentation). Viceversa the driver will try to set the MDC
228 * clock dynamically according to the actual clock input.
229 */
cd7201f4
GC		 230static void stmmac_clk_csr_set(struct stmmac_priv *priv)
231{
cd7201f4
GC		 232 u32 clk_rate;
233
f573c0b9 234 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
cd7201f4
GC		 235
236 /* Platform provided default clk_csr would be assumed valid
ceb69499
GC		 237 * for all other cases except for the below mentioned ones.
238 * For values higher than the IEEE 802.3 specified frequency
239 * we can not estimate the proper divider as it is not known
240 * the frequency of clk_csr_i. So we do not change the default
241 * divider.
242 */
cd7201f4
GC		 243 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
244 if (clk_rate < CSR_F_35M)
245 priv->clk_csr = STMMAC_CSR_20_35M;
246 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
247 priv->clk_csr = STMMAC_CSR_35_60M;
248 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
249 priv->clk_csr = STMMAC_CSR_60_100M;
250 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
251 priv->clk_csr = STMMAC_CSR_100_150M;
252 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
253 priv->clk_csr = STMMAC_CSR_150_250M;
19d857c9 254 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
cd7201f4 255 priv->clk_csr = STMMAC_CSR_250_300M;
ceb69499 256 }
9f93ac8d
LC		 257
258 if (priv->plat->has_sun8i) {
259 if (clk_rate > 160000000)
260 priv->clk_csr = 0x03;
261 else if (clk_rate > 80000000)
262 priv->clk_csr = 0x02;
263 else if (clk_rate > 40000000)
264 priv->clk_csr = 0x01;
265 else
266 priv->clk_csr = 0;
267 }
7d9e6c5a
JA		 268
269 if (priv->plat->has_xgmac) {
270 if (clk_rate > 400000000)
271 priv->clk_csr = 0x5;
272 else if (clk_rate > 350000000)
273 priv->clk_csr = 0x4;
274 else if (clk_rate > 300000000)
275 priv->clk_csr = 0x3;
276 else if (clk_rate > 250000000)
277 priv->clk_csr = 0x2;
278 else if (clk_rate > 150000000)
279 priv->clk_csr = 0x1;
280 else
281 priv->clk_csr = 0x0;
282 }
cd7201f4
GC		 283}
284
47dd7a54
GC		 285static void print_pkt(unsigned char *buf, int len)
286{
424c4f78
AS		 287 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
288 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
47dd7a54 289}
47dd7a54 290
ce736788 291static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
47dd7a54 292{
ce736788 293 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
a6a3e026 294 u32 avail;
e3ad57c9 295
ce736788
JP		 296 if (tx_q->dirty_tx > tx_q->cur_tx)
297 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
e3ad57c9 298 else
ce736788 299 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
e3ad57c9
GC		 300
301 return avail;
302}
303
54139cf3
JP		 304/**
305 * stmmac_rx_dirty - Get RX queue dirty
306 * @priv: driver private structure
307 * @queue: RX queue index
308 */
309static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
e3ad57c9 310{
54139cf3 311 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
a6a3e026 312 u32 dirty;
e3ad57c9 313
54139cf3
JP		 314 if (rx_q->dirty_rx <= rx_q->cur_rx)
315 dirty = rx_q->cur_rx - rx_q->dirty_rx;
e3ad57c9 316 else
54139cf3 317 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
e3ad57c9
GC		 318
319 return dirty;
47dd7a54
GC		 320}
321
32ceabca 322/**
732fdf0e 323 * stmmac_enable_eee_mode - check and enter in LPI mode
32ceabca 324 * @priv: driver private structure
732fdf0e
GC		 325 * Description: this function is to verify and enter in LPI mode in case of
326 * EEE.
32ceabca 327 */
d765955d
GC		 328static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
329{
ce736788
JP		 330 u32 tx_cnt = priv->plat->tx_queues_to_use;
331 u32 queue;
332
333 /* check if all TX queues have the work finished */
334 for (queue = 0; queue < tx_cnt; queue++) {
335 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
336
337 if (tx_q->dirty_tx != tx_q->cur_tx)
338 return; /* still unfinished work */
339 }
340
d765955d 341 /* Check and enter in LPI mode */
ce736788 342 if (!priv->tx_path_in_lpi_mode)
c10d4c82
JA		 343 stmmac_set_eee_mode(priv, priv->hw,
344 priv->plat->en_tx_lpi_clockgating);
d765955d
GC		 345}
346
32ceabca 347/**
732fdf0e 348 * stmmac_disable_eee_mode - disable and exit from LPI mode
32ceabca
GC		 349 * @priv: driver private structure
350 * Description: this function is to exit and disable EEE in case of
351 * LPI state is true. This is called by the xmit.
352 */
d765955d
GC		 353void stmmac_disable_eee_mode(struct stmmac_priv *priv)
354{
c10d4c82 355 stmmac_reset_eee_mode(priv, priv->hw);
d765955d
GC		 356 del_timer_sync(&priv->eee_ctrl_timer);
357 priv->tx_path_in_lpi_mode = false;
358}
359
360/**
732fdf0e 361 * stmmac_eee_ctrl_timer - EEE TX SW timer.
d765955d
GC		 362 * @arg : data hook
363 * Description:
32ceabca 364 * if there is no data transfer and if we are not in LPI state,
d765955d
GC		 365 * then MAC Transmitter can be moved to LPI state.
366 */
e99e88a9 367static void stmmac_eee_ctrl_timer(struct timer_list *t)
d765955d 368{
e99e88a9 369 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
d765955d
GC		 370
371 stmmac_enable_eee_mode(priv);
f5351ef7 372 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
d765955d
GC		 373}
374
375/**
732fdf0e 376 * stmmac_eee_init - init EEE
32ceabca 377 * @priv: driver private structure
d765955d 378 * Description:
732fdf0e
GC		 379 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
380 * can also manage EEE, this function enable the LPI state and start related
381 * timer.
d765955d
GC		 382 */
383bool stmmac_eee_init(struct stmmac_priv *priv)
384{
74371272 385 int tx_lpi_timer = priv->tx_lpi_timer;
879626e3 386
f5351ef7
GC		 387 /* Using PCS we cannot dial with the phy registers at this stage
388 * so we do not support extra feature like EEE.
389 */
3fe5cadb
GC		 390 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
391 (priv->hw->pcs == STMMAC_PCS_TBI) ||
392 (priv->hw->pcs == STMMAC_PCS_RTBI))
74371272 393 return false;
d765955d 394
74371272
JA		 395 /* Check if MAC core supports the EEE feature. */
396 if (!priv->dma_cap.eee)
397 return false;
398
399 mutex_lock(&priv->lock);
4741cf9c 400
74371272 401 /* Check if it needs to be deactivated */
177d935a
JH		 402 if (!priv->eee_active) {
403 if (priv->eee_enabled) {
404 netdev_dbg(priv->dev, "disable EEE\n");
405 del_timer_sync(&priv->eee_ctrl_timer);
406 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
407 }
0867bb97 408 mutex_unlock(&priv->lock);
74371272 409 return false;
d765955d 410 }
74371272
JA		 411
412 if (priv->eee_active && !priv->eee_enabled) {
413 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
414 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
415 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
416 tx_lpi_timer);
417 }
418
419 mutex_unlock(&priv->lock);
420 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
421 return true;
d765955d
GC		 422}
423
732fdf0e 424/* stmmac_get_tx_hwtstamp - get HW TX timestamps
32ceabca 425 * @priv: driver private structure
ba1ffd74 426 * @p : descriptor pointer
891434b1
RK		 427 * @skb : the socket buffer
428 * Description :
429 * This function will read timestamp from the descriptor & pass it to stack.
430 * and also perform some sanity checks.
431 */
432static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
ba1ffd74 433 struct dma_desc *p, struct sk_buff *skb)
891434b1
RK		 434{
435 struct skb_shared_hwtstamps shhwtstamp;
25e80cd0 436 bool found = false;
df103170 437 u64 ns = 0;
891434b1
RK		 438
439 if (!priv->hwts_tx_en)
440 return;
441
ceb69499 442 /* exit if skb doesn't support hw tstamp */
75e4364f 443 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
891434b1
RK		 444 return;
445
891434b1 446 /* check tx tstamp status */
42de047d 447 if (stmmac_get_tx_timestamp_status(priv, p)) {
42de047d 448 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
25e80cd0
JA		 449 found = true;
450 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
451 found = true;
452 }
891434b1 453
25e80cd0 454 if (found) {
ba1ffd74
GC		 455 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
456 shhwtstamp.hwtstamp = ns_to_ktime(ns);
891434b1 457
33d4c482 458 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
ba1ffd74
GC		 459 /* pass tstamp to stack */
460 skb_tstamp_tx(skb, &shhwtstamp);
461 }
891434b1
RK		 462}
463
732fdf0e 464/* stmmac_get_rx_hwtstamp - get HW RX timestamps
32ceabca 465 * @priv: driver private structure
ba1ffd74
GC		 466 * @p : descriptor pointer
467 * @np : next descriptor pointer
891434b1
RK		 468 * @skb : the socket buffer
469 * Description :
470 * This function will read received packet's timestamp from the descriptor
471 * and pass it to stack. It also perform some sanity checks.
472 */
ba1ffd74
GC		 473static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
474 struct dma_desc *np, struct sk_buff *skb)
891434b1
RK		 475{
476 struct skb_shared_hwtstamps *shhwtstamp = NULL;
98870943 477 struct dma_desc *desc = p;
df103170 478 u64 ns = 0;
891434b1
RK		 479
480 if (!priv->hwts_rx_en)
481 return;
98870943 482 /* For GMAC4, the valid timestamp is from CTX next desc. */
7d9e6c5a 483 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
98870943 484 desc = np;
891434b1 485
ba1ffd74 486 /* Check if timestamp is available */
42de047d
JA		 487 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
488 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
33d4c482 489 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
ba1ffd74
GC		 490 shhwtstamp = skb_hwtstamps(skb);
491 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
492 shhwtstamp->hwtstamp = ns_to_ktime(ns);
493 } else {
33d4c482 494 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
ba1ffd74 495 }
891434b1
RK		 496}
497
498/**
d6228b7c 499 * stmmac_hwtstamp_set - control hardware timestamping.
891434b1 500 * @dev: device pointer.
8d45e42b 501 * @ifr: An IOCTL specific structure, that can contain a pointer to
891434b1
RK		 502 * a proprietary structure used to pass information to the driver.
503 * Description:
504 * This function configures the MAC to enable/disable both outgoing(TX)
505 * and incoming(RX) packets time stamping based on user input.
506 * Return Value:
507 * 0 on success and an appropriate -ve integer on failure.
508 */
d6228b7c 509static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
891434b1
RK		 510{
511 struct stmmac_priv *priv = netdev_priv(dev);
512 struct hwtstamp_config config;
0a624155 513 struct timespec64 now;
891434b1
RK		 514 u64 temp = 0;
515 u32 ptp_v2 = 0;
516 u32 tstamp_all = 0;
517 u32 ptp_over_ipv4_udp = 0;
518 u32 ptp_over_ipv6_udp = 0;
519 u32 ptp_over_ethernet = 0;
520 u32 snap_type_sel = 0;
521 u32 ts_master_en = 0;
522 u32 ts_event_en = 0;
df103170 523 u32 sec_inc = 0;
891434b1 524 u32 value = 0;
7d9e6c5a
JA		 525 bool xmac;
526
527 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
891434b1
RK		 528
529 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
530 netdev_alert(priv->dev, "No support for HW time stamping\n");
531 priv->hwts_tx_en = 0;
532 priv->hwts_rx_en = 0;
533
534 return -EOPNOTSUPP;
535 }
536
537 if (copy_from_user(&config, ifr->ifr_data,
d6228b7c 538 sizeof(config)))
891434b1
RK		 539 return -EFAULT;
540
38ddc59d
LC		 541 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
542 __func__, config.flags, config.tx_type, config.rx_filter);
891434b1
RK		 543
544 /* reserved for future extensions */
545 if (config.flags)
546 return -EINVAL;
547
5f3da328
BH		 548 if (config.tx_type != HWTSTAMP_TX_OFF &&
549 config.tx_type != HWTSTAMP_TX_ON)
891434b1 550 return -ERANGE;
891434b1
RK		 551
552 if (priv->adv_ts) {
553 switch (config.rx_filter) {
891434b1 554 case HWTSTAMP_FILTER_NONE:
ceb69499 555 /* time stamp no incoming packet at all */
891434b1
RK		 556 config.rx_filter = HWTSTAMP_FILTER_NONE;
557 break;
558
891434b1 559 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
ceb69499 560 /* PTP v1, UDP, any kind of event packet */
891434b1 561 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
7d8e249f
IA		 562 /* 'xmac' hardware can support Sync, Pdelay_Req and
563 * Pdelay_resp by setting bit14 and bits17/16 to 01
564 * This leaves Delay_Req timestamps out.
565 * Enable all events *and* general purpose message
566 * timestamping
567 */
568 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
891434b1
RK		 569 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
570 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
571 break;
572
891434b1 573 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
ceb69499 574 /* PTP v1, UDP, Sync packet */
891434b1
RK		 575 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
576 /* take time stamp for SYNC messages only */
577 ts_event_en = PTP_TCR_TSEVNTENA;
578
579 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
580 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
581 break;
582
891434b1 583 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
ceb69499 584 /* PTP v1, UDP, Delay_req packet */
891434b1
RK		 585 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
586 /* take time stamp for Delay_Req messages only */
587 ts_master_en = PTP_TCR_TSMSTRENA;
588 ts_event_en = PTP_TCR_TSEVNTENA;
589
590 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
591 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
592 break;
593
891434b1 594 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
ceb69499 595 /* PTP v2, UDP, any kind of event packet */
891434b1
RK		 596 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
597 ptp_v2 = PTP_TCR_TSVER2ENA;
598 /* take time stamp for all event messages */
7d8e249f 599 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
891434b1
RK		 600
601 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
602 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
603 break;
604
891434b1 605 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
ceb69499 606 /* PTP v2, UDP, Sync packet */
891434b1
RK		 607 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
608 ptp_v2 = PTP_TCR_TSVER2ENA;
609 /* take time stamp for SYNC messages only */
610 ts_event_en = PTP_TCR_TSEVNTENA;
611
612 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
613 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
614 break;
615
891434b1 616 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
ceb69499 617 /* PTP v2, UDP, Delay_req packet */
891434b1
RK		 618 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
619 ptp_v2 = PTP_TCR_TSVER2ENA;
620 /* take time stamp for Delay_Req messages only */
621 ts_master_en = PTP_TCR_TSMSTRENA;
622 ts_event_en = PTP_TCR_TSEVNTENA;
623
624 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
625 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
626 break;
627
891434b1 628 case HWTSTAMP_FILTER_PTP_V2_EVENT:
ceb69499 629 /* PTP v2/802.AS1 any layer, any kind of event packet */
891434b1
RK		 630 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
631 ptp_v2 = PTP_TCR_TSVER2ENA;
7d8e249f 632 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
14f34733 633 ts_event_en = PTP_TCR_TSEVNTENA;
891434b1
RK		 634 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
635 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
636 ptp_over_ethernet = PTP_TCR_TSIPENA;
637 break;
638
891434b1 639 case HWTSTAMP_FILTER_PTP_V2_SYNC:
ceb69499 640 /* PTP v2/802.AS1, any layer, Sync packet */
891434b1
RK		 641 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
642 ptp_v2 = PTP_TCR_TSVER2ENA;
643 /* take time stamp for SYNC messages only */
644 ts_event_en = PTP_TCR_TSEVNTENA;
645
646 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
647 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
648 ptp_over_ethernet = PTP_TCR_TSIPENA;
649 break;
650
891434b1 651 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
ceb69499 652 /* PTP v2/802.AS1, any layer, Delay_req packet */
891434b1
RK		 653 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
654 ptp_v2 = PTP_TCR_TSVER2ENA;
655 /* take time stamp for Delay_Req messages only */
656 ts_master_en = PTP_TCR_TSMSTRENA;
657 ts_event_en = PTP_TCR_TSEVNTENA;
658
659 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
660 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
661 ptp_over_ethernet = PTP_TCR_TSIPENA;
662 break;
663
e3412575 664 case HWTSTAMP_FILTER_NTP_ALL:
891434b1 665 case HWTSTAMP_FILTER_ALL:
ceb69499 666 /* time stamp any incoming packet */
891434b1
RK		 667 config.rx_filter = HWTSTAMP_FILTER_ALL;
668 tstamp_all = PTP_TCR_TSENALL;
669 break;
670
671 default:
672 return -ERANGE;
673 }
674 } else {
675 switch (config.rx_filter) {
676 case HWTSTAMP_FILTER_NONE:
677 config.rx_filter = HWTSTAMP_FILTER_NONE;
678 break;
679 default:
680 /* PTP v1, UDP, any kind of event packet */
681 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
682 break;
683 }
684 }
685 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
5f3da328 686 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
891434b1
RK		 687
688 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
cc4c9001 689 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
891434b1
RK		 690 else {
691 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
ceb69499
GC		 692 tstamp_all | ptp_v2 | ptp_over_ethernet |
693 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
694 ts_master_en | snap_type_sel);
cc4c9001 695 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
891434b1
RK		 696
697 /* program Sub Second Increment reg */
cc4c9001
JA		 698 stmmac_config_sub_second_increment(priv,
699 priv->ptpaddr, priv->plat->clk_ptp_rate,
7d9e6c5a 700 xmac, &sec_inc);
19d857c9 701 temp = div_u64(1000000000ULL, sec_inc);
891434b1 702
9a8a02c9
JA		 703 /* Store sub second increment and flags for later use */
704 priv->sub_second_inc = sec_inc;
705 priv->systime_flags = value;
706
891434b1
RK		 707 /* calculate default added value:
708 * formula is :
709 * addend = (2^32)/freq_div_ratio;
19d857c9 710 * where, freq_div_ratio = 1e9ns/sec_inc
891434b1 711 */
19d857c9 712 temp = (u64)(temp << 32);
f573c0b9 713 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
cc4c9001 714 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
891434b1
RK		 715
716 /* initialize system time */
0a624155
AB		 717 ktime_get_real_ts64(&now);
718
719 /* lower 32 bits of tv_sec are safe until y2106 */
cc4c9001
JA		 720 stmmac_init_systime(priv, priv->ptpaddr,
721 (u32)now.tv_sec, now.tv_nsec);
891434b1
RK		 722 }
723
d6228b7c
AP		 724 memcpy(&priv->tstamp_config, &config, sizeof(config));
725
891434b1 726 return copy_to_user(ifr->ifr_data, &config,
d6228b7c
AP		 727 sizeof(config)) ? -EFAULT : 0;
728}
729
730/**
731 * stmmac_hwtstamp_get - read hardware timestamping.
732 * @dev: device pointer.
733 * @ifr: An IOCTL specific structure, that can contain a pointer to
734 * a proprietary structure used to pass information to the driver.
735 * Description:
736 * This function obtain the current hardware timestamping settings
737 as requested.
738 */
739static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
740{
741 struct stmmac_priv *priv = netdev_priv(dev);
742 struct hwtstamp_config *config = &priv->tstamp_config;
743
744 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
745 return -EOPNOTSUPP;
746
747 return copy_to_user(ifr->ifr_data, config,
748 sizeof(*config)) ? -EFAULT : 0;
891434b1
RK		 749}
750
32ceabca 751/**
732fdf0e 752 * stmmac_init_ptp - init PTP
32ceabca 753 * @priv: driver private structure
732fdf0e 754 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
32ceabca 755 * This is done by looking at the HW cap. register.
732fdf0e 756 * This function also registers the ptp driver.
32ceabca 757 */
92ba6888 758static int stmmac_init_ptp(struct stmmac_priv *priv)
891434b1 759{
7d9e6c5a
JA		 760 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
761
92ba6888
RK		 762 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
763 return -EOPNOTSUPP;
764
7cd01399 765 priv->adv_ts = 0;
7d9e6c5a
JA		 766 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
767 if (xmac && priv->dma_cap.atime_stamp)
be9b3174
GC		 768 priv->adv_ts = 1;
769 /* Dwmac 3.x core with extend_desc can support adv_ts */
770 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
7cd01399
VB		 771 priv->adv_ts = 1;
772
be9b3174
GC		 773 if (priv->dma_cap.time_stamp)
774 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
7cd01399 775
be9b3174
GC		 776 if (priv->adv_ts)
777 netdev_info(priv->dev,
778 "IEEE 1588-2008 Advanced Timestamp supported\n");
891434b1 779
891434b1
RK		 780 priv->hwts_tx_en = 0;
781 priv->hwts_rx_en = 0;
92ba6888 782
c30a70d3
GC		 783 stmmac_ptp_register(priv);
784
785 return 0;
92ba6888
RK		 786}
787
788static void stmmac_release_ptp(struct stmmac_priv *priv)
789{
f573c0b9 790 if (priv->plat->clk_ptp_ref)
791 clk_disable_unprepare(priv->plat->clk_ptp_ref);
92ba6888 792 stmmac_ptp_unregister(priv);
891434b1
RK		 793}
794
29feff39
JP		 795/**
796 * stmmac_mac_flow_ctrl - Configure flow control in all queues
797 * @priv: driver private structure
798 * Description: It is used for configuring the flow control in all queues
799 */
800static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
801{
802 u32 tx_cnt = priv->plat->tx_queues_to_use;
803
c10d4c82
JA		 804 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
805 priv->pause, tx_cnt);
29feff39
JP		 806}
807
eeef2f6b
JA		 808static void stmmac_validate(struct phylink_config *config,
809 unsigned long *supported,
810 struct phylink_link_state *state)
811{
812 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
5b0d7d7d 813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
eeef2f6b
JA		 814 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
815 int tx_cnt = priv->plat->tx_queues_to_use;
816 int max_speed = priv->plat->max_speed;
817
5b0d7d7d
JA		 818 phylink_set(mac_supported, 10baseT_Half);
819 phylink_set(mac_supported, 10baseT_Full);
820 phylink_set(mac_supported, 100baseT_Half);
821 phylink_set(mac_supported, 100baseT_Full);
df7699c7
JA		 822 phylink_set(mac_supported, 1000baseT_Half);
823 phylink_set(mac_supported, 1000baseT_Full);
824 phylink_set(mac_supported, 1000baseKX_Full);
5b0d7d7d
JA		 825
826 phylink_set(mac_supported, Autoneg);
827 phylink_set(mac_supported, Pause);
828 phylink_set(mac_supported, Asym_Pause);
829 phylink_set_port_modes(mac_supported);
830
eeef2f6b
JA		 831 /* Cut down 1G if asked to */
832 if ((max_speed > 0) && (max_speed < 1000)) {
833 phylink_set(mask, 1000baseT_Full);
834 phylink_set(mask, 1000baseX_Full);
5b0d7d7d 835 } else if (priv->plat->has_xgmac) {
d9da2c87
JA		 836 if (!max_speed || (max_speed >= 2500)) {
837 phylink_set(mac_supported, 2500baseT_Full);
838 phylink_set(mac_supported, 2500baseX_Full);
839 }
840 if (!max_speed || (max_speed >= 5000)) {
841 phylink_set(mac_supported, 5000baseT_Full);
842 }
843 if (!max_speed || (max_speed >= 10000)) {
844 phylink_set(mac_supported, 10000baseSR_Full);
845 phylink_set(mac_supported, 10000baseLR_Full);
846 phylink_set(mac_supported, 10000baseER_Full);
847 phylink_set(mac_supported, 10000baseLRM_Full);
848 phylink_set(mac_supported, 10000baseT_Full);
849 phylink_set(mac_supported, 10000baseKX4_Full);
850 phylink_set(mac_supported, 10000baseKR_Full);
851 }
eeef2f6b
JA		 852 }
853
854 /* Half-Duplex can only work with single queue */
855 if (tx_cnt > 1) {
856 phylink_set(mask, 10baseT_Half);
857 phylink_set(mask, 100baseT_Half);
858 phylink_set(mask, 1000baseT_Half);
859 }
860
5b0d7d7d
JA		 861 bitmap_and(supported, supported, mac_supported,
862 __ETHTOOL_LINK_MODE_MASK_NBITS);
863 bitmap_andnot(supported, supported, mask,
864 __ETHTOOL_LINK_MODE_MASK_NBITS);
865 bitmap_and(state->advertising, state->advertising, mac_supported,
866 __ETHTOOL_LINK_MODE_MASK_NBITS);
eeef2f6b
JA		 867 bitmap_andnot(state->advertising, state->advertising, mask,
868 __ETHTOOL_LINK_MODE_MASK_NBITS);
869}
870
d46b7e4f
RK		 871static void stmmac_mac_pcs_get_state(struct phylink_config *config,
872 struct phylink_link_state *state)
eeef2f6b 873{
d46b7e4f 874 state->link = 0;
eeef2f6b
JA		 875}
876
74371272
JA		 877static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
878 const struct phylink_link_state *state)
9ad372fc 879{
74371272 880 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
9ad372fc
JA		 881 u32 ctrl;
882
883 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
74371272 884 ctrl &= ~priv->hw->link.speed_mask;
9ad372fc 885
5b0d7d7d
JA		 886 if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
887 switch (state->speed) {
888 case SPEED_10000:
889 ctrl |= priv->hw->link.xgmii.speed10000;
890 break;
891 case SPEED_5000:
892 ctrl |= priv->hw->link.xgmii.speed5000;
893 break;
894 case SPEED_2500:
895 ctrl |= priv->hw->link.xgmii.speed2500;
896 break;
897 default:
898 return;
899 }
900 } else {
901 switch (state->speed) {
902 case SPEED_2500:
903 ctrl |= priv->hw->link.speed2500;
904 break;
905 case SPEED_1000:
906 ctrl |= priv->hw->link.speed1000;
907 break;
908 case SPEED_100:
909 ctrl |= priv->hw->link.speed100;
910 break;
911 case SPEED_10:
912 ctrl |= priv->hw->link.speed10;
913 break;
914 default:
915 return;
916 }
9ad372fc
JA		 917 }
918
74371272 919 priv->speed = state->speed;
9ad372fc 920
74371272
JA		 921 if (priv->plat->fix_mac_speed)
922 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
923
924 if (!state->duplex)
925 ctrl &= ~priv->hw->link.duplex;
926 else
927 ctrl |= priv->hw->link.duplex;
9ad372fc
JA		 928
929 /* Flow Control operation */
74371272
JA		 930 if (state->pause)
931 stmmac_mac_flow_ctrl(priv, state->duplex);
9ad372fc
JA		 932
933 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
934}
935
eeef2f6b
JA		 936static void stmmac_mac_an_restart(struct phylink_config *config)
937{
938 /* Not Supported */
939}
940
74371272
JA		 941static void stmmac_mac_link_down(struct phylink_config *config,
942 unsigned int mode, phy_interface_t interface)
9ad372fc 943{
74371272 944 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
9ad372fc
JA		 945
946 stmmac_mac_set(priv, priv->ioaddr, false);
74371272
JA		 947 priv->eee_active = false;
948 stmmac_eee_init(priv);
949 stmmac_set_eee_pls(priv, priv->hw, false);
9ad372fc
JA		 950}
951
74371272
JA		 952static void stmmac_mac_link_up(struct phylink_config *config,
953 unsigned int mode, phy_interface_t interface,
954 struct phy_device *phy)
9ad372fc 955{
74371272 956 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
9ad372fc
JA		 957
958 stmmac_mac_set(priv, priv->ioaddr, true);
5b111770 959 if (phy && priv->dma_cap.eee) {
74371272
JA		 960 priv->eee_active = phy_init_eee(phy, 1) >= 0;
961 priv->eee_enabled = stmmac_eee_init(priv);
962 stmmac_set_eee_pls(priv, priv->hw, true);
963 }
9ad372fc
JA		 964}
965
74371272 966static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
eeef2f6b 967 .validate = stmmac_validate,
d46b7e4f 968 .mac_pcs_get_state = stmmac_mac_pcs_get_state,
74371272 969 .mac_config = stmmac_mac_config,
eeef2f6b 970 .mac_an_restart = stmmac_mac_an_restart,
74371272
JA		 971 .mac_link_down = stmmac_mac_link_down,
972 .mac_link_up = stmmac_mac_link_up,
eeef2f6b
JA		 973};
974
32ceabca 975/**
732fdf0e 976 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
32ceabca
GC		 977 * @priv: driver private structure
978 * Description: this is to verify if the HW supports the PCS.
979 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
980 * configured for the TBI, RTBI, or SGMII PHY interface.
981 */
e58bb43f
GC		 982static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
983{
984 int interface = priv->plat->interface;
985
986 if (priv->dma_cap.pcs) {
0d909dcd
BA		 987 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
988 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
989 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
990 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
38ddc59d 991 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
3fe5cadb 992 priv->hw->pcs = STMMAC_PCS_RGMII;
0d909dcd 993 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
38ddc59d 994 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
3fe5cadb 995 priv->hw->pcs = STMMAC_PCS_SGMII;
e58bb43f
GC		 996 }
997 }
998}
999
47dd7a54
GC		 1000/**
1001 * stmmac_init_phy - PHY initialization
1002 * @dev: net device structure
1003 * Description: it initializes the driver's PHY state, and attaches the PHY
1004 * to the mac driver.
1005 * Return value:
1006 * 0 on success
1007 */
1008static int stmmac_init_phy(struct net_device *dev)
1009{
1010 struct stmmac_priv *priv = netdev_priv(dev);
74371272
JA		 1011 struct device_node *node;
1012 int ret;
5790cf3c 1013
4838a540 1014 node = priv->plat->phylink_node;
5790cf3c 1015
42e87024 1016 if (node)
74371272 1017 ret = phylink_of_phy_connect(priv->phylink, node, 0);
42e87024
JA		 1018
1019 /* Some DT bindings do not set-up the PHY handle. Let's try to
1020 * manually parse it
1021 */
1022 if (!node || ret) {
74371272
JA		 1023 int addr = priv->plat->phy_addr;
1024 struct phy_device *phydev;
47dd7a54 1025
74371272
JA		 1026 phydev = mdiobus_get_phy(priv->mii, addr);
1027 if (!phydev) {
1028 netdev_err(priv->dev, "no phy at addr %d\n", addr);
dfc50fca 1029 return -ENODEV;
74371272 1030 }
dfc50fca 1031
74371272 1032 ret = phylink_connect_phy(priv->phylink, phydev);
47dd7a54
GC		 1033 }
1034
74371272
JA		 1035 return ret;
1036}
79ee1dc3 1037
74371272
JA		 1038static int stmmac_phy_setup(struct stmmac_priv *priv)
1039{
c63d1e5c 1040 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
0060c878 1041 int mode = priv->plat->phy_interface;
74371272 1042 struct phylink *phylink;
b6cfffa7 1043
74371272
JA		 1044 priv->phylink_config.dev = &priv->dev->dev;
1045 priv->phylink_config.type = PHYLINK_NETDEV;
8e99fc5f 1046
c63d1e5c 1047 phylink = phylink_create(&priv->phylink_config, fwnode,
74371272
JA		 1048 mode, &stmmac_phylink_mac_ops);
1049 if (IS_ERR(phylink))
1050 return PTR_ERR(phylink);
c51e424d 1051
74371272 1052 priv->phylink = phylink;
47dd7a54
GC		 1053 return 0;
1054}
1055
71fedb01 1056static void stmmac_display_rx_rings(struct stmmac_priv *priv)
c24602ef 1057{
54139cf3 1058 u32 rx_cnt = priv->plat->rx_queues_to_use;
71fedb01 1059 void *head_rx;
54139cf3 1060 u32 queue;
aff3d9ef 1061
54139cf3
JP		 1062 /* Display RX rings */
1063 for (queue = 0; queue < rx_cnt; queue++) {
1064 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
d0225e7d 1065
54139cf3
JP		 1066 pr_info("\tRX Queue %u rings\n", queue);
1067
1068 if (priv->extend_desc)
1069 head_rx = (void *)rx_q->dma_erx;
1070 else
1071 head_rx = (void *)rx_q->dma_rx;
1072
1073 /* Display RX ring */
42de047d 1074 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
54139cf3 1075 }
71fedb01
JP		 1076}
1077
1078static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1079{
ce736788 1080 u32 tx_cnt = priv->plat->tx_queues_to_use;
71fedb01 1081 void *head_tx;
ce736788 1082 u32 queue;
71fedb01 1083
ce736788
JP		 1084 /* Display TX rings */
1085 for (queue = 0; queue < tx_cnt; queue++) {
1086 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
71fedb01 1087
ce736788
JP		 1088 pr_info("\tTX Queue %d rings\n", queue);
1089
1090 if (priv->extend_desc)
1091 head_tx = (void *)tx_q->dma_etx;
1092 else
1093 head_tx = (void *)tx_q->dma_tx;
1094
42de047d 1095 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
ce736788 1096 }
c24602ef
GC		 1097}
1098
71fedb01
JP		 1099static void stmmac_display_rings(struct stmmac_priv *priv)
1100{
1101 /* Display RX ring */
1102 stmmac_display_rx_rings(priv);
1103
1104 /* Display TX ring */
1105 stmmac_display_tx_rings(priv);
1106}
1107
286a8372
GC		 1108static int stmmac_set_bfsize(int mtu, int bufsize)
1109{
1110 int ret = bufsize;
1111
1112 if (mtu >= BUF_SIZE_4KiB)
1113 ret = BUF_SIZE_8KiB;
1114 else if (mtu >= BUF_SIZE_2KiB)
1115 ret = BUF_SIZE_4KiB;
d916701c 1116 else if (mtu > DEFAULT_BUFSIZE)
286a8372
GC		 1117 ret = BUF_SIZE_2KiB;
1118 else
d916701c 1119 ret = DEFAULT_BUFSIZE;
286a8372
GC		 1120
1121 return ret;
1122}
1123
32ceabca 1124/**
71fedb01 1125 * stmmac_clear_rx_descriptors - clear RX descriptors
32ceabca 1126 * @priv: driver private structure
54139cf3 1127 * @queue: RX queue index
71fedb01 1128 * Description: this function is called to clear the RX descriptors
32ceabca
GC		 1129 * in case of both basic and extended descriptors are used.
1130 */
54139cf3 1131static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
c24602ef 1132{
54139cf3 1133 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5bacd778 1134 int i;
c24602ef 1135
71fedb01 1136 /* Clear the RX descriptors */
e3ad57c9 1137 for (i = 0; i < DMA_RX_SIZE; i++)
c24602ef 1138 if (priv->extend_desc)
42de047d
JA		 1139 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1140 priv->use_riwt, priv->mode,
583e6361
AK		 1141 (i == DMA_RX_SIZE - 1),
1142 priv->dma_buf_sz);
c24602ef 1143 else
42de047d
JA		 1144 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1145 priv->use_riwt, priv->mode,
583e6361
AK		 1146 (i == DMA_RX_SIZE - 1),
1147 priv->dma_buf_sz);
71fedb01
JP		 1148}
1149
1150/**
1151 * stmmac_clear_tx_descriptors - clear tx descriptors
1152 * @priv: driver private structure
ce736788 1153 * @queue: TX queue index.
71fedb01
JP		 1154 * Description: this function is called to clear the TX descriptors
1155 * in case of both basic and extended descriptors are used.
1156 */
ce736788 1157static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
71fedb01 1158{
ce736788 1159 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
71fedb01
JP		 1160 int i;
1161
1162 /* Clear the TX descriptors */
e3ad57c9 1163 for (i = 0; i < DMA_TX_SIZE; i++)
c24602ef 1164 if (priv->extend_desc)
42de047d
JA		 1165 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1166 priv->mode, (i == DMA_TX_SIZE - 1));
c24602ef 1167 else
42de047d
JA		 1168 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1169 priv->mode, (i == DMA_TX_SIZE - 1));
c24602ef
GC		 1170}
1171
71fedb01
JP		 1172/**
1173 * stmmac_clear_descriptors - clear descriptors
1174 * @priv: driver private structure
1175 * Description: this function is called to clear the TX and RX descriptors
1176 * in case of both basic and extended descriptors are used.
1177 */
1178static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1179{
54139cf3 1180 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
ce736788 1181 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
54139cf3
JP		 1182 u32 queue;
1183
71fedb01 1184 /* Clear the RX descriptors */
54139cf3
JP		 1185 for (queue = 0; queue < rx_queue_cnt; queue++)
1186 stmmac_clear_rx_descriptors(priv, queue);
71fedb01
JP		 1187
1188 /* Clear the TX descriptors */
ce736788
JP		 1189 for (queue = 0; queue < tx_queue_cnt; queue++)
1190 stmmac_clear_tx_descriptors(priv, queue);
71fedb01
JP		 1191}
1192
732fdf0e
GC		 1193/**
1194 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1195 * @priv: driver private structure
1196 * @p: descriptor pointer
1197 * @i: descriptor index
54139cf3
JP		 1198 * @flags: gfp flag
1199 * @queue: RX queue index
732fdf0e
GC		 1200 * Description: this function is called to allocate a receive buffer, perform
1201 * the DMA mapping and init the descriptor.
1202 */
c24602ef 1203static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
54139cf3 1204 int i, gfp_t flags, u32 queue)
c24602ef 1205{
54139cf3 1206 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
2af6106a 1207 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
c24602ef 1208
2af6106a
JA		 1209 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1210 if (!buf->page)
56329137 1211 return -ENOMEM;
c24602ef 1212
67afd6d1
JA		 1213 if (priv->sph) {
1214 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
1215 if (!buf->sec_page)
1216 return -ENOMEM;
1217
1218 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1219 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
1220 } else {
1221 buf->sec_page = NULL;
1222 }
1223
2af6106a
JA		 1224 buf->addr = page_pool_get_dma_addr(buf->page);
1225 stmmac_set_desc_addr(priv, p, buf->addr);
2c520b1c
JA		 1226 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1227 stmmac_init_desc3(priv, p);
c24602ef
GC		 1228
1229 return 0;
1230}
1231
71fedb01
JP		 1232/**
1233 * stmmac_free_rx_buffer - free RX dma buffers
1234 * @priv: private structure
54139cf3 1235 * @queue: RX queue index
71fedb01
JP		 1236 * @i: buffer index.
1237 */
54139cf3 1238static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
56329137 1239{
54139cf3 1240 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
2af6106a 1241 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
54139cf3 1242
2af6106a
JA		 1243 if (buf->page)
1244 page_pool_put_page(rx_q->page_pool, buf->page, false);
1245 buf->page = NULL;
67afd6d1
JA		 1246
1247 if (buf->sec_page)
1248 page_pool_put_page(rx_q->page_pool, buf->sec_page, false);
1249 buf->sec_page = NULL;
aff3d9ef
JP		 1250}
1251
1252/**
71fedb01
JP		 1253 * stmmac_free_tx_buffer - free RX dma buffers
1254 * @priv: private structure
ce736788 1255 * @queue: RX queue index
71fedb01
JP		 1256 * @i: buffer index.
1257 */
ce736788 1258static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
71fedb01 1259{
ce736788
JP		 1260 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1261
1262 if (tx_q->tx_skbuff_dma[i].buf) {
1263 if (tx_q->tx_skbuff_dma[i].map_as_page)
71fedb01 1264 dma_unmap_page(priv->device,
ce736788
JP		 1265 tx_q->tx_skbuff_dma[i].buf,
1266 tx_q->tx_skbuff_dma[i].len,
71fedb01
JP		 1267 DMA_TO_DEVICE);
1268 else
1269 dma_unmap_single(priv->device,
ce736788
JP		 1270 tx_q->tx_skbuff_dma[i].buf,
1271 tx_q->tx_skbuff_dma[i].len,
71fedb01
JP		 1272 DMA_TO_DEVICE);
1273 }
1274
ce736788
JP		 1275 if (tx_q->tx_skbuff[i]) {
1276 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1277 tx_q->tx_skbuff[i] = NULL;
1278 tx_q->tx_skbuff_dma[i].buf = 0;
1279 tx_q->tx_skbuff_dma[i].map_as_page = false;
71fedb01
JP		 1280 }
1281}
1282
1283/**
1284 * init_dma_rx_desc_rings - init the RX descriptor rings
47dd7a54 1285 * @dev: net device structure
732fdf0e 1286 * @flags: gfp flag.
71fedb01 1287 * Description: this function initializes the DMA RX descriptors
5bacd778 1288 * and allocates the socket buffers. It supports the chained and ring
286a8372 1289 * modes.
47dd7a54 1290 */
71fedb01 1291static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
47dd7a54 1292{
47dd7a54 1293 struct stmmac_priv *priv = netdev_priv(dev);
54139cf3 1294 u32 rx_count = priv->plat->rx_queues_to_use;
56329137 1295 int ret = -ENOMEM;
2c520b1c 1296 int bfsize = 0;
1d3028f4 1297 int queue;
54139cf3 1298 int i;
47dd7a54 1299
2c520b1c
JA		 1300 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1301 if (bfsize < 0)
1302 bfsize = 0;
286a8372 1303
4a7d666a 1304 if (bfsize < BUF_SIZE_16KiB)
286a8372 1305 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
47dd7a54 1306
2618abb7
VB		 1307 priv->dma_buf_sz = bfsize;
1308
54139cf3 1309 /* RX INITIALIZATION */
b3e51069
LC		 1310 netif_dbg(priv, probe, priv->dev,
1311 "SKB addresses:\nskb\t\tskb data\tdma data\n");
47dd7a54 1312
54139cf3
JP		 1313 for (queue = 0; queue < rx_count; queue++) {
1314 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
c24602ef 1315
54139cf3
JP		 1316 netif_dbg(priv, probe, priv->dev,
1317 "(%s) dma_rx_phy=0x%08x\n", __func__,
1318 (u32)rx_q->dma_rx_phy);
f748be53 1319
cbcf0999
JA		 1320 stmmac_clear_rx_descriptors(priv, queue);
1321
54139cf3
JP		 1322 for (i = 0; i < DMA_RX_SIZE; i++) {
1323 struct dma_desc *p;
aff3d9ef 1324
54139cf3
JP		 1325 if (priv->extend_desc)
1326 p = &((rx_q->dma_erx + i)->basic);
1327 else
1328 p = rx_q->dma_rx + i;
1329
1330 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1331 queue);
1332 if (ret)
1333 goto err_init_rx_buffers;
54139cf3
JP		 1334 }
1335
1336 rx_q->cur_rx = 0;
1337 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1338
54139cf3
JP		 1339 /* Setup the chained descriptor addresses */
1340 if (priv->mode == STMMAC_CHAIN_MODE) {
1341 if (priv->extend_desc)
2c520b1c
JA		 1342 stmmac_mode_init(priv, rx_q->dma_erx,
1343 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
54139cf3 1344 else
2c520b1c
JA		 1345 stmmac_mode_init(priv, rx_q->dma_rx,
1346 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
54139cf3 1347 }
71fedb01
JP		 1348 }
1349
54139cf3
JP		 1350 buf_sz = bfsize;
1351
71fedb01 1352 return 0;
54139cf3 1353
71fedb01 1354err_init_rx_buffers:
54139cf3
JP		 1355 while (queue >= 0) {
1356 while (--i >= 0)
1357 stmmac_free_rx_buffer(priv, queue, i);
1358
1359 if (queue == 0)
1360 break;
1361
1362 i = DMA_RX_SIZE;
1363 queue--;
1364 }
1365
71fedb01
JP		 1366 return ret;
1367}
1368
1369/**
1370 * init_dma_tx_desc_rings - init the TX descriptor rings
1371 * @dev: net device structure.
1372 * Description: this function initializes the DMA TX descriptors
1373 * and allocates the socket buffers. It supports the chained and ring
1374 * modes.
1375 */
1376static int init_dma_tx_desc_rings(struct net_device *dev)
1377{
1378 struct stmmac_priv *priv = netdev_priv(dev);
ce736788
JP		 1379 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1380 u32 queue;
71fedb01
JP		 1381 int i;
1382
ce736788
JP		 1383 for (queue = 0; queue < tx_queue_cnt; queue++) {
1384 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
71fedb01 1385
ce736788
JP		 1386 netif_dbg(priv, probe, priv->dev,
1387 "(%s) dma_tx_phy=0x%08x\n", __func__,
1388 (u32)tx_q->dma_tx_phy);
f748be53 1389
ce736788
JP		 1390 /* Setup the chained descriptor addresses */
1391 if (priv->mode == STMMAC_CHAIN_MODE) {
1392 if (priv->extend_desc)
2c520b1c
JA		 1393 stmmac_mode_init(priv, tx_q->dma_etx,
1394 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
ce736788 1395 else
2c520b1c
JA		 1396 stmmac_mode_init(priv, tx_q->dma_tx,
1397 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
ce736788 1398 }
aff3d9ef 1399
ce736788
JP		 1400 for (i = 0; i < DMA_TX_SIZE; i++) {
1401 struct dma_desc *p;
ce736788
JP		 1402 if (priv->extend_desc)
1403 p = &((tx_q->dma_etx + i)->basic);
1404 else
1405 p = tx_q->dma_tx + i;
1406
44c67f85 1407 stmmac_clear_desc(priv, p);
ce736788
JP		 1408
1409 tx_q->tx_skbuff_dma[i].buf = 0;
1410 tx_q->tx_skbuff_dma[i].map_as_page = false;
1411 tx_q->tx_skbuff_dma[i].len = 0;
1412 tx_q->tx_skbuff_dma[i].last_segment = false;
1413 tx_q->tx_skbuff[i] = NULL;
5bacd778 1414 }
aff3d9ef 1415
ce736788
JP		 1416 tx_q->dirty_tx = 0;
1417 tx_q->cur_tx = 0;
8d212a9e 1418 tx_q->mss = 0;
286a8372 1419
c22a3f48
JP		 1420 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1421 }
aff3d9ef 1422
71fedb01
JP		 1423 return 0;
1424}
1425
1426/**
1427 * init_dma_desc_rings - init the RX/TX descriptor rings
1428 * @dev: net device structure
1429 * @flags: gfp flag.
1430 * Description: this function initializes the DMA RX/TX descriptors
1431 * and allocates the socket buffers. It supports the chained and ring
1432 * modes.
1433 */
1434static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1435{
1436 struct stmmac_priv *priv = netdev_priv(dev);
1437 int ret;
1438
1439 ret = init_dma_rx_desc_rings(dev, flags);
1440 if (ret)
1441 return ret;
1442
1443 ret = init_dma_tx_desc_rings(dev);
1444
5bacd778 1445 stmmac_clear_descriptors(priv);
47dd7a54 1446
c24602ef
GC		 1447 if (netif_msg_hw(priv))
1448 stmmac_display_rings(priv);
56329137 1449
56329137 1450 return ret;
47dd7a54
GC		 1451}
1452
71fedb01
JP		 1453/**
1454 * dma_free_rx_skbufs - free RX dma buffers
1455 * @priv: private structure
54139cf3 1456 * @queue: RX queue index
71fedb01 1457 */
54139cf3 1458static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
47dd7a54
GC		 1459{
1460 int i;
1461
e3ad57c9 1462 for (i = 0; i < DMA_RX_SIZE; i++)
54139cf3 1463 stmmac_free_rx_buffer(priv, queue, i);
47dd7a54
GC		 1464}
1465
71fedb01
JP		 1466/**
1467 * dma_free_tx_skbufs - free TX dma buffers
1468 * @priv: private structure
ce736788 1469 * @queue: TX queue index
71fedb01 1470 */
ce736788 1471static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
47dd7a54
GC		 1472{
1473 int i;
1474
71fedb01 1475 for (i = 0; i < DMA_TX_SIZE; i++)
ce736788 1476 stmmac_free_tx_buffer(priv, queue, i);
47dd7a54
GC		 1477}
1478
54139cf3
JP		 1479/**
1480 * free_dma_rx_desc_resources - free RX dma desc resources
1481 * @priv: private structure
1482 */
1483static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1484{
1485 u32 rx_count = priv->plat->rx_queues_to_use;
1486 u32 queue;
1487
1488 /* Free RX queue resources */
1489 for (queue = 0; queue < rx_count; queue++) {
1490 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1491
1492 /* Release the DMA RX socket buffers */
1493 dma_free_rx_skbufs(priv, queue);
1494
1495 /* Free DMA regions of consistent memory previously allocated */
1496 if (!priv->extend_desc)
1497 dma_free_coherent(priv->device,
1498 DMA_RX_SIZE * sizeof(struct dma_desc),
1499 rx_q->dma_rx, rx_q->dma_rx_phy);
1500 else
1501 dma_free_coherent(priv->device, DMA_RX_SIZE *
1502 sizeof(struct dma_extended_desc),
1503 rx_q->dma_erx, rx_q->dma_rx_phy);
1504
2af6106a 1505 kfree(rx_q->buf_pool);
c3f812ce 1506 if (rx_q->page_pool)
2af6106a 1507 page_pool_destroy(rx_q->page_pool);
54139cf3
JP		 1508 }
1509}
1510
ce736788
JP		 1511/**
1512 * free_dma_tx_desc_resources - free TX dma desc resources
1513 * @priv: private structure
1514 */
1515static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1516{
1517 u32 tx_count = priv->plat->tx_queues_to_use;
62242260 1518 u32 queue;
ce736788
JP		 1519
1520 /* Free TX queue resources */
1521 for (queue = 0; queue < tx_count; queue++) {
1522 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1523
1524 /* Release the DMA TX socket buffers */
1525 dma_free_tx_skbufs(priv, queue);
1526
1527 /* Free DMA regions of consistent memory previously allocated */
1528 if (!priv->extend_desc)
1529 dma_free_coherent(priv->device,
1530 DMA_TX_SIZE * sizeof(struct dma_desc),
1531 tx_q->dma_tx, tx_q->dma_tx_phy);
1532 else
1533 dma_free_coherent(priv->device, DMA_TX_SIZE *
1534 sizeof(struct dma_extended_desc),
1535 tx_q->dma_etx, tx_q->dma_tx_phy);
1536
1537 kfree(tx_q->tx_skbuff_dma);
1538 kfree(tx_q->tx_skbuff);
1539 }
1540}
1541
732fdf0e 1542/**
71fedb01 1543 * alloc_dma_rx_desc_resources - alloc RX resources.
732fdf0e
GC		 1544 * @priv: private structure
1545 * Description: according to which descriptor can be used (extend or basic)
5bacd778
LC		 1546 * this function allocates the resources for TX and RX paths. In case of
1547 * reception, for example, it pre-allocated the RX socket buffer in order to
1548 * allow zero-copy mechanism.
732fdf0e 1549 */
71fedb01 1550static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
09f8d696 1551{
54139cf3 1552 u32 rx_count = priv->plat->rx_queues_to_use;
09f8d696 1553 int ret = -ENOMEM;
54139cf3 1554 u32 queue;
09f8d696 1555
54139cf3
JP		 1556 /* RX queues buffers and DMA */
1557 for (queue = 0; queue < rx_count; queue++) {
1558 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
2af6106a 1559 struct page_pool_params pp_params = { 0 };
4f28bd95 1560 unsigned int num_pages;
09f8d696 1561
54139cf3
JP		 1562 rx_q->queue_index = queue;
1563 rx_q->priv_data = priv;
5bacd778 1564
2af6106a
JA		 1565 pp_params.flags = PP_FLAG_DMA_MAP;
1566 pp_params.pool_size = DMA_RX_SIZE;
4f28bd95
TR		 1567 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1568 pp_params.order = ilog2(num_pages);
2af6106a
JA		 1569 pp_params.nid = dev_to_node(priv->device);
1570 pp_params.dev = priv->device;
1571 pp_params.dma_dir = DMA_FROM_DEVICE;
1572
1573 rx_q->page_pool = page_pool_create(&pp_params);
1574 if (IS_ERR(rx_q->page_pool)) {
1575 ret = PTR_ERR(rx_q->page_pool);
1576 rx_q->page_pool = NULL;
63c3aa6b 1577 goto err_dma;
2af6106a 1578 }
71fedb01 1579
ec5e5ce1
JA		 1580 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool),
1581 GFP_KERNEL);
2af6106a 1582 if (!rx_q->buf_pool)
71fedb01 1583 goto err_dma;
54139cf3
JP		 1584
1585 if (priv->extend_desc) {
750afb08
LC		 1586 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1587 DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1588 &rx_q->dma_rx_phy,
1589 GFP_KERNEL);
54139cf3
JP		 1590 if (!rx_q->dma_erx)
1591 goto err_dma;
1592
1593 } else {
750afb08
LC		 1594 rx_q->dma_rx = dma_alloc_coherent(priv->device,
1595 DMA_RX_SIZE * sizeof(struct dma_desc),
1596 &rx_q->dma_rx_phy,
1597 GFP_KERNEL);
54139cf3
JP		 1598 if (!rx_q->dma_rx)
1599 goto err_dma;
1600 }
71fedb01
JP		 1601 }
1602
1603 return 0;
1604
1605err_dma:
54139cf3
JP		 1606 free_dma_rx_desc_resources(priv);
1607
71fedb01
JP		 1608 return ret;
1609}
1610
1611/**
1612 * alloc_dma_tx_desc_resources - alloc TX resources.
1613 * @priv: private structure
1614 * Description: according to which descriptor can be used (extend or basic)
1615 * this function allocates the resources for TX and RX paths. In case of
1616 * reception, for example, it pre-allocated the RX socket buffer in order to
1617 * allow zero-copy mechanism.
1618 */
1619static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1620{
ce736788 1621 u32 tx_count = priv->plat->tx_queues_to_use;
71fedb01 1622 int ret = -ENOMEM;
ce736788 1623 u32 queue;
71fedb01 1624
ce736788
JP		 1625 /* TX queues buffers and DMA */
1626 for (queue = 0; queue < tx_count; queue++) {
1627 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
5bacd778 1628
ce736788
JP		 1629 tx_q->queue_index = queue;
1630 tx_q->priv_data = priv;
5bacd778 1631
ec5e5ce1
JA		 1632 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE,
1633 sizeof(*tx_q->tx_skbuff_dma),
1634 GFP_KERNEL);
ce736788 1635 if (!tx_q->tx_skbuff_dma)
62242260 1636 goto err_dma;
ce736788 1637
ec5e5ce1
JA		 1638 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE,
1639 sizeof(struct sk_buff *),
1640 GFP_KERNEL);
ce736788 1641 if (!tx_q->tx_skbuff)
62242260 1642 goto err_dma;
ce736788
JP		 1643
1644 if (priv->extend_desc) {
750afb08
LC		 1645 tx_q->dma_etx = dma_alloc_coherent(priv->device,
1646 DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1647 &tx_q->dma_tx_phy,
1648 GFP_KERNEL);
ce736788 1649 if (!tx_q->dma_etx)
62242260 1650 goto err_dma;
ce736788 1651 } else {
750afb08
LC		 1652 tx_q->dma_tx = dma_alloc_coherent(priv->device,
1653 DMA_TX_SIZE * sizeof(struct dma_desc),
1654 &tx_q->dma_tx_phy,
1655 GFP_KERNEL);
ce736788 1656 if (!tx_q->dma_tx)
62242260 1657 goto err_dma;
ce736788 1658 }
09f8d696
SK		 1659 }
1660
1661 return 0;
1662
62242260 1663err_dma:
ce736788
JP		 1664 free_dma_tx_desc_resources(priv);
1665
09f8d696
SK		 1666 return ret;
1667}
1668
71fedb01
JP		 1669/**
1670 * alloc_dma_desc_resources - alloc TX/RX resources.
1671 * @priv: private structure
1672 * Description: according to which descriptor can be used (extend or basic)
1673 * this function allocates the resources for TX and RX paths. In case of
1674 * reception, for example, it pre-allocated the RX socket buffer in order to
1675 * allow zero-copy mechanism.
1676 */
1677static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1678{
54139cf3 1679 /* RX Allocation */
71fedb01
JP		 1680 int ret = alloc_dma_rx_desc_resources(priv);
1681
1682 if (ret)
1683 return ret;
1684
1685 ret = alloc_dma_tx_desc_resources(priv);
1686
1687 return ret;
1688}
1689
71fedb01
JP		 1690/**
1691 * free_dma_desc_resources - free dma desc resources
1692 * @priv: private structure
1693 */
1694static void free_dma_desc_resources(struct stmmac_priv *priv)
1695{
1696 /* Release the DMA RX socket buffers */
1697 free_dma_rx_desc_resources(priv);
1698
1699 /* Release the DMA TX socket buffers */
1700 free_dma_tx_desc_resources(priv);
1701}
1702
9eb12474 1703/**
1704 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1705 * @priv: driver private structure
1706 * Description: It is used for enabling the rx queues in the MAC
1707 */
1708static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1709{
4f6046f5
JP		 1710 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1711 int queue;
1712 u8 mode;
9eb12474 1713
4f6046f5
JP		 1714 for (queue = 0; queue < rx_queues_count; queue++) {
1715 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
c10d4c82 1716 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
4f6046f5 1717 }
9eb12474 1718}
1719
ae4f0d46
JP		 1720/**
1721 * stmmac_start_rx_dma - start RX DMA channel
1722 * @priv: driver private structure
1723 * @chan: RX channel index
1724 * Description:
1725 * This starts a RX DMA channel
1726 */
1727static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1728{
1729 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
a4e887fa 1730 stmmac_start_rx(priv, priv->ioaddr, chan);
ae4f0d46
JP		 1731}
1732
1733/**
1734 * stmmac_start_tx_dma - start TX DMA channel
1735 * @priv: driver private structure
1736 * @chan: TX channel index
1737 * Description:
1738 * This starts a TX DMA channel
1739 */
1740static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1741{
1742 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
a4e887fa 1743 stmmac_start_tx(priv, priv->ioaddr, chan);
ae4f0d46
JP		 1744}
1745
1746/**
1747 * stmmac_stop_rx_dma - stop RX DMA channel
1748 * @priv: driver private structure
1749 * @chan: RX channel index
1750 * Description:
1751 * This stops a RX DMA channel
1752 */
1753static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1754{
1755 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
a4e887fa 1756 stmmac_stop_rx(priv, priv->ioaddr, chan);
ae4f0d46
JP		 1757}
1758
1759/**
1760 * stmmac_stop_tx_dma - stop TX DMA channel
1761 * @priv: driver private structure
1762 * @chan: TX channel index
1763 * Description:
1764 * This stops a TX DMA channel
1765 */
1766static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1767{
1768 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
a4e887fa 1769 stmmac_stop_tx(priv, priv->ioaddr, chan);
ae4f0d46
JP		 1770}
1771
1772/**
1773 * stmmac_start_all_dma - start all RX and TX DMA channels
1774 * @priv: driver private structure
1775 * Description:
1776 * This starts all the RX and TX DMA channels
1777 */
1778static void stmmac_start_all_dma(struct stmmac_priv *priv)
1779{
1780 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1781 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1782 u32 chan = 0;
1783
1784 for (chan = 0; chan < rx_channels_count; chan++)
1785 stmmac_start_rx_dma(priv, chan);
1786
1787 for (chan = 0; chan < tx_channels_count; chan++)
1788 stmmac_start_tx_dma(priv, chan);
1789}
1790
1791/**
1792 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1793 * @priv: driver private structure
1794 * Description:
1795 * This stops the RX and TX DMA channels
1796 */
1797static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1798{
1799 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1800 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1801 u32 chan = 0;
1802
1803 for (chan = 0; chan < rx_channels_count; chan++)
1804 stmmac_stop_rx_dma(priv, chan);
1805
1806 for (chan = 0; chan < tx_channels_count; chan++)
1807 stmmac_stop_tx_dma(priv, chan);
1808}
1809
47dd7a54
GC		 1810/**
1811 * stmmac_dma_operation_mode - HW DMA operation mode
32ceabca 1812 * @priv: driver private structure
732fdf0e
GC		 1813 * Description: it is used for configuring the DMA operation mode register in
1814 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
47dd7a54
GC		 1815 */
1816static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1817{
6deee222
JP		 1818 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1819 u32 tx_channels_count = priv->plat->tx_queues_to_use;
f88203a2 1820 int rxfifosz = priv->plat->rx_fifo_size;
52a76235 1821 int txfifosz = priv->plat->tx_fifo_size;
6deee222
JP		 1822 u32 txmode = 0;
1823 u32 rxmode = 0;
1824 u32 chan = 0;
a0daae13 1825 u8 qmode = 0;
f88203a2 1826
11fbf811
TR		 1827 if (rxfifosz == 0)
1828 rxfifosz = priv->dma_cap.rx_fifo_size;
52a76235
JA		 1829 if (txfifosz == 0)
1830 txfifosz = priv->dma_cap.tx_fifo_size;
1831
1832 /* Adjust for real per queue fifo size */
1833 rxfifosz /= rx_channels_count;
1834 txfifosz /= tx_channels_count;
11fbf811 1835
6deee222
JP		 1836 if (priv->plat->force_thresh_dma_mode) {
1837 txmode = tc;
1838 rxmode = tc;
1839 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
61b8013a
SK		 1840 /*
1841 * In case of GMAC, SF mode can be enabled
1842 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 1843 * 1) TX COE if actually supported
1844 * 2) There is no bugged Jumbo frame support
1845 * that needs to not insert csum in the TDES.
1846 */
6deee222
JP		 1847 txmode = SF_DMA_MODE;
1848 rxmode = SF_DMA_MODE;
b2dec116 1849 priv->xstats.threshold = SF_DMA_MODE;
6deee222
JP		 1850 } else {
1851 txmode = tc;
1852 rxmode = SF_DMA_MODE;
1853 }
1854
1855 /* configure all channels */
ab0204e3
JA		 1856 for (chan = 0; chan < rx_channels_count; chan++) {
1857 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
a0daae13 1858
ab0204e3
JA		 1859 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1860 rxfifosz, qmode);
4205c88e
JA		 1861 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1862 chan);
ab0204e3 1863 }
a0daae13 1864
ab0204e3
JA		 1865 for (chan = 0; chan < tx_channels_count; chan++) {
1866 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
6deee222 1867
ab0204e3
JA		 1868 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1869 txfifosz, qmode);
6deee222 1870 }
47dd7a54
GC		 1871}
1872
47dd7a54 1873/**
732fdf0e 1874 * stmmac_tx_clean - to manage the transmission completion
32ceabca 1875 * @priv: driver private structure
ce736788 1876 * @queue: TX queue index
732fdf0e 1877 * Description: it reclaims the transmit resources after transmission completes.
47dd7a54 1878 */
8fce3331 1879static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
47dd7a54 1880{
ce736788 1881 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
38979574 1882 unsigned int bytes_compl = 0, pkts_compl = 0;
8fce3331 1883 unsigned int entry, count = 0;
47dd7a54 1884
8fce3331 1885 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
a9097a96 1886
9125cdd1
GC		 1887 priv->xstats.tx_clean++;
1888
8d5f4b07 1889 entry = tx_q->dirty_tx;
8fce3331 1890 while ((entry != tx_q->cur_tx) && (count < budget)) {
ce736788 1891 struct sk_buff *skb = tx_q->tx_skbuff[entry];
c24602ef 1892 struct dma_desc *p;
c363b658 1893 int status;
c24602ef
GC		 1894
1895 if (priv->extend_desc)
ce736788 1896 p = (struct dma_desc *)(tx_q->dma_etx + entry);
c24602ef 1897 else
ce736788 1898 p = tx_q->dma_tx + entry;
47dd7a54 1899
42de047d
JA		 1900 status = stmmac_tx_status(priv, &priv->dev->stats,
1901 &priv->xstats, p, priv->ioaddr);
c363b658
FG		 1902 /* Check if the descriptor is owned by the DMA */
1903 if (unlikely(status & tx_dma_own))
1904 break;
1905
8fce3331
JA		 1906 count++;
1907
a6b25da5
NC		 1908 /* Make sure descriptor fields are read after reading
1909 * the own bit.
1910 */
1911 dma_rmb();
1912
c363b658
FG		 1913 /* Just consider the last segment and ...*/
1914 if (likely(!(status & tx_not_ls))) {
1915 /* ... verify the status error condition */
1916 if (unlikely(status & tx_err)) {
1917 priv->dev->stats.tx_errors++;
1918 } else {
47dd7a54
GC		 1919 priv->dev->stats.tx_packets++;
1920 priv->xstats.tx_pkt_n++;
c363b658 1921 }
ba1ffd74 1922 stmmac_get_tx_hwtstamp(priv, p, skb);
47dd7a54 1923 }
47dd7a54 1924
ce736788
JP		 1925 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1926 if (tx_q->tx_skbuff_dma[entry].map_as_page)
362b37be 1927 dma_unmap_page(priv->device,
ce736788
JP		 1928 tx_q->tx_skbuff_dma[entry].buf,
1929 tx_q->tx_skbuff_dma[entry].len,
362b37be
GC		 1930 DMA_TO_DEVICE);
1931 else
1932 dma_unmap_single(priv->device,
ce736788
JP		 1933 tx_q->tx_skbuff_dma[entry].buf,
1934 tx_q->tx_skbuff_dma[entry].len,
362b37be 1935 DMA_TO_DEVICE);
ce736788
JP		 1936 tx_q->tx_skbuff_dma[entry].buf = 0;
1937 tx_q->tx_skbuff_dma[entry].len = 0;
1938 tx_q->tx_skbuff_dma[entry].map_as_page = false;
cf32deec 1939 }
f748be53 1940
2c520b1c 1941 stmmac_clean_desc3(priv, tx_q, p);
f748be53 1942
ce736788
JP		 1943 tx_q->tx_skbuff_dma[entry].last_segment = false;
1944 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
47dd7a54
GC		 1945
1946 if (likely(skb != NULL)) {
38979574
BG		 1947 pkts_compl++;
1948 bytes_compl += skb->len;
7c565c33 1949 dev_consume_skb_any(skb);
ce736788 1950 tx_q->tx_skbuff[entry] = NULL;
47dd7a54
GC		 1951 }
1952
42de047d 1953 stmmac_release_tx_desc(priv, p, priv->mode);
47dd7a54 1954
e3ad57c9 1955 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
47dd7a54 1956 }
ce736788 1957 tx_q->dirty_tx = entry;
38979574 1958
c22a3f48
JP		 1959 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1960 pkts_compl, bytes_compl);
1961
1962 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1963 queue))) &&
1964 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
38979574 1965
739c8e14
LS		 1966 netif_dbg(priv, tx_done, priv->dev,
1967 "%s: restart transmit\n", __func__);
c22a3f48 1968 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
47dd7a54 1969 }
d765955d
GC		 1970
1971 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1972 stmmac_enable_eee_mode(priv);
f5351ef7 1973 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
d765955d 1974 }
8fce3331 1975
4ccb4585
JA		 1976 /* We still have pending packets, let's call for a new scheduling */
1977 if (tx_q->dirty_tx != tx_q->cur_tx)
1978 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1979
8fce3331
JA		 1980 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1981
1982 return count;
47dd7a54
GC		 1983}
1984
47dd7a54 1985/**
732fdf0e 1986 * stmmac_tx_err - to manage the tx error
32ceabca 1987 * @priv: driver private structure
5bacd778 1988 * @chan: channel index
47dd7a54 1989 * Description: it cleans the descriptors and restarts the transmission
732fdf0e 1990 * in case of transmission errors.
47dd7a54 1991 */
5bacd778 1992static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
47dd7a54 1993{
ce736788 1994 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
c24602ef 1995 int i;
ce736788 1996
c22a3f48 1997 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
47dd7a54 1998
ae4f0d46 1999 stmmac_stop_tx_dma(priv, chan);
ce736788 2000 dma_free_tx_skbufs(priv, chan);
e3ad57c9 2001 for (i = 0; i < DMA_TX_SIZE; i++)
c24602ef 2002 if (priv->extend_desc)
42de047d
JA		 2003 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
2004 priv->mode, (i == DMA_TX_SIZE - 1));
c24602ef 2005 else
42de047d
JA		 2006 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
2007 priv->mode, (i == DMA_TX_SIZE - 1));
ce736788
JP		 2008 tx_q->dirty_tx = 0;
2009 tx_q->cur_tx = 0;
8d212a9e 2010 tx_q->mss = 0;
c22a3f48 2011 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
ae4f0d46 2012 stmmac_start_tx_dma(priv, chan);
47dd7a54
GC		 2013
2014 priv->dev->stats.tx_errors++;
c22a3f48 2015 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
47dd7a54
GC		 2016}
2017
6deee222
JP		 2018/**
2019 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2020 * @priv: driver private structure
2021 * @txmode: TX operating mode
2022 * @rxmode: RX operating mode
2023 * @chan: channel index
2024 * Description: it is used for configuring of the DMA operation mode in
2025 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2026 * mode.
2027 */
2028static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2029 u32 rxmode, u32 chan)
2030{
a0daae13
JA		 2031 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2032 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
52a76235
JA		 2033 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2034 u32 tx_channels_count = priv->plat->tx_queues_to_use;
6deee222 2035 int rxfifosz = priv->plat->rx_fifo_size;
52a76235 2036 int txfifosz = priv->plat->tx_fifo_size;
6deee222
JP		 2037
2038 if (rxfifosz == 0)
2039 rxfifosz = priv->dma_cap.rx_fifo_size;
52a76235
JA		 2040 if (txfifosz == 0)
2041 txfifosz = priv->dma_cap.tx_fifo_size;
2042
2043 /* Adjust for real per queue fifo size */
2044 rxfifosz /= rx_channels_count;
2045 txfifosz /= tx_channels_count;
6deee222 2046
ab0204e3
JA		 2047 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2048 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
6deee222
JP		 2049}
2050
8bf993a5
JA		 2051static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2052{
63a550fc 2053 int ret;
8bf993a5 2054
c10d4c82
JA		 2055 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2056 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2057 if (ret && (ret != -EINVAL)) {
8bf993a5 2058 stmmac_global_err(priv);
c10d4c82
JA		 2059 return true;
2060 }
2061
2062 return false;
8bf993a5
JA		 2063}
2064
8fce3331
JA		 2065static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2066{
2067 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2068 &priv->xstats, chan);
2069 struct stmmac_channel *ch = &priv->channel[chan];
8fce3331 2070
4ccb4585 2071 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
3ba07deb
JA		 2072 if (napi_schedule_prep(&ch->rx_napi)) {
2073 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2074 __napi_schedule_irqoff(&ch->rx_napi);
2075 status |= handle_tx;
2076 }
8fce3331
JA		 2077 }
2078
a66b5884 2079 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use))
4ccb4585 2080 napi_schedule_irqoff(&ch->tx_napi);
8fce3331
JA		 2081
2082 return status;
2083}
2084
32ceabca 2085/**
732fdf0e 2086 * stmmac_dma_interrupt - DMA ISR
32ceabca
GC		 2087 * @priv: driver private structure
2088 * Description: this is the DMA ISR. It is called by the main ISR.
732fdf0e
GC		 2089 * It calls the dwmac dma routine and schedule poll method in case of some
2090 * work can be done.
32ceabca 2091 */
aec7ff27
GC		 2092static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2093{
d62a107a 2094 u32 tx_channel_count = priv->plat->tx_queues_to_use;
5a6a0445
NC		 2095 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2096 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2097 tx_channel_count : rx_channel_count;
d62a107a 2098 u32 chan;
8ac60ffb
KC		 2099 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2100
2101 /* Make sure we never check beyond our status buffer. */
2102 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2103 channels_to_check = ARRAY_SIZE(status);
5a6a0445 2104
5a6a0445 2105 for (chan = 0; chan < channels_to_check; chan++)
8fce3331 2106 status[chan] = stmmac_napi_check(priv, chan);
6deee222 2107
5a6a0445
NC		 2108 for (chan = 0; chan < tx_channel_count; chan++) {
2109 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
d62a107a
JP		 2110 /* Try to bump up the dma threshold on this failure */
2111 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2112 (tc <= 256)) {
2113 tc += 64;
2114 if (priv->plat->force_thresh_dma_mode)
2115 stmmac_set_dma_operation_mode(priv,
2116 tc,
2117 tc,
2118 chan);
2119 else
2120 stmmac_set_dma_operation_mode(priv,
2121 tc,
2122 SF_DMA_MODE,
2123 chan);
2124 priv->xstats.threshold = tc;
2125 }
5a6a0445 2126 } else if (unlikely(status[chan] == tx_hard_error)) {
d62a107a 2127 stmmac_tx_err(priv, chan);
47dd7a54 2128 }
d62a107a 2129 }
47dd7a54
GC		 2130}
2131
32ceabca
GC		 2132/**
2133 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2134 * @priv: driver private structure
2135 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2136 */
1c901a46
GC		 2137static void stmmac_mmc_setup(struct stmmac_priv *priv)
2138{
2139 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
36ff7c1e 2140 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1c901a46 2141
3b1dd2c5 2142 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
4f795b25
GC		 2143
2144 if (priv->dma_cap.rmon) {
3b1dd2c5 2145 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
4f795b25
GC		 2146 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2147 } else
38ddc59d 2148 netdev_info(priv->dev, "No MAC Management Counters available\n");
1c901a46
GC		 2149}
2150
19e30c14 2151/**
732fdf0e 2152 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
32ceabca 2153 * @priv: driver private structure
19e30c14
GC		 2154 * Description:
2155 * new GMAC chip generations have a new register to indicate the
2156 * presence of the optional feature/functions.
2157 * This can be also used to override the value passed through the
2158 * platform and necessary for old MAC10/100 and GMAC chips.
e7434821
GC		 2159 */
2160static int stmmac_get_hw_features(struct stmmac_priv *priv)
2161{
a4e887fa 2162 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
e7434821
GC		 2163}
2164
32ceabca 2165/**
732fdf0e 2166 * stmmac_check_ether_addr - check if the MAC addr is valid
32ceabca
GC		 2167 * @priv: driver private structure
2168 * Description:
2169 * it is to verify if the MAC address is valid, in case of failures it
2170 * generates a random MAC address
2171 */
bfab27a1
GC		 2172static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2173{
bfab27a1 2174 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
c10d4c82 2175 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
ceb69499 2176 if (!is_valid_ether_addr(priv->dev->dev_addr))
f2cedb63 2177 eth_hw_addr_random(priv->dev);
af649352
JZ		 2178 dev_info(priv->device, "device MAC address %pM\n",
2179 priv->dev->dev_addr);
bfab27a1 2180 }
bfab27a1
GC		 2181}
2182
32ceabca 2183/**
732fdf0e 2184 * stmmac_init_dma_engine - DMA init.
32ceabca
GC		 2185 * @priv: driver private structure
2186 * Description:
2187 * It inits the DMA invoking the specific MAC/GMAC callback.
2188 * Some DMA parameters can be passed from the platform;
2189 * in case of these are not passed a default is kept for the MAC or GMAC.
2190 */
0f1f88a8
GC		 2191static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2192{
47f2a9ce
JP		 2193 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2194 u32 tx_channels_count = priv->plat->tx_queues_to_use;
24aaed0c 2195 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
54139cf3 2196 struct stmmac_rx_queue *rx_q;
ce736788 2197 struct stmmac_tx_queue *tx_q;
47f2a9ce 2198 u32 chan = 0;
c24602ef 2199 int atds = 0;
495db273 2200 int ret = 0;
0f1f88a8 2201
a332e2fa
NC		 2202 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2203 dev_err(priv->device, "Invalid DMA configuration\n");
89ab75bf 2204 return -EINVAL;
0f1f88a8
GC		 2205 }
2206
c24602ef
GC		 2207 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2208 atds = 1;
2209
a4e887fa 2210 ret = stmmac_reset(priv, priv->ioaddr);
495db273
GC		 2211 if (ret) {
2212 dev_err(priv->device, "Failed to reset the dma\n");
2213 return ret;
2214 }
2215
7d9e6c5a
JA		 2216 /* DMA Configuration */
2217 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2218
2219 if (priv->plat->axi)
2220 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2221
af8f3fb7
WV		 2222 /* DMA CSR Channel configuration */
2223 for (chan = 0; chan < dma_csr_ch; chan++)
2224 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2225
24aaed0c
JA		 2226 /* DMA RX Channel Configuration */
2227 for (chan = 0; chan < rx_channels_count; chan++) {
2228 rx_q = &priv->rx_queue[chan];
47f2a9ce 2229
24aaed0c
JA		 2230 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2231 rx_q->dma_rx_phy, chan);
54139cf3 2232
24aaed0c
JA		 2233 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2234 (DMA_RX_SIZE * sizeof(struct dma_desc));
2235 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2236 rx_q->rx_tail_addr, chan);
2237 }
47f2a9ce 2238
24aaed0c
JA		 2239 /* DMA TX Channel Configuration */
2240 for (chan = 0; chan < tx_channels_count; chan++) {
2241 tx_q = &priv->tx_queue[chan];
47f2a9ce 2242
24aaed0c
JA		 2243 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2244 tx_q->dma_tx_phy, chan);
ce736788 2245
0431100b 2246 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
24aaed0c
JA		 2247 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2248 tx_q->tx_tail_addr, chan);
2249 }
47f2a9ce 2250
495db273 2251 return ret;
0f1f88a8
GC		 2252}
2253
8fce3331
JA		 2254static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2255{
2256 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2257
2258 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2259}
2260
9125cdd1 2261/**
732fdf0e 2262 * stmmac_tx_timer - mitigation sw timer for tx.
9125cdd1
GC		 2263 * @data: data pointer
2264 * Description:
2265 * This is the timer handler to directly invoke the stmmac_tx_clean.
2266 */
e99e88a9 2267static void stmmac_tx_timer(struct timer_list *t)
9125cdd1 2268{
8fce3331
JA		 2269 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2270 struct stmmac_priv *priv = tx_q->priv_data;
2271 struct stmmac_channel *ch;
2272
2273 ch = &priv->channel[tx_q->queue_index];
9125cdd1 2274
4ccb4585
JA		 2275 /*
2276 * If NAPI is already running we can miss some events. Let's rearm
2277 * the timer and try again.
2278 */
2279 if (likely(napi_schedule_prep(&ch->tx_napi)))
2280 __napi_schedule(&ch->tx_napi);
2281 else
2282 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
9125cdd1
GC		 2283}
2284
2285/**
d429b66e 2286 * stmmac_init_coalesce - init mitigation options.
32ceabca 2287 * @priv: driver private structure
9125cdd1 2288 * Description:
d429b66e 2289 * This inits the coalesce parameters: i.e. timer rate,
9125cdd1
GC		 2290 * timer handler and default threshold used for enabling the
2291 * interrupt on completion bit.
2292 */
d429b66e 2293static void stmmac_init_coalesce(struct stmmac_priv *priv)
9125cdd1 2294{
8fce3331
JA		 2295 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2296 u32 chan;
2297
9125cdd1
GC		 2298 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2299 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
d429b66e 2300 priv->rx_coal_frames = STMMAC_RX_FRAMES;
8fce3331
JA		 2301
2302 for (chan = 0; chan < tx_channel_count; chan++) {
2303 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2304
2305 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2306 }
9125cdd1
GC		 2307}
2308
4854ab99
JP		 2309static void stmmac_set_rings_length(struct stmmac_priv *priv)
2310{
2311 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2312 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2313 u32 chan;
2314
2315 /* set TX ring length */
a4e887fa
JA		 2316 for (chan = 0; chan < tx_channels_count; chan++)
2317 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2318 (DMA_TX_SIZE - 1), chan);
4854ab99
JP		 2319
2320 /* set RX ring length */
a4e887fa
JA		 2321 for (chan = 0; chan < rx_channels_count; chan++)
2322 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2323 (DMA_RX_SIZE - 1), chan);
4854ab99
JP		 2324}
2325
6a3a7193
JP		 2326/**
2327 * stmmac_set_tx_queue_weight - Set TX queue weight
2328 * @priv: driver private structure
2329 * Description: It is used for setting TX queues weight
2330 */
2331static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2332{
2333 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2334 u32 weight;
2335 u32 queue;
2336
2337 for (queue = 0; queue < tx_queues_count; queue++) {
2338 weight = priv->plat->tx_queues_cfg[queue].weight;
c10d4c82 2339 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
6a3a7193
JP		 2340 }
2341}
2342
19d91873
JP		 2343/**
2344 * stmmac_configure_cbs - Configure CBS in TX queue
2345 * @priv: driver private structure
2346 * Description: It is used for configuring CBS in AVB TX queues
2347 */
2348static void stmmac_configure_cbs(struct stmmac_priv *priv)
2349{
2350 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2351 u32 mode_to_use;
2352 u32 queue;
2353
44781fef
JP		 2354 /* queue 0 is reserved for legacy traffic */
2355 for (queue = 1; queue < tx_queues_count; queue++) {
19d91873
JP		 2356 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2357 if (mode_to_use == MTL_QUEUE_DCB)
2358 continue;
2359
c10d4c82 2360 stmmac_config_cbs(priv, priv->hw,
19d91873
JP		 2361 priv->plat->tx_queues_cfg[queue].send_slope,
2362 priv->plat->tx_queues_cfg[queue].idle_slope,
2363 priv->plat->tx_queues_cfg[queue].high_credit,
2364 priv->plat->tx_queues_cfg[queue].low_credit,
2365 queue);
2366 }
2367}
2368
d43042f4
JP		 2369/**
2370 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2371 * @priv: driver private structure
2372 * Description: It is used for mapping RX queues to RX dma channels
2373 */
2374static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2375{
2376 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2377 u32 queue;
2378 u32 chan;
2379
2380 for (queue = 0; queue < rx_queues_count; queue++) {
2381 chan = priv->plat->rx_queues_cfg[queue].chan;
c10d4c82 2382 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
d43042f4
JP		 2383 }
2384}
2385
a8f5102a
JP		 2386/**
2387 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2388 * @priv: driver private structure
2389 * Description: It is used for configuring the RX Queue Priority
2390 */
2391static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2392{
2393 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2394 u32 queue;
2395 u32 prio;
2396
2397 for (queue = 0; queue < rx_queues_count; queue++) {
2398 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2399 continue;
2400
2401 prio = priv->plat->rx_queues_cfg[queue].prio;
c10d4c82 2402 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
a8f5102a
JP		 2403 }
2404}
2405
2406/**
2407 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2408 * @priv: driver private structure
2409 * Description: It is used for configuring the TX Queue Priority
2410 */
2411static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2412{
2413 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2414 u32 queue;
2415 u32 prio;
2416
2417 for (queue = 0; queue < tx_queues_count; queue++) {
2418 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2419 continue;
2420
2421 prio = priv->plat->tx_queues_cfg[queue].prio;
c10d4c82 2422 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
a8f5102a
JP		 2423 }
2424}
2425
abe80fdc
JP		 2426/**
2427 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2428 * @priv: driver private structure
2429 * Description: It is used for configuring the RX queue routing
2430 */
2431static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2432{
2433 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2434 u32 queue;
2435 u8 packet;
2436
2437 for (queue = 0; queue < rx_queues_count; queue++) {
2438 /* no specific packet type routing specified for the queue */
2439 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2440 continue;
2441
2442 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
c10d4c82 2443 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
abe80fdc
JP		 2444 }
2445}
2446
76067459
JA		 2447static void stmmac_mac_config_rss(struct stmmac_priv *priv)
2448{
2449 if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
2450 priv->rss.enable = false;
2451 return;
2452 }
2453
2454 if (priv->dev->features & NETIF_F_RXHASH)
2455 priv->rss.enable = true;
2456 else
2457 priv->rss.enable = false;
2458
2459 stmmac_rss_configure(priv, priv->hw, &priv->rss,
2460 priv->plat->rx_queues_to_use);
2461}
2462
d0a9c9f9
JP		 2463/**
2464 * stmmac_mtl_configuration - Configure MTL
2465 * @priv: driver private structure
2466 * Description: It is used for configurring MTL
2467 */
2468static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2469{
2470 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2471 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2472
c10d4c82 2473 if (tx_queues_count > 1)
6a3a7193
JP		 2474 stmmac_set_tx_queue_weight(priv);
2475
d0a9c9f9 2476 /* Configure MTL RX algorithms */
c10d4c82
JA		 2477 if (rx_queues_count > 1)
2478 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2479 priv->plat->rx_sched_algorithm);
d0a9c9f9
JP		 2480
2481 /* Configure MTL TX algorithms */
c10d4c82
JA		 2482 if (tx_queues_count > 1)
2483 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2484 priv->plat->tx_sched_algorithm);
d0a9c9f9 2485
19d91873 2486 /* Configure CBS in AVB TX queues */
c10d4c82 2487 if (tx_queues_count > 1)
19d91873
JP		 2488 stmmac_configure_cbs(priv);
2489
d43042f4 2490 /* Map RX MTL to DMA channels */
c10d4c82 2491 stmmac_rx_queue_dma_chan_map(priv);
d43042f4 2492
d0a9c9f9 2493 /* Enable MAC RX Queues */
c10d4c82 2494 stmmac_mac_enable_rx_queues(priv);
6deee222 2495
a8f5102a 2496 /* Set RX priorities */
c10d4c82 2497 if (rx_queues_count > 1)
a8f5102a
JP		 2498 stmmac_mac_config_rx_queues_prio(priv);
2499
2500 /* Set TX priorities */
c10d4c82 2501 if (tx_queues_count > 1)
a8f5102a 2502 stmmac_mac_config_tx_queues_prio(priv);
abe80fdc
JP		 2503
2504 /* Set RX routing */
c10d4c82 2505 if (rx_queues_count > 1)
abe80fdc 2506 stmmac_mac_config_rx_queues_routing(priv);
76067459
JA		 2507
2508 /* Receive Side Scaling */
2509 if (rx_queues_count > 1)
2510 stmmac_mac_config_rss(priv);
d0a9c9f9
JP		 2511}
2512
8bf993a5
JA		 2513static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2514{
c10d4c82 2515 if (priv->dma_cap.asp) {
8bf993a5 2516 netdev_info(priv->dev, "Enabling Safety Features\n");
c10d4c82 2517 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
8bf993a5
JA		 2518 } else {
2519 netdev_info(priv->dev, "No Safety Features support found\n");
2520 }
2521}
2522
523f11b5 2523/**
732fdf0e 2524 * stmmac_hw_setup - setup mac in a usable state.
523f11b5
SK		 2525 * @dev : pointer to the device structure.
2526 * Description:
732fdf0e
GC		 2527 * this is the main function to setup the HW in a usable state because the
2528 * dma engine is reset, the core registers are configured (e.g. AXI,
2529 * Checksum features, timers). The DMA is ready to start receiving and
2530 * transmitting.
523f11b5
SK		 2531 * Return value:
2532 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2533 * file on failure.
2534 */
fe131929 2535static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
523f11b5
SK		 2536{
2537 struct stmmac_priv *priv = netdev_priv(dev);
3c55d4d0 2538 u32 rx_cnt = priv->plat->rx_queues_to_use;
146617b8
JP		 2539 u32 tx_cnt = priv->plat->tx_queues_to_use;
2540 u32 chan;
523f11b5
SK		 2541 int ret;
2542
523f11b5
SK		 2543 /* DMA initialization and SW reset */
2544 ret = stmmac_init_dma_engine(priv);
2545 if (ret < 0) {
38ddc59d
LC		 2546 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2547 __func__);
523f11b5
SK		 2548 return ret;
2549 }
2550
2551 /* Copy the MAC addr into the HW */
c10d4c82 2552 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
523f11b5 2553
02e57b9d
GC		 2554 /* PS and related bits will be programmed according to the speed */
2555 if (priv->hw->pcs) {
2556 int speed = priv->plat->mac_port_sel_speed;
2557
2558 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2559 (speed == SPEED_1000)) {
2560 priv->hw->ps = speed;
2561 } else {
2562 dev_warn(priv->device, "invalid port speed\n");
2563 priv->hw->ps = 0;
2564 }
2565 }
2566
523f11b5 2567 /* Initialize the MAC Core */
c10d4c82 2568 stmmac_core_init(priv, priv->hw, dev);
523f11b5 2569
d0a9c9f9 2570 /* Initialize MTL*/
63a550fc 2571 stmmac_mtl_configuration(priv);
9eb12474 2572
8bf993a5 2573 /* Initialize Safety Features */
63a550fc 2574 stmmac_safety_feat_configuration(priv);
8bf993a5 2575
c10d4c82 2576 ret = stmmac_rx_ipc(priv, priv->hw);
978aded4 2577 if (!ret) {
38ddc59d 2578 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
978aded4 2579 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
d2afb5bd 2580 priv->hw->rx_csum = 0;
978aded4
GC		 2581 }
2582
523f11b5 2583 /* Enable the MAC Rx/Tx */
c10d4c82 2584 stmmac_mac_set(priv, priv->ioaddr, true);
523f11b5 2585
b4f0a661
JP		 2586 /* Set the HW DMA mode and the COE */
2587 stmmac_dma_operation_mode(priv);
2588
523f11b5
SK		 2589 stmmac_mmc_setup(priv);
2590
fe131929 2591 if (init_ptp) {
0ad2be79
TR		 2592 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2593 if (ret < 0)
2594 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2595
fe131929 2596 ret = stmmac_init_ptp(priv);
722eef28
HK		 2597 if (ret == -EOPNOTSUPP)
2598 netdev_warn(priv->dev, "PTP not supported by HW\n");
2599 else if (ret)
2600 netdev_warn(priv->dev, "PTP init failed\n");
fe131929 2601 }
523f11b5 2602
523f11b5
SK		 2603 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2604
a4e887fa 2605 if (priv->use_riwt) {
4e4337cc
JA		 2606 if (!priv->rx_riwt)
2607 priv->rx_riwt = DEF_DMA_RIWT;
2608
2609 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt);
523f11b5
SK		 2610 }
2611
c10d4c82 2612 if (priv->hw->pcs)
c9ad4c10 2613 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
523f11b5 2614
4854ab99
JP		 2615 /* set TX and RX rings length */
2616 stmmac_set_rings_length(priv);
2617
f748be53 2618 /* Enable TSO */
146617b8
JP		 2619 if (priv->tso) {
2620 for (chan = 0; chan < tx_cnt; chan++)
a4e887fa 2621 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
146617b8 2622 }
f748be53 2623
67afd6d1
JA		 2624 /* Enable Split Header */
2625 if (priv->sph && priv->hw->rx_csum) {
2626 for (chan = 0; chan < rx_cnt; chan++)
2627 stmmac_enable_sph(priv, priv->ioaddr, 1, chan);
2628 }
2629
30d93227
JA		 2630 /* VLAN Tag Insertion */
2631 if (priv->dma_cap.vlins)
2632 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
2633
7d9e6c5a
JA		 2634 /* Start the ball rolling... */
2635 stmmac_start_all_dma(priv);
2636
523f11b5
SK		 2637 return 0;
2638}
2639
c66f6c37
TR		 2640static void stmmac_hw_teardown(struct net_device *dev)
2641{
2642 struct stmmac_priv *priv = netdev_priv(dev);
2643
2644 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2645}
2646
47dd7a54
GC		 2647/**
2648 * stmmac_open - open entry point of the driver
2649 * @dev : pointer to the device structure.
2650 * Description:
2651 * This function is the open entry point of the driver.
2652 * Return value:
2653 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2654 * file on failure.
2655 */
2656static int stmmac_open(struct net_device *dev)
2657{
2658 struct stmmac_priv *priv = netdev_priv(dev);
8fce3331 2659 u32 chan;
47dd7a54
GC		 2660 int ret;
2661
3fe5cadb
GC		 2662 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2663 priv->hw->pcs != STMMAC_PCS_TBI &&
2664 priv->hw->pcs != STMMAC_PCS_RTBI) {
e58bb43f
GC		 2665 ret = stmmac_init_phy(dev);
2666 if (ret) {
38ddc59d
LC		 2667 netdev_err(priv->dev,
2668 "%s: Cannot attach to PHY (error: %d)\n",
2669 __func__, ret);
89df20d9 2670 return ret;
e58bb43f 2671 }
f66ffe28 2672 }
47dd7a54 2673
523f11b5
SK		 2674 /* Extra statistics */
2675 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2676 priv->xstats.threshold = tc;
2677
5bacd778 2678 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
22ad3838 2679 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
56329137 2680
5bacd778
LC		 2681 ret = alloc_dma_desc_resources(priv);
2682 if (ret < 0) {
2683 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2684 __func__);
2685 goto dma_desc_error;
2686 }
2687
2688 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2689 if (ret < 0) {
2690 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2691 __func__);
2692 goto init_error;
2693 }
2694
fe131929 2695 ret = stmmac_hw_setup(dev, true);
56329137 2696 if (ret < 0) {
38ddc59d 2697 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
c9324d18 2698 goto init_error;
47dd7a54
GC		 2699 }
2700
d429b66e 2701 stmmac_init_coalesce(priv);
777da230 2702
74371272 2703 phylink_start(priv->phylink);
47dd7a54 2704
f66ffe28
GC		 2705 /* Request the IRQ lines */
2706 ret = request_irq(dev->irq, stmmac_interrupt,
ceb69499 2707 IRQF_SHARED, dev->name, dev);
f66ffe28 2708 if (unlikely(ret < 0)) {
38ddc59d
LC		 2709 netdev_err(priv->dev,
2710 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2711 __func__, dev->irq, ret);
6c1e5abe 2712 goto irq_error;
f66ffe28
GC		 2713 }
2714
7a13f8f5
FV		 2715 /* Request the Wake IRQ in case of another line is used for WoL */
2716 if (priv->wol_irq != dev->irq) {
2717 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2718 IRQF_SHARED, dev->name, dev);
2719 if (unlikely(ret < 0)) {
38ddc59d
LC		 2720 netdev_err(priv->dev,
2721 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2722 __func__, priv->wol_irq, ret);
c9324d18 2723 goto wolirq_error;
7a13f8f5
FV		 2724 }
2725 }
2726
d765955d 2727 /* Request the IRQ lines */
d7ec8584 2728 if (priv->lpi_irq > 0) {
d765955d
GC		 2729 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2730 dev->name, dev);
2731 if (unlikely(ret < 0)) {
38ddc59d
LC		 2732 netdev_err(priv->dev,
2733 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2734 __func__, priv->lpi_irq, ret);
c9324d18 2735 goto lpiirq_error;
d765955d
GC		 2736 }
2737 }
2738
c22a3f48
JP		 2739 stmmac_enable_all_queues(priv);
2740 stmmac_start_all_queues(priv);
f66ffe28 2741
47dd7a54 2742 return 0;
f66ffe28 2743
c9324d18 2744lpiirq_error:
d765955d
GC		 2745 if (priv->wol_irq != dev->irq)
2746 free_irq(priv->wol_irq, dev);
c9324d18 2747wolirq_error:
7a13f8f5 2748 free_irq(dev->irq, dev);
6c1e5abe 2749irq_error:
74371272 2750 phylink_stop(priv->phylink);
7a13f8f5 2751
8fce3331
JA		 2752 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2753 del_timer_sync(&priv->tx_queue[chan].txtimer);
2754
c66f6c37 2755 stmmac_hw_teardown(dev);
c9324d18
GC		 2756init_error:
2757 free_dma_desc_resources(priv);
5bacd778 2758dma_desc_error:
74371272 2759 phylink_disconnect_phy(priv->phylink);
f66ffe28 2760 return ret;
47dd7a54
GC		 2761}
2762
2763/**
2764 * stmmac_release - close entry point of the driver
2765 * @dev : device pointer.
2766 * Description:
2767 * This is the stop entry point of the driver.
2768 */
2769static int stmmac_release(struct net_device *dev)
2770{
2771 struct stmmac_priv *priv = netdev_priv(dev);
8fce3331 2772 u32 chan;
47dd7a54 2773
d765955d
GC		 2774 if (priv->eee_enabled)
2775 del_timer_sync(&priv->eee_ctrl_timer);
2776
47dd7a54 2777 /* Stop and disconnect the PHY */
74371272
JA		 2778 phylink_stop(priv->phylink);
2779 phylink_disconnect_phy(priv->phylink);
47dd7a54 2780
c22a3f48 2781 stmmac_stop_all_queues(priv);
47dd7a54 2782
c22a3f48 2783 stmmac_disable_all_queues(priv);
47dd7a54 2784
8fce3331
JA		 2785 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2786 del_timer_sync(&priv->tx_queue[chan].txtimer);
9125cdd1 2787
47dd7a54
GC		 2788 /* Free the IRQ lines */
2789 free_irq(dev->irq, dev);
7a13f8f5
FV		 2790 if (priv->wol_irq != dev->irq)
2791 free_irq(priv->wol_irq, dev);
d7ec8584 2792 if (priv->lpi_irq > 0)
d765955d 2793 free_irq(priv->lpi_irq, dev);
47dd7a54
GC		 2794
2795 /* Stop TX/RX DMA and clear the descriptors */
ae4f0d46 2796 stmmac_stop_all_dma(priv);
47dd7a54
GC		 2797
2798 /* Release and free the Rx/Tx resources */
2799 free_dma_desc_resources(priv);
2800
19449bfc 2801 /* Disable the MAC Rx/Tx */
c10d4c82 2802 stmmac_mac_set(priv, priv->ioaddr, false);
47dd7a54
GC		 2803
2804 netif_carrier_off(dev);
2805
92ba6888
RK		 2806 stmmac_release_ptp(priv);
2807
47dd7a54
GC		 2808 return 0;
2809}
2810
30d93227
JA		 2811static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
2812 struct stmmac_tx_queue *tx_q)
2813{
2814 u16 tag = 0x0, inner_tag = 0x0;
2815 u32 inner_type = 0x0;
2816 struct dma_desc *p;
2817
2818 if (!priv->dma_cap.vlins)
2819 return false;
2820 if (!skb_vlan_tag_present(skb))
2821 return false;
2822 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
2823 inner_tag = skb_vlan_tag_get(skb);
2824 inner_type = STMMAC_VLAN_INSERT;
2825 }
2826
2827 tag = skb_vlan_tag_get(skb);
2828
2829 p = tx_q->dma_tx + tx_q->cur_tx;
2830 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
2831 return false;
2832
2833 stmmac_set_tx_owner(priv, p);
2834 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2835 return true;
2836}
2837
f748be53
AT		 2838/**
2839 * stmmac_tso_allocator - close entry point of the driver
2840 * @priv: driver private structure
2841 * @des: buffer start address
2842 * @total_len: total length to fill in descriptors
2843 * @last_segmant: condition for the last descriptor
ce736788 2844 * @queue: TX queue index
f748be53
AT		 2845 * Description:
2846 * This function fills descriptor and request new descriptors according to
2847 * buffer length to fill
2848 */
a993db88 2849static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
ce736788 2850 int total_len, bool last_segment, u32 queue)
f748be53 2851{
ce736788 2852 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
f748be53 2853 struct dma_desc *desc;
5bacd778 2854 u32 buff_size;
ce736788 2855 int tmp_len;
f748be53
AT		 2856
2857 tmp_len = total_len;
2858
2859 while (tmp_len > 0) {
a993db88
JA		 2860 dma_addr_t curr_addr;
2861
ce736788 2862 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
b4c9784c 2863 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
ce736788 2864 desc = tx_q->dma_tx + tx_q->cur_tx;
f748be53 2865
a993db88
JA		 2866 curr_addr = des + (total_len - tmp_len);
2867 if (priv->dma_cap.addr64 <= 32)
2868 desc->des0 = cpu_to_le32(curr_addr);
2869 else
2870 stmmac_set_desc_addr(priv, desc, curr_addr);
2871
f748be53
AT		 2872 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2873 TSO_MAX_BUFF_SIZE : tmp_len;
2874
42de047d
JA		 2875 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2876 0, 1,
2877 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2878 0, 0);
f748be53
AT		 2879
2880 tmp_len -= TSO_MAX_BUFF_SIZE;
2881 }
2882}
2883
2884/**
2885 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2886 * @skb : the socket buffer
2887 * @dev : device pointer
2888 * Description: this is the transmit function that is called on TSO frames
2889 * (support available on GMAC4 and newer chips).
2890 * Diagram below show the ring programming in case of TSO frames:
2891 *
2892 * First Descriptor
2893 * --------
2894 * | DES0 |---> buffer1 = L2/L3/L4 header
2895 * | DES1 |---> TCP Payload (can continue on next descr...)
2896 * | DES2 |---> buffer 1 and 2 len
2897 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2898 * --------
2899 * |
2900 * ...
2901 * |
2902 * --------
2903 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2904 * | DES1 | --|
2905 * | DES2 | --> buffer 1 and 2 len
2906 * | DES3 |
2907 * --------
2908 *
2909 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2910 */
2911static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2912{
ce736788 2913 struct dma_desc *desc, *first, *mss_desc = NULL;
f748be53
AT		 2914 struct stmmac_priv *priv = netdev_priv(dev);
2915 int nfrags = skb_shinfo(skb)->nr_frags;
ce736788 2916 u32 queue = skb_get_queue_mapping(skb);
c2837423
JA		 2917 unsigned int first_entry, tx_packets;
2918 int tmp_pay_len = 0, first_tx;
ce736788 2919 struct stmmac_tx_queue *tx_q;
b7766206 2920 u8 proto_hdr_len, hdr;
c2837423 2921 bool has_vlan, set_ic;
ce736788 2922 u32 pay_len, mss;
a993db88 2923 dma_addr_t des;
f748be53
AT		 2924 int i;
2925
ce736788 2926 tx_q = &priv->tx_queue[queue];
c2837423 2927 first_tx = tx_q->cur_tx;
ce736788 2928
f748be53 2929 /* Compute header lengths */
b7766206
JA		 2930 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
2931 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
2932 hdr = sizeof(struct udphdr);
2933 } else {
2934 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2935 hdr = tcp_hdrlen(skb);
2936 }
f748be53
AT		 2937
2938 /* Desc availability based on threshold should be enough safe */
ce736788 2939 if (unlikely(stmmac_tx_avail(priv, queue) <
f748be53 2940 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
c22a3f48
JP		 2941 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2942 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2943 queue));
f748be53 2944 /* This is a hard error, log it. */
38ddc59d
LC		 2945 netdev_err(priv->dev,
2946 "%s: Tx Ring full when queue awake\n",
2947 __func__);
f748be53 2948 }
f748be53
AT		 2949 return NETDEV_TX_BUSY;
2950 }
2951
2952 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2953
2954 mss = skb_shinfo(skb)->gso_size;
2955
2956 /* set new MSS value if needed */
8d212a9e 2957 if (mss != tx_q->mss) {
ce736788 2958 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
42de047d 2959 stmmac_set_mss(priv, mss_desc, mss);
8d212a9e 2960 tx_q->mss = mss;
ce736788 2961 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
b4c9784c 2962 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
f748be53
AT		 2963 }
2964
2965 if (netif_msg_tx_queued(priv)) {
b7766206
JA		 2966 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2967 __func__, hdr, proto_hdr_len, pay_len, mss);
f748be53
AT		 2968 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2969 skb->data_len);
2970 }
2971
30d93227
JA		 2972 /* Check if VLAN can be inserted by HW */
2973 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
2974
ce736788 2975 first_entry = tx_q->cur_tx;
b4c9784c 2976 WARN_ON(tx_q->tx_skbuff[first_entry]);
f748be53 2977
ce736788 2978 desc = tx_q->dma_tx + first_entry;
f748be53
AT		 2979 first = desc;
2980
30d93227
JA		 2981 if (has_vlan)
2982 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
2983
f748be53
AT		 2984 /* first descriptor: fill Headers on Buf1 */
2985 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2986 DMA_TO_DEVICE);
2987 if (dma_mapping_error(priv->device, des))
2988 goto dma_map_err;
2989
ce736788
JP		 2990 tx_q->tx_skbuff_dma[first_entry].buf = des;
2991 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
f748be53 2992
a993db88
JA		 2993 if (priv->dma_cap.addr64 <= 32) {
2994 first->des0 = cpu_to_le32(des);
f748be53 2995
a993db88
JA		 2996 /* Fill start of payload in buff2 of first descriptor */
2997 if (pay_len)
2998 first->des1 = cpu_to_le32(des + proto_hdr_len);
f748be53 2999
a993db88
JA		 3000 /* If needed take extra descriptors to fill the remaining payload */
3001 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
3002 } else {
3003 stmmac_set_desc_addr(priv, first, des);
3004 tmp_pay_len = pay_len;
34c15202 3005 des += proto_hdr_len;
b2f07199 3006 pay_len = 0;
a993db88 3007 }
f748be53 3008
ce736788 3009 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
f748be53
AT		 3010
3011 /* Prepare fragments */
3012 for (i = 0; i < nfrags; i++) {
3013 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3014
3015 des = skb_frag_dma_map(priv->device, frag, 0,
3016 skb_frag_size(frag),
3017 DMA_TO_DEVICE);
937071c1
TR		 3018 if (dma_mapping_error(priv->device, des))
3019 goto dma_map_err;
f748be53
AT		 3020
3021 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
ce736788 3022 (i == nfrags - 1), queue);
f748be53 3023
ce736788
JP		 3024 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
3025 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
ce736788 3026 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
f748be53
AT		 3027 }
3028
ce736788 3029 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
f748be53 3030
05cf0d1b
NC		 3031 /* Only the last descriptor gets to point to the skb. */
3032 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
3033
7df4a3a7 3034 /* Manage tx mitigation */
c2837423
JA		 3035 tx_packets = (tx_q->cur_tx + 1) - first_tx;
3036 tx_q->tx_count_frames += tx_packets;
3037
3038 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
3039 set_ic = true;
3040 else if (!priv->tx_coal_frames)
3041 set_ic = false;
3042 else if (tx_packets > priv->tx_coal_frames)
3043 set_ic = true;
3044 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets)
3045 set_ic = true;
3046 else
3047 set_ic = false;
3048
3049 if (set_ic) {
7df4a3a7
JA		 3050 desc = &tx_q->dma_tx[tx_q->cur_tx];
3051 tx_q->tx_count_frames = 0;
3052 stmmac_set_tx_ic(priv, desc);
3053 priv->xstats.tx_set_ic_bit++;
c2837423
JA		 3054 } else {
3055 stmmac_tx_timer_arm(priv, queue);
7df4a3a7
JA		 3056 }
3057
05cf0d1b
NC		 3058 /* We've used all descriptors we need for this skb, however,
3059 * advance cur_tx so that it references a fresh descriptor.
3060 * ndo_start_xmit will fill this descriptor the next time it's
3061 * called and stmmac_tx_clean may clean up to this descriptor.
3062 */
ce736788 3063 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
f748be53 3064
ce736788 3065 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
b3e51069
LC		 3066 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3067 __func__);
c22a3f48 3068 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
f748be53
AT		 3069 }
3070
3071 dev->stats.tx_bytes += skb->len;
3072 priv->xstats.tx_tso_frames++;
3073 priv->xstats.tx_tso_nfrags += nfrags;
3074
8000ddc0
JA		 3075 if (priv->sarc_type)
3076 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3077
74abc9b1 3078 skb_tx_timestamp(skb);
f748be53
AT		 3079
3080 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3081 priv->hwts_tx_en)) {
3082 /* declare that device is doing timestamping */
3083 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
42de047d 3084 stmmac_enable_tx_timestamp(priv, first);
f748be53
AT		 3085 }
3086
3087 /* Complete the first descriptor before granting the DMA */
42de047d 3088 stmmac_prepare_tso_tx_desc(priv, first, 1,
f748be53
AT		 3089 proto_hdr_len,
3090 pay_len,
ce736788 3091 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
b7766206 3092 hdr / 4, (skb->len - proto_hdr_len));
f748be53
AT		 3093
3094 /* If context desc is used to change MSS */
15d2ee42
NC		 3095 if (mss_desc) {
3096 /* Make sure that first descriptor has been completely
3097 * written, including its own bit. This is because MSS is
3098 * actually before first descriptor, so we need to make
3099 * sure that MSS's own bit is the last thing written.
3100 */
3101 dma_wmb();
42de047d 3102 stmmac_set_tx_owner(priv, mss_desc);
15d2ee42 3103 }
f748be53
AT		 3104
3105 /* The own bit must be the latest setting done when prepare the
3106 * descriptor and then barrier is needed to make sure that
3107 * all is coherent before granting the DMA engine.
3108 */
95eb930a 3109 wmb();
f748be53
AT		 3110
3111 if (netif_msg_pktdata(priv)) {
3112 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
ce736788
JP		 3113 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3114 tx_q->cur_tx, first, nfrags);
f748be53 3115
42de047d 3116 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
f748be53
AT		 3117
3118 pr_info(">>> frame to be transmitted: ");
3119 print_pkt(skb->data, skb_headlen(skb));
3120 }
3121
c22a3f48 3122 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
f748be53 3123
0431100b 3124 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
a4e887fa 3125 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
f748be53 3126
f748be53
AT		 3127 return NETDEV_TX_OK;
3128
3129dma_map_err:
f748be53
AT		 3130 dev_err(priv->device, "Tx dma map failed\n");
3131 dev_kfree_skb(skb);
3132 priv->dev->stats.tx_dropped++;
3133 return NETDEV_TX_OK;
3134}
3135
47dd7a54 3136/**
732fdf0e 3137 * stmmac_xmit - Tx entry point of the driver
47dd7a54
GC		 3138 * @skb : the socket buffer
3139 * @dev : device pointer
32ceabca
GC		 3140 * Description : this is the tx entry point of the driver.
3141 * It programs the chain or the ring and supports oversized frames
3142 * and SG feature.
47dd7a54
GC		 3143 */
3144static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3145{
c2837423 3146 unsigned int first_entry, tx_packets, enh_desc;
47dd7a54 3147 struct stmmac_priv *priv = netdev_priv(dev);
0e80bdc9 3148 unsigned int nopaged_len = skb_headlen(skb);
4a7d666a 3149 int i, csum_insertion = 0, is_jumbo = 0;
ce736788 3150 u32 queue = skb_get_queue_mapping(skb);
47dd7a54 3151 int nfrags = skb_shinfo(skb)->nr_frags;
b7766206 3152 int gso = skb_shinfo(skb)->gso_type;
47dd7a54 3153 struct dma_desc *desc, *first;
ce736788 3154 struct stmmac_tx_queue *tx_q;
c2837423
JA		 3155 bool has_vlan, set_ic;
3156 int entry, first_tx;
a993db88 3157 dma_addr_t des;
f748be53 3158
ce736788 3159 tx_q = &priv->tx_queue[queue];
c2837423 3160 first_tx = tx_q->cur_tx;
ce736788 3161
e2cd682d
JA		 3162 if (priv->tx_path_in_lpi_mode)
3163 stmmac_disable_eee_mode(priv);
3164
f748be53
AT		 3165 /* Manage oversized TCP frames for GMAC4 device */
3166 if (skb_is_gso(skb) && priv->tso) {
b7766206
JA		 3167 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
3168 return stmmac_tso_xmit(skb, dev);
3169 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
f748be53
AT		 3170 return stmmac_tso_xmit(skb, dev);
3171 }
47dd7a54 3172
ce736788 3173 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
c22a3f48
JP		 3174 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3175 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3176 queue));
47dd7a54 3177 /* This is a hard error, log it. */
38ddc59d
LC		 3178 netdev_err(priv->dev,
3179 "%s: Tx Ring full when queue awake\n",
3180 __func__);
47dd7a54
GC		 3181 }
3182 return NETDEV_TX_BUSY;
3183 }
3184
30d93227
JA		 3185 /* Check if VLAN can be inserted by HW */
3186 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
3187
ce736788 3188 entry = tx_q->cur_tx;
0e80bdc9 3189 first_entry = entry;
b4c9784c 3190 WARN_ON(tx_q->tx_skbuff[first_entry]);
47dd7a54 3191
5e982f3b 3192 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54 3193
0e80bdc9 3194 if (likely(priv->extend_desc))
ce736788 3195 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
c24602ef 3196 else
ce736788 3197 desc = tx_q->dma_tx + entry;
c24602ef 3198
47dd7a54
GC		 3199 first = desc;
3200
30d93227
JA		 3201 if (has_vlan)
3202 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
3203
0e80bdc9 3204 enh_desc = priv->plat->enh_desc;
4a7d666a 3205 /* To program the descriptors according to the size of the frame */
29896a67 3206 if (enh_desc)
2c520b1c 3207 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
29896a67 3208
63a550fc 3209 if (unlikely(is_jumbo)) {
2c520b1c 3210 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
63a550fc 3211 if (unlikely(entry < 0) && (entry != -EINVAL))
362b37be 3212 goto dma_map_err;
29896a67 3213 }
47dd7a54
GC		 3214
3215 for (i = 0; i < nfrags; i++) {
9e903e08
ED		 3216 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3217 int len = skb_frag_size(frag);
be434d50 3218 bool last_segment = (i == (nfrags - 1));
47dd7a54 3219
e3ad57c9 3220 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
b4c9784c 3221 WARN_ON(tx_q->tx_skbuff[entry]);
e3ad57c9 3222
0e80bdc9 3223 if (likely(priv->extend_desc))
ce736788 3224 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
c24602ef 3225 else
ce736788 3226 desc = tx_q->dma_tx + entry;
47dd7a54 3227
f748be53
AT		 3228 des = skb_frag_dma_map(priv->device, frag, 0, len,
3229 DMA_TO_DEVICE);
3230 if (dma_mapping_error(priv->device, des))
362b37be
GC		 3231 goto dma_map_err; /* should reuse desc w/o issues */
3232
ce736788 3233 tx_q->tx_skbuff_dma[entry].buf = des;
6844171d
JA		 3234
3235 stmmac_set_desc_addr(priv, desc, des);
f748be53 3236
ce736788
JP		 3237 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3238 tx_q->tx_skbuff_dma[entry].len = len;
3239 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
0e80bdc9
GC		 3240
3241 /* Prepare the descriptor and set the own bit too */
42de047d
JA		 3242 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3243 priv->mode, 1, last_segment, skb->len);
47dd7a54
GC		 3244 }
3245
05cf0d1b
NC		 3246 /* Only the last descriptor gets to point to the skb. */
3247 tx_q->tx_skbuff[entry] = skb;
e3ad57c9 3248
7df4a3a7
JA		 3249 /* According to the coalesce parameter the IC bit for the latest
3250 * segment is reset and the timer re-started to clean the tx status.
3251 * This approach takes care about the fragments: desc is the first
3252 * element in case of no SG.
3253 */
c2837423
JA		 3254 tx_packets = (entry + 1) - first_tx;
3255 tx_q->tx_count_frames += tx_packets;
3256
3257 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
3258 set_ic = true;
3259 else if (!priv->tx_coal_frames)
3260 set_ic = false;
3261 else if (tx_packets > priv->tx_coal_frames)
3262 set_ic = true;
3263 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets)
3264 set_ic = true;
3265 else
3266 set_ic = false;
3267
3268 if (set_ic) {
7df4a3a7
JA		 3269 if (likely(priv->extend_desc))
3270 desc = &tx_q->dma_etx[entry].basic;
3271 else
3272 desc = &tx_q->dma_tx[entry];
3273
3274 tx_q->tx_count_frames = 0;
3275 stmmac_set_tx_ic(priv, desc);
3276 priv->xstats.tx_set_ic_bit++;
c2837423
JA		 3277 } else {
3278 stmmac_tx_timer_arm(priv, queue);
7df4a3a7
JA		 3279 }
3280
05cf0d1b
NC		 3281 /* We've used all descriptors we need for this skb, however,
3282 * advance cur_tx so that it references a fresh descriptor.
3283 * ndo_start_xmit will fill this descriptor the next time it's
3284 * called and stmmac_tx_clean may clean up to this descriptor.
3285 */
3286 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
ce736788 3287 tx_q->cur_tx = entry;
47dd7a54 3288
47dd7a54 3289 if (netif_msg_pktdata(priv)) {
d0225e7d
AT		 3290 void *tx_head;
3291
38ddc59d
LC		 3292 netdev_dbg(priv->dev,
3293 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
ce736788 3294 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
38ddc59d 3295 entry, first, nfrags);
83d7af64 3296
c24602ef 3297 if (priv->extend_desc)
ce736788 3298 tx_head = (void *)tx_q->dma_etx;
c24602ef 3299 else
ce736788 3300 tx_head = (void *)tx_q->dma_tx;
d0225e7d 3301
42de047d 3302 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
c24602ef 3303
38ddc59d 3304 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
47dd7a54
GC		 3305 print_pkt(skb->data, skb->len);
3306 }
0e80bdc9 3307
ce736788 3308 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
b3e51069
LC		 3309 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3310 __func__);
c22a3f48 3311 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
47dd7a54
GC		 3312 }
3313
3314 dev->stats.tx_bytes += skb->len;
3315
8000ddc0
JA		 3316 if (priv->sarc_type)
3317 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3318
74abc9b1 3319 skb_tx_timestamp(skb);
3e82ce12 3320
0e80bdc9
GC		 3321 /* Ready to fill the first descriptor and set the OWN bit w/o any
3322 * problems because all the descriptors are actually ready to be
3323 * passed to the DMA engine.
3324 */
3325 if (likely(!is_jumbo)) {
3326 bool last_segment = (nfrags == 0);
3327
f748be53
AT		 3328 des = dma_map_single(priv->device, skb->data,
3329 nopaged_len, DMA_TO_DEVICE);
3330 if (dma_mapping_error(priv->device, des))
0e80bdc9
GC		 3331 goto dma_map_err;
3332
ce736788 3333 tx_q->tx_skbuff_dma[first_entry].buf = des;
6844171d
JA		 3334
3335 stmmac_set_desc_addr(priv, first, des);
f748be53 3336
ce736788
JP		 3337 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3338 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
0e80bdc9
GC		 3339
3340 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3341 priv->hwts_tx_en)) {
3342 /* declare that device is doing timestamping */
3343 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
42de047d 3344 stmmac_enable_tx_timestamp(priv, first);
0e80bdc9
GC		 3345 }
3346
3347 /* Prepare the first descriptor setting the OWN bit too */
42de047d
JA		 3348 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3349 csum_insertion, priv->mode, 1, last_segment,
3350 skb->len);
80acbed9
AK		 3351 } else {
3352 stmmac_set_tx_owner(priv, first);
0e80bdc9
GC		 3353 }
3354
80acbed9
AK		 3355 /* The own bit must be the latest setting done when prepare the
3356 * descriptor and then barrier is needed to make sure that
3357 * all is coherent before granting the DMA engine.
3358 */
3359 wmb();
3360
c22a3f48 3361 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
f748be53 3362
f1565c60 3363 stmmac_enable_dma_transmission(priv, priv->ioaddr);
8fce3331 3364
0431100b 3365 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
f1565c60 3366 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
52f64fae 3367
362b37be 3368 return NETDEV_TX_OK;
a9097a96 3369
362b37be 3370dma_map_err:
38ddc59d 3371 netdev_err(priv->dev, "Tx DMA map failed\n");
362b37be
GC		 3372 dev_kfree_skb(skb);
3373 priv->dev->stats.tx_dropped++;
47dd7a54
GC		 3374 return NETDEV_TX_OK;
3375}
3376
b9381985
VB		 3377static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3378{
ab188e8f
EN		 3379 struct vlan_ethhdr *veth;
3380 __be16 vlan_proto;
b9381985
VB		 3381 u16 vlanid;
3382
ab188e8f
EN		 3383 veth = (struct vlan_ethhdr *)skb->data;
3384 vlan_proto = veth->h_vlan_proto;
3385
3386 if ((vlan_proto == htons(ETH_P_8021Q) &&
3387 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3388 (vlan_proto == htons(ETH_P_8021AD) &&
3389 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
b9381985 3390 /* pop the vlan tag */
ab188e8f
EN		 3391 vlanid = ntohs(veth->h_vlan_TCI);
3392 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
b9381985 3393 skb_pull(skb, VLAN_HLEN);
ab188e8f 3394 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
b9381985
VB		 3395 }
3396}
3397
3398
54139cf3 3399static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
120e87f9 3400{
54139cf3 3401 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
120e87f9
GC		 3402 return 0;
3403
3404 return 1;
3405}
3406
32ceabca 3407/**
732fdf0e 3408 * stmmac_rx_refill - refill used skb preallocated buffers
32ceabca 3409 * @priv: driver private structure
54139cf3 3410 * @queue: RX queue index
32ceabca
GC		 3411 * Description : this is to reallocate the skb for the reception process
3412 * that is based on zero-copy.
3413 */
54139cf3 3414static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
47dd7a54 3415{
54139cf3 3416 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3caa61c2 3417 int len, dirty = stmmac_rx_dirty(priv, queue);
54139cf3
JP		 3418 unsigned int entry = rx_q->dirty_rx;
3419
3caa61c2
JA		 3420 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
3421
e3ad57c9 3422 while (dirty-- > 0) {
2af6106a 3423 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
c24602ef 3424 struct dma_desc *p;
d429b66e 3425 bool use_rx_wd;
c24602ef
GC		 3426
3427 if (priv->extend_desc)
54139cf3 3428 p = (struct dma_desc *)(rx_q->dma_erx + entry);
c24602ef 3429 else
54139cf3 3430 p = rx_q->dma_rx + entry;
c24602ef 3431
2af6106a
JA		 3432 if (!buf->page) {
3433 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
3434 if (!buf->page)
362b37be 3435 break;
47dd7a54 3436 }
2af6106a 3437
67afd6d1
JA		 3438 if (priv->sph && !buf->sec_page) {
3439 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
3440 if (!buf->sec_page)
3441 break;
3442
3443 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
3444
3445 dma_sync_single_for_device(priv->device, buf->sec_addr,
3446 len, DMA_FROM_DEVICE);
3447 }
3448
2af6106a 3449 buf->addr = page_pool_get_dma_addr(buf->page);
3caa61c2
JA		 3450
3451 /* Sync whole allocation to device. This will invalidate old
3452 * data.
3453 */
3454 dma_sync_single_for_device(priv->device, buf->addr, len,
3455 DMA_FROM_DEVICE);
3456
2af6106a 3457 stmmac_set_desc_addr(priv, p, buf->addr);
67afd6d1 3458 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
2af6106a 3459 stmmac_refill_desc3(priv, rx_q, p);
f748be53 3460
d429b66e 3461 rx_q->rx_count_frames++;
6fa9d691
JA		 3462 rx_q->rx_count_frames += priv->rx_coal_frames;
3463 if (rx_q->rx_count_frames > priv->rx_coal_frames)
3464 rx_q->rx_count_frames = 0;
09146abe
JA		 3465
3466 use_rx_wd = !priv->rx_coal_frames;
3467 use_rx_wd |= rx_q->rx_count_frames > 0;
3468 if (!priv->use_riwt)
3469 use_rx_wd = false;
d429b66e 3470
ad688cdb 3471 dma_wmb();
2af6106a 3472 stmmac_set_rx_owner(priv, p, use_rx_wd);
e3ad57c9
GC		 3473
3474 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
47dd7a54 3475 }
54139cf3 3476 rx_q->dirty_rx = entry;
858a31ff
JA		 3477 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
3478 (rx_q->dirty_rx * sizeof(struct dma_desc));
4523a561 3479 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
47dd7a54
GC		 3480}
3481
88ebe2cf
JA		 3482static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
3483 struct dma_desc *p,
3484 int status, unsigned int len)
3485{
3486 int ret, coe = priv->hw->rx_csum;
3487 unsigned int plen = 0, hlen = 0;
3488
3489 /* Not first descriptor, buffer is always zero */
3490 if (priv->sph && len)
3491 return 0;
3492
3493 /* First descriptor, get split header length */
3494 ret = stmmac_get_rx_header_len(priv, p, &hlen);
3495 if (priv->sph && hlen) {
3496 priv->xstats.rx_split_hdr_pkt_n++;
3497 return hlen;
3498 }
3499
3500 /* First descriptor, not last descriptor and not split header */
3501 if (status & rx_not_ls)
3502 return priv->dma_buf_sz;
3503
3504 plen = stmmac_get_rx_frame_len(priv, p, coe);
3505
3506 /* First descriptor and last descriptor and not split header */
3507 return min_t(unsigned int, priv->dma_buf_sz, plen);
3508}
3509
3510static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
3511 struct dma_desc *p,
3512 int status, unsigned int len)
3513{
3514 int coe = priv->hw->rx_csum;
3515 unsigned int plen = 0;
3516
3517 /* Not split header, buffer is not available */
3518 if (!priv->sph)
3519 return 0;
3520
3521 /* Not last descriptor */
3522 if (status & rx_not_ls)
3523 return priv->dma_buf_sz;
3524
3525 plen = stmmac_get_rx_frame_len(priv, p, coe);
3526
3527 /* Last descriptor */
3528 return plen - len;
3529}
3530
32ceabca 3531/**
732fdf0e 3532 * stmmac_rx - manage the receive process
32ceabca 3533 * @priv: driver private structure
54139cf3
JP		 3534 * @limit: napi bugget
3535 * @queue: RX queue index.
32ceabca
GC		 3536 * Description : this the function called by the napi poll method.
3537 * It gets all the frames inside the ring.
3538 */
54139cf3 3539static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
47dd7a54 3540{
54139cf3 3541 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
8fce3331 3542 struct stmmac_channel *ch = &priv->channel[queue];
ec222003
JA		 3543 unsigned int count = 0, error = 0, len = 0;
3544 int status = 0, coe = priv->hw->rx_csum;
07b39753 3545 unsigned int next_entry = rx_q->cur_rx;
ec222003 3546 struct sk_buff *skb = NULL;
47dd7a54 3547
83d7af64 3548 if (netif_msg_rx_status(priv)) {
d0225e7d
AT		 3549 void *rx_head;
3550
38ddc59d 3551 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
c24602ef 3552 if (priv->extend_desc)
54139cf3 3553 rx_head = (void *)rx_q->dma_erx;
c24602ef 3554 else
54139cf3 3555 rx_head = (void *)rx_q->dma_rx;
d0225e7d 3556
42de047d 3557 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
47dd7a54 3558 }
c24602ef 3559 while (count < limit) {
88ebe2cf 3560 unsigned int buf1_len = 0, buf2_len = 0;
ec222003 3561 enum pkt_hash_types hash_type;
2af6106a
JA		 3562 struct stmmac_rx_buffer *buf;
3563 struct dma_desc *np, *p;
ec222003
JA		 3564 int entry;
3565 u32 hash;
47dd7a54 3566
ec222003
JA		 3567 if (!count && rx_q->state_saved) {
3568 skb = rx_q->state.skb;
3569 error = rx_q->state.error;
3570 len = rx_q->state.len;
3571 } else {
3572 rx_q->state_saved = false;
3573 skb = NULL;
3574 error = 0;
3575 len = 0;
3576 }
3577
3578 if (count >= limit)
3579 break;
3580
3581read_again:
88ebe2cf
JA		 3582 buf1_len = 0;
3583 buf2_len = 0;
07b39753 3584 entry = next_entry;
2af6106a 3585 buf = &rx_q->buf_pool[entry];
07b39753 3586
c24602ef 3587 if (priv->extend_desc)
54139cf3 3588 p = (struct dma_desc *)(rx_q->dma_erx + entry);
c24602ef 3589 else
54139cf3 3590 p = rx_q->dma_rx + entry;
c24602ef 3591
c1fa3212 3592 /* read the status of the incoming frame */
42de047d
JA		 3593 status = stmmac_rx_status(priv, &priv->dev->stats,
3594 &priv->xstats, p);
c1fa3212
FG		 3595 /* check if managed by the DMA otherwise go ahead */
3596 if (unlikely(status & dma_own))
47dd7a54
GC		 3597 break;
3598
54139cf3
JP		 3599 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3600 next_entry = rx_q->cur_rx;
e3ad57c9 3601
c24602ef 3602 if (priv->extend_desc)
54139cf3 3603 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
c24602ef 3604 else
54139cf3 3605 np = rx_q->dma_rx + next_entry;
ba1ffd74
GC		 3606
3607 prefetch(np);
47dd7a54 3608
42de047d
JA		 3609 if (priv->extend_desc)
3610 stmmac_rx_extended_status(priv, &priv->dev->stats,
3611 &priv->xstats, rx_q->dma_erx + entry);
891434b1 3612 if (unlikely(status == discard_frame)) {
2af6106a 3613 page_pool_recycle_direct(rx_q->page_pool, buf->page);
2af6106a 3614 buf->page = NULL;
ec222003 3615 error = 1;
0b273ca4
JA		 3616 if (!priv->hwts_rx_en)
3617 priv->dev->stats.rx_errors++;
ec222003
JA		 3618 }
3619
3620 if (unlikely(error && (status & rx_not_ls)))
3621 goto read_again;
3622 if (unlikely(error)) {
399e06a5 3623 dev_kfree_skb(skb);
88ebe2cf 3624 skb = NULL;
cda4985a 3625 count++;
ec222003
JA		 3626 continue;
3627 }
3628
3629 /* Buffer is good. Go on. */
3630
88ebe2cf
JA		 3631 prefetch(page_address(buf->page));
3632 if (buf->sec_page)
3633 prefetch(page_address(buf->sec_page));
3634
3635 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
3636 len += buf1_len;
3637 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
3638 len += buf2_len;
3639
3640 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3641 * Type frames (LLC/LLC-SNAP)
3642 *
3643 * llc_snap is never checked in GMAC >= 4, so this ACS
3644 * feature is always disabled and packets need to be
3645 * stripped manually.
3646 */
3647 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3648 unlikely(status != llc_snap)) {
3649 if (buf2_len)
3650 buf2_len -= ETH_FCS_LEN;
3651 else
3652 buf1_len -= ETH_FCS_LEN;
3653
3654 len -= ETH_FCS_LEN;
ec222003 3655 }
22ad3838 3656
ec222003 3657 if (!skb) {
88ebe2cf 3658 skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
ec222003 3659 if (!skb) {
2af6106a 3660 priv->dev->stats.rx_dropped++;
cda4985a 3661 count++;
88ebe2cf 3662 goto drain_data;
47dd7a54 3663 }
47dd7a54 3664
88ebe2cf
JA		 3665 dma_sync_single_for_cpu(priv->device, buf->addr,
3666 buf1_len, DMA_FROM_DEVICE);
2af6106a 3667 skb_copy_to_linear_data(skb, page_address(buf->page),
88ebe2cf
JA		 3668 buf1_len);
3669 skb_put(skb, buf1_len);
2af6106a 3670
ec222003
JA		 3671 /* Data payload copied into SKB, page ready for recycle */
3672 page_pool_recycle_direct(rx_q->page_pool, buf->page);
3673 buf->page = NULL;
88ebe2cf 3674 } else if (buf1_len) {
ec222003 3675 dma_sync_single_for_cpu(priv->device, buf->addr,
88ebe2cf 3676 buf1_len, DMA_FROM_DEVICE);
ec222003 3677 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
88ebe2cf 3678 buf->page, 0, buf1_len,
ec222003 3679 priv->dma_buf_sz);
b9381985 3680
ec222003
JA		 3681 /* Data payload appended into SKB */
3682 page_pool_release_page(rx_q->page_pool, buf->page);
3683 buf->page = NULL;
3684 }
47dd7a54 3685
88ebe2cf 3686 if (buf2_len) {
67afd6d1 3687 dma_sync_single_for_cpu(priv->device, buf->sec_addr,
88ebe2cf 3688 buf2_len, DMA_FROM_DEVICE);
67afd6d1 3689 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
88ebe2cf 3690 buf->sec_page, 0, buf2_len,
67afd6d1
JA		 3691 priv->dma_buf_sz);
3692
67afd6d1
JA		 3693 /* Data payload appended into SKB */
3694 page_pool_release_page(rx_q->page_pool, buf->sec_page);
3695 buf->sec_page = NULL;
3696 }
3697
88ebe2cf 3698drain_data:
ec222003
JA		 3699 if (likely(status & rx_not_ls))
3700 goto read_again;
88ebe2cf
JA		 3701 if (!skb)
3702 continue;
62a2ab93 3703
ec222003 3704 /* Got entire packet into SKB. Finish it. */
76067459 3705
ec222003
JA		 3706 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3707 stmmac_rx_vlan(priv->dev, skb);
3708 skb->protocol = eth_type_trans(skb, priv->dev);
47dd7a54 3709
ec222003
JA		 3710 if (unlikely(!coe))
3711 skb_checksum_none_assert(skb);
3712 else
3713 skb->ip_summed = CHECKSUM_UNNECESSARY;
2af6106a 3714
ec222003
JA		 3715 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
3716 skb_set_hash(skb, hash, hash_type);
3717
3718 skb_record_rx_queue(skb, queue);
3719 napi_gro_receive(&ch->rx_napi, skb);
88ebe2cf 3720 skb = NULL;
ec222003
JA		 3721
3722 priv->dev->stats.rx_packets++;
3723 priv->dev->stats.rx_bytes += len;
cda4985a 3724 count++;
ec222003
JA		 3725 }
3726
88ebe2cf 3727 if (status & rx_not_ls || skb) {
ec222003
JA		 3728 rx_q->state_saved = true;
3729 rx_q->state.skb = skb;
3730 rx_q->state.error = error;
3731 rx_q->state.len = len;
47dd7a54
GC		 3732 }
3733
54139cf3 3734 stmmac_rx_refill(priv, queue);
47dd7a54
GC		 3735
3736 priv->xstats.rx_pkt_n += count;
3737
3738 return count;
3739}
3740
4ccb4585 3741static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
47dd7a54 3742{
8fce3331 3743 struct stmmac_channel *ch =
4ccb4585 3744 container_of(napi, struct stmmac_channel, rx_napi);
8fce3331 3745 struct stmmac_priv *priv = ch->priv_data;
8fce3331 3746 u32 chan = ch->index;
4ccb4585 3747 int work_done;
47dd7a54 3748
9125cdd1 3749 priv->xstats.napi_poll++;
ce736788 3750
4ccb4585
JA		 3751 work_done = stmmac_rx(priv, budget, chan);
3752 if (work_done < budget && napi_complete_done(napi, work_done))
3753 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3754 return work_done;
3755}
ce736788 3756
4ccb4585
JA		 3757static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3758{
3759 struct stmmac_channel *ch =
3760 container_of(napi, struct stmmac_channel, tx_napi);
3761 struct stmmac_priv *priv = ch->priv_data;
3762 struct stmmac_tx_queue *tx_q;
3763 u32 chan = ch->index;
3764 int work_done;
8fce3331 3765
4ccb4585
JA		 3766 priv->xstats.napi_poll++;
3767
3768 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3769 work_done = min(work_done, budget);
8fce3331 3770
a66b5884
JA		 3771 if (work_done < budget)
3772 napi_complete_done(napi, work_done);
4ccb4585
JA		 3773
3774 /* Force transmission restart */
3775 tx_q = &priv->tx_queue[chan];
3776 if (tx_q->cur_tx != tx_q->dirty_tx) {
3777 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3778 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3779 chan);
fa0be0a4 3780 }
8fce3331 3781
47dd7a54
GC		 3782 return work_done;
3783}
3784
3785/**
3786 * stmmac_tx_timeout
3787 * @dev : Pointer to net device structure
3788 * Description: this function is called when a packet transmission fails to
7284a3f1 3789 * complete within a reasonable time. The driver will mark the error in the
47dd7a54
GC		 3790 * netdev structure and arrange for the device to be reset to a sane state
3791 * in order to transmit a new packet.
3792 */
3793static void stmmac_tx_timeout(struct net_device *dev)
3794{
3795 struct stmmac_priv *priv = netdev_priv(dev);
3796
34877a15 3797 stmmac_global_err(priv);
47dd7a54
GC		 3798}
3799
47dd7a54 3800/**
01789349 3801 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 3802 * @dev : pointer to the device structure
3803 * Description:
3804 * This function is a driver entry point which gets called by the kernel
3805 * whenever multicast addresses must be enabled/disabled.
3806 * Return value:
3807 * void.
3808 */
01789349 3809static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 3810{
3811 struct stmmac_priv *priv = netdev_priv(dev);
3812
c10d4c82 3813 stmmac_set_filter(priv, priv->hw, dev);
47dd7a54
GC		 3814}
3815
3816/**
3817 * stmmac_change_mtu - entry point to change MTU size for the device.
3818 * @dev : device pointer.
3819 * @new_mtu : the new MTU size for the device.
3820 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3821 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3822 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3823 * Return value:
3824 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3825 * file on failure.
3826 */
3827static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3828{
38ddc59d
LC		 3829 struct stmmac_priv *priv = netdev_priv(dev);
3830
47dd7a54 3831 if (netif_running(dev)) {
38ddc59d 3832 netdev_err(priv->dev, "must be stopped to change its MTU\n");
47dd7a54
GC		 3833 return -EBUSY;
3834 }
3835
5e982f3b 3836 dev->mtu = new_mtu;
f748be53 3837
5e982f3b
MM		 3838 netdev_update_features(dev);
3839
3840 return 0;
3841}
3842
c8f44aff 3843static netdev_features_t stmmac_fix_features(struct net_device *dev,
ceb69499 3844 netdev_features_t features)
5e982f3b
MM		 3845{
3846 struct stmmac_priv *priv = netdev_priv(dev);
3847
38912bdb 3848 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5e982f3b 3849 features &= ~NETIF_F_RXCSUM;
d2afb5bd 3850
5e982f3b 3851 if (!priv->plat->tx_coe)
a188222b 3852 features &= ~NETIF_F_CSUM_MASK;
5e982f3b 3853
ebbb293f
GC		 3854 /* Some GMAC devices have a bugged Jumbo frame support that
3855 * needs to have the Tx COE disabled for oversized frames
3856 * (due to limited buffer sizes). In this case we disable
8d45e42b 3857 * the TX csum insertion in the TDES and not use SF.
ceb69499 3858 */
5e982f3b 3859 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
a188222b 3860 features &= ~NETIF_F_CSUM_MASK;
ebbb293f 3861
f748be53
AT		 3862 /* Disable tso if asked by ethtool */
3863 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3864 if (features & NETIF_F_TSO)
3865 priv->tso = true;
3866 else
3867 priv->tso = false;
3868 }
3869
5e982f3b 3870 return features;
47dd7a54
GC		 3871}
3872
d2afb5bd
GC		 3873static int stmmac_set_features(struct net_device *netdev,
3874 netdev_features_t features)
3875{
3876 struct stmmac_priv *priv = netdev_priv(netdev);
67afd6d1
JA		 3877 bool sph_en;
3878 u32 chan;
d2afb5bd
GC		 3879
3880 /* Keep the COE Type in case of csum is supporting */
3881 if (features & NETIF_F_RXCSUM)
3882 priv->hw->rx_csum = priv->plat->rx_coe;
3883 else
3884 priv->hw->rx_csum = 0;
3885 /* No check needed because rx_coe has been set before and it will be
3886 * fixed in case of issue.
3887 */
c10d4c82 3888 stmmac_rx_ipc(priv, priv->hw);
d2afb5bd 3889
67afd6d1
JA		 3890 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3891 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
3892 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3893
d2afb5bd
GC		 3894 return 0;
3895}
3896
32ceabca
GC		 3897/**
3898 * stmmac_interrupt - main ISR
3899 * @irq: interrupt number.
3900 * @dev_id: to pass the net device pointer.
3901 * Description: this is the main driver interrupt service routine.
732fdf0e
GC		 3902 * It can call:
3903 * o DMA service routine (to manage incoming frame reception and transmission
3904 * status)
3905 * o Core interrupts to manage: remote wake-up, management counter, LPI
3906 * interrupts.
32ceabca 3907 */
47dd7a54
GC		 3908static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3909{
3910 struct net_device *dev = (struct net_device *)dev_id;
3911 struct stmmac_priv *priv = netdev_priv(dev);
7bac4e1e
JP		 3912 u32 rx_cnt = priv->plat->rx_queues_to_use;
3913 u32 tx_cnt = priv->plat->tx_queues_to_use;
3914 u32 queues_count;
3915 u32 queue;
7d9e6c5a 3916 bool xmac;
7bac4e1e 3917
7d9e6c5a 3918 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
7bac4e1e 3919 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
47dd7a54 3920
89f7f2cf
SK		 3921 if (priv->irq_wake)
3922 pm_wakeup_event(priv->device, 0);
3923
47dd7a54 3924 if (unlikely(!dev)) {
38ddc59d 3925 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
47dd7a54
GC		 3926 return IRQ_NONE;
3927 }
3928
34877a15
JA		 3929 /* Check if adapter is up */
3930 if (test_bit(STMMAC_DOWN, &priv->state))
3931 return IRQ_HANDLED;
8bf993a5
JA		 3932 /* Check if a fatal error happened */
3933 if (stmmac_safety_feat_interrupt(priv))
3934 return IRQ_HANDLED;
34877a15 3935
d765955d 3936 /* To handle GMAC own interrupts */
7d9e6c5a 3937 if ((priv->plat->has_gmac) || xmac) {
c10d4c82 3938 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
61fac60a 3939 int mtl_status;
8f71a88d 3940
d765955d 3941 if (unlikely(status)) {
d765955d 3942 /* For LPI we need to save the tx status */
0982a0f6 3943 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
d765955d 3944 priv->tx_path_in_lpi_mode = true;
0982a0f6 3945 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
d765955d 3946 priv->tx_path_in_lpi_mode = false;
7bac4e1e
JP		 3947 }
3948
61fac60a
JA		 3949 for (queue = 0; queue < queues_count; queue++) {
3950 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
54139cf3 3951
61fac60a
JA		 3952 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3953 queue);
3954 if (mtl_status != -EINVAL)
3955 status |= mtl_status;
7bac4e1e 3956
61fac60a
JA		 3957 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3958 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3959 rx_q->rx_tail_addr,
3960 queue);
d765955d 3961 }
70523e63
GC		 3962
3963 /* PCS link status */
3fe5cadb 3964 if (priv->hw->pcs) {
70523e63
GC		 3965 if (priv->xstats.pcs_link)
3966 netif_carrier_on(dev);
3967 else
3968 netif_carrier_off(dev);
3969 }
d765955d 3970 }
aec7ff27 3971
d765955d 3972 /* To handle DMA interrupts */
aec7ff27 3973 stmmac_dma_interrupt(priv);
47dd7a54
GC		 3974
3975 return IRQ_HANDLED;
3976}
3977
3978#ifdef CONFIG_NET_POLL_CONTROLLER
3979/* Polling receive - used by NETCONSOLE and other diagnostic tools
ceb69499
GC		 3980 * to allow network I/O with interrupts disabled.
3981 */
47dd7a54
GC		 3982static void stmmac_poll_controller(struct net_device *dev)
3983{
3984 disable_irq(dev->irq);
3985 stmmac_interrupt(dev->irq, dev);
3986 enable_irq(dev->irq);
3987}
3988#endif
3989
3990/**
3991 * stmmac_ioctl - Entry point for the Ioctl
3992 * @dev: Device pointer.
3993 * @rq: An IOCTL specefic structure, that can contain a pointer to
3994 * a proprietary structure used to pass information to the driver.
3995 * @cmd: IOCTL command
3996 * Description:
32ceabca 3997 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
47dd7a54
GC		 3998 */
3999static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4000{
74371272 4001 struct stmmac_priv *priv = netdev_priv (dev);
891434b1 4002 int ret = -EOPNOTSUPP;
47dd7a54
GC		 4003
4004 if (!netif_running(dev))
4005 return -EINVAL;
4006
891434b1
RK		 4007 switch (cmd) {
4008 case SIOCGMIIPHY:
4009 case SIOCGMIIREG:
4010 case SIOCSMIIREG:
74371272 4011 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
891434b1
RK		 4012 break;
4013 case SIOCSHWTSTAMP:
d6228b7c
AP		 4014 ret = stmmac_hwtstamp_set(dev, rq);
4015 break;
4016 case SIOCGHWTSTAMP:
4017 ret = stmmac_hwtstamp_get(dev, rq);
891434b1
RK		 4018 break;
4019 default:
4020 break;
4021 }
28b04113 4022
47dd7a54
GC		 4023 return ret;
4024}
4025
4dbbe8dd
JA		 4026static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
4027 void *cb_priv)
4028{
4029 struct stmmac_priv *priv = cb_priv;
4030 int ret = -EOPNOTSUPP;
4031
425eabdd
JA		 4032 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
4033 return ret;
4034
4dbbe8dd
JA		 4035 stmmac_disable_all_queues(priv);
4036
4037 switch (type) {
4038 case TC_SETUP_CLSU32:
425eabdd
JA		 4039 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
4040 break;
4041 case TC_SETUP_CLSFLOWER:
4042 ret = stmmac_tc_setup_cls(priv, priv, type_data);
4dbbe8dd
JA		 4043 break;
4044 default:
4045 break;
4046 }
4047
4048 stmmac_enable_all_queues(priv);
4049 return ret;
4050}
4051
955bcb6e
PNA		 4052static LIST_HEAD(stmmac_block_cb_list);
4053
4dbbe8dd
JA		 4054static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
4055 void *type_data)
4056{
4057 struct stmmac_priv *priv = netdev_priv(ndev);
4058
4059 switch (type) {
4060 case TC_SETUP_BLOCK:
955bcb6e
PNA		 4061 return flow_block_cb_setup_simple(type_data,
4062 &stmmac_block_cb_list,
4e95bc26
PNA		 4063 stmmac_setup_tc_block_cb,
4064 priv, priv, true);
1f705bc6
JA		 4065 case TC_SETUP_QDISC_CBS:
4066 return stmmac_tc_setup_cbs(priv, priv, type_data);
4dbbe8dd
JA		 4067 default:
4068 return -EOPNOTSUPP;
4069 }
4070}
4071
4993e5b3
JA		 4072static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
4073 struct net_device *sb_dev)
4074{
b7766206
JA		 4075 int gso = skb_shinfo(skb)->gso_type;
4076
4077 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
4993e5b3 4078 /*
b7766206 4079 * There is no way to determine the number of TSO/USO
4993e5b3 4080 * capable Queues. Let's use always the Queue 0
b7766206 4081 * because if TSO/USO is supported then at least this
4993e5b3
JA		 4082 * one will be capable.
4083 */
4084 return 0;
4085 }
4086
4087 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
4088}
4089
a830405e
BV		 4090static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
4091{
4092 struct stmmac_priv *priv = netdev_priv(ndev);
4093 int ret = 0;
4094
4095 ret = eth_mac_addr(ndev, addr);
4096 if (ret)
4097 return ret;
4098
c10d4c82 4099 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
a830405e
BV		 4100
4101 return ret;
4102}
4103
50fb4f74 4104#ifdef CONFIG_DEBUG_FS
7ac29055 4105static struct dentry *stmmac_fs_dir;
7ac29055 4106
c24602ef 4107static void sysfs_display_ring(void *head, int size, int extend_desc,
ceb69499 4108 struct seq_file *seq)
7ac29055 4109{
7ac29055 4110 int i;
ceb69499
GC		 4111 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
4112 struct dma_desc *p = (struct dma_desc *)head;
7ac29055 4113
c24602ef 4114 for (i = 0; i < size; i++) {
c24602ef 4115 if (extend_desc) {
c24602ef 4116 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
ceb69499 4117 i, (unsigned int)virt_to_phys(ep),
f8be0d78
MW		 4118 le32_to_cpu(ep->basic.des0),
4119 le32_to_cpu(ep->basic.des1),
4120 le32_to_cpu(ep->basic.des2),
4121 le32_to_cpu(ep->basic.des3));
c24602ef
GC		 4122 ep++;
4123 } else {
c24602ef 4124 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
66c25f6e 4125 i, (unsigned int)virt_to_phys(p),
f8be0d78
MW		 4126 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
4127 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
c24602ef
GC		 4128 p++;
4129 }
7ac29055
GC		 4130 seq_printf(seq, "\n");
4131 }
c24602ef 4132}
7ac29055 4133
fb0d9c63 4134static int stmmac_rings_status_show(struct seq_file *seq, void *v)
c24602ef
GC		 4135{
4136 struct net_device *dev = seq->private;
4137 struct stmmac_priv *priv = netdev_priv(dev);
54139cf3 4138 u32 rx_count = priv->plat->rx_queues_to_use;
ce736788 4139 u32 tx_count = priv->plat->tx_queues_to_use;
54139cf3
JP		 4140 u32 queue;
4141
5f2b8b62
TR		 4142 if ((dev->flags & IFF_UP) == 0)
4143 return 0;
4144
54139cf3
JP		 4145 for (queue = 0; queue < rx_count; queue++) {
4146 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4147
4148 seq_printf(seq, "RX Queue %d:\n", queue);
4149
4150 if (priv->extend_desc) {
4151 seq_printf(seq, "Extended descriptor ring:\n");
4152 sysfs_display_ring((void *)rx_q->dma_erx,
4153 DMA_RX_SIZE, 1, seq);
4154 } else {
4155 seq_printf(seq, "Descriptor ring:\n");
4156 sysfs_display_ring((void *)rx_q->dma_rx,
4157 DMA_RX_SIZE, 0, seq);
4158 }
4159 }
aff3d9ef 4160
ce736788
JP		 4161 for (queue = 0; queue < tx_count; queue++) {
4162 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4163
4164 seq_printf(seq, "TX Queue %d:\n", queue);
4165
4166 if (priv->extend_desc) {
4167 seq_printf(seq, "Extended descriptor ring:\n");
4168 sysfs_display_ring((void *)tx_q->dma_etx,
4169 DMA_TX_SIZE, 1, seq);
4170 } else {
4171 seq_printf(seq, "Descriptor ring:\n");
4172 sysfs_display_ring((void *)tx_q->dma_tx,
4173 DMA_TX_SIZE, 0, seq);
4174 }
7ac29055
GC		 4175 }
4176
4177 return 0;
4178}
fb0d9c63 4179DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
7ac29055 4180
fb0d9c63 4181static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
e7434821
GC		 4182{
4183 struct net_device *dev = seq->private;
4184 struct stmmac_priv *priv = netdev_priv(dev);
4185
19e30c14 4186 if (!priv->hw_cap_support) {
e7434821
GC		 4187 seq_printf(seq, "DMA HW features not supported\n");
4188 return 0;
4189 }
4190
4191 seq_printf(seq, "==============================\n");
4192 seq_printf(seq, "\tDMA HW features\n");
4193 seq_printf(seq, "==============================\n");
4194
22d3efe5 4195 seq_printf(seq, "\t10/100 Mbps: %s\n",
e7434821 4196 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
22d3efe5 4197 seq_printf(seq, "\t1000 Mbps: %s\n",
e7434821 4198 (priv->dma_cap.mbps_1000) ? "Y" : "N");
22d3efe5 4199 seq_printf(seq, "\tHalf duplex: %s\n",
e7434821
GC		 4200 (priv->dma_cap.half_duplex) ? "Y" : "N");
4201 seq_printf(seq, "\tHash Filter: %s\n",
4202 (priv->dma_cap.hash_filter) ? "Y" : "N");
4203 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
4204 (priv->dma_cap.multi_addr) ? "Y" : "N");
8d45e42b 4205 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
e7434821
GC		 4206 (priv->dma_cap.pcs) ? "Y" : "N");
4207 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
4208 (priv->dma_cap.sma_mdio) ? "Y" : "N");
4209 seq_printf(seq, "\tPMT Remote wake up: %s\n",
4210 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
4211 seq_printf(seq, "\tPMT Magic Frame: %s\n",
4212 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
4213 seq_printf(seq, "\tRMON module: %s\n",
4214 (priv->dma_cap.rmon) ? "Y" : "N");
4215 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
4216 (priv->dma_cap.time_stamp) ? "Y" : "N");
22d3efe5 4217 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
e7434821 4218 (priv->dma_cap.atime_stamp) ? "Y" : "N");
22d3efe5 4219 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
e7434821
GC		 4220 (priv->dma_cap.eee) ? "Y" : "N");
4221 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4222 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4223 (priv->dma_cap.tx_coe) ? "Y" : "N");
f748be53
AT		 4224 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4225 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4226 (priv->dma_cap.rx_coe) ? "Y" : "N");
4227 } else {
4228 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4229 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4230 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4231 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4232 }
e7434821
GC		 4233 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4234 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4235 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4236 priv->dma_cap.number_rx_channel);
4237 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4238 priv->dma_cap.number_tx_channel);
4239 seq_printf(seq, "\tEnhanced descriptors: %s\n",
4240 (priv->dma_cap.enh_desc) ? "Y" : "N");
4241
4242 return 0;
4243}
fb0d9c63 4244DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
e7434821 4245
8d72ab11 4246static void stmmac_init_fs(struct net_device *dev)
7ac29055 4247{
466c5ac8
MO		 4248 struct stmmac_priv *priv = netdev_priv(dev);
4249
4250 /* Create per netdev entries */
4251 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
7ac29055 4252
7ac29055 4253 /* Entry to report DMA RX/TX rings */
8d72ab11
GKH		 4254 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
4255 &stmmac_rings_status_fops);
7ac29055 4256
e7434821 4257 /* Entry to report the DMA HW features */
8d72ab11
GKH		 4258 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
4259 &stmmac_dma_cap_fops);
7ac29055
GC		 4260}
4261
466c5ac8 4262static void stmmac_exit_fs(struct net_device *dev)
7ac29055 4263{
466c5ac8
MO		 4264 struct stmmac_priv *priv = netdev_priv(dev);
4265
4266 debugfs_remove_recursive(priv->dbgfs_dir);
7ac29055 4267}
50fb4f74 4268#endif /* CONFIG_DEBUG_FS */
7ac29055 4269
3cd1cfcb
JA		 4270static u32 stmmac_vid_crc32_le(__le16 vid_le)
4271{
4272 unsigned char *data = (unsigned char *)&vid_le;
4273 unsigned char data_byte = 0;
4274 u32 crc = ~0x0;
4275 u32 temp = 0;
4276 int i, bits;
4277
4278 bits = get_bitmask_order(VLAN_VID_MASK);
4279 for (i = 0; i < bits; i++) {
4280 if ((i % 8) == 0)
4281 data_byte = data[i / 8];
4282
4283 temp = ((crc & 1) ^ data_byte) & 1;
4284 crc >>= 1;
4285 data_byte >>= 1;
4286
4287 if (temp)
4288 crc ^= 0xedb88320;
4289 }
4290
4291 return crc;
4292}
4293
4294static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
4295{
4296 u32 crc, hash = 0;
a24cae70 4297 __le16 pmatch = 0;
c7ab0b80
JA		 4298 int count = 0;
4299 u16 vid = 0;
3cd1cfcb
JA		 4300
4301 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
4302 __le16 vid_le = cpu_to_le16(vid);
4303 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
4304 hash |= (1 << crc);
c7ab0b80
JA		 4305 count++;
4306 }
4307
4308 if (!priv->dma_cap.vlhash) {
4309 if (count > 2) /* VID = 0 always passes filter */
4310 return -EOPNOTSUPP;
4311
a24cae70 4312 pmatch = cpu_to_le16(vid);
c7ab0b80 4313 hash = 0;
3cd1cfcb
JA		 4314 }
4315
a24cae70 4316 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
3cd1cfcb
JA		 4317}
4318
4319static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
4320{
4321 struct stmmac_priv *priv = netdev_priv(ndev);
4322 bool is_double = false;
4323 int ret;
4324
3cd1cfcb
JA		 4325 if (be16_to_cpu(proto) == ETH_P_8021AD)
4326 is_double = true;
4327
4328 set_bit(vid, priv->active_vlans);
4329 ret = stmmac_vlan_update(priv, is_double);
4330 if (ret) {
4331 clear_bit(vid, priv->active_vlans);
4332 return ret;
4333 }
4334
4335 return ret;
4336}
4337
4338static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
4339{
4340 struct stmmac_priv *priv = netdev_priv(ndev);
4341 bool is_double = false;
4342
3cd1cfcb
JA		 4343 if (be16_to_cpu(proto) == ETH_P_8021AD)
4344 is_double = true;
4345
4346 clear_bit(vid, priv->active_vlans);
4347 return stmmac_vlan_update(priv, is_double);
4348}
4349
47dd7a54
GC		 4350static const struct net_device_ops stmmac_netdev_ops = {
4351 .ndo_open = stmmac_open,
4352 .ndo_start_xmit = stmmac_xmit,
4353 .ndo_stop = stmmac_release,
4354 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 4355 .ndo_fix_features = stmmac_fix_features,
d2afb5bd 4356 .ndo_set_features = stmmac_set_features,
01789349 4357 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 4358 .ndo_tx_timeout = stmmac_tx_timeout,
4359 .ndo_do_ioctl = stmmac_ioctl,
4dbbe8dd 4360 .ndo_setup_tc = stmmac_setup_tc,
4993e5b3 4361 .ndo_select_queue = stmmac_select_queue,
47dd7a54
GC		 4362#ifdef CONFIG_NET_POLL_CONTROLLER
4363 .ndo_poll_controller = stmmac_poll_controller,
4364#endif
a830405e 4365 .ndo_set_mac_address = stmmac_set_mac_address,
3cd1cfcb
JA		 4366 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
4367 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
47dd7a54
GC		 4368};
4369
34877a15
JA		 4370static void stmmac_reset_subtask(struct stmmac_priv *priv)
4371{
4372 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4373 return;
4374 if (test_bit(STMMAC_DOWN, &priv->state))
4375 return;
4376
4377 netdev_err(priv->dev, "Reset adapter.\n");
4378
4379 rtnl_lock();
4380 netif_trans_update(priv->dev);
4381 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4382 usleep_range(1000, 2000);
4383
4384 set_bit(STMMAC_DOWN, &priv->state);
4385 dev_close(priv->dev);
00f54e68 4386 dev_open(priv->dev, NULL);
34877a15
JA		 4387 clear_bit(STMMAC_DOWN, &priv->state);
4388 clear_bit(STMMAC_RESETING, &priv->state);
4389 rtnl_unlock();
4390}
4391
4392static void stmmac_service_task(struct work_struct *work)
4393{
4394 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4395 service_task);
4396
4397 stmmac_reset_subtask(priv);
4398 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4399}
4400
cf3f047b
GC		 4401/**
4402 * stmmac_hw_init - Init the MAC device
32ceabca 4403 * @priv: driver private structure
732fdf0e
GC		 4404 * Description: this function is to configure the MAC device according to
4405 * some platform parameters or the HW capability register. It prepares the
4406 * driver to use either ring or chain modes and to setup either enhanced or
4407 * normal descriptors.
cf3f047b
GC		 4408 */
4409static int stmmac_hw_init(struct stmmac_priv *priv)
4410{
5f0456b4 4411 int ret;
cf3f047b 4412
9f93ac8d
LC		 4413 /* dwmac-sun8i only work in chain mode */
4414 if (priv->plat->has_sun8i)
4415 chain_mode = 1;
5f0456b4 4416 priv->chain_mode = chain_mode;
9f93ac8d 4417
5f0456b4
JA		 4418 /* Initialize HW Interface */
4419 ret = stmmac_hwif_init(priv);
4420 if (ret)
4421 return ret;
4a7d666a 4422
cf3f047b
GC		 4423 /* Get the HW capability (new GMAC newer than 3.50a) */
4424 priv->hw_cap_support = stmmac_get_hw_features(priv);
4425 if (priv->hw_cap_support) {
38ddc59d 4426 dev_info(priv->device, "DMA HW capability register supported\n");
cf3f047b
GC		 4427
4428 /* We can override some gmac/dma configuration fields: e.g.
4429 * enh_desc, tx_coe (e.g. that are passed through the
4430 * platform) with the values from the HW capability
4431 * register (if supported).
4432 */
4433 priv->plat->enh_desc = priv->dma_cap.enh_desc;
cf3f047b 4434 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3fe5cadb 4435 priv->hw->pmt = priv->plat->pmt;
b8ef7020
BH		 4436 if (priv->dma_cap.hash_tb_sz) {
4437 priv->hw->multicast_filter_bins =
4438 (BIT(priv->dma_cap.hash_tb_sz) << 5);
4439 priv->hw->mcast_bits_log2 =
4440 ilog2(priv->hw->multicast_filter_bins);
4441 }
38912bdb 4442
a8df35d4
EG		 4443 /* TXCOE doesn't work in thresh DMA mode */
4444 if (priv->plat->force_thresh_dma_mode)
4445 priv->plat->tx_coe = 0;
4446 else
4447 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4448
f748be53
AT		 4449 /* In case of GMAC4 rx_coe is from HW cap register. */
4450 priv->plat->rx_coe = priv->dma_cap.rx_coe;
38912bdb
DS		 4451
4452 if (priv->dma_cap.rx_coe_type2)
4453 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4454 else if (priv->dma_cap.rx_coe_type1)
4455 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4456
38ddc59d
LC		 4457 } else {
4458 dev_info(priv->device, "No HW DMA feature register supported\n");
4459 }
cf3f047b 4460
d2afb5bd
GC		 4461 if (priv->plat->rx_coe) {
4462 priv->hw->rx_csum = priv->plat->rx_coe;
38ddc59d 4463 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
f748be53 4464 if (priv->synopsys_id < DWMAC_CORE_4_00)
38ddc59d 4465 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
d2afb5bd 4466 }
cf3f047b 4467 if (priv->plat->tx_coe)
38ddc59d 4468 dev_info(priv->device, "TX Checksum insertion supported\n");
cf3f047b
GC		 4469
4470 if (priv->plat->pmt) {
38ddc59d 4471 dev_info(priv->device, "Wake-Up On Lan supported\n");
cf3f047b
GC		 4472 device_set_wakeup_capable(priv->device, 1);
4473 }
4474
f748be53 4475 if (priv->dma_cap.tsoen)
38ddc59d 4476 dev_info(priv->device, "TSO supported\n");
f748be53 4477
7cfde0af
JA		 4478 /* Run HW quirks, if any */
4479 if (priv->hwif_quirks) {
4480 ret = priv->hwif_quirks(priv);
4481 if (ret)
4482 return ret;
4483 }
4484
3b509466
JA		 4485 /* Rx Watchdog is available in the COREs newer than the 3.40.
4486 * In some case, for example on bugged HW this feature
4487 * has to be disable and this can be done by passing the
4488 * riwt_off field from the platform.
4489 */
4490 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4491 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4492 priv->use_riwt = 1;
4493 dev_info(priv->device,
4494 "Enable RX Mitigation via HW Watchdog Timer\n");
4495 }
4496
c24602ef 4497 return 0;
cf3f047b
GC		 4498}
4499
47dd7a54 4500/**
bfab27a1
GC		 4501 * stmmac_dvr_probe
4502 * @device: device pointer
ff3dd78c 4503 * @plat_dat: platform data pointer
e56788cf 4504 * @res: stmmac resource pointer
bfab27a1
GC		 4505 * Description: this is the main probe function used to
4506 * call the alloc_etherdev, allocate the priv structure.
9afec6ef 4507 * Return:
15ffac73 4508 * returns 0 on success, otherwise errno.
47dd7a54 4509 */
15ffac73
JE		 4510int stmmac_dvr_probe(struct device *device,
4511 struct plat_stmmacenet_data *plat_dat,
4512 struct stmmac_resources *res)
47dd7a54 4513{
bfab27a1
GC		 4514 struct net_device *ndev = NULL;
4515 struct stmmac_priv *priv;
76067459
JA		 4516 u32 queue, rxq, maxq;
4517 int i, ret = 0;
47dd7a54 4518
9737070c
JZ		 4519 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4520 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
41de8d4c 4521 if (!ndev)
15ffac73 4522 return -ENOMEM;
bfab27a1
GC		 4523
4524 SET_NETDEV_DEV(ndev, device);
4525
4526 priv = netdev_priv(ndev);
4527 priv->device = device;
4528 priv->dev = ndev;
47dd7a54 4529
bfab27a1 4530 stmmac_set_ethtool_ops(ndev);
cf3f047b
GC		 4531 priv->pause = pause;
4532 priv->plat = plat_dat;
e56788cf
JE		 4533 priv->ioaddr = res->addr;
4534 priv->dev->base_addr = (unsigned long)res->addr;
4535
4536 priv->dev->irq = res->irq;
4537 priv->wol_irq = res->wol_irq;
4538 priv->lpi_irq = res->lpi_irq;
4539
a51645f7 4540 if (!IS_ERR_OR_NULL(res->mac))
e56788cf 4541 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
cf3f047b 4542
a7a62685 4543 dev_set_drvdata(device, priv->dev);
803f8fc4 4544
cf3f047b
GC		 4545 /* Verify driver arguments */
4546 stmmac_verify_args();
bfab27a1 4547
34877a15
JA		 4548 /* Allocate workqueue */
4549 priv->wq = create_singlethread_workqueue("stmmac_wq");
4550 if (!priv->wq) {
4551 dev_err(priv->device, "failed to create workqueue\n");
9737070c 4552 return -ENOMEM;
34877a15
JA		 4553 }
4554
4555 INIT_WORK(&priv->service_task, stmmac_service_task);
4556
cf3f047b 4557 /* Override with kernel parameters if supplied XXX CRS XXX
ceb69499
GC		 4558 * this needs to have multiple instances
4559 */
cf3f047b
GC		 4560 if ((phyaddr >= 0) && (phyaddr <= 31))
4561 priv->plat->phy_addr = phyaddr;
4562
90f522a2
EP		 4563 if (priv->plat->stmmac_rst) {
4564 ret = reset_control_assert(priv->plat->stmmac_rst);
f573c0b9 4565 reset_control_deassert(priv->plat->stmmac_rst);
90f522a2
EP		 4566 /* Some reset controllers have only reset callback instead of
4567 * assert + deassert callbacks pair.
4568 */
4569 if (ret == -ENOTSUPP)
4570 reset_control_reset(priv->plat->stmmac_rst);
4571 }
c5e4ddbd 4572
cf3f047b 4573 /* Init MAC and get the capabilities */
c24602ef
GC		 4574 ret = stmmac_hw_init(priv);
4575 if (ret)
62866e98 4576 goto error_hw_init;
cf3f047b 4577
b561af36
VK		 4578 stmmac_check_ether_addr(priv);
4579
c22a3f48 4580 /* Configure real RX and TX queues */
c02b7a91
JP		 4581 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4582 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
c22a3f48 4583
cf3f047b 4584 ndev->netdev_ops = &stmmac_netdev_ops;
bfab27a1 4585
cf3f047b
GC		 4586 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4587 NETIF_F_RXCSUM;
f748be53 4588
4dbbe8dd
JA		 4589 ret = stmmac_tc_init(priv, priv);
4590 if (!ret) {
4591 ndev->hw_features |= NETIF_F_HW_TC;
4592 }
4593
f748be53 4594 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
9edfa7da 4595 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
b7766206
JA		 4596 if (priv->plat->has_gmac4)
4597 ndev->hw_features |= NETIF_F_GSO_UDP_L4;
f748be53 4598 priv->tso = true;
38ddc59d 4599 dev_info(priv->device, "TSO feature enabled\n");
f748be53 4600 }
a993db88 4601
67afd6d1
JA		 4602 if (priv->dma_cap.sphen) {
4603 ndev->hw_features |= NETIF_F_GRO;
4604 priv->sph = true;
4605 dev_info(priv->device, "SPH feature enabled\n");
4606 }
4607
a993db88
JA		 4608 if (priv->dma_cap.addr64) {
4609 ret = dma_set_mask_and_coherent(device,
4610 DMA_BIT_MASK(priv->dma_cap.addr64));
4611 if (!ret) {
4612 dev_info(priv->device, "Using %d bits DMA width\n",
4613 priv->dma_cap.addr64);
968a2978
TR		 4614
4615 /*
4616 * If more than 32 bits can be addressed, make sure to
4617 * enable enhanced addressing mode.
4618 */
4619 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
4620 priv->plat->dma_cfg->eame = true;
a993db88
JA		 4621 } else {
4622 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
4623 if (ret) {
4624 dev_err(priv->device, "Failed to set DMA Mask\n");
4625 goto error_hw_init;
4626 }
4627
4628 priv->dma_cap.addr64 = 32;
4629 }
4630 }
4631
bfab27a1
GC		 4632 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4633 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
47dd7a54
GC		 4634#ifdef STMMAC_VLAN_TAG_USED
4635 /* Both mac100 and gmac support receive VLAN tag detection */
ab188e8f 4636 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
3cd1cfcb
JA		 4637 if (priv->dma_cap.vlhash) {
4638 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4639 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4640 }
30d93227
JA		 4641 if (priv->dma_cap.vlins) {
4642 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
4643 if (priv->dma_cap.dvlan)
4644 ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
4645 }
47dd7a54
GC		 4646#endif
4647 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4648
76067459
JA		 4649 /* Initialize RSS */
4650 rxq = priv->plat->rx_queues_to_use;
4651 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
4652 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
4653 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
4654
4655 if (priv->dma_cap.rssen && priv->plat->rss_en)
4656 ndev->features |= NETIF_F_RXHASH;
4657
44770e11
JW		 4658 /* MTU range: 46 - hw-specific max */
4659 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
56bcd591 4660 if (priv->plat->has_xgmac)
7d9e6c5a 4661 ndev->max_mtu = XGMAC_JUMBO_LEN;
56bcd591
JA		 4662 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4663 ndev->max_mtu = JUMBO_LEN;
44770e11
JW		 4664 else
4665 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
a2cd64f3
KHL		 4666 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4667 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4668 */
4669 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4670 (priv->plat->maxmtu >= ndev->min_mtu))
44770e11 4671 ndev->max_mtu = priv->plat->maxmtu;
a2cd64f3 4672 else if (priv->plat->maxmtu < ndev->min_mtu)
b618ab45
HK		 4673 dev_warn(priv->device,
4674 "%s: warning: maxmtu having invalid value (%d)\n",
4675 __func__, priv->plat->maxmtu);
44770e11 4676
47dd7a54
GC		 4677 if (flow_ctrl)
4678 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4679
8fce3331
JA		 4680 /* Setup channels NAPI */
4681 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
c22a3f48 4682
8fce3331
JA		 4683 for (queue = 0; queue < maxq; queue++) {
4684 struct stmmac_channel *ch = &priv->channel[queue];
4685
4686 ch->priv_data = priv;
4687 ch->index = queue;
4688
4ccb4585
JA		 4689 if (queue < priv->plat->rx_queues_to_use) {
4690 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4691 NAPI_POLL_WEIGHT);
4692 }
4693 if (queue < priv->plat->tx_queues_to_use) {
4d97972b
FI		 4694 netif_tx_napi_add(ndev, &ch->tx_napi,
4695 stmmac_napi_poll_tx,
4696 NAPI_POLL_WEIGHT);
4ccb4585 4697 }
c22a3f48 4698 }
47dd7a54 4699
29555fa3 4700 mutex_init(&priv->lock);
f8e96161 4701
cd7201f4
GC		 4702 /* If a specific clk_csr value is passed from the platform
4703 * this means that the CSR Clock Range selection cannot be
4704 * changed at run-time and it is fixed. Viceversa the driver'll try to
4705 * set the MDC clock dynamically according to the csr actual
4706 * clock input.
4707 */
5e7f7fc5 4708 if (priv->plat->clk_csr >= 0)
cd7201f4 4709 priv->clk_csr = priv->plat->clk_csr;
5e7f7fc5
BH		 4710 else
4711 stmmac_clk_csr_set(priv);
cd7201f4 4712
e58bb43f
GC		 4713 stmmac_check_pcs_mode(priv);
4714
3fe5cadb
GC		 4715 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4716 priv->hw->pcs != STMMAC_PCS_TBI &&
4717 priv->hw->pcs != STMMAC_PCS_RTBI) {
e58bb43f
GC		 4718 /* MDIO bus Registration */
4719 ret = stmmac_mdio_register(ndev);
4720 if (ret < 0) {
b618ab45
HK		 4721 dev_err(priv->device,
4722 "%s: MDIO bus (id: %d) registration failed",
4723 __func__, priv->plat->bus_id);
e58bb43f
GC		 4724 goto error_mdio_register;
4725 }
4bfcbd7a
FV		 4726 }
4727
74371272
JA		 4728 ret = stmmac_phy_setup(priv);
4729 if (ret) {
4730 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4731 goto error_phy_setup;
4732 }
4733
57016590 4734 ret = register_netdev(ndev);
b2eb09af 4735 if (ret) {
b618ab45
HK		 4736 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4737 __func__, ret);
b2eb09af
FF		 4738 goto error_netdev_register;
4739 }
57016590 4740
5f2b8b62 4741#ifdef CONFIG_DEBUG_FS
8d72ab11 4742 stmmac_init_fs(ndev);
5f2b8b62
TR		 4743#endif
4744
57016590 4745 return ret;
47dd7a54 4746
6a81c26f 4747error_netdev_register:
74371272
JA		 4748 phylink_destroy(priv->phylink);
4749error_phy_setup:
b2eb09af
FF		 4750 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4751 priv->hw->pcs != STMMAC_PCS_TBI &&
4752 priv->hw->pcs != STMMAC_PCS_RTBI)
4753 stmmac_mdio_unregister(ndev);
6a81c26f 4754error_mdio_register:
8fce3331
JA		 4755 for (queue = 0; queue < maxq; queue++) {
4756 struct stmmac_channel *ch = &priv->channel[queue];
c22a3f48 4757
4ccb4585
JA		 4758 if (queue < priv->plat->rx_queues_to_use)
4759 netif_napi_del(&ch->rx_napi);
4760 if (queue < priv->plat->tx_queues_to_use)
4761 netif_napi_del(&ch->tx_napi);
c22a3f48 4762 }
62866e98 4763error_hw_init:
34877a15 4764 destroy_workqueue(priv->wq);
47dd7a54 4765
15ffac73 4766 return ret;
47dd7a54 4767}
b2e2f0c7 4768EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
47dd7a54
GC		 4769
4770/**
4771 * stmmac_dvr_remove
f4e7bd81 4772 * @dev: device pointer
47dd7a54 4773 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
bfab27a1 4774 * changes the link status, releases the DMA descriptor rings.
47dd7a54 4775 */
f4e7bd81 4776int stmmac_dvr_remove(struct device *dev)
47dd7a54 4777{
f4e7bd81 4778 struct net_device *ndev = dev_get_drvdata(dev);
aec7ff27 4779 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54 4780
38ddc59d 4781 netdev_info(priv->dev, "%s: removing driver", __func__);
47dd7a54 4782
5f2b8b62
TR		 4783#ifdef CONFIG_DEBUG_FS
4784 stmmac_exit_fs(ndev);
4785#endif
ae4f0d46 4786 stmmac_stop_all_dma(priv);
47dd7a54 4787
c10d4c82 4788 stmmac_mac_set(priv, priv->ioaddr, false);
47dd7a54 4789 netif_carrier_off(ndev);
47dd7a54 4790 unregister_netdev(ndev);
74371272 4791 phylink_destroy(priv->phylink);
f573c0b9 4792 if (priv->plat->stmmac_rst)
4793 reset_control_assert(priv->plat->stmmac_rst);
4794 clk_disable_unprepare(priv->plat->pclk);
4795 clk_disable_unprepare(priv->plat->stmmac_clk);
3fe5cadb
GC		 4796 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4797 priv->hw->pcs != STMMAC_PCS_TBI &&
4798 priv->hw->pcs != STMMAC_PCS_RTBI)
e743471f 4799 stmmac_mdio_unregister(ndev);
34877a15 4800 destroy_workqueue(priv->wq);
29555fa3 4801 mutex_destroy(&priv->lock);
47dd7a54
GC		 4802
4803 return 0;
4804}
b2e2f0c7 4805EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
47dd7a54 4806
732fdf0e
GC		 4807/**
4808 * stmmac_suspend - suspend callback
f4e7bd81 4809 * @dev: device pointer
732fdf0e
GC		 4810 * Description: this is the function to suspend the device and it is called
4811 * by the platform driver to stop the network queue, release the resources,
4812 * program the PMT register (for WoL), clean and release driver resources.
4813 */
f4e7bd81 4814int stmmac_suspend(struct device *dev)
47dd7a54 4815{
f4e7bd81 4816 struct net_device *ndev = dev_get_drvdata(dev);
874bd42d 4817 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54 4818
874bd42d 4819 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 4820 return 0;
4821
3e2bf04f 4822 phylink_mac_change(priv->phylink, false);
47dd7a54 4823
134cc4ce 4824 mutex_lock(&priv->lock);
19e13cb2 4825
874bd42d 4826 netif_device_detach(ndev);
c22a3f48 4827 stmmac_stop_all_queues(priv);
47dd7a54 4828
c22a3f48 4829 stmmac_disable_all_queues(priv);
874bd42d
GC		 4830
4831 /* Stop TX/RX DMA */
ae4f0d46 4832 stmmac_stop_all_dma(priv);
c24602ef 4833
874bd42d 4834 /* Enable Power down mode by programming the PMT regs */
89f7f2cf 4835 if (device_may_wakeup(priv->device)) {
c10d4c82 4836 stmmac_pmt(priv, priv->hw, priv->wolopts);
89f7f2cf
SK		 4837 priv->irq_wake = 1;
4838 } else {
134cc4ce 4839 mutex_unlock(&priv->lock);
3e2bf04f
JA		 4840 rtnl_lock();
4841 phylink_stop(priv->phylink);
4842 rtnl_unlock();
134cc4ce 4843 mutex_lock(&priv->lock);
3e2bf04f 4844
c10d4c82 4845 stmmac_mac_set(priv, priv->ioaddr, false);
db88f10a 4846 pinctrl_pm_select_sleep_state(priv->device);
ba1377ff 4847 /* Disable clock in case of PWM is off */
e497c20e
BH		 4848 if (priv->plat->clk_ptp_ref)
4849 clk_disable_unprepare(priv->plat->clk_ptp_ref);
4850 clk_disable_unprepare(priv->plat->pclk);
4851 clk_disable_unprepare(priv->plat->stmmac_clk);
ba1377ff 4852 }
29555fa3 4853 mutex_unlock(&priv->lock);
2d871aa0 4854
bd00632c 4855 priv->speed = SPEED_UNKNOWN;
47dd7a54
GC		 4856 return 0;
4857}
b2e2f0c7 4858EXPORT_SYMBOL_GPL(stmmac_suspend);
47dd7a54 4859
54139cf3
JP		 4860/**
4861 * stmmac_reset_queues_param - reset queue parameters
4862 * @dev: device pointer
4863 */
4864static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4865{
4866 u32 rx_cnt = priv->plat->rx_queues_to_use;
ce736788 4867 u32 tx_cnt = priv->plat->tx_queues_to_use;
54139cf3
JP		 4868 u32 queue;
4869
4870 for (queue = 0; queue < rx_cnt; queue++) {
4871 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4872
4873 rx_q->cur_rx = 0;
4874 rx_q->dirty_rx = 0;
4875 }
4876
ce736788
JP		 4877 for (queue = 0; queue < tx_cnt; queue++) {
4878 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4879
4880 tx_q->cur_tx = 0;
4881 tx_q->dirty_tx = 0;
8d212a9e 4882 tx_q->mss = 0;
ce736788 4883 }
54139cf3
JP		 4884}
4885
732fdf0e
GC		 4886/**
4887 * stmmac_resume - resume callback
f4e7bd81 4888 * @dev: device pointer
732fdf0e
GC		 4889 * Description: when resume this function is invoked to setup the DMA and CORE
4890 * in a usable state.
4891 */
f4e7bd81 4892int stmmac_resume(struct device *dev)
47dd7a54 4893{
f4e7bd81 4894 struct net_device *ndev = dev_get_drvdata(dev);
874bd42d 4895 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54 4896
874bd42d 4897 if (!netif_running(ndev))
47dd7a54
GC		 4898 return 0;
4899
47dd7a54
GC		 4900 /* Power Down bit, into the PM register, is cleared
4901 * automatically as soon as a magic packet or a Wake-up frame
4902 * is received. Anyway, it's better to manually clear
4903 * this bit because it can generate problems while resuming
ceb69499
GC		 4904 * from another devices (e.g. serial console).
4905 */
623997fb 4906 if (device_may_wakeup(priv->device)) {
29555fa3 4907 mutex_lock(&priv->lock);
c10d4c82 4908 stmmac_pmt(priv, priv->hw, 0);
29555fa3 4909 mutex_unlock(&priv->lock);
89f7f2cf 4910 priv->irq_wake = 0;
623997fb 4911 } else {
db88f10a 4912 pinctrl_pm_select_default_state(priv->device);
8d45e42b 4913 /* enable the clk previously disabled */
e497c20e
BH		 4914 clk_prepare_enable(priv->plat->stmmac_clk);
4915 clk_prepare_enable(priv->plat->pclk);
4916 if (priv->plat->clk_ptp_ref)
4917 clk_prepare_enable(priv->plat->clk_ptp_ref);
623997fb
SK		 4918 /* reset the phy so that it's ready */
4919 if (priv->mii)
4920 stmmac_mdio_reset(priv->mii);
4921 }
47dd7a54 4922
874bd42d 4923 netif_device_attach(ndev);
47dd7a54 4924
29555fa3 4925 mutex_lock(&priv->lock);
f55d84b0 4926
54139cf3
JP		 4927 stmmac_reset_queues_param(priv);
4928
ae79a639
GC		 4929 stmmac_clear_descriptors(priv);
4930
fe131929 4931 stmmac_hw_setup(ndev, false);
d429b66e 4932 stmmac_init_coalesce(priv);
ac316c78 4933 stmmac_set_rx_mode(ndev);
47dd7a54 4934
c22a3f48 4935 stmmac_enable_all_queues(priv);
47dd7a54 4936
c22a3f48 4937 stmmac_start_all_queues(priv);
47dd7a54 4938
19e13cb2 4939 mutex_unlock(&priv->lock);
102463b1 4940
3e2bf04f
JA		 4941 if (!device_may_wakeup(priv->device)) {
4942 rtnl_lock();
4943 phylink_start(priv->phylink);
4944 rtnl_unlock();
4945 }
4946
4947 phylink_mac_change(priv->phylink, true);
19e13cb2 4948
47dd7a54
GC		 4949 return 0;
4950}
b2e2f0c7 4951EXPORT_SYMBOL_GPL(stmmac_resume);
ba27ec66 4952
47dd7a54
GC		 4953#ifndef MODULE
4954static int __init stmmac_cmdline_opt(char *str)
4955{
4956 char *opt;
4957
4958 if (!str || !*str)
4959 return -EINVAL;
4960 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28 4961 if (!strncmp(opt, "debug:", 6)) {
ea2ab871 4962 if (kstrtoint(opt + 6, 0, &debug))
f3240e28
GC		 4963 goto err;
4964 } else if (!strncmp(opt, "phyaddr:", 8)) {
ea2ab871 4965 if (kstrtoint(opt + 8, 0, &phyaddr))
f3240e28 4966 goto err;
f3240e28 4967 } else if (!strncmp(opt, "buf_sz:", 7)) {
ea2ab871 4968 if (kstrtoint(opt + 7, 0, &buf_sz))
f3240e28
GC		 4969 goto err;
4970 } else if (!strncmp(opt, "tc:", 3)) {
ea2ab871 4971 if (kstrtoint(opt + 3, 0, &tc))
f3240e28
GC		 4972 goto err;
4973 } else if (!strncmp(opt, "watchdog:", 9)) {
ea2ab871 4974 if (kstrtoint(opt + 9, 0, &watchdog))
f3240e28
GC		 4975 goto err;
4976 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
ea2ab871 4977 if (kstrtoint(opt + 10, 0, &flow_ctrl))
f3240e28
GC		 4978 goto err;
4979 } else if (!strncmp(opt, "pause:", 6)) {
ea2ab871 4980 if (kstrtoint(opt + 6, 0, &pause))
f3240e28 4981 goto err;
506f669c 4982 } else if (!strncmp(opt, "eee_timer:", 10)) {
d765955d
GC		 4983 if (kstrtoint(opt + 10, 0, &eee_timer))
4984 goto err;
4a7d666a
GC		 4985 } else if (!strncmp(opt, "chain_mode:", 11)) {
4986 if (kstrtoint(opt + 11, 0, &chain_mode))
4987 goto err;
f3240e28 4988 }
47dd7a54
GC		 4989 }
4990 return 0;
f3240e28
GC		 4991
4992err:
4993 pr_err("%s: ERROR broken module parameter conversion", __func__);
4994 return -EINVAL;
47dd7a54
GC		 4995}
4996
4997__setup("stmmaceth=", stmmac_cmdline_opt);
ceb69499 4998#endif /* MODULE */
6fc0d0f2 4999
466c5ac8
MO		 5000static int __init stmmac_init(void)
5001{
5002#ifdef CONFIG_DEBUG_FS
5003 /* Create debugfs main directory if it doesn't exist yet */
8d72ab11 5004 if (!stmmac_fs_dir)
466c5ac8 5005 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
466c5ac8
MO		 5006#endif
5007
5008 return 0;
5009}
5010
5011static void __exit stmmac_exit(void)
5012{
5013#ifdef CONFIG_DEBUG_FS
5014 debugfs_remove_recursive(stmmac_fs_dir);
5015#endif
5016}
5017
5018module_init(stmmac_init)
5019module_exit(stmmac_exit)
5020
6fc0d0f2
GC		 5021MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
5022MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
5023MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)