[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / dwmac4_dma.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
 * DWC Ether MAC version 4.xx  has been used for  developing this code.
 *
 * This contains the functions to handle the dma.
 *
 * Copyright (C) 2015  STMicroelectronics Ltd
 *
 * Author: Alexandre Torgue <alexandre.torgue@st.com>
 */

#include <linux/io.h>
#include "dwmac4.h"
#include "dwmac4_dma.h"

static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
{
	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
	int i;

	pr_info("dwmac4: Master AXI performs %s burst length\n",
		(value & DMA_SYS_BUS_FB) ? "fixed" : "any");

	if (axi->axi_lpi_en)
		value |= DMA_AXI_EN_LPI;
	if (axi->axi_xit_frm)
		value |= DMA_AXI_LPI_XIT_FRM;

	value &= ~DMA_AXI_WR_OSR_LMT;
	value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
		 DMA_AXI_WR_OSR_LMT_SHIFT;

	value &= ~DMA_AXI_RD_OSR_LMT;
	value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
		 DMA_AXI_RD_OSR_LMT_SHIFT;

	/* Depending on the UNDEF bit the Master AXI will perform any burst
	 * length according to the BLEN programmed (by default all BLEN are
	 * set).
	 */
	for (i = 0; i < AXI_BLEN; i++) {
		switch (axi->axi_blen[i]) {
		case 256:
			value |= DMA_AXI_BLEN256;
			break;
		case 128:
			value |= DMA_AXI_BLEN128;
			break;
		case 64:
			value |= DMA_AXI_BLEN64;
			break;
		case 32:
			value |= DMA_AXI_BLEN32;
			break;
		case 16:
			value |= DMA_AXI_BLEN16;
			break;
		case 8:
			value |= DMA_AXI_BLEN8;
			break;
		case 4:
			value |= DMA_AXI_BLEN4;
			break;
		}
	}

	writel(value, ioaddr + DMA_SYS_BUS_MODE);
}

static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
				    struct stmmac_dma_cfg *dma_cfg,
				    dma_addr_t dma_rx_phy, u32 chan)
{
	u32 value;
	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;

	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
	value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));

	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
}

static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
				    struct stmmac_dma_cfg *dma_cfg,
				    dma_addr_t dma_tx_phy, u32 chan)
{
	u32 value;
	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;

	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
	value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);

	/* Enable OSP to get best performance */
	value |= DMA_CONTROL_OSP;

	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));

	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
}

static void dwmac4_dma_init_channel(void __iomem *ioaddr,
				    struct stmmac_dma_cfg *dma_cfg, u32 chan)
{
	u32 value;

	/* common channel control register config */
	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
	if (dma_cfg->pblx8)
		value = value | DMA_BUS_MODE_PBL;
	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));

	/* Mask interrupts by writing to CSR7 */
	writel(DMA_CHAN_INTR_DEFAULT_MASK,
	       ioaddr + DMA_CHAN_INTR_ENA(chan));
}

static void dwmac4_dma_init(void __iomem *ioaddr,
			    struct stmmac_dma_cfg *dma_cfg, int atds)
{
	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);

	/* Set the Fixed burst mode */
	if (dma_cfg->fixed_burst)
		value |= DMA_SYS_BUS_FB;

	/* Mixed Burst has no effect when fb is set */
	if (dma_cfg->mixed_burst)
		value |= DMA_SYS_BUS_MB;

	if (dma_cfg->aal)
		value |= DMA_SYS_BUS_AAL;

	writel(value, ioaddr + DMA_SYS_BUS_MODE);
}

static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
				  u32 *reg_space)
{
	reg_space[DMA_CHAN_CONTROL(channel) / 4] =
		readl(ioaddr + DMA_CHAN_CONTROL(channel));
	reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
		readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
	reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
		readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
	reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
	reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
	reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
	reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
	reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
		readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
	reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
		readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
	reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
		readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
	reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
		readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
	reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
		readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
	reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
		readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
	reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
		readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
	reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
	reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
	reg_space[DMA_CHAN_STATUS(channel) / 4] =
		readl(ioaddr + DMA_CHAN_STATUS(channel));
}

static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
{
	int i;

	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
		_dwmac4_dump_dma_regs(ioaddr, i, reg_space);
}

static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan)
{
	u32 chan;

	for (chan = 0; chan < number_chan; chan++)
		writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan));
}

static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
				       u32 channel, int fifosz, u8 qmode)
{
	unsigned int rqs = fifosz / 256 - 1;
	u32 mtl_rx_op, mtl_rx_int;

	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));

	if (mode == SF_DMA_MODE) {
		pr_debug("GMAC: enable RX store and forward mode\n");
		mtl_rx_op |= MTL_OP_MODE_RSF;
	} else {
		pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
		mtl_rx_op &= ~MTL_OP_MODE_RSF;
		mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
		if (mode <= 32)
			mtl_rx_op |= MTL_OP_MODE_RTC_32;
		else if (mode <= 64)
			mtl_rx_op |= MTL_OP_MODE_RTC_64;
		else if (mode <= 96)
			mtl_rx_op |= MTL_OP_MODE_RTC_96;
		else
			mtl_rx_op |= MTL_OP_MODE_RTC_128;
	}

	mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
	mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;

	/* Enable flow control only if each channel gets 4 KiB or more FIFO and
	 * only if channel is not an AVB channel.
	 */
	if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
		unsigned int rfd, rfa;

		mtl_rx_op |= MTL_OP_MODE_EHFC;

		/* Set Threshold for Activating Flow Control to min 2 frames,
		 * i.e. 1500 * 2 = 3000 bytes.
		 *
		 * Set Threshold for Deactivating Flow Control to min 1 frame,
		 * i.e. 1500 bytes.
		 */
		switch (fifosz) {
		case 4096:
			/* This violates the above formula because of FIFO size
			 * limit therefore overflow may occur in spite of this.
			 */
			rfd = 0x03; /* Full-2.5K */
			rfa = 0x01; /* Full-1.5K */
			break;

		case 8192:
			rfd = 0x06; /* Full-4K */
			rfa = 0x0a; /* Full-6K */
			break;

		case 16384:
			rfd = 0x06; /* Full-4K */
			rfa = 0x12; /* Full-10K */
			break;

		default:
			rfd = 0x06; /* Full-4K */
			rfa = 0x1e; /* Full-16K */
			break;
		}

		mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
		mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;

		mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
		mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;
	}

	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));

	/* Enable MTL RX overflow */
	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
	writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
	       ioaddr + MTL_CHAN_INT_CTRL(channel));
}

static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
				       u32 channel, int fifosz, u8 qmode)
{
	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
	unsigned int tqs = fifosz / 256 - 1;

	if (mode == SF_DMA_MODE) {
		pr_debug("GMAC: enable TX store and forward mode\n");
		/* Transmit COE type 2 cannot be done in cut-through mode. */
		mtl_tx_op |= MTL_OP_MODE_TSF;
	} else {
		pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
		mtl_tx_op &= ~MTL_OP_MODE_TSF;
		mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
		/* Set the transmit threshold */
		if (mode <= 32)
			mtl_tx_op |= MTL_OP_MODE_TTC_32;
		else if (mode <= 64)
			mtl_tx_op |= MTL_OP_MODE_TTC_64;
		else if (mode <= 96)
			mtl_tx_op |= MTL_OP_MODE_TTC_96;
		else if (mode <= 128)
			mtl_tx_op |= MTL_OP_MODE_TTC_128;
		else if (mode <= 192)
			mtl_tx_op |= MTL_OP_MODE_TTC_192;
		else if (mode <= 256)
			mtl_tx_op |= MTL_OP_MODE_TTC_256;
		else if (mode <= 384)
			mtl_tx_op |= MTL_OP_MODE_TTC_384;
		else
			mtl_tx_op |= MTL_OP_MODE_TTC_512;
	}
	/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
	 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
	 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
	 * with reset values: TXQEN off, TQS 256 bytes.
	 *
	 * TXQEN must be written for multi-channel operation and TQS must
	 * reflect the available fifo size per queue (total fifo size / number
	 * of enabled queues).
	 */
	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
	if (qmode != MTL_QUEUE_AVB)
		mtl_tx_op |= MTL_OP_MODE_TXQEN;
	else
		mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
	mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
	mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;

	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
}

static void dwmac4_get_hw_feature(void __iomem *ioaddr,
				  struct dma_features *dma_cap)
{
	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);

	/*  MAC HW feature0 */
	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
	dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
	dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
	dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
	/* MMC */
	dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
	/* IEEE 1588-2008 */
	dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
	/* TX and RX csum */
	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
	dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
	dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
	dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;

	/* MAC HW feature1 */
	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
	dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
	/* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
	 * shifting and store the sizes in bytes.
	 */
	dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
	dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
	/* MAC HW feature2 */
	hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
	/* TX and RX number of channels */
	dma_cap->number_rx_channel =
		((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
	dma_cap->number_tx_channel =
		((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
	/* TX and RX number of queues */
	dma_cap->number_rx_queues =
		((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
	dma_cap->number_tx_queues =
		((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
	/* PPS output */
	dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;

	/* IEEE 1588-2002 */
	dma_cap->time_stamp = 0;

	/* MAC HW feature3 */
	hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);

	/* 5.10 Features */
	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
	dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
	dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
	dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
	dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
}

/* Enable/disable TSO feature and set MSS */
static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
{
	u32 value;

	if (en) {
		/* enable TSO */
		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
		writel(value | DMA_CONTROL_TSE,
		       ioaddr + DMA_CHAN_TX_CONTROL(chan));
	} else {
		/* enable TSO */
		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
		writel(value & ~DMA_CONTROL_TSE,
		       ioaddr + DMA_CHAN_TX_CONTROL(chan));
	}
}

static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
{
	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));

	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
	if (qmode != MTL_QUEUE_AVB)
		mtl_tx_op |= MTL_OP_MODE_TXQEN;
	else
		mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;

	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
}

static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
{
	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));

	value &= ~DMA_RBSZ_MASK;
	value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;

	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
}

const struct stmmac_dma_ops dwmac4_dma_ops = {
	.reset = dwmac4_dma_reset,
	.init = dwmac4_dma_init,
	.init_chan = dwmac4_dma_init_channel,
	.init_rx_chan = dwmac4_dma_init_rx_chan,
	.init_tx_chan = dwmac4_dma_init_tx_chan,
	.axi = dwmac4_dma_axi,
	.dump_regs = dwmac4_dump_dma_regs,
	.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
	.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
	.enable_dma_irq = dwmac4_enable_dma_irq,
	.disable_dma_irq = dwmac4_disable_dma_irq,
	.start_tx = dwmac4_dma_start_tx,
	.stop_tx = dwmac4_dma_stop_tx,
	.start_rx = dwmac4_dma_start_rx,
	.stop_rx = dwmac4_dma_stop_rx,
	.dma_interrupt = dwmac4_dma_interrupt,
	.get_hw_feature = dwmac4_get_hw_feature,
	.rx_watchdog = dwmac4_rx_watchdog,
	.set_rx_ring_len = dwmac4_set_rx_ring_len,
	.set_tx_ring_len = dwmac4_set_tx_ring_len,
	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
	.enable_tso = dwmac4_enable_tso,
	.qmode = dwmac4_qmode,
	.set_bfsize = dwmac4_set_bfsize,
};

const struct stmmac_dma_ops dwmac410_dma_ops = {
	.reset = dwmac4_dma_reset,
	.init = dwmac4_dma_init,
	.init_chan = dwmac4_dma_init_channel,
	.init_rx_chan = dwmac4_dma_init_rx_chan,
	.init_tx_chan = dwmac4_dma_init_tx_chan,
	.axi = dwmac4_dma_axi,
	.dump_regs = dwmac4_dump_dma_regs,
	.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
	.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
	.enable_dma_irq = dwmac410_enable_dma_irq,
	.disable_dma_irq = dwmac4_disable_dma_irq,
	.start_tx = dwmac4_dma_start_tx,
	.stop_tx = dwmac4_dma_stop_tx,
	.start_rx = dwmac4_dma_start_rx,
	.stop_rx = dwmac4_dma_stop_rx,
	.dma_interrupt = dwmac4_dma_interrupt,
	.get_hw_feature = dwmac4_get_hw_feature,
	.rx_watchdog = dwmac4_rx_watchdog,
	.set_rx_ring_len = dwmac4_set_rx_ring_len,
	.set_tx_ring_len = dwmac4_set_tx_ring_len,
	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
	.enable_tso = dwmac4_enable_tso,
	.qmode = dwmac4_qmode,
	.set_bfsize = dwmac4_set_bfsize,
};
Commit	Line	Data
75a6faf6	1	// SPDX-License-Identifier: GPL-2.0-only
48863ce5 AT	2	/*
	3	* This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
	4	* DWC Ether MAC version 4.xx has been used for developing this code.
	5	*
	6	* This contains the functions to handle the dma.
	7	*
	8	* Copyright (C) 2015 STMicroelectronics Ltd
	9	*
48863ce5 AT	10	* Author: Alexandre Torgue <alexandre.torgue@st.com>
	11	*/
	12
	13	#include <linux/io.h>
	14	#include "dwmac4.h"
	15	#include "dwmac4_dma.h"
	16
	17	static void dwmac4_dma_axi(void __iomem ioaddr, struct stmmac_axi axi)
	18	{
	19	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
	20	int i;
	21
	22	pr_info("dwmac4: Master AXI performs %s burst length\n",
	23	(value & DMA_SYS_BUS_FB) ? "fixed" : "any");
	24
	25	if (axi->axi_lpi_en)
	26	value \|= DMA_AXI_EN_LPI;
	27	if (axi->axi_xit_frm)
	28	value \|= DMA_AXI_LPI_XIT_FRM;
	29
6b3374cb	30	value &= ~DMA_AXI_WR_OSR_LMT;
48863ce5 AT	31	value \|= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
	32	DMA_AXI_WR_OSR_LMT_SHIFT;
	33
6b3374cb	34	value &= ~DMA_AXI_RD_OSR_LMT;
48863ce5 AT	35	value \|= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
	36	DMA_AXI_RD_OSR_LMT_SHIFT;
	37
	38	/* Depending on the UNDEF bit the Master AXI will perform any burst
	39	* length according to the BLEN programmed (by default all BLEN are
	40	* set).
	41	*/
	42	for (i = 0; i < AXI_BLEN; i++) {
	43	switch (axi->axi_blen[i]) {
	44	case 256:
	45	value \|= DMA_AXI_BLEN256;
	46	break;
	47	case 128:
	48	value \|= DMA_AXI_BLEN128;
	49	break;
	50	case 64:
	51	value \|= DMA_AXI_BLEN64;
	52	break;
	53	case 32:
	54	value \|= DMA_AXI_BLEN32;
	55	break;
	56	case 16:
	57	value \|= DMA_AXI_BLEN16;
	58	break;
	59	case 8:
	60	value \|= DMA_AXI_BLEN8;
	61	break;
	62	case 4:
	63	value \|= DMA_AXI_BLEN4;
	64	break;
	65	}
	66	}
	67
	68	writel(value, ioaddr + DMA_SYS_BUS_MODE);
	69	}
	70
72de4655 CIK	71	static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
72de4655 CIK	72	struct stmmac_dma_cfg *dma_cfg,
06a80a7d	73	dma_addr_t dma_rx_phy, u32 chan)
48863ce5 AT	74	{
48863ce5 AT	75	u32 value;
47f2a9ce	76	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
48863ce5	77
47f2a9ce JP	78	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
	79	value = value \| (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
	80	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
	81
06a80a7d	82	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
47f2a9ce	83	}
48863ce5	84
72de4655 CIK	85	static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
72de4655 CIK	86	struct stmmac_dma_cfg *dma_cfg,
06a80a7d	87	dma_addr_t dma_tx_phy, u32 chan)
47f2a9ce JP	88	{
	89	u32 value;
	90	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
	91
	92	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
89caaa2d	93	value = value \| (txpbl << DMA_BUS_MODE_PBL_SHIFT);
67e1c406 JA	94
	95	/* Enable OSP to get best performance */
	96	value \|= DMA_CONTROL_OSP;
	97
47f2a9ce	98	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
48863ce5	99
06a80a7d	100	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
47f2a9ce	101	}
48863ce5	102
72de4655 CIK	103	static void dwmac4_dma_init_channel(void __iomem *ioaddr,
72de4655 CIK	104	struct stmmac_dma_cfg *dma_cfg, u32 chan)
47f2a9ce JP	105	{
	106	u32 value;
	107
	108	/* common channel control register config */
	109	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
	110	if (dma_cfg->pblx8)
	111	value = value \| DMA_BUS_MODE_PBL;
	112	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
48863ce5	113
47f2a9ce JP	114	/* Mask interrupts by writing to CSR7 */
	115	writel(DMA_CHAN_INTR_DEFAULT_MASK,
	116	ioaddr + DMA_CHAN_INTR_ENA(chan));
48863ce5 AT	117	}
48863ce5 AT	118
50ca903a	119	static void dwmac4_dma_init(void __iomem *ioaddr,
24aaed0c	120	struct stmmac_dma_cfg *dma_cfg, int atds)
48863ce5 AT	121	{
48863ce5 AT	122	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
48863ce5 AT	123
48863ce5 AT	124	/* Set the Fixed burst mode */
50ca903a	125	if (dma_cfg->fixed_burst)
48863ce5 AT	126	value \|= DMA_SYS_BUS_FB;
	127
	128	/* Mixed Burst has no effect when fb is set */
50ca903a	129	if (dma_cfg->mixed_burst)
48863ce5 AT	130	value \|= DMA_SYS_BUS_MB;
48863ce5 AT	131
50ca903a	132	if (dma_cfg->aal)
48863ce5 AT	133	value \|= DMA_SYS_BUS_AAL;
	134
	135	writel(value, ioaddr + DMA_SYS_BUS_MODE);
48863ce5 AT	136	}
48863ce5 AT	137
fbf68229 LC	138	static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
fbf68229 LC	139	u32 *reg_space)
48863ce5	140	{
fbf68229 LC	141	reg_space[DMA_CHAN_CONTROL(channel) / 4] =
	142	readl(ioaddr + DMA_CHAN_CONTROL(channel));
	143	reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
	144	readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
	145	reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
	146	readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
	147	reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
	148	readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
	149	reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
	150	readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
	151	reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
	152	readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
	153	reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
	154	readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
	155	reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
	156	readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
	157	reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
	158	readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
	159	reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
	160	readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
	161	reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
	162	readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
	163	reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
	164	readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
	165	reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
	166	readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
	167	reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
	168	readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
	169	reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
	170	readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
	171	reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
	172	readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
	173	reg_space[DMA_CHAN_STATUS(channel) / 4] =
	174	readl(ioaddr + DMA_CHAN_STATUS(channel));
48863ce5 AT	175	}
48863ce5 AT	176
fbf68229	177	static void dwmac4_dump_dma_regs(void __iomem ioaddr, u32 reg_space)
48863ce5 AT	178	{
	179	int i;
	180
48863ce5	181	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
fbf68229	182	_dwmac4_dump_dma_regs(ioaddr, i, reg_space);
48863ce5 AT	183	}
48863ce5 AT	184
3c55d4d0	185	static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan)
48863ce5	186	{
3c55d4d0	187	u32 chan;
48863ce5	188
3c55d4d0 JP	189	for (chan = 0; chan < number_chan; chan++)
3c55d4d0 JP	190	writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan));
48863ce5 AT	191	}
48863ce5 AT	192
6deee222	193	static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
a0daae13	194	u32 channel, int fifosz, u8 qmode)
48863ce5	195	{
6deee222 JP	196	unsigned int rqs = fifosz / 256 - 1;
6deee222 JP	197	u32 mtl_rx_op, mtl_rx_int;
48863ce5 AT	198
	199	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
	200
6deee222	201	if (mode == SF_DMA_MODE) {
48863ce5 AT	202	pr_debug("GMAC: enable RX store and forward mode\n");
	203	mtl_rx_op \|= MTL_OP_MODE_RSF;
	204	} else {
6deee222	205	pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
48863ce5 AT	206	mtl_rx_op &= ~MTL_OP_MODE_RSF;
48863ce5 AT	207	mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
6deee222	208	if (mode <= 32)
48863ce5	209	mtl_rx_op \|= MTL_OP_MODE_RTC_32;
6deee222	210	else if (mode <= 64)
48863ce5	211	mtl_rx_op \|= MTL_OP_MODE_RTC_64;
6deee222	212	else if (mode <= 96)
48863ce5 AT	213	mtl_rx_op \|= MTL_OP_MODE_RTC_96;
	214	else
	215	mtl_rx_op \|= MTL_OP_MODE_RTC_128;
	216	}
	217
356b7557 TR	218	mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
	219	mtl_rx_op \|= rqs << MTL_OP_MODE_RQS_SHIFT;
	220
a0daae13 JA	221	/* Enable flow control only if each channel gets 4 KiB or more FIFO and
	222	* only if channel is not an AVB channel.
	223	*/
	224	if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
356b7557 TR	225	unsigned int rfd, rfa;
	226
	227	mtl_rx_op \|= MTL_OP_MODE_EHFC;
	228
	229	/* Set Threshold for Activating Flow Control to min 2 frames,
	230	* i.e. 1500 * 2 = 3000 bytes.
	231	*
	232	* Set Threshold for Deactivating Flow Control to min 1 frame,
	233	* i.e. 1500 bytes.
	234	*/
6deee222	235	switch (fifosz) {
356b7557 TR	236	case 4096:
	237	/* This violates the above formula because of FIFO size
	238	* limit therefore overflow may occur in spite of this.
	239	*/
	240	rfd = 0x03; /* Full-2.5K */
	241	rfa = 0x01; /* Full-1.5K */
	242	break;
	243
	244	case 8192:
	245	rfd = 0x06; /* Full-4K */
	246	rfa = 0x0a; /* Full-6K */
	247	break;
	248
	249	case 16384:
	250	rfd = 0x06; /* Full-4K */
	251	rfa = 0x12; /* Full-10K */
	252	break;
	253
	254	default:
	255	rfd = 0x06; /* Full-4K */
	256	rfa = 0x1e; /* Full-16K */
	257	break;
	258	}
	259
	260	mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
	261	mtl_rx_op \|= rfd << MTL_OP_MODE_RFD_SHIFT;
	262
	263	mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
	264	mtl_rx_op \|= rfa << MTL_OP_MODE_RFA_SHIFT;
	265	}
	266
48863ce5 AT	267	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
	268
	269	/* Enable MTL RX overflow */
	270	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
	271	writel(mtl_rx_int \| MTL_RX_OVERFLOW_INT_EN,
	272	ioaddr + MTL_CHAN_INT_CTRL(channel));
	273	}
	274
6deee222	275	static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
a0daae13	276	u32 channel, int fifosz, u8 qmode)
48863ce5	277	{
6deee222	278	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
52a76235	279	unsigned int tqs = fifosz / 256 - 1;
6deee222 JP	280
	281	if (mode == SF_DMA_MODE) {
	282	pr_debug("GMAC: enable TX store and forward mode\n");
	283	/* Transmit COE type 2 cannot be done in cut-through mode. */
	284	mtl_tx_op \|= MTL_OP_MODE_TSF;
	285	} else {
	286	pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
	287	mtl_tx_op &= ~MTL_OP_MODE_TSF;
	288	mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
	289	/* Set the transmit threshold */
	290	if (mode <= 32)
	291	mtl_tx_op \|= MTL_OP_MODE_TTC_32;
	292	else if (mode <= 64)
	293	mtl_tx_op \|= MTL_OP_MODE_TTC_64;
	294	else if (mode <= 96)
	295	mtl_tx_op \|= MTL_OP_MODE_TTC_96;
	296	else if (mode <= 128)
	297	mtl_tx_op \|= MTL_OP_MODE_TTC_128;
	298	else if (mode <= 192)
	299	mtl_tx_op \|= MTL_OP_MODE_TTC_192;
	300	else if (mode <= 256)
	301	mtl_tx_op \|= MTL_OP_MODE_TTC_256;
	302	else if (mode <= 384)
	303	mtl_tx_op \|= MTL_OP_MODE_TTC_384;
	304	else
	305	mtl_tx_op \|= MTL_OP_MODE_TTC_512;
	306	}
	307	/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
	308	* with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
	309	* For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
	310	* with reset values: TXQEN off, TQS 256 bytes.
	311	*
52a76235 JA	312	* TXQEN must be written for multi-channel operation and TQS must
	313	* reflect the available fifo size per queue (total fifo size / number
	314	* of enabled queues).
6deee222	315	*/
a0daae13 JA	316	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
	317	if (qmode != MTL_QUEUE_AVB)
	318	mtl_tx_op \|= MTL_OP_MODE_TXQEN;
	319	else
	320	mtl_tx_op \|= MTL_OP_MODE_TXQEN_AV;
52a76235 JA	321	mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
	322	mtl_tx_op \|= tqs << MTL_OP_MODE_TQS_SHIFT;
	323
6deee222	324	writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
48863ce5 AT	325	}
	326
	327	static void dwmac4_get_hw_feature(void __iomem *ioaddr,
	328	struct dma_features *dma_cap)
	329	{
	330	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
	331
	332	/* MAC HW feature0 */
	333	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
	334	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
	335	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
c1be0022	336	dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
48863ce5 AT	337	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
	338	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
	339	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
	340	dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
	341	dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
	342	/* MMC */
	343	dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
	344	/* IEEE 1588-2008 */
	345	dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
	346	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	347	dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
	348	/* TX and RX csum */
	349	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
	350	dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
1d982e93	351	dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
c9b10043	352	dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
48863ce5 AT	353
	354	/* MAC HW feature1 */
	355	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
b8ef7020	356	dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
48863ce5 AT	357	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
48863ce5 AT	358	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
11fbf811 TR	359	/* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
	360	* shifting and store the sizes in bytes.
	361	*/
	362	dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
	363	dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
48863ce5 AT	364	/* MAC HW feature2 */
	365	hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
	366	/* TX and RX number of channels */
	367	dma_cap->number_rx_channel =
	368	((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
	369	dma_cap->number_tx_channel =
	370	((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
9eb12474	371	/* TX and RX number of queues */
	372	dma_cap->number_rx_queues =
	373	((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
	374	dma_cap->number_tx_queues =
	375	((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
9a8a02c9 JA	376	/* PPS output */
9a8a02c9 JA	377	dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;
48863ce5 AT	378
	379	/* IEEE 1588-2002 */
	380	dma_cap->time_stamp = 0;
8bf993a5 JA	381
	382	/* MAC HW feature3 */
	383	hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);
	384
	385	/* 5.10 Features */
	386	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
4dbbe8dd JA	387	dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
	388	dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
	389	dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
e94e3f3b	390	dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
48863ce5 AT	391	}
	392
	393	/* Enable/disable TSO feature and set MSS */
	394	static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
	395	{
	396	u32 value;
	397
	398	if (en) {
	399	/* enable TSO */
	400	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
	401	writel(value \| DMA_CONTROL_TSE,
	402	ioaddr + DMA_CHAN_TX_CONTROL(chan));
	403	} else {
	404	/* enable TSO */
	405	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
	406	writel(value & ~DMA_CONTROL_TSE,
	407	ioaddr + DMA_CHAN_TX_CONTROL(chan));
	408	}
	409	}
	410
1f705bc6 JA	411	static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
	412	{
	413	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
	414
	415	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
	416	if (qmode != MTL_QUEUE_AVB)
	417	mtl_tx_op \|= MTL_OP_MODE_TXQEN;
	418	else
	419	mtl_tx_op \|= MTL_OP_MODE_TXQEN_AV;
	420
	421	writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
	422	}
	423
4205c88e JA	424	static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
	425	{
	426	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
	427
	428	value &= ~DMA_RBSZ_MASK;
	429	value \|= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;
	430
	431	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
	432	}
	433
48863ce5 AT	434	const struct stmmac_dma_ops dwmac4_dma_ops = {
	435	.reset = dwmac4_dma_reset,
	436	.init = dwmac4_dma_init,
47f2a9ce JP	437	.init_chan = dwmac4_dma_init_channel,
	438	.init_rx_chan = dwmac4_dma_init_rx_chan,
	439	.init_tx_chan = dwmac4_dma_init_tx_chan,
48863ce5 AT	440	.axi = dwmac4_dma_axi,
48863ce5 AT	441	.dump_regs = dwmac4_dump_dma_regs,
6deee222 JP	442	.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
6deee222 JP	443	.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
48863ce5 AT	444	.enable_dma_irq = dwmac4_enable_dma_irq,
	445	.disable_dma_irq = dwmac4_disable_dma_irq,
	446	.start_tx = dwmac4_dma_start_tx,
	447	.stop_tx = dwmac4_dma_stop_tx,
	448	.start_rx = dwmac4_dma_start_rx,
	449	.stop_rx = dwmac4_dma_stop_rx,
	450	.dma_interrupt = dwmac4_dma_interrupt,
	451	.get_hw_feature = dwmac4_get_hw_feature,
	452	.rx_watchdog = dwmac4_rx_watchdog,
	453	.set_rx_ring_len = dwmac4_set_rx_ring_len,
	454	.set_tx_ring_len = dwmac4_set_tx_ring_len,
	455	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
	456	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
	457	.enable_tso = dwmac4_enable_tso,
1f705bc6	458	.qmode = dwmac4_qmode,
4205c88e	459	.set_bfsize = dwmac4_set_bfsize,
48863ce5 AT	460	};
	461
	462	const struct stmmac_dma_ops dwmac410_dma_ops = {
	463	.reset = dwmac4_dma_reset,
	464	.init = dwmac4_dma_init,
47f2a9ce JP	465	.init_chan = dwmac4_dma_init_channel,
	466	.init_rx_chan = dwmac4_dma_init_rx_chan,
	467	.init_tx_chan = dwmac4_dma_init_tx_chan,
48863ce5 AT	468	.axi = dwmac4_dma_axi,
48863ce5 AT	469	.dump_regs = dwmac4_dump_dma_regs,
6deee222 JP	470	.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
6deee222 JP	471	.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
48863ce5 AT	472	.enable_dma_irq = dwmac410_enable_dma_irq,
	473	.disable_dma_irq = dwmac4_disable_dma_irq,
	474	.start_tx = dwmac4_dma_start_tx,
	475	.stop_tx = dwmac4_dma_stop_tx,
	476	.start_rx = dwmac4_dma_start_rx,
	477	.stop_rx = dwmac4_dma_stop_rx,
	478	.dma_interrupt = dwmac4_dma_interrupt,
	479	.get_hw_feature = dwmac4_get_hw_feature,
	480	.rx_watchdog = dwmac4_rx_watchdog,
	481	.set_rx_ring_len = dwmac4_set_rx_ring_len,
	482	.set_tx_ring_len = dwmac4_set_tx_ring_len,
	483	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
	484	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
	485	.enable_tso = dwmac4_enable_tso,
1f705bc6	486	.qmode = dwmac4_qmode,
4205c88e	487	.set_bfsize = dwmac4_set_bfsize,
48863ce5	488	};