[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / dwmac4_dma.c

/*
 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
 * DWC Ether MAC version 4.xx  has been used for  developing this code.
 *
 * This contains the functions to handle the dma.
 *
 * Copyright (C) 2015  STMicroelectronics Ltd
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * Author: Alexandre Torgue <alexandre.torgue@st.com>
 */

#include <linux/io.h>
#include "dwmac4.h"
#include "dwmac4_dma.h"

static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
{
	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
	int i;

	pr_info("dwmac4: Master AXI performs %s burst length\n",
		(value & DMA_SYS_BUS_FB) ? "fixed" : "any");

	if (axi->axi_lpi_en)
		value |= DMA_AXI_EN_LPI;
	if (axi->axi_xit_frm)
		value |= DMA_AXI_LPI_XIT_FRM;

	value &= ~DMA_AXI_WR_OSR_LMT;
	value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
		 DMA_AXI_WR_OSR_LMT_SHIFT;

	value &= ~DMA_AXI_RD_OSR_LMT;
	value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
		 DMA_AXI_RD_OSR_LMT_SHIFT;

	/* Depending on the UNDEF bit the Master AXI will perform any burst
	 * length according to the BLEN programmed (by default all BLEN are
	 * set).
	 */
	for (i = 0; i < AXI_BLEN; i++) {
		switch (axi->axi_blen[i]) {
		case 256:
			value |= DMA_AXI_BLEN256;
			break;
		case 128:
			value |= DMA_AXI_BLEN128;
			break;
		case 64:
			value |= DMA_AXI_BLEN64;
			break;
		case 32:
			value |= DMA_AXI_BLEN32;
			break;
		case 16:
			value |= DMA_AXI_BLEN16;
			break;
		case 8:
			value |= DMA_AXI_BLEN8;
			break;
		case 4:
			value |= DMA_AXI_BLEN4;
			break;
		}
	}

	writel(value, ioaddr + DMA_SYS_BUS_MODE);
}

static void dwmac4_dma_init_channel(void __iomem *ioaddr, int pbl,
				    u32 dma_tx_phy, u32 dma_rx_phy,
				    u32 channel)
{
	u32 value;

	/* set PBL for each channels. Currently we affect same configuration
	 * on each channel
	 */
	value = readl(ioaddr + DMA_CHAN_CONTROL(channel));
	value = value | DMA_BUS_MODE_PBL;
	writel(value, ioaddr + DMA_CHAN_CONTROL(channel));

	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
	value = value | (pbl << DMA_BUS_MODE_PBL_SHIFT);
	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel));

	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
	value = value | (pbl << DMA_BUS_MODE_RPBL_SHIFT);
	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel));

	/* Mask interrupts by writing to CSR7 */
	writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel));

	writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
	writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
}

static void dwmac4_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
			    int aal, u32 dma_tx, u32 dma_rx, int atds)
{
	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
	int i;

	/* Set the Fixed burst mode */
	if (fb)
		value |= DMA_SYS_BUS_FB;

	/* Mixed Burst has no effect when fb is set */
	if (mb)
		value |= DMA_SYS_BUS_MB;

	if (aal)
		value |= DMA_SYS_BUS_AAL;

	writel(value, ioaddr + DMA_SYS_BUS_MODE);

	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
		dwmac4_dma_init_channel(ioaddr, pbl, dma_tx, dma_rx, i);
}

static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel)
{
	pr_debug(" Channel %d\n", channel);
	pr_debug("\tDMA_CHAN_CONTROL, offset: 0x%x, val: 0x%x\n", 0,
		 readl(ioaddr + DMA_CHAN_CONTROL(channel)));
	pr_debug("\tDMA_CHAN_TX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x4,
		 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)));
	pr_debug("\tDMA_CHAN_RX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x8,
		 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)));
	pr_debug("\tDMA_CHAN_TX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x14,
		 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)));
	pr_debug("\tDMA_CHAN_RX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x1c,
		 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)));
	pr_debug("\tDMA_CHAN_TX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x20,
		 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)));
	pr_debug("\tDMA_CHAN_RX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x28,
		 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)));
	pr_debug("\tDMA_CHAN_TX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x2c,
		 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)));
	pr_debug("\tDMA_CHAN_RX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x30,
		 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)));
	pr_debug("\tDMA_CHAN_INTR_ENA, offset: 0x%x, val: 0x%x\n", 0x34,
		 readl(ioaddr + DMA_CHAN_INTR_ENA(channel)));
	pr_debug("\tDMA_CHAN_RX_WATCHDOG, offset: 0x%x, val: 0x%x\n", 0x38,
		 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)));
	pr_debug("\tDMA_CHAN_SLOT_CTRL_STATUS, offset: 0x%x, val: 0x%x\n", 0x3c,
		 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)));
	pr_debug("\tDMA_CHAN_CUR_TX_DESC, offset: 0x%x, val: 0x%x\n", 0x44,
		 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)));
	pr_debug("\tDMA_CHAN_CUR_RX_DESC, offset: 0x%x, val: 0x%x\n", 0x4c,
		 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)));
	pr_debug("\tDMA_CHAN_CUR_TX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x54,
		 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)));
	pr_debug("\tDMA_CHAN_CUR_RX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x5c,
		 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)));
	pr_debug("\tDMA_CHAN_STATUS, offset: 0x%x, val: 0x%x\n", 0x60,
		 readl(ioaddr + DMA_CHAN_STATUS(channel)));
}

static void dwmac4_dump_dma_regs(void __iomem *ioaddr)
{
	int i;

	pr_debug(" GMAC4 DMA registers\n");

	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
		_dwmac4_dump_dma_regs(ioaddr, i);
}

static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt)
{
	int i;

	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
		writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i));
}

static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode,
				    int rxmode, u32 channel)
{
	u32 mtl_tx_op, mtl_rx_op, mtl_rx_int;

	/* Following code only done for channel 0, other channels not yet
	 * supported.
	 */
	mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));

	if (txmode == SF_DMA_MODE) {
		pr_debug("GMAC: enable TX store and forward mode\n");
		/* Transmit COE type 2 cannot be done in cut-through mode. */
		mtl_tx_op |= MTL_OP_MODE_TSF;
	} else {
		pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode);
		mtl_tx_op &= ~MTL_OP_MODE_TSF;
		mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
		/* Set the transmit threshold */
		if (txmode <= 32)
			mtl_tx_op |= MTL_OP_MODE_TTC_32;
		else if (txmode <= 64)
			mtl_tx_op |= MTL_OP_MODE_TTC_64;
		else if (txmode <= 96)
			mtl_tx_op |= MTL_OP_MODE_TTC_96;
		else if (txmode <= 128)
			mtl_tx_op |= MTL_OP_MODE_TTC_128;
		else if (txmode <= 192)
			mtl_tx_op |= MTL_OP_MODE_TTC_192;
		else if (txmode <= 256)
			mtl_tx_op |= MTL_OP_MODE_TTC_256;
		else if (txmode <= 384)
			mtl_tx_op |= MTL_OP_MODE_TTC_384;
		else
			mtl_tx_op |= MTL_OP_MODE_TTC_512;
	}
	/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
	 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
	 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
	 * with reset values: TXQEN off, TQS 256 bytes.
	 *
	 * Write the bits in both cases, since it will have no effect when RO.
	 * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might
	 * be RO, however, writing the whole TQS field will result in a value
	 * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1.
	 */
	mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK;
	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));

	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));

	if (rxmode == SF_DMA_MODE) {
		pr_debug("GMAC: enable RX store and forward mode\n");
		mtl_rx_op |= MTL_OP_MODE_RSF;
	} else {
		pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode);
		mtl_rx_op &= ~MTL_OP_MODE_RSF;
		mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
		if (rxmode <= 32)
			mtl_rx_op |= MTL_OP_MODE_RTC_32;
		else if (rxmode <= 64)
			mtl_rx_op |= MTL_OP_MODE_RTC_64;
		else if (rxmode <= 96)
			mtl_rx_op |= MTL_OP_MODE_RTC_96;
		else
			mtl_rx_op |= MTL_OP_MODE_RTC_128;
	}

	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));

	/* Enable MTL RX overflow */
	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
	writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
	       ioaddr + MTL_CHAN_INT_CTRL(channel));
}

static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode,
				      int rxmode, int rxfifosz)
{
	/* Only Channel 0 is actually configured and used */
	dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0);
}

static void dwmac4_get_hw_feature(void __iomem *ioaddr,
				  struct dma_features *dma_cap)
{
	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);

	/*  MAC HW feature0 */
	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
	dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
	dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
	dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
	/* MMC */
	dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
	/* IEEE 1588-2008 */
	dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
	/* TX and RX csum */
	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
	dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;

	/* MAC HW feature1 */
	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
	/* MAC HW feature2 */
	hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
	/* TX and RX number of channels */
	dma_cap->number_rx_channel =
		((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
	dma_cap->number_tx_channel =
		((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;

	/* IEEE 1588-2002 */
	dma_cap->time_stamp = 0;
}

/* Enable/disable TSO feature and set MSS */
static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
{
	u32 value;

	if (en) {
		/* enable TSO */
		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
		writel(value | DMA_CONTROL_TSE,
		       ioaddr + DMA_CHAN_TX_CONTROL(chan));
	} else {
		/* enable TSO */
		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
		writel(value & ~DMA_CONTROL_TSE,
		       ioaddr + DMA_CHAN_TX_CONTROL(chan));
	}
}

const struct stmmac_dma_ops dwmac4_dma_ops = {
	.reset = dwmac4_dma_reset,
	.init = dwmac4_dma_init,
	.axi = dwmac4_dma_axi,
	.dump_regs = dwmac4_dump_dma_regs,
	.dma_mode = dwmac4_dma_operation_mode,
	.enable_dma_irq = dwmac4_enable_dma_irq,
	.disable_dma_irq = dwmac4_disable_dma_irq,
	.start_tx = dwmac4_dma_start_tx,
	.stop_tx = dwmac4_dma_stop_tx,
	.start_rx = dwmac4_dma_start_rx,
	.stop_rx = dwmac4_dma_stop_rx,
	.dma_interrupt = dwmac4_dma_interrupt,
	.get_hw_feature = dwmac4_get_hw_feature,
	.rx_watchdog = dwmac4_rx_watchdog,
	.set_rx_ring_len = dwmac4_set_rx_ring_len,
	.set_tx_ring_len = dwmac4_set_tx_ring_len,
	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
	.enable_tso = dwmac4_enable_tso,
};

const struct stmmac_dma_ops dwmac410_dma_ops = {
	.reset = dwmac4_dma_reset,
	.init = dwmac4_dma_init,
	.axi = dwmac4_dma_axi,
	.dump_regs = dwmac4_dump_dma_regs,
	.dma_mode = dwmac4_dma_operation_mode,
	.enable_dma_irq = dwmac410_enable_dma_irq,
	.disable_dma_irq = dwmac4_disable_dma_irq,
	.start_tx = dwmac4_dma_start_tx,
	.stop_tx = dwmac4_dma_stop_tx,
	.start_rx = dwmac4_dma_start_rx,
	.stop_rx = dwmac4_dma_stop_rx,
	.dma_interrupt = dwmac4_dma_interrupt,
	.get_hw_feature = dwmac4_get_hw_feature,
	.rx_watchdog = dwmac4_rx_watchdog,
	.set_rx_ring_len = dwmac4_set_rx_ring_len,
	.set_tx_ring_len = dwmac4_set_tx_ring_len,
	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
	.enable_tso = dwmac4_enable_tso,
};
Commit	Line	Data
48863ce5 AT	1	/*
	2	* This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
	3	* DWC Ether MAC version 4.xx has been used for developing this code.
	4	*
	5	* This contains the functions to handle the dma.
	6	*
	7	* Copyright (C) 2015 STMicroelectronics Ltd
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms and conditions of the GNU General Public License,
	11	* version 2, as published by the Free Software Foundation.
	12	*
	13	* Author: Alexandre Torgue <alexandre.torgue@st.com>
	14	*/
	15
	16	#include <linux/io.h>
	17	#include "dwmac4.h"
	18	#include "dwmac4_dma.h"
	19
	20	static void dwmac4_dma_axi(void __iomem ioaddr, struct stmmac_axi axi)
	21	{
	22	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
	23	int i;
	24
	25	pr_info("dwmac4: Master AXI performs %s burst length\n",
	26	(value & DMA_SYS_BUS_FB) ? "fixed" : "any");
	27
	28	if (axi->axi_lpi_en)
	29	value \|= DMA_AXI_EN_LPI;
	30	if (axi->axi_xit_frm)
	31	value \|= DMA_AXI_LPI_XIT_FRM;
	32
6b3374cb	33	value &= ~DMA_AXI_WR_OSR_LMT;
48863ce5 AT	34	value \|= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
	35	DMA_AXI_WR_OSR_LMT_SHIFT;
	36
6b3374cb	37	value &= ~DMA_AXI_RD_OSR_LMT;
48863ce5 AT	38	value \|= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
	39	DMA_AXI_RD_OSR_LMT_SHIFT;
	40
	41	/* Depending on the UNDEF bit the Master AXI will perform any burst
	42	* length according to the BLEN programmed (by default all BLEN are
	43	* set).
	44	*/
	45	for (i = 0; i < AXI_BLEN; i++) {
	46	switch (axi->axi_blen[i]) {
	47	case 256:
	48	value \|= DMA_AXI_BLEN256;
	49	break;
	50	case 128:
	51	value \|= DMA_AXI_BLEN128;
	52	break;
	53	case 64:
	54	value \|= DMA_AXI_BLEN64;
	55	break;
	56	case 32:
	57	value \|= DMA_AXI_BLEN32;
	58	break;
	59	case 16:
	60	value \|= DMA_AXI_BLEN16;
	61	break;
	62	case 8:
	63	value \|= DMA_AXI_BLEN8;
	64	break;
	65	case 4:
	66	value \|= DMA_AXI_BLEN4;
	67	break;
	68	}
	69	}
	70
	71	writel(value, ioaddr + DMA_SYS_BUS_MODE);
	72	}
	73
	74	static void dwmac4_dma_init_channel(void __iomem *ioaddr, int pbl,
	75	u32 dma_tx_phy, u32 dma_rx_phy,
	76	u32 channel)
	77	{
	78	u32 value;
	79
	80	/* set PBL for each channels. Currently we affect same configuration
	81	* on each channel
	82	*/
	83	value = readl(ioaddr + DMA_CHAN_CONTROL(channel));
	84	value = value \| DMA_BUS_MODE_PBL;
	85	writel(value, ioaddr + DMA_CHAN_CONTROL(channel));
	86
	87	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
	88	value = value \| (pbl << DMA_BUS_MODE_PBL_SHIFT);
	89	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel));
	90
	91	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
	92	value = value \| (pbl << DMA_BUS_MODE_RPBL_SHIFT);
	93	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel));
	94
	95	/* Mask interrupts by writing to CSR7 */
	96	writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel));
	97
	98	writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
	99	writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
	100	}
	101
102	static void dwmac4_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
103	int aal, u32 dma_tx, u32 dma_rx, int atds)
104	{
105	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
106	int i;
107
108	/* Set the Fixed burst mode */
109	if (fb)
110	value \|= DMA_SYS_BUS_FB;
111
112	/* Mixed Burst has no effect when fb is set */
113	if (mb)
114	value \|= DMA_SYS_BUS_MB;
115
116	if (aal)
117	value \|= DMA_SYS_BUS_AAL;
118
119	writel(value, ioaddr + DMA_SYS_BUS_MODE);
120
121	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
122	dwmac4_dma_init_channel(ioaddr, pbl, dma_tx, dma_rx, i);
123	}
124
125	static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel)
126	{
127	pr_debug(" Channel %d\n", channel);
128	pr_debug("\tDMA_CHAN_CONTROL, offset: 0x%x, val: 0x%x\n", 0,
129	readl(ioaddr + DMA_CHAN_CONTROL(channel)));
130	pr_debug("\tDMA_CHAN_TX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x4,
131	readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)));
132	pr_debug("\tDMA_CHAN_RX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x8,
133	readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)));
134	pr_debug("\tDMA_CHAN_TX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x14,
135	readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)));
136	pr_debug("\tDMA_CHAN_RX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x1c,
137	readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)));
138	pr_debug("\tDMA_CHAN_TX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x20,
139	readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)));
140	pr_debug("\tDMA_CHAN_RX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x28,
141	readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)));
142	pr_debug("\tDMA_CHAN_TX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x2c,
143	readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)));
144	pr_debug("\tDMA_CHAN_RX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x30,
145	readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)));
146	pr_debug("\tDMA_CHAN_INTR_ENA, offset: 0x%x, val: 0x%x\n", 0x34,
147	readl(ioaddr + DMA_CHAN_INTR_ENA(channel)));
148	pr_debug("\tDMA_CHAN_RX_WATCHDOG, offset: 0x%x, val: 0x%x\n", 0x38,
149	readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)));
150	pr_debug("\tDMA_CHAN_SLOT_CTRL_STATUS, offset: 0x%x, val: 0x%x\n", 0x3c,
151	readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)));
152	pr_debug("\tDMA_CHAN_CUR_TX_DESC, offset: 0x%x, val: 0x%x\n", 0x44,
153	readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)));
154	pr_debug("\tDMA_CHAN_CUR_RX_DESC, offset: 0x%x, val: 0x%x\n", 0x4c,
155	readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)));
156	pr_debug("\tDMA_CHAN_CUR_TX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x54,
157	readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)));
158	pr_debug("\tDMA_CHAN_CUR_RX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x5c,
159	readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)));
160	pr_debug("\tDMA_CHAN_STATUS, offset: 0x%x, val: 0x%x\n", 0x60,
161	readl(ioaddr + DMA_CHAN_STATUS(channel)));
162	}
163
164	static void dwmac4_dump_dma_regs(void __iomem *ioaddr)
165	{
166	int i;
167
168	pr_debug(" GMAC4 DMA registers\n");
169
170	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
171	_dwmac4_dump_dma_regs(ioaddr, i);
172	}
173
174	static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt)
175	{
176	int i;
177
178	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
179	writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i));
180	}
181
182	static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode,
183	int rxmode, u32 channel)
184	{
185	u32 mtl_tx_op, mtl_rx_op, mtl_rx_int;
186
187	/* Following code only done for channel 0, other channels not yet
188	* supported.
189	*/
190	mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
191
192	if (txmode == SF_DMA_MODE) {
193	pr_debug("GMAC: enable TX store and forward mode\n");
194	/* Transmit COE type 2 cannot be done in cut-through mode. */
195	mtl_tx_op \|= MTL_OP_MODE_TSF;
196	} else {
197	pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode);
198	mtl_tx_op &= ~MTL_OP_MODE_TSF;
199	mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
200	/* Set the transmit threshold */
201	if (txmode <= 32)
202	mtl_tx_op \|= MTL_OP_MODE_TTC_32;
203	else if (txmode <= 64)
204	mtl_tx_op \|= MTL_OP_MODE_TTC_64;
205	else if (txmode <= 96)
206	mtl_tx_op \|= MTL_OP_MODE_TTC_96;
207	else if (txmode <= 128)
208	mtl_tx_op \|= MTL_OP_MODE_TTC_128;
209	else if (txmode <= 192)
210	mtl_tx_op \|= MTL_OP_MODE_TTC_192;
211	else if (txmode <= 256)
212	mtl_tx_op \|= MTL_OP_MODE_TTC_256;
213	else if (txmode <= 384)
214	mtl_tx_op \|= MTL_OP_MODE_TTC_384;
215	else
216	mtl_tx_op \|= MTL_OP_MODE_TTC_512;
217	}
436feafe NC	218	/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
	219	* with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
	220	* For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
	221	* with reset values: TXQEN off, TQS 256 bytes.
	222	*
	223	* Write the bits in both cases, since it will have no effect when RO.
	224	* For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might
	225	* be RO, however, writing the whole TQS field will result in a value
	226	* equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1.
	227	*/
	228	mtl_tx_op \|= MTL_OP_MODE_TXQEN \| MTL_OP_MODE_TQS_MASK;
48863ce5 AT	229	writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
	230
	231	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
	232
	233	if (rxmode == SF_DMA_MODE) {
	234	pr_debug("GMAC: enable RX store and forward mode\n");
	235	mtl_rx_op \|= MTL_OP_MODE_RSF;
	236	} else {
	237	pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode);
	238	mtl_rx_op &= ~MTL_OP_MODE_RSF;
	239	mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
	240	if (rxmode <= 32)
	241	mtl_rx_op \|= MTL_OP_MODE_RTC_32;
	242	else if (rxmode <= 64)
	243	mtl_rx_op \|= MTL_OP_MODE_RTC_64;
	244	else if (rxmode <= 96)
	245	mtl_rx_op \|= MTL_OP_MODE_RTC_96;
	246	else
	247	mtl_rx_op \|= MTL_OP_MODE_RTC_128;
	248	}
	249
	250	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
	251
	252	/* Enable MTL RX overflow */
	253	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
	254	writel(mtl_rx_int \| MTL_RX_OVERFLOW_INT_EN,
	255	ioaddr + MTL_CHAN_INT_CTRL(channel));
	256	}
	257
	258	static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode,
	259	int rxmode, int rxfifosz)
	260	{
	261	/* Only Channel 0 is actually configured and used */
	262	dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0);
	263	}
	264
	265	static void dwmac4_get_hw_feature(void __iomem *ioaddr,
	266	struct dma_features *dma_cap)
	267	{
	268	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
	269
	270	/* MAC HW feature0 */
	271	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
	272	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
	273	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
	274	dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
	275	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
	276	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
	277	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
	278	dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
	279	dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
	280	/* MMC */
	281	dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
	282	/* IEEE 1588-2008 */
	283	dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
	284	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	285	dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
	286	/* TX and RX csum */
	287	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
	288	dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
	289
	290	/* MAC HW feature1 */
	291	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
	292	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
293	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
294	/* MAC HW feature2 */
295	hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
296	/* TX and RX number of channels */
297	dma_cap->number_rx_channel =
298	((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
299	dma_cap->number_tx_channel =
300	((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
301
302	/* IEEE 1588-2002 */
303	dma_cap->time_stamp = 0;
304	}
305
306	/* Enable/disable TSO feature and set MSS */
307	static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
308	{
309	u32 value;
310
311	if (en) {
312	/* enable TSO */
313	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
314	writel(value \| DMA_CONTROL_TSE,
315	ioaddr + DMA_CHAN_TX_CONTROL(chan));
316	} else {
317	/* enable TSO */
318	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
319	writel(value & ~DMA_CONTROL_TSE,
320	ioaddr + DMA_CHAN_TX_CONTROL(chan));
321	}
322	}
323
324	const struct stmmac_dma_ops dwmac4_dma_ops = {
325	.reset = dwmac4_dma_reset,
326	.init = dwmac4_dma_init,
327	.axi = dwmac4_dma_axi,
328	.dump_regs = dwmac4_dump_dma_regs,
329	.dma_mode = dwmac4_dma_operation_mode,
330	.enable_dma_irq = dwmac4_enable_dma_irq,
331	.disable_dma_irq = dwmac4_disable_dma_irq,
332	.start_tx = dwmac4_dma_start_tx,
333	.stop_tx = dwmac4_dma_stop_tx,
334	.start_rx = dwmac4_dma_start_rx,
335	.stop_rx = dwmac4_dma_stop_rx,
336	.dma_interrupt = dwmac4_dma_interrupt,
337	.get_hw_feature = dwmac4_get_hw_feature,
338	.rx_watchdog = dwmac4_rx_watchdog,
339	.set_rx_ring_len = dwmac4_set_rx_ring_len,
340	.set_tx_ring_len = dwmac4_set_tx_ring_len,
341	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
342	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
343	.enable_tso = dwmac4_enable_tso,
344	};
345
346	const struct stmmac_dma_ops dwmac410_dma_ops = {
347	.reset = dwmac4_dma_reset,
348	.init = dwmac4_dma_init,
349	.axi = dwmac4_dma_axi,
350	.dump_regs = dwmac4_dump_dma_regs,
351	.dma_mode = dwmac4_dma_operation_mode,
352	.enable_dma_irq = dwmac410_enable_dma_irq,
353	.disable_dma_irq = dwmac4_disable_dma_irq,
354	.start_tx = dwmac4_dma_start_tx,
355	.stop_tx = dwmac4_dma_stop_tx,
356	.start_rx = dwmac4_dma_start_rx,
357	.stop_rx = dwmac4_dma_stop_rx,
358	.dma_interrupt = dwmac4_dma_interrupt,
359	.get_hw_feature = dwmac4_get_hw_feature,
360	.rx_watchdog = dwmac4_rx_watchdog,
361	.set_rx_ring_len = dwmac4_set_rx_ring_len,
362	.set_tx_ring_len = dwmac4_set_tx_ring_len,
363	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
364	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
365	.enable_tso = dwmac4_enable_tso,
366	};