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Merge branches 'acpi-ec', 'acpi-video', 'acpi-button' and 'acpi-thermal'
[linux-2.6-block.git] / drivers / net / ethernet / smsc / smsc911x.c
CommitLineData
fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
0ab75ae8 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
fd9abb3d
SG		 18 *
19 ***************************************************************************
20 * Rewritten, heavily based on smsc911x simple driver by SMSC.
21 * Partly uses io macros from smc91x.c by Nicolas Pitre
22 *
23 * Supported devices:
24 * LAN9115, LAN9116, LAN9117, LAN9118
25 * LAN9215, LAN9216, LAN9217, LAN9218
26 * LAN9210, LAN9211
27 * LAN9220, LAN9221
28c21379 28 * LAN89218
fd9abb3d
SG		 29 *
30 */
31
dffc6b24
JP		 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
fd9abb3d 34#include <linux/crc32.h>
b6c23019 35#include <linux/clk.h>
fd9abb3d
SG		 36#include <linux/delay.h>
37#include <linux/errno.h>
38#include <linux/etherdevice.h>
39#include <linux/ethtool.h>
40#include <linux/init.h>
a6b7a407 41#include <linux/interrupt.h>
fd9abb3d
SG		 42#include <linux/ioport.h>
43#include <linux/kernel.h>
44#include <linux/module.h>
45#include <linux/netdevice.h>
46#include <linux/platform_device.h>
c7e963f6 47#include <linux/regulator/consumer.h>
fd9abb3d 48#include <linux/sched.h>
fd9abb3d 49#include <linux/timer.h>
fd9abb3d
SG		 50#include <linux/bug.h>
51#include <linux/bitops.h>
52#include <linux/irq.h>
53#include <linux/io.h>
833cc67c 54#include <linux/swab.h>
fd9abb3d
SG		 55#include <linux/phy.h>
56#include <linux/smsc911x.h>
6cb87823 57#include <linux/device.h>
79f88ee9
SG		 58#include <linux/of.h>
59#include <linux/of_device.h>
60#include <linux/of_gpio.h>
61#include <linux/of_net.h>
0b50dc4f 62#include <linux/acpi.h>
3a611e26 63#include <linux/pm_runtime.h>
0b50dc4f 64#include <linux/property.h>
3a611e26 65
fd9abb3d
SG		 66#include "smsc911x.h"
67
68#define SMSC_CHIPNAME "smsc911x"
69#define SMSC_MDIONAME "smsc911x-mdio"
70#define SMSC_DRV_VERSION "2008-10-21"
71
72MODULE_LICENSE("GPL");
73MODULE_VERSION(SMSC_DRV_VERSION);
62038e4a 74MODULE_ALIAS("platform:smsc911x");
fd9abb3d
SG		 75
76#if USE_DEBUG > 0
77static int debug = 16;
78#else
79static int debug = 3;
80#endif
81
82module_param(debug, int, 0);
83MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
84
c326de88
MP		 85struct smsc911x_data;
86
87struct smsc911x_ops {
88 u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
89 void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
90 void (*rx_readfifo)(struct smsc911x_data *pdata,
91 unsigned int *buf, unsigned int wordcount);
92 void (*tx_writefifo)(struct smsc911x_data *pdata,
93 unsigned int *buf, unsigned int wordcount);
94};
95
c7e963f6
RM		 96#define SMSC911X_NUM_SUPPLIES 2
97
fd9abb3d
SG		 98struct smsc911x_data {
99 void __iomem *ioaddr;
100
101 unsigned int idrev;
102
103 /* used to decide which workarounds apply */
104 unsigned int generation;
105
106 /* device configuration (copied from platform_data during probe) */
2107fb8b 107 struct smsc911x_platform_config config;
fd9abb3d
SG		 108
109 /* This needs to be acquired before calling any of below:
110 * smsc911x_mac_read(), smsc911x_mac_write()
111 */
112 spinlock_t mac_lock;
113
492c5d94 114 /* spinlock to ensure register accesses are serialised */
fd9abb3d 115 spinlock_t dev_lock;
fd9abb3d
SG		 116
117 struct phy_device *phy_dev;
118 struct mii_bus *mii_bus;
fd9abb3d
SG		 119 unsigned int using_extphy;
120 int last_duplex;
121 int last_carrier;
122
123 u32 msg_enable;
124 unsigned int gpio_setting;
125 unsigned int gpio_orig_setting;
126 struct net_device *dev;
127 struct napi_struct napi;
128
129 unsigned int software_irq_signal;
130
131#ifdef USE_PHY_WORK_AROUND
132#define MIN_PACKET_SIZE (64)
133 char loopback_tx_pkt[MIN_PACKET_SIZE];
134 char loopback_rx_pkt[MIN_PACKET_SIZE];
135 unsigned int resetcount;
136#endif
137
138 /* Members for Multicast filter workaround */
139 unsigned int multicast_update_pending;
140 unsigned int set_bits_mask;
141 unsigned int clear_bits_mask;
142 unsigned int hashhi;
143 unsigned int hashlo;
c326de88
MP		 144
145 /* register access functions */
146 const struct smsc911x_ops *ops;
c7e963f6
RM		 147
148 /* regulators */
149 struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES];
b6c23019
LJ		 150
151 /* clock */
152 struct clk *clk;
fd9abb3d
SG		 153};
154
c326de88
MP		 155/* Easy access to information */
156#define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
157
492c5d94 158static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
fd9abb3d 159{
2107fb8b
SG		 160 if (pdata->config.flags & SMSC911X_USE_32BIT)
161 return readl(pdata->ioaddr + reg);
162
492c5d94
CM		 163 if (pdata->config.flags & SMSC911X_USE_16BIT)
164 return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
2107fb8b 165 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
fd9abb3d 166
2107fb8b 167 BUG();
702403af 168 return 0;
fd9abb3d
SG		 169}
170
c326de88
MP		 171static inline u32
172__smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
173{
174 if (pdata->config.flags & SMSC911X_USE_32BIT)
175 return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
176
177 if (pdata->config.flags & SMSC911X_USE_16BIT)
178 return (readw(pdata->ioaddr +
179 __smsc_shift(pdata, reg)) & 0xFFFF) |
180 ((readw(pdata->ioaddr +
181 __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
182
183 BUG();
184 return 0;
185}
186
492c5d94
CM		 187static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
188{
189 u32 data;
190 unsigned long flags;
191
192 spin_lock_irqsave(&pdata->dev_lock, flags);
c326de88 193 data = pdata->ops->reg_read(pdata, reg);
492c5d94
CM		 194 spin_unlock_irqrestore(&pdata->dev_lock, flags);
195
196 return data;
197}
198
199static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
200 u32 val)
fd9abb3d 201{
2107fb8b
SG		 202 if (pdata->config.flags & SMSC911X_USE_32BIT) {
203 writel(val, pdata->ioaddr + reg);
204 return;
205 }
206
207 if (pdata->config.flags & SMSC911X_USE_16BIT) {
2107fb8b
SG		 208 writew(val & 0xFFFF, pdata->ioaddr + reg);
209 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
2107fb8b
SG		 210 return;
211 }
fd9abb3d 212
2107fb8b 213 BUG();
fd9abb3d
SG		 214}
215
c326de88
MP		 216static inline void
217__smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
218{
219 if (pdata->config.flags & SMSC911X_USE_32BIT) {
220 writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
221 return;
222 }
223
224 if (pdata->config.flags & SMSC911X_USE_16BIT) {
225 writew(val & 0xFFFF,
226 pdata->ioaddr + __smsc_shift(pdata, reg));
227 writew((val >> 16) & 0xFFFF,
228 pdata->ioaddr + __smsc_shift(pdata, reg + 2));
229 return;
230 }
231
232 BUG();
233}
234
492c5d94
CM		 235static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
236 u32 val)
237{
238 unsigned long flags;
239
240 spin_lock_irqsave(&pdata->dev_lock, flags);
c326de88 241 pdata->ops->reg_write(pdata, reg, val);
492c5d94
CM		 242 spin_unlock_irqrestore(&pdata->dev_lock, flags);
243}
244
fd9abb3d
SG		 245/* Writes a packet to the TX_DATA_FIFO */
246static inline void
247smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
248 unsigned int wordcount)
249{
492c5d94
CM		 250 unsigned long flags;
251
252 spin_lock_irqsave(&pdata->dev_lock, flags);
253
833cc67c
MD		 254 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
255 while (wordcount--)
492c5d94
CM		 256 __smsc911x_reg_write(pdata, TX_DATA_FIFO,
257 swab32(*buf++));
258 goto out;
833cc67c
MD		 259 }
260
2107fb8b 261 if (pdata->config.flags & SMSC911X_USE_32BIT) {
2925f6c0 262 iowrite32_rep(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
492c5d94 263 goto out;
2107fb8b
SG		 264 }
265
266 if (pdata->config.flags & SMSC911X_USE_16BIT) {
267 while (wordcount--)
492c5d94
CM		 268 __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
269 goto out;
2107fb8b
SG		 270 }
271
272 BUG();
492c5d94
CM		 273out:
274 spin_unlock_irqrestore(&pdata->dev_lock, flags);
fd9abb3d
SG		 275}
276
c326de88
MP		 277/* Writes a packet to the TX_DATA_FIFO - shifted version */
278static inline void
279smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
280 unsigned int wordcount)
281{
282 unsigned long flags;
283
284 spin_lock_irqsave(&pdata->dev_lock, flags);
285
286 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
287 while (wordcount--)
288 __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
289 swab32(*buf++));
290 goto out;
291 }
292
293 if (pdata->config.flags & SMSC911X_USE_32BIT) {
2925f6c0 294 iowrite32_rep(pdata->ioaddr + __smsc_shift(pdata,
c326de88
MP		 295 TX_DATA_FIFO), buf, wordcount);
296 goto out;
297 }
298
299 if (pdata->config.flags & SMSC911X_USE_16BIT) {
300 while (wordcount--)
301 __smsc911x_reg_write_shift(pdata,
302 TX_DATA_FIFO, *buf++);
303 goto out;
304 }
305
306 BUG();
307out:
308 spin_unlock_irqrestore(&pdata->dev_lock, flags);
309}
310
fd9abb3d
SG		 311/* Reads a packet out of the RX_DATA_FIFO */
312static inline void
313smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
314 unsigned int wordcount)
315{
492c5d94
CM		 316 unsigned long flags;
317
318 spin_lock_irqsave(&pdata->dev_lock, flags);
319
833cc67c
MD		 320 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
321 while (wordcount--)
492c5d94
CM		 322 *buf++ = swab32(__smsc911x_reg_read(pdata,
323 RX_DATA_FIFO));
324 goto out;
833cc67c
MD		 325 }
326
2107fb8b 327 if (pdata->config.flags & SMSC911X_USE_32BIT) {
2925f6c0 328 ioread32_rep(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
492c5d94 329 goto out;
2107fb8b 330 }
fd9abb3d 331
2107fb8b
SG		 332 if (pdata->config.flags & SMSC911X_USE_16BIT) {
333 while (wordcount--)
492c5d94
CM		 334 *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
335 goto out;
2107fb8b
SG		 336 }
337
338 BUG();
492c5d94
CM		 339out:
340 spin_unlock_irqrestore(&pdata->dev_lock, flags);
2107fb8b 341}
fd9abb3d 342
c326de88
MP		 343/* Reads a packet out of the RX_DATA_FIFO - shifted version */
344static inline void
345smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
346 unsigned int wordcount)
347{
348 unsigned long flags;
349
350 spin_lock_irqsave(&pdata->dev_lock, flags);
351
352 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
353 while (wordcount--)
354 *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
355 RX_DATA_FIFO));
356 goto out;
357 }
358
359 if (pdata->config.flags & SMSC911X_USE_32BIT) {
2925f6c0 360 ioread32_rep(pdata->ioaddr + __smsc_shift(pdata,
c326de88
MP		 361 RX_DATA_FIFO), buf, wordcount);
362 goto out;
363 }
364
365 if (pdata->config.flags & SMSC911X_USE_16BIT) {
366 while (wordcount--)
367 *buf++ = __smsc911x_reg_read_shift(pdata,
368 RX_DATA_FIFO);
369 goto out;
370 }
371
372 BUG();
373out:
374 spin_unlock_irqrestore(&pdata->dev_lock, flags);
375}
376
c7e963f6 377/*
b6c23019 378 * enable regulator and clock resources.
c7e963f6
RM		 379 */
380static int smsc911x_enable_resources(struct platform_device *pdev)
381{
382 struct net_device *ndev = platform_get_drvdata(pdev);
383 struct smsc911x_data *pdata = netdev_priv(ndev);
384 int ret = 0;
385
386 ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies),
387 pdata->supplies);
388 if (ret)
389 netdev_err(ndev, "failed to enable regulators %d\n",
390 ret);
b6c23019
LJ		 391
392 if (!IS_ERR(pdata->clk)) {
393 ret = clk_prepare_enable(pdata->clk);
394 if (ret < 0)
395 netdev_err(ndev, "failed to enable clock %d\n", ret);
396 }
397
c7e963f6
RM		 398 return ret;
399}
400
401/*
402 * disable resources, currently just regulators.
403 */
404static int smsc911x_disable_resources(struct platform_device *pdev)
405{
406 struct net_device *ndev = platform_get_drvdata(pdev);
407 struct smsc911x_data *pdata = netdev_priv(ndev);
408 int ret = 0;
409
410 ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies),
411 pdata->supplies);
b6c23019
LJ		 412
413 if (!IS_ERR(pdata->clk))
414 clk_disable_unprepare(pdata->clk);
415
c7e963f6
RM		 416 return ret;
417}
418
419/*
420 * Request resources, currently just regulators.
421 *
422 * The SMSC911x has two power pins: vddvario and vdd33a, in designs where
423 * these are not always-on we need to request regulators to be turned on
424 * before we can try to access the device registers.
425 */
426static int smsc911x_request_resources(struct platform_device *pdev)
427{
428 struct net_device *ndev = platform_get_drvdata(pdev);
429 struct smsc911x_data *pdata = netdev_priv(ndev);
430 int ret = 0;
431
432 /* Request regulators */
433 pdata->supplies[0].supply = "vdd33a";
434 pdata->supplies[1].supply = "vddvario";
435 ret = regulator_bulk_get(&pdev->dev,
436 ARRAY_SIZE(pdata->supplies),
437 pdata->supplies);
438 if (ret)
439 netdev_err(ndev, "couldn't get regulators %d\n",
440 ret);
b6c23019
LJ		 441
442 /* Request clock */
443 pdata->clk = clk_get(&pdev->dev, NULL);
444 if (IS_ERR(pdata->clk))
1e87af97
FE		 445 dev_dbg(&pdev->dev, "couldn't get clock %li\n",
446 PTR_ERR(pdata->clk));
b6c23019 447
c7e963f6
RM		 448 return ret;
449}
450
451/*
452 * Free resources, currently just regulators.
453 *
454 */
455static void smsc911x_free_resources(struct platform_device *pdev)
456{
457 struct net_device *ndev = platform_get_drvdata(pdev);
458 struct smsc911x_data *pdata = netdev_priv(ndev);
459
460 /* Free regulators */
461 regulator_bulk_free(ARRAY_SIZE(pdata->supplies),
462 pdata->supplies);
b6c23019
LJ		 463
464 /* Free clock */
465 if (!IS_ERR(pdata->clk)) {
466 clk_put(pdata->clk);
467 pdata->clk = NULL;
468 }
c7e963f6
RM		 469}
470
fd9abb3d
SG		 471/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
472 * and smsc911x_mac_write, so assumes mac_lock is held */
473static int smsc911x_mac_complete(struct smsc911x_data *pdata)
474{
475 int i;
476 u32 val;
477
478 SMSC_ASSERT_MAC_LOCK(pdata);
479
480 for (i = 0; i < 40; i++) {
481 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
482 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
483 return 0;
484 }
dffc6b24
JP		 485 SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
486 "MAC_CSR_CMD: 0x%08X", val);
fd9abb3d
SG		 487 return -EIO;
488}
489
490/* Fetches a MAC register value. Assumes mac_lock is acquired */
491static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
492{
493 unsigned int temp;
494
495 SMSC_ASSERT_MAC_LOCK(pdata);
496
497 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
498 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
dffc6b24 499 SMSC_WARN(pdata, hw, "MAC busy at entry");
fd9abb3d
SG		 500 return 0xFFFFFFFF;
501 }
502
503 /* Send the MAC cmd */
504 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
505 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
506
507 /* Workaround for hardware read-after-write restriction */
508 temp = smsc911x_reg_read(pdata, BYTE_TEST);
509
510 /* Wait for the read to complete */
511 if (likely(smsc911x_mac_complete(pdata) == 0))
512 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
513
dffc6b24 514 SMSC_WARN(pdata, hw, "MAC busy after read");
fd9abb3d
SG		 515 return 0xFFFFFFFF;
516}
517
518/* Set a mac register, mac_lock must be acquired before calling */
519static void smsc911x_mac_write(struct smsc911x_data *pdata,
520 unsigned int offset, u32 val)
521{
522 unsigned int temp;
523
524 SMSC_ASSERT_MAC_LOCK(pdata);
525
526 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
527 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
dffc6b24
JP		 528 SMSC_WARN(pdata, hw,
529 "smsc911x_mac_write failed, MAC busy at entry");
fd9abb3d
SG		 530 return;
531 }
532
533 /* Send data to write */
534 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
535
536 /* Write the actual data */
537 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
538 MAC_CSR_CMD_CSR_BUSY_));
539
540 /* Workaround for hardware read-after-write restriction */
541 temp = smsc911x_reg_read(pdata, BYTE_TEST);
542
543 /* Wait for the write to complete */
544 if (likely(smsc911x_mac_complete(pdata) == 0))
545 return;
546
dffc6b24 547 SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
fd9abb3d
SG		 548}
549
550/* Get a phy register */
551static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
552{
553 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
554 unsigned long flags;
555 unsigned int addr;
556 int i, reg;
557
558 spin_lock_irqsave(&pdata->mac_lock, flags);
559
560 /* Confirm MII not busy */
561 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
dffc6b24 562 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
fd9abb3d
SG		 563 reg = -EIO;
564 goto out;
565 }
566
567 /* Set the address, index & direction (read from PHY) */
568 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
569 smsc911x_mac_write(pdata, MII_ACC, addr);
570
571 /* Wait for read to complete w/ timeout */
572 for (i = 0; i < 100; i++)
573 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
574 reg = smsc911x_mac_read(pdata, MII_DATA);
575 goto out;
576 }
577
dffc6b24 578 SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
fd9abb3d
SG		 579 reg = -EIO;
580
581out:
582 spin_unlock_irqrestore(&pdata->mac_lock, flags);
583 return reg;
584}
585
586/* Set a phy register */
587static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
588 u16 val)
589{
590 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
591 unsigned long flags;
592 unsigned int addr;
593 int i, reg;
594
595 spin_lock_irqsave(&pdata->mac_lock, flags);
596
597 /* Confirm MII not busy */
598 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
dffc6b24 599 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
fd9abb3d
SG		 600 reg = -EIO;
601 goto out;
602 }
603
604 /* Put the data to write in the MAC */
605 smsc911x_mac_write(pdata, MII_DATA, val);
606
607 /* Set the address, index & direction (write to PHY) */
608 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
609 MII_ACC_MII_WRITE_;
610 smsc911x_mac_write(pdata, MII_ACC, addr);
611
612 /* Wait for write to complete w/ timeout */
613 for (i = 0; i < 100; i++)
614 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
615 reg = 0;
616 goto out;
617 }
618
dffc6b24 619 SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
fd9abb3d
SG		 620 reg = -EIO;
621
622out:
623 spin_unlock_irqrestore(&pdata->mac_lock, flags);
624 return reg;
625}
626
d23f028a
SG		 627/* Switch to external phy. Assumes tx and rx are stopped. */
628static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 629{
630 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
631
d23f028a
SG		 632 /* Disable phy clocks to the MAC */
633 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
634 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
635 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
636 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 637
d23f028a
SG		 638 /* Switch to external phy */
639 hwcfg |= HW_CFG_EXT_PHY_EN_;
640 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 641
d23f028a
SG		 642 /* Enable phy clocks to the MAC */
643 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
644 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
645 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
646 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 647
d23f028a
SG		 648 hwcfg |= HW_CFG_SMI_SEL_;
649 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
650}
fd9abb3d 651
d23f028a
SG		 652/* Autodetects and enables external phy if present on supported chips.
653 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
654 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
655static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
656{
657 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 658
d23f028a 659 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
dffc6b24 660 SMSC_TRACE(pdata, hw, "Forcing internal PHY");
d23f028a
SG		 661 pdata->using_extphy = 0;
662 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
dffc6b24 663 SMSC_TRACE(pdata, hw, "Forcing external PHY");
d23f028a
SG		 664 smsc911x_phy_enable_external(pdata);
665 pdata->using_extphy = 1;
666 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
dffc6b24
JP		 667 SMSC_TRACE(pdata, hw,
668 "HW_CFG EXT_PHY_DET set, using external PHY");
d23f028a 669 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 670 pdata->using_extphy = 1;
671 } else {
dffc6b24
JP		 672 SMSC_TRACE(pdata, hw,
673 "HW_CFG EXT_PHY_DET clear, using internal PHY");
d23f028a 674 pdata->using_extphy = 0;
fd9abb3d 675 }
fd9abb3d
SG		 676}
677
678/* Fetches a tx status out of the status fifo */
679static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
680{
681 unsigned int result =
682 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
683
684 if (result != 0)
685 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
686
687 return result;
688}
689
690/* Fetches the next rx status */
691static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
692{
693 unsigned int result =
694 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
695
696 if (result != 0)
697 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
698
699 return result;
700}
701
702#ifdef USE_PHY_WORK_AROUND
703static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
704{
705 unsigned int tries;
706 u32 wrsz;
707 u32 rdsz;
708 ulong bufp;
709
710 for (tries = 0; tries < 10; tries++) {
711 unsigned int txcmd_a;
712 unsigned int txcmd_b;
713 unsigned int status;
714 unsigned int pktlength;
715 unsigned int i;
716
717 /* Zero-out rx packet memory */
718 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
719
720 /* Write tx packet to 118 */
721 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
722 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
723 txcmd_a |= MIN_PACKET_SIZE;
724
725 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
726
727 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
728 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
729
730 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
731 wrsz = MIN_PACKET_SIZE + 3;
732 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
733 wrsz >>= 2;
734
c326de88 735 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
fd9abb3d
SG		 736
737 /* Wait till transmit is done */
738 i = 60;
739 do {
740 udelay(5);
741 status = smsc911x_tx_get_txstatus(pdata);
742 } while ((i--) && (!status));
743
744 if (!status) {
dffc6b24
JP		 745 SMSC_WARN(pdata, hw,
746 "Failed to transmit during loopback test");
fd9abb3d
SG		 747 continue;
748 }
749 if (status & TX_STS_ES_) {
dffc6b24
JP		 750 SMSC_WARN(pdata, hw,
751 "Transmit encountered errors during loopback test");
fd9abb3d
SG		 752 continue;
753 }
754
755 /* Wait till receive is done */
756 i = 60;
757 do {
758 udelay(5);
759 status = smsc911x_rx_get_rxstatus(pdata);
760 } while ((i--) && (!status));
761
762 if (!status) {
dffc6b24
JP		 763 SMSC_WARN(pdata, hw,
764 "Failed to receive during loopback test");
fd9abb3d
SG		 765 continue;
766 }
767 if (status & RX_STS_ES_) {
dffc6b24
JP		 768 SMSC_WARN(pdata, hw,
769 "Receive encountered errors during loopback test");
fd9abb3d
SG		 770 continue;
771 }
772
773 pktlength = ((status & 0x3FFF0000UL) >> 16);
774 bufp = (ulong)pdata->loopback_rx_pkt;
775 rdsz = pktlength + 3;
776 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
777 rdsz >>= 2;
778
c326de88 779 pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
fd9abb3d
SG		 780
781 if (pktlength != (MIN_PACKET_SIZE + 4)) {
dffc6b24
JP		 782 SMSC_WARN(pdata, hw, "Unexpected packet size "
783 "during loop back test, size=%d, will retry",
784 pktlength);
fd9abb3d
SG		 785 } else {
786 unsigned int j;
787 int mismatch = 0;
788 for (j = 0; j < MIN_PACKET_SIZE; j++) {
789 if (pdata->loopback_tx_pkt[j]
790 != pdata->loopback_rx_pkt[j]) {
791 mismatch = 1;
792 break;
793 }
794 }
795 if (!mismatch) {
dffc6b24 796 SMSC_TRACE(pdata, hw, "Successfully verified "
fd9abb3d
SG		 797 "loopback packet");
798 return 0;
799 } else {
dffc6b24
JP		 800 SMSC_WARN(pdata, hw, "Data mismatch "
801 "during loop back test, will retry");
fd9abb3d
SG		 802 }
803 }
804 }
805
806 return -EIO;
807}
808
809static int smsc911x_phy_reset(struct smsc911x_data *pdata)
810{
fd9abb3d
SG		 811 unsigned int temp;
812 unsigned int i = 100000;
813
cd998ecd
PF		 814 temp = smsc911x_reg_read(pdata, PMT_CTRL);
815 smsc911x_reg_write(pdata, PMT_CTRL, temp | PMT_CTRL_PHY_RST_);
fd9abb3d
SG		 816 do {
817 msleep(1);
cd998ecd
PF		 818 temp = smsc911x_reg_read(pdata, PMT_CTRL);
819 } while ((i--) && (temp & PMT_CTRL_PHY_RST_));
fd9abb3d 820
cd998ecd 821 if (unlikely(temp & PMT_CTRL_PHY_RST_)) {
dffc6b24 822 SMSC_WARN(pdata, hw, "PHY reset failed to complete");
fd9abb3d
SG		 823 return -EIO;
824 }
825 /* Extra delay required because the phy may not be completed with
826 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
827 * enough delay but using 1ms here to be safe */
828 msleep(1);
829
830 return 0;
831}
832
833static int smsc911x_phy_loopbacktest(struct net_device *dev)
834{
835 struct smsc911x_data *pdata = netdev_priv(dev);
836 struct phy_device *phy_dev = pdata->phy_dev;
837 int result = -EIO;
838 unsigned int i, val;
839 unsigned long flags;
840
841 /* Initialise tx packet using broadcast destination address */
c7bf7169 842 eth_broadcast_addr(pdata->loopback_tx_pkt);
fd9abb3d
SG		 843
844 /* Use incrementing source address */
845 for (i = 6; i < 12; i++)
846 pdata->loopback_tx_pkt[i] = (char)i;
847
848 /* Set length type field */
849 pdata->loopback_tx_pkt[12] = 0x00;
850 pdata->loopback_tx_pkt[13] = 0x00;
851
852 for (i = 14; i < MIN_PACKET_SIZE; i++)
853 pdata->loopback_tx_pkt[i] = (char)i;
854
855 val = smsc911x_reg_read(pdata, HW_CFG);
856 val &= HW_CFG_TX_FIF_SZ_;
857 val |= HW_CFG_SF_;
858 smsc911x_reg_write(pdata, HW_CFG, val);
859
860 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
861 smsc911x_reg_write(pdata, RX_CFG,
862 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
863
864 for (i = 0; i < 10; i++) {
865 /* Set PHY to 10/FD, no ANEG, and loopback mode */
e5a03bfd
AL		 866 smsc911x_mii_write(phy_dev->mdio.bus, phy_dev->mdio.addr,
867 MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX);
fd9abb3d
SG		 868
869 /* Enable MAC tx/rx, FD */
870 spin_lock_irqsave(&pdata->mac_lock, flags);
871 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
872 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
873 spin_unlock_irqrestore(&pdata->mac_lock, flags);
874
875 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
876 result = 0;
877 break;
878 }
879 pdata->resetcount++;
880
881 /* Disable MAC rx */
882 spin_lock_irqsave(&pdata->mac_lock, flags);
883 smsc911x_mac_write(pdata, MAC_CR, 0);
884 spin_unlock_irqrestore(&pdata->mac_lock, flags);
885
886 smsc911x_phy_reset(pdata);
887 }
888
889 /* Disable MAC */
890 spin_lock_irqsave(&pdata->mac_lock, flags);
891 smsc911x_mac_write(pdata, MAC_CR, 0);
892 spin_unlock_irqrestore(&pdata->mac_lock, flags);
893
894 /* Cancel PHY loopback mode */
e5a03bfd 895 smsc911x_mii_write(phy_dev->mdio.bus, phy_dev->mdio.addr, MII_BMCR, 0);
fd9abb3d
SG		 896
897 smsc911x_reg_write(pdata, TX_CFG, 0);
898 smsc911x_reg_write(pdata, RX_CFG, 0);
899
900 return result;
901}
902#endif /* USE_PHY_WORK_AROUND */
903
fd9abb3d
SG		 904static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
905{
906 struct phy_device *phy_dev = pdata->phy_dev;
907 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
908 u32 flow;
909 unsigned long flags;
910
911 if (phy_dev->duplex == DUPLEX_FULL) {
912 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
913 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 914 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 915
916 if (cap & FLOW_CTRL_RX)
917 flow = 0xFFFF0002;
918 else
919 flow = 0;
920
921 if (cap & FLOW_CTRL_TX)
922 afc |= 0xF;
923 else
924 afc &= ~0xF;
925
dffc6b24
JP		 926 SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
927 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
928 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
fd9abb3d 929 } else {
dffc6b24 930 SMSC_TRACE(pdata, hw, "half duplex");
fd9abb3d
SG		 931 flow = 0;
932 afc |= 0xF;
933 }
934
935 spin_lock_irqsave(&pdata->mac_lock, flags);
936 smsc911x_mac_write(pdata, FLOW, flow);
937 spin_unlock_irqrestore(&pdata->mac_lock, flags);
938
939 smsc911x_reg_write(pdata, AFC_CFG, afc);
940}
941
942/* Update link mode if anything has changed. Called periodically when the
943 * PHY is in polling mode, even if nothing has changed. */
944static void smsc911x_phy_adjust_link(struct net_device *dev)
945{
946 struct smsc911x_data *pdata = netdev_priv(dev);
947 struct phy_device *phy_dev = pdata->phy_dev;
948 unsigned long flags;
949 int carrier;
950
951 if (phy_dev->duplex != pdata->last_duplex) {
952 unsigned int mac_cr;
dffc6b24 953 SMSC_TRACE(pdata, hw, "duplex state has changed");
fd9abb3d
SG		 954
955 spin_lock_irqsave(&pdata->mac_lock, flags);
956 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
957 if (phy_dev->duplex) {
dffc6b24
JP		 958 SMSC_TRACE(pdata, hw,
959 "configuring for full duplex mode");
fd9abb3d
SG		 960 mac_cr |= MAC_CR_FDPX_;
961 } else {
dffc6b24
JP		 962 SMSC_TRACE(pdata, hw,
963 "configuring for half duplex mode");
fd9abb3d
SG		 964 mac_cr &= ~MAC_CR_FDPX_;
965 }
966 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
967 spin_unlock_irqrestore(&pdata->mac_lock, flags);
968
969 smsc911x_phy_update_flowcontrol(pdata);
970 pdata->last_duplex = phy_dev->duplex;
971 }
972
973 carrier = netif_carrier_ok(dev);
974 if (carrier != pdata->last_carrier) {
dffc6b24 975 SMSC_TRACE(pdata, hw, "carrier state has changed");
fd9abb3d 976 if (carrier) {
dffc6b24 977 SMSC_TRACE(pdata, hw, "configuring for carrier OK");
fd9abb3d
SG		 978 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
979 (!pdata->using_extphy)) {
88393161 980 /* Restore original GPIO configuration */
fd9abb3d
SG		 981 pdata->gpio_setting = pdata->gpio_orig_setting;
982 smsc911x_reg_write(pdata, GPIO_CFG,
983 pdata->gpio_setting);
984 }
985 } else {
dffc6b24 986 SMSC_TRACE(pdata, hw, "configuring for no carrier");
fd9abb3d
SG		 987 /* Check global setting that LED1
988 * usage is 10/100 indicator */
989 pdata->gpio_setting = smsc911x_reg_read(pdata,
990 GPIO_CFG);
8e95a202
JP		 991 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
992 (!pdata->using_extphy)) {
fd9abb3d 993 /* Force 10/100 LED off, after saving
88393161 994 * original GPIO configuration */
fd9abb3d
SG		 995 pdata->gpio_orig_setting = pdata->gpio_setting;
996
997 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
998 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
999 | GPIO_CFG_GPIODIR0_
1000 | GPIO_CFG_GPIOD0_);
1001 smsc911x_reg_write(pdata, GPIO_CFG,
1002 pdata->gpio_setting);
1003 }
1004 }
1005 pdata->last_carrier = carrier;
1006 }
1007}
1008
1009static int smsc911x_mii_probe(struct net_device *dev)
1010{
1011 struct smsc911x_data *pdata = netdev_priv(dev);
1012 struct phy_device *phydev = NULL;
e4a474f8 1013 int ret;
fd9abb3d
SG		 1014
1015 /* find the first phy */
e4a474f8 1016 phydev = phy_find_first(pdata->mii_bus);
fd9abb3d 1017 if (!phydev) {
dffc6b24 1018 netdev_err(dev, "no PHY found\n");
fd9abb3d
SG		 1019 return -ENODEV;
1020 }
1021
dffc6b24 1022 SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
e5a03bfd 1023 phydev->mdio.addr, phydev->phy_id);
e4a474f8 1024
f9a8f83b
FF		 1025 ret = phy_connect_direct(dev, phydev, &smsc911x_phy_adjust_link,
1026 pdata->config.phy_interface);
fd9abb3d 1027
e4a474f8 1028 if (ret) {
dffc6b24 1029 netdev_err(dev, "Could not attach to PHY\n");
e4a474f8 1030 return ret;
fd9abb3d
SG		 1031 }
1032
2220943a 1033 phy_attached_info(phydev);
fd9abb3d
SG		 1034
1035 /* mask with MAC supported features */
1036 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1037 SUPPORTED_Asym_Pause);
1038 phydev->advertising = phydev->supported;
1039
1040 pdata->phy_dev = phydev;
1041 pdata->last_duplex = -1;
1042 pdata->last_carrier = -1;
1043
1044#ifdef USE_PHY_WORK_AROUND
1045 if (smsc911x_phy_loopbacktest(dev) < 0) {
dffc6b24 1046 SMSC_WARN(pdata, hw, "Failed Loop Back Test");
b43c142f 1047 phy_disconnect(phydev);
fd9abb3d
SG		 1048 return -ENODEV;
1049 }
dffc6b24 1050 SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
fd9abb3d
SG		 1051#endif /* USE_PHY_WORK_AROUND */
1052
dffc6b24 1053 SMSC_TRACE(pdata, hw, "phy initialised successfully");
fd9abb3d
SG		 1054 return 0;
1055}
1056
8489ec1f 1057static int smsc911x_mii_init(struct platform_device *pdev,
1dd06ae8 1058 struct net_device *dev)
fd9abb3d
SG		 1059{
1060 struct smsc911x_data *pdata = netdev_priv(dev);
e7f4dc35 1061 int err = -ENXIO;
fd9abb3d
SG		 1062
1063 pdata->mii_bus = mdiobus_alloc();
1064 if (!pdata->mii_bus) {
1065 err = -ENOMEM;
1066 goto err_out_1;
1067 }
1068
1069 pdata->mii_bus->name = SMSC_MDIONAME;
09ef0789
FF		 1070 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1071 pdev->name, pdev->id);
fd9abb3d
SG		 1072 pdata->mii_bus->priv = pdata;
1073 pdata->mii_bus->read = smsc911x_mii_read;
1074 pdata->mii_bus->write = smsc911x_mii_write;
fd9abb3d
SG		 1075
1076 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 1077
fd9abb3d
SG		 1078 switch (pdata->idrev & 0xFFFF0000) {
1079 case 0x01170000:
1080 case 0x01150000:
1081 case 0x117A0000:
1082 case 0x115A0000:
1083 /* External PHY supported, try to autodetect */
d23f028a 1084 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 1085 break;
1086 default:
dffc6b24
JP		 1087 SMSC_TRACE(pdata, hw, "External PHY is not supported, "
1088 "using internal PHY");
d23f028a 1089 pdata->using_extphy = 0;
fd9abb3d
SG		 1090 break;
1091 }
1092
1093 if (!pdata->using_extphy) {
1094 /* Mask all PHYs except ID 1 (internal) */
1095 pdata->mii_bus->phy_mask = ~(1 << 1);
1096 }
1097
1098 if (mdiobus_register(pdata->mii_bus)) {
dffc6b24 1099 SMSC_WARN(pdata, probe, "Error registering mii bus");
fd9abb3d
SG		 1100 goto err_out_free_bus_2;
1101 }
1102
1103 if (smsc911x_mii_probe(dev) < 0) {
dffc6b24 1104 SMSC_WARN(pdata, probe, "Error registering mii bus");
fd9abb3d
SG		 1105 goto err_out_unregister_bus_3;
1106 }
1107
1108 return 0;
1109
1110err_out_unregister_bus_3:
1111 mdiobus_unregister(pdata->mii_bus);
1112err_out_free_bus_2:
1113 mdiobus_free(pdata->mii_bus);
1114err_out_1:
1115 return err;
1116}
1117
1118/* Gets the number of tx statuses in the fifo */
1119static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
1120{
1121 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
1122 & TX_FIFO_INF_TSUSED_) >> 16;
1123}
1124
1125/* Reads tx statuses and increments counters where necessary */
1126static void smsc911x_tx_update_txcounters(struct net_device *dev)
1127{
1128 struct smsc911x_data *pdata = netdev_priv(dev);
1129 unsigned int tx_stat;
1130
1131 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
1132 if (unlikely(tx_stat & 0x80000000)) {
1133 /* In this driver the packet tag is used as the packet
1134 * length. Since a packet length can never reach the
1135 * size of 0x8000, this bit is reserved. It is worth
1136 * noting that the "reserved bit" in the warning above
1137 * does not reference a hardware defined reserved bit
1138 * but rather a driver defined one.
1139 */
dffc6b24 1140 SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
fd9abb3d 1141 } else {
785b6f97 1142 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 1143 dev->stats.tx_errors++;
1144 } else {
1145 dev->stats.tx_packets++;
1146 dev->stats.tx_bytes += (tx_stat >> 16);
1147 }
785b6f97 1148 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 1149 dev->stats.collisions += 16;
1150 dev->stats.tx_aborted_errors += 1;
1151 } else {
1152 dev->stats.collisions +=
1153 ((tx_stat >> 3) & 0xF);
1154 }
785b6f97 1155 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 1156 dev->stats.tx_carrier_errors += 1;
785b6f97 1157 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 1158 dev->stats.collisions++;
1159 dev->stats.tx_aborted_errors++;
1160 }
1161 }
1162 }
1163}
1164
1165/* Increments the Rx error counters */
1166static void
1167smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
1168{
1169 int crc_err = 0;
1170
785b6f97 1171 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 1172 dev->stats.rx_errors++;
785b6f97 1173 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 1174 dev->stats.rx_crc_errors++;
1175 crc_err = 1;
1176 }
1177 }
1178 if (likely(!crc_err)) {
785b6f97
SG		 1179 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
1180 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 1181 dev->stats.rx_length_errors++;
fd9abb3d
SG		 1182 if (rxstat & RX_STS_MCAST_)
1183 dev->stats.multicast++;
1184 }
1185}
1186
1187/* Quickly dumps bad packets */
1188static void
3c5e979b 1189smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords)
fd9abb3d 1190{
fd9abb3d
SG		 1191 if (likely(pktwords >= 4)) {
1192 unsigned int timeout = 500;
1193 unsigned int val;
1194 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
1195 do {
1196 udelay(1);
1197 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 1198 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 1199
1200 if (unlikely(timeout == 0))
dffc6b24
JP		 1201 SMSC_WARN(pdata, hw, "Timed out waiting for "
1202 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
fd9abb3d
SG		 1203 } else {
1204 unsigned int temp;
1205 while (pktwords--)
1206 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
1207 }
1208}
1209
1210/* NAPI poll function */
1211static int smsc911x_poll(struct napi_struct *napi, int budget)
1212{
1213 struct smsc911x_data *pdata =
1214 container_of(napi, struct smsc911x_data, napi);
1215 struct net_device *dev = pdata->dev;
1216 int npackets = 0;
1217
f88c5b98 1218 while (npackets < budget) {
fd9abb3d
SG		 1219 unsigned int pktlength;
1220 unsigned int pktwords;
1221 struct sk_buff *skb;
1222 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
1223
1224 if (!rxstat) {
1225 unsigned int temp;
1226 /* We processed all packets available. Tell NAPI it can
1227 * stop polling then re-enable rx interrupts */
1228 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 1229 napi_complete(napi);
fd9abb3d
SG		 1230 temp = smsc911x_reg_read(pdata, INT_EN);
1231 temp |= INT_EN_RSFL_EN_;
1232 smsc911x_reg_write(pdata, INT_EN, temp);
1233 break;
1234 }
1235
1236 /* Count packet for NAPI scheduling, even if it has an error.
1237 * Error packets still require cycles to discard */
1238 npackets++;
1239
1240 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1241 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1242 smsc911x_rx_counterrors(dev, rxstat);
1243
1244 if (unlikely(rxstat & RX_STS_ES_)) {
dffc6b24
JP		 1245 SMSC_WARN(pdata, rx_err,
1246 "Discarding packet with error bit set");
fd9abb3d
SG		 1247 /* Packet has an error, discard it and continue with
1248 * the next */
1249 smsc911x_rx_fastforward(pdata, pktwords);
1250 dev->stats.rx_dropped++;
1251 continue;
1252 }
1253
3c5e979b 1254 skb = netdev_alloc_skb(dev, pktwords << 2);
fd9abb3d 1255 if (unlikely(!skb)) {
dffc6b24
JP		 1256 SMSC_WARN(pdata, rx_err,
1257 "Unable to allocate skb for rx packet");
fd9abb3d
SG		 1258 /* Drop the packet and stop this polling iteration */
1259 smsc911x_rx_fastforward(pdata, pktwords);
1260 dev->stats.rx_dropped++;
1261 break;
1262 }
1263
3c5e979b
WD		 1264 pdata->ops->rx_readfifo(pdata,
1265 (unsigned int *)skb->data, pktwords);
fd9abb3d
SG		 1266
1267 /* Align IP on 16B boundary */
1268 skb_reserve(skb, NET_IP_ALIGN);
1269 skb_put(skb, pktlength - 4);
fd9abb3d 1270 skb->protocol = eth_type_trans(skb, dev);
bc8acf2c 1271 skb_checksum_none_assert(skb);
fd9abb3d
SG		 1272 netif_receive_skb(skb);
1273
1274 /* Update counters */
1275 dev->stats.rx_packets++;
1276 dev->stats.rx_bytes += (pktlength - 4);
fd9abb3d
SG		 1277 }
1278
1279 /* Return total received packets */
1280 return npackets;
1281}
1282
1283/* Returns hash bit number for given MAC address
1284 * Example:
1285 * 01 00 5E 00 00 01 -> returns bit number 31 */
1286static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1287{
1288 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1289}
1290
1291static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1292{
1293 /* Performs the multicast & mac_cr update. This is called when
1294 * safe on the current hardware, and with the mac_lock held */
1295 unsigned int mac_cr;
1296
1297 SMSC_ASSERT_MAC_LOCK(pdata);
1298
1299 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1300 mac_cr |= pdata->set_bits_mask;
1301 mac_cr &= ~(pdata->clear_bits_mask);
1302 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1303 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1304 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
dffc6b24
JP		 1305 SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1306 mac_cr, pdata->hashhi, pdata->hashlo);
fd9abb3d
SG		 1307}
1308
1309static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1310{
1311 unsigned int mac_cr;
1312
1313 /* This function is only called for older LAN911x devices
1314 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1315 * be modified during Rx - newer devices immediately update the
1316 * registers.
1317 *
1318 * This is called from interrupt context */
1319
1320 spin_lock(&pdata->mac_lock);
1321
1322 /* Check Rx has stopped */
1323 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
dffc6b24 1324 SMSC_WARN(pdata, drv, "Rx not stopped");
fd9abb3d
SG		 1325
1326 /* Perform the update - safe to do now Rx has stopped */
1327 smsc911x_rx_multicast_update(pdata);
1328
1329 /* Re-enable Rx */
1330 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1331 mac_cr |= MAC_CR_RXEN_;
1332 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1333
1334 pdata->multicast_update_pending = 0;
1335
1336 spin_unlock(&pdata->mac_lock);
1337}
1338
ccf899a2
EBS		 1339static int smsc911x_phy_general_power_up(struct smsc911x_data *pdata)
1340{
1341 int rc = 0;
1342
1343 if (!pdata->phy_dev)
1344 return rc;
1345
1346 /* If the internal PHY is in General Power-Down mode, all, except the
1347 * management interface, is powered-down and stays in that condition as
1348 * long as Phy register bit 0.11 is HIGH.
1349 *
1350 * In that case, clear the bit 0.11, so the PHY powers up and we can
1351 * access to the phy registers.
1352 */
1353 rc = phy_read(pdata->phy_dev, MII_BMCR);
1354 if (rc < 0) {
1355 SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
1356 return rc;
1357 }
1358
1359 /* If the PHY general power-down bit is not set is not necessary to
1360 * disable the general power down-mode.
1361 */
1362 if (rc & BMCR_PDOWN) {
1363 rc = phy_write(pdata->phy_dev, MII_BMCR, rc & ~BMCR_PDOWN);
1364 if (rc < 0) {
1365 SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
1366 return rc;
1367 }
1368
1369 usleep_range(1000, 1500);
1370 }
1371
1372 return 0;
1373}
1374
6386994e
JMC		 1375static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata)
1376{
1377 int rc = 0;
1378
1379 if (!pdata->phy_dev)
1380 return rc;
1381
1382 rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS);
1383
1384 if (rc < 0) {
1385 SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
1386 return rc;
1387 }
1388
242bcd5b
AK		 1389 /* Only disable if energy detect mode is already enabled */
1390 if (rc & MII_LAN83C185_EDPWRDOWN) {
6386994e
JMC		 1391 /* Disable energy detect mode for this SMSC Transceivers */
1392 rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
1393 rc & (~MII_LAN83C185_EDPWRDOWN));
1394
1395 if (rc < 0) {
1396 SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
1397 return rc;
1398 }
6ff53fd3
AK		 1399 /* Allow PHY to wakeup */
1400 mdelay(2);
6386994e
JMC		 1401 }
1402
1403 return 0;
1404}
1405
1406static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata)
1407{
1408 int rc = 0;
1409
1410 if (!pdata->phy_dev)
1411 return rc;
1412
1413 rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS);
1414
1415 if (rc < 0) {
1416 SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
1417 return rc;
1418 }
1419
1420 /* Only enable if energy detect mode is already disabled */
1421 if (!(rc & MII_LAN83C185_EDPWRDOWN)) {
6386994e
JMC		 1422 /* Enable energy detect mode for this SMSC Transceivers */
1423 rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
1424 rc | MII_LAN83C185_EDPWRDOWN);
1425
1426 if (rc < 0) {
1427 SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
1428 return rc;
1429 }
6386994e
JMC		 1430 }
1431 return 0;
1432}
1433
fd9abb3d
SG		 1434static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1435{
1436 unsigned int timeout;
1437 unsigned int temp;
6386994e
JMC		 1438 int ret;
1439
ccf899a2
EBS		 1440 /*
1441 * Make sure to power-up the PHY chip before doing a reset, otherwise
1442 * the reset fails.
1443 */
1444 ret = smsc911x_phy_general_power_up(pdata);
1445 if (ret) {
1446 SMSC_WARN(pdata, drv, "Failed to power-up the PHY chip");
1447 return ret;
1448 }
1449
6386994e
JMC		 1450 /*
1451 * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that
1452 * are initialized in a Energy Detect Power-Down mode that prevents
1453 * the MAC chip to be software reseted. So we have to wakeup the PHY
1454 * before.
1455 */
1456 if (pdata->generation == 4) {
1457 ret = smsc911x_phy_disable_energy_detect(pdata);
1458
1459 if (ret) {
1460 SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
1461 return ret;
1462 }
1463 }
fd9abb3d
SG		 1464
1465 /* Reset the LAN911x */
1466 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1467 timeout = 10;
1468 do {
1469 udelay(10);
1470 temp = smsc911x_reg_read(pdata, HW_CFG);
1471 } while ((--timeout) && (temp & HW_CFG_SRST_));
1472
1473 if (unlikely(temp & HW_CFG_SRST_)) {
dffc6b24 1474 SMSC_WARN(pdata, drv, "Failed to complete reset");
fd9abb3d
SG		 1475 return -EIO;
1476 }
6386994e
JMC		 1477
1478 if (pdata->generation == 4) {
1479 ret = smsc911x_phy_enable_energy_detect(pdata);
1480
1481 if (ret) {
1482 SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
1483 return ret;
1484 }
1485 }
1486
fd9abb3d
SG		 1487 return 0;
1488}
1489
1490/* Sets the device MAC address to dev_addr, called with mac_lock held */
1491static void
225ddf49 1492smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1493{
1494 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1495 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1496 (dev_addr[1] << 8) | dev_addr[0];
1497
1498 SMSC_ASSERT_MAC_LOCK(pdata);
1499
1500 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1501 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1502}
1503
8e27628e
MB		 1504static void smsc911x_disable_irq_chip(struct net_device *dev)
1505{
1506 struct smsc911x_data *pdata = netdev_priv(dev);
1507
1508 smsc911x_reg_write(pdata, INT_EN, 0);
1509 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1510}
1511
fd9abb3d
SG		 1512static int smsc911x_open(struct net_device *dev)
1513{
1514 struct smsc911x_data *pdata = netdev_priv(dev);
1515 unsigned int timeout;
1516 unsigned int temp;
1517 unsigned int intcfg;
1518
1519 /* if the phy is not yet registered, retry later*/
1520 if (!pdata->phy_dev) {
dffc6b24 1521 SMSC_WARN(pdata, hw, "phy_dev is NULL");
fd9abb3d
SG		 1522 return -EAGAIN;
1523 }
1524
fd9abb3d
SG		 1525 /* Reset the LAN911x */
1526 if (smsc911x_soft_reset(pdata)) {
dffc6b24 1527 SMSC_WARN(pdata, hw, "soft reset failed");
fd9abb3d
SG		 1528 return -EIO;
1529 }
1530
1531 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1532 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1533
f277e65e
GW		 1534 /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
1535 spin_lock_irq(&pdata->mac_lock);
1536 smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
1537 spin_unlock_irq(&pdata->mac_lock);
1538
fd9abb3d
SG		 1539 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1540 timeout = 50;
f7efb6cc
SG		 1541 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1542 --timeout) {
fd9abb3d
SG		 1543 udelay(10);
1544 }
1545
1546 if (unlikely(timeout == 0))
dffc6b24
JP		 1547 SMSC_WARN(pdata, ifup,
1548 "Timed out waiting for EEPROM busy bit to clear");
fd9abb3d
SG		 1549
1550 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1551
1552 /* The soft reset above cleared the device's MAC address,
1553 * restore it from local copy (set in probe) */
1554 spin_lock_irq(&pdata->mac_lock);
225ddf49 1555 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1556 spin_unlock_irq(&pdata->mac_lock);
1557
1558 /* Initialise irqs, but leave all sources disabled */
8e27628e 1559 smsc911x_disable_irq_chip(dev);
fd9abb3d
SG		 1560
1561 /* Set interrupt deassertion to 100uS */
1562 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1563
2107fb8b 1564 if (pdata->config.irq_polarity) {
dffc6b24 1565 SMSC_TRACE(pdata, ifup, "irq polarity: active high");
fd9abb3d
SG		 1566 intcfg |= INT_CFG_IRQ_POL_;
1567 } else {
dffc6b24 1568 SMSC_TRACE(pdata, ifup, "irq polarity: active low");
fd9abb3d
SG		 1569 }
1570
2107fb8b 1571 if (pdata->config.irq_type) {
dffc6b24 1572 SMSC_TRACE(pdata, ifup, "irq type: push-pull");
fd9abb3d
SG		 1573 intcfg |= INT_CFG_IRQ_TYPE_;
1574 } else {
dffc6b24 1575 SMSC_TRACE(pdata, ifup, "irq type: open drain");
fd9abb3d
SG		 1576 }
1577
1578 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1579
dffc6b24 1580 SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
fd9abb3d
SG		 1581 pdata->software_irq_signal = 0;
1582 smp_wmb();
1583
1584 temp = smsc911x_reg_read(pdata, INT_EN);
1585 temp |= INT_EN_SW_INT_EN_;
1586 smsc911x_reg_write(pdata, INT_EN, temp);
1587
1588 timeout = 1000;
1589 while (timeout--) {
1590 if (pdata->software_irq_signal)
1591 break;
1592 msleep(1);
1593 }
1594
1595 if (!pdata->software_irq_signal) {
dffc6b24
JP		 1596 netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
1597 dev->irq);
fd9abb3d
SG		 1598 return -ENODEV;
1599 }
dffc6b24
JP		 1600 SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
1601 dev->irq);
fd9abb3d 1602
dffc6b24
JP		 1603 netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1604 (unsigned long)pdata->ioaddr, dev->irq);
fd9abb3d 1605
44c1d6f9
SG		 1606 /* Reset the last known duplex and carrier */
1607 pdata->last_duplex = -1;
1608 pdata->last_carrier = -1;
1609
fd9abb3d
SG		 1610 /* Bring the PHY up */
1611 phy_start(pdata->phy_dev);
1612
1613 temp = smsc911x_reg_read(pdata, HW_CFG);
1614 /* Preserve TX FIFO size and external PHY configuration */
1615 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1616 temp |= HW_CFG_SF_;
1617 smsc911x_reg_write(pdata, HW_CFG, temp);
1618
1619 temp = smsc911x_reg_read(pdata, FIFO_INT);
1620 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1621 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1622 smsc911x_reg_write(pdata, FIFO_INT, temp);
1623
1624 /* set RX Data offset to 2 bytes for alignment */
3c5e979b 1625 smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8));
fd9abb3d
SG		 1626
1627 /* enable NAPI polling before enabling RX interrupts */
1628 napi_enable(&pdata->napi);
1629
1630 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1631 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1632 smsc911x_reg_write(pdata, INT_EN, temp);
1633
1634 spin_lock_irq(&pdata->mac_lock);
1635 temp = smsc911x_mac_read(pdata, MAC_CR);
1636 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1637 smsc911x_mac_write(pdata, MAC_CR, temp);
1638 spin_unlock_irq(&pdata->mac_lock);
1639
1640 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1641
1642 netif_start_queue(dev);
1643 return 0;
1644}
1645
1646/* Entry point for stopping the interface */
1647static int smsc911x_stop(struct net_device *dev)
1648{
1649 struct smsc911x_data *pdata = netdev_priv(dev);
1650 unsigned int temp;
1651
fd9abb3d
SG		 1652 /* Disable all device interrupts */
1653 temp = smsc911x_reg_read(pdata, INT_CFG);
1654 temp &= ~INT_CFG_IRQ_EN_;
1655 smsc911x_reg_write(pdata, INT_CFG, temp);
1656
1657 /* Stop Tx and Rx polling */
1658 netif_stop_queue(dev);
1659 napi_disable(&pdata->napi);
1660
1661 /* At this point all Rx and Tx activity is stopped */
1662 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1663 smsc911x_tx_update_txcounters(dev);
1664
1665 /* Bring the PHY down */
dd045193
SG		 1666 if (pdata->phy_dev)
1667 phy_stop(pdata->phy_dev);
fd9abb3d 1668
dffc6b24 1669 SMSC_TRACE(pdata, ifdown, "Interface stopped");
fd9abb3d
SG		 1670 return 0;
1671}
1672
1673/* Entry point for transmitting a packet */
1674static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1675{
1676 struct smsc911x_data *pdata = netdev_priv(dev);
1677 unsigned int freespace;
1678 unsigned int tx_cmd_a;
1679 unsigned int tx_cmd_b;
1680 unsigned int temp;
1681 u32 wrsz;
1682 ulong bufp;
1683
1684 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1685
1686 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
dffc6b24
JP		 1687 SMSC_WARN(pdata, tx_err,
1688 "Tx data fifo low, space available: %d", freespace);
fd9abb3d
SG		 1689
1690 /* Word alignment adjustment */
1691 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1692 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1693 tx_cmd_a |= (unsigned int)skb->len;
1694
1695 tx_cmd_b = ((unsigned int)skb->len) << 16;
1696 tx_cmd_b |= (unsigned int)skb->len;
1697
1698 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1699 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1700
1701 bufp = (ulong)skb->data & (~0x3);
1702 wrsz = (u32)skb->len + 3;
1703 wrsz += (u32)((ulong)skb->data & 0x3);
1704 wrsz >>= 2;
1705
c326de88 1706 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
fd9abb3d 1707 freespace -= (skb->len + 32);
8c0069ae 1708 skb_tx_timestamp(skb);
89a9eb63 1709 dev_consume_skb_any(skb);
fd9abb3d
SG		 1710
1711 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1712 smsc911x_tx_update_txcounters(dev);
1713
1714 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1715 netif_stop_queue(dev);
1716 temp = smsc911x_reg_read(pdata, FIFO_INT);
1717 temp &= 0x00FFFFFF;
1718 temp |= 0x32000000;
1719 smsc911x_reg_write(pdata, FIFO_INT, temp);
1720 }
1721
1722 return NETDEV_TX_OK;
1723}
1724
1725/* Entry point for getting status counters */
1726static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1727{
1728 struct smsc911x_data *pdata = netdev_priv(dev);
1729 smsc911x_tx_update_txcounters(dev);
1730 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1731 return &dev->stats;
1732}
1733
1734/* Entry point for setting addressing modes */
1735static void smsc911x_set_multicast_list(struct net_device *dev)
1736{
1737 struct smsc911x_data *pdata = netdev_priv(dev);
1738 unsigned long flags;
1739
1740 if (dev->flags & IFF_PROMISC) {
1741 /* Enabling promiscuous mode */
1742 pdata->set_bits_mask = MAC_CR_PRMS_;
1743 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1744 pdata->hashhi = 0;
1745 pdata->hashlo = 0;
1746 } else if (dev->flags & IFF_ALLMULTI) {
1747 /* Enabling all multicast mode */
1748 pdata->set_bits_mask = MAC_CR_MCPAS_;
1749 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1750 pdata->hashhi = 0;
1751 pdata->hashlo = 0;
4cd24eaf 1752 } else if (!netdev_mc_empty(dev)) {
fd9abb3d
SG		 1753 /* Enabling specific multicast addresses */
1754 unsigned int hash_high = 0;
1755 unsigned int hash_low = 0;
22bedad3 1756 struct netdev_hw_addr *ha;
fd9abb3d
SG		 1757
1758 pdata->set_bits_mask = MAC_CR_HPFILT_;
1759 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1760
22bedad3
JP		 1761 netdev_for_each_mc_addr(ha, dev) {
1762 unsigned int bitnum = smsc911x_hash(ha->addr);
2a0d18f9
JP		 1763 unsigned int mask = 0x01 << (bitnum & 0x1F);
1764
1765 if (bitnum & 0x20)
1766 hash_high |= mask;
1767 else
1768 hash_low |= mask;
fd9abb3d 1769 }
fd9abb3d
SG		 1770
1771 pdata->hashhi = hash_high;
1772 pdata->hashlo = hash_low;
1773 } else {
1774 /* Enabling local MAC address only */
1775 pdata->set_bits_mask = 0;
1776 pdata->clear_bits_mask =
1777 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1778 pdata->hashhi = 0;
1779 pdata->hashlo = 0;
1780 }
1781
1782 spin_lock_irqsave(&pdata->mac_lock, flags);
1783
1784 if (pdata->generation <= 1) {
1785 /* Older hardware revision - cannot change these flags while
1786 * receiving data */
1787 if (!pdata->multicast_update_pending) {
1788 unsigned int temp;
dffc6b24 1789 SMSC_TRACE(pdata, hw, "scheduling mcast update");
fd9abb3d
SG		 1790 pdata->multicast_update_pending = 1;
1791
1792 /* Request the hardware to stop, then perform the
1793 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1794 temp = smsc911x_mac_read(pdata, MAC_CR);
1795 temp &= ~(MAC_CR_RXEN_);
1796 smsc911x_mac_write(pdata, MAC_CR, temp);
1797 } else {
1798 /* There is another update pending, this should now
1799 * use the newer values */
1800 }
1801 } else {
1802 /* Newer hardware revision - can write immediately */
1803 smsc911x_rx_multicast_update(pdata);
1804 }
1805
1806 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1807}
1808
1809static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1810{
1811 struct net_device *dev = dev_id;
1812 struct smsc911x_data *pdata = netdev_priv(dev);
1813 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1814 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1815 int serviced = IRQ_NONE;
1816 u32 temp;
1817
1818 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1819 temp = smsc911x_reg_read(pdata, INT_EN);
1820 temp &= (~INT_EN_SW_INT_EN_);
1821 smsc911x_reg_write(pdata, INT_EN, temp);
1822 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1823 pdata->software_irq_signal = 1;
1824 smp_wmb();
1825 serviced = IRQ_HANDLED;
1826 }
1827
1828 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1829 /* Called when there is a multicast update scheduled and
1830 * it is now safe to complete the update */
dffc6b24 1831 SMSC_TRACE(pdata, intr, "RX Stop interrupt");
fd9abb3d 1832 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1833 if (pdata->multicast_update_pending)
1834 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1835 serviced = IRQ_HANDLED;
1836 }
1837
1838 if (intsts & inten & INT_STS_TDFA_) {
1839 temp = smsc911x_reg_read(pdata, FIFO_INT);
1840 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1841 smsc911x_reg_write(pdata, FIFO_INT, temp);
1842 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1843 netif_wake_queue(dev);
1844 serviced = IRQ_HANDLED;
1845 }
1846
1847 if (unlikely(intsts & inten & INT_STS_RXE_)) {
dffc6b24 1848 SMSC_TRACE(pdata, intr, "RX Error interrupt");
fd9abb3d
SG		 1849 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1850 serviced = IRQ_HANDLED;
1851 }
1852
1853 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1854 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1855 /* Disable Rx interrupts */
1856 temp = smsc911x_reg_read(pdata, INT_EN);
1857 temp &= (~INT_EN_RSFL_EN_);
1858 smsc911x_reg_write(pdata, INT_EN, temp);
1859 /* Schedule a NAPI poll */
288379f0 1860 __napi_schedule(&pdata->napi);
fd9abb3d 1861 } else {
dffc6b24 1862 SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
fd9abb3d
SG		 1863 }
1864 serviced = IRQ_HANDLED;
1865 }
1866
1867 return serviced;
1868}
1869
1870#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1871static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1872{
1873 disable_irq(dev->irq);
1874 smsc911x_irqhandler(0, dev);
1875 enable_irq(dev->irq);
1876}
1877#endif /* CONFIG_NET_POLL_CONTROLLER */
1878
225ddf49
SG		 1879static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1880{
1881 struct smsc911x_data *pdata = netdev_priv(dev);
1882 struct sockaddr *addr = p;
1883
1884 /* On older hardware revisions we cannot change the mac address
1885 * registers while receiving data. Newer devices can safely change
1886 * this at any time. */
1887 if (pdata->generation <= 1 && netif_running(dev))
1888 return -EBUSY;
1889
1890 if (!is_valid_ether_addr(addr->sa_data))
1891 return -EADDRNOTAVAIL;
1892
1893 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1894
1895 spin_lock_irq(&pdata->mac_lock);
1896 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1897 spin_unlock_irq(&pdata->mac_lock);
1898
dffc6b24 1899 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
225ddf49
SG		 1900
1901 return 0;
1902}
1903
fd9abb3d
SG		 1904/* Standard ioctls for mii-tool */
1905static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1906{
1907 struct smsc911x_data *pdata = netdev_priv(dev);
1908
1909 if (!netif_running(dev) || !pdata->phy_dev)
1910 return -EINVAL;
1911
28b04113 1912 return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
fd9abb3d
SG		 1913}
1914
1915static int
1916smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1917{
1918 struct smsc911x_data *pdata = netdev_priv(dev);
1919
1920 cmd->maxtxpkt = 1;
1921 cmd->maxrxpkt = 1;
1922 return phy_ethtool_gset(pdata->phy_dev, cmd);
1923}
1924
1925static int
1926smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1927{
1928 struct smsc911x_data *pdata = netdev_priv(dev);
1929
1930 return phy_ethtool_sset(pdata->phy_dev, cmd);
1931}
1932
1933static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1934 struct ethtool_drvinfo *info)
1935{
1936 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1937 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1938 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1939 sizeof(info->bus_info));
1940}
1941
1942static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1943{
1944 struct smsc911x_data *pdata = netdev_priv(dev);
1945
1946 return phy_start_aneg(pdata->phy_dev);
1947}
1948
1949static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1950{
1951 struct smsc911x_data *pdata = netdev_priv(dev);
1952 return pdata->msg_enable;
1953}
1954
1955static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1956{
1957 struct smsc911x_data *pdata = netdev_priv(dev);
1958 pdata->msg_enable = level;
1959}
1960
1961static int smsc911x_ethtool_getregslen(struct net_device *dev)
1962{
1963 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1964 sizeof(u32);
1965}
1966
1967static void
1968smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1969 void *buf)
1970{
1971 struct smsc911x_data *pdata = netdev_priv(dev);
1972 struct phy_device *phy_dev = pdata->phy_dev;
1973 unsigned long flags;
1974 unsigned int i;
1975 unsigned int j = 0;
1976 u32 *data = buf;
1977
1978 regs->version = pdata->idrev;
1979 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1980 data[j++] = smsc911x_reg_read(pdata, i);
1981
1982 for (i = MAC_CR; i <= WUCSR; i++) {
1983 spin_lock_irqsave(&pdata->mac_lock, flags);
1984 data[j++] = smsc911x_mac_read(pdata, i);
1985 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1986 }
1987
1988 for (i = 0; i <= 31; i++)
e5a03bfd
AL		 1989 data[j++] = smsc911x_mii_read(phy_dev->mdio.bus,
1990 phy_dev->mdio.addr, i);
fd9abb3d
SG		 1991}
1992
1993static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1994{
1995 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1996 temp &= ~GPIO_CFG_EEPR_EN_;
1997 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1998 msleep(1);
1999}
2000
2001static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
2002{
2003 int timeout = 100;
2004 u32 e2cmd;
2005
dffc6b24 2006 SMSC_TRACE(pdata, drv, "op 0x%08x", op);
fd9abb3d 2007 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
dffc6b24 2008 SMSC_WARN(pdata, drv, "Busy at start");
fd9abb3d
SG		 2009 return -EBUSY;
2010 }
2011
2012 e2cmd = op | E2P_CMD_EPC_BUSY_;
2013 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
2014
2015 do {
2016 msleep(1);
2017 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 2018 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 2019
2020 if (!timeout) {
dffc6b24 2021 SMSC_TRACE(pdata, drv, "TIMED OUT");
fd9abb3d
SG		 2022 return -EAGAIN;
2023 }
2024
2025 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1c01a80c 2026 SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
fd9abb3d
SG		 2027 return -EINVAL;
2028 }
2029
2030 return 0;
2031}
2032
2033static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
2034 u8 address, u8 *data)
2035{
2036 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
2037 int ret;
2038
dffc6b24 2039 SMSC_TRACE(pdata, drv, "address 0x%x", address);
fd9abb3d
SG		 2040 ret = smsc911x_eeprom_send_cmd(pdata, op);
2041
2042 if (!ret)
2043 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
2044
2045 return ret;
2046}
2047
2048static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
2049 u8 address, u8 data)
2050{
2051 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
58add9fc 2052 u32 temp;
fd9abb3d
SG		 2053 int ret;
2054
dffc6b24 2055 SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
fd9abb3d
SG		 2056 ret = smsc911x_eeprom_send_cmd(pdata, op);
2057
2058 if (!ret) {
2059 op = E2P_CMD_EPC_CMD_WRITE_ | address;
2060 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
58add9fc
SG		 2061
2062 /* Workaround for hardware read-after-write restriction */
2063 temp = smsc911x_reg_read(pdata, BYTE_TEST);
2064
fd9abb3d
SG		 2065 ret = smsc911x_eeprom_send_cmd(pdata, op);
2066 }
2067
2068 return ret;
2069}
2070
2071static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
2072{
2073 return SMSC911X_EEPROM_SIZE;
2074}
2075
2076static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
2077 struct ethtool_eeprom *eeprom, u8 *data)
2078{
2079 struct smsc911x_data *pdata = netdev_priv(dev);
2080 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
2081 int len;
2082 int i;
2083
2084 smsc911x_eeprom_enable_access(pdata);
2085
2086 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
2087 for (i = 0; i < len; i++) {
2088 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
2089 if (ret < 0) {
2090 eeprom->len = 0;
2091 return ret;
2092 }
2093 }
2094
2095 memcpy(data, &eeprom_data[eeprom->offset], len);
2096 eeprom->len = len;
2097 return 0;
2098}
2099
2100static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
2101 struct ethtool_eeprom *eeprom, u8 *data)
2102{
2103 int ret;
2104 struct smsc911x_data *pdata = netdev_priv(dev);
2105
2106 smsc911x_eeprom_enable_access(pdata);
2107 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
2108 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
2109 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
2110
2111 /* Single byte write, according to man page */
2112 eeprom->len = 1;
2113
2114 return ret;
2115}
2116
cb5b04fe 2117static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 2118 .get_settings = smsc911x_ethtool_getsettings,
2119 .set_settings = smsc911x_ethtool_setsettings,
2120 .get_link = ethtool_op_get_link,
2121 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
2122 .nway_reset = smsc911x_ethtool_nwayreset,
2123 .get_msglevel = smsc911x_ethtool_getmsglevel,
2124 .set_msglevel = smsc911x_ethtool_setmsglevel,
2125 .get_regs_len = smsc911x_ethtool_getregslen,
2126 .get_regs = smsc911x_ethtool_getregs,
2127 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
2128 .get_eeprom = smsc911x_ethtool_get_eeprom,
2129 .set_eeprom = smsc911x_ethtool_set_eeprom,
b5d1d256 2130 .get_ts_info = ethtool_op_get_ts_info,
fd9abb3d
SG		 2131};
2132
631b7568
SG		 2133static const struct net_device_ops smsc911x_netdev_ops = {
2134 .ndo_open = smsc911x_open,
2135 .ndo_stop = smsc911x_stop,
2136 .ndo_start_xmit = smsc911x_hard_start_xmit,
2137 .ndo_get_stats = smsc911x_get_stats,
afc4b13d 2138 .ndo_set_rx_mode = smsc911x_set_multicast_list,
631b7568 2139 .ndo_do_ioctl = smsc911x_do_ioctl,
635ecaa7 2140 .ndo_change_mtu = eth_change_mtu,
631b7568 2141 .ndo_validate_addr = eth_validate_addr,
225ddf49 2142 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 2143#ifdef CONFIG_NET_POLL_CONTROLLER
2144 .ndo_poll_controller = smsc911x_poll_controller,
2145#endif
2146};
2147
31f45747 2148/* copies the current mac address from hardware to dev->dev_addr */
8489ec1f 2149static void smsc911x_read_mac_address(struct net_device *dev)
31f45747
SG		 2150{
2151 struct smsc911x_data *pdata = netdev_priv(dev);
2152 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
2153 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
2154
2155 dev->dev_addr[0] = (u8)(mac_low32);
2156 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
2157 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
2158 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
2159 dev->dev_addr[4] = (u8)(mac_high16);
2160 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
2161}
2162
fd9abb3d 2163/* Initializing private device structures, only called from probe */
8489ec1f 2164static int smsc911x_init(struct net_device *dev)
fd9abb3d
SG		 2165{
2166 struct smsc911x_data *pdata = netdev_priv(dev);
769ce4c9 2167 unsigned int byte_test, mask;
3ac3546e 2168 unsigned int to = 100;
fd9abb3d 2169
dffc6b24
JP		 2170 SMSC_TRACE(pdata, probe, "Driver Parameters:");
2171 SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
2172 (unsigned long)pdata->ioaddr);
2173 SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
2174 SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
fd9abb3d 2175
fd9abb3d 2176 spin_lock_init(&pdata->dev_lock);
35a67edf 2177 spin_lock_init(&pdata->mac_lock);
fd9abb3d 2178
6fed9592 2179 if (pdata->ioaddr == NULL) {
dffc6b24 2180 SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
fd9abb3d
SG		 2181 return -ENODEV;
2182 }
2183
3ac3546e
RM		 2184 /*
2185 * poll the READY bit in PMT_CTRL. Any other access to the device is
2186 * forbidden while this bit isn't set. Try for 100ms
769ce4c9
KP		 2187 *
2188 * Note that this test is done before the WORD_SWAP register is
2189 * programmed. So in some configurations the READY bit is at 16 before
2190 * WORD_SWAP is written to. This issue is worked around by waiting
2191 * until either bit 0 or bit 16 gets set in PMT_CTRL.
2192 *
2193 * SMSC has confirmed that checking bit 16 (marked as reserved in
2194 * the datasheet) is fine since these bits "will either never be set
2195 * or can only go high after READY does (so also indicate the device
2196 * is ready)".
3ac3546e 2197 */
769ce4c9
KP		 2198
2199 mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_);
2200 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to)
3ac3546e 2201 udelay(1000);
769ce4c9 2202
3ac3546e 2203 if (to == 0) {
b1a04a62 2204 netdev_err(dev, "Device not READY in 100ms aborting\n");
3ac3546e
RM		 2205 return -ENODEV;
2206 }
2207
fd9abb3d
SG		 2208 /* Check byte ordering */
2209 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
dffc6b24 2210 SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
fd9abb3d 2211 if (byte_test == 0x43218765) {
dffc6b24
JP		 2212 SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
2213 "applying WORD_SWAP");
fd9abb3d
SG		 2214 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
2215
2216 /* 1 dummy read of BYTE_TEST is needed after a write to
2217 * WORD_SWAP before its contents are valid */
2218 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
2219
2220 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
2221 }
2222
2223 if (byte_test != 0x87654321) {
dffc6b24 2224 SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
fd9abb3d 2225 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
dffc6b24
JP		 2226 SMSC_WARN(pdata, probe,
2227 "top 16 bits equal to bottom 16 bits");
2228 SMSC_TRACE(pdata, probe,
2229 "This may mean the chip is set "
2230 "for 32 bit while the bus is reading 16 bit");
fd9abb3d
SG		 2231 }
2232 return -ENODEV;
2233 }
2234
2235 /* Default generation to zero (all workarounds apply) */
2236 pdata->generation = 0;
2237
2238 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
2239 switch (pdata->idrev & 0xFFFF0000) {
2240 case 0x01180000:
2241 case 0x01170000:
2242 case 0x01160000:
2243 case 0x01150000:
28c21379 2244 case 0x218A0000:
fd9abb3d
SG		 2245 /* LAN911[5678] family */
2246 pdata->generation = pdata->idrev & 0x0000FFFF;
2247 break;
2248
2249 case 0x118A0000:
2250 case 0x117A0000:
2251 case 0x116A0000:
2252 case 0x115A0000:
2253 /* LAN921[5678] family */
2254 pdata->generation = 3;
2255 break;
2256
2257 case 0x92100000:
2258 case 0x92110000:
2259 case 0x92200000:
2260 case 0x92210000:
2261 /* LAN9210/LAN9211/LAN9220/LAN9221 */
2262 pdata->generation = 4;
2263 break;
2264
2265 default:
dffc6b24
JP		 2266 SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
2267 pdata->idrev);
fd9abb3d
SG		 2268 return -ENODEV;
2269 }
2270
dffc6b24
JP		 2271 SMSC_TRACE(pdata, probe,
2272 "LAN911x identified, idrev: 0x%08X, generation: %d",
2273 pdata->idrev, pdata->generation);
fd9abb3d
SG		 2274
2275 if (pdata->generation == 0)
dffc6b24
JP		 2276 SMSC_WARN(pdata, probe,
2277 "This driver is not intended for this chip revision");
fd9abb3d 2278
31f45747
SG		 2279 /* workaround for platforms without an eeprom, where the mac address
2280 * is stored elsewhere and set by the bootloader. This saves the
2281 * mac address before resetting the device */
35a67edf
EBS		 2282 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
2283 spin_lock_irq(&pdata->mac_lock);
31f45747 2284 smsc911x_read_mac_address(dev);
35a67edf
EBS		 2285 spin_unlock_irq(&pdata->mac_lock);
2286 }
31f45747 2287
fd9abb3d 2288 /* Reset the LAN911x */
cd998ecd 2289 if (smsc911x_phy_reset(pdata) || smsc911x_soft_reset(pdata))
fd9abb3d
SG		 2290 return -ENODEV;
2291
fd9abb3d 2292 dev->flags |= IFF_MULTICAST;
fd9abb3d 2293 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 2294 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 2295 dev->ethtool_ops = &smsc911x_ethtool_ops;
2296
fd9abb3d
SG		 2297 return 0;
2298}
2299
8489ec1f 2300static int smsc911x_drv_remove(struct platform_device *pdev)
fd9abb3d
SG		 2301{
2302 struct net_device *dev;
2303 struct smsc911x_data *pdata;
2304 struct resource *res;
2305
2306 dev = platform_get_drvdata(pdev);
2307 BUG_ON(!dev);
2308 pdata = netdev_priv(dev);
2309 BUG_ON(!pdata);
2310 BUG_ON(!pdata->ioaddr);
2311 BUG_ON(!pdata->phy_dev);
2312
dffc6b24 2313 SMSC_TRACE(pdata, ifdown, "Stopping driver");
fd9abb3d
SG		 2314
2315 phy_disconnect(pdata->phy_dev);
2316 pdata->phy_dev = NULL;
2317 mdiobus_unregister(pdata->mii_bus);
2318 mdiobus_free(pdata->mii_bus);
2319
fd9abb3d
SG		 2320 unregister_netdev(dev);
2321 free_irq(dev->irq, dev);
2322 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2323 "smsc911x-memory");
2324 if (!res)
d4522739 2325 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d 2326
39424539 2327 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2328
2329 iounmap(pdata->ioaddr);
2330
c7e963f6
RM		 2331 (void)smsc911x_disable_resources(pdev);
2332 smsc911x_free_resources(pdev);
2333
fd9abb3d
SG		 2334 free_netdev(dev);
2335
3a611e26
GU		 2336 pm_runtime_put(&pdev->dev);
2337 pm_runtime_disable(&pdev->dev);
2338
fd9abb3d
SG		 2339 return 0;
2340}
2341
c326de88
MP		 2342/* standard register acces */
2343static const struct smsc911x_ops standard_smsc911x_ops = {
2344 .reg_read = __smsc911x_reg_read,
2345 .reg_write = __smsc911x_reg_write,
2346 .rx_readfifo = smsc911x_rx_readfifo,
2347 .tx_writefifo = smsc911x_tx_writefifo,
2348};
2349
2350/* shifted register access */
2351static const struct smsc911x_ops shifted_smsc911x_ops = {
2352 .reg_read = __smsc911x_reg_read_shift,
2353 .reg_write = __smsc911x_reg_write_shift,
2354 .rx_readfifo = smsc911x_rx_readfifo_shift,
2355 .tx_writefifo = smsc911x_tx_writefifo_shift,
2356};
2357
0b50dc4f
JL		 2358static int smsc911x_probe_config(struct smsc911x_platform_config *config,
2359 struct device *dev)
79f88ee9 2360{
62ee783b 2361 int phy_interface;
79f88ee9 2362 u32 width = 0;
31cb5c9e 2363 int err;
79f88ee9 2364
62ee783b
GR		 2365 phy_interface = device_get_phy_mode(dev);
2366 if (phy_interface < 0)
31cb5c9e 2367 phy_interface = PHY_INTERFACE_MODE_NA;
62ee783b 2368 config->phy_interface = phy_interface;
79f88ee9 2369
0b50dc4f 2370 device_get_mac_address(dev, config->mac, ETH_ALEN);
79f88ee9 2371
31cb5c9e
GR		 2372 err = device_property_read_u32(dev, "reg-io-width", &width);
2373 if (err == -ENXIO)
2374 return err;
2375 if (!err && width == 4)
79f88ee9 2376 config->flags |= SMSC911X_USE_32BIT;
f26cd41a
DM		 2377 else
2378 config->flags |= SMSC911X_USE_16BIT;
79f88ee9 2379
31cb5c9e
GR		 2380 device_property_read_u32(dev, "reg-shift", &config->shift);
2381
0b50dc4f 2382 if (device_property_present(dev, "smsc,irq-active-high"))
79f88ee9
SG		 2383 config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
2384
0b50dc4f 2385 if (device_property_present(dev, "smsc,irq-push-pull"))
79f88ee9
SG		 2386 config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
2387
0b50dc4f 2388 if (device_property_present(dev, "smsc,force-internal-phy"))
79f88ee9
SG		 2389 config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
2390
0b50dc4f 2391 if (device_property_present(dev, "smsc,force-external-phy"))
79f88ee9
SG		 2392 config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
2393
0b50dc4f 2394 if (device_property_present(dev, "smsc,save-mac-address"))
79f88ee9
SG		 2395 config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
2396
2397 return 0;
2398}
79f88ee9 2399
8489ec1f 2400static int smsc911x_drv_probe(struct platform_device *pdev)
fd9abb3d
SG		 2401{
2402 struct net_device *dev;
2403 struct smsc911x_data *pdata;
495c765d 2404 struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev);
965b2aa7 2405 struct resource *res;
fd9abb3d 2406 unsigned int intcfg = 0;
965b2aa7 2407 int res_size, irq, irq_flags;
fd9abb3d 2408 int retval;
fd9abb3d 2409
fd9abb3d
SG		 2410 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2411 "smsc911x-memory");
2412 if (!res)
2413 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2414 if (!res) {
dffc6b24 2415 pr_warn("Could not allocate resource\n");
fd9abb3d
SG		 2416 retval = -ENODEV;
2417 goto out_0;
2418 }
39424539 2419 res_size = resource_size(res);
fd9abb3d 2420
965b2aa7 2421 irq = platform_get_irq(pdev, 0);
f892a84c
TL		 2422 if (irq == -EPROBE_DEFER) {
2423 retval = -EPROBE_DEFER;
2424 goto out_0;
2425 } else if (irq <= 0) {
dffc6b24 2426 pr_warn("Could not allocate irq resource\n");
61307ed8
SG		 2427 retval = -ENODEV;
2428 goto out_0;
2429 }
2430
fd9abb3d
SG		 2431 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
2432 retval = -EBUSY;
2433 goto out_0;
2434 }
2435
2436 dev = alloc_etherdev(sizeof(struct smsc911x_data));
2437 if (!dev) {
fd9abb3d
SG		 2438 retval = -ENOMEM;
2439 goto out_release_io_1;
2440 }
2441
2442 SET_NETDEV_DEV(dev, &pdev->dev);
2443
2444 pdata = netdev_priv(dev);
965b2aa7
KP		 2445 dev->irq = irq;
2446 irq_flags = irq_get_trigger_type(irq);
fd9abb3d
SG		 2447 pdata->ioaddr = ioremap_nocache(res->start, res_size);
2448
fd9abb3d
SG		 2449 pdata->dev = dev;
2450 pdata->msg_enable = ((1 << debug) - 1);
2451
c7e963f6
RM		 2452 platform_set_drvdata(pdev, dev);
2453
2454 retval = smsc911x_request_resources(pdev);
2455 if (retval)
2e1d4a06 2456 goto out_request_resources_fail;
c7e963f6
RM		 2457
2458 retval = smsc911x_enable_resources(pdev);
2459 if (retval)
2e1d4a06 2460 goto out_enable_resources_fail;
c7e963f6 2461
fd9abb3d 2462 if (pdata->ioaddr == NULL) {
dffc6b24 2463 SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
fd9abb3d 2464 retval = -ENOMEM;
c7e963f6 2465 goto out_disable_resources;
fd9abb3d
SG		 2466 }
2467
0b50dc4f 2468 retval = smsc911x_probe_config(&pdata->config, &pdev->dev);
79f88ee9
SG		 2469 if (retval && config) {
2470 /* copy config parameters across to pdata */
2471 memcpy(&pdata->config, config, sizeof(pdata->config));
2472 retval = 0;
2473 }
2474
2475 if (retval) {
2476 SMSC_WARN(pdata, probe, "Error smsc911x config not found");
c7e963f6 2477 goto out_disable_resources;
79f88ee9
SG		 2478 }
2479
c326de88
MP		 2480 /* assume standard, non-shifted, access to HW registers */
2481 pdata->ops = &standard_smsc911x_ops;
2482 /* apply the right access if shifting is needed */
79f88ee9 2483 if (pdata->config.shift)
c326de88
MP		 2484 pdata->ops = &shifted_smsc911x_ops;
2485
3a611e26
GU		 2486 pm_runtime_enable(&pdev->dev);
2487 pm_runtime_get_sync(&pdev->dev);
2488
fd9abb3d
SG		 2489 retval = smsc911x_init(dev);
2490 if (retval < 0)
c7e963f6 2491 goto out_disable_resources;
fd9abb3d
SG		 2492
2493 /* configure irq polarity and type before connecting isr */
2107fb8b 2494 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2495 intcfg |= INT_CFG_IRQ_POL_;
2496
2107fb8b 2497 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2498 intcfg |= INT_CFG_IRQ_TYPE_;
2499
2500 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2501
2502 /* Ensure interrupts are globally disabled before connecting ISR */
8e27628e 2503 smsc911x_disable_irq_chip(dev);
fd9abb3d 2504
61307ed8 2505 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2506 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d 2507 if (retval) {
dffc6b24
JP		 2508 SMSC_WARN(pdata, probe,
2509 "Unable to claim requested irq: %d", dev->irq);
163faf31 2510 goto out_disable_resources;
fd9abb3d
SG		 2511 }
2512
31f6f291
BK		 2513 netif_carrier_off(dev);
2514
fd9abb3d
SG		 2515 retval = register_netdev(dev);
2516 if (retval) {
dffc6b24 2517 SMSC_WARN(pdata, probe, "Error %i registering device", retval);
c7e963f6 2518 goto out_free_irq;
fd9abb3d 2519 } else {
dffc6b24
JP		 2520 SMSC_TRACE(pdata, probe,
2521 "Network interface: \"%s\"", dev->name);
fd9abb3d
SG		 2522 }
2523
fd9abb3d
SG		 2524 retval = smsc911x_mii_init(pdev, dev);
2525 if (retval) {
dffc6b24 2526 SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
fd9abb3d
SG		 2527 goto out_unregister_netdev_5;
2528 }
2529
2530 spin_lock_irq(&pdata->mac_lock);
2531
2532 /* Check if mac address has been specified when bringing interface up */
2533 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2534 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
dffc6b24
JP		 2535 SMSC_TRACE(pdata, probe,
2536 "MAC Address is specified by configuration");
aace4959 2537 } else if (is_valid_ether_addr(pdata->config.mac)) {
d458cdf7 2538 memcpy(dev->dev_addr, pdata->config.mac, ETH_ALEN);
dffc6b24
JP		 2539 SMSC_TRACE(pdata, probe,
2540 "MAC Address specified by platform data");
fd9abb3d
SG		 2541 } else {
2542 /* Try reading mac address from device. if EEPROM is present
2543 * it will already have been set */
62747cd2 2544 smsc_get_mac(dev);
fd9abb3d
SG		 2545
2546 if (is_valid_ether_addr(dev->dev_addr)) {
2547 /* eeprom values are valid so use them */
dffc6b24
JP		 2548 SMSC_TRACE(pdata, probe,
2549 "Mac Address is read from LAN911x EEPROM");
fd9abb3d
SG		 2550 } else {
2551 /* eeprom values are invalid, generate random MAC */
7ce5d222 2552 eth_hw_addr_random(dev);
225ddf49 2553 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
dffc6b24 2554 SMSC_TRACE(pdata, probe,
7efd26d0 2555 "MAC Address is set to eth_random_addr");
fd9abb3d
SG		 2556 }
2557 }
2558
2559 spin_unlock_irq(&pdata->mac_lock);
2560
dffc6b24 2561 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2562
2563 return 0;
2564
2565out_unregister_netdev_5:
2566 unregister_netdev(dev);
c7e963f6 2567out_free_irq:
fd9abb3d 2568 free_irq(dev->irq, dev);
c7e963f6 2569out_disable_resources:
3a611e26
GU		 2570 pm_runtime_put(&pdev->dev);
2571 pm_runtime_disable(&pdev->dev);
c7e963f6 2572 (void)smsc911x_disable_resources(pdev);
2e1d4a06 2573out_enable_resources_fail:
c7e963f6 2574 smsc911x_free_resources(pdev);
2e1d4a06 2575out_request_resources_fail:
fd9abb3d 2576 iounmap(pdata->ioaddr);
fd9abb3d
SG		 2577 free_netdev(dev);
2578out_release_io_1:
39424539 2579 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2580out_0:
2581 return retval;
2582}
2583
b6907b0c
DM		 2584#ifdef CONFIG_PM
2585/* This implementation assumes the devices remains powered on its VDDVARIO
2586 * pins during suspend. */
2587
6cb87823
DM		 2588/* TODO: implement freeze/thaw callbacks for hibernation.*/
2589
2590static int smsc911x_suspend(struct device *dev)
b6907b0c 2591{
6cb87823
DM		 2592 struct net_device *ndev = dev_get_drvdata(dev);
2593 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2594
2595 /* enable wake on LAN, energy detection and the external PME
2596 * signal. */
2597 smsc911x_reg_write(pdata, PMT_CTRL,
2598 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2599 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2600
2601 return 0;
2602}
2603
6cb87823 2604static int smsc911x_resume(struct device *dev)
b6907b0c 2605{
6cb87823
DM		 2606 struct net_device *ndev = dev_get_drvdata(dev);
2607 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2608 unsigned int to = 100;
2609
2610 /* Note 3.11 from the datasheet:
2611 * "When the LAN9220 is in a power saving state, a write of any
2612 * data to the BYTE_TEST register will wake-up the device."
2613 */
2614 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2615
2616 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2617 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2618 * if it failed. */
2619 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2620 udelay(1000);
2621
2622 return (to == 0) ? -EIO : 0;
2623}
2624
47145210 2625static const struct dev_pm_ops smsc911x_pm_ops = {
6cb87823
DM		 2626 .suspend = smsc911x_suspend,
2627 .resume = smsc911x_resume,
2628};
2629
2630#define SMSC911X_PM_OPS (&smsc911x_pm_ops)
2631
b6907b0c 2632#else
6cb87823 2633#define SMSC911X_PM_OPS NULL
b6907b0c
DM		 2634#endif
2635
d62fdf8b 2636#ifdef CONFIG_OF
79f88ee9
SG		 2637static const struct of_device_id smsc911x_dt_ids[] = {
2638 { .compatible = "smsc,lan9115", },
2639 { /* sentinel */ }
2640};
2641MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
d62fdf8b 2642#endif
79f88ee9 2643
0b50dc4f
JL		 2644static const struct acpi_device_id smsc911x_acpi_match[] = {
2645 { "ARMH9118", 0 },
2646 { }
2647};
2648MODULE_DEVICE_TABLE(acpi, smsc911x_acpi_match);
2649
fd9abb3d
SG		 2650static struct platform_driver smsc911x_driver = {
2651 .probe = smsc911x_drv_probe,
8489ec1f 2652 .remove = smsc911x_drv_remove,
fd9abb3d 2653 .driver = {
6cb87823 2654 .name = SMSC_CHIPNAME,
6cb87823 2655 .pm = SMSC911X_PM_OPS,
d62fdf8b 2656 .of_match_table = of_match_ptr(smsc911x_dt_ids),
0b50dc4f 2657 .acpi_match_table = ACPI_PTR(smsc911x_acpi_match),
fd9abb3d
SG		 2658 },
2659};
2660
2661/* Entry point for loading the module */
2662static int __init smsc911x_init_module(void)
2663{
62747cd2 2664 SMSC_INITIALIZE();
fd9abb3d
SG		 2665 return platform_driver_register(&smsc911x_driver);
2666}
2667
2668/* entry point for unloading the module */
2669static void __exit smsc911x_cleanup_module(void)
2670{
2671 platform_driver_unregister(&smsc911x_driver);
2672}
2673
2674module_init(smsc911x_init_module);
2675module_exit(smsc911x_cleanup_module);
Linux 6.x block layer and io_uring tree(s)