Commit | Line | Data |
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c1b6a3d8 TB |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Driver for SGI's IOC3 based Ethernet cards as found in the PCI card. | |
1da177e4 | 3 | * |
bbfb86c5 | 4 | * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle |
1da177e4 LT |
5 | * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc. |
6 | * | |
7 | * References: | |
8 | * o IOC3 ASIC specification 4.51, 1996-04-18 | |
9 | * o IEEE 802.3 specification, 2000 edition | |
10 | * o DP38840A Specification, National Semiconductor, March 1997 | |
11 | * | |
12 | * To do: | |
13 | * | |
1da177e4 LT |
14 | * o Use prefetching for large packets. What is a good lower limit for |
15 | * prefetching? | |
1da177e4 LT |
16 | * o Use hardware checksums. |
17 | * o Convert to using a IOC3 meta driver. | |
18 | * o Which PHYs might possibly be attached to the IOC3 in real live, | |
19 | * which workarounds are required for them? Do we ever have Lucent's? | |
20 | * o For the 2.5 branch kill the mii-tool ioctls. | |
21 | */ | |
22 | ||
23 | #define IOC3_NAME "ioc3-eth" | |
d5b20697 | 24 | #define IOC3_VERSION "2.6.3-4" |
1da177e4 | 25 | |
1da177e4 LT |
26 | #include <linux/delay.h> |
27 | #include <linux/kernel.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/crc32.h> | |
33 | #include <linux/mii.h> | |
34 | #include <linux/in.h> | |
c1b6a3d8 | 35 | #include <linux/io.h> |
1da177e4 LT |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
38 | #include <linux/udp.h> | |
5a0e3ad6 | 39 | #include <linux/gfp.h> |
1da177e4 LT |
40 | |
41 | #ifdef CONFIG_SERIAL_8250 | |
15a93807 RB |
42 | #include <linux/serial_core.h> |
43 | #include <linux/serial_8250.h> | |
0491d1f3 | 44 | #include <linux/serial_reg.h> |
1da177e4 LT |
45 | #endif |
46 | ||
47 | #include <linux/netdevice.h> | |
48 | #include <linux/etherdevice.h> | |
49 | #include <linux/ethtool.h> | |
50 | #include <linux/skbuff.h> | |
4dd14747 | 51 | #include <linux/dma-mapping.h> |
ed870f6a | 52 | |
1da177e4 LT |
53 | #include <net/ip.h> |
54 | ||
55 | #include <asm/byteorder.h> | |
1da177e4 | 56 | #include <asm/pgtable.h> |
7c0f6ba6 | 57 | #include <linux/uaccess.h> |
1da177e4 | 58 | #include <asm/sn/types.h> |
1da177e4 | 59 | #include <asm/sn/ioc3.h> |
1da177e4 LT |
60 | #include <asm/pci/bridge.h> |
61 | ||
141a7dbb TB |
62 | /* Number of RX buffers. This is tunable in the range of 16 <= x < 512. |
63 | * The value must be a power of two. | |
1da177e4 | 64 | */ |
141a7dbb TB |
65 | #define RX_BUFFS 64 |
66 | #define RX_RING_ENTRIES 512 /* fixed in hardware */ | |
67 | #define RX_RING_MASK (RX_RING_ENTRIES - 1) | |
ed870f6a | 68 | #define RX_RING_SIZE (RX_RING_ENTRIES * sizeof(u64)) |
141a7dbb TB |
69 | |
70 | /* 128 TX buffers (not tunable) */ | |
71 | #define TX_RING_ENTRIES 128 | |
72 | #define TX_RING_MASK (TX_RING_ENTRIES - 1) | |
ed870f6a | 73 | #define TX_RING_SIZE (TX_RING_ENTRIES * sizeof(struct ioc3_etxd)) |
1da177e4 | 74 | |
850d2fed TB |
75 | /* IOC3 does dma transfers in 128 byte blocks */ |
76 | #define IOC3_DMA_XFER_LEN 128UL | |
77 | ||
78 | /* Every RX buffer starts with 8 byte descriptor data */ | |
79 | #define RX_OFFSET (sizeof(struct ioc3_erxbuf) + NET_IP_ALIGN) | |
80 | #define RX_BUF_SIZE (13 * IOC3_DMA_XFER_LEN) | |
81 | ||
3498cb27 TB |
82 | #define ETCSR_FD ((21 << ETCSR_IPGR2_SHIFT) | (21 << ETCSR_IPGR1_SHIFT) | 21) |
83 | #define ETCSR_HD ((17 << ETCSR_IPGR2_SHIFT) | (11 << ETCSR_IPGR1_SHIFT) | 21) | |
1da177e4 LT |
84 | |
85 | /* Private per NIC data of the driver. */ | |
86 | struct ioc3_private { | |
cbe7d517 TB |
87 | struct ioc3_ethregs *regs; |
88 | struct ioc3 *all_regs; | |
ed870f6a | 89 | struct device *dma_dev; |
cbe7d517 | 90 | u32 *ssram; |
1da177e4 LT |
91 | unsigned long *rxr; /* pointer to receiver ring */ |
92 | struct ioc3_etxd *txr; | |
ed870f6a TB |
93 | dma_addr_t rxr_dma; |
94 | dma_addr_t txr_dma; | |
141a7dbb TB |
95 | struct sk_buff *rx_skbs[RX_RING_ENTRIES]; |
96 | struct sk_buff *tx_skbs[TX_RING_ENTRIES]; | |
1da177e4 LT |
97 | int rx_ci; /* RX consumer index */ |
98 | int rx_pi; /* RX producer index */ | |
99 | int tx_ci; /* TX consumer index */ | |
100 | int tx_pi; /* TX producer index */ | |
101 | int txqlen; | |
102 | u32 emcr, ehar_h, ehar_l; | |
103 | spinlock_t ioc3_lock; | |
104 | struct mii_if_info mii; | |
bbfb86c5 | 105 | |
dfcc16c9 | 106 | struct net_device *dev; |
1da177e4 LT |
107 | struct pci_dev *pdev; |
108 | ||
109 | /* Members used by autonegotiation */ | |
110 | struct timer_list ioc3_timer; | |
111 | }; | |
112 | ||
1da177e4 LT |
113 | static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
114 | static void ioc3_set_multicast_list(struct net_device *dev); | |
28d304ef | 115 | static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev); |
1da177e4 LT |
116 | static void ioc3_timeout(struct net_device *dev); |
117 | static inline unsigned int ioc3_hash(const unsigned char *addr); | |
fcd0da5a | 118 | static void ioc3_start(struct ioc3_private *ip); |
1da177e4 LT |
119 | static inline void ioc3_stop(struct ioc3_private *ip); |
120 | static void ioc3_init(struct net_device *dev); | |
850d2fed | 121 | static int ioc3_alloc_rx_bufs(struct net_device *dev); |
19a957b6 TB |
122 | static void ioc3_free_rx_bufs(struct ioc3_private *ip); |
123 | static inline void ioc3_clean_tx_ring(struct ioc3_private *ip); | |
1da177e4 LT |
124 | |
125 | static const char ioc3_str[] = "IOC3 Ethernet"; | |
7282d491 | 126 | static const struct ethtool_ops ioc3_ethtool_ops; |
1da177e4 | 127 | |
1da177e4 LT |
128 | |
129 | static inline unsigned long aligned_rx_skb_addr(unsigned long addr) | |
130 | { | |
850d2fed | 131 | return (~addr + 1) & (IOC3_DMA_XFER_LEN - 1UL); |
1da177e4 LT |
132 | } |
133 | ||
ed870f6a TB |
134 | static inline int ioc3_alloc_skb(struct ioc3_private *ip, struct sk_buff **skb, |
135 | struct ioc3_erxbuf **rxb, dma_addr_t *rxb_dma) | |
1da177e4 | 136 | { |
850d2fed | 137 | struct sk_buff *new_skb; |
ed870f6a | 138 | dma_addr_t d; |
850d2fed | 139 | int offset; |
1da177e4 | 140 | |
850d2fed TB |
141 | new_skb = alloc_skb(RX_BUF_SIZE + IOC3_DMA_XFER_LEN - 1, GFP_ATOMIC); |
142 | if (!new_skb) | |
143 | return -ENOMEM; | |
c1b6a3d8 | 144 | |
850d2fed TB |
145 | /* ensure buffer is aligned to IOC3_DMA_XFER_LEN */ |
146 | offset = aligned_rx_skb_addr((unsigned long)new_skb->data); | |
147 | if (offset) | |
148 | skb_reserve(new_skb, offset); | |
149 | ||
ed870f6a TB |
150 | d = dma_map_single(ip->dma_dev, new_skb->data, |
151 | RX_BUF_SIZE, DMA_FROM_DEVICE); | |
152 | ||
153 | if (dma_mapping_error(ip->dma_dev, d)) { | |
154 | dev_kfree_skb_any(new_skb); | |
155 | return -ENOMEM; | |
156 | } | |
157 | *rxb_dma = d; | |
850d2fed TB |
158 | *rxb = (struct ioc3_erxbuf *)new_skb->data; |
159 | skb_reserve(new_skb, RX_OFFSET); | |
160 | *skb = new_skb; | |
1da177e4 | 161 | |
850d2fed | 162 | return 0; |
1da177e4 LT |
163 | } |
164 | ||
ed870f6a TB |
165 | #ifdef CONFIG_PCI_XTALK_BRIDGE |
166 | static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr) | |
1da177e4 | 167 | { |
ed870f6a TB |
168 | return (addr & ~PCI64_ATTR_BAR) | attr; |
169 | } | |
1da177e4 | 170 | |
ed870f6a | 171 | #define ERBAR_VAL (ERBAR_BARRIER_BIT << ERBAR_RXBARR_SHIFT) |
1da177e4 | 172 | #else |
ed870f6a TB |
173 | static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr) |
174 | { | |
175 | return addr; | |
1da177e4 | 176 | } |
ed870f6a TB |
177 | |
178 | #define ERBAR_VAL 0 | |
179 | #endif | |
180 | ||
1da177e4 LT |
181 | #define IOC3_SIZE 0x100000 |
182 | ||
1da177e4 LT |
183 | static inline u32 mcr_pack(u32 pulse, u32 sample) |
184 | { | |
185 | return (pulse << 10) | (sample << 2); | |
186 | } | |
187 | ||
cbe7d517 | 188 | static int nic_wait(u32 __iomem *mcr) |
1da177e4 | 189 | { |
cbe7d517 | 190 | u32 m; |
1da177e4 | 191 | |
cbe7d517 TB |
192 | do { |
193 | m = readl(mcr); | |
194 | } while (!(m & 2)); | |
1da177e4 | 195 | |
cbe7d517 | 196 | return m & 1; |
1da177e4 LT |
197 | } |
198 | ||
cbe7d517 | 199 | static int nic_reset(u32 __iomem *mcr) |
1da177e4 | 200 | { |
c1b6a3d8 | 201 | int presence; |
1da177e4 | 202 | |
cbe7d517 TB |
203 | writel(mcr_pack(500, 65), mcr); |
204 | presence = nic_wait(mcr); | |
1da177e4 | 205 | |
cbe7d517 TB |
206 | writel(mcr_pack(0, 500), mcr); |
207 | nic_wait(mcr); | |
1da177e4 | 208 | |
c1b6a3d8 | 209 | return presence; |
1da177e4 LT |
210 | } |
211 | ||
cbe7d517 | 212 | static inline int nic_read_bit(u32 __iomem *mcr) |
1da177e4 LT |
213 | { |
214 | int result; | |
215 | ||
cbe7d517 TB |
216 | writel(mcr_pack(6, 13), mcr); |
217 | result = nic_wait(mcr); | |
218 | writel(mcr_pack(0, 100), mcr); | |
219 | nic_wait(mcr); | |
1da177e4 LT |
220 | |
221 | return result; | |
222 | } | |
223 | ||
cbe7d517 | 224 | static inline void nic_write_bit(u32 __iomem *mcr, int bit) |
1da177e4 LT |
225 | { |
226 | if (bit) | |
cbe7d517 | 227 | writel(mcr_pack(6, 110), mcr); |
1da177e4 | 228 | else |
cbe7d517 | 229 | writel(mcr_pack(80, 30), mcr); |
1da177e4 | 230 | |
cbe7d517 | 231 | nic_wait(mcr); |
1da177e4 LT |
232 | } |
233 | ||
c1b6a3d8 | 234 | /* Read a byte from an iButton device |
1da177e4 | 235 | */ |
cbe7d517 | 236 | static u32 nic_read_byte(u32 __iomem *mcr) |
1da177e4 LT |
237 | { |
238 | u32 result = 0; | |
239 | int i; | |
240 | ||
241 | for (i = 0; i < 8; i++) | |
cbe7d517 | 242 | result = (result >> 1) | (nic_read_bit(mcr) << 7); |
1da177e4 LT |
243 | |
244 | return result; | |
245 | } | |
246 | ||
c1b6a3d8 | 247 | /* Write a byte to an iButton device |
1da177e4 | 248 | */ |
cbe7d517 | 249 | static void nic_write_byte(u32 __iomem *mcr, int byte) |
1da177e4 LT |
250 | { |
251 | int i, bit; | |
252 | ||
253 | for (i = 8; i; i--) { | |
254 | bit = byte & 1; | |
255 | byte >>= 1; | |
256 | ||
cbe7d517 | 257 | nic_write_bit(mcr, bit); |
1da177e4 LT |
258 | } |
259 | } | |
260 | ||
cbe7d517 | 261 | static u64 nic_find(u32 __iomem *mcr, int *last) |
1da177e4 LT |
262 | { |
263 | int a, b, index, disc; | |
264 | u64 address = 0; | |
265 | ||
cbe7d517 | 266 | nic_reset(mcr); |
1da177e4 | 267 | /* Search ROM. */ |
cbe7d517 | 268 | nic_write_byte(mcr, 0xf0); |
1da177e4 LT |
269 | |
270 | /* Algorithm from ``Book of iButton Standards''. */ | |
271 | for (index = 0, disc = 0; index < 64; index++) { | |
cbe7d517 TB |
272 | a = nic_read_bit(mcr); |
273 | b = nic_read_bit(mcr); | |
1da177e4 LT |
274 | |
275 | if (a && b) { | |
c1b6a3d8 | 276 | pr_warn("NIC search failed (not fatal).\n"); |
1da177e4 LT |
277 | *last = 0; |
278 | return 0; | |
279 | } | |
280 | ||
281 | if (!a && !b) { | |
282 | if (index == *last) { | |
283 | address |= 1UL << index; | |
284 | } else if (index > *last) { | |
285 | address &= ~(1UL << index); | |
286 | disc = index; | |
c1b6a3d8 | 287 | } else if ((address & (1UL << index)) == 0) { |
1da177e4 | 288 | disc = index; |
c1b6a3d8 | 289 | } |
cbe7d517 | 290 | nic_write_bit(mcr, address & (1UL << index)); |
1da177e4 LT |
291 | continue; |
292 | } else { | |
293 | if (a) | |
294 | address |= 1UL << index; | |
295 | else | |
296 | address &= ~(1UL << index); | |
cbe7d517 | 297 | nic_write_bit(mcr, a); |
1da177e4 LT |
298 | continue; |
299 | } | |
300 | } | |
301 | ||
302 | *last = disc; | |
303 | ||
304 | return address; | |
305 | } | |
306 | ||
cbe7d517 | 307 | static int nic_init(u32 __iomem *mcr) |
1da177e4 | 308 | { |
f49343a5 AC |
309 | const char *unknown = "unknown"; |
310 | const char *type = unknown; | |
1da177e4 LT |
311 | u8 crc; |
312 | u8 serial[6]; | |
313 | int save = 0, i; | |
314 | ||
1da177e4 LT |
315 | while (1) { |
316 | u64 reg; | |
c1b6a3d8 | 317 | |
cbe7d517 | 318 | reg = nic_find(mcr, &save); |
1da177e4 LT |
319 | |
320 | switch (reg & 0xff) { | |
321 | case 0x91: | |
322 | type = "DS1981U"; | |
323 | break; | |
324 | default: | |
325 | if (save == 0) { | |
326 | /* Let the caller try again. */ | |
327 | return -1; | |
328 | } | |
329 | continue; | |
330 | } | |
331 | ||
cbe7d517 | 332 | nic_reset(mcr); |
1da177e4 LT |
333 | |
334 | /* Match ROM. */ | |
cbe7d517 | 335 | nic_write_byte(mcr, 0x55); |
1da177e4 | 336 | for (i = 0; i < 8; i++) |
cbe7d517 | 337 | nic_write_byte(mcr, (reg >> (i << 3)) & 0xff); |
1da177e4 LT |
338 | |
339 | reg >>= 8; /* Shift out type. */ | |
340 | for (i = 0; i < 6; i++) { | |
341 | serial[i] = reg & 0xff; | |
342 | reg >>= 8; | |
343 | } | |
344 | crc = reg & 0xff; | |
345 | break; | |
346 | } | |
347 | ||
c1b6a3d8 | 348 | pr_info("Found %s NIC", type); |
7c510e4b | 349 | if (type != unknown) |
c1b6a3d8 TB |
350 | pr_cont(" registration number %pM, CRC %02x", serial, crc); |
351 | pr_cont(".\n"); | |
1da177e4 LT |
352 | |
353 | return 0; | |
354 | } | |
355 | ||
c1b6a3d8 | 356 | /* Read the NIC (Number-In-a-Can) device used to store the MAC address on |
1da177e4 LT |
357 | * SN0 / SN00 nodeboards and PCI cards. |
358 | */ | |
359 | static void ioc3_get_eaddr_nic(struct ioc3_private *ip) | |
360 | { | |
cbe7d517 | 361 | u32 __iomem *mcr = &ip->all_regs->mcr; |
1da177e4 | 362 | int tries = 2; /* There may be some problem with the battery? */ |
cbe7d517 | 363 | u8 nic[14]; |
1da177e4 LT |
364 | int i; |
365 | ||
cbe7d517 | 366 | writel(1 << 21, &ip->all_regs->gpcr_s); |
1da177e4 LT |
367 | |
368 | while (tries--) { | |
cbe7d517 | 369 | if (!nic_init(mcr)) |
1da177e4 LT |
370 | break; |
371 | udelay(500); | |
372 | } | |
373 | ||
374 | if (tries < 0) { | |
c1b6a3d8 | 375 | pr_err("Failed to read MAC address\n"); |
1da177e4 LT |
376 | return; |
377 | } | |
378 | ||
379 | /* Read Memory. */ | |
cbe7d517 TB |
380 | nic_write_byte(mcr, 0xf0); |
381 | nic_write_byte(mcr, 0x00); | |
382 | nic_write_byte(mcr, 0x00); | |
1da177e4 LT |
383 | |
384 | for (i = 13; i >= 0; i--) | |
cbe7d517 | 385 | nic[i] = nic_read_byte(mcr); |
1da177e4 LT |
386 | |
387 | for (i = 2; i < 8; i++) | |
dfcc16c9 | 388 | ip->dev->dev_addr[i - 2] = nic[i]; |
1da177e4 LT |
389 | } |
390 | ||
c1b6a3d8 | 391 | /* Ok, this is hosed by design. It's necessary to know what machine the |
1da177e4 LT |
392 | * NIC is in in order to know how to read the NIC address. We also have |
393 | * to know if it's a PCI card or a NIC in on the node board ... | |
394 | */ | |
395 | static void ioc3_get_eaddr(struct ioc3_private *ip) | |
396 | { | |
1da177e4 LT |
397 | ioc3_get_eaddr_nic(ip); |
398 | ||
c1b6a3d8 | 399 | pr_info("Ethernet address is %pM.\n", ip->dev->dev_addr); |
1da177e4 LT |
400 | } |
401 | ||
402 | static void __ioc3_set_mac_address(struct net_device *dev) | |
403 | { | |
404 | struct ioc3_private *ip = netdev_priv(dev); | |
1da177e4 | 405 | |
cbe7d517 TB |
406 | writel((dev->dev_addr[5] << 8) | |
407 | dev->dev_addr[4], | |
408 | &ip->regs->emar_h); | |
409 | writel((dev->dev_addr[3] << 24) | | |
410 | (dev->dev_addr[2] << 16) | | |
411 | (dev->dev_addr[1] << 8) | | |
412 | dev->dev_addr[0], | |
413 | &ip->regs->emar_l); | |
1da177e4 LT |
414 | } |
415 | ||
416 | static int ioc3_set_mac_address(struct net_device *dev, void *addr) | |
417 | { | |
418 | struct ioc3_private *ip = netdev_priv(dev); | |
419 | struct sockaddr *sa = addr; | |
420 | ||
421 | memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); | |
422 | ||
423 | spin_lock_irq(&ip->ioc3_lock); | |
424 | __ioc3_set_mac_address(dev); | |
425 | spin_unlock_irq(&ip->ioc3_lock); | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
c1b6a3d8 | 430 | /* Caller must hold the ioc3_lock ever for MII readers. This is also |
1da177e4 LT |
431 | * used to protect the transmitter side but it's low contention. |
432 | */ | |
433 | static int ioc3_mdio_read(struct net_device *dev, int phy, int reg) | |
434 | { | |
435 | struct ioc3_private *ip = netdev_priv(dev); | |
cbe7d517 | 436 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 437 | |
cbe7d517 TB |
438 | while (readl(®s->micr) & MICR_BUSY) |
439 | ; | |
440 | writel((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG, | |
441 | ®s->micr); | |
442 | while (readl(®s->micr) & MICR_BUSY) | |
443 | ; | |
1da177e4 | 444 | |
cbe7d517 | 445 | return readl(®s->midr_r) & MIDR_DATA_MASK; |
1da177e4 LT |
446 | } |
447 | ||
448 | static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data) | |
449 | { | |
450 | struct ioc3_private *ip = netdev_priv(dev); | |
cbe7d517 TB |
451 | struct ioc3_ethregs *regs = ip->regs; |
452 | ||
453 | while (readl(®s->micr) & MICR_BUSY) | |
454 | ; | |
455 | writel(data, ®s->midr_w); | |
456 | writel((phy << MICR_PHYADDR_SHIFT) | reg, ®s->micr); | |
457 | while (readl(®s->micr) & MICR_BUSY) | |
458 | ; | |
1da177e4 LT |
459 | } |
460 | ||
461 | static int ioc3_mii_init(struct ioc3_private *ip); | |
462 | ||
463 | static struct net_device_stats *ioc3_get_stats(struct net_device *dev) | |
464 | { | |
465 | struct ioc3_private *ip = netdev_priv(dev); | |
cbe7d517 | 466 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 467 | |
cbe7d517 | 468 | dev->stats.collisions += readl(®s->etcdc) & ETCDC_COLLCNT_MASK; |
0a17ee90 | 469 | return &dev->stats; |
1da177e4 LT |
470 | } |
471 | ||
c1b6a3d8 | 472 | static void ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len) |
1da177e4 LT |
473 | { |
474 | struct ethhdr *eh = eth_hdr(skb); | |
1da177e4 | 475 | unsigned int proto; |
1da177e4 | 476 | unsigned char *cp; |
c1b6a3d8 TB |
477 | struct iphdr *ih; |
478 | u32 csum, ehsum; | |
479 | u16 *ew; | |
1da177e4 | 480 | |
c1b6a3d8 | 481 | /* Did hardware handle the checksum at all? The cases we can handle |
1da177e4 LT |
482 | * are: |
483 | * | |
484 | * - TCP and UDP checksums of IPv4 only. | |
485 | * - IPv6 would be doable but we keep that for later ... | |
486 | * - Only unfragmented packets. Did somebody already tell you | |
487 | * fragmentation is evil? | |
488 | * - don't care about packet size. Worst case when processing a | |
489 | * malformed packet we'll try to access the packet at ip header + | |
490 | * 64 bytes which is still inside the skb. Even in the unlikely | |
491 | * case where the checksum is right the higher layers will still | |
492 | * drop the packet as appropriate. | |
493 | */ | |
17d0cdfa | 494 | if (eh->h_proto != htons(ETH_P_IP)) |
1da177e4 LT |
495 | return; |
496 | ||
c1b6a3d8 | 497 | ih = (struct iphdr *)((char *)eh + ETH_HLEN); |
56f8a75c | 498 | if (ip_is_fragment(ih)) |
1da177e4 LT |
499 | return; |
500 | ||
501 | proto = ih->protocol; | |
502 | if (proto != IPPROTO_TCP && proto != IPPROTO_UDP) | |
503 | return; | |
504 | ||
505 | /* Same as tx - compute csum of pseudo header */ | |
506 | csum = hwsum + | |
507 | (ih->tot_len - (ih->ihl << 2)) + | |
c1b6a3d8 | 508 | htons((u16)ih->protocol) + |
1da177e4 LT |
509 | (ih->saddr >> 16) + (ih->saddr & 0xffff) + |
510 | (ih->daddr >> 16) + (ih->daddr & 0xffff); | |
511 | ||
512 | /* Sum up ethernet dest addr, src addr and protocol */ | |
c1b6a3d8 | 513 | ew = (u16 *)eh; |
1da177e4 LT |
514 | ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6]; |
515 | ||
516 | ehsum = (ehsum & 0xffff) + (ehsum >> 16); | |
517 | ehsum = (ehsum & 0xffff) + (ehsum >> 16); | |
518 | ||
519 | csum += 0xffff ^ ehsum; | |
520 | ||
521 | /* In the next step we also subtract the 1's complement | |
c1b6a3d8 TB |
522 | * checksum of the trailing ethernet CRC. |
523 | */ | |
1da177e4 LT |
524 | cp = (char *)eh + len; /* points at trailing CRC */ |
525 | if (len & 1) { | |
c1b6a3d8 TB |
526 | csum += 0xffff ^ (u16)((cp[1] << 8) | cp[0]); |
527 | csum += 0xffff ^ (u16)((cp[3] << 8) | cp[2]); | |
1da177e4 | 528 | } else { |
c1b6a3d8 TB |
529 | csum += 0xffff ^ (u16)((cp[0] << 8) | cp[1]); |
530 | csum += 0xffff ^ (u16)((cp[2] << 8) | cp[3]); | |
1da177e4 LT |
531 | } |
532 | ||
533 | csum = (csum & 0xffff) + (csum >> 16); | |
534 | csum = (csum & 0xffff) + (csum >> 16); | |
535 | ||
536 | if (csum == 0xffff) | |
537 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
538 | } | |
1da177e4 | 539 | |
0a17ee90 | 540 | static inline void ioc3_rx(struct net_device *dev) |
1da177e4 | 541 | { |
0a17ee90 | 542 | struct ioc3_private *ip = netdev_priv(dev); |
1da177e4 | 543 | struct sk_buff *skb, *new_skb; |
1da177e4 LT |
544 | int rx_entry, n_entry, len; |
545 | struct ioc3_erxbuf *rxb; | |
546 | unsigned long *rxr; | |
ed870f6a | 547 | dma_addr_t d; |
1da177e4 LT |
548 | u32 w0, err; |
549 | ||
64699336 | 550 | rxr = ip->rxr; /* Ring base */ |
1da177e4 LT |
551 | rx_entry = ip->rx_ci; /* RX consume index */ |
552 | n_entry = ip->rx_pi; | |
553 | ||
554 | skb = ip->rx_skbs[rx_entry]; | |
c1b6a3d8 | 555 | rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET); |
1da177e4 LT |
556 | w0 = be32_to_cpu(rxb->w0); |
557 | ||
558 | while (w0 & ERXBUF_V) { | |
559 | err = be32_to_cpu(rxb->err); /* It's valid ... */ | |
560 | if (err & ERXBUF_GOODPKT) { | |
561 | len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4; | |
850d2fed | 562 | skb_put(skb, len); |
0a17ee90 | 563 | skb->protocol = eth_type_trans(skb, dev); |
1da177e4 | 564 | |
ed870f6a | 565 | if (ioc3_alloc_skb(ip, &new_skb, &rxb, &d)) { |
1da177e4 | 566 | /* Ouch, drop packet and just recycle packet |
c1b6a3d8 TB |
567 | * to keep the ring filled. |
568 | */ | |
0a17ee90 | 569 | dev->stats.rx_dropped++; |
1da177e4 | 570 | new_skb = skb; |
ed870f6a | 571 | d = rxr[rx_entry]; |
1da177e4 LT |
572 | goto next; |
573 | } | |
574 | ||
6d95ff97 | 575 | if (likely(dev->features & NETIF_F_RXCSUM)) |
bbfb86c5 | 576 | ioc3_tcpudp_checksum(skb, |
c1b6a3d8 TB |
577 | w0 & ERXBUF_IPCKSUM_MASK, |
578 | len); | |
1da177e4 | 579 | |
ed870f6a TB |
580 | dma_unmap_single(ip->dma_dev, rxr[rx_entry], |
581 | RX_BUF_SIZE, DMA_FROM_DEVICE); | |
582 | ||
1da177e4 LT |
583 | netif_rx(skb); |
584 | ||
585 | ip->rx_skbs[rx_entry] = NULL; /* Poison */ | |
586 | ||
0a17ee90 RB |
587 | dev->stats.rx_packets++; /* Statistics */ |
588 | dev->stats.rx_bytes += len; | |
1da177e4 | 589 | } else { |
0a17ee90 | 590 | /* The frame is invalid and the skb never |
c1b6a3d8 TB |
591 | * reached the network layer so we can just |
592 | * recycle it. | |
593 | */ | |
0a17ee90 | 594 | new_skb = skb; |
ed870f6a | 595 | d = rxr[rx_entry]; |
0a17ee90 | 596 | dev->stats.rx_errors++; |
1da177e4 LT |
597 | } |
598 | if (err & ERXBUF_CRCERR) /* Statistics */ | |
0a17ee90 | 599 | dev->stats.rx_crc_errors++; |
1da177e4 | 600 | if (err & ERXBUF_FRAMERR) |
0a17ee90 | 601 | dev->stats.rx_frame_errors++; |
ed870f6a | 602 | |
1da177e4 LT |
603 | next: |
604 | ip->rx_skbs[n_entry] = new_skb; | |
ed870f6a | 605 | rxr[n_entry] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR)); |
1da177e4 | 606 | rxb->w0 = 0; /* Clear valid flag */ |
141a7dbb | 607 | n_entry = (n_entry + 1) & RX_RING_MASK; /* Update erpir */ |
1da177e4 LT |
608 | |
609 | /* Now go on to the next ring entry. */ | |
141a7dbb | 610 | rx_entry = (rx_entry + 1) & RX_RING_MASK; |
1da177e4 | 611 | skb = ip->rx_skbs[rx_entry]; |
c1b6a3d8 | 612 | rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET); |
1da177e4 LT |
613 | w0 = be32_to_cpu(rxb->w0); |
614 | } | |
cbe7d517 | 615 | writel((n_entry << 3) | ERPIR_ARM, &ip->regs->erpir); |
1da177e4 LT |
616 | ip->rx_pi = n_entry; |
617 | ip->rx_ci = rx_entry; | |
618 | } | |
619 | ||
0a17ee90 | 620 | static inline void ioc3_tx(struct net_device *dev) |
1da177e4 | 621 | { |
0a17ee90 | 622 | struct ioc3_private *ip = netdev_priv(dev); |
cbe7d517 | 623 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 624 | unsigned long packets, bytes; |
1da177e4 LT |
625 | int tx_entry, o_entry; |
626 | struct sk_buff *skb; | |
627 | u32 etcir; | |
628 | ||
629 | spin_lock(&ip->ioc3_lock); | |
cbe7d517 | 630 | etcir = readl(®s->etcir); |
1da177e4 | 631 | |
141a7dbb | 632 | tx_entry = (etcir >> 7) & TX_RING_MASK; |
1da177e4 LT |
633 | o_entry = ip->tx_ci; |
634 | packets = 0; | |
635 | bytes = 0; | |
636 | ||
637 | while (o_entry != tx_entry) { | |
638 | packets++; | |
639 | skb = ip->tx_skbs[o_entry]; | |
640 | bytes += skb->len; | |
d1a096c2 | 641 | dev_consume_skb_irq(skb); |
1da177e4 LT |
642 | ip->tx_skbs[o_entry] = NULL; |
643 | ||
141a7dbb | 644 | o_entry = (o_entry + 1) & TX_RING_MASK; /* Next */ |
1da177e4 | 645 | |
cbe7d517 | 646 | etcir = readl(®s->etcir); /* More pkts sent? */ |
141a7dbb | 647 | tx_entry = (etcir >> 7) & TX_RING_MASK; |
1da177e4 LT |
648 | } |
649 | ||
0a17ee90 RB |
650 | dev->stats.tx_packets += packets; |
651 | dev->stats.tx_bytes += bytes; | |
1da177e4 LT |
652 | ip->txqlen -= packets; |
653 | ||
141a7dbb | 654 | if (netif_queue_stopped(dev) && ip->txqlen < TX_RING_ENTRIES) |
0a17ee90 | 655 | netif_wake_queue(dev); |
1da177e4 LT |
656 | |
657 | ip->tx_ci = o_entry; | |
658 | spin_unlock(&ip->ioc3_lock); | |
659 | } | |
660 | ||
c1b6a3d8 | 661 | /* Deal with fatal IOC3 errors. This condition might be caused by a hard or |
1da177e4 LT |
662 | * software problems, so we should try to recover |
663 | * more gracefully if this ever happens. In theory we might be flooded | |
664 | * with such error interrupts if something really goes wrong, so we might | |
665 | * also consider to take the interface down. | |
666 | */ | |
0a17ee90 | 667 | static void ioc3_error(struct net_device *dev, u32 eisr) |
1da177e4 | 668 | { |
0a17ee90 | 669 | struct ioc3_private *ip = netdev_priv(dev); |
1da177e4 LT |
670 | |
671 | spin_lock(&ip->ioc3_lock); | |
672 | ||
673 | if (eisr & EISR_RXOFLO) | |
c1b6a3d8 | 674 | net_err_ratelimited("%s: RX overflow.\n", dev->name); |
1da177e4 | 675 | if (eisr & EISR_RXBUFOFLO) |
c1b6a3d8 | 676 | net_err_ratelimited("%s: RX buffer overflow.\n", dev->name); |
1da177e4 | 677 | if (eisr & EISR_RXMEMERR) |
c1b6a3d8 | 678 | net_err_ratelimited("%s: RX PCI error.\n", dev->name); |
1da177e4 | 679 | if (eisr & EISR_RXPARERR) |
c1b6a3d8 | 680 | net_err_ratelimited("%s: RX SSRAM parity error.\n", dev->name); |
1da177e4 | 681 | if (eisr & EISR_TXBUFUFLO) |
c1b6a3d8 | 682 | net_err_ratelimited("%s: TX buffer underflow.\n", dev->name); |
1da177e4 | 683 | if (eisr & EISR_TXMEMERR) |
c1b6a3d8 | 684 | net_err_ratelimited("%s: TX PCI error.\n", dev->name); |
1da177e4 LT |
685 | |
686 | ioc3_stop(ip); | |
19a957b6 TB |
687 | ioc3_free_rx_bufs(ip); |
688 | ioc3_clean_tx_ring(ip); | |
689 | ||
1da177e4 | 690 | ioc3_init(dev); |
850d2fed TB |
691 | if (ioc3_alloc_rx_bufs(dev)) { |
692 | netdev_err(dev, "%s: rx buffer allocation failed\n", __func__); | |
693 | spin_unlock(&ip->ioc3_lock); | |
694 | return; | |
695 | } | |
fcd0da5a | 696 | ioc3_start(ip); |
1da177e4 LT |
697 | ioc3_mii_init(ip); |
698 | ||
699 | netif_wake_queue(dev); | |
700 | ||
701 | spin_unlock(&ip->ioc3_lock); | |
702 | } | |
703 | ||
704 | /* The interrupt handler does all of the Rx thread work and cleans up | |
c1b6a3d8 TB |
705 | * after the Tx thread. |
706 | */ | |
cbe7d517 | 707 | static irqreturn_t ioc3_interrupt(int irq, void *dev_id) |
1da177e4 | 708 | { |
cbe7d517 TB |
709 | struct ioc3_private *ip = netdev_priv(dev_id); |
710 | struct ioc3_ethregs *regs = ip->regs; | |
1da177e4 LT |
711 | u32 eisr; |
712 | ||
cbe7d517 TB |
713 | eisr = readl(®s->eisr); |
714 | writel(eisr, ®s->eisr); | |
715 | readl(®s->eisr); /* Flush */ | |
1da177e4 LT |
716 | |
717 | if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR | | |
c1b6a3d8 | 718 | EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR)) |
cbe7d517 | 719 | ioc3_error(dev_id, eisr); |
1da177e4 | 720 | if (eisr & EISR_RXTIMERINT) |
cbe7d517 | 721 | ioc3_rx(dev_id); |
1da177e4 | 722 | if (eisr & EISR_TXEXPLICIT) |
cbe7d517 | 723 | ioc3_tx(dev_id); |
1da177e4 LT |
724 | |
725 | return IRQ_HANDLED; | |
726 | } | |
727 | ||
728 | static inline void ioc3_setup_duplex(struct ioc3_private *ip) | |
729 | { | |
cbe7d517 | 730 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 731 | |
d1c94542 TB |
732 | spin_lock_irq(&ip->ioc3_lock); |
733 | ||
1da177e4 | 734 | if (ip->mii.full_duplex) { |
cbe7d517 | 735 | writel(ETCSR_FD, ®s->etcsr); |
1da177e4 LT |
736 | ip->emcr |= EMCR_DUPLEX; |
737 | } else { | |
cbe7d517 | 738 | writel(ETCSR_HD, ®s->etcsr); |
1da177e4 LT |
739 | ip->emcr &= ~EMCR_DUPLEX; |
740 | } | |
cbe7d517 | 741 | writel(ip->emcr, ®s->emcr); |
d1c94542 TB |
742 | |
743 | spin_unlock_irq(&ip->ioc3_lock); | |
1da177e4 LT |
744 | } |
745 | ||
dfc57004 | 746 | static void ioc3_timer(struct timer_list *t) |
1da177e4 | 747 | { |
dfc57004 | 748 | struct ioc3_private *ip = from_timer(ip, t, ioc3_timer); |
1da177e4 LT |
749 | |
750 | /* Print the link status if it has changed */ | |
751 | mii_check_media(&ip->mii, 1, 0); | |
752 | ioc3_setup_duplex(ip); | |
753 | ||
c1b6a3d8 | 754 | ip->ioc3_timer.expires = jiffies + ((12 * HZ) / 10); /* 1.2s */ |
1da177e4 LT |
755 | add_timer(&ip->ioc3_timer); |
756 | } | |
757 | ||
c1b6a3d8 | 758 | /* Try to find a PHY. There is no apparent relation between the MII addresses |
1da177e4 LT |
759 | * in the SGI documentation and what we find in reality, so we simply probe |
760 | * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my | |
761 | * onboard IOC3s has the special oddity that probing doesn't seem to find it | |
762 | * yet the interface seems to work fine, so if probing fails we for now will | |
763 | * simply default to PHY 31 instead of bailing out. | |
764 | */ | |
765 | static int ioc3_mii_init(struct ioc3_private *ip) | |
766 | { | |
1da177e4 | 767 | int ioc3_phy_workaround = 1; |
c1b6a3d8 | 768 | int i, found = 0, res = 0; |
1da177e4 LT |
769 | u16 word; |
770 | ||
771 | for (i = 0; i < 32; i++) { | |
dfcc16c9 | 772 | word = ioc3_mdio_read(ip->dev, i, MII_PHYSID1); |
1da177e4 LT |
773 | |
774 | if (word != 0xffff && word != 0x0000) { | |
775 | found = 1; | |
776 | break; /* Found a PHY */ | |
777 | } | |
778 | } | |
779 | ||
780 | if (!found) { | |
c1b6a3d8 | 781 | if (ioc3_phy_workaround) { |
1da177e4 | 782 | i = 31; |
c1b6a3d8 | 783 | } else { |
1da177e4 LT |
784 | ip->mii.phy_id = -1; |
785 | res = -ENODEV; | |
786 | goto out; | |
787 | } | |
788 | } | |
789 | ||
790 | ip->mii.phy_id = i; | |
f0ba7358 RB |
791 | |
792 | out: | |
793 | return res; | |
794 | } | |
795 | ||
796 | static void ioc3_mii_start(struct ioc3_private *ip) | |
797 | { | |
c1b6a3d8 | 798 | ip->ioc3_timer.expires = jiffies + (12 * HZ) / 10; /* 1.2 sec. */ |
1da177e4 | 799 | add_timer(&ip->ioc3_timer); |
1da177e4 LT |
800 | } |
801 | ||
ed870f6a TB |
802 | static inline void ioc3_tx_unmap(struct ioc3_private *ip, int entry) |
803 | { | |
804 | struct ioc3_etxd *desc; | |
805 | u32 cmd, bufcnt, len; | |
806 | ||
807 | desc = &ip->txr[entry]; | |
808 | cmd = be32_to_cpu(desc->cmd); | |
809 | bufcnt = be32_to_cpu(desc->bufcnt); | |
810 | if (cmd & ETXD_B1V) { | |
811 | len = (bufcnt & ETXD_B1CNT_MASK) >> ETXD_B1CNT_SHIFT; | |
812 | dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p1), | |
813 | len, DMA_TO_DEVICE); | |
814 | } | |
815 | if (cmd & ETXD_B2V) { | |
816 | len = (bufcnt & ETXD_B2CNT_MASK) >> ETXD_B2CNT_SHIFT; | |
817 | dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p2), | |
818 | len, DMA_TO_DEVICE); | |
819 | } | |
820 | } | |
821 | ||
1da177e4 LT |
822 | static inline void ioc3_clean_tx_ring(struct ioc3_private *ip) |
823 | { | |
824 | struct sk_buff *skb; | |
825 | int i; | |
826 | ||
141a7dbb | 827 | for (i = 0; i < TX_RING_ENTRIES; i++) { |
1da177e4 LT |
828 | skb = ip->tx_skbs[i]; |
829 | if (skb) { | |
ed870f6a | 830 | ioc3_tx_unmap(ip, i); |
1da177e4 LT |
831 | ip->tx_skbs[i] = NULL; |
832 | dev_kfree_skb_any(skb); | |
833 | } | |
834 | ip->txr[i].cmd = 0; | |
835 | } | |
836 | ip->tx_pi = 0; | |
837 | ip->tx_ci = 0; | |
838 | } | |
839 | ||
9c328b05 | 840 | static void ioc3_free_rx_bufs(struct ioc3_private *ip) |
1da177e4 | 841 | { |
1da177e4 | 842 | int rx_entry, n_entry; |
ed870f6a | 843 | struct sk_buff *skb; |
1da177e4 | 844 | |
c7b57274 TB |
845 | n_entry = ip->rx_ci; |
846 | rx_entry = ip->rx_pi; | |
1da177e4 | 847 | |
c7b57274 | 848 | while (n_entry != rx_entry) { |
ed870f6a TB |
849 | skb = ip->rx_skbs[n_entry]; |
850 | if (skb) { | |
851 | dma_unmap_single(ip->dma_dev, | |
852 | be64_to_cpu(ip->rxr[n_entry]), | |
853 | RX_BUF_SIZE, DMA_FROM_DEVICE); | |
854 | dev_kfree_skb_any(skb); | |
855 | } | |
c7b57274 | 856 | n_entry = (n_entry + 1) & RX_RING_MASK; |
1da177e4 LT |
857 | } |
858 | } | |
859 | ||
850d2fed | 860 | static int ioc3_alloc_rx_bufs(struct net_device *dev) |
1da177e4 LT |
861 | { |
862 | struct ioc3_private *ip = netdev_priv(dev); | |
863 | struct ioc3_erxbuf *rxb; | |
ed870f6a | 864 | dma_addr_t d; |
1da177e4 LT |
865 | int i; |
866 | ||
c7b57274 TB |
867 | /* Now the rx buffers. The RX ring may be larger but |
868 | * we only allocate 16 buffers for now. Need to tune | |
869 | * this for performance and memory later. | |
870 | */ | |
871 | for (i = 0; i < RX_BUFFS; i++) { | |
ed870f6a | 872 | if (ioc3_alloc_skb(ip, &ip->rx_skbs[i], &rxb, &d)) |
850d2fed | 873 | return -ENOMEM; |
c7b57274 | 874 | |
489467e5 | 875 | rxb->w0 = 0; /* Clear valid flag */ |
ed870f6a | 876 | ip->rxr[i] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR)); |
1da177e4 | 877 | } |
c7b57274 TB |
878 | ip->rx_ci = 0; |
879 | ip->rx_pi = RX_BUFFS; | |
850d2fed TB |
880 | |
881 | return 0; | |
1da177e4 LT |
882 | } |
883 | ||
1da177e4 LT |
884 | static inline void ioc3_ssram_disc(struct ioc3_private *ip) |
885 | { | |
cbe7d517 TB |
886 | struct ioc3_ethregs *regs = ip->regs; |
887 | u32 *ssram0 = &ip->ssram[0x0000]; | |
888 | u32 *ssram1 = &ip->ssram[0x4000]; | |
889 | u32 pattern = 0x5555; | |
1da177e4 LT |
890 | |
891 | /* Assume the larger size SSRAM and enable parity checking */ | |
cbe7d517 TB |
892 | writel(readl(®s->emcr) | (EMCR_BUFSIZ | EMCR_RAMPAR), ®s->emcr); |
893 | readl(®s->emcr); /* Flush */ | |
1da177e4 | 894 | |
cbe7d517 TB |
895 | writel(pattern, ssram0); |
896 | writel(~pattern & IOC3_SSRAM_DM, ssram1); | |
1da177e4 | 897 | |
cbe7d517 TB |
898 | if ((readl(ssram0) & IOC3_SSRAM_DM) != pattern || |
899 | (readl(ssram1) & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) { | |
1da177e4 | 900 | /* set ssram size to 64 KB */ |
cbe7d517 TB |
901 | ip->emcr |= EMCR_RAMPAR; |
902 | writel(readl(®s->emcr) & ~EMCR_BUFSIZ, ®s->emcr); | |
903 | } else { | |
904 | ip->emcr |= EMCR_BUFSIZ | EMCR_RAMPAR; | |
905 | } | |
1da177e4 LT |
906 | } |
907 | ||
908 | static void ioc3_init(struct net_device *dev) | |
909 | { | |
910 | struct ioc3_private *ip = netdev_priv(dev); | |
cbe7d517 | 911 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 912 | |
cfadbd29 | 913 | del_timer_sync(&ip->ioc3_timer); /* Kill if running */ |
1da177e4 | 914 | |
cbe7d517 TB |
915 | writel(EMCR_RST, ®s->emcr); /* Reset */ |
916 | readl(®s->emcr); /* Flush WB */ | |
1da177e4 | 917 | udelay(4); /* Give it time ... */ |
cbe7d517 TB |
918 | writel(0, ®s->emcr); |
919 | readl(®s->emcr); | |
1da177e4 LT |
920 | |
921 | /* Misc registers */ | |
ed870f6a | 922 | writel(ERBAR_VAL, ®s->erbar); |
cbe7d517 TB |
923 | readl(®s->etcdc); /* Clear on read */ |
924 | writel(15, ®s->ercsr); /* RX low watermark */ | |
925 | writel(0, ®s->ertr); /* Interrupt immediately */ | |
1da177e4 | 926 | __ioc3_set_mac_address(dev); |
cbe7d517 TB |
927 | writel(ip->ehar_h, ®s->ehar_h); |
928 | writel(ip->ehar_l, ®s->ehar_l); | |
929 | writel(42, ®s->ersr); /* XXX should be random */ | |
fcd0da5a TB |
930 | } |
931 | ||
932 | static void ioc3_start(struct ioc3_private *ip) | |
933 | { | |
934 | struct ioc3_ethregs *regs = ip->regs; | |
935 | unsigned long ring; | |
936 | ||
937 | /* Now the rx ring base, consume & produce registers. */ | |
ed870f6a | 938 | ring = ioc3_map(ip->rxr_dma, PCI64_ATTR_PREC); |
fcd0da5a TB |
939 | writel(ring >> 32, ®s->erbr_h); |
940 | writel(ring & 0xffffffff, ®s->erbr_l); | |
941 | writel(ip->rx_ci << 3, ®s->ercir); | |
942 | writel((ip->rx_pi << 3) | ERPIR_ARM, ®s->erpir); | |
943 | ||
ed870f6a | 944 | ring = ioc3_map(ip->txr_dma, PCI64_ATTR_PREC); |
fcd0da5a TB |
945 | |
946 | ip->txqlen = 0; /* nothing queued */ | |
947 | ||
948 | /* Now the tx ring base, consume & produce registers. */ | |
949 | writel(ring >> 32, ®s->etbr_h); | |
950 | writel(ring & 0xffffffff, ®s->etbr_l); | |
951 | writel(ip->tx_pi << 7, ®s->etpir); | |
952 | writel(ip->tx_ci << 7, ®s->etcir); | |
953 | readl(®s->etcir); /* Flush */ | |
1da177e4 LT |
954 | |
955 | ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN | | |
c1b6a3d8 | 956 | EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN; |
cbe7d517 TB |
957 | writel(ip->emcr, ®s->emcr); |
958 | writel(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO | | |
959 | EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO | | |
960 | EISR_TXEXPLICIT | EISR_TXMEMERR, ®s->eier); | |
961 | readl(®s->eier); | |
1da177e4 LT |
962 | } |
963 | ||
964 | static inline void ioc3_stop(struct ioc3_private *ip) | |
965 | { | |
cbe7d517 | 966 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 967 | |
cbe7d517 TB |
968 | writel(0, ®s->emcr); /* Shutup */ |
969 | writel(0, ®s->eier); /* Disable interrupts */ | |
970 | readl(®s->eier); /* Flush */ | |
1da177e4 LT |
971 | } |
972 | ||
973 | static int ioc3_open(struct net_device *dev) | |
974 | { | |
975 | struct ioc3_private *ip = netdev_priv(dev); | |
976 | ||
1fb9df5d | 977 | if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) { |
c1b6a3d8 | 978 | netdev_err(dev, "Can't get irq %d\n", dev->irq); |
1da177e4 LT |
979 | |
980 | return -EAGAIN; | |
981 | } | |
982 | ||
983 | ip->ehar_h = 0; | |
984 | ip->ehar_l = 0; | |
19a957b6 | 985 | |
1da177e4 | 986 | ioc3_init(dev); |
850d2fed TB |
987 | if (ioc3_alloc_rx_bufs(dev)) { |
988 | netdev_err(dev, "%s: rx buffer allocation failed\n", __func__); | |
989 | return -ENOMEM; | |
990 | } | |
fcd0da5a | 991 | ioc3_start(ip); |
f0ba7358 | 992 | ioc3_mii_start(ip); |
1da177e4 LT |
993 | |
994 | netif_start_queue(dev); | |
995 | return 0; | |
996 | } | |
997 | ||
998 | static int ioc3_close(struct net_device *dev) | |
999 | { | |
1000 | struct ioc3_private *ip = netdev_priv(dev); | |
1001 | ||
cfadbd29 | 1002 | del_timer_sync(&ip->ioc3_timer); |
1da177e4 LT |
1003 | |
1004 | netif_stop_queue(dev); | |
1005 | ||
1006 | ioc3_stop(ip); | |
1007 | free_irq(dev->irq, dev); | |
1008 | ||
9c328b05 TB |
1009 | ioc3_free_rx_bufs(ip); |
1010 | ioc3_clean_tx_ring(ip); | |
1011 | ||
1da177e4 LT |
1012 | return 0; |
1013 | } | |
1014 | ||
c1b6a3d8 | 1015 | /* MENET cards have four IOC3 chips, which are attached to two sets of |
1da177e4 LT |
1016 | * PCI slot resources each: the primary connections are on slots |
1017 | * 0..3 and the secondaries are on 4..7 | |
1018 | * | |
1019 | * All four ethernets are brought out to connectors; six serial ports | |
1020 | * (a pair from each of the first three IOC3s) are brought out to | |
1021 | * MiniDINs; all other subdevices are left swinging in the wind, leave | |
1022 | * them disabled. | |
1023 | */ | |
f49343a5 AC |
1024 | |
1025 | static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot) | |
1026 | { | |
1027 | struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(slot, 0)); | |
1028 | int ret = 0; | |
1029 | ||
1030 | if (dev) { | |
1031 | if (dev->vendor == PCI_VENDOR_ID_SGI && | |
c1b6a3d8 | 1032 | dev->device == PCI_DEVICE_ID_SGI_IOC3) |
f49343a5 AC |
1033 | ret = 1; |
1034 | pci_dev_put(dev); | |
1035 | } | |
1036 | ||
1037 | return ret; | |
1038 | } | |
1039 | ||
1040 | static int ioc3_is_menet(struct pci_dev *pdev) | |
1da177e4 | 1041 | { |
c1b6a3d8 | 1042 | return !pdev->bus->parent && |
f49343a5 AC |
1043 | ioc3_adjacent_is_ioc3(pdev, 0) && |
1044 | ioc3_adjacent_is_ioc3(pdev, 1) && | |
1045 | ioc3_adjacent_is_ioc3(pdev, 2); | |
1da177e4 LT |
1046 | } |
1047 | ||
1048 | #ifdef CONFIG_SERIAL_8250 | |
c1b6a3d8 | 1049 | /* Note about serial ports and consoles: |
1da177e4 LT |
1050 | * For console output, everyone uses the IOC3 UARTA (offset 0x178) |
1051 | * connected to the master node (look in ip27_setup_console() and | |
1052 | * ip27prom_console_write()). | |
1053 | * | |
1054 | * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port | |
1055 | * addresses on a partitioned machine. Since we currently use the ioc3 | |
1056 | * serial ports, we use dynamic serial port discovery that the serial.c | |
1057 | * driver uses for pci/pnp ports (there is an entry for the SGI ioc3 | |
1058 | * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater | |
1059 | * than UARTB's, although UARTA on o200s has traditionally been known as | |
1060 | * port 0. So, we just use one serial port from each ioc3 (since the | |
1061 | * serial driver adds addresses to get to higher ports). | |
1062 | * | |
1063 | * The first one to do a register_console becomes the preferred console | |
1064 | * (if there is no kernel command line console= directive). /dev/console | |
1065 | * (ie 5, 1) is then "aliased" into the device number returned by the | |
1066 | * "device" routine referred to in this console structure | |
1067 | * (ip27prom_console_dev). | |
1068 | * | |
1069 | * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working | |
1070 | * around ioc3 oddities in this respect. | |
1071 | * | |
0491d1f3 RB |
1072 | * The IOC3 serials use a 22MHz clock rate with an additional divider which |
1073 | * can be programmed in the SCR register if the DLAB bit is set. | |
1074 | * | |
1075 | * Register to interrupt zero because we share the interrupt with | |
1076 | * the serial driver which we don't properly support yet. | |
1077 | * | |
1078 | * Can't use UPF_IOREMAP as the whole of IOC3 resources have already been | |
1079 | * registered. | |
1da177e4 | 1080 | */ |
f48a3c2a | 1081 | static void ioc3_8250_register(struct ioc3_uartregs __iomem *uart) |
0491d1f3 RB |
1082 | { |
1083 | #define COSMISC_CONSTANT 6 | |
1084 | ||
ce7240e4 | 1085 | struct uart_8250_port port = { |
c1b6a3d8 | 1086 | .port = { |
ce7240e4 AC |
1087 | .irq = 0, |
1088 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | |
1089 | .iotype = UPIO_MEM, | |
1090 | .regshift = 0, | |
1091 | .uartclk = (22000000 << 1) / COSMISC_CONSTANT, | |
1092 | ||
c1b6a3d8 TB |
1093 | .membase = (unsigned char __iomem *)uart, |
1094 | .mapbase = (unsigned long)uart, | |
1095 | } | |
0491d1f3 RB |
1096 | }; |
1097 | unsigned char lcr; | |
1098 | ||
cbe7d517 TB |
1099 | lcr = readb(&uart->iu_lcr); |
1100 | writeb(lcr | UART_LCR_DLAB, &uart->iu_lcr); | |
1101 | writeb(COSMISC_CONSTANT, &uart->iu_scr); | |
1102 | writeb(lcr, &uart->iu_lcr); | |
1103 | readb(&uart->iu_lcr); | |
ce7240e4 | 1104 | serial8250_register_8250_port(&port); |
0491d1f3 | 1105 | } |
1da177e4 | 1106 | |
f48a3c2a | 1107 | static void ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3) |
1da177e4 | 1108 | { |
cbe7d517 TB |
1109 | u32 sio_iec; |
1110 | ||
c1b6a3d8 | 1111 | /* We need to recognice and treat the fourth MENET serial as it |
1da177e4 LT |
1112 | * does not have an SuperIO chip attached to it, therefore attempting |
1113 | * to access it will result in bus errors. We call something an | |
1114 | * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3 | |
1115 | * in it. This is paranoid but we want to avoid blowing up on a | |
1116 | * showhorn PCI box that happens to have 4 IOC3 cards in it so it's | |
1117 | * not paranoid enough ... | |
1118 | */ | |
1119 | if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3) | |
1120 | return; | |
1121 | ||
c1b6a3d8 | 1122 | /* Switch IOC3 to PIO mode. It probably already was but let's be |
0491d1f3 | 1123 | * paranoid |
15a93807 | 1124 | */ |
cbe7d517 TB |
1125 | writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL, &ioc3->gpcr_s); |
1126 | readl(&ioc3->gpcr_s); | |
1127 | writel(0, &ioc3->gppr[6]); | |
1128 | readl(&ioc3->gppr[6]); | |
1129 | writel(0, &ioc3->gppr[7]); | |
1130 | readl(&ioc3->gppr[7]); | |
1131 | writel(readl(&ioc3->port_a.sscr) & ~SSCR_DMA_EN, &ioc3->port_a.sscr); | |
1132 | readl(&ioc3->port_a.sscr); | |
1133 | writel(readl(&ioc3->port_b.sscr) & ~SSCR_DMA_EN, &ioc3->port_b.sscr); | |
1134 | readl(&ioc3->port_b.sscr); | |
0491d1f3 | 1135 | /* Disable all SA/B interrupts except for SA/B_INT in SIO_IEC. */ |
cbe7d517 TB |
1136 | sio_iec = readl(&ioc3->sio_iec); |
1137 | sio_iec &= ~(SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | | |
1138 | SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | | |
1139 | SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | | |
1140 | SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR); | |
1141 | sio_iec |= SIO_IR_SA_INT; | |
1142 | sio_iec &= ~(SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | | |
1143 | SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | | |
1144 | SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | | |
1145 | SIO_IR_SB_TX_EXPLICIT | SIO_IR_SB_MEMERR); | |
1146 | sio_iec |= SIO_IR_SB_INT; | |
1147 | writel(sio_iec, &ioc3->sio_iec); | |
1148 | writel(0, &ioc3->port_a.sscr); | |
1149 | writel(0, &ioc3->port_b.sscr); | |
0491d1f3 RB |
1150 | |
1151 | ioc3_8250_register(&ioc3->sregs.uarta); | |
1152 | ioc3_8250_register(&ioc3->sregs.uartb); | |
1da177e4 LT |
1153 | } |
1154 | #endif | |
1155 | ||
2b142542 AB |
1156 | static const struct net_device_ops ioc3_netdev_ops = { |
1157 | .ndo_open = ioc3_open, | |
1158 | .ndo_stop = ioc3_close, | |
1159 | .ndo_start_xmit = ioc3_start_xmit, | |
1160 | .ndo_tx_timeout = ioc3_timeout, | |
1161 | .ndo_get_stats = ioc3_get_stats, | |
afc4b13d | 1162 | .ndo_set_rx_mode = ioc3_set_multicast_list, |
2b142542 AB |
1163 | .ndo_do_ioctl = ioc3_ioctl, |
1164 | .ndo_validate_addr = eth_validate_addr, | |
1165 | .ndo_set_mac_address = ioc3_set_mac_address, | |
2b142542 AB |
1166 | }; |
1167 | ||
1dd06ae8 | 1168 | static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
1169 | { |
1170 | unsigned int sw_physid1, sw_physid2; | |
1171 | struct net_device *dev = NULL; | |
1172 | struct ioc3_private *ip; | |
1173 | struct ioc3 *ioc3; | |
1174 | unsigned long ioc3_base, ioc3_size; | |
1175 | u32 vendor, model, rev; | |
051a07ec | 1176 | int err; |
1da177e4 LT |
1177 | |
1178 | /* Configure DMA attributes. */ | |
051a07ec CH |
1179 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
1180 | if (err) { | |
1181 | pr_err("%s: No usable DMA configuration, aborting.\n", | |
1182 | pci_name(pdev)); | |
1183 | goto out; | |
1da177e4 LT |
1184 | } |
1185 | ||
1186 | if (pci_enable_device(pdev)) | |
1187 | return -ENODEV; | |
1188 | ||
1189 | dev = alloc_etherdev(sizeof(struct ioc3_private)); | |
1190 | if (!dev) { | |
1191 | err = -ENOMEM; | |
1192 | goto out_disable; | |
1193 | } | |
1194 | ||
051a07ec | 1195 | dev->features |= NETIF_F_HIGHDMA; |
1da177e4 LT |
1196 | |
1197 | err = pci_request_regions(pdev, "ioc3"); | |
1198 | if (err) | |
1199 | goto out_free; | |
1200 | ||
1da177e4 LT |
1201 | SET_NETDEV_DEV(dev, &pdev->dev); |
1202 | ||
1203 | ip = netdev_priv(dev); | |
dfcc16c9 | 1204 | ip->dev = dev; |
ed870f6a | 1205 | ip->dma_dev = &pdev->dev; |
1da177e4 LT |
1206 | |
1207 | dev->irq = pdev->irq; | |
1208 | ||
1209 | ioc3_base = pci_resource_start(pdev, 0); | |
1210 | ioc3_size = pci_resource_len(pdev, 0); | |
c1b6a3d8 | 1211 | ioc3 = (struct ioc3 *)ioremap(ioc3_base, ioc3_size); |
1da177e4 | 1212 | if (!ioc3) { |
c1b6a3d8 | 1213 | pr_err("ioc3eth(%s): ioremap failed, goodbye.\n", |
1da177e4 LT |
1214 | pci_name(pdev)); |
1215 | err = -ENOMEM; | |
1216 | goto out_res; | |
1217 | } | |
cbe7d517 TB |
1218 | ip->regs = &ioc3->eth; |
1219 | ip->ssram = ioc3->ssram; | |
1220 | ip->all_regs = ioc3; | |
1da177e4 LT |
1221 | |
1222 | #ifdef CONFIG_SERIAL_8250 | |
1223 | ioc3_serial_probe(pdev, ioc3); | |
1224 | #endif | |
1225 | ||
1226 | spin_lock_init(&ip->ioc3_lock); | |
dfc57004 | 1227 | timer_setup(&ip->ioc3_timer, ioc3_timer, 0); |
1da177e4 LT |
1228 | |
1229 | ioc3_stop(ip); | |
c7b57274 TB |
1230 | |
1231 | /* Allocate rx ring. 4kb = 512 entries, must be 4kb aligned */ | |
4dd14747 | 1232 | ip->rxr = dma_alloc_coherent(ip->dma_dev, RX_RING_SIZE, &ip->rxr_dma, |
59511bcf | 1233 | GFP_KERNEL); |
c7b57274 TB |
1234 | if (!ip->rxr) { |
1235 | pr_err("ioc3-eth: rx ring allocation failed\n"); | |
1236 | err = -ENOMEM; | |
1237 | goto out_stop; | |
1238 | } | |
1239 | ||
1240 | /* Allocate tx rings. 16kb = 128 bufs, must be 16kb aligned */ | |
4dd14747 | 1241 | ip->txr = dma_alloc_coherent(ip->dma_dev, TX_RING_SIZE, &ip->txr_dma, |
59511bcf | 1242 | GFP_KERNEL); |
c7b57274 TB |
1243 | if (!ip->txr) { |
1244 | pr_err("ioc3-eth: tx ring allocation failed\n"); | |
1245 | err = -ENOMEM; | |
1246 | goto out_stop; | |
1247 | } | |
1248 | ||
1da177e4 LT |
1249 | ioc3_init(dev); |
1250 | ||
1251 | ip->pdev = pdev; | |
1252 | ||
1253 | ip->mii.phy_id_mask = 0x1f; | |
1254 | ip->mii.reg_num_mask = 0x1f; | |
1255 | ip->mii.dev = dev; | |
1256 | ip->mii.mdio_read = ioc3_mdio_read; | |
1257 | ip->mii.mdio_write = ioc3_mdio_write; | |
1258 | ||
1259 | ioc3_mii_init(ip); | |
1260 | ||
1261 | if (ip->mii.phy_id == -1) { | |
c1b6a3d8 | 1262 | pr_err("ioc3-eth(%s): Didn't find a PHY, goodbye.\n", |
1da177e4 LT |
1263 | pci_name(pdev)); |
1264 | err = -ENODEV; | |
1265 | goto out_stop; | |
1266 | } | |
1267 | ||
f0ba7358 | 1268 | ioc3_mii_start(ip); |
1da177e4 LT |
1269 | ioc3_ssram_disc(ip); |
1270 | ioc3_get_eaddr(ip); | |
1271 | ||
1272 | /* The IOC3-specific entries in the device structure. */ | |
1da177e4 | 1273 | dev->watchdog_timeo = 5 * HZ; |
2b142542 | 1274 | dev->netdev_ops = &ioc3_netdev_ops; |
1da177e4 | 1275 | dev->ethtool_ops = &ioc3_ethtool_ops; |
6d95ff97 | 1276 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM; |
1da177e4 | 1277 | dev->features = NETIF_F_IP_CSUM; |
1da177e4 | 1278 | |
1da177e4 LT |
1279 | sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1); |
1280 | sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2); | |
1281 | ||
1282 | err = register_netdev(dev); | |
1283 | if (err) | |
1284 | goto out_stop; | |
1285 | ||
1286 | mii_check_media(&ip->mii, 1, 1); | |
852ea22a | 1287 | ioc3_setup_duplex(ip); |
1da177e4 LT |
1288 | |
1289 | vendor = (sw_physid1 << 12) | (sw_physid2 >> 4); | |
1290 | model = (sw_physid2 >> 4) & 0x3f; | |
1291 | rev = sw_physid2 & 0xf; | |
c1b6a3d8 TB |
1292 | netdev_info(dev, "Using PHY %d, vendor 0x%x, model %d, rev %d.\n", |
1293 | ip->mii.phy_id, vendor, model, rev); | |
1294 | netdev_info(dev, "IOC3 SSRAM has %d kbyte.\n", | |
1295 | ip->emcr & EMCR_BUFSIZ ? 128 : 64); | |
1da177e4 LT |
1296 | |
1297 | return 0; | |
1298 | ||
1299 | out_stop: | |
f0ba7358 | 1300 | del_timer_sync(&ip->ioc3_timer); |
c7b57274 | 1301 | if (ip->rxr) |
4dd14747 CH |
1302 | dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr, |
1303 | ip->rxr_dma); | |
c7b57274 | 1304 | if (ip->txr) |
4dd14747 CH |
1305 | dma_free_coherent(ip->dma_dev, TX_RING_SIZE, ip->txr, |
1306 | ip->txr_dma); | |
1da177e4 LT |
1307 | out_res: |
1308 | pci_release_regions(pdev); | |
1309 | out_free: | |
1310 | free_netdev(dev); | |
1311 | out_disable: | |
c1b6a3d8 | 1312 | /* We should call pci_disable_device(pdev); here if the IOC3 wasn't |
1da177e4 LT |
1313 | * such a weird device ... |
1314 | */ | |
1315 | out: | |
1316 | return err; | |
1317 | } | |
1318 | ||
f48a3c2a | 1319 | static void ioc3_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
1320 | { |
1321 | struct net_device *dev = pci_get_drvdata(pdev); | |
1322 | struct ioc3_private *ip = netdev_priv(dev); | |
1da177e4 | 1323 | |
4dd14747 CH |
1324 | dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr, ip->rxr_dma); |
1325 | dma_free_coherent(ip->dma_dev, TX_RING_SIZE, ip->txr, ip->txr_dma); | |
c7b57274 | 1326 | |
1da177e4 | 1327 | unregister_netdev(dev); |
f0ba7358 RB |
1328 | del_timer_sync(&ip->ioc3_timer); |
1329 | ||
cbe7d517 | 1330 | iounmap(ip->all_regs); |
1da177e4 LT |
1331 | pci_release_regions(pdev); |
1332 | free_netdev(dev); | |
c1b6a3d8 | 1333 | /* We should call pci_disable_device(pdev); here if the IOC3 wasn't |
1da177e4 LT |
1334 | * such a weird device ... |
1335 | */ | |
1336 | } | |
1337 | ||
9baa3c34 | 1338 | static const struct pci_device_id ioc3_pci_tbl[] = { |
1da177e4 LT |
1339 | { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID }, |
1340 | { 0 } | |
1341 | }; | |
1342 | MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl); | |
1343 | ||
1344 | static struct pci_driver ioc3_driver = { | |
1345 | .name = "ioc3-eth", | |
1346 | .id_table = ioc3_pci_tbl, | |
1347 | .probe = ioc3_probe, | |
f48a3c2a | 1348 | .remove = ioc3_remove_one, |
1da177e4 LT |
1349 | }; |
1350 | ||
28d304ef | 1351 | static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 1352 | { |
1da177e4 | 1353 | struct ioc3_private *ip = netdev_priv(dev); |
1da177e4 | 1354 | struct ioc3_etxd *desc; |
cbe7d517 TB |
1355 | unsigned long data; |
1356 | unsigned int len; | |
1da177e4 | 1357 | int produce; |
c1b6a3d8 | 1358 | u32 w0 = 0; |
1da177e4 | 1359 | |
c1b6a3d8 | 1360 | /* IOC3 has a fairly simple minded checksumming hardware which simply |
1da177e4 LT |
1361 | * adds up the 1's complement checksum for the entire packet and |
1362 | * inserts it at an offset which can be specified in the descriptor | |
1363 | * into the transmit packet. This means we have to compensate for the | |
1364 | * MAC header which should not be summed and the TCP/UDP pseudo headers | |
1365 | * manually. | |
1366 | */ | |
84fa7933 | 1367 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 ACM |
1368 | const struct iphdr *ih = ip_hdr(skb); |
1369 | const int proto = ntohs(ih->protocol); | |
1da177e4 | 1370 | unsigned int csoff; |
c1b6a3d8 TB |
1371 | u32 csum, ehsum; |
1372 | u16 *eh; | |
1da177e4 LT |
1373 | |
1374 | /* The MAC header. skb->mac seem the logic approach | |
c1b6a3d8 TB |
1375 | * to find the MAC header - except it's a NULL pointer ... |
1376 | */ | |
1377 | eh = (u16 *)skb->data; | |
1da177e4 LT |
1378 | |
1379 | /* Sum up dest addr, src addr and protocol */ | |
1380 | ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6]; | |
1381 | ||
1da177e4 | 1382 | /* Skip IP header; it's sum is always zero and was |
c1b6a3d8 TB |
1383 | * already filled in by ip_output.c |
1384 | */ | |
1da177e4 | 1385 | csum = csum_tcpudp_nofold(ih->saddr, ih->daddr, |
c1b6a3d8 | 1386 | ih->tot_len - (ih->ihl << 2), |
8dff19a6 | 1387 | proto, csum_fold(ehsum)); |
1da177e4 LT |
1388 | |
1389 | csum = (csum & 0xffff) + (csum >> 16); /* Fold again */ | |
1390 | csum = (csum & 0xffff) + (csum >> 16); | |
1391 | ||
1392 | csoff = ETH_HLEN + (ih->ihl << 2); | |
1393 | if (proto == IPPROTO_UDP) { | |
1394 | csoff += offsetof(struct udphdr, check); | |
4bedb452 | 1395 | udp_hdr(skb)->check = csum; |
1da177e4 LT |
1396 | } |
1397 | if (proto == IPPROTO_TCP) { | |
1398 | csoff += offsetof(struct tcphdr, check); | |
aa8223c7 | 1399 | tcp_hdr(skb)->check = csum; |
1da177e4 LT |
1400 | } |
1401 | ||
1402 | w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT); | |
1403 | } | |
1da177e4 LT |
1404 | |
1405 | spin_lock_irq(&ip->ioc3_lock); | |
1406 | ||
c1b6a3d8 | 1407 | data = (unsigned long)skb->data; |
1da177e4 LT |
1408 | len = skb->len; |
1409 | ||
1410 | produce = ip->tx_pi; | |
1411 | desc = &ip->txr[produce]; | |
1412 | ||
1413 | if (len <= 104) { | |
1414 | /* Short packet, let's copy it directly into the ring. */ | |
d626f62b | 1415 | skb_copy_from_linear_data(skb, desc->data, skb->len); |
1da177e4 LT |
1416 | if (len < ETH_ZLEN) { |
1417 | /* Very short packet, pad with zeros at the end. */ | |
1418 | memset(desc->data + len, 0, ETH_ZLEN - len); | |
1419 | len = ETH_ZLEN; | |
1420 | } | |
1421 | desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0); | |
1422 | desc->bufcnt = cpu_to_be32(len); | |
1423 | } else if ((data ^ (data + len - 1)) & 0x4000) { | |
1424 | unsigned long b2 = (data | 0x3fffUL) + 1UL; | |
1425 | unsigned long s1 = b2 - data; | |
1426 | unsigned long s2 = data + len - b2; | |
ed870f6a | 1427 | dma_addr_t d1, d2; |
1da177e4 LT |
1428 | |
1429 | desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | | |
c1b6a3d8 | 1430 | ETXD_B1V | ETXD_B2V | w0); |
1da177e4 | 1431 | desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) | |
c1b6a3d8 | 1432 | (s2 << ETXD_B2CNT_SHIFT)); |
ed870f6a TB |
1433 | d1 = dma_map_single(ip->dma_dev, skb->data, s1, DMA_TO_DEVICE); |
1434 | if (dma_mapping_error(ip->dma_dev, d1)) | |
1435 | goto drop_packet; | |
1436 | d2 = dma_map_single(ip->dma_dev, (void *)b2, s1, DMA_TO_DEVICE); | |
1437 | if (dma_mapping_error(ip->dma_dev, d2)) { | |
1438 | dma_unmap_single(ip->dma_dev, d1, len, DMA_TO_DEVICE); | |
1439 | goto drop_packet; | |
1440 | } | |
1441 | desc->p1 = cpu_to_be64(ioc3_map(d1, PCI64_ATTR_PREF)); | |
1442 | desc->p2 = cpu_to_be64(ioc3_map(d2, PCI64_ATTR_PREF)); | |
1da177e4 | 1443 | } else { |
ed870f6a TB |
1444 | dma_addr_t d; |
1445 | ||
1da177e4 LT |
1446 | /* Normal sized packet that doesn't cross a page boundary. */ |
1447 | desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0); | |
1448 | desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT); | |
ed870f6a TB |
1449 | d = dma_map_single(ip->dma_dev, skb->data, len, DMA_TO_DEVICE); |
1450 | if (dma_mapping_error(ip->dma_dev, d)) | |
1451 | goto drop_packet; | |
1452 | desc->p1 = cpu_to_be64(ioc3_map(d, PCI64_ATTR_PREF)); | |
1da177e4 LT |
1453 | } |
1454 | ||
c1b6a3d8 | 1455 | mb(); /* make sure all descriptor changes are visible */ |
1da177e4 | 1456 | |
1da177e4 | 1457 | ip->tx_skbs[produce] = skb; /* Remember skb */ |
141a7dbb | 1458 | produce = (produce + 1) & TX_RING_MASK; |
1da177e4 | 1459 | ip->tx_pi = produce; |
cbe7d517 | 1460 | writel(produce << 7, &ip->regs->etpir); /* Fire ... */ |
1da177e4 LT |
1461 | |
1462 | ip->txqlen++; | |
1463 | ||
141a7dbb | 1464 | if (ip->txqlen >= (TX_RING_ENTRIES - 1)) |
1da177e4 LT |
1465 | netif_stop_queue(dev); |
1466 | ||
1467 | spin_unlock_irq(&ip->ioc3_lock); | |
1468 | ||
ed870f6a TB |
1469 | return NETDEV_TX_OK; |
1470 | ||
1471 | drop_packet: | |
1472 | dev_kfree_skb_any(skb); | |
1473 | dev->stats.tx_dropped++; | |
1474 | ||
1475 | spin_unlock_irq(&ip->ioc3_lock); | |
1476 | ||
6ed10654 | 1477 | return NETDEV_TX_OK; |
1da177e4 LT |
1478 | } |
1479 | ||
1480 | static void ioc3_timeout(struct net_device *dev) | |
1481 | { | |
1482 | struct ioc3_private *ip = netdev_priv(dev); | |
1483 | ||
c1b6a3d8 | 1484 | netdev_err(dev, "transmit timed out, resetting\n"); |
1da177e4 LT |
1485 | |
1486 | spin_lock_irq(&ip->ioc3_lock); | |
1487 | ||
1488 | ioc3_stop(ip); | |
19a957b6 TB |
1489 | ioc3_free_rx_bufs(ip); |
1490 | ioc3_clean_tx_ring(ip); | |
1491 | ||
1da177e4 | 1492 | ioc3_init(dev); |
850d2fed TB |
1493 | if (ioc3_alloc_rx_bufs(dev)) { |
1494 | netdev_err(dev, "%s: rx buffer allocation failed\n", __func__); | |
1495 | spin_unlock_irq(&ip->ioc3_lock); | |
1496 | return; | |
1497 | } | |
fcd0da5a | 1498 | ioc3_start(ip); |
1da177e4 | 1499 | ioc3_mii_init(ip); |
f0ba7358 | 1500 | ioc3_mii_start(ip); |
1da177e4 LT |
1501 | |
1502 | spin_unlock_irq(&ip->ioc3_lock); | |
1503 | ||
1504 | netif_wake_queue(dev); | |
1505 | } | |
1506 | ||
c1b6a3d8 | 1507 | /* Given a multicast ethernet address, this routine calculates the |
1da177e4 LT |
1508 | * address's bit index in the logical address filter mask |
1509 | */ | |
1da177e4 LT |
1510 | static inline unsigned int ioc3_hash(const unsigned char *addr) |
1511 | { | |
1512 | unsigned int temp = 0; | |
1da177e4 | 1513 | int bits; |
c1b6a3d8 | 1514 | u32 crc; |
1da177e4 LT |
1515 | |
1516 | crc = ether_crc_le(ETH_ALEN, addr); | |
1517 | ||
1518 | crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */ | |
1519 | for (bits = 6; --bits >= 0; ) { | |
1520 | temp <<= 1; | |
1521 | temp |= (crc & 0x1); | |
1522 | crc >>= 1; | |
1523 | } | |
1524 | ||
1525 | return temp; | |
1526 | } | |
1527 | ||
c1b6a3d8 TB |
1528 | static void ioc3_get_drvinfo(struct net_device *dev, |
1529 | struct ethtool_drvinfo *info) | |
1da177e4 LT |
1530 | { |
1531 | struct ioc3_private *ip = netdev_priv(dev); | |
852ea22a | 1532 | |
7826d43f JP |
1533 | strlcpy(info->driver, IOC3_NAME, sizeof(info->driver)); |
1534 | strlcpy(info->version, IOC3_VERSION, sizeof(info->version)); | |
1535 | strlcpy(info->bus_info, pci_name(ip->pdev), sizeof(info->bus_info)); | |
1da177e4 LT |
1536 | } |
1537 | ||
b61a26f8 PR |
1538 | static int ioc3_get_link_ksettings(struct net_device *dev, |
1539 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
1540 | { |
1541 | struct ioc3_private *ip = netdev_priv(dev); | |
1da177e4 LT |
1542 | |
1543 | spin_lock_irq(&ip->ioc3_lock); | |
82c01a84 | 1544 | mii_ethtool_get_link_ksettings(&ip->mii, cmd); |
1da177e4 LT |
1545 | spin_unlock_irq(&ip->ioc3_lock); |
1546 | ||
82c01a84 | 1547 | return 0; |
1da177e4 LT |
1548 | } |
1549 | ||
b61a26f8 PR |
1550 | static int ioc3_set_link_ksettings(struct net_device *dev, |
1551 | const struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
1552 | { |
1553 | struct ioc3_private *ip = netdev_priv(dev); | |
1554 | int rc; | |
1555 | ||
1556 | spin_lock_irq(&ip->ioc3_lock); | |
b61a26f8 | 1557 | rc = mii_ethtool_set_link_ksettings(&ip->mii, cmd); |
1da177e4 | 1558 | spin_unlock_irq(&ip->ioc3_lock); |
852ea22a | 1559 | |
1da177e4 LT |
1560 | return rc; |
1561 | } | |
1562 | ||
1563 | static int ioc3_nway_reset(struct net_device *dev) | |
1564 | { | |
1565 | struct ioc3_private *ip = netdev_priv(dev); | |
1566 | int rc; | |
1567 | ||
1568 | spin_lock_irq(&ip->ioc3_lock); | |
1569 | rc = mii_nway_restart(&ip->mii); | |
1570 | spin_unlock_irq(&ip->ioc3_lock); | |
1571 | ||
1572 | return rc; | |
1573 | } | |
1574 | ||
1575 | static u32 ioc3_get_link(struct net_device *dev) | |
1576 | { | |
1577 | struct ioc3_private *ip = netdev_priv(dev); | |
1578 | int rc; | |
1579 | ||
1580 | spin_lock_irq(&ip->ioc3_lock); | |
1581 | rc = mii_link_ok(&ip->mii); | |
1582 | spin_unlock_irq(&ip->ioc3_lock); | |
1583 | ||
1584 | return rc; | |
1585 | } | |
1586 | ||
7282d491 | 1587 | static const struct ethtool_ops ioc3_ethtool_ops = { |
1da177e4 | 1588 | .get_drvinfo = ioc3_get_drvinfo, |
1da177e4 LT |
1589 | .nway_reset = ioc3_nway_reset, |
1590 | .get_link = ioc3_get_link, | |
b61a26f8 PR |
1591 | .get_link_ksettings = ioc3_get_link_ksettings, |
1592 | .set_link_ksettings = ioc3_set_link_ksettings, | |
1da177e4 LT |
1593 | }; |
1594 | ||
1595 | static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1596 | { | |
1597 | struct ioc3_private *ip = netdev_priv(dev); | |
1598 | int rc; | |
1599 | ||
1600 | spin_lock_irq(&ip->ioc3_lock); | |
1601 | rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL); | |
1602 | spin_unlock_irq(&ip->ioc3_lock); | |
1603 | ||
1604 | return rc; | |
1605 | } | |
1606 | ||
1607 | static void ioc3_set_multicast_list(struct net_device *dev) | |
1608 | { | |
1da177e4 | 1609 | struct ioc3_private *ip = netdev_priv(dev); |
cbe7d517 TB |
1610 | struct ioc3_ethregs *regs = ip->regs; |
1611 | struct netdev_hw_addr *ha; | |
1da177e4 | 1612 | u64 ehar = 0; |
1da177e4 | 1613 | |
d1c94542 TB |
1614 | spin_lock_irq(&ip->ioc3_lock); |
1615 | ||
1da177e4 | 1616 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ |
1da177e4 | 1617 | ip->emcr |= EMCR_PROMISC; |
cbe7d517 TB |
1618 | writel(ip->emcr, ®s->emcr); |
1619 | readl(®s->emcr); | |
1da177e4 LT |
1620 | } else { |
1621 | ip->emcr &= ~EMCR_PROMISC; | |
cbe7d517 TB |
1622 | writel(ip->emcr, ®s->emcr); /* Clear promiscuous. */ |
1623 | readl(®s->emcr); | |
1da177e4 | 1624 | |
4cd24eaf JP |
1625 | if ((dev->flags & IFF_ALLMULTI) || |
1626 | (netdev_mc_count(dev) > 64)) { | |
1da177e4 | 1627 | /* Too many for hashing to make sense or we want all |
c1b6a3d8 TB |
1628 | * multicast packets anyway, so skip computing all the |
1629 | * hashes and just accept all packets. | |
1630 | */ | |
1da177e4 LT |
1631 | ip->ehar_h = 0xffffffff; |
1632 | ip->ehar_l = 0xffffffff; | |
1633 | } else { | |
22bedad3 | 1634 | netdev_for_each_mc_addr(ha, dev) { |
498d8e23 | 1635 | ehar |= (1UL << ioc3_hash(ha->addr)); |
1da177e4 LT |
1636 | } |
1637 | ip->ehar_h = ehar >> 32; | |
1638 | ip->ehar_l = ehar & 0xffffffff; | |
1639 | } | |
cbe7d517 TB |
1640 | writel(ip->ehar_h, ®s->ehar_h); |
1641 | writel(ip->ehar_l, ®s->ehar_l); | |
1da177e4 LT |
1642 | } |
1643 | ||
d1c94542 | 1644 | spin_unlock_irq(&ip->ioc3_lock); |
1da177e4 LT |
1645 | } |
1646 | ||
e0fc4441 | 1647 | module_pci_driver(ioc3_driver); |
1da177e4 LT |
1648 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); |
1649 | MODULE_DESCRIPTION("SGI IOC3 Ethernet driver"); | |
1650 | MODULE_LICENSE("GPL"); |