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qlcnic: 83xx data path routines
[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_init.c
CommitLineData
af19b491 1/*
40839129
SV		 2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
af19b491 4 *
40839129 5 * See LICENSE.qlcnic for copyright and licensing details.
af19b491
AKS		 6 */
7
af19b491 8#include "qlcnic.h"
a15ebd37 9#include "qlcnic_hw.h"
af19b491
AKS		 10
11struct crb_addr_pair {
12 u32 addr;
13 u32 data;
14};
15
16#define QLCNIC_MAX_CRB_XFORM 60
17static unsigned int crb_addr_xform[QLCNIC_MAX_CRB_XFORM];
18
19#define crb_addr_transform(name) \
20 (crb_addr_xform[QLCNIC_HW_PX_MAP_CRB_##name] = \
21 QLCNIC_HW_CRB_HUB_AGT_ADR_##name << 20)
22
23#define QLCNIC_ADDR_ERROR (0xffffffff)
24
4e70812b
SC		 25static int
26qlcnic_check_fw_hearbeat(struct qlcnic_adapter *adapter);
27
af19b491
AKS		 28static void crb_addr_transform_setup(void)
29{
30 crb_addr_transform(XDMA);
31 crb_addr_transform(TIMR);
32 crb_addr_transform(SRE);
33 crb_addr_transform(SQN3);
34 crb_addr_transform(SQN2);
35 crb_addr_transform(SQN1);
36 crb_addr_transform(SQN0);
37 crb_addr_transform(SQS3);
38 crb_addr_transform(SQS2);
39 crb_addr_transform(SQS1);
40 crb_addr_transform(SQS0);
41 crb_addr_transform(RPMX7);
42 crb_addr_transform(RPMX6);
43 crb_addr_transform(RPMX5);
44 crb_addr_transform(RPMX4);
45 crb_addr_transform(RPMX3);
46 crb_addr_transform(RPMX2);
47 crb_addr_transform(RPMX1);
48 crb_addr_transform(RPMX0);
49 crb_addr_transform(ROMUSB);
50 crb_addr_transform(SN);
51 crb_addr_transform(QMN);
52 crb_addr_transform(QMS);
53 crb_addr_transform(PGNI);
54 crb_addr_transform(PGND);
55 crb_addr_transform(PGN3);
56 crb_addr_transform(PGN2);
57 crb_addr_transform(PGN1);
58 crb_addr_transform(PGN0);
59 crb_addr_transform(PGSI);
60 crb_addr_transform(PGSD);
61 crb_addr_transform(PGS3);
62 crb_addr_transform(PGS2);
63 crb_addr_transform(PGS1);
64 crb_addr_transform(PGS0);
65 crb_addr_transform(PS);
66 crb_addr_transform(PH);
67 crb_addr_transform(NIU);
68 crb_addr_transform(I2Q);
69 crb_addr_transform(EG);
70 crb_addr_transform(MN);
71 crb_addr_transform(MS);
72 crb_addr_transform(CAS2);
73 crb_addr_transform(CAS1);
74 crb_addr_transform(CAS0);
75 crb_addr_transform(CAM);
76 crb_addr_transform(C2C1);
77 crb_addr_transform(C2C0);
78 crb_addr_transform(SMB);
79 crb_addr_transform(OCM0);
80 crb_addr_transform(I2C0);
81}
82
83void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter)
84{
85 struct qlcnic_recv_context *recv_ctx;
86 struct qlcnic_host_rds_ring *rds_ring;
87 struct qlcnic_rx_buffer *rx_buf;
88 int i, ring;
89
b1fc6d3c 90 recv_ctx = adapter->recv_ctx;
af19b491
AKS		 91 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
92 rds_ring = &recv_ctx->rds_rings[ring];
93 for (i = 0; i < rds_ring->num_desc; ++i) {
94 rx_buf = &(rds_ring->rx_buf_arr[i]);
96659828 95 if (rx_buf->skb == NULL)
af19b491 96 continue;
96659828 97
af19b491
AKS		 98 pci_unmap_single(adapter->pdev,
99 rx_buf->dma,
100 rds_ring->dma_size,
101 PCI_DMA_FROMDEVICE);
96659828
AKS		 102
103 dev_kfree_skb_any(rx_buf->skb);
af19b491
AKS		 104 }
105 }
106}
107
8a15ad1f
AKS		 108void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter)
109{
110 struct qlcnic_recv_context *recv_ctx;
111 struct qlcnic_host_rds_ring *rds_ring;
112 struct qlcnic_rx_buffer *rx_buf;
113 int i, ring;
114
b1fc6d3c 115 recv_ctx = adapter->recv_ctx;
8a15ad1f
AKS		 116 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
117 rds_ring = &recv_ctx->rds_rings[ring];
118
8a15ad1f
AKS		 119 INIT_LIST_HEAD(&rds_ring->free_list);
120
121 rx_buf = rds_ring->rx_buf_arr;
122 for (i = 0; i < rds_ring->num_desc; i++) {
123 list_add_tail(&rx_buf->list,
124 &rds_ring->free_list);
125 rx_buf++;
126 }
8a15ad1f
AKS		 127 }
128}
129
af19b491
AKS		 130void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter)
131{
132 struct qlcnic_cmd_buffer *cmd_buf;
133 struct qlcnic_skb_frag *buffrag;
134 int i, j;
135 struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
136
137 cmd_buf = tx_ring->cmd_buf_arr;
138 for (i = 0; i < tx_ring->num_desc; i++) {
139 buffrag = cmd_buf->frag_array;
140 if (buffrag->dma) {
141 pci_unmap_single(adapter->pdev, buffrag->dma,
142 buffrag->length, PCI_DMA_TODEVICE);
143 buffrag->dma = 0ULL;
144 }
145 for (j = 0; j < cmd_buf->frag_count; j++) {
146 buffrag++;
147 if (buffrag->dma) {
148 pci_unmap_page(adapter->pdev, buffrag->dma,
149 buffrag->length,
150 PCI_DMA_TODEVICE);
151 buffrag->dma = 0ULL;
152 }
153 }
154 if (cmd_buf->skb) {
155 dev_kfree_skb_any(cmd_buf->skb);
156 cmd_buf->skb = NULL;
157 }
158 cmd_buf++;
159 }
160}
161
162void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter)
163{
164 struct qlcnic_recv_context *recv_ctx;
165 struct qlcnic_host_rds_ring *rds_ring;
af19b491
AKS		 166 int ring;
167
b1fc6d3c 168 recv_ctx = adapter->recv_ctx;
af19b491
AKS		 169
170 if (recv_ctx->rds_rings == NULL)
4be41e92 171 return;
af19b491
AKS		 172
173 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
174 rds_ring = &recv_ctx->rds_rings[ring];
175 vfree(rds_ring->rx_buf_arr);
176 rds_ring->rx_buf_arr = NULL;
177 }
178 kfree(recv_ctx->rds_rings);
af19b491
AKS		 179}
180
181int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter)
182{
183 struct qlcnic_recv_context *recv_ctx;
184 struct qlcnic_host_rds_ring *rds_ring;
185 struct qlcnic_host_sds_ring *sds_ring;
af19b491
AKS		 186 struct qlcnic_rx_buffer *rx_buf;
187 int ring, i, size;
188
af19b491
AKS		 189 struct net_device *netdev = adapter->netdev;
190
b1fc6d3c 191 recv_ctx = adapter->recv_ctx;
af19b491
AKS		 192
193 size = adapter->max_rds_rings * sizeof(struct qlcnic_host_rds_ring);
194 rds_ring = kzalloc(size, GFP_KERNEL);
195 if (rds_ring == NULL) {
196 dev_err(&netdev->dev, "failed to allocate rds ring struct\n");
aadd8184 197 goto err_out;
af19b491
AKS		 198 }
199 recv_ctx->rds_rings = rds_ring;
200
201 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
202 rds_ring = &recv_ctx->rds_rings[ring];
203 switch (ring) {
204 case RCV_RING_NORMAL:
205 rds_ring->num_desc = adapter->num_rxd;
ff1b1bf8 206 rds_ring->dma_size = QLCNIC_P3P_RX_BUF_MAX_LEN;
251a84c9 207 rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
af19b491
AKS		 208 break;
209
210 case RCV_RING_JUMBO:
211 rds_ring->num_desc = adapter->num_jumbo_rxd;
212 rds_ring->dma_size =
ff1b1bf8 213 QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN;
af19b491 214
79788450
SC		 215 if (adapter->ahw->capabilities &
216 QLCNIC_FW_CAPABILITY_HW_LRO)
af19b491
AKS		 217 rds_ring->dma_size += QLCNIC_LRO_BUFFER_EXTRA;
218
219 rds_ring->skb_size =
220 rds_ring->dma_size + NET_IP_ALIGN;
221 break;
af19b491 222 }
f3167460 223 rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
af19b491 224 if (rds_ring->rx_buf_arr == NULL) {
4be41e92
SC		 225 dev_err(&netdev->dev,
226 "Failed to allocate rx buffer ring %d\n", ring);
af19b491
AKS		 227 goto err_out;
228 }
4be41e92 229
af19b491
AKS		 230 INIT_LIST_HEAD(&rds_ring->free_list);
231 /*
232 * Now go through all of them, set reference handles
233 * and put them in the queues.
234 */
235 rx_buf = rds_ring->rx_buf_arr;
236 for (i = 0; i < rds_ring->num_desc; i++) {
237 list_add_tail(&rx_buf->list,
238 &rds_ring->free_list);
239 rx_buf->ref_handle = i;
af19b491
AKS		 240 rx_buf++;
241 }
242 spin_lock_init(&rds_ring->lock);
243 }
244
245 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
246 sds_ring = &recv_ctx->sds_rings[ring];
247 sds_ring->irq = adapter->msix_entries[ring].vector;
248 sds_ring->adapter = adapter;
249 sds_ring->num_desc = adapter->num_rxd;
250
251 for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
252 INIT_LIST_HEAD(&sds_ring->free_list[i]);
253 }
254
255 return 0;
256
257err_out:
258 qlcnic_free_sw_resources(adapter);
259 return -ENOMEM;
260}
261
262/*
263 * Utility to translate from internal Phantom CRB address
264 * to external PCI CRB address.
265 */
266static u32 qlcnic_decode_crb_addr(u32 addr)
267{
268 int i;
269 u32 base_addr, offset, pci_base;
270
271 crb_addr_transform_setup();
272
273 pci_base = QLCNIC_ADDR_ERROR;
274 base_addr = addr & 0xfff00000;
275 offset = addr & 0x000fffff;
276
277 for (i = 0; i < QLCNIC_MAX_CRB_XFORM; i++) {
278 if (crb_addr_xform[i] == base_addr) {
279 pci_base = i << 20;
280 break;
281 }
282 }
283 if (pci_base == QLCNIC_ADDR_ERROR)
284 return pci_base;
285 else
286 return pci_base + offset;
287}
288
289#define QLCNIC_MAX_ROM_WAIT_USEC 100
290
291static int qlcnic_wait_rom_done(struct qlcnic_adapter *adapter)
292{
293 long timeout = 0;
294 long done = 0;
295
296 cond_resched();
af19b491
AKS		 297 while (done == 0) {
298 done = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_STATUS);
299 done &= 2;
300 if (++timeout >= QLCNIC_MAX_ROM_WAIT_USEC) {
301 dev_err(&adapter->pdev->dev,
302 "Timeout reached waiting for rom done");
303 return -EIO;
304 }
305 udelay(1);
306 }
307 return 0;
308}
309
310static int do_rom_fast_read(struct qlcnic_adapter *adapter,
18f2f616 311 u32 addr, u32 *valp)
af19b491
AKS		 312{
313 QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ADDRESS, addr);
314 QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
315 QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 3);
316 QLCWR32(adapter, QLCNIC_ROMUSB_ROM_INSTR_OPCODE, 0xb);
317 if (qlcnic_wait_rom_done(adapter)) {
318 dev_err(&adapter->pdev->dev, "Error waiting for rom done\n");
319 return -EIO;
320 }
321 /* reset abyte_cnt and dummy_byte_cnt */
322 QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 0);
323 udelay(10);
324 QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
325
326 *valp = QLCRD32(adapter, QLCNIC_ROMUSB_ROM_RDATA);
327 return 0;
328}
329
330static int do_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
331 u8 *bytes, size_t size)
332{
333 int addridx;
334 int ret = 0;
335
336 for (addridx = addr; addridx < (addr + size); addridx += 4) {
337 int v;
338 ret = do_rom_fast_read(adapter, addridx, &v);
339 if (ret != 0)
340 break;
341 *(__le32 *)bytes = cpu_to_le32(v);
342 bytes += 4;
343 }
344
345 return ret;
346}
347
348int
349qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
350 u8 *bytes, size_t size)
351{
352 int ret;
353
354 ret = qlcnic_rom_lock(adapter);
355 if (ret < 0)
356 return ret;
357
358 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
359
360 qlcnic_rom_unlock(adapter);
361 return ret;
362}
363
18f2f616 364int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp)
af19b491
AKS		 365{
366 int ret;
367
368 if (qlcnic_rom_lock(adapter) != 0)
369 return -EIO;
370
371 ret = do_rom_fast_read(adapter, addr, valp);
372 qlcnic_rom_unlock(adapter);
373 return ret;
374}
375
376int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter)
377{
378 int addr, val;
379 int i, n, init_delay;
380 struct crb_addr_pair *buf;
381 unsigned offset;
382 u32 off;
383 struct pci_dev *pdev = adapter->pdev;
384
a15ebd37
HM		 385 QLC_SHARED_REG_WR32(adapter, QLCNIC_CMDPEG_STATE, 0);
386 QLC_SHARED_REG_WR32(adapter, QLCNIC_RCVPEG_STATE, 0);
d4066833 387
68233c58
SC		 388 /* Halt all the indiviual PEGs and other blocks */
389 /* disable all I2Q */
390 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x10, 0x0);
391 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x14, 0x0);
392 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x18, 0x0);
393 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x1c, 0x0);
394 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x20, 0x0);
395 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x24, 0x0);
396
397 /* disable all niu interrupts */
398 QLCWR32(adapter, QLCNIC_CRB_NIU + 0x40, 0xff);
399 /* disable xge rx/tx */
400 QLCWR32(adapter, QLCNIC_CRB_NIU + 0x70000, 0x00);
401 /* disable xg1 rx/tx */
402 QLCWR32(adapter, QLCNIC_CRB_NIU + 0x80000, 0x00);
403 /* disable sideband mac */
404 QLCWR32(adapter, QLCNIC_CRB_NIU + 0x90000, 0x00);
405 /* disable ap0 mac */
406 QLCWR32(adapter, QLCNIC_CRB_NIU + 0xa0000, 0x00);
407 /* disable ap1 mac */
408 QLCWR32(adapter, QLCNIC_CRB_NIU + 0xb0000, 0x00);
409
410 /* halt sre */
411 val = QLCRD32(adapter, QLCNIC_CRB_SRE + 0x1000);
412 QLCWR32(adapter, QLCNIC_CRB_SRE + 0x1000, val & (~(0x1)));
413
414 /* halt epg */
415 QLCWR32(adapter, QLCNIC_CRB_EPG + 0x1300, 0x1);
416
417 /* halt timers */
418 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x0, 0x0);
419 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x8, 0x0);
420 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x10, 0x0);
421 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x18, 0x0);
422 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x100, 0x0);
423 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x200, 0x0);
424 /* halt pegs */
425 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x3c, 1);
426 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x3c, 1);
427 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x3c, 1);
428 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x3c, 1);
429 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x3c, 1);
430 msleep(20);
431
af19b491 432 qlcnic_rom_unlock(adapter);
68233c58
SC		 433 /* big hammer don't reset CAM block on reset */
434 QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0xfeffffff);
af19b491 435
d4066833 436 /* Init HW CRB block */
af19b491
AKS		 437 if (qlcnic_rom_fast_read(adapter, 0, &n) != 0 || (n != 0xcafecafe) ||
438 qlcnic_rom_fast_read(adapter, 4, &n) != 0) {
439 dev_err(&pdev->dev, "ERROR Reading crb_init area: val:%x\n", n);
440 return -EIO;
441 }
442 offset = n & 0xffffU;
443 n = (n >> 16) & 0xffffU;
444
445 if (n >= 1024) {
446 dev_err(&pdev->dev, "QLOGIC card flash not initialized.\n");
447 return -EIO;
448 }
449
450 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
451 if (buf == NULL) {
452 dev_err(&pdev->dev, "Unable to calloc memory for rom read.\n");
453 return -ENOMEM;
454 }
455
456 for (i = 0; i < n; i++) {
457 if (qlcnic_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
458 qlcnic_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
459 kfree(buf);
460 return -EIO;
461 }
462
463 buf[i].addr = addr;
464 buf[i].data = val;
465 }
466
467 for (i = 0; i < n; i++) {
468
469 off = qlcnic_decode_crb_addr(buf[i].addr);
470 if (off == QLCNIC_ADDR_ERROR) {
471 dev_err(&pdev->dev, "CRB init value out of range %x\n",
472 buf[i].addr);
473 continue;
474 }
475 off += QLCNIC_PCI_CRBSPACE;
476
477 if (off & 1)
478 continue;
479
480 /* skipping cold reboot MAGIC */
481 if (off == QLCNIC_CAM_RAM(0x1fc))
482 continue;
483 if (off == (QLCNIC_CRB_I2C0 + 0x1c))
484 continue;
485 if (off == (ROMUSB_GLB + 0xbc)) /* do not reset PCI */
486 continue;
487 if (off == (ROMUSB_GLB + 0xa8))
488 continue;
489 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
490 continue;
491 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
492 continue;
493 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
494 continue;
495 if ((off & 0x0ff00000) == QLCNIC_CRB_DDR_NET)
496 continue;
497 /* skip the function enable register */
498 if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION))
499 continue;
500 if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION2))
501 continue;
502 if ((off & 0x0ff00000) == QLCNIC_CRB_SMB)
503 continue;
504
505 init_delay = 1;
506 /* After writing this register, HW needs time for CRB */
507 /* to quiet down (else crb_window returns 0xffffffff) */
508 if (off == QLCNIC_ROMUSB_GLB_SW_RESET)
509 init_delay = 1000;
510
511 QLCWR32(adapter, off, buf[i].data);
512
513 msleep(init_delay);
514 }
515 kfree(buf);
516
d4066833 517 /* Initialize protocol process engine */
af19b491 518 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0xec, 0x1e);
af19b491
AKS		 519 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0x4c, 8);
520 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_I + 0x4c, 8);
af19b491
AKS		 521 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x8, 0);
522 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0xc, 0);
523 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x8, 0);
524 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0xc, 0);
525 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x8, 0);
526 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0xc, 0);
527 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x8, 0);
528 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0xc, 0);
d4066833
SC		 529 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x8, 0);
530 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0xc, 0);
531 msleep(1);
68233c58 532
a15ebd37
HM		 533 QLC_SHARED_REG_WR32(adapter, QLCNIC_PEG_HALT_STATUS1, 0);
534 QLC_SHARED_REG_WR32(adapter, QLCNIC_PEG_HALT_STATUS2, 0);
68233c58 535
af19b491
AKS		 536 return 0;
537}
538
4e70812b 539static int qlcnic_cmd_peg_ready(struct qlcnic_adapter *adapter)
d4066833 540{
4e70812b
SC		 541 u32 val;
542 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
d4066833 543
d4066833 544 do {
a15ebd37 545 val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CMDPEG_STATE);
4e70812b
SC		 546
547 switch (val) {
548 case PHAN_INITIALIZE_COMPLETE:
549 case PHAN_INITIALIZE_ACK:
550 return 0;
551 case PHAN_INITIALIZE_FAILED:
552 goto out_err;
553 default:
554 break;
d4066833 555 }
4e70812b
SC		 556
557 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
558
d4066833
SC		 559 } while (--retries);
560
a15ebd37
HM		 561 QLC_SHARED_REG_WR32(adapter, QLCNIC_CMDPEG_STATE,
562 PHAN_INITIALIZE_FAILED);
4e70812b
SC		 563
564out_err:
565 dev_err(&adapter->pdev->dev, "Command Peg initialization not "
566 "complete, state: 0x%x.\n", val);
567 return -EIO;
568}
569
570static int
571qlcnic_receive_peg_ready(struct qlcnic_adapter *adapter)
572{
573 u32 val;
574 int retries = QLCNIC_RCVPEG_CHECK_RETRY_COUNT;
575
576 do {
a15ebd37 577 val = QLC_SHARED_REG_RD32(adapter, QLCNIC_RCVPEG_STATE);
4e70812b
SC		 578
579 if (val == PHAN_PEG_RCV_INITIALIZED)
580 return 0;
581
582 msleep(QLCNIC_RCVPEG_CHECK_DELAY);
583
584 } while (--retries);
585
586 if (!retries) {
587 dev_err(&adapter->pdev->dev, "Receive Peg initialization not "
588 "complete, state: 0x%x.\n", val);
589 return -EIO;
590 }
591
592 return 0;
593}
594
595int
596qlcnic_check_fw_status(struct qlcnic_adapter *adapter)
597{
598 int err;
599
600 err = qlcnic_cmd_peg_ready(adapter);
601 if (err)
602 return err;
603
604 err = qlcnic_receive_peg_ready(adapter);
605 if (err)
606 return err;
607
a15ebd37 608 QLC_SHARED_REG_WR32(adapter, QLCNIC_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
4e70812b
SC		 609
610 return err;
d4066833
SC		 611}
612
b3a24649 613int
aa5e18c0
SC		 614qlcnic_setup_idc_param(struct qlcnic_adapter *adapter) {
615
616 int timeo;
b3a24649
SC		 617 u32 val;
618
a15ebd37 619 val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DEV_PARTITION_INFO);
45918e2f
AC		 620 val = QLC_DEV_GET_DRV(val, adapter->portnum);
621 if ((val & 0x3) != QLCNIC_TYPE_NIC) {
622 dev_err(&adapter->pdev->dev,
623 "Not an Ethernet NIC func=%u\n", val);
624 return -EIO;
b3a24649 625 }
79788450 626 adapter->ahw->physical_port = (val >> 2);
aa5e18c0 627 if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DEV_INIT_TIMEOUT, &timeo))
251b036a 628 timeo = QLCNIC_INIT_TIMEOUT_SECS;
aa5e18c0
SC		 629
630 adapter->dev_init_timeo = timeo;
631
632 if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DRV_RESET_TIMEOUT, &timeo))
251b036a 633 timeo = QLCNIC_RESET_TIMEOUT_SECS;
aa5e18c0
SC		 634
635 adapter->reset_ack_timeo = timeo;
b3a24649
SC		 636
637 return 0;
aa5e18c0
SC		 638}
639
0e5f20b6 640static int qlcnic_get_flt_entry(struct qlcnic_adapter *adapter, u8 region,
641 struct qlcnic_flt_entry *region_entry)
642{
643 struct qlcnic_flt_header flt_hdr;
644 struct qlcnic_flt_entry *flt_entry;
645 int i = 0, ret;
646 u32 entry_size;
647
648 memset(region_entry, 0, sizeof(struct qlcnic_flt_entry));
649 ret = qlcnic_rom_fast_read_words(adapter, QLCNIC_FLT_LOCATION,
650 (u8 *)&flt_hdr,
651 sizeof(struct qlcnic_flt_header));
652 if (ret) {
653 dev_warn(&adapter->pdev->dev,
654 "error reading flash layout header\n");
655 return -EIO;
656 }
657
658 entry_size = flt_hdr.len - sizeof(struct qlcnic_flt_header);
a15ebd37 659 flt_entry = vzalloc(entry_size);
0e5f20b6 660 if (flt_entry == NULL) {
661 dev_warn(&adapter->pdev->dev, "error allocating memory\n");
662 return -EIO;
663 }
664
665 ret = qlcnic_rom_fast_read_words(adapter, QLCNIC_FLT_LOCATION +
666 sizeof(struct qlcnic_flt_header),
667 (u8 *)flt_entry, entry_size);
668 if (ret) {
669 dev_warn(&adapter->pdev->dev,
670 "error reading flash layout entries\n");
671 goto err_out;
672 }
673
674 while (i < (entry_size/sizeof(struct qlcnic_flt_entry))) {
675 if (flt_entry[i].region == region)
676 break;
677 i++;
678 }
679 if (i >= (entry_size/sizeof(struct qlcnic_flt_entry))) {
680 dev_warn(&adapter->pdev->dev,
681 "region=%x not found in %d regions\n", region, i);
682 ret = -EIO;
683 goto err_out;
684 }
685 memcpy(region_entry, &flt_entry[i], sizeof(struct qlcnic_flt_entry));
686
687err_out:
688 vfree(flt_entry);
689 return ret;
690}
691
8f891387 692int
693qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter)
694{
0e5f20b6 695 struct qlcnic_flt_entry fw_entry;
8f891387 696 u32 ver = -1, min_ver;
0e5f20b6 697 int ret;
8f891387 698
a2050c7e
SV		 699 if (adapter->ahw->revision_id == QLCNIC_P3P_C0)
700 ret = qlcnic_get_flt_entry(adapter, QLCNIC_C0_FW_IMAGE_REGION,
701 &fw_entry);
702 else
703 ret = qlcnic_get_flt_entry(adapter, QLCNIC_B0_FW_IMAGE_REGION,
704 &fw_entry);
705
0e5f20b6 706 if (!ret)
707 /* 0-4:-signature, 4-8:-fw version */
708 qlcnic_rom_fast_read(adapter, fw_entry.start_addr + 4,
709 (int *)&ver);
710 else
711 qlcnic_rom_fast_read(adapter, QLCNIC_FW_VERSION_OFFSET,
712 (int *)&ver);
8f891387 713
714 ver = QLCNIC_DECODE_VERSION(ver);
715 min_ver = QLCNIC_MIN_FW_VERSION;
716
717 if (ver < min_ver) {
718 dev_err(&adapter->pdev->dev,
719 "firmware version %d.%d.%d unsupported."
720 "Min supported version %d.%d.%d\n",
721 _major(ver), _minor(ver), _build(ver),
722 _major(min_ver), _minor(min_ver), _build(min_ver));
723 return -EINVAL;
724 }
725
726 return 0;
727}
728
af19b491
AKS		 729static int
730qlcnic_has_mn(struct qlcnic_adapter *adapter)
731{
8f891387 732 u32 capability;
af19b491
AKS		 733 capability = 0;
734
251a84c9
AKS		 735 capability = QLCRD32(adapter, QLCNIC_PEG_TUNE_CAPABILITY);
736 if (capability & QLCNIC_PEG_TUNE_MN_PRESENT)
737 return 1;
af19b491 738
af19b491
AKS		 739 return 0;
740}
741
742static
743struct uni_table_desc *qlcnic_get_table_desc(const u8 *unirom, int section)
744{
63507592 745 u32 i, entries;
af19b491 746 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
63507592 747 entries = le32_to_cpu(directory->num_entries);
af19b491
AKS		 748
749 for (i = 0; i < entries; i++) {
750
63507592
SS		 751 u32 offs = le32_to_cpu(directory->findex) +
752 i * le32_to_cpu(directory->entry_size);
753 u32 tab_type = le32_to_cpu(*((__le32 *)&unirom[offs] + 8));
af19b491
AKS		 754
755 if (tab_type == section)
756 return (struct uni_table_desc *) &unirom[offs];
757 }
758
759 return NULL;
760}
761
b7eff100
SC		 762#define FILEHEADER_SIZE (14 * 4)
763
af19b491 764static int
b7eff100 765qlcnic_validate_header(struct qlcnic_adapter *adapter)
af19b491 766{
af19b491 767 const u8 *unirom = adapter->fw->data;
b7eff100 768 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
63507592
SS		 769 u32 entries, entry_size, tab_size, fw_file_size;
770
771 fw_file_size = adapter->fw->size;
b7eff100
SC		 772
773 if (fw_file_size < FILEHEADER_SIZE)
774 return -EINVAL;
775
63507592
SS		 776 entries = le32_to_cpu(directory->num_entries);
777 entry_size = le32_to_cpu(directory->entry_size);
778 tab_size = le32_to_cpu(directory->findex) + (entries * entry_size);
b7eff100
SC		 779
780 if (fw_file_size < tab_size)
781 return -EINVAL;
782
783 return 0;
784}
785
786static int
787qlcnic_validate_bootld(struct qlcnic_adapter *adapter)
788{
789 struct uni_table_desc *tab_desc;
790 struct uni_data_desc *descr;
63507592 791 u32 offs, tab_size, data_size, idx;
b7eff100 792 const u8 *unirom = adapter->fw->data;
63507592 793 __le32 temp;
b7eff100 794
63507592
SS		 795 temp = *((__le32 *)&unirom[adapter->file_prd_off] +
796 QLCNIC_UNI_BOOTLD_IDX_OFF);
797 idx = le32_to_cpu(temp);
b7eff100
SC		 798 tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_BOOTLD);
799
800 if (!tab_desc)
801 return -EINVAL;
802
63507592
SS		 803 tab_size = le32_to_cpu(tab_desc->findex) +
804 le32_to_cpu(tab_desc->entry_size) * (idx + 1);
b7eff100
SC		 805
806 if (adapter->fw->size < tab_size)
807 return -EINVAL;
808
63507592
SS		 809 offs = le32_to_cpu(tab_desc->findex) +
810 le32_to_cpu(tab_desc->entry_size) * idx;
b7eff100
SC		 811 descr = (struct uni_data_desc *)&unirom[offs];
812
63507592 813 data_size = le32_to_cpu(descr->findex) + le32_to_cpu(descr->size);
b7eff100
SC		 814
815 if (adapter->fw->size < data_size)
816 return -EINVAL;
817
818 return 0;
819}
820
821static int
822qlcnic_validate_fw(struct qlcnic_adapter *adapter)
823{
824 struct uni_table_desc *tab_desc;
825 struct uni_data_desc *descr;
826 const u8 *unirom = adapter->fw->data;
63507592
SS		 827 u32 offs, tab_size, data_size, idx;
828 __le32 temp;
b7eff100 829
63507592
SS		 830 temp = *((__le32 *)&unirom[adapter->file_prd_off] +
831 QLCNIC_UNI_FIRMWARE_IDX_OFF);
832 idx = le32_to_cpu(temp);
b7eff100
SC		 833 tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_FW);
834
835 if (!tab_desc)
836 return -EINVAL;
837
63507592
SS		 838 tab_size = le32_to_cpu(tab_desc->findex) +
839 le32_to_cpu(tab_desc->entry_size) * (idx + 1);
b7eff100
SC		 840
841 if (adapter->fw->size < tab_size)
842 return -EINVAL;
843
63507592
SS		 844 offs = le32_to_cpu(tab_desc->findex) +
845 le32_to_cpu(tab_desc->entry_size) * idx;
b7eff100 846 descr = (struct uni_data_desc *)&unirom[offs];
63507592 847 data_size = le32_to_cpu(descr->findex) + le32_to_cpu(descr->size);
b7eff100
SC		 848
849 if (adapter->fw->size < data_size)
850 return -EINVAL;
851
852 return 0;
853}
854
855static int
856qlcnic_validate_product_offs(struct qlcnic_adapter *adapter)
857{
858 struct uni_table_desc *ptab_descr;
859 const u8 *unirom = adapter->fw->data;
af19b491 860 int mn_present = qlcnic_has_mn(adapter);
63507592
SS		 861 u32 entries, entry_size, tab_size, i;
862 __le32 temp;
af19b491
AKS		 863
864 ptab_descr = qlcnic_get_table_desc(unirom,
865 QLCNIC_UNI_DIR_SECT_PRODUCT_TBL);
b7eff100
SC		 866 if (!ptab_descr)
867 return -EINVAL;
af19b491 868
63507592
SS		 869 entries = le32_to_cpu(ptab_descr->num_entries);
870 entry_size = le32_to_cpu(ptab_descr->entry_size);
871 tab_size = le32_to_cpu(ptab_descr->findex) + (entries * entry_size);
b7eff100
SC		 872
873 if (adapter->fw->size < tab_size)
874 return -EINVAL;
875
af19b491
AKS		 876nomn:
877 for (i = 0; i < entries; i++) {
878
63507592 879 u32 flags, file_chiprev, offs;
b1fc6d3c 880 u8 chiprev = adapter->ahw->revision_id;
af19b491
AKS		 881 u32 flagbit;
882
63507592
SS		 883 offs = le32_to_cpu(ptab_descr->findex) +
884 i * le32_to_cpu(ptab_descr->entry_size);
885 temp = *((__le32 *)&unirom[offs] + QLCNIC_UNI_FLAGS_OFF);
886 flags = le32_to_cpu(temp);
887 temp = *((__le32 *)&unirom[offs] + QLCNIC_UNI_CHIP_REV_OFF);
888 file_chiprev = le32_to_cpu(temp);
af19b491
AKS		 889
890 flagbit = mn_present ? 1 : 2;
891
892 if ((chiprev == file_chiprev) &&
893 ((1ULL << flagbit) & flags)) {
894 adapter->file_prd_off = offs;
895 return 0;
896 }
897 }
898 if (mn_present) {
899 mn_present = 0;
900 goto nomn;
901 }
b7eff100
SC		 902 return -EINVAL;
903}
904
905static int
906qlcnic_validate_unified_romimage(struct qlcnic_adapter *adapter)
907{
908 if (qlcnic_validate_header(adapter)) {
909 dev_err(&adapter->pdev->dev,
910 "unified image: header validation failed\n");
911 return -EINVAL;
912 }
913
914 if (qlcnic_validate_product_offs(adapter)) {
915 dev_err(&adapter->pdev->dev,
916 "unified image: product validation failed\n");
917 return -EINVAL;
918 }
919
920 if (qlcnic_validate_bootld(adapter)) {
921 dev_err(&adapter->pdev->dev,
922 "unified image: bootld validation failed\n");
923 return -EINVAL;
924 }
925
926 if (qlcnic_validate_fw(adapter)) {
927 dev_err(&adapter->pdev->dev,
928 "unified image: firmware validation failed\n");
929 return -EINVAL;
930 }
931
932 return 0;
af19b491
AKS		 933}
934
935static
936struct uni_data_desc *qlcnic_get_data_desc(struct qlcnic_adapter *adapter,
937 u32 section, u32 idx_offset)
938{
939 const u8 *unirom = adapter->fw->data;
af19b491 940 struct uni_table_desc *tab_desc;
63507592
SS		 941 u32 offs, idx;
942 __le32 temp;
943
944 temp = *((__le32 *)&unirom[adapter->file_prd_off] + idx_offset);
945 idx = le32_to_cpu(temp);
af19b491
AKS		 946
947 tab_desc = qlcnic_get_table_desc(unirom, section);
948
949 if (tab_desc == NULL)
950 return NULL;
951
63507592
SS		 952 offs = le32_to_cpu(tab_desc->findex) +
953 le32_to_cpu(tab_desc->entry_size) * idx;
af19b491
AKS		 954
955 return (struct uni_data_desc *)&unirom[offs];
956}
957
958static u8 *
959qlcnic_get_bootld_offs(struct qlcnic_adapter *adapter)
960{
961 u32 offs = QLCNIC_BOOTLD_START;
63507592
SS		 962 struct uni_data_desc *data_desc;
963
964 data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_BOOTLD,
965 QLCNIC_UNI_BOOTLD_IDX_OFF);
af19b491 966
79788450 967 if (adapter->ahw->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
63507592 968 offs = le32_to_cpu(data_desc->findex);
af19b491
AKS		 969
970 return (u8 *)&adapter->fw->data[offs];
971}
972
973static u8 *
974qlcnic_get_fw_offs(struct qlcnic_adapter *adapter)
975{
976 u32 offs = QLCNIC_IMAGE_START;
63507592 977 struct uni_data_desc *data_desc;
af19b491 978
63507592
SS		 979 data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
980 QLCNIC_UNI_FIRMWARE_IDX_OFF);
79788450 981 if (adapter->ahw->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
63507592 982 offs = le32_to_cpu(data_desc->findex);
af19b491
AKS		 983
984 return (u8 *)&adapter->fw->data[offs];
985}
986
63507592 987static u32 qlcnic_get_fw_size(struct qlcnic_adapter *adapter)
af19b491 988{
63507592
SS		 989 struct uni_data_desc *data_desc;
990 const u8 *unirom = adapter->fw->data;
991
992 data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
993 QLCNIC_UNI_FIRMWARE_IDX_OFF);
994
79788450 995 if (adapter->ahw->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
63507592 996 return le32_to_cpu(data_desc->size);
af19b491 997 else
63507592 998 return le32_to_cpu(*(__le32 *)&unirom[QLCNIC_FW_SIZE_OFFSET]);
af19b491
AKS		 999}
1000
63507592 1001static u32 qlcnic_get_fw_version(struct qlcnic_adapter *adapter)
af19b491
AKS		 1002{
1003 struct uni_data_desc *fw_data_desc;
1004 const struct firmware *fw = adapter->fw;
63507592
SS		 1005 u32 major, minor, sub;
1006 __le32 version_offset;
af19b491
AKS		 1007 const u8 *ver_str;
1008 int i, ret;
1009
79788450 1010 if (adapter->ahw->fw_type != QLCNIC_UNIFIED_ROMIMAGE) {
63507592
SS		 1011 version_offset = *(__le32 *)&fw->data[QLCNIC_FW_VERSION_OFFSET];
1012 return le32_to_cpu(version_offset);
1013 }
af19b491
AKS		 1014
1015 fw_data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
1016 QLCNIC_UNI_FIRMWARE_IDX_OFF);
63507592
SS		 1017 ver_str = fw->data + le32_to_cpu(fw_data_desc->findex) +
1018 le32_to_cpu(fw_data_desc->size) - 17;
af19b491
AKS		 1019
1020 for (i = 0; i < 12; i++) {
1021 if (!strncmp(&ver_str[i], "REV=", 4)) {
1022 ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
1023 &major, &minor, &sub);
1024 if (ret != 3)
1025 return 0;
1026 else
1027 return major + (minor << 8) + (sub << 16);
1028 }
1029 }
1030
1031 return 0;
1032}
1033
63507592 1034static u32 qlcnic_get_bios_version(struct qlcnic_adapter *adapter)
af19b491
AKS		 1035{
1036 const struct firmware *fw = adapter->fw;
63507592
SS		 1037 u32 bios_ver, prd_off = adapter->file_prd_off;
1038 u8 *version_offset;
1039 __le32 temp;
af19b491 1040
79788450 1041 if (adapter->ahw->fw_type != QLCNIC_UNIFIED_ROMIMAGE) {
63507592
SS		 1042 version_offset = (u8 *)&fw->data[QLCNIC_BIOS_VERSION_OFFSET];
1043 return le32_to_cpu(*(__le32 *)version_offset);
1044 }
af19b491 1045
63507592
SS		 1046 temp = *((__le32 *)(&fw->data[prd_off]) + QLCNIC_UNI_BIOS_VERSION_OFF);
1047 bios_ver = le32_to_cpu(temp);
af19b491 1048
addd5abf 1049 return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) + (bios_ver >> 24);
af19b491
AKS		 1050}
1051
091754a1
SC		 1052static void qlcnic_rom_lock_recovery(struct qlcnic_adapter *adapter)
1053{
1054 if (qlcnic_pcie_sem_lock(adapter, 2, QLCNIC_ROM_LOCK_ID))
1055 dev_info(&adapter->pdev->dev, "Resetting rom_lock\n");
1056
1057 qlcnic_pcie_sem_unlock(adapter, 2);
1058}
1059
4e70812b
SC		 1060static int
1061qlcnic_check_fw_hearbeat(struct qlcnic_adapter *adapter)
1062{
1063 u32 heartbeat, ret = -EIO;
1064 int retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1065
a15ebd37
HM		 1066 adapter->heartbeat = QLC_SHARED_REG_RD32(adapter,
1067 QLCNIC_PEG_ALIVE_COUNTER);
4e70812b
SC		 1068
1069 do {
1070 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
a15ebd37
HM		 1071 heartbeat = QLC_SHARED_REG_RD32(adapter,
1072 QLCNIC_PEG_ALIVE_COUNTER);
4e70812b
SC		 1073 if (heartbeat != adapter->heartbeat) {
1074 ret = QLCNIC_RCODE_SUCCESS;
1075 break;
1076 }
1077 } while (--retries);
1078
1079 return ret;
1080}
1081
af19b491
AKS		 1082int
1083qlcnic_need_fw_reset(struct qlcnic_adapter *adapter)
1084{
032a13c7
SV		 1085 if ((adapter->flags & QLCNIC_FW_HANG) ||
1086 qlcnic_check_fw_hearbeat(adapter)) {
091754a1 1087 qlcnic_rom_lock_recovery(adapter);
af19b491 1088 return 1;
091754a1 1089 }
af19b491 1090
091754a1 1091 if (adapter->need_fw_reset)
af19b491
AKS		 1092 return 1;
1093
97f29d82
AKS		 1094 if (adapter->fw)
1095 return 1;
af19b491
AKS		 1096
1097 return 0;
1098}
1099
1100static const char *fw_name[] = {
1101 QLCNIC_UNIFIED_ROMIMAGE_NAME,
1102 QLCNIC_FLASH_ROMIMAGE_NAME,
1103};
1104
1105int
1106qlcnic_load_firmware(struct qlcnic_adapter *adapter)
1107{
63507592 1108 __le64 *ptr64;
af19b491
AKS		 1109 u32 i, flashaddr, size;
1110 const struct firmware *fw = adapter->fw;
1111 struct pci_dev *pdev = adapter->pdev;
1112
1113 dev_info(&pdev->dev, "loading firmware from %s\n",
79788450 1114 fw_name[adapter->ahw->fw_type]);
af19b491
AKS		 1115
1116 if (fw) {
63507592 1117 u64 data;
af19b491
AKS		 1118
1119 size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
1120
63507592 1121 ptr64 = (__le64 *)qlcnic_get_bootld_offs(adapter);
af19b491
AKS		 1122 flashaddr = QLCNIC_BOOTLD_START;
1123
1124 for (i = 0; i < size; i++) {
63507592 1125 data = le64_to_cpu(ptr64[i]);
af19b491
AKS		 1126
1127 if (qlcnic_pci_mem_write_2M(adapter, flashaddr, data))
1128 return -EIO;
1129
1130 flashaddr += 8;
1131 }
1132
63507592 1133 size = qlcnic_get_fw_size(adapter) / 8;
af19b491 1134
63507592 1135 ptr64 = (__le64 *)qlcnic_get_fw_offs(adapter);
af19b491
AKS		 1136 flashaddr = QLCNIC_IMAGE_START;
1137
1138 for (i = 0; i < size; i++) {
63507592 1139 data = le64_to_cpu(ptr64[i]);
af19b491
AKS		 1140
1141 if (qlcnic_pci_mem_write_2M(adapter,
1142 flashaddr, data))
1143 return -EIO;
1144
1145 flashaddr += 8;
1146 }
0bc92b5b 1147
63507592 1148 size = qlcnic_get_fw_size(adapter) % 8;
0bc92b5b 1149 if (size) {
63507592 1150 data = le64_to_cpu(ptr64[i]);
0bc92b5b
AKS		 1151
1152 if (qlcnic_pci_mem_write_2M(adapter,
1153 flashaddr, data))
1154 return -EIO;
1155 }
1156
af19b491
AKS		 1157 } else {
1158 u64 data;
1159 u32 hi, lo;
f8d54811
SV		 1160 int ret;
1161 struct qlcnic_flt_entry bootld_entry;
1162
1163 ret = qlcnic_get_flt_entry(adapter, QLCNIC_BOOTLD_REGION,
1164 &bootld_entry);
1165 if (!ret) {
1166 size = bootld_entry.size / 8;
1167 flashaddr = bootld_entry.start_addr;
1168 } else {
1169 size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
1170 flashaddr = QLCNIC_BOOTLD_START;
1171 dev_info(&pdev->dev,
1172 "using legacy method to get flash fw region");
1173 }
af19b491
AKS		 1174
1175 for (i = 0; i < size; i++) {
1176 if (qlcnic_rom_fast_read(adapter,
1177 flashaddr, (int *)&lo) != 0)
1178 return -EIO;
1179 if (qlcnic_rom_fast_read(adapter,
1180 flashaddr + 4, (int *)&hi) != 0)
1181 return -EIO;
1182
1183 data = (((u64)hi << 32) | lo);
1184
1185 if (qlcnic_pci_mem_write_2M(adapter,
1186 flashaddr, data))
1187 return -EIO;
1188
1189 flashaddr += 8;
1190 }
1191 }
1192 msleep(1);
1193
1194 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x18, 0x1020);
1195 QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0x80001e);
1196 return 0;
1197}
1198
1199static int
1200qlcnic_validate_firmware(struct qlcnic_adapter *adapter)
1201{
63507592 1202 u32 val;
8f891387 1203 u32 ver, bios, min_size;
af19b491
AKS		 1204 struct pci_dev *pdev = adapter->pdev;
1205 const struct firmware *fw = adapter->fw;
79788450 1206 u8 fw_type = adapter->ahw->fw_type;
af19b491
AKS		 1207
1208 if (fw_type == QLCNIC_UNIFIED_ROMIMAGE) {
b7eff100 1209 if (qlcnic_validate_unified_romimage(adapter))
af19b491
AKS		 1210 return -EINVAL;
1211
1212 min_size = QLCNIC_UNI_FW_MIN_SIZE;
1213 } else {
63507592
SS		 1214 val = le32_to_cpu(*(__le32 *)&fw->data[QLCNIC_FW_MAGIC_OFFSET]);
1215 if (val != QLCNIC_BDINFO_MAGIC)
af19b491
AKS		 1216 return -EINVAL;
1217
1218 min_size = QLCNIC_FW_MIN_SIZE;
1219 }
1220
1221 if (fw->size < min_size)
1222 return -EINVAL;
1223
1224 val = qlcnic_get_fw_version(adapter);
af19b491
AKS		 1225 ver = QLCNIC_DECODE_VERSION(val);
1226
8f891387 1227 if (ver < QLCNIC_MIN_FW_VERSION) {
af19b491
AKS		 1228 dev_err(&pdev->dev,
1229 "%s: firmware version %d.%d.%d unsupported\n",
1230 fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
1231 return -EINVAL;
1232 }
1233
1234 val = qlcnic_get_bios_version(adapter);
1235 qlcnic_rom_fast_read(adapter, QLCNIC_BIOS_VERSION_OFFSET, (int *)&bios);
63507592 1236 if (val != bios) {
af19b491
AKS		 1237 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
1238 fw_name[fw_type]);
1239 return -EINVAL;
1240 }
1241
a15ebd37 1242 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, QLCNIC_BDINFO_MAGIC);
af19b491
AKS		 1243 return 0;
1244}
1245
1246static void
1247qlcnic_get_next_fwtype(struct qlcnic_adapter *adapter)
1248{
1249 u8 fw_type;
1250
79788450 1251 switch (adapter->ahw->fw_type) {
af19b491
AKS		 1252 case QLCNIC_UNKNOWN_ROMIMAGE:
1253 fw_type = QLCNIC_UNIFIED_ROMIMAGE;
1254 break;
1255
1256 case QLCNIC_UNIFIED_ROMIMAGE:
1257 default:
1258 fw_type = QLCNIC_FLASH_ROMIMAGE;
1259 break;
1260 }
1261
79788450 1262 adapter->ahw->fw_type = fw_type;
af19b491
AKS		 1263}
1264
1265
1266
1267void qlcnic_request_firmware(struct qlcnic_adapter *adapter)
1268{
1269 struct pci_dev *pdev = adapter->pdev;
1270 int rc;
1271
79788450 1272 adapter->ahw->fw_type = QLCNIC_UNKNOWN_ROMIMAGE;
af19b491
AKS		 1273
1274next:
1275 qlcnic_get_next_fwtype(adapter);
1276
79788450 1277 if (adapter->ahw->fw_type == QLCNIC_FLASH_ROMIMAGE) {
af19b491
AKS		 1278 adapter->fw = NULL;
1279 } else {
1280 rc = request_firmware(&adapter->fw,
79788450
SC		 1281 fw_name[adapter->ahw->fw_type],
1282 &pdev->dev);
af19b491
AKS		 1283 if (rc != 0)
1284 goto next;
1285
1286 rc = qlcnic_validate_firmware(adapter);
1287 if (rc != 0) {
1288 release_firmware(adapter->fw);
1289 msleep(1);
1290 goto next;
1291 }
1292 }
1293}
1294
1295
1296void
1297qlcnic_release_firmware(struct qlcnic_adapter *adapter)
1298{
62baaf34 1299 release_firmware(adapter->fw);
af19b491
AKS		 1300 adapter->fw = NULL;
1301}
Linux 6.x block layer and io_uring tree(s)