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Documentation: fix neigh/default/gc_thresh1 default value.
[linux-2.6-block.git] / drivers / net / ethernet / qlogic / netxen / netxen_nic_init.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
13af7a6e 3 * Copyright (C) 2009 - QLogic Corporation.
3d396eb1 4 * All rights reserved.
80922fbc 5 *
3d396eb1
AK		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
80922fbc 10 *
3d396eb1
AK		 11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
80922fbc 15 *
3d396eb1
AK		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
80922fbc 20 *
3d396eb1 21 * The full GNU General Public License is included in this distribution
4d21fef4 22 * in the file called "COPYING".
80922fbc 23 *
3d396eb1
AK		 24 */
25
26#include <linux/netdevice.h>
27#include <linux/delay.h>
5a0e3ad6 28#include <linux/slab.h>
57569d0e 29#include <linux/if_vlan.h>
3d396eb1
AK		 30#include "netxen_nic.h"
31#include "netxen_nic_hw.h"
3d396eb1
AK		 32
33struct crb_addr_pair {
e0e20a1a
LCMT		 34 u32 addr;
35 u32 data;
3d396eb1
AK		 36};
37
38#define NETXEN_MAX_CRB_XFORM 60
39static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
e0e20a1a 40#define NETXEN_ADDR_ERROR (0xffffffff)
3d396eb1
AK		 41
42#define crb_addr_transform(name) \
43 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
44 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
45
cb8011ad
AK		 46#define NETXEN_NIC_XDMA_RESET 0x8000ff
47
becf46a0 48static void
d8b100c5
DP		 49netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
50 struct nx_host_rds_ring *rds_ring);
f50330f9 51static int netxen_p3_has_mn(struct netxen_adapter *adapter);
993fb90c 52
3d396eb1
AK		 53static void crb_addr_transform_setup(void)
54{
55 crb_addr_transform(XDMA);
56 crb_addr_transform(TIMR);
57 crb_addr_transform(SRE);
58 crb_addr_transform(SQN3);
59 crb_addr_transform(SQN2);
60 crb_addr_transform(SQN1);
61 crb_addr_transform(SQN0);
62 crb_addr_transform(SQS3);
63 crb_addr_transform(SQS2);
64 crb_addr_transform(SQS1);
65 crb_addr_transform(SQS0);
66 crb_addr_transform(RPMX7);
67 crb_addr_transform(RPMX6);
68 crb_addr_transform(RPMX5);
69 crb_addr_transform(RPMX4);
70 crb_addr_transform(RPMX3);
71 crb_addr_transform(RPMX2);
72 crb_addr_transform(RPMX1);
73 crb_addr_transform(RPMX0);
74 crb_addr_transform(ROMUSB);
75 crb_addr_transform(SN);
76 crb_addr_transform(QMN);
77 crb_addr_transform(QMS);
78 crb_addr_transform(PGNI);
79 crb_addr_transform(PGND);
80 crb_addr_transform(PGN3);
81 crb_addr_transform(PGN2);
82 crb_addr_transform(PGN1);
83 crb_addr_transform(PGN0);
84 crb_addr_transform(PGSI);
85 crb_addr_transform(PGSD);
86 crb_addr_transform(PGS3);
87 crb_addr_transform(PGS2);
88 crb_addr_transform(PGS1);
89 crb_addr_transform(PGS0);
90 crb_addr_transform(PS);
91 crb_addr_transform(PH);
92 crb_addr_transform(NIU);
93 crb_addr_transform(I2Q);
94 crb_addr_transform(EG);
95 crb_addr_transform(MN);
96 crb_addr_transform(MS);
97 crb_addr_transform(CAS2);
98 crb_addr_transform(CAS1);
99 crb_addr_transform(CAS0);
100 crb_addr_transform(CAM);
101 crb_addr_transform(C2C1);
102 crb_addr_transform(C2C0);
1fcca1a5 103 crb_addr_transform(SMB);
e4c93c81
DP		 104 crb_addr_transform(OCM0);
105 crb_addr_transform(I2C0);
3d396eb1
AK		 106}
107
2956640d 108void netxen_release_rx_buffers(struct netxen_adapter *adapter)
3d396eb1 109{
2956640d 110 struct netxen_recv_context *recv_ctx;
48bfd1e0 111 struct nx_host_rds_ring *rds_ring;
2956640d 112 struct netxen_rx_buffer *rx_buf;
becf46a0
DP		 113 int i, ring;
114
115 recv_ctx = &adapter->recv_ctx;
116 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
117 rds_ring = &recv_ctx->rds_rings[ring];
438627c7 118 for (i = 0; i < rds_ring->num_desc; ++i) {
becf46a0
DP		 119 rx_buf = &(rds_ring->rx_buf_arr[i]);
120 if (rx_buf->state == NETXEN_BUFFER_FREE)
121 continue;
122 pci_unmap_single(adapter->pdev,
123 rx_buf->dma,
124 rds_ring->dma_size,
125 PCI_DMA_FROMDEVICE);
126 if (rx_buf->skb != NULL)
127 dev_kfree_skb_any(rx_buf->skb);
2956640d
DP		 128 }
129 }
130}
131
132void netxen_release_tx_buffers(struct netxen_adapter *adapter)
133{
134 struct netxen_cmd_buffer *cmd_buf;
135 struct netxen_skb_frag *buffrag;
136 int i, j;
4ea528a1 137 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
2956640d 138
d877f1e3
DP		 139 cmd_buf = tx_ring->cmd_buf_arr;
140 for (i = 0; i < tx_ring->num_desc; i++) {
2956640d
DP		 141 buffrag = cmd_buf->frag_array;
142 if (buffrag->dma) {
143 pci_unmap_single(adapter->pdev, buffrag->dma,
144 buffrag->length, PCI_DMA_TODEVICE);
145 buffrag->dma = 0ULL;
146 }
a05948f2 147 for (j = 1; j < cmd_buf->frag_count; j++) {
2956640d
DP		 148 buffrag++;
149 if (buffrag->dma) {
150 pci_unmap_page(adapter->pdev, buffrag->dma,
151 buffrag->length,
152 PCI_DMA_TODEVICE);
153 buffrag->dma = 0ULL;
154 }
155 }
2956640d
DP		 156 if (cmd_buf->skb) {
157 dev_kfree_skb_any(cmd_buf->skb);
158 cmd_buf->skb = NULL;
159 }
160 cmd_buf++;
161 }
162}
163
164void netxen_free_sw_resources(struct netxen_adapter *adapter)
165{
166 struct netxen_recv_context *recv_ctx;
48bfd1e0 167 struct nx_host_rds_ring *rds_ring;
d877f1e3 168 struct nx_host_tx_ring *tx_ring;
becf46a0
DP		 169 int ring;
170
171 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 172
173 if (recv_ctx->rds_rings == NULL)
174 goto skip_rds;
175
becf46a0
DP		 176 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
177 rds_ring = &recv_ctx->rds_rings[ring];
f2333a01
F		 178 vfree(rds_ring->rx_buf_arr);
179 rds_ring->rx_buf_arr = NULL;
2956640d 180 }
4ea528a1
DP		 181 kfree(recv_ctx->rds_rings);
182
183skip_rds:
184 if (adapter->tx_ring == NULL)
185 return;
becf46a0 186
4ea528a1 187 tx_ring = adapter->tx_ring;
f2333a01 188 vfree(tx_ring->cmd_buf_arr);
011f4ea0
AKS		 189 kfree(tx_ring);
190 adapter->tx_ring = NULL;
2956640d
DP		 191}
192
193int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
194{
195 struct netxen_recv_context *recv_ctx;
48bfd1e0 196 struct nx_host_rds_ring *rds_ring;
d8b100c5 197 struct nx_host_sds_ring *sds_ring;
4ea528a1 198 struct nx_host_tx_ring *tx_ring;
2956640d 199 struct netxen_rx_buffer *rx_buf;
b2adaca9 200 int ring, i;
2956640d
DP		 201
202 struct netxen_cmd_buffer *cmd_buf_arr;
203 struct net_device *netdev = adapter->netdev;
204
b2adaca9
JP		 205 tx_ring = kzalloc(sizeof(struct nx_host_tx_ring), GFP_KERNEL);
206 if (tx_ring == NULL)
4ea528a1 207 return -ENOMEM;
b2adaca9 208
4ea528a1
DP		 209 adapter->tx_ring = tx_ring;
210
d877f1e3 211 tx_ring->num_desc = adapter->num_txd;
b2af9cb0 212 tx_ring->txq = netdev_get_tx_queue(netdev, 0);
4ea528a1 213
89bf67f1 214 cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
b2adaca9 215 if (cmd_buf_arr == NULL)
bf445080 216 goto err_out;
b2adaca9 217
d877f1e3 218 tx_ring->cmd_buf_arr = cmd_buf_arr;
2956640d 219
becf46a0 220 recv_ctx = &adapter->recv_ctx;
4ea528a1 221
b2adaca9
JP		 222 rds_ring = kcalloc(adapter->max_rds_rings,
223 sizeof(struct nx_host_rds_ring), GFP_KERNEL);
224 if (rds_ring == NULL)
bf445080 225 goto err_out;
b2adaca9 226
4ea528a1
DP		 227 recv_ctx->rds_rings = rds_ring;
228
becf46a0
DP		 229 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
230 rds_ring = &recv_ctx->rds_rings[ring];
438627c7
DP		 231 switch (ring) {
232 case RCV_RING_NORMAL:
233 rds_ring->num_desc = adapter->num_rxd;
becf46a0
DP		 234 if (adapter->ahw.cut_through) {
235 rds_ring->dma_size =
236 NX_CT_DEFAULT_RX_BUF_LEN;
48bfd1e0 237 rds_ring->skb_size =
becf46a0
DP		 238 NX_CT_DEFAULT_RX_BUF_LEN;
239 } else {
9b08beba
DP		 240 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
241 rds_ring->dma_size =
242 NX_P3_RX_BUF_MAX_LEN;
243 else
244 rds_ring->dma_size =
245 NX_P2_RX_BUF_MAX_LEN;
becf46a0 246 rds_ring->skb_size =
9b08beba 247 rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 248 }
249 break;
2956640d 250
438627c7
DP		 251 case RCV_RING_JUMBO:
252 rds_ring->num_desc = adapter->num_jumbo_rxd;
becf46a0
DP		 253 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
254 rds_ring->dma_size =
255 NX_P3_RX_JUMBO_BUF_MAX_LEN;
256 else
257 rds_ring->dma_size =
258 NX_P2_RX_JUMBO_BUF_MAX_LEN;
bc75e5bf
DP		 259
260 if (adapter->capabilities & NX_CAP0_HW_LRO)
261 rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
262
becf46a0
DP		 263 rds_ring->skb_size =
264 rds_ring->dma_size + NET_IP_ALIGN;
265 break;
2956640d 266
becf46a0 267 case RCV_RING_LRO:
438627c7 268 rds_ring->num_desc = adapter->num_lro_rxd;
9b08beba
DP		 269 rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
270 rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 271 break;
272
273 }
0acdf68f 274 rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
e404decb 275 if (rds_ring->rx_buf_arr == NULL)
becf46a0
DP		 276 /* free whatever was already allocated */
277 goto err_out;
e404decb 278
becf46a0
DP		 279 INIT_LIST_HEAD(&rds_ring->free_list);
280 /*
281 * Now go through all of them, set reference handles
282 * and put them in the queues.
283 */
becf46a0 284 rx_buf = rds_ring->rx_buf_arr;
4ea528a1 285 for (i = 0; i < rds_ring->num_desc; i++) {
becf46a0
DP		 286 list_add_tail(&rx_buf->list,
287 &rds_ring->free_list);
288 rx_buf->ref_handle = i;
289 rx_buf->state = NETXEN_BUFFER_FREE;
290 rx_buf++;
3d396eb1 291 }
d8b100c5
DP		 292 spin_lock_init(&rds_ring->lock);
293 }
294
295 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
296 sds_ring = &recv_ctx->sds_rings[ring];
297 sds_ring->irq = adapter->msix_entries[ring].vector;
d8b100c5
DP		 298 sds_ring->adapter = adapter;
299 sds_ring->num_desc = adapter->num_rxd;
300
301 for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
302 INIT_LIST_HEAD(&sds_ring->free_list[i]);
3d396eb1 303 }
2956640d
DP		 304
305 return 0;
306
307err_out:
308 netxen_free_sw_resources(adapter);
309 return -ENOMEM;
3d396eb1
AK		 310}
311
3d396eb1
AK		 312/*
313 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
314 * address to external PCI CRB address.
315 */
993fb90c 316static u32 netxen_decode_crb_addr(u32 addr)
3d396eb1
AK		 317{
318 int i;
e0e20a1a 319 u32 base_addr, offset, pci_base;
3d396eb1
AK		 320
321 crb_addr_transform_setup();
322
323 pci_base = NETXEN_ADDR_ERROR;
324 base_addr = addr & 0xfff00000;
325 offset = addr & 0x000fffff;
326
327 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
328 if (crb_addr_xform[i] == base_addr) {
329 pci_base = i << 20;
330 break;
331 }
332 }
333 if (pci_base == NETXEN_ADDR_ERROR)
334 return pci_base;
335 else
807540ba 336 return pci_base + offset;
3d396eb1
AK		 337}
338
c9517e58 339#define NETXEN_MAX_ROM_WAIT_USEC 100
3d396eb1 340
993fb90c 341static int netxen_wait_rom_done(struct netxen_adapter *adapter)
3d396eb1
AK		 342{
343 long timeout = 0;
344 long done = 0;
345
27c915a4
DP		 346 cond_resched();
347
3d396eb1 348 while (done == 0) {
f98a9f69 349 done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
3d396eb1 350 done &= 2;
c9517e58
DP		 351 if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
352 dev_err(&adapter->pdev->dev,
353 "Timeout reached waiting for rom done");
3d396eb1
AK		 354 return -EIO;
355 }
c9517e58 356 udelay(1);
3d396eb1
AK		 357 }
358 return 0;
359}
360
993fb90c
AB		 361static int do_rom_fast_read(struct netxen_adapter *adapter,
362 int addr, int *valp)
3d396eb1 363{
f98a9f69
DP		 364 NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
365 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
366 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
367 NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
3d396eb1
AK		 368 if (netxen_wait_rom_done(adapter)) {
369 printk("Error waiting for rom done\n");
370 return -EIO;
371 }
372 /* reset abyte_cnt and dummy_byte_cnt */
f98a9f69 373 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
27c915a4 374 udelay(10);
f98a9f69 375 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
3d396eb1 376
f98a9f69 377 *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
3d396eb1
AK		 378 return 0;
379}
380
993fb90c
AB		 381static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
382 u8 *bytes, size_t size)
27d2ab54
AK		 383{
384 int addridx;
385 int ret = 0;
386
387 for (addridx = addr; addridx < (addr + size); addridx += 4) {
f305f789
AV		 388 int v;
389 ret = do_rom_fast_read(adapter, addridx, &v);
27d2ab54
AK		 390 if (ret != 0)
391 break;
f305f789 392 *(__le32 *)bytes = cpu_to_le32(v);
27d2ab54
AK		 393 bytes += 4;
394 }
395
396 return ret;
397}
398
399int
4790654c 400netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
27d2ab54
AK		 401 u8 *bytes, size_t size)
402{
403 int ret;
404
c9517e58 405 ret = netxen_rom_lock(adapter);
27d2ab54
AK		 406 if (ret < 0)
407 return ret;
408
409 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
410
411 netxen_rom_unlock(adapter);
412 return ret;
413}
414
3d396eb1
AK		 415int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
416{
417 int ret;
418
c9517e58 419 if (netxen_rom_lock(adapter) != 0)
3d396eb1
AK		 420 return -EIO;
421
422 ret = do_rom_fast_read(adapter, addr, valp);
cb8011ad
AK		 423 netxen_rom_unlock(adapter);
424 return ret;
425}
426
3d396eb1
AK		 427#define NETXEN_BOARDTYPE 0x4008
428#define NETXEN_BOARDNUM 0x400c
429#define NETXEN_CHIPNUM 0x4010
3d396eb1 430
0be367bd 431int netxen_pinit_from_rom(struct netxen_adapter *adapter)
3d396eb1 432{
dcd56fdb 433 int addr, val;
27c915a4 434 int i, n, init_delay = 0;
3d396eb1 435 struct crb_addr_pair *buf;
27c915a4 436 unsigned offset;
e0e20a1a 437 u32 off;
3d396eb1
AK		 438
439 /* resetall */
c9517e58 440 netxen_rom_lock(adapter);
83f18a55 441 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xfeffffff);
27c915a4 442 netxen_rom_unlock(adapter);
3d396eb1 443
2956640d
DP		 444 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
445 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
27c915a4 446 (n != 0xcafecafe) ||
2956640d
DP		 447 netxen_rom_fast_read(adapter, 4, &n) != 0) {
448 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
449 "n: %08x\n", netxen_nic_driver_name, n);
3d396eb1
AK		 450 return -EIO;
451 }
2956640d
DP		 452 offset = n & 0xffffU;
453 n = (n >> 16) & 0xffffU;
454 } else {
455 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
456 !(n & 0x80000000)) {
457 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
458 "n: %08x\n", netxen_nic_driver_name, n);
459 return -EIO;
3d396eb1 460 }
2956640d
DP		 461 offset = 1;
462 n &= ~0x80000000;
463 }
464
0be367bd 465 if (n >= 1024) {
2956640d
DP		 466 printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
467 " initialized.\n", __func__, n);
468 return -EIO;
469 }
3d396eb1 470
2956640d 471 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
e404decb 472 if (buf == NULL)
2956640d 473 return -ENOMEM;
0be367bd 474
2956640d
DP		 475 for (i = 0; i < n; i++) {
476 if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
584dbe94
DM		 477 netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
478 kfree(buf);
2956640d 479 return -EIO;
584dbe94 480 }
2956640d
DP		 481
482 buf[i].addr = addr;
483 buf[i].data = val;
484
2956640d 485 }
0be367bd 486
2956640d
DP		 487 for (i = 0; i < n; i++) {
488
489 off = netxen_decode_crb_addr(buf[i].addr);
490 if (off == NETXEN_ADDR_ERROR) {
491 printk(KERN_ERR"CRB init value out of range %x\n",
1fcca1a5 492 buf[i].addr);
2956640d
DP		 493 continue;
494 }
495 off += NETXEN_PCI_CRBSPACE;
0be367bd
AKS		 496
497 if (off & 1)
498 continue;
499
2956640d
DP		 500 /* skipping cold reboot MAGIC */
501 if (off == NETXEN_CAM_RAM(0x1fc))
502 continue;
503
504 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
8bee0a91
DP		 505 if (off == (NETXEN_CRB_I2C0 + 0x1c))
506 continue;
2956640d
DP		 507 /* do not reset PCI */
508 if (off == (ROMUSB_GLB + 0xbc))
1fcca1a5 509 continue;
27c915a4
DP		 510 if (off == (ROMUSB_GLB + 0xa8))
511 continue;
512 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
513 continue;
514 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
515 continue;
516 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
517 continue;
e7473f12
AKS		 518 if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
519 continue;
0be367bd
AKS		 520 if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
521 !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
2956640d
DP		 522 buf[i].data = 0x1020;
523 /* skip the function enable register */
524 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
3d396eb1 525 continue;
2956640d
DP		 526 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
527 continue;
528 if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
529 continue;
530 }
3d396eb1 531
27c915a4 532 init_delay = 1;
2956640d
DP		 533 /* After writing this register, HW needs time for CRB */
534 /* to quiet down (else crb_window returns 0xffffffff) */
535 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
27c915a4 536 init_delay = 1000;
2956640d 537 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
3d396eb1 538 /* hold xdma in reset also */
cb8011ad 539 buf[i].data = NETXEN_NIC_XDMA_RESET;
27c915a4 540 buf[i].data = 0x8000ff;
3d396eb1 541 }
2956640d 542 }
3d396eb1 543
f98a9f69 544 NXWR32(adapter, off, buf[i].data);
3d396eb1 545
27c915a4 546 msleep(init_delay);
2956640d
DP		 547 }
548 kfree(buf);
3d396eb1 549
2956640d 550 /* disable_peg_cache_all */
3d396eb1 551
2956640d
DP		 552 /* unreset_net_cache */
553 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
f98a9f69
DP		 554 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
555 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
3d396eb1 556 }
2956640d
DP		 557
558 /* p2dn replyCount */
f98a9f69 559 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
2956640d 560 /* disable_peg_cache 0 */
f98a9f69 561 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
2956640d 562 /* disable_peg_cache 1 */
f98a9f69 563 NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
2956640d
DP		 564
565 /* peg_clr_all */
566
567 /* peg_clr 0 */
f98a9f69
DP		 568 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
569 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
2956640d 570 /* peg_clr 1 */
f98a9f69
DP		 571 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
572 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
2956640d 573 /* peg_clr 2 */
f98a9f69
DP		 574 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
575 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
2956640d 576 /* peg_clr 3 */
f98a9f69
DP		 577 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
578 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
3d396eb1
AK		 579 return 0;
580}
581
f50330f9
AKS		 582static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
583{
584 uint32_t i;
585 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
586 __le32 entries = cpu_to_le32(directory->num_entries);
587
588 for (i = 0; i < entries; i++) {
589
590 __le32 offs = cpu_to_le32(directory->findex) +
591 (i * cpu_to_le32(directory->entry_size));
592 __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
593
594 if (tab_type == section)
595 return (struct uni_table_desc *) &unirom[offs];
596 }
597
598 return NULL;
599}
600
10c0f2a8
RB		 601#define QLCNIC_FILEHEADER_SIZE (14 * 4)
602
f50330f9 603static int
10c0f2a8
RB		 604netxen_nic_validate_header(struct netxen_adapter *adapter)
605 {
f50330f9 606 const u8 *unirom = adapter->fw->data;
10c0f2a8
RB		 607 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
608 u32 fw_file_size = adapter->fw->size;
609 u32 tab_size;
f50330f9 610 __le32 entries;
10c0f2a8
RB		 611 __le32 entry_size;
612
613 if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
614 return -EINVAL;
615
616 entries = cpu_to_le32(directory->num_entries);
617 entry_size = cpu_to_le32(directory->entry_size);
618 tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
619
620 if (fw_file_size < tab_size)
621 return -EINVAL;
622
623 return 0;
624}
625
626static int
627netxen_nic_validate_bootld(struct netxen_adapter *adapter)
628{
629 struct uni_table_desc *tab_desc;
630 struct uni_data_desc *descr;
631 const u8 *unirom = adapter->fw->data;
632 __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
633 NX_UNI_BOOTLD_IDX_OFF));
634 u32 offs;
635 u32 tab_size;
636 u32 data_size;
637
638 tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
639
640 if (!tab_desc)
641 return -EINVAL;
642
643 tab_size = cpu_to_le32(tab_desc->findex) +
644 (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
645
646 if (adapter->fw->size < tab_size)
647 return -EINVAL;
648
649 offs = cpu_to_le32(tab_desc->findex) +
650 (cpu_to_le32(tab_desc->entry_size) * (idx));
651 descr = (struct uni_data_desc *)&unirom[offs];
652
653 data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
654
655 if (adapter->fw->size < data_size)
656 return -EINVAL;
657
658 return 0;
659}
660
661static int
662netxen_nic_validate_fw(struct netxen_adapter *adapter)
663{
664 struct uni_table_desc *tab_desc;
665 struct uni_data_desc *descr;
666 const u8 *unirom = adapter->fw->data;
667 __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
668 NX_UNI_FIRMWARE_IDX_OFF));
669 u32 offs;
670 u32 tab_size;
671 u32 data_size;
672
673 tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
674
675 if (!tab_desc)
676 return -EINVAL;
f50330f9 677
10c0f2a8
RB		 678 tab_size = cpu_to_le32(tab_desc->findex) +
679 (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
680
681 if (adapter->fw->size < tab_size)
682 return -EINVAL;
683
684 offs = cpu_to_le32(tab_desc->findex) +
685 (cpu_to_le32(tab_desc->entry_size) * (idx));
686 descr = (struct uni_data_desc *)&unirom[offs];
687 data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
688
689 if (adapter->fw->size < data_size)
690 return -EINVAL;
691
692 return 0;
693}
694
695
696static int
697netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
698{
699 struct uni_table_desc *ptab_descr;
700 const u8 *unirom = adapter->fw->data;
634d7df8
DP		 701 int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
702 1 : netxen_p3_has_mn(adapter);
10c0f2a8
RB		 703 __le32 entries;
704 __le32 entry_size;
705 u32 tab_size;
706 u32 i;
634d7df8 707
f50330f9
AKS		 708 ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
709 if (ptab_descr == NULL)
10c0f2a8 710 return -EINVAL;
f50330f9
AKS		 711
712 entries = cpu_to_le32(ptab_descr->num_entries);
10c0f2a8
RB		 713 entry_size = cpu_to_le32(ptab_descr->entry_size);
714 tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
715
716 if (adapter->fw->size < tab_size)
717 return -EINVAL;
f50330f9 718
634d7df8 719nomn:
f50330f9
AKS		 720 for (i = 0; i < entries; i++) {
721
722 __le32 flags, file_chiprev, offs;
723 u8 chiprev = adapter->ahw.revision_id;
f50330f9
AKS		 724 uint32_t flagbit;
725
726 offs = cpu_to_le32(ptab_descr->findex) +
727 (i * cpu_to_le32(ptab_descr->entry_size));
728 flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
729 file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
730 NX_UNI_CHIP_REV_OFF));
731
732 flagbit = mn_present ? 1 : 2;
733
734 if ((chiprev == file_chiprev) &&
735 ((1ULL << flagbit) & flags)) {
736 adapter->file_prd_off = offs;
737 return 0;
738 }
739 }
740
634d7df8
DP		 741 if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
742 mn_present = 0;
743 goto nomn;
744 }
745
10c0f2a8 746 return -EINVAL;
f50330f9
AKS		 747}
748
10c0f2a8
RB		 749static int
750netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
751{
752 if (netxen_nic_validate_header(adapter)) {
753 dev_err(&adapter->pdev->dev,
754 "unified image: header validation failed\n");
755 return -EINVAL;
756 }
757
758 if (netxen_nic_validate_product_offs(adapter)) {
759 dev_err(&adapter->pdev->dev,
760 "unified image: product validation failed\n");
761 return -EINVAL;
762 }
763
764 if (netxen_nic_validate_bootld(adapter)) {
765 dev_err(&adapter->pdev->dev,
766 "unified image: bootld validation failed\n");
767 return -EINVAL;
768 }
769
770 if (netxen_nic_validate_fw(adapter)) {
771 dev_err(&adapter->pdev->dev,
772 "unified image: firmware validation failed\n");
773 return -EINVAL;
774 }
775
776 return 0;
777}
f50330f9
AKS		 778
779static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
780 u32 section, u32 idx_offset)
781{
782 const u8 *unirom = adapter->fw->data;
783 int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
784 idx_offset));
785 struct uni_table_desc *tab_desc;
786 __le32 offs;
787
788 tab_desc = nx_get_table_desc(unirom, section);
789
790 if (tab_desc == NULL)
791 return NULL;
792
793 offs = cpu_to_le32(tab_desc->findex) +
794 (cpu_to_le32(tab_desc->entry_size) * idx);
795
796 return (struct uni_data_desc *)&unirom[offs];
797}
798
799static u8 *
800nx_get_bootld_offs(struct netxen_adapter *adapter)
801{
802 u32 offs = NETXEN_BOOTLD_START;
803
804 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
805 offs = cpu_to_le32((nx_get_data_desc(adapter,
806 NX_UNI_DIR_SECT_BOOTLD,
807 NX_UNI_BOOTLD_IDX_OFF))->findex);
808
809 return (u8 *)&adapter->fw->data[offs];
810}
811
812static u8 *
813nx_get_fw_offs(struct netxen_adapter *adapter)
814{
815 u32 offs = NETXEN_IMAGE_START;
816
817 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
818 offs = cpu_to_le32((nx_get_data_desc(adapter,
819 NX_UNI_DIR_SECT_FW,
820 NX_UNI_FIRMWARE_IDX_OFF))->findex);
821
822 return (u8 *)&adapter->fw->data[offs];
823}
824
825static __le32
826nx_get_fw_size(struct netxen_adapter *adapter)
827{
828 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
829 return cpu_to_le32((nx_get_data_desc(adapter,
830 NX_UNI_DIR_SECT_FW,
831 NX_UNI_FIRMWARE_IDX_OFF))->size);
832 else
833 return cpu_to_le32(
834 *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
835}
836
837static __le32
838nx_get_fw_version(struct netxen_adapter *adapter)
839{
840 struct uni_data_desc *fw_data_desc;
841 const struct firmware *fw = adapter->fw;
842 __le32 major, minor, sub;
843 const u8 *ver_str;
844 int i, ret = 0;
845
846 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
847
848 fw_data_desc = nx_get_data_desc(adapter,
849 NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
850 ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
851 cpu_to_le32(fw_data_desc->size) - 17;
852
853 for (i = 0; i < 12; i++) {
854 if (!strncmp(&ver_str[i], "REV=", 4)) {
855 ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
856 &major, &minor, &sub);
857 break;
858 }
859 }
860
861 if (ret != 3)
862 return 0;
863
864 return major + (minor << 8) + (sub << 16);
865
866 } else
867 return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
868}
869
870static __le32
871nx_get_bios_version(struct netxen_adapter *adapter)
872{
873 const struct firmware *fw = adapter->fw;
874 __le32 bios_ver, prd_off = adapter->file_prd_off;
875
876 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
877 bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
878 + NX_UNI_BIOS_VERSION_OFF));
bb2792e0 879 return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
f50330f9
AKS		 880 (bios_ver >> 24);
881 } else
882 return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
883
884}
885
67c38fc6
DP		 886int
887netxen_need_fw_reset(struct netxen_adapter *adapter)
888{
889 u32 count, old_count;
890 u32 val, version, major, minor, build;
891 int i, timeout;
892 u8 fw_type;
893
894 /* NX2031 firmware doesn't support heartbit */
895 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
896 return 1;
897
6a808c6c
AKS		 898 if (adapter->need_fw_reset)
899 return 1;
900
67c38fc6
DP		 901 /* last attempt had failed */
902 if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
903 return 1;
904
581e8ae4 905 old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
67c38fc6
DP		 906
907 for (i = 0; i < 10; i++) {
908
909 timeout = msleep_interruptible(200);
910 if (timeout) {
911 NXWR32(adapter, CRB_CMDPEG_STATE,
912 PHAN_INITIALIZE_FAILED);
913 return -EINTR;
914 }
915
916 count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
917 if (count != old_count)
918 break;
919 }
920
921 /* firmware is dead */
922 if (count == old_count)
923 return 1;
924
925 /* check if we have got newer or different file firmware */
926 if (adapter->fw) {
927
f50330f9 928 val = nx_get_fw_version(adapter);
67c38fc6 929
67c38fc6
DP		 930 version = NETXEN_DECODE_VERSION(val);
931
932 major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
933 minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
934 build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
935
936 if (version > NETXEN_VERSION_CODE(major, minor, build))
937 return 1;
938
f50330f9
AKS		 939 if (version == NETXEN_VERSION_CODE(major, minor, build) &&
940 adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
67c38fc6
DP		 941
942 val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
943 fw_type = (val & 0x4) ?
944 NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
945
946 if (adapter->fw_type != fw_type)
947 return 1;
948 }
949 }
950
951 return 0;
952}
953
e933d019
AKS		 954#define NETXEN_MIN_P3_FW_SUPP NETXEN_VERSION_CODE(4, 0, 505)
955
956int
957netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter)
958{
959 u32 flash_fw_ver, min_fw_ver;
960
961 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
962 return 0;
963
964 if (netxen_rom_fast_read(adapter,
965 NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
966 dev_err(&adapter->pdev->dev, "Unable to read flash fw"
967 "version\n");
968 return -EIO;
969 }
970
971 flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
972 min_fw_ver = NETXEN_MIN_P3_FW_SUPP;
973 if (flash_fw_ver >= min_fw_ver)
974 return 0;
975
976 dev_info(&adapter->pdev->dev, "Flash fw[%d.%d.%d] is < min fw supported"
977 "[4.0.505]. Please update firmware on flash\n",
978 _major(flash_fw_ver), _minor(flash_fw_ver),
979 _build(flash_fw_ver));
980 return -EINVAL;
981}
982
67c38fc6 983static char *fw_name[] = {
7e8e5d97
DP		 984 NX_P2_MN_ROMIMAGE_NAME,
985 NX_P3_CT_ROMIMAGE_NAME,
986 NX_P3_MN_ROMIMAGE_NAME,
987 NX_UNIFIED_ROMIMAGE_NAME,
988 NX_FLASH_ROMIMAGE_NAME,
67c38fc6
DP		 989};
990
f7185c71
DP		 991int
992netxen_load_firmware(struct netxen_adapter *adapter)
993{
994 u64 *ptr64;
995 u32 i, flashaddr, size;
996 const struct firmware *fw = adapter->fw;
67c38fc6
DP		 997 struct pci_dev *pdev = adapter->pdev;
998
999 dev_info(&pdev->dev, "loading firmware from %s\n",
1000 fw_name[adapter->fw_type]);
f7185c71
DP		 1001
1002 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1003 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
1004
1005 if (fw) {
1006 __le64 data;
1007
1008 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
1009
f50330f9 1010 ptr64 = (u64 *)nx_get_bootld_offs(adapter);
f7185c71
DP		 1011 flashaddr = NETXEN_BOOTLD_START;
1012
1013 for (i = 0; i < size; i++) {
1014 data = cpu_to_le64(ptr64[i]);
f50330f9
AKS		 1015
1016 if (adapter->pci_mem_write(adapter, flashaddr, data))
1f5e055d
AKS		 1017 return -EIO;
1018
f7185c71
DP		 1019 flashaddr += 8;
1020 }
1021
f50330f9 1022 size = (__force u32)nx_get_fw_size(adapter) / 8;
f7185c71 1023
f50330f9 1024 ptr64 = (u64 *)nx_get_fw_offs(adapter);
f7185c71
DP		 1025 flashaddr = NETXEN_IMAGE_START;
1026
1027 for (i = 0; i < size; i++) {
1028 data = cpu_to_le64(ptr64[i]);
1029
1030 if (adapter->pci_mem_write(adapter,
1f5e055d 1031 flashaddr, data))
f7185c71
DP		 1032 return -EIO;
1033
1034 flashaddr += 8;
1035 }
e270299a
AKS		 1036
1037 size = (__force u32)nx_get_fw_size(adapter) % 8;
1038 if (size) {
1039 data = cpu_to_le64(ptr64[i]);
1040
1041 if (adapter->pci_mem_write(adapter,
1042 flashaddr, data))
1043 return -EIO;
1044 }
1045
f7185c71 1046 } else {
f78c0850
AKS		 1047 u64 data;
1048 u32 hi, lo;
f7185c71 1049
f78c0850 1050 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
f7185c71
DP		 1051 flashaddr = NETXEN_BOOTLD_START;
1052
1053 for (i = 0; i < size; i++) {
1054 if (netxen_rom_fast_read(adapter,
1f5e055d 1055 flashaddr, (int *)&lo) != 0)
f78c0850
AKS		 1056 return -EIO;
1057 if (netxen_rom_fast_read(adapter,
1f5e055d 1058 flashaddr + 4, (int *)&hi) != 0)
f7185c71
DP		 1059 return -EIO;
1060
f78c0850
AKS		 1061 /* hi, lo are already in host endian byteorder */
1062 data = (((u64)hi << 32) | lo);
1063
f7185c71 1064 if (adapter->pci_mem_write(adapter,
1f5e055d 1065 flashaddr, data))
f7185c71
DP		 1066 return -EIO;
1067
f78c0850 1068 flashaddr += 8;
f7185c71
DP		 1069 }
1070 }
1071 msleep(1);
1072
0be367bd
AKS		 1073 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
1074 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
1075 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
1076 } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
f7185c71
DP		 1077 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1078 else {
1079 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1080 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
1081 }
1082
1083 return 0;
1084}
1085
1086static int
f50330f9 1087netxen_validate_firmware(struct netxen_adapter *adapter)
f7185c71
DP		 1088{
1089 __le32 val;
e933d019
AKS		 1090 __le32 flash_fw_ver;
1091 u32 file_fw_ver, min_ver, bios;
f7185c71
DP		 1092 struct pci_dev *pdev = adapter->pdev;
1093 const struct firmware *fw = adapter->fw;
f50330f9 1094 u8 fw_type = adapter->fw_type;
e933d019 1095 u32 crbinit_fix_fw;
f7185c71 1096
f50330f9 1097 if (fw_type == NX_UNIFIED_ROMIMAGE) {
10c0f2a8 1098 if (netxen_nic_validate_unified_romimage(adapter))
f50330f9 1099 return -EINVAL;
f50330f9
AKS		 1100 } else {
1101 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
1102 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
1103 return -EINVAL;
f7185c71 1104
10c0f2a8
RB		 1105 if (fw->size < NX_FW_MIN_SIZE)
1106 return -EINVAL;
f50330f9
AKS		 1107 }
1108
f50330f9 1109 val = nx_get_fw_version(adapter);
f7185c71
DP		 1110
1111 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
e933d019 1112 min_ver = NETXEN_MIN_P3_FW_SUPP;
f7185c71
DP		 1113 else
1114 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
1115
e933d019 1116 file_fw_ver = NETXEN_DECODE_VERSION(val);
f7185c71 1117
e933d019
AKS		 1118 if ((_major(file_fw_ver) > _NETXEN_NIC_LINUX_MAJOR) ||
1119 (file_fw_ver < min_ver)) {
f7185c71
DP		 1120 dev_err(&pdev->dev,
1121 "%s: firmware version %d.%d.%d unsupported\n",
e933d019
AKS		 1122 fw_name[fw_type], _major(file_fw_ver), _minor(file_fw_ver),
1123 _build(file_fw_ver));
f7185c71
DP		 1124 return -EINVAL;
1125 }
f50330f9 1126 val = nx_get_bios_version(adapter);
f7185c71
DP		 1127 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
1128 if ((__force u32)val != bios) {
1129 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
f50330f9 1130 fw_name[fw_type]);
f7185c71
DP		 1131 return -EINVAL;
1132 }
1133
f7185c71 1134 if (netxen_rom_fast_read(adapter,
e933d019
AKS		 1135 NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
1136 dev_err(&pdev->dev, "Unable to read flash fw version\n");
f7185c71 1137 return -EIO;
e933d019
AKS		 1138 }
1139 flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
1140
1141 /* New fw from file is not allowed, if fw on flash is < 4.0.554 */
1142 crbinit_fix_fw = NETXEN_VERSION_CODE(4, 0, 554);
1143 if (file_fw_ver >= crbinit_fix_fw && flash_fw_ver < crbinit_fix_fw &&
1144 NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1145 dev_err(&pdev->dev, "Incompatibility detected between driver "
1146 "and firmware version on flash. This configuration "
1147 "is not recommended. Please update the firmware on "
1148 "flash immediately\n");
f7185c71 1149 return -EINVAL;
98e31bb0 1150 }
f7185c71 1151
e933d019
AKS		 1152 /* check if flashed firmware is newer only for no-mn and P2 case*/
1153 if (!netxen_p3_has_mn(adapter) ||
1154 NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1155 if (flash_fw_ver > file_fw_ver) {
1156 dev_info(&pdev->dev, "%s: firmware is older than flash\n",
1157 fw_name[fw_type]);
1158 return -EINVAL;
1159 }
1160 }
1161
f7185c71
DP		 1162 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
1163 return 0;
1164}
1165
f50330f9
AKS		 1166static void
1167nx_get_next_fwtype(struct netxen_adapter *adapter)
1168{
1169 u8 fw_type;
1170
1171 switch (adapter->fw_type) {
1172 case NX_UNKNOWN_ROMIMAGE:
1173 fw_type = NX_UNIFIED_ROMIMAGE;
1174 break;
1175
1176 case NX_UNIFIED_ROMIMAGE:
1177 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
1178 fw_type = NX_FLASH_ROMIMAGE;
1179 else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1180 fw_type = NX_P2_MN_ROMIMAGE;
1181 else if (netxen_p3_has_mn(adapter))
1182 fw_type = NX_P3_MN_ROMIMAGE;
1183 else
1184 fw_type = NX_P3_CT_ROMIMAGE;
1185 break;
1186
1187 case NX_P3_MN_ROMIMAGE:
1188 fw_type = NX_P3_CT_ROMIMAGE;
1189 break;
1190
1191 case NX_P2_MN_ROMIMAGE:
1192 case NX_P3_CT_ROMIMAGE:
1193 default:
1194 fw_type = NX_FLASH_ROMIMAGE;
1195 break;
1196 }
1197
1198 adapter->fw_type = fw_type;
1199}
1200
6598b169
DP		 1201static int
1202netxen_p3_has_mn(struct netxen_adapter *adapter)
f7185c71
DP		 1203{
1204 u32 capability, flashed_ver;
f7185c71
DP		 1205 capability = 0;
1206
634d7df8
DP		 1207 /* NX2031 always had MN */
1208 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1209 return 1;
1210
f7185c71
DP		 1211 netxen_rom_fast_read(adapter,
1212 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
98e31bb0
DP		 1213 flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
1214
f7185c71 1215 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
6598b169 1216
f7185c71 1217 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
6598b169
DP		 1218 if (capability & NX_PEG_TUNE_MN_PRESENT)
1219 return 1;
1220 }
1221 return 0;
1222}
1223
1224void netxen_request_firmware(struct netxen_adapter *adapter)
1225{
6598b169
DP		 1226 struct pci_dev *pdev = adapter->pdev;
1227 int rc = 0;
1228
f50330f9 1229 adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
f7185c71 1230
f50330f9
AKS		 1231next:
1232 nx_get_next_fwtype(adapter);
f7185c71 1233
f50330f9 1234 if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
f7185c71 1235 adapter->fw = NULL;
f50330f9
AKS		 1236 } else {
1237 rc = request_firmware(&adapter->fw,
1238 fw_name[adapter->fw_type], &pdev->dev);
1239 if (rc != 0)
1240 goto next;
1241
1242 rc = netxen_validate_firmware(adapter);
1243 if (rc != 0) {
1244 release_firmware(adapter->fw);
f7185c71 1245 msleep(1);
f50330f9 1246 goto next;
f7185c71 1247 }
f7185c71 1248 }
f7185c71
DP		 1249}
1250
1251
1252void
1253netxen_release_firmware(struct netxen_adapter *adapter)
1254{
62baaf34 1255 release_firmware(adapter->fw);
db4cfd8a 1256 adapter->fw = NULL;
f7185c71
DP		 1257}
1258
83ac51fa 1259int netxen_init_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 1260{
83ac51fa
DP		 1261 u64 addr;
1262 u32 hi, lo;
ed25ffa1 1263
83ac51fa
DP		 1264 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1265 return 0;
1266
1267 adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
ed25ffa1
AK		 1268 NETXEN_HOST_DUMMY_DMA_SIZE,
1269 &adapter->dummy_dma.phys_addr);
1270 if (adapter->dummy_dma.addr == NULL) {
83ac51fa
DP		 1271 dev_err(&adapter->pdev->dev,
1272 "ERROR: Could not allocate dummy DMA memory\n");
ed25ffa1
AK		 1273 return -ENOMEM;
1274 }
1275
1276 addr = (uint64_t) adapter->dummy_dma.phys_addr;
1277 hi = (addr >> 32) & 0xffffffff;
1278 lo = addr & 0xffffffff;
1279
f98a9f69
DP		 1280 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
1281 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
ed25ffa1
AK		 1282
1283 return 0;
1284}
1285
83ac51fa
DP		 1286/*
1287 * NetXen DMA watchdog control:
1288 *
1289 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1290 * Bit 1 : disable_request => 1 req disable dma watchdog
1291 * Bit 2 : enable_request => 1 req enable dma watchdog
1292 * Bit 3-31 : unused
1293 */
1294void netxen_free_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 1295{
15eef1e1 1296 int i = 100;
83ac51fa
DP		 1297 u32 ctrl;
1298
1299 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1300 return;
15eef1e1
DP		 1301
1302 if (!adapter->dummy_dma.addr)
1303 return;
439b454e 1304
83ac51fa
DP		 1305 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1306 if ((ctrl & 0x1) != 0) {
1307 NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
1308
1309 while ((ctrl & 0x1) != 0) {
1310
439b454e 1311 msleep(50);
83ac51fa
DP		 1312
1313 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1314
1315 if (--i == 0)
439b454e 1316 break;
6403eab1 1317 }
15eef1e1 1318 }
439b454e 1319
15eef1e1
DP		 1320 if (i) {
1321 pci_free_consistent(adapter->pdev,
1322 NETXEN_HOST_DUMMY_DMA_SIZE,
1323 adapter->dummy_dma.addr,
1324 adapter->dummy_dma.phys_addr);
1325 adapter->dummy_dma.addr = NULL;
83ac51fa
DP		 1326 } else
1327 dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
ed25ffa1
AK		 1328}
1329
96acb6eb 1330int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
3d396eb1
AK		 1331{
1332 u32 val = 0;
2956640d 1333 int retries = 60;
3d396eb1 1334
96f2ebd2
DP		 1335 if (pegtune_val)
1336 return 0;
1337
1338 do {
1339 val = NXRD32(adapter, CRB_CMDPEG_STATE);
96f2ebd2
DP		 1340 switch (val) {
1341 case PHAN_INITIALIZE_COMPLETE:
1342 case PHAN_INITIALIZE_ACK:
1343 return 0;
1344 case PHAN_INITIALIZE_FAILED:
1345 goto out_err;
1346 default:
1347 break;
1348 }
96acb6eb 1349
96f2ebd2 1350 msleep(500);
2956640d 1351
96f2ebd2 1352 } while (--retries);
2956640d 1353
96f2ebd2 1354 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
96acb6eb 1355
96f2ebd2
DP		 1356out_err:
1357 dev_warn(&adapter->pdev->dev, "firmware init failed\n");
1358 return -EIO;
3d396eb1
AK		 1359}
1360
56a00787
DP		 1361static int
1362netxen_receive_peg_ready(struct netxen_adapter *adapter)
2956640d
DP		 1363{
1364 u32 val = 0;
1365 int retries = 2000;
1366
1367 do {
f98a9f69 1368 val = NXRD32(adapter, CRB_RCVPEG_STATE);
2956640d
DP		 1369
1370 if (val == PHAN_PEG_RCV_INITIALIZED)
1371 return 0;
1372
1373 msleep(10);
1374
1375 } while (--retries);
1376
1377 if (!retries) {
1378 printk(KERN_ERR "Receive Peg initialization not "
1379 "complete, state: 0x%x.\n", val);
1380 return -EIO;
1381 }
1382
1383 return 0;
1384}
1385
56a00787
DP		 1386int netxen_init_firmware(struct netxen_adapter *adapter)
1387{
1388 int err;
1389
1390 err = netxen_receive_peg_ready(adapter);
1391 if (err)
1392 return err;
1393
f98a9f69 1394 NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
f98a9f69
DP		 1395 NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
1396 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
56a00787 1397
f8e21f8f
AKS		 1398 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1399 NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
1400
56a00787
DP		 1401 return err;
1402}
1403
3bf26ce3
DP		 1404static void
1405netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
1406{
1407 u32 cable_OUI;
1408 u16 cable_len;
1409 u16 link_speed;
1410 u8 link_status, module, duplex, autoneg;
1411 struct net_device *netdev = adapter->netdev;
1412
1413 adapter->has_link_events = 1;
1414
1415 cable_OUI = msg->body[1] & 0xffffffff;
1416 cable_len = (msg->body[1] >> 32) & 0xffff;
1417 link_speed = (msg->body[1] >> 48) & 0xffff;
1418
1419 link_status = msg->body[2] & 0xff;
1420 duplex = (msg->body[2] >> 16) & 0xff;
1421 autoneg = (msg->body[2] >> 24) & 0xff;
1422
1423 module = (msg->body[2] >> 8) & 0xff;
1424 if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
1425 printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
1426 netdev->name, cable_OUI, cable_len);
1427 } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
1428 printk(KERN_INFO "%s: unsupported cable length %d\n",
1429 netdev->name, cable_len);
1430 }
1431
3bf26ce3
DP		 1432 /* update link parameters */
1433 if (duplex == LINKEVENT_FULL_DUPLEX)
1434 adapter->link_duplex = DUPLEX_FULL;
1435 else
1436 adapter->link_duplex = DUPLEX_HALF;
1437 adapter->module_type = module;
1438 adapter->link_autoneg = autoneg;
1439 adapter->link_speed = link_speed;
fa919833
FL		 1440
1441 netxen_advert_link_change(adapter, link_status);
3bf26ce3
DP		 1442}
1443
1444static void
1445netxen_handle_fw_message(int desc_cnt, int index,
1446 struct nx_host_sds_ring *sds_ring)
1447{
1448 nx_fw_msg_t msg;
1449 struct status_desc *desc;
1450 int i = 0, opcode;
1451
1452 while (desc_cnt > 0 && i < 8) {
1453 desc = &sds_ring->desc_head[index];
1454 msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
1455 msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
1456
1457 index = get_next_index(index, sds_ring->num_desc);
1458 desc_cnt--;
1459 }
1460
1461 opcode = netxen_get_nic_msg_opcode(msg.body[0]);
1462 switch (opcode) {
1463 case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
1464 netxen_handle_linkevent(sds_ring->adapter, &msg);
1465 break;
1466 default:
1467 break;
1468 }
1469}
1470
d8b100c5
DP		 1471static int
1472netxen_alloc_rx_skb(struct netxen_adapter *adapter,
1473 struct nx_host_rds_ring *rds_ring,
1474 struct netxen_rx_buffer *buffer)
1475{
1476 struct sk_buff *skb;
1477 dma_addr_t dma;
1478 struct pci_dev *pdev = adapter->pdev;
1479
dae2e9f4 1480 buffer->skb = netdev_alloc_skb(adapter->netdev, rds_ring->skb_size);
d8b100c5
DP		 1481 if (!buffer->skb)
1482 return 1;
1483
1484 skb = buffer->skb;
1485
1486 if (!adapter->ahw.cut_through)
1487 skb_reserve(skb, 2);
1488
1489 dma = pci_map_single(pdev, skb->data,
1490 rds_ring->dma_size, PCI_DMA_FROMDEVICE);
1491
1492 if (pci_dma_mapping_error(pdev, dma)) {
1493 dev_kfree_skb_any(skb);
1494 buffer->skb = NULL;
1495 return 1;
1496 }
1497
1498 buffer->skb = skb;
1499 buffer->dma = dma;
1500 buffer->state = NETXEN_BUFFER_BUSY;
1501
1502 return 0;
1503}
1504
d9e651bc
DP		 1505static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
1506 struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
1507{
1508 struct netxen_rx_buffer *buffer;
1509 struct sk_buff *skb;
1510
1511 buffer = &rds_ring->rx_buf_arr[index];
1512
1513 pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
1514 PCI_DMA_FROMDEVICE);
1515
1516 skb = buffer->skb;
1517 if (!skb)
1518 goto no_skb;
1519
066413da
MM		 1520 if (likely((adapter->netdev->features & NETIF_F_RXCSUM)
1521 && cksum == STATUS_CKSUM_OK)) {
d9e651bc
DP		 1522 adapter->stats.csummed++;
1523 skb->ip_summed = CHECKSUM_UNNECESSARY;
1524 } else
1525 skb->ip_summed = CHECKSUM_NONE;
1526
d9e651bc 1527 buffer->skb = NULL;
d9e651bc
DP		 1528no_skb:
1529 buffer->state = NETXEN_BUFFER_FREE;
d9e651bc
DP		 1530 return skb;
1531}
1532
d8b100c5 1533static struct netxen_rx_buffer *
9b3ef55c 1534netxen_process_rcv(struct netxen_adapter *adapter,
c1c00ab8
DP		 1535 struct nx_host_sds_ring *sds_ring,
1536 int ring, u64 sts_data0)
3d396eb1 1537{
3176ff3e 1538 struct net_device *netdev = adapter->netdev;
becf46a0 1539 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
3d396eb1
AK		 1540 struct netxen_rx_buffer *buffer;
1541 struct sk_buff *skb;
c1c00ab8
DP		 1542 struct nx_host_rds_ring *rds_ring;
1543 int index, length, cksum, pkt_offset;
3d396eb1 1544
c1c00ab8
DP		 1545 if (unlikely(ring >= adapter->max_rds_rings))
1546 return NULL;
1547
1548 rds_ring = &recv_ctx->rds_rings[ring];
1549
1550 index = netxen_get_sts_refhandle(sts_data0);
1551 if (unlikely(index >= rds_ring->num_desc))
d8b100c5 1552 return NULL;
438627c7 1553
48bfd1e0 1554 buffer = &rds_ring->rx_buf_arr[index];
3d396eb1 1555
c1c00ab8
DP		 1556 length = netxen_get_sts_totallength(sts_data0);
1557 cksum = netxen_get_sts_status(sts_data0);
1558 pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
1559
d9e651bc
DP		 1560 skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
1561 if (!skb)
d8b100c5 1562 return buffer;
200eef20 1563
9b3ef55c
DP		 1564 if (length > rds_ring->skb_size)
1565 skb_put(skb, rds_ring->skb_size);
1566 else
1567 skb_put(skb, length);
d9e651bc 1568
9b3ef55c
DP		 1569
1570 if (pkt_offset)
1571 skb_pull(skb, pkt_offset);
ed25ffa1 1572
3d396eb1
AK		 1573 skb->protocol = eth_type_trans(skb, netdev);
1574
a92e9e65 1575 napi_gro_receive(&sds_ring->napi, skb);
d9e651bc 1576
1bb482f8 1577 adapter->stats.rx_pkts++;
0ddc110c 1578 adapter->stats.rxbytes += length;
d8b100c5
DP		 1579
1580 return buffer;
3d396eb1
AK		 1581}
1582
c1c00ab8
DP		 1583#define TCP_HDR_SIZE 20
1584#define TCP_TS_OPTION_SIZE 12
1585#define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
1586
1587static struct netxen_rx_buffer *
1588netxen_process_lro(struct netxen_adapter *adapter,
1589 struct nx_host_sds_ring *sds_ring,
1590 int ring, u64 sts_data0, u64 sts_data1)
1591{
1592 struct net_device *netdev = adapter->netdev;
1593 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
1594 struct netxen_rx_buffer *buffer;
1595 struct sk_buff *skb;
1596 struct nx_host_rds_ring *rds_ring;
1597 struct iphdr *iph;
1598 struct tcphdr *th;
1599 bool push, timestamp;
1600 int l2_hdr_offset, l4_hdr_offset;
1601 int index;
1602 u16 lro_length, length, data_offset;
1603 u32 seq_number;
a7ffa289 1604 u8 vhdr_len = 0;
c1c00ab8
DP		 1605
1606 if (unlikely(ring > adapter->max_rds_rings))
1607 return NULL;
1608
1609 rds_ring = &recv_ctx->rds_rings[ring];
1610
1611 index = netxen_get_lro_sts_refhandle(sts_data0);
1612 if (unlikely(index > rds_ring->num_desc))
1613 return NULL;
1614
1615 buffer = &rds_ring->rx_buf_arr[index];
1616
1617 timestamp = netxen_get_lro_sts_timestamp(sts_data0);
1618 lro_length = netxen_get_lro_sts_length(sts_data0);
1619 l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
1620 l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
1621 push = netxen_get_lro_sts_push_flag(sts_data0);
1622 seq_number = netxen_get_lro_sts_seq_number(sts_data1);
1623
1624 skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
1625 if (!skb)
1626 return buffer;
1627
1628 if (timestamp)
1629 data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
1630 else
1631 data_offset = l4_hdr_offset + TCP_HDR_SIZE;
1632
1633 skb_put(skb, lro_length + data_offset);
1634
c1c00ab8
DP		 1635 skb_pull(skb, l2_hdr_offset);
1636 skb->protocol = eth_type_trans(skb, netdev);
1637
57569d0e
RB		 1638 if (skb->protocol == htons(ETH_P_8021Q))
1639 vhdr_len = VLAN_HLEN;
1640 iph = (struct iphdr *)(skb->data + vhdr_len);
1641 th = (struct tcphdr *)((skb->data + vhdr_len) + (iph->ihl << 2));
c1c00ab8
DP		 1642
1643 length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
1644 iph->tot_len = htons(length);
1645 iph->check = 0;
1646 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
1647 th->psh = push;
1648 th->seq = htonl(seq_number);
1649
1bb482f8
NK		 1650 length = skb->len;
1651
01da0c2b
RB		 1652 if (adapter->flags & NETXEN_FW_MSS_CAP)
1653 skb_shinfo(skb)->gso_size = netxen_get_lro_sts_mss(sts_data1);
1654
c1c00ab8
DP		 1655 netif_receive_skb(skb);
1656
1bb482f8
NK		 1657 adapter->stats.lro_pkts++;
1658 adapter->stats.rxbytes += length;
1659
c1c00ab8
DP		 1660 return buffer;
1661}
1662
d8b100c5
DP		 1663#define netxen_merge_rx_buffers(list, head) \
1664 do { list_splice_tail_init(list, head); } while (0);
1665
becf46a0 1666int
d8b100c5 1667netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
3d396eb1 1668{
d8b100c5
DP		 1669 struct netxen_adapter *adapter = sds_ring->adapter;
1670
1671 struct list_head *cur;
1672
0ddc110c 1673 struct status_desc *desc;
d8b100c5
DP		 1674 struct netxen_rx_buffer *rxbuf;
1675
1676 u32 consumer = sds_ring->consumer;
1677
9b3ef55c 1678 int count = 0;
c1c00ab8
DP		 1679 u64 sts_data0, sts_data1;
1680 int opcode, ring = 0, desc_cnt;
3d396eb1 1681
3d396eb1 1682 while (count < max) {
d8b100c5 1683 desc = &sds_ring->desc_head[consumer];
c1c00ab8 1684 sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
0ddc110c 1685
c1c00ab8 1686 if (!(sts_data0 & STATUS_OWNER_HOST))
3d396eb1 1687 break;
d9e651bc 1688
c1c00ab8 1689 desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
3bf26ce3 1690
c1c00ab8 1691 opcode = netxen_get_sts_opcode(sts_data0);
d9e651bc 1692
3bf26ce3
DP		 1693 switch (opcode) {
1694 case NETXEN_NIC_RXPKT_DESC:
1695 case NETXEN_OLD_RXPKT_DESC:
6598b169 1696 case NETXEN_NIC_SYN_OFFLOAD:
c1c00ab8
DP		 1697 ring = netxen_get_sts_type(sts_data0);
1698 rxbuf = netxen_process_rcv(adapter, sds_ring,
1699 ring, sts_data0);
1700 break;
1701 case NETXEN_NIC_LRO_DESC:
1702 ring = netxen_get_lro_sts_type(sts_data0);
1703 sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
1704 rxbuf = netxen_process_lro(adapter, sds_ring,
1705 ring, sts_data0, sts_data1);
3bf26ce3
DP		 1706 break;
1707 case NETXEN_NIC_RESPONSE_DESC:
1708 netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
1709 default:
1710 goto skip;
1711 }
1712
1713 WARN_ON(desc_cnt > 1);
1714
d8b100c5
DP		 1715 if (rxbuf)
1716 list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
1717
3bf26ce3
DP		 1718skip:
1719 for (; desc_cnt > 0; desc_cnt--) {
1720 desc = &sds_ring->desc_head[consumer];
1721 desc->status_desc_data[0] =
1722 cpu_to_le64(STATUS_OWNER_PHANTOM);
1723 consumer = get_next_index(consumer, sds_ring->num_desc);
1724 }
3d396eb1
AK		 1725 count++;
1726 }
0ddc110c 1727
d8b100c5
DP		 1728 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1729 struct nx_host_rds_ring *rds_ring =
1730 &adapter->recv_ctx.rds_rings[ring];
1731
1732 if (!list_empty(&sds_ring->free_list[ring])) {
1733 list_for_each(cur, &sds_ring->free_list[ring]) {
1734 rxbuf = list_entry(cur,
1735 struct netxen_rx_buffer, list);
1736 netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
1737 }
1738 spin_lock(&rds_ring->lock);
1739 netxen_merge_rx_buffers(&sds_ring->free_list[ring],
1740 &rds_ring->free_list);
1741 spin_unlock(&rds_ring->lock);
1742 }
1743
1744 netxen_post_rx_buffers_nodb(adapter, rds_ring);
1745 }
3d396eb1 1746
3d396eb1 1747 if (count) {
d8b100c5 1748 sds_ring->consumer = consumer;
195c5f98 1749 NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
3d396eb1
AK		 1750 }
1751
1752 return count;
1753}
1754
1755/* Process Command status ring */
05aaa02d 1756int netxen_process_cmd_ring(struct netxen_adapter *adapter)
3d396eb1 1757{
d877f1e3 1758 u32 sw_consumer, hw_consumer;
ba53e6b4 1759 int count = 0, i;
3d396eb1 1760 struct netxen_cmd_buffer *buffer;
ba53e6b4
DP		 1761 struct pci_dev *pdev = adapter->pdev;
1762 struct net_device *netdev = adapter->netdev;
3d396eb1 1763 struct netxen_skb_frag *frag;
ba53e6b4 1764 int done = 0;
4ea528a1 1765 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
3d396eb1 1766
d8b100c5
DP		 1767 if (!spin_trylock(&adapter->tx_clean_lock))
1768 return 1;
1769
d877f1e3 1770 sw_consumer = tx_ring->sw_consumer;
d877f1e3 1771 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
3d396eb1 1772
d877f1e3
DP		 1773 while (sw_consumer != hw_consumer) {
1774 buffer = &tx_ring->cmd_buf_arr[sw_consumer];
53a01e00 1775 if (buffer->skb) {
1776 frag = &buffer->frag_array[0];
3d396eb1
AK		 1777 pci_unmap_single(pdev, frag->dma, frag->length,
1778 PCI_DMA_TODEVICE);
96acb6eb 1779 frag->dma = 0ULL;
3d396eb1 1780 for (i = 1; i < buffer->frag_count; i++) {
3d396eb1
AK		 1781 frag++; /* Get the next frag */
1782 pci_unmap_page(pdev, frag->dma, frag->length,
1783 PCI_DMA_TODEVICE);
96acb6eb 1784 frag->dma = 0ULL;
3d396eb1
AK		 1785 }
1786
ba53e6b4 1787 adapter->stats.xmitfinished++;
53a01e00 1788 dev_kfree_skb_any(buffer->skb);
1789 buffer->skb = NULL;
3d396eb1
AK		 1790 }
1791
d877f1e3 1792 sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
ba53e6b4
DP		 1793 if (++count >= MAX_STATUS_HANDLE)
1794 break;
3d396eb1 1795 }
3d396eb1 1796
22527864 1797 if (count && netif_running(netdev)) {
cb2107be
DP		 1798 tx_ring->sw_consumer = sw_consumer;
1799
ba53e6b4 1800 smp_mb();
cb2107be 1801
7a9905e6
RB		 1802 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev))
1803 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
cb2107be 1804 netif_wake_queue(netdev);
7a9905e6 1805 adapter->tx_timeo_cnt = 0;
3d396eb1 1806 }
ed25ffa1
AK		 1807 /*
1808 * If everything is freed up to consumer then check if the ring is full
1809 * If the ring is full then check if more needs to be freed and
1810 * schedule the call back again.
1811 *
1812 * This happens when there are 2 CPUs. One could be freeing and the
1813 * other filling it. If the ring is full when we get out of here and
1814 * the card has already interrupted the host then the host can miss the
1815 * interrupt.
1816 *
1817 * There is still a possible race condition and the host could miss an
1818 * interrupt. The card has to take care of this.
1819 */
d877f1e3
DP		 1820 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1821 done = (sw_consumer == hw_consumer);
d8b100c5 1822 spin_unlock(&adapter->tx_clean_lock);
3d396eb1 1823
807540ba 1824 return done;
3d396eb1
AK		 1825}
1826
becf46a0 1827void
d8b100c5
DP		 1828netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1829 struct nx_host_rds_ring *rds_ring)
3d396eb1 1830{
3d396eb1
AK		 1831 struct rcv_desc *pdesc;
1832 struct netxen_rx_buffer *buffer;
d8b100c5 1833 int producer, count = 0;
ed25ffa1 1834 netxen_ctx_msg msg = 0;
d9e651bc 1835 struct list_head *head;
3d396eb1 1836
48bfd1e0 1837 producer = rds_ring->producer;
d9e651bc 1838
d8b100c5 1839 head = &rds_ring->free_list;
d9e651bc
DP		 1840 while (!list_empty(head)) {
1841
d8b100c5 1842 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1843
d8b100c5
DP		 1844 if (!buffer->skb) {
1845 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1846 break;
6f703406
DP		 1847 }
1848
1849 count++;
d9e651bc
DP		 1850 list_del(&buffer->list);
1851
ed25ffa1 1852 /* make a rcv descriptor */
6f703406 1853 pdesc = &rds_ring->desc_head[producer];
d8b100c5 1854 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
ed33ebe4 1855 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1856 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
6f703406 1857
438627c7 1858 producer = get_next_index(producer, rds_ring->num_desc);
ed25ffa1 1859 }
9b3ef55c 1860
ed25ffa1 1861 if (count) {
48bfd1e0 1862 rds_ring->producer = producer;
195c5f98 1863 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1864 (producer-1) & (rds_ring->num_desc-1));
48bfd1e0 1865
4f96b988 1866 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
ed25ffa1
AK		 1867 /*
1868 * Write a doorbell msg to tell phanmon of change in
1869 * receive ring producer
48bfd1e0 1870 * Only for firmware version < 4.0.0
ed25ffa1
AK		 1871 */
1872 netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
1873 netxen_set_msg_privid(msg);
1874 netxen_set_msg_count(msg,
438627c7
DP		 1875 ((producer - 1) &
1876 (rds_ring->num_desc - 1)));
3176ff3e 1877 netxen_set_msg_ctxid(msg, adapter->portnum);
ed25ffa1 1878 netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
f03b0ebd
DP		 1879 NXWRIO(adapter, DB_NORMALIZE(adapter,
1880 NETXEN_RCV_PRODUCER_OFFSET), msg);
48bfd1e0 1881 }
ed25ffa1
AK		 1882 }
1883}
1884
becf46a0 1885static void
d8b100c5
DP		 1886netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1887 struct nx_host_rds_ring *rds_ring)
ed25ffa1 1888{
ed25ffa1
AK		 1889 struct rcv_desc *pdesc;
1890 struct netxen_rx_buffer *buffer;
d8b100c5 1891 int producer, count = 0;
d9e651bc 1892 struct list_head *head;
ed25ffa1 1893
d8b100c5
DP		 1894 if (!spin_trylock(&rds_ring->lock))
1895 return;
1896
2227bae2
AKS		 1897 producer = rds_ring->producer;
1898
d9e651bc 1899 head = &rds_ring->free_list;
d9e651bc
DP		 1900 while (!list_empty(head)) {
1901
d8b100c5 1902 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1903
d8b100c5
DP		 1904 if (!buffer->skb) {
1905 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1906 break;
6f703406
DP		 1907 }
1908
1909 count++;
d9e651bc
DP		 1910 list_del(&buffer->list);
1911
3d396eb1 1912 /* make a rcv descriptor */
6f703406 1913 pdesc = &rds_ring->desc_head[producer];
ed33ebe4 1914 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1915 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
3d396eb1 1916 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
6f703406 1917
438627c7 1918 producer = get_next_index(producer, rds_ring->num_desc);
3d396eb1
AK		 1919 }
1920
3d396eb1 1921 if (count) {
48bfd1e0 1922 rds_ring->producer = producer;
195c5f98 1923 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1924 (producer - 1) & (rds_ring->num_desc - 1));
3d396eb1 1925 }
d8b100c5 1926 spin_unlock(&rds_ring->lock);
3d396eb1
AK		 1927}
1928
3d396eb1
AK		 1929void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1930{
3d396eb1 1931 memset(&adapter->stats, 0, sizeof(adapter->stats));
3d396eb1
AK		 1932}
1933
Linux 6.x block layer and io_uring tree(s)