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[linux-2.6-block.git] / drivers / net / ethernet / qlogic / netxen / netxen_nic_init.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
13af7a6e 3 * Copyright (C) 2009 - QLogic Corporation.
3d396eb1 4 * All rights reserved.
80922fbc 5 *
3d396eb1
AK		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
80922fbc 10 *
3d396eb1
AK		 11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
80922fbc 15 *
3d396eb1
AK		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
80922fbc 20 *
3d396eb1 21 * The full GNU General Public License is included in this distribution
4d21fef4 22 * in the file called "COPYING".
80922fbc 23 *
3d396eb1
AK		 24 */
25
26#include <linux/netdevice.h>
27#include <linux/delay.h>
5a0e3ad6 28#include <linux/slab.h>
57569d0e 29#include <linux/if_vlan.h>
3d396eb1
AK		 30#include "netxen_nic.h"
31#include "netxen_nic_hw.h"
3d396eb1
AK		 32
33struct crb_addr_pair {
e0e20a1a
LCMT		 34 u32 addr;
35 u32 data;
3d396eb1
AK		 36};
37
38#define NETXEN_MAX_CRB_XFORM 60
39static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
e0e20a1a 40#define NETXEN_ADDR_ERROR (0xffffffff)
3d396eb1
AK		 41
42#define crb_addr_transform(name) \
43 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
44 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
45
cb8011ad
AK		 46#define NETXEN_NIC_XDMA_RESET 0x8000ff
47
becf46a0 48static void
d8b100c5
DP		 49netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
50 struct nx_host_rds_ring *rds_ring);
f50330f9 51static int netxen_p3_has_mn(struct netxen_adapter *adapter);
993fb90c 52
3d396eb1
AK		 53static void crb_addr_transform_setup(void)
54{
55 crb_addr_transform(XDMA);
56 crb_addr_transform(TIMR);
57 crb_addr_transform(SRE);
58 crb_addr_transform(SQN3);
59 crb_addr_transform(SQN2);
60 crb_addr_transform(SQN1);
61 crb_addr_transform(SQN0);
62 crb_addr_transform(SQS3);
63 crb_addr_transform(SQS2);
64 crb_addr_transform(SQS1);
65 crb_addr_transform(SQS0);
66 crb_addr_transform(RPMX7);
67 crb_addr_transform(RPMX6);
68 crb_addr_transform(RPMX5);
69 crb_addr_transform(RPMX4);
70 crb_addr_transform(RPMX3);
71 crb_addr_transform(RPMX2);
72 crb_addr_transform(RPMX1);
73 crb_addr_transform(RPMX0);
74 crb_addr_transform(ROMUSB);
75 crb_addr_transform(SN);
76 crb_addr_transform(QMN);
77 crb_addr_transform(QMS);
78 crb_addr_transform(PGNI);
79 crb_addr_transform(PGND);
80 crb_addr_transform(PGN3);
81 crb_addr_transform(PGN2);
82 crb_addr_transform(PGN1);
83 crb_addr_transform(PGN0);
84 crb_addr_transform(PGSI);
85 crb_addr_transform(PGSD);
86 crb_addr_transform(PGS3);
87 crb_addr_transform(PGS2);
88 crb_addr_transform(PGS1);
89 crb_addr_transform(PGS0);
90 crb_addr_transform(PS);
91 crb_addr_transform(PH);
92 crb_addr_transform(NIU);
93 crb_addr_transform(I2Q);
94 crb_addr_transform(EG);
95 crb_addr_transform(MN);
96 crb_addr_transform(MS);
97 crb_addr_transform(CAS2);
98 crb_addr_transform(CAS1);
99 crb_addr_transform(CAS0);
100 crb_addr_transform(CAM);
101 crb_addr_transform(C2C1);
102 crb_addr_transform(C2C0);
1fcca1a5 103 crb_addr_transform(SMB);
e4c93c81
DP		 104 crb_addr_transform(OCM0);
105 crb_addr_transform(I2C0);
3d396eb1
AK		 106}
107
2956640d 108void netxen_release_rx_buffers(struct netxen_adapter *adapter)
3d396eb1 109{
2956640d 110 struct netxen_recv_context *recv_ctx;
48bfd1e0 111 struct nx_host_rds_ring *rds_ring;
2956640d 112 struct netxen_rx_buffer *rx_buf;
becf46a0
DP		 113 int i, ring;
114
115 recv_ctx = &adapter->recv_ctx;
116 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
117 rds_ring = &recv_ctx->rds_rings[ring];
438627c7 118 for (i = 0; i < rds_ring->num_desc; ++i) {
becf46a0
DP		 119 rx_buf = &(rds_ring->rx_buf_arr[i]);
120 if (rx_buf->state == NETXEN_BUFFER_FREE)
121 continue;
122 pci_unmap_single(adapter->pdev,
123 rx_buf->dma,
124 rds_ring->dma_size,
125 PCI_DMA_FROMDEVICE);
126 if (rx_buf->skb != NULL)
127 dev_kfree_skb_any(rx_buf->skb);
2956640d
DP		 128 }
129 }
130}
131
132void netxen_release_tx_buffers(struct netxen_adapter *adapter)
133{
134 struct netxen_cmd_buffer *cmd_buf;
135 struct netxen_skb_frag *buffrag;
136 int i, j;
4ea528a1 137 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
2956640d 138
d877f1e3
DP		 139 cmd_buf = tx_ring->cmd_buf_arr;
140 for (i = 0; i < tx_ring->num_desc; i++) {
2956640d
DP		 141 buffrag = cmd_buf->frag_array;
142 if (buffrag->dma) {
143 pci_unmap_single(adapter->pdev, buffrag->dma,
144 buffrag->length, PCI_DMA_TODEVICE);
145 buffrag->dma = 0ULL;
146 }
147 for (j = 0; j < cmd_buf->frag_count; j++) {
148 buffrag++;
149 if (buffrag->dma) {
150 pci_unmap_page(adapter->pdev, buffrag->dma,
151 buffrag->length,
152 PCI_DMA_TODEVICE);
153 buffrag->dma = 0ULL;
154 }
155 }
2956640d
DP		 156 if (cmd_buf->skb) {
157 dev_kfree_skb_any(cmd_buf->skb);
158 cmd_buf->skb = NULL;
159 }
160 cmd_buf++;
161 }
162}
163
164void netxen_free_sw_resources(struct netxen_adapter *adapter)
165{
166 struct netxen_recv_context *recv_ctx;
48bfd1e0 167 struct nx_host_rds_ring *rds_ring;
d877f1e3 168 struct nx_host_tx_ring *tx_ring;
becf46a0
DP		 169 int ring;
170
171 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 172
173 if (recv_ctx->rds_rings == NULL)
174 goto skip_rds;
175
becf46a0
DP		 176 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
177 rds_ring = &recv_ctx->rds_rings[ring];
f2333a01
F		 178 vfree(rds_ring->rx_buf_arr);
179 rds_ring->rx_buf_arr = NULL;
2956640d 180 }
4ea528a1
DP		 181 kfree(recv_ctx->rds_rings);
182
183skip_rds:
184 if (adapter->tx_ring == NULL)
185 return;
becf46a0 186
4ea528a1 187 tx_ring = adapter->tx_ring;
f2333a01 188 vfree(tx_ring->cmd_buf_arr);
011f4ea0
AKS		 189 kfree(tx_ring);
190 adapter->tx_ring = NULL;
2956640d
DP		 191}
192
193int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
194{
195 struct netxen_recv_context *recv_ctx;
48bfd1e0 196 struct nx_host_rds_ring *rds_ring;
d8b100c5 197 struct nx_host_sds_ring *sds_ring;
4ea528a1 198 struct nx_host_tx_ring *tx_ring;
2956640d 199 struct netxen_rx_buffer *rx_buf;
4ea528a1 200 int ring, i, size;
2956640d
DP		 201
202 struct netxen_cmd_buffer *cmd_buf_arr;
203 struct net_device *netdev = adapter->netdev;
d877f1e3 204 struct pci_dev *pdev = adapter->pdev;
2956640d 205
4ea528a1
DP		 206 size = sizeof(struct nx_host_tx_ring);
207 tx_ring = kzalloc(size, GFP_KERNEL);
208 if (tx_ring == NULL) {
209 dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
210 netdev->name);
211 return -ENOMEM;
212 }
213 adapter->tx_ring = tx_ring;
214
d877f1e3 215 tx_ring->num_desc = adapter->num_txd;
b2af9cb0 216 tx_ring->txq = netdev_get_tx_queue(netdev, 0);
4ea528a1 217
89bf67f1 218 cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
2956640d 219 if (cmd_buf_arr == NULL) {
d877f1e3 220 dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
2956640d 221 netdev->name);
bf445080 222 goto err_out;
2956640d 223 }
d877f1e3 224 tx_ring->cmd_buf_arr = cmd_buf_arr;
2956640d 225
becf46a0 226 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 227
228 size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
229 rds_ring = kzalloc(size, GFP_KERNEL);
230 if (rds_ring == NULL) {
231 dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
232 netdev->name);
bf445080 233 goto err_out;
4ea528a1
DP		 234 }
235 recv_ctx->rds_rings = rds_ring;
236
becf46a0
DP		 237 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
238 rds_ring = &recv_ctx->rds_rings[ring];
438627c7
DP		 239 switch (ring) {
240 case RCV_RING_NORMAL:
241 rds_ring->num_desc = adapter->num_rxd;
becf46a0
DP		 242 if (adapter->ahw.cut_through) {
243 rds_ring->dma_size =
244 NX_CT_DEFAULT_RX_BUF_LEN;
48bfd1e0 245 rds_ring->skb_size =
becf46a0
DP		 246 NX_CT_DEFAULT_RX_BUF_LEN;
247 } else {
9b08beba
DP		 248 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
249 rds_ring->dma_size =
250 NX_P3_RX_BUF_MAX_LEN;
251 else
252 rds_ring->dma_size =
253 NX_P2_RX_BUF_MAX_LEN;
becf46a0 254 rds_ring->skb_size =
9b08beba 255 rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 256 }
257 break;
2956640d 258
438627c7
DP		 259 case RCV_RING_JUMBO:
260 rds_ring->num_desc = adapter->num_jumbo_rxd;
becf46a0
DP		 261 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
262 rds_ring->dma_size =
263 NX_P3_RX_JUMBO_BUF_MAX_LEN;
264 else
265 rds_ring->dma_size =
266 NX_P2_RX_JUMBO_BUF_MAX_LEN;
bc75e5bf
DP		 267
268 if (adapter->capabilities & NX_CAP0_HW_LRO)
269 rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
270
becf46a0
DP		 271 rds_ring->skb_size =
272 rds_ring->dma_size + NET_IP_ALIGN;
273 break;
2956640d 274
becf46a0 275 case RCV_RING_LRO:
438627c7 276 rds_ring->num_desc = adapter->num_lro_rxd;
9b08beba
DP		 277 rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
278 rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 279 break;
280
281 }
0acdf68f 282 rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 283 if (rds_ring->rx_buf_arr == NULL) {
284 printk(KERN_ERR "%s: Failed to allocate "
285 "rx buffer ring %d\n",
286 netdev->name, ring);
287 /* free whatever was already allocated */
288 goto err_out;
289 }
becf46a0
DP		 290 INIT_LIST_HEAD(&rds_ring->free_list);
291 /*
292 * Now go through all of them, set reference handles
293 * and put them in the queues.
294 */
becf46a0 295 rx_buf = rds_ring->rx_buf_arr;
4ea528a1 296 for (i = 0; i < rds_ring->num_desc; i++) {
becf46a0
DP		 297 list_add_tail(&rx_buf->list,
298 &rds_ring->free_list);
299 rx_buf->ref_handle = i;
300 rx_buf->state = NETXEN_BUFFER_FREE;
301 rx_buf++;
3d396eb1 302 }
d8b100c5
DP		 303 spin_lock_init(&rds_ring->lock);
304 }
305
306 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
307 sds_ring = &recv_ctx->sds_rings[ring];
308 sds_ring->irq = adapter->msix_entries[ring].vector;
d8b100c5
DP		 309 sds_ring->adapter = adapter;
310 sds_ring->num_desc = adapter->num_rxd;
311
312 for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
313 INIT_LIST_HEAD(&sds_ring->free_list[i]);
3d396eb1 314 }
2956640d
DP		 315
316 return 0;
317
318err_out:
319 netxen_free_sw_resources(adapter);
320 return -ENOMEM;
3d396eb1
AK		 321}
322
3d396eb1
AK		 323/*
324 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
325 * address to external PCI CRB address.
326 */
993fb90c 327static u32 netxen_decode_crb_addr(u32 addr)
3d396eb1
AK		 328{
329 int i;
e0e20a1a 330 u32 base_addr, offset, pci_base;
3d396eb1
AK		 331
332 crb_addr_transform_setup();
333
334 pci_base = NETXEN_ADDR_ERROR;
335 base_addr = addr & 0xfff00000;
336 offset = addr & 0x000fffff;
337
338 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
339 if (crb_addr_xform[i] == base_addr) {
340 pci_base = i << 20;
341 break;
342 }
343 }
344 if (pci_base == NETXEN_ADDR_ERROR)
345 return pci_base;
346 else
807540ba 347 return pci_base + offset;
3d396eb1
AK		 348}
349
c9517e58 350#define NETXEN_MAX_ROM_WAIT_USEC 100
3d396eb1 351
993fb90c 352static int netxen_wait_rom_done(struct netxen_adapter *adapter)
3d396eb1
AK		 353{
354 long timeout = 0;
355 long done = 0;
356
27c915a4
DP		 357 cond_resched();
358
3d396eb1 359 while (done == 0) {
f98a9f69 360 done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
3d396eb1 361 done &= 2;
c9517e58
DP		 362 if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
363 dev_err(&adapter->pdev->dev,
364 "Timeout reached waiting for rom done");
3d396eb1
AK		 365 return -EIO;
366 }
c9517e58 367 udelay(1);
3d396eb1
AK		 368 }
369 return 0;
370}
371
993fb90c
AB		 372static int do_rom_fast_read(struct netxen_adapter *adapter,
373 int addr, int *valp)
3d396eb1 374{
f98a9f69
DP		 375 NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
376 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
377 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
378 NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
3d396eb1
AK		 379 if (netxen_wait_rom_done(adapter)) {
380 printk("Error waiting for rom done\n");
381 return -EIO;
382 }
383 /* reset abyte_cnt and dummy_byte_cnt */
f98a9f69 384 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
27c915a4 385 udelay(10);
f98a9f69 386 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
3d396eb1 387
f98a9f69 388 *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
3d396eb1
AK		 389 return 0;
390}
391
993fb90c
AB		 392static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
393 u8 *bytes, size_t size)
27d2ab54
AK		 394{
395 int addridx;
396 int ret = 0;
397
398 for (addridx = addr; addridx < (addr + size); addridx += 4) {
f305f789
AV		 399 int v;
400 ret = do_rom_fast_read(adapter, addridx, &v);
27d2ab54
AK		 401 if (ret != 0)
402 break;
f305f789 403 *(__le32 *)bytes = cpu_to_le32(v);
27d2ab54
AK		 404 bytes += 4;
405 }
406
407 return ret;
408}
409
410int
4790654c 411netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
27d2ab54
AK		 412 u8 *bytes, size_t size)
413{
414 int ret;
415
c9517e58 416 ret = netxen_rom_lock(adapter);
27d2ab54
AK		 417 if (ret < 0)
418 return ret;
419
420 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
421
422 netxen_rom_unlock(adapter);
423 return ret;
424}
425
3d396eb1
AK		 426int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
427{
428 int ret;
429
c9517e58 430 if (netxen_rom_lock(adapter) != 0)
3d396eb1
AK		 431 return -EIO;
432
433 ret = do_rom_fast_read(adapter, addr, valp);
cb8011ad
AK		 434 netxen_rom_unlock(adapter);
435 return ret;
436}
437
3d396eb1
AK		 438#define NETXEN_BOARDTYPE 0x4008
439#define NETXEN_BOARDNUM 0x400c
440#define NETXEN_CHIPNUM 0x4010
3d396eb1 441
0be367bd 442int netxen_pinit_from_rom(struct netxen_adapter *adapter)
3d396eb1 443{
dcd56fdb 444 int addr, val;
27c915a4 445 int i, n, init_delay = 0;
3d396eb1 446 struct crb_addr_pair *buf;
27c915a4 447 unsigned offset;
e0e20a1a 448 u32 off;
3d396eb1
AK		 449
450 /* resetall */
c9517e58 451 netxen_rom_lock(adapter);
f98a9f69 452 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
27c915a4 453 netxen_rom_unlock(adapter);
3d396eb1 454
2956640d
DP		 455 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
456 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
27c915a4 457 (n != 0xcafecafe) ||
2956640d
DP		 458 netxen_rom_fast_read(adapter, 4, &n) != 0) {
459 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
460 "n: %08x\n", netxen_nic_driver_name, n);
3d396eb1
AK		 461 return -EIO;
462 }
2956640d
DP		 463 offset = n & 0xffffU;
464 n = (n >> 16) & 0xffffU;
465 } else {
466 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
467 !(n & 0x80000000)) {
468 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
469 "n: %08x\n", netxen_nic_driver_name, n);
470 return -EIO;
3d396eb1 471 }
2956640d
DP		 472 offset = 1;
473 n &= ~0x80000000;
474 }
475
0be367bd 476 if (n >= 1024) {
2956640d
DP		 477 printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
478 " initialized.\n", __func__, n);
479 return -EIO;
480 }
3d396eb1 481
2956640d
DP		 482 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
483 if (buf == NULL) {
484 printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
485 netxen_nic_driver_name);
486 return -ENOMEM;
487 }
0be367bd 488
2956640d
DP		 489 for (i = 0; i < n; i++) {
490 if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
584dbe94
DM		 491 netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
492 kfree(buf);
2956640d 493 return -EIO;
584dbe94 494 }
2956640d
DP		 495
496 buf[i].addr = addr;
497 buf[i].data = val;
498
2956640d 499 }
0be367bd 500
2956640d
DP		 501 for (i = 0; i < n; i++) {
502
503 off = netxen_decode_crb_addr(buf[i].addr);
504 if (off == NETXEN_ADDR_ERROR) {
505 printk(KERN_ERR"CRB init value out of range %x\n",
1fcca1a5 506 buf[i].addr);
2956640d
DP		 507 continue;
508 }
509 off += NETXEN_PCI_CRBSPACE;
0be367bd
AKS		 510
511 if (off & 1)
512 continue;
513
2956640d
DP		 514 /* skipping cold reboot MAGIC */
515 if (off == NETXEN_CAM_RAM(0x1fc))
516 continue;
517
518 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
8bee0a91
DP		 519 if (off == (NETXEN_CRB_I2C0 + 0x1c))
520 continue;
2956640d
DP		 521 /* do not reset PCI */
522 if (off == (ROMUSB_GLB + 0xbc))
1fcca1a5 523 continue;
27c915a4
DP		 524 if (off == (ROMUSB_GLB + 0xa8))
525 continue;
526 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
527 continue;
528 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
529 continue;
530 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
531 continue;
e7473f12
AKS		 532 if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
533 continue;
0be367bd
AKS		 534 if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
535 !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
2956640d
DP		 536 buf[i].data = 0x1020;
537 /* skip the function enable register */
538 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
3d396eb1 539 continue;
2956640d
DP		 540 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
541 continue;
542 if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
543 continue;
544 }
3d396eb1 545
27c915a4 546 init_delay = 1;
2956640d
DP		 547 /* After writing this register, HW needs time for CRB */
548 /* to quiet down (else crb_window returns 0xffffffff) */
549 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
27c915a4 550 init_delay = 1000;
2956640d 551 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
3d396eb1 552 /* hold xdma in reset also */
cb8011ad 553 buf[i].data = NETXEN_NIC_XDMA_RESET;
27c915a4 554 buf[i].data = 0x8000ff;
3d396eb1 555 }
2956640d 556 }
3d396eb1 557
f98a9f69 558 NXWR32(adapter, off, buf[i].data);
3d396eb1 559
27c915a4 560 msleep(init_delay);
2956640d
DP		 561 }
562 kfree(buf);
3d396eb1 563
2956640d 564 /* disable_peg_cache_all */
3d396eb1 565
2956640d
DP		 566 /* unreset_net_cache */
567 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
f98a9f69
DP		 568 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
569 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
3d396eb1 570 }
2956640d
DP		 571
572 /* p2dn replyCount */
f98a9f69 573 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
2956640d 574 /* disable_peg_cache 0 */
f98a9f69 575 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
2956640d 576 /* disable_peg_cache 1 */
f98a9f69 577 NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
2956640d
DP		 578
579 /* peg_clr_all */
580
581 /* peg_clr 0 */
f98a9f69
DP		 582 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
583 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
2956640d 584 /* peg_clr 1 */
f98a9f69
DP		 585 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
586 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
2956640d 587 /* peg_clr 2 */
f98a9f69
DP		 588 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
589 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
2956640d 590 /* peg_clr 3 */
f98a9f69
DP		 591 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
592 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
3d396eb1
AK		 593 return 0;
594}
595
f50330f9
AKS		 596static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
597{
598 uint32_t i;
599 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
600 __le32 entries = cpu_to_le32(directory->num_entries);
601
602 for (i = 0; i < entries; i++) {
603
604 __le32 offs = cpu_to_le32(directory->findex) +
605 (i * cpu_to_le32(directory->entry_size));
606 __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
607
608 if (tab_type == section)
609 return (struct uni_table_desc *) &unirom[offs];
610 }
611
612 return NULL;
613}
614
10c0f2a8
RB		 615#define QLCNIC_FILEHEADER_SIZE (14 * 4)
616
f50330f9 617static int
10c0f2a8
RB		 618netxen_nic_validate_header(struct netxen_adapter *adapter)
619 {
f50330f9 620 const u8 *unirom = adapter->fw->data;
10c0f2a8
RB		 621 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
622 u32 fw_file_size = adapter->fw->size;
623 u32 tab_size;
f50330f9 624 __le32 entries;
10c0f2a8
RB		 625 __le32 entry_size;
626
627 if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
628 return -EINVAL;
629
630 entries = cpu_to_le32(directory->num_entries);
631 entry_size = cpu_to_le32(directory->entry_size);
632 tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
633
634 if (fw_file_size < tab_size)
635 return -EINVAL;
636
637 return 0;
638}
639
640static int
641netxen_nic_validate_bootld(struct netxen_adapter *adapter)
642{
643 struct uni_table_desc *tab_desc;
644 struct uni_data_desc *descr;
645 const u8 *unirom = adapter->fw->data;
646 __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
647 NX_UNI_BOOTLD_IDX_OFF));
648 u32 offs;
649 u32 tab_size;
650 u32 data_size;
651
652 tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
653
654 if (!tab_desc)
655 return -EINVAL;
656
657 tab_size = cpu_to_le32(tab_desc->findex) +
658 (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
659
660 if (adapter->fw->size < tab_size)
661 return -EINVAL;
662
663 offs = cpu_to_le32(tab_desc->findex) +
664 (cpu_to_le32(tab_desc->entry_size) * (idx));
665 descr = (struct uni_data_desc *)&unirom[offs];
666
667 data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
668
669 if (adapter->fw->size < data_size)
670 return -EINVAL;
671
672 return 0;
673}
674
675static int
676netxen_nic_validate_fw(struct netxen_adapter *adapter)
677{
678 struct uni_table_desc *tab_desc;
679 struct uni_data_desc *descr;
680 const u8 *unirom = adapter->fw->data;
681 __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
682 NX_UNI_FIRMWARE_IDX_OFF));
683 u32 offs;
684 u32 tab_size;
685 u32 data_size;
686
687 tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
688
689 if (!tab_desc)
690 return -EINVAL;
f50330f9 691
10c0f2a8
RB		 692 tab_size = cpu_to_le32(tab_desc->findex) +
693 (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
694
695 if (adapter->fw->size < tab_size)
696 return -EINVAL;
697
698 offs = cpu_to_le32(tab_desc->findex) +
699 (cpu_to_le32(tab_desc->entry_size) * (idx));
700 descr = (struct uni_data_desc *)&unirom[offs];
701 data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
702
703 if (adapter->fw->size < data_size)
704 return -EINVAL;
705
706 return 0;
707}
708
709
710static int
711netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
712{
713 struct uni_table_desc *ptab_descr;
714 const u8 *unirom = adapter->fw->data;
634d7df8
DP		 715 int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
716 1 : netxen_p3_has_mn(adapter);
10c0f2a8
RB		 717 __le32 entries;
718 __le32 entry_size;
719 u32 tab_size;
720 u32 i;
634d7df8 721
f50330f9
AKS		 722 ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
723 if (ptab_descr == NULL)
10c0f2a8 724 return -EINVAL;
f50330f9
AKS		 725
726 entries = cpu_to_le32(ptab_descr->num_entries);
10c0f2a8
RB		 727 entry_size = cpu_to_le32(ptab_descr->entry_size);
728 tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
729
730 if (adapter->fw->size < tab_size)
731 return -EINVAL;
f50330f9 732
634d7df8 733nomn:
f50330f9
AKS		 734 for (i = 0; i < entries; i++) {
735
736 __le32 flags, file_chiprev, offs;
737 u8 chiprev = adapter->ahw.revision_id;
f50330f9
AKS		 738 uint32_t flagbit;
739
740 offs = cpu_to_le32(ptab_descr->findex) +
741 (i * cpu_to_le32(ptab_descr->entry_size));
742 flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
743 file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
744 NX_UNI_CHIP_REV_OFF));
745
746 flagbit = mn_present ? 1 : 2;
747
748 if ((chiprev == file_chiprev) &&
749 ((1ULL << flagbit) & flags)) {
750 adapter->file_prd_off = offs;
751 return 0;
752 }
753 }
754
634d7df8
DP		 755 if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
756 mn_present = 0;
757 goto nomn;
758 }
759
10c0f2a8 760 return -EINVAL;
f50330f9
AKS		 761}
762
10c0f2a8
RB		 763static int
764netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
765{
766 if (netxen_nic_validate_header(adapter)) {
767 dev_err(&adapter->pdev->dev,
768 "unified image: header validation failed\n");
769 return -EINVAL;
770 }
771
772 if (netxen_nic_validate_product_offs(adapter)) {
773 dev_err(&adapter->pdev->dev,
774 "unified image: product validation failed\n");
775 return -EINVAL;
776 }
777
778 if (netxen_nic_validate_bootld(adapter)) {
779 dev_err(&adapter->pdev->dev,
780 "unified image: bootld validation failed\n");
781 return -EINVAL;
782 }
783
784 if (netxen_nic_validate_fw(adapter)) {
785 dev_err(&adapter->pdev->dev,
786 "unified image: firmware validation failed\n");
787 return -EINVAL;
788 }
789
790 return 0;
791}
f50330f9
AKS		 792
793static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
794 u32 section, u32 idx_offset)
795{
796 const u8 *unirom = adapter->fw->data;
797 int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
798 idx_offset));
799 struct uni_table_desc *tab_desc;
800 __le32 offs;
801
802 tab_desc = nx_get_table_desc(unirom, section);
803
804 if (tab_desc == NULL)
805 return NULL;
806
807 offs = cpu_to_le32(tab_desc->findex) +
808 (cpu_to_le32(tab_desc->entry_size) * idx);
809
810 return (struct uni_data_desc *)&unirom[offs];
811}
812
813static u8 *
814nx_get_bootld_offs(struct netxen_adapter *adapter)
815{
816 u32 offs = NETXEN_BOOTLD_START;
817
818 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
819 offs = cpu_to_le32((nx_get_data_desc(adapter,
820 NX_UNI_DIR_SECT_BOOTLD,
821 NX_UNI_BOOTLD_IDX_OFF))->findex);
822
823 return (u8 *)&adapter->fw->data[offs];
824}
825
826static u8 *
827nx_get_fw_offs(struct netxen_adapter *adapter)
828{
829 u32 offs = NETXEN_IMAGE_START;
830
831 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
832 offs = cpu_to_le32((nx_get_data_desc(adapter,
833 NX_UNI_DIR_SECT_FW,
834 NX_UNI_FIRMWARE_IDX_OFF))->findex);
835
836 return (u8 *)&adapter->fw->data[offs];
837}
838
839static __le32
840nx_get_fw_size(struct netxen_adapter *adapter)
841{
842 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
843 return cpu_to_le32((nx_get_data_desc(adapter,
844 NX_UNI_DIR_SECT_FW,
845 NX_UNI_FIRMWARE_IDX_OFF))->size);
846 else
847 return cpu_to_le32(
848 *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
849}
850
851static __le32
852nx_get_fw_version(struct netxen_adapter *adapter)
853{
854 struct uni_data_desc *fw_data_desc;
855 const struct firmware *fw = adapter->fw;
856 __le32 major, minor, sub;
857 const u8 *ver_str;
858 int i, ret = 0;
859
860 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
861
862 fw_data_desc = nx_get_data_desc(adapter,
863 NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
864 ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
865 cpu_to_le32(fw_data_desc->size) - 17;
866
867 for (i = 0; i < 12; i++) {
868 if (!strncmp(&ver_str[i], "REV=", 4)) {
869 ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
870 &major, &minor, &sub);
871 break;
872 }
873 }
874
875 if (ret != 3)
876 return 0;
877
878 return major + (minor << 8) + (sub << 16);
879
880 } else
881 return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
882}
883
884static __le32
885nx_get_bios_version(struct netxen_adapter *adapter)
886{
887 const struct firmware *fw = adapter->fw;
888 __le32 bios_ver, prd_off = adapter->file_prd_off;
889
890 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
891 bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
892 + NX_UNI_BIOS_VERSION_OFF));
bb2792e0 893 return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
f50330f9
AKS		 894 (bios_ver >> 24);
895 } else
896 return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
897
898}
899
67c38fc6
DP		 900int
901netxen_need_fw_reset(struct netxen_adapter *adapter)
902{
903 u32 count, old_count;
904 u32 val, version, major, minor, build;
905 int i, timeout;
906 u8 fw_type;
907
908 /* NX2031 firmware doesn't support heartbit */
909 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
910 return 1;
911
6a808c6c
AKS		 912 if (adapter->need_fw_reset)
913 return 1;
914
67c38fc6
DP		 915 /* last attempt had failed */
916 if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
917 return 1;
918
581e8ae4 919 old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
67c38fc6
DP		 920
921 for (i = 0; i < 10; i++) {
922
923 timeout = msleep_interruptible(200);
924 if (timeout) {
925 NXWR32(adapter, CRB_CMDPEG_STATE,
926 PHAN_INITIALIZE_FAILED);
927 return -EINTR;
928 }
929
930 count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
931 if (count != old_count)
932 break;
933 }
934
935 /* firmware is dead */
936 if (count == old_count)
937 return 1;
938
939 /* check if we have got newer or different file firmware */
940 if (adapter->fw) {
941
f50330f9 942 val = nx_get_fw_version(adapter);
67c38fc6 943
67c38fc6
DP		 944 version = NETXEN_DECODE_VERSION(val);
945
946 major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
947 minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
948 build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
949
950 if (version > NETXEN_VERSION_CODE(major, minor, build))
951 return 1;
952
f50330f9
AKS		 953 if (version == NETXEN_VERSION_CODE(major, minor, build) &&
954 adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
67c38fc6
DP		 955
956 val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
957 fw_type = (val & 0x4) ?
958 NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
959
960 if (adapter->fw_type != fw_type)
961 return 1;
962 }
963 }
964
965 return 0;
966}
967
e933d019
AKS		 968#define NETXEN_MIN_P3_FW_SUPP NETXEN_VERSION_CODE(4, 0, 505)
969
970int
971netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter)
972{
973 u32 flash_fw_ver, min_fw_ver;
974
975 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
976 return 0;
977
978 if (netxen_rom_fast_read(adapter,
979 NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
980 dev_err(&adapter->pdev->dev, "Unable to read flash fw"
981 "version\n");
982 return -EIO;
983 }
984
985 flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
986 min_fw_ver = NETXEN_MIN_P3_FW_SUPP;
987 if (flash_fw_ver >= min_fw_ver)
988 return 0;
989
990 dev_info(&adapter->pdev->dev, "Flash fw[%d.%d.%d] is < min fw supported"
991 "[4.0.505]. Please update firmware on flash\n",
992 _major(flash_fw_ver), _minor(flash_fw_ver),
993 _build(flash_fw_ver));
994 return -EINVAL;
995}
996
67c38fc6 997static char *fw_name[] = {
7e8e5d97
DP		 998 NX_P2_MN_ROMIMAGE_NAME,
999 NX_P3_CT_ROMIMAGE_NAME,
1000 NX_P3_MN_ROMIMAGE_NAME,
1001 NX_UNIFIED_ROMIMAGE_NAME,
1002 NX_FLASH_ROMIMAGE_NAME,
67c38fc6
DP		 1003};
1004
f7185c71
DP		 1005int
1006netxen_load_firmware(struct netxen_adapter *adapter)
1007{
1008 u64 *ptr64;
1009 u32 i, flashaddr, size;
1010 const struct firmware *fw = adapter->fw;
67c38fc6
DP		 1011 struct pci_dev *pdev = adapter->pdev;
1012
1013 dev_info(&pdev->dev, "loading firmware from %s\n",
1014 fw_name[adapter->fw_type]);
f7185c71
DP		 1015
1016 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1017 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
1018
1019 if (fw) {
1020 __le64 data;
1021
1022 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
1023
f50330f9 1024 ptr64 = (u64 *)nx_get_bootld_offs(adapter);
f7185c71
DP		 1025 flashaddr = NETXEN_BOOTLD_START;
1026
1027 for (i = 0; i < size; i++) {
1028 data = cpu_to_le64(ptr64[i]);
f50330f9
AKS		 1029
1030 if (adapter->pci_mem_write(adapter, flashaddr, data))
1f5e055d
AKS		 1031 return -EIO;
1032
f7185c71
DP		 1033 flashaddr += 8;
1034 }
1035
f50330f9 1036 size = (__force u32)nx_get_fw_size(adapter) / 8;
f7185c71 1037
f50330f9 1038 ptr64 = (u64 *)nx_get_fw_offs(adapter);
f7185c71
DP		 1039 flashaddr = NETXEN_IMAGE_START;
1040
1041 for (i = 0; i < size; i++) {
1042 data = cpu_to_le64(ptr64[i]);
1043
1044 if (adapter->pci_mem_write(adapter,
1f5e055d 1045 flashaddr, data))
f7185c71
DP		 1046 return -EIO;
1047
1048 flashaddr += 8;
1049 }
e270299a
AKS		 1050
1051 size = (__force u32)nx_get_fw_size(adapter) % 8;
1052 if (size) {
1053 data = cpu_to_le64(ptr64[i]);
1054
1055 if (adapter->pci_mem_write(adapter,
1056 flashaddr, data))
1057 return -EIO;
1058 }
1059
f7185c71 1060 } else {
f78c0850
AKS		 1061 u64 data;
1062 u32 hi, lo;
f7185c71 1063
f78c0850 1064 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
f7185c71
DP		 1065 flashaddr = NETXEN_BOOTLD_START;
1066
1067 for (i = 0; i < size; i++) {
1068 if (netxen_rom_fast_read(adapter,
1f5e055d 1069 flashaddr, (int *)&lo) != 0)
f78c0850
AKS		 1070 return -EIO;
1071 if (netxen_rom_fast_read(adapter,
1f5e055d 1072 flashaddr + 4, (int *)&hi) != 0)
f7185c71
DP		 1073 return -EIO;
1074
f78c0850
AKS		 1075 /* hi, lo are already in host endian byteorder */
1076 data = (((u64)hi << 32) | lo);
1077
f7185c71 1078 if (adapter->pci_mem_write(adapter,
1f5e055d 1079 flashaddr, data))
f7185c71
DP		 1080 return -EIO;
1081
f78c0850 1082 flashaddr += 8;
f7185c71
DP		 1083 }
1084 }
1085 msleep(1);
1086
0be367bd
AKS		 1087 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
1088 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
1089 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
1090 } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
f7185c71
DP		 1091 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1092 else {
1093 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1094 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
1095 }
1096
1097 return 0;
1098}
1099
1100static int
f50330f9 1101netxen_validate_firmware(struct netxen_adapter *adapter)
f7185c71
DP		 1102{
1103 __le32 val;
e933d019
AKS		 1104 __le32 flash_fw_ver;
1105 u32 file_fw_ver, min_ver, bios;
f7185c71
DP		 1106 struct pci_dev *pdev = adapter->pdev;
1107 const struct firmware *fw = adapter->fw;
f50330f9 1108 u8 fw_type = adapter->fw_type;
e933d019 1109 u32 crbinit_fix_fw;
f7185c71 1110
f50330f9 1111 if (fw_type == NX_UNIFIED_ROMIMAGE) {
10c0f2a8 1112 if (netxen_nic_validate_unified_romimage(adapter))
f50330f9 1113 return -EINVAL;
f50330f9
AKS		 1114 } else {
1115 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
1116 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
1117 return -EINVAL;
f7185c71 1118
10c0f2a8
RB		 1119 if (fw->size < NX_FW_MIN_SIZE)
1120 return -EINVAL;
f50330f9
AKS		 1121 }
1122
f50330f9 1123 val = nx_get_fw_version(adapter);
f7185c71
DP		 1124
1125 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
e933d019 1126 min_ver = NETXEN_MIN_P3_FW_SUPP;
f7185c71
DP		 1127 else
1128 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
1129
e933d019 1130 file_fw_ver = NETXEN_DECODE_VERSION(val);
f7185c71 1131
e933d019
AKS		 1132 if ((_major(file_fw_ver) > _NETXEN_NIC_LINUX_MAJOR) ||
1133 (file_fw_ver < min_ver)) {
f7185c71
DP		 1134 dev_err(&pdev->dev,
1135 "%s: firmware version %d.%d.%d unsupported\n",
e933d019
AKS		 1136 fw_name[fw_type], _major(file_fw_ver), _minor(file_fw_ver),
1137 _build(file_fw_ver));
f7185c71
DP		 1138 return -EINVAL;
1139 }
1140
f50330f9 1141 val = nx_get_bios_version(adapter);
f7185c71
DP		 1142 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
1143 if ((__force u32)val != bios) {
1144 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
f50330f9 1145 fw_name[fw_type]);
f7185c71
DP		 1146 return -EINVAL;
1147 }
1148
f7185c71 1149 if (netxen_rom_fast_read(adapter,
e933d019
AKS		 1150 NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
1151 dev_err(&pdev->dev, "Unable to read flash fw version\n");
f7185c71 1152 return -EIO;
e933d019
AKS		 1153 }
1154 flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
1155
1156 /* New fw from file is not allowed, if fw on flash is < 4.0.554 */
1157 crbinit_fix_fw = NETXEN_VERSION_CODE(4, 0, 554);
1158 if (file_fw_ver >= crbinit_fix_fw && flash_fw_ver < crbinit_fix_fw &&
1159 NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1160 dev_err(&pdev->dev, "Incompatibility detected between driver "
1161 "and firmware version on flash. This configuration "
1162 "is not recommended. Please update the firmware on "
1163 "flash immediately\n");
f7185c71 1164 return -EINVAL;
98e31bb0 1165 }
f7185c71 1166
e933d019
AKS		 1167 /* check if flashed firmware is newer only for no-mn and P2 case*/
1168 if (!netxen_p3_has_mn(adapter) ||
1169 NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1170 if (flash_fw_ver > file_fw_ver) {
1171 dev_info(&pdev->dev, "%s: firmware is older than flash\n",
1172 fw_name[fw_type]);
1173 return -EINVAL;
1174 }
1175 }
1176
f7185c71
DP		 1177 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
1178 return 0;
1179}
1180
f50330f9
AKS		 1181static void
1182nx_get_next_fwtype(struct netxen_adapter *adapter)
1183{
1184 u8 fw_type;
1185
1186 switch (adapter->fw_type) {
1187 case NX_UNKNOWN_ROMIMAGE:
1188 fw_type = NX_UNIFIED_ROMIMAGE;
1189 break;
1190
1191 case NX_UNIFIED_ROMIMAGE:
1192 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
1193 fw_type = NX_FLASH_ROMIMAGE;
1194 else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1195 fw_type = NX_P2_MN_ROMIMAGE;
1196 else if (netxen_p3_has_mn(adapter))
1197 fw_type = NX_P3_MN_ROMIMAGE;
1198 else
1199 fw_type = NX_P3_CT_ROMIMAGE;
1200 break;
1201
1202 case NX_P3_MN_ROMIMAGE:
1203 fw_type = NX_P3_CT_ROMIMAGE;
1204 break;
1205
1206 case NX_P2_MN_ROMIMAGE:
1207 case NX_P3_CT_ROMIMAGE:
1208 default:
1209 fw_type = NX_FLASH_ROMIMAGE;
1210 break;
1211 }
1212
1213 adapter->fw_type = fw_type;
1214}
1215
6598b169
DP		 1216static int
1217netxen_p3_has_mn(struct netxen_adapter *adapter)
f7185c71
DP		 1218{
1219 u32 capability, flashed_ver;
f7185c71
DP		 1220 capability = 0;
1221
634d7df8
DP		 1222 /* NX2031 always had MN */
1223 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1224 return 1;
1225
f7185c71
DP		 1226 netxen_rom_fast_read(adapter,
1227 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
98e31bb0
DP		 1228 flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
1229
f7185c71 1230 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
6598b169 1231
f7185c71 1232 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
6598b169
DP		 1233 if (capability & NX_PEG_TUNE_MN_PRESENT)
1234 return 1;
1235 }
1236 return 0;
1237}
1238
1239void netxen_request_firmware(struct netxen_adapter *adapter)
1240{
6598b169
DP		 1241 struct pci_dev *pdev = adapter->pdev;
1242 int rc = 0;
1243
f50330f9 1244 adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
f7185c71 1245
f50330f9
AKS		 1246next:
1247 nx_get_next_fwtype(adapter);
f7185c71 1248
f50330f9 1249 if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
f7185c71 1250 adapter->fw = NULL;
f50330f9
AKS		 1251 } else {
1252 rc = request_firmware(&adapter->fw,
1253 fw_name[adapter->fw_type], &pdev->dev);
1254 if (rc != 0)
1255 goto next;
1256
1257 rc = netxen_validate_firmware(adapter);
1258 if (rc != 0) {
1259 release_firmware(adapter->fw);
f7185c71 1260 msleep(1);
f50330f9 1261 goto next;
f7185c71 1262 }
f7185c71 1263 }
f7185c71
DP		 1264}
1265
1266
1267void
1268netxen_release_firmware(struct netxen_adapter *adapter)
1269{
1270 if (adapter->fw)
1271 release_firmware(adapter->fw);
db4cfd8a 1272 adapter->fw = NULL;
f7185c71
DP		 1273}
1274
83ac51fa 1275int netxen_init_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 1276{
83ac51fa
DP		 1277 u64 addr;
1278 u32 hi, lo;
ed25ffa1 1279
83ac51fa
DP		 1280 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1281 return 0;
1282
1283 adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
ed25ffa1
AK		 1284 NETXEN_HOST_DUMMY_DMA_SIZE,
1285 &adapter->dummy_dma.phys_addr);
1286 if (adapter->dummy_dma.addr == NULL) {
83ac51fa
DP		 1287 dev_err(&adapter->pdev->dev,
1288 "ERROR: Could not allocate dummy DMA memory\n");
ed25ffa1
AK		 1289 return -ENOMEM;
1290 }
1291
1292 addr = (uint64_t) adapter->dummy_dma.phys_addr;
1293 hi = (addr >> 32) & 0xffffffff;
1294 lo = addr & 0xffffffff;
1295
f98a9f69
DP		 1296 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
1297 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
ed25ffa1
AK		 1298
1299 return 0;
1300}
1301
83ac51fa
DP		 1302/*
1303 * NetXen DMA watchdog control:
1304 *
1305 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1306 * Bit 1 : disable_request => 1 req disable dma watchdog
1307 * Bit 2 : enable_request => 1 req enable dma watchdog
1308 * Bit 3-31 : unused
1309 */
1310void netxen_free_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 1311{
15eef1e1 1312 int i = 100;
83ac51fa
DP		 1313 u32 ctrl;
1314
1315 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1316 return;
15eef1e1
DP		 1317
1318 if (!adapter->dummy_dma.addr)
1319 return;
439b454e 1320
83ac51fa
DP		 1321 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1322 if ((ctrl & 0x1) != 0) {
1323 NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
1324
1325 while ((ctrl & 0x1) != 0) {
1326
439b454e 1327 msleep(50);
83ac51fa
DP		 1328
1329 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1330
1331 if (--i == 0)
439b454e 1332 break;
6403eab1 1333 }
15eef1e1 1334 }
439b454e 1335
15eef1e1
DP		 1336 if (i) {
1337 pci_free_consistent(adapter->pdev,
1338 NETXEN_HOST_DUMMY_DMA_SIZE,
1339 adapter->dummy_dma.addr,
1340 adapter->dummy_dma.phys_addr);
1341 adapter->dummy_dma.addr = NULL;
83ac51fa
DP		 1342 } else
1343 dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
ed25ffa1
AK		 1344}
1345
96acb6eb 1346int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
3d396eb1
AK		 1347{
1348 u32 val = 0;
2956640d 1349 int retries = 60;
3d396eb1 1350
96f2ebd2
DP		 1351 if (pegtune_val)
1352 return 0;
1353
1354 do {
1355 val = NXRD32(adapter, CRB_CMDPEG_STATE);
96acb6eb 1356
96f2ebd2
DP		 1357 switch (val) {
1358 case PHAN_INITIALIZE_COMPLETE:
1359 case PHAN_INITIALIZE_ACK:
1360 return 0;
1361 case PHAN_INITIALIZE_FAILED:
1362 goto out_err;
1363 default:
1364 break;
1365 }
96acb6eb 1366
96f2ebd2 1367 msleep(500);
2956640d 1368
96f2ebd2 1369 } while (--retries);
2956640d 1370
96f2ebd2 1371 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
96acb6eb 1372
96f2ebd2
DP		 1373out_err:
1374 dev_warn(&adapter->pdev->dev, "firmware init failed\n");
1375 return -EIO;
3d396eb1
AK		 1376}
1377
56a00787
DP		 1378static int
1379netxen_receive_peg_ready(struct netxen_adapter *adapter)
2956640d
DP		 1380{
1381 u32 val = 0;
1382 int retries = 2000;
1383
1384 do {
f98a9f69 1385 val = NXRD32(adapter, CRB_RCVPEG_STATE);
2956640d
DP		 1386
1387 if (val == PHAN_PEG_RCV_INITIALIZED)
1388 return 0;
1389
1390 msleep(10);
1391
1392 } while (--retries);
1393
1394 if (!retries) {
1395 printk(KERN_ERR "Receive Peg initialization not "
1396 "complete, state: 0x%x.\n", val);
1397 return -EIO;
1398 }
1399
1400 return 0;
1401}
1402
56a00787
DP		 1403int netxen_init_firmware(struct netxen_adapter *adapter)
1404{
1405 int err;
1406
1407 err = netxen_receive_peg_ready(adapter);
1408 if (err)
1409 return err;
1410
f98a9f69 1411 NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
f98a9f69
DP		 1412 NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
1413 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
56a00787 1414
f8e21f8f
AKS		 1415 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1416 NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
1417
56a00787
DP		 1418 return err;
1419}
1420
3bf26ce3
DP		 1421static void
1422netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
1423{
1424 u32 cable_OUI;
1425 u16 cable_len;
1426 u16 link_speed;
1427 u8 link_status, module, duplex, autoneg;
1428 struct net_device *netdev = adapter->netdev;
1429
1430 adapter->has_link_events = 1;
1431
1432 cable_OUI = msg->body[1] & 0xffffffff;
1433 cable_len = (msg->body[1] >> 32) & 0xffff;
1434 link_speed = (msg->body[1] >> 48) & 0xffff;
1435
1436 link_status = msg->body[2] & 0xff;
1437 duplex = (msg->body[2] >> 16) & 0xff;
1438 autoneg = (msg->body[2] >> 24) & 0xff;
1439
1440 module = (msg->body[2] >> 8) & 0xff;
1441 if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
1442 printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
1443 netdev->name, cable_OUI, cable_len);
1444 } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
1445 printk(KERN_INFO "%s: unsupported cable length %d\n",
1446 netdev->name, cable_len);
1447 }
1448
1449 netxen_advert_link_change(adapter, link_status);
1450
1451 /* update link parameters */
1452 if (duplex == LINKEVENT_FULL_DUPLEX)
1453 adapter->link_duplex = DUPLEX_FULL;
1454 else
1455 adapter->link_duplex = DUPLEX_HALF;
1456 adapter->module_type = module;
1457 adapter->link_autoneg = autoneg;
1458 adapter->link_speed = link_speed;
1459}
1460
1461static void
1462netxen_handle_fw_message(int desc_cnt, int index,
1463 struct nx_host_sds_ring *sds_ring)
1464{
1465 nx_fw_msg_t msg;
1466 struct status_desc *desc;
1467 int i = 0, opcode;
1468
1469 while (desc_cnt > 0 && i < 8) {
1470 desc = &sds_ring->desc_head[index];
1471 msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
1472 msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
1473
1474 index = get_next_index(index, sds_ring->num_desc);
1475 desc_cnt--;
1476 }
1477
1478 opcode = netxen_get_nic_msg_opcode(msg.body[0]);
1479 switch (opcode) {
1480 case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
1481 netxen_handle_linkevent(sds_ring->adapter, &msg);
1482 break;
1483 default:
1484 break;
1485 }
1486}
1487
d8b100c5
DP		 1488static int
1489netxen_alloc_rx_skb(struct netxen_adapter *adapter,
1490 struct nx_host_rds_ring *rds_ring,
1491 struct netxen_rx_buffer *buffer)
1492{
1493 struct sk_buff *skb;
1494 dma_addr_t dma;
1495 struct pci_dev *pdev = adapter->pdev;
1496
1497 buffer->skb = dev_alloc_skb(rds_ring->skb_size);
1498 if (!buffer->skb)
1499 return 1;
1500
1501 skb = buffer->skb;
1502
1503 if (!adapter->ahw.cut_through)
1504 skb_reserve(skb, 2);
1505
1506 dma = pci_map_single(pdev, skb->data,
1507 rds_ring->dma_size, PCI_DMA_FROMDEVICE);
1508
1509 if (pci_dma_mapping_error(pdev, dma)) {
1510 dev_kfree_skb_any(skb);
1511 buffer->skb = NULL;
1512 return 1;
1513 }
1514
1515 buffer->skb = skb;
1516 buffer->dma = dma;
1517 buffer->state = NETXEN_BUFFER_BUSY;
1518
1519 return 0;
1520}
1521
d9e651bc
DP		 1522static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
1523 struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
1524{
1525 struct netxen_rx_buffer *buffer;
1526 struct sk_buff *skb;
1527
1528 buffer = &rds_ring->rx_buf_arr[index];
1529
1530 pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
1531 PCI_DMA_FROMDEVICE);
1532
1533 skb = buffer->skb;
1534 if (!skb)
1535 goto no_skb;
1536
066413da
MM		 1537 if (likely((adapter->netdev->features & NETIF_F_RXCSUM)
1538 && cksum == STATUS_CKSUM_OK)) {
d9e651bc
DP		 1539 adapter->stats.csummed++;
1540 skb->ip_summed = CHECKSUM_UNNECESSARY;
1541 } else
1542 skb->ip_summed = CHECKSUM_NONE;
1543
1544 skb->dev = adapter->netdev;
1545
1546 buffer->skb = NULL;
d9e651bc
DP		 1547no_skb:
1548 buffer->state = NETXEN_BUFFER_FREE;
d9e651bc
DP		 1549 return skb;
1550}
1551
d8b100c5 1552static struct netxen_rx_buffer *
9b3ef55c 1553netxen_process_rcv(struct netxen_adapter *adapter,
c1c00ab8
DP		 1554 struct nx_host_sds_ring *sds_ring,
1555 int ring, u64 sts_data0)
3d396eb1 1556{
3176ff3e 1557 struct net_device *netdev = adapter->netdev;
becf46a0 1558 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
3d396eb1
AK		 1559 struct netxen_rx_buffer *buffer;
1560 struct sk_buff *skb;
c1c00ab8
DP		 1561 struct nx_host_rds_ring *rds_ring;
1562 int index, length, cksum, pkt_offset;
3d396eb1 1563
c1c00ab8
DP		 1564 if (unlikely(ring >= adapter->max_rds_rings))
1565 return NULL;
1566
1567 rds_ring = &recv_ctx->rds_rings[ring];
1568
1569 index = netxen_get_sts_refhandle(sts_data0);
1570 if (unlikely(index >= rds_ring->num_desc))
d8b100c5 1571 return NULL;
438627c7 1572
48bfd1e0 1573 buffer = &rds_ring->rx_buf_arr[index];
3d396eb1 1574
c1c00ab8
DP		 1575 length = netxen_get_sts_totallength(sts_data0);
1576 cksum = netxen_get_sts_status(sts_data0);
1577 pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
1578
d9e651bc
DP		 1579 skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
1580 if (!skb)
d8b100c5 1581 return buffer;
200eef20 1582
9b3ef55c
DP		 1583 if (length > rds_ring->skb_size)
1584 skb_put(skb, rds_ring->skb_size);
1585 else
1586 skb_put(skb, length);
d9e651bc 1587
9b3ef55c
DP		 1588
1589 if (pkt_offset)
1590 skb_pull(skb, pkt_offset);
ed25ffa1 1591
3d396eb1
AK		 1592 skb->protocol = eth_type_trans(skb, netdev);
1593
a92e9e65 1594 napi_gro_receive(&sds_ring->napi, skb);
d9e651bc 1595
1bb482f8 1596 adapter->stats.rx_pkts++;
0ddc110c 1597 adapter->stats.rxbytes += length;
d8b100c5
DP		 1598
1599 return buffer;
3d396eb1
AK		 1600}
1601
c1c00ab8
DP		 1602#define TCP_HDR_SIZE 20
1603#define TCP_TS_OPTION_SIZE 12
1604#define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
1605
1606static struct netxen_rx_buffer *
1607netxen_process_lro(struct netxen_adapter *adapter,
1608 struct nx_host_sds_ring *sds_ring,
1609 int ring, u64 sts_data0, u64 sts_data1)
1610{
1611 struct net_device *netdev = adapter->netdev;
1612 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
1613 struct netxen_rx_buffer *buffer;
1614 struct sk_buff *skb;
1615 struct nx_host_rds_ring *rds_ring;
1616 struct iphdr *iph;
1617 struct tcphdr *th;
1618 bool push, timestamp;
1619 int l2_hdr_offset, l4_hdr_offset;
1620 int index;
1621 u16 lro_length, length, data_offset;
1622 u32 seq_number;
a7ffa289 1623 u8 vhdr_len = 0;
c1c00ab8
DP		 1624
1625 if (unlikely(ring > adapter->max_rds_rings))
1626 return NULL;
1627
1628 rds_ring = &recv_ctx->rds_rings[ring];
1629
1630 index = netxen_get_lro_sts_refhandle(sts_data0);
1631 if (unlikely(index > rds_ring->num_desc))
1632 return NULL;
1633
1634 buffer = &rds_ring->rx_buf_arr[index];
1635
1636 timestamp = netxen_get_lro_sts_timestamp(sts_data0);
1637 lro_length = netxen_get_lro_sts_length(sts_data0);
1638 l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
1639 l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
1640 push = netxen_get_lro_sts_push_flag(sts_data0);
1641 seq_number = netxen_get_lro_sts_seq_number(sts_data1);
1642
1643 skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
1644 if (!skb)
1645 return buffer;
1646
1647 if (timestamp)
1648 data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
1649 else
1650 data_offset = l4_hdr_offset + TCP_HDR_SIZE;
1651
1652 skb_put(skb, lro_length + data_offset);
1653
c1c00ab8
DP		 1654 skb_pull(skb, l2_hdr_offset);
1655 skb->protocol = eth_type_trans(skb, netdev);
1656
57569d0e
RB		 1657 if (skb->protocol == htons(ETH_P_8021Q))
1658 vhdr_len = VLAN_HLEN;
1659 iph = (struct iphdr *)(skb->data + vhdr_len);
1660 th = (struct tcphdr *)((skb->data + vhdr_len) + (iph->ihl << 2));
c1c00ab8
DP		 1661
1662 length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
1663 iph->tot_len = htons(length);
1664 iph->check = 0;
1665 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
1666 th->psh = push;
1667 th->seq = htonl(seq_number);
1668
1bb482f8
NK		 1669 length = skb->len;
1670
c1c00ab8
DP		 1671 netif_receive_skb(skb);
1672
1bb482f8
NK		 1673 adapter->stats.lro_pkts++;
1674 adapter->stats.rxbytes += length;
1675
c1c00ab8
DP		 1676 return buffer;
1677}
1678
d8b100c5
DP		 1679#define netxen_merge_rx_buffers(list, head) \
1680 do { list_splice_tail_init(list, head); } while (0);
1681
becf46a0 1682int
d8b100c5 1683netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
3d396eb1 1684{
d8b100c5
DP		 1685 struct netxen_adapter *adapter = sds_ring->adapter;
1686
1687 struct list_head *cur;
1688
0ddc110c 1689 struct status_desc *desc;
d8b100c5
DP		 1690 struct netxen_rx_buffer *rxbuf;
1691
1692 u32 consumer = sds_ring->consumer;
1693
9b3ef55c 1694 int count = 0;
c1c00ab8
DP		 1695 u64 sts_data0, sts_data1;
1696 int opcode, ring = 0, desc_cnt;
3d396eb1 1697
3d396eb1 1698 while (count < max) {
d8b100c5 1699 desc = &sds_ring->desc_head[consumer];
c1c00ab8 1700 sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
0ddc110c 1701
c1c00ab8 1702 if (!(sts_data0 & STATUS_OWNER_HOST))
3d396eb1 1703 break;
d9e651bc 1704
c1c00ab8 1705 desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
3bf26ce3 1706
c1c00ab8 1707 opcode = netxen_get_sts_opcode(sts_data0);
d9e651bc 1708
3bf26ce3
DP		 1709 switch (opcode) {
1710 case NETXEN_NIC_RXPKT_DESC:
1711 case NETXEN_OLD_RXPKT_DESC:
6598b169 1712 case NETXEN_NIC_SYN_OFFLOAD:
c1c00ab8
DP		 1713 ring = netxen_get_sts_type(sts_data0);
1714 rxbuf = netxen_process_rcv(adapter, sds_ring,
1715 ring, sts_data0);
1716 break;
1717 case NETXEN_NIC_LRO_DESC:
1718 ring = netxen_get_lro_sts_type(sts_data0);
1719 sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
1720 rxbuf = netxen_process_lro(adapter, sds_ring,
1721 ring, sts_data0, sts_data1);
3bf26ce3
DP		 1722 break;
1723 case NETXEN_NIC_RESPONSE_DESC:
1724 netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
1725 default:
1726 goto skip;
1727 }
1728
1729 WARN_ON(desc_cnt > 1);
1730
d8b100c5
DP		 1731 if (rxbuf)
1732 list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
1733
3bf26ce3
DP		 1734skip:
1735 for (; desc_cnt > 0; desc_cnt--) {
1736 desc = &sds_ring->desc_head[consumer];
1737 desc->status_desc_data[0] =
1738 cpu_to_le64(STATUS_OWNER_PHANTOM);
1739 consumer = get_next_index(consumer, sds_ring->num_desc);
1740 }
3d396eb1
AK		 1741 count++;
1742 }
0ddc110c 1743
d8b100c5
DP		 1744 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1745 struct nx_host_rds_ring *rds_ring =
1746 &adapter->recv_ctx.rds_rings[ring];
1747
1748 if (!list_empty(&sds_ring->free_list[ring])) {
1749 list_for_each(cur, &sds_ring->free_list[ring]) {
1750 rxbuf = list_entry(cur,
1751 struct netxen_rx_buffer, list);
1752 netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
1753 }
1754 spin_lock(&rds_ring->lock);
1755 netxen_merge_rx_buffers(&sds_ring->free_list[ring],
1756 &rds_ring->free_list);
1757 spin_unlock(&rds_ring->lock);
1758 }
1759
1760 netxen_post_rx_buffers_nodb(adapter, rds_ring);
1761 }
3d396eb1 1762
3d396eb1 1763 if (count) {
d8b100c5 1764 sds_ring->consumer = consumer;
195c5f98 1765 NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
3d396eb1
AK		 1766 }
1767
1768 return count;
1769}
1770
1771/* Process Command status ring */
05aaa02d 1772int netxen_process_cmd_ring(struct netxen_adapter *adapter)
3d396eb1 1773{
d877f1e3 1774 u32 sw_consumer, hw_consumer;
ba53e6b4 1775 int count = 0, i;
3d396eb1 1776 struct netxen_cmd_buffer *buffer;
ba53e6b4
DP		 1777 struct pci_dev *pdev = adapter->pdev;
1778 struct net_device *netdev = adapter->netdev;
3d396eb1 1779 struct netxen_skb_frag *frag;
ba53e6b4 1780 int done = 0;
4ea528a1 1781 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
3d396eb1 1782
d8b100c5
DP		 1783 if (!spin_trylock(&adapter->tx_clean_lock))
1784 return 1;
1785
d877f1e3 1786 sw_consumer = tx_ring->sw_consumer;
d877f1e3 1787 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
3d396eb1 1788
d877f1e3
DP		 1789 while (sw_consumer != hw_consumer) {
1790 buffer = &tx_ring->cmd_buf_arr[sw_consumer];
53a01e00 1791 if (buffer->skb) {
1792 frag = &buffer->frag_array[0];
3d396eb1
AK		 1793 pci_unmap_single(pdev, frag->dma, frag->length,
1794 PCI_DMA_TODEVICE);
96acb6eb 1795 frag->dma = 0ULL;
3d396eb1 1796 for (i = 1; i < buffer->frag_count; i++) {
3d396eb1
AK		 1797 frag++; /* Get the next frag */
1798 pci_unmap_page(pdev, frag->dma, frag->length,
1799 PCI_DMA_TODEVICE);
96acb6eb 1800 frag->dma = 0ULL;
3d396eb1
AK		 1801 }
1802
ba53e6b4 1803 adapter->stats.xmitfinished++;
53a01e00 1804 dev_kfree_skb_any(buffer->skb);
1805 buffer->skb = NULL;
3d396eb1
AK		 1806 }
1807
d877f1e3 1808 sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
ba53e6b4
DP		 1809 if (++count >= MAX_STATUS_HANDLE)
1810 break;
3d396eb1 1811 }
3d396eb1 1812
22527864 1813 if (count && netif_running(netdev)) {
cb2107be
DP		 1814 tx_ring->sw_consumer = sw_consumer;
1815
ba53e6b4 1816 smp_mb();
cb2107be 1817
7a9905e6
RB		 1818 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev))
1819 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
cb2107be 1820 netif_wake_queue(netdev);
7a9905e6 1821 adapter->tx_timeo_cnt = 0;
3d396eb1 1822 }
ed25ffa1
AK		 1823 /*
1824 * If everything is freed up to consumer then check if the ring is full
1825 * If the ring is full then check if more needs to be freed and
1826 * schedule the call back again.
1827 *
1828 * This happens when there are 2 CPUs. One could be freeing and the
1829 * other filling it. If the ring is full when we get out of here and
1830 * the card has already interrupted the host then the host can miss the
1831 * interrupt.
1832 *
1833 * There is still a possible race condition and the host could miss an
1834 * interrupt. The card has to take care of this.
1835 */
d877f1e3
DP		 1836 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1837 done = (sw_consumer == hw_consumer);
d8b100c5 1838 spin_unlock(&adapter->tx_clean_lock);
3d396eb1 1839
807540ba 1840 return done;
3d396eb1
AK		 1841}
1842
becf46a0 1843void
d8b100c5
DP		 1844netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1845 struct nx_host_rds_ring *rds_ring)
3d396eb1 1846{
3d396eb1
AK		 1847 struct rcv_desc *pdesc;
1848 struct netxen_rx_buffer *buffer;
d8b100c5 1849 int producer, count = 0;
ed25ffa1 1850 netxen_ctx_msg msg = 0;
d9e651bc 1851 struct list_head *head;
3d396eb1 1852
48bfd1e0 1853 producer = rds_ring->producer;
d9e651bc 1854
d8b100c5 1855 head = &rds_ring->free_list;
d9e651bc
DP		 1856 while (!list_empty(head)) {
1857
d8b100c5 1858 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1859
d8b100c5
DP		 1860 if (!buffer->skb) {
1861 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1862 break;
6f703406
DP		 1863 }
1864
1865 count++;
d9e651bc
DP		 1866 list_del(&buffer->list);
1867
ed25ffa1 1868 /* make a rcv descriptor */
6f703406 1869 pdesc = &rds_ring->desc_head[producer];
d8b100c5 1870 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
ed33ebe4 1871 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1872 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
6f703406 1873
438627c7 1874 producer = get_next_index(producer, rds_ring->num_desc);
ed25ffa1 1875 }
9b3ef55c 1876
ed25ffa1 1877 if (count) {
48bfd1e0 1878 rds_ring->producer = producer;
195c5f98 1879 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1880 (producer-1) & (rds_ring->num_desc-1));
48bfd1e0 1881
4f96b988 1882 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
ed25ffa1
AK		 1883 /*
1884 * Write a doorbell msg to tell phanmon of change in
1885 * receive ring producer
48bfd1e0 1886 * Only for firmware version < 4.0.0
ed25ffa1
AK		 1887 */
1888 netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
1889 netxen_set_msg_privid(msg);
1890 netxen_set_msg_count(msg,
438627c7
DP		 1891 ((producer - 1) &
1892 (rds_ring->num_desc - 1)));
3176ff3e 1893 netxen_set_msg_ctxid(msg, adapter->portnum);
ed25ffa1 1894 netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
f03b0ebd
DP		 1895 NXWRIO(adapter, DB_NORMALIZE(adapter,
1896 NETXEN_RCV_PRODUCER_OFFSET), msg);
48bfd1e0 1897 }
ed25ffa1
AK		 1898 }
1899}
1900
becf46a0 1901static void
d8b100c5
DP		 1902netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1903 struct nx_host_rds_ring *rds_ring)
ed25ffa1 1904{
ed25ffa1
AK		 1905 struct rcv_desc *pdesc;
1906 struct netxen_rx_buffer *buffer;
d8b100c5 1907 int producer, count = 0;
d9e651bc 1908 struct list_head *head;
ed25ffa1 1909
d8b100c5
DP		 1910 if (!spin_trylock(&rds_ring->lock))
1911 return;
1912
2227bae2
AKS		 1913 producer = rds_ring->producer;
1914
d9e651bc 1915 head = &rds_ring->free_list;
d9e651bc
DP		 1916 while (!list_empty(head)) {
1917
d8b100c5 1918 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1919
d8b100c5
DP		 1920 if (!buffer->skb) {
1921 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1922 break;
6f703406
DP		 1923 }
1924
1925 count++;
d9e651bc
DP		 1926 list_del(&buffer->list);
1927
3d396eb1 1928 /* make a rcv descriptor */
6f703406 1929 pdesc = &rds_ring->desc_head[producer];
ed33ebe4 1930 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1931 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
3d396eb1 1932 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
6f703406 1933
438627c7 1934 producer = get_next_index(producer, rds_ring->num_desc);
3d396eb1
AK		 1935 }
1936
3d396eb1 1937 if (count) {
48bfd1e0 1938 rds_ring->producer = producer;
195c5f98 1939 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1940 (producer - 1) & (rds_ring->num_desc - 1));
3d396eb1 1941 }
d8b100c5 1942 spin_unlock(&rds_ring->lock);
3d396eb1
AK		 1943}
1944
3d396eb1
AK		 1945void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1946{
3d396eb1 1947 memset(&adapter->stats, 0, sizeof(adapter->stats));
3d396eb1
AK		 1948}
1949
Linux 6.x block layer and io_uring tree(s)