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Merge tag 'modules-next-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / net / ethernet / myricom / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
3bea1237 4 * Copyright (C) 2005 - 2011 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
78ca90ea
JP		 41#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42
0da34b6d
BG		 43#include <linux/tcp.h>
44#include <linux/netdevice.h>
45#include <linux/skbuff.h>
46#include <linux/string.h>
47#include <linux/module.h>
48#include <linux/pci.h>
b10c0668 49#include <linux/dma-mapping.h>
0da34b6d
BG		 50#include <linux/etherdevice.h>
51#include <linux/if_ether.h>
52#include <linux/if_vlan.h>
981813d8 53#include <linux/dca.h>
0da34b6d
BG		 54#include <linux/ip.h>
55#include <linux/inet.h>
56#include <linux/in.h>
57#include <linux/ethtool.h>
58#include <linux/firmware.h>
59#include <linux/delay.h>
0da34b6d
BG		 60#include <linux/timer.h>
61#include <linux/vmalloc.h>
62#include <linux/crc32.h>
63#include <linux/moduleparam.h>
64#include <linux/io.h>
199126a2 65#include <linux/log2.h>
5a0e3ad6 66#include <linux/slab.h>
70c71606 67#include <linux/prefetch.h>
0da34b6d 68#include <net/checksum.h>
1e6e9342
AG		 69#include <net/ip.h>
70#include <net/tcp.h>
0da34b6d
BG		 71#include <asm/byteorder.h>
72#include <asm/io.h>
0da34b6d
BG		 73#include <asm/processor.h>
74#ifdef CONFIG_MTRR
75#include <asm/mtrr.h>
76#endif
0dde8026 77#include <net/busy_poll.h>
0da34b6d
BG		 78
79#include "myri10ge_mcp.h"
80#include "myri10ge_mcp_gen_header.h"
81
3bea1237 82#define MYRI10GE_VERSION_STR "1.5.3-1.534"
0da34b6d
BG		 83
84MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
85MODULE_AUTHOR("Maintainer: help@myri.com");
86MODULE_VERSION(MYRI10GE_VERSION_STR);
87MODULE_LICENSE("Dual BSD/GPL");
88
89#define MYRI10GE_MAX_ETHER_MTU 9014
90
91#define MYRI10GE_ETH_STOPPED 0
92#define MYRI10GE_ETH_STOPPING 1
93#define MYRI10GE_ETH_STARTING 2
94#define MYRI10GE_ETH_RUNNING 3
95#define MYRI10GE_ETH_OPEN_FAILED 4
96
97#define MYRI10GE_EEPROM_STRINGS_SIZE 256
98#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
99
40f6cff5 100#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 101#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
102
dd50f336
BG		 103#define MYRI10GE_ALLOC_ORDER 0
104#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
105#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
106
236bb5e6
BG		 107#define MYRI10GE_MAX_SLICES 32
108
0da34b6d 109struct myri10ge_rx_buffer_state {
dd50f336
BG		 110 struct page *page;
111 int page_offset;
c755b4b6
FT		 112 DEFINE_DMA_UNMAP_ADDR(bus);
113 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 114};
115
116struct myri10ge_tx_buffer_state {
117 struct sk_buff *skb;
118 int last;
c755b4b6
FT		 119 DEFINE_DMA_UNMAP_ADDR(bus);
120 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 121};
122
123struct myri10ge_cmd {
124 u32 data0;
125 u32 data1;
126 u32 data2;
127};
128
129struct myri10ge_rx_buf {
130 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 131 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
132 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 133 struct page *page;
134 dma_addr_t bus;
135 int page_offset;
0da34b6d 136 int cnt;
dd50f336 137 int fill_cnt;
0da34b6d
BG		 138 int alloc_fail;
139 int mask; /* number of rx slots -1 */
dd50f336 140 int watchdog_needed;
0da34b6d
BG		 141};
142
143struct myri10ge_tx_buf {
144 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 145 __be32 __iomem *send_go; /* "go" doorbell ptr */
146 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 147 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
148 char *req_bytes;
149 struct myri10ge_tx_buffer_state *info;
150 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 151 int req ____cacheline_aligned; /* transmit slots submitted */
152 int pkt_start; /* packets started */
b53bef84
BG		 153 int stop_queue;
154 int linearized;
0da34b6d
BG		 155 int done ____cacheline_aligned; /* transmit slots completed */
156 int pkt_done; /* packets completed */
b53bef84 157 int wake_queue;
236bb5e6 158 int queue_active;
0da34b6d
BG		 159};
160
161struct myri10ge_rx_done {
162 struct mcp_slot *entry;
163 dma_addr_t bus;
164 int cnt;
165 int idx;
166};
167
b53bef84
BG		 168struct myri10ge_slice_netstats {
169 unsigned long rx_packets;
170 unsigned long tx_packets;
171 unsigned long rx_bytes;
172 unsigned long tx_bytes;
173 unsigned long rx_dropped;
174 unsigned long tx_dropped;
175};
176
177struct myri10ge_slice_state {
0da34b6d
BG		 178 struct myri10ge_tx_buf tx; /* transmit ring */
179 struct myri10ge_rx_buf rx_small;
180 struct myri10ge_rx_buf rx_big;
181 struct myri10ge_rx_done rx_done;
b53bef84
BG		 182 struct net_device *dev;
183 struct napi_struct napi;
184 struct myri10ge_priv *mgp;
185 struct myri10ge_slice_netstats stats;
186 __be32 __iomem *irq_claim;
187 struct mcp_irq_data *fw_stats;
188 dma_addr_t fw_stats_bus;
189 int watchdog_tx_done;
190 int watchdog_tx_req;
d0234215 191 int watchdog_rx_done;
c689b81b 192 int stuck;
5dd2d332 193#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 194 int cached_dca_tag;
195 int cpu;
196 __be32 __iomem *dca_tag;
197#endif
0dde8026
HYK		 198#ifdef CONFIG_NET_RX_BUSY_POLL
199 unsigned int state;
200#define SLICE_STATE_IDLE 0
201#define SLICE_STATE_NAPI 1 /* NAPI owns this slice */
202#define SLICE_STATE_POLL 2 /* poll owns this slice */
203#define SLICE_LOCKED (SLICE_STATE_NAPI | SLICE_STATE_POLL)
204#define SLICE_STATE_NAPI_YIELD 4 /* NAPI yielded this slice */
205#define SLICE_STATE_POLL_YIELD 8 /* poll yielded this slice */
206#define SLICE_USER_PEND (SLICE_STATE_POLL | SLICE_STATE_POLL_YIELD)
207 spinlock_t lock;
208 unsigned long lock_napi_yield;
209 unsigned long lock_poll_yield;
210 unsigned long busy_poll_miss;
211 unsigned long busy_poll_cnt;
212#endif /* CONFIG_NET_RX_BUSY_POLL */
0dcffac1 213 char irq_desc[32];
b53bef84
BG		 214};
215
216struct myri10ge_priv {
0dcffac1 217 struct myri10ge_slice_state *ss;
b53bef84 218 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 219 int num_slices;
b53bef84 220 int running; /* running? */
0da34b6d 221 int small_bytes;
dd50f336 222 int big_bytes;
fa0a90d9 223 int max_intr_slots;
0da34b6d 224 struct net_device *dev;
0da34b6d
BG		 225 u8 __iomem *sram;
226 int sram_size;
227 unsigned long board_span;
228 unsigned long iomem_base;
40f6cff5 229 __be32 __iomem *irq_deassert;
0da34b6d
BG		 230 char *mac_addr_string;
231 struct mcp_cmd_response *cmd;
232 dma_addr_t cmd_bus;
0da34b6d
BG		 233 struct pci_dev *pdev;
234 int msi_enabled;
0dcffac1
BG		 235 int msix_enabled;
236 struct msix_entry *msix_vectors;
5dd2d332 237#ifdef CONFIG_MYRI10GE_DCA
981813d8 238 int dca_enabled;
ef09aadf 239 int relaxed_order;
981813d8 240#endif
66341fff 241 u32 link_state;
0da34b6d
BG		 242 unsigned int rdma_tags_available;
243 int intr_coal_delay;
40f6cff5 244 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 245 int mtrr;
276e26c3 246 int wc_enabled;
0da34b6d
BG		 247 int down_cnt;
248 wait_queue_head_t down_wq;
249 struct work_struct watchdog_work;
250 struct timer_list watchdog_timer;
0da34b6d 251 int watchdog_resets;
b53bef84 252 int watchdog_pause;
0da34b6d 253 int pause;
7d351035 254 bool fw_name_allocated;
0da34b6d
BG		 255 char *fw_name;
256 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 257 char *product_code_string;
0da34b6d 258 char fw_version[128];
9dc6f0e7
BG		 259 int fw_ver_major;
260 int fw_ver_minor;
261 int fw_ver_tiny;
262 int adopted_rx_filter_bug;
1409a932 263 u8 mac_addr[ETH_ALEN]; /* eeprom mac address */
0da34b6d
BG		 264 unsigned long serial_number;
265 int vendor_specific_offset;
85a7ea1b 266 int fw_multicast_support;
04ed3e74 267 u32 features;
4f93fde0 268 u32 max_tso6;
0da34b6d
BG		 269 u32 read_dma;
270 u32 write_dma;
271 u32 read_write_dma;
c58ac5ca
BG		 272 u32 link_changes;
273 u32 msg_enable;
2d90b0aa 274 unsigned int board_number;
d0234215 275 int rebooted;
0da34b6d
BG		 276};
277
278static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
279static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 280static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
281static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
b9721d5a
BH		 282MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
283MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
284MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
285MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
0da34b6d 286
7d351035 287/* Careful: must be accessed under kparam_block_sysfs_write */
0da34b6d
BG		 288static char *myri10ge_fw_name = NULL;
289module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 290MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 291
2d90b0aa
BG		 292#define MYRI10GE_MAX_BOARDS 8
293static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 294 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 295module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
296 0444);
297MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
298
0da34b6d
BG		 299static int myri10ge_ecrc_enable = 1;
300module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 301MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 302
0da34b6d
BG		 303static int myri10ge_small_bytes = -1; /* -1 == auto */
304module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 305MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 306
307static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 308module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 309MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 310
f761fae1 311static int myri10ge_intr_coal_delay = 75;
0da34b6d 312module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 313MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 314
315static int myri10ge_flow_control = 1;
316module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 317MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 318
319static int myri10ge_deassert_wait = 1;
320module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
321MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 322 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 323
324static int myri10ge_force_firmware = 0;
325module_param(myri10ge_force_firmware, int, S_IRUGO);
326MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 327 "Force firmware to assume aligned completions");
0da34b6d 328
0da34b6d
BG		 329static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
330module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 331MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 332
333static int myri10ge_napi_weight = 64;
334module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 335MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 336
337static int myri10ge_watchdog_timeout = 1;
338module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 339MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 340
341static int myri10ge_max_irq_loops = 1048576;
342module_param(myri10ge_max_irq_loops, int, S_IRUGO);
343MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 344 "Set stuck legacy IRQ detection threshold");
0da34b6d 345
c58ac5ca
BG		 346#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
347
348static int myri10ge_debug = -1; /* defaults above */
349module_param(myri10ge_debug, int, 0);
350MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
351
dd50f336
BG		 352static int myri10ge_fill_thresh = 256;
353module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 354MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 355
f181137f
BG		 356static int myri10ge_reset_recover = 1;
357
0dcffac1
BG		 358static int myri10ge_max_slices = 1;
359module_param(myri10ge_max_slices, int, S_IRUGO);
360MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
361
4b860abf 362static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
0dcffac1
BG		 363module_param(myri10ge_rss_hash, int, S_IRUGO);
364MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
365
981813d8
BG		 366static int myri10ge_dca = 1;
367module_param(myri10ge_dca, int, S_IRUGO);
368MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
369
0da34b6d
BG		 370#define MYRI10GE_FW_OFFSET 1024*1024
371#define MYRI10GE_HIGHPART_TO_U32(X) \
372(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
373#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
374
375#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
376
2f76216f 377static void myri10ge_set_multicast_list(struct net_device *dev);
61357325
SH		 378static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
379 struct net_device *dev);
2f76216f 380
6250223e 381static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 382{
6250223e 383 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 384}
385
c5f7ef72 386static struct rtnl_link_stats64 *myri10ge_get_stats(struct net_device *dev,
387 struct rtnl_link_stats64 *stats);
59081825 388
7d351035
RR		 389static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
390{
391 if (mgp->fw_name_allocated)
392 kfree(mgp->fw_name);
393 mgp->fw_name = name;
394 mgp->fw_name_allocated = allocated;
395}
396
0da34b6d
BG		 397static int
398myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
399 struct myri10ge_cmd *data, int atomic)
400{
401 struct mcp_cmd *buf;
402 char buf_bytes[sizeof(*buf) + 8];
403 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 404 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 405 u32 dma_low, dma_high, result, value;
406 int sleep_total = 0;
407
408 /* ensure buf is aligned to 8 bytes */
409 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
410
411 buf->data0 = htonl(data->data0);
412 buf->data1 = htonl(data->data1);
413 buf->data2 = htonl(data->data2);
414 buf->cmd = htonl(cmd);
415 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
416 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
417
418 buf->response_addr.low = htonl(dma_low);
419 buf->response_addr.high = htonl(dma_high);
40f6cff5 420 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 421 mb();
422 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
423
424 /* wait up to 15ms. Longest command is the DMA benchmark,
425 * which is capped at 5ms, but runs from a timeout handler
426 * that runs every 7.8ms. So a 15ms timeout leaves us with
427 * a 2.2ms margin
428 */
429 if (atomic) {
430 /* if atomic is set, do not sleep,
431 * and try to get the completion quickly
432 * (1ms will be enough for those commands) */
433 for (sleep_total = 0;
8e95a202
JP		 434 sleep_total < 1000 &&
435 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 436 sleep_total += 10) {
0da34b6d 437 udelay(10);
bd2db0cf
BG		 438 mb();
439 }
0da34b6d
BG		 440 } else {
441 /* use msleep for most command */
442 for (sleep_total = 0;
8e95a202
JP		 443 sleep_total < 15 &&
444 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 445 sleep_total++)
446 msleep(1);
447 }
448
449 result = ntohl(response->result);
450 value = ntohl(response->data);
451 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
452 if (result == 0) {
453 data->data0 = value;
454 return 0;
85a7ea1b
BG		 455 } else if (result == MXGEFW_CMD_UNKNOWN) {
456 return -ENOSYS;
5443e9ea
BG		 457 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
458 return -E2BIG;
236bb5e6
BG		 459 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
460 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
461 (data->
462 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
463 0) {
464 return -ERANGE;
0da34b6d
BG		 465 } else {
466 dev_err(&mgp->pdev->dev,
467 "command %d failed, result = %d\n",
468 cmd, result);
469 return -ENXIO;
470 }
471 }
472
473 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
474 cmd, result);
475 return -EAGAIN;
476}
477
478/*
479 * The eeprom strings on the lanaiX have the format
480 * SN=x\0
481 * MAC=x:x:x:x:x:x\0
482 * PT:ddd mmm xx xx:xx:xx xx\0
483 * PV:ddd mmm xx xx:xx:xx xx\0
484 */
485static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
486{
487 char *ptr, *limit;
488 int i;
489
490 ptr = mgp->eeprom_strings;
491 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
492
493 while (*ptr != '\0' && ptr < limit) {
494 if (memcmp(ptr, "MAC=", 4) == 0) {
495 ptr += 4;
496 mgp->mac_addr_string = ptr;
497 for (i = 0; i < 6; i++) {
498 if ((ptr + 2) > limit)
499 goto abort;
500 mgp->mac_addr[i] =
501 simple_strtoul(ptr, &ptr, 16);
502 ptr += 1;
503 }
504 }
c0bf8801
BG		 505 if (memcmp(ptr, "PC=", 3) == 0) {
506 ptr += 3;
507 mgp->product_code_string = ptr;
508 }
0da34b6d
BG		 509 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
510 ptr += 3;
511 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
512 }
513 while (ptr < limit && *ptr++) ;
514 }
515
516 return 0;
517
518abort:
519 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
520 return -ENXIO;
521}
522
523/*
524 * Enable or disable periodic RDMAs from the host to make certain
525 * chipsets resend dropped PCIe messages
526 */
527
528static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
529{
530 char __iomem *submit;
f8fd57c1 531 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 532 u32 dma_low, dma_high;
533 int i;
534
535 /* clear confirmation addr */
536 mgp->cmd->data = 0;
537 mb();
538
539 /* send a rdma command to the PCIe engine, and wait for the
540 * response in the confirmation address. The firmware should
541 * write a -1 there to indicate it is alive and well
542 */
543 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
544 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
545
546 buf[0] = htonl(dma_high); /* confirm addr MSW */
547 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 548 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 549 buf[3] = htonl(dma_high); /* dummy addr MSW */
550 buf[4] = htonl(dma_low); /* dummy addr LSW */
551 buf[5] = htonl(enable); /* enable? */
552
e700f9f4 553 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 554
555 myri10ge_pio_copy(submit, &buf, sizeof(buf));
556 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
557 msleep(1);
558 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
559 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
560 (enable ? "enable" : "disable"));
561}
562
563static int
564myri10ge_validate_firmware(struct myri10ge_priv *mgp,
565 struct mcp_gen_header *hdr)
566{
567 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 568
569 /* check firmware type */
570 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
571 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
572 return -EINVAL;
573 }
574
575 /* save firmware version for ethtool */
576 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
577
9dc6f0e7
BG		 578 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
579 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 580
8e95a202
JP		 581 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
582 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 583 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
584 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
585 MXGEFW_VERSION_MINOR);
586 return -EINVAL;
587 }
588 return 0;
589}
590
591static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
592{
593 unsigned crc, reread_crc;
594 const struct firmware *fw;
595 struct device *dev = &mgp->pdev->dev;
b0d31d6b 596 unsigned char *fw_readback;
0da34b6d
BG		 597 struct mcp_gen_header *hdr;
598 size_t hdr_offset;
599 int status;
e454358a 600 unsigned i;
0da34b6d
BG		 601
602 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
603 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
604 mgp->fw_name);
605 status = -EINVAL;
606 goto abort_with_nothing;
607 }
608
609 /* check size */
610
611 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
612 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
613 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
614 status = -EINVAL;
615 goto abort_with_fw;
616 }
617
618 /* check id */
40f6cff5 619 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 620 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
621 dev_err(dev, "Bad firmware file\n");
622 status = -EINVAL;
623 goto abort_with_fw;
624 }
625 hdr = (void *)(fw->data + hdr_offset);
626
627 status = myri10ge_validate_firmware(mgp, hdr);
628 if (status != 0)
629 goto abort_with_fw;
630
631 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 632 for (i = 0; i < fw->size; i += 256) {
633 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
634 fw->data + i,
635 min(256U, (unsigned)(fw->size - i)));
636 mb();
637 readb(mgp->sram);
b10c0668 638 }
b0d31d6b
DW		 639 fw_readback = vmalloc(fw->size);
640 if (!fw_readback) {
641 status = -ENOMEM;
642 goto abort_with_fw;
643 }
0da34b6d 644 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 645 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
646 reread_crc = crc32(~0, fw_readback, fw->size);
647 vfree(fw_readback);
0da34b6d
BG		 648 if (crc != reread_crc) {
649 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
650 (unsigned)fw->size, reread_crc, crc);
651 status = -EIO;
652 goto abort_with_fw;
653 }
654 *size = (u32) fw->size;
655
656abort_with_fw:
657 release_firmware(fw);
658
659abort_with_nothing:
660 return status;
661}
662
663static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
664{
665 struct mcp_gen_header *hdr;
666 struct device *dev = &mgp->pdev->dev;
667 const size_t bytes = sizeof(struct mcp_gen_header);
668 size_t hdr_offset;
669 int status;
670
671 /* find running firmware header */
66341fff 672 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 673
674 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
675 dev_err(dev, "Running firmware has bad header offset (%d)\n",
676 (int)hdr_offset);
677 return -EIO;
678 }
679
680 /* copy header of running firmware from SRAM to host memory to
681 * validate firmware */
682 hdr = kmalloc(bytes, GFP_KERNEL);
b2adaca9 683 if (hdr == NULL)
0da34b6d 684 return -ENOMEM;
b2adaca9 685
0da34b6d
BG		 686 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
687 status = myri10ge_validate_firmware(mgp, hdr);
688 kfree(hdr);
9dc6f0e7
BG		 689
690 /* check to see if adopted firmware has bug where adopting
691 * it will cause broadcasts to be filtered unless the NIC
692 * is kept in ALLMULTI mode */
693 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
694 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
695 mgp->adopted_rx_filter_bug = 1;
696 dev_warn(dev, "Adopting fw %d.%d.%d: "
697 "working around rx filter bug\n",
698 mgp->fw_ver_major, mgp->fw_ver_minor,
699 mgp->fw_ver_tiny);
700 }
0da34b6d
BG		 701 return status;
702}
703
0178ec3d 704static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 705{
706 struct myri10ge_cmd cmd;
707 int status;
708
709 /* probe for IPv6 TSO support */
710 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
711 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
712 &cmd, 0);
713 if (status == 0) {
714 mgp->max_tso6 = cmd.data0;
715 mgp->features |= NETIF_F_TSO6;
716 }
717
718 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
719 if (status != 0) {
720 dev_err(&mgp->pdev->dev,
721 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
722 return -ENXIO;
723 }
724
725 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
726
727 return 0;
728}
729
0dcffac1 730static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 731{
732 char __iomem *submit;
f8fd57c1 733 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 734 u32 dma_low, dma_high, size;
735 int status, i;
736
b10c0668 737 size = 0;
0da34b6d
BG		 738 status = myri10ge_load_hotplug_firmware(mgp, &size);
739 if (status) {
0dcffac1
BG		 740 if (!adopt)
741 return status;
0da34b6d
BG		 742 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
743
744 /* Do not attempt to adopt firmware if there
745 * was a bad crc */
746 if (status == -EIO)
747 return status;
748
749 status = myri10ge_adopt_running_firmware(mgp);
750 if (status != 0) {
751 dev_err(&mgp->pdev->dev,
752 "failed to adopt running firmware\n");
753 return status;
754 }
755 dev_info(&mgp->pdev->dev,
756 "Successfully adopted running firmware\n");
b53bef84 757 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 758 dev_warn(&mgp->pdev->dev,
759 "Using firmware currently running on NIC"
760 ". For optimal\n");
761 dev_warn(&mgp->pdev->dev,
762 "performance consider loading optimized "
763 "firmware\n");
764 dev_warn(&mgp->pdev->dev, "via hotplug\n");
765 }
766
7d351035 767 set_fw_name(mgp, "adopted", false);
b53bef84 768 mgp->tx_boundary = 2048;
fa0a90d9
BG		 769 myri10ge_dummy_rdma(mgp, 1);
770 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 771 return status;
772 }
773
774 /* clear confirmation addr */
775 mgp->cmd->data = 0;
776 mb();
777
778 /* send a reload command to the bootstrap MCP, and wait for the
779 * response in the confirmation address. The firmware should
780 * write a -1 there to indicate it is alive and well
781 */
782 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
783 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
784
785 buf[0] = htonl(dma_high); /* confirm addr MSW */
786 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 787 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 788
789 /* FIX: All newest firmware should un-protect the bottom of
790 * the sram before handoff. However, the very first interfaces
791 * do not. Therefore the handoff copy must skip the first 8 bytes
792 */
793 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
794 buf[4] = htonl(size - 8); /* length of code */
795 buf[5] = htonl(8); /* where to copy to */
796 buf[6] = htonl(0); /* where to jump to */
797
e700f9f4 798 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 799
800 myri10ge_pio_copy(submit, &buf, sizeof(buf));
801 mb();
802 msleep(1);
803 mb();
804 i = 0;
d93ca2a4
BG		 805 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
806 msleep(1 << i);
0da34b6d
BG		 807 i++;
808 }
809 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
810 dev_err(&mgp->pdev->dev, "handoff failed\n");
811 return -ENXIO;
812 }
9a71db72 813 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 814 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 815
fa0a90d9 816 return status;
0da34b6d
BG		 817}
818
819static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
820{
821 struct myri10ge_cmd cmd;
822 int status;
823
824 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
825 | (addr[2] << 8) | addr[3]);
826
827 cmd.data1 = ((addr[4] << 8) | (addr[5]));
828
829 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
830 return status;
831}
832
833static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
834{
835 struct myri10ge_cmd cmd;
836 int status, ctl;
837
838 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
839 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
840
841 if (status) {
78ca90ea 842 netdev_err(mgp->dev, "Failed to set flow control mode\n");
0da34b6d
BG		 843 return status;
844 }
845 mgp->pause = pause;
846 return 0;
847}
848
849static void
850myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
851{
852 struct myri10ge_cmd cmd;
853 int status, ctl;
854
855 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
856 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
857 if (status)
78ca90ea 858 netdev_err(mgp->dev, "Failed to set promisc mode\n");
0da34b6d
BG		 859}
860
0d6ac257 861static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 862{
863 struct myri10ge_cmd cmd;
864 int status;
0da34b6d 865 u32 len;
34fdccea
BG		 866 struct page *dmatest_page;
867 dma_addr_t dmatest_bus;
0d6ac257
BG		 868 char *test = " ";
869
870 dmatest_page = alloc_page(GFP_KERNEL);
871 if (!dmatest_page)
872 return -ENOMEM;
873 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
874 DMA_BIDIRECTIONAL);
875
876 /* Run a small DMA test.
877 * The magic multipliers to the length tell the firmware
878 * to do DMA read, write, or read+write tests. The
879 * results are returned in cmd.data0. The upper 16
880 * bits or the return is the number of transfers completed.
881 * The lower 16 bits is the time in 0.5us ticks that the
882 * transfers took to complete.
883 */
884
b53bef84 885 len = mgp->tx_boundary;
0d6ac257
BG		 886
887 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
888 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
889 cmd.data2 = len * 0x10000;
890 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
891 if (status != 0) {
892 test = "read";
893 goto abort;
894 }
895 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
896 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
897 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
898 cmd.data2 = len * 0x1;
899 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
900 if (status != 0) {
901 test = "write";
902 goto abort;
903 }
904 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
905
906 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
907 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
908 cmd.data2 = len * 0x10001;
909 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
910 if (status != 0) {
911 test = "read/write";
912 goto abort;
913 }
914 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
915 (cmd.data0 & 0xffff);
916
917abort:
918 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
919 put_page(dmatest_page);
920
921 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
922 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
923 test, status);
924
925 return status;
926}
927
0dde8026
HYK		 928#ifdef CONFIG_NET_RX_BUSY_POLL
929static inline void myri10ge_ss_init_lock(struct myri10ge_slice_state *ss)
930{
931 spin_lock_init(&ss->lock);
932 ss->state = SLICE_STATE_IDLE;
933}
934
935static inline bool myri10ge_ss_lock_napi(struct myri10ge_slice_state *ss)
936{
de36cef3 937 bool rc = true;
0dde8026
HYK		 938 spin_lock(&ss->lock);
939 if ((ss->state & SLICE_LOCKED)) {
940 WARN_ON((ss->state & SLICE_STATE_NAPI));
941 ss->state |= SLICE_STATE_NAPI_YIELD;
942 rc = false;
943 ss->lock_napi_yield++;
944 } else
945 ss->state = SLICE_STATE_NAPI;
946 spin_unlock(&ss->lock);
947 return rc;
948}
949
950static inline void myri10ge_ss_unlock_napi(struct myri10ge_slice_state *ss)
951{
952 spin_lock(&ss->lock);
953 WARN_ON((ss->state & (SLICE_STATE_POLL | SLICE_STATE_NAPI_YIELD)));
954 ss->state = SLICE_STATE_IDLE;
955 spin_unlock(&ss->lock);
956}
957
958static inline bool myri10ge_ss_lock_poll(struct myri10ge_slice_state *ss)
959{
de36cef3 960 bool rc = true;
0dde8026
HYK		 961 spin_lock_bh(&ss->lock);
962 if ((ss->state & SLICE_LOCKED)) {
963 ss->state |= SLICE_STATE_POLL_YIELD;
964 rc = false;
965 ss->lock_poll_yield++;
966 } else
967 ss->state |= SLICE_STATE_POLL;
968 spin_unlock_bh(&ss->lock);
969 return rc;
970}
971
972static inline void myri10ge_ss_unlock_poll(struct myri10ge_slice_state *ss)
973{
974 spin_lock_bh(&ss->lock);
975 WARN_ON((ss->state & SLICE_STATE_NAPI));
976 ss->state = SLICE_STATE_IDLE;
977 spin_unlock_bh(&ss->lock);
978}
979
980static inline bool myri10ge_ss_busy_polling(struct myri10ge_slice_state *ss)
981{
982 WARN_ON(!(ss->state & SLICE_LOCKED));
983 return (ss->state & SLICE_USER_PEND);
984}
985#else /* CONFIG_NET_RX_BUSY_POLL */
986static inline void myri10ge_ss_init_lock(struct myri10ge_slice_state *ss)
987{
988}
989
990static inline bool myri10ge_ss_lock_napi(struct myri10ge_slice_state *ss)
991{
992 return false;
993}
994
995static inline void myri10ge_ss_unlock_napi(struct myri10ge_slice_state *ss)
996{
997}
998
999static inline bool myri10ge_ss_lock_poll(struct myri10ge_slice_state *ss)
1000{
1001 return false;
1002}
1003
1004static inline void myri10ge_ss_unlock_poll(struct myri10ge_slice_state *ss)
1005{
1006}
1007
1008static inline bool myri10ge_ss_busy_polling(struct myri10ge_slice_state *ss)
1009{
1010 return false;
1011}
1012#endif
1013
0d6ac257
BG		 1014static int myri10ge_reset(struct myri10ge_priv *mgp)
1015{
1016 struct myri10ge_cmd cmd;
0dcffac1
BG		 1017 struct myri10ge_slice_state *ss;
1018 int i, status;
0d6ac257 1019 size_t bytes;
5dd2d332 1020#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1021 unsigned long dca_tag_off;
1022#endif
0da34b6d
BG		 1023
1024 /* try to send a reset command to the card to see if it
1025 * is alive */
1026 memset(&cmd, 0, sizeof(cmd));
1027 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
1028 if (status != 0) {
1029 dev_err(&mgp->pdev->dev, "failed reset\n");
1030 return -ENXIO;
1031 }
0d6ac257
BG		 1032
1033 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 1034 /*
1035 * Use non-ndis mcp_slot (eg, 4 bytes total,
1036 * no toeplitz hash value returned. Older firmware will
1037 * not understand this command, but will use the correct
1038 * sized mcp_slot, so we ignore error returns
1039 */
1040 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
1041 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 1042
1043 /* Now exchange information about interrupts */
1044
0dcffac1 1045 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 1046 cmd.data0 = (u32) bytes;
1047 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 1048
1049 /*
1050 * Even though we already know how many slices are supported
1051 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
1052 * has magic side effects, and must be called after a reset.
1053 * It must be called prior to calling any RSS related cmds,
1054 * including assigning an interrupt queue for anything but
1055 * slice 0. It must also be called *after*
1056 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
1057 * the firmware to compute offsets.
1058 */
1059
1060 if (mgp->num_slices > 1) {
1061
1062 /* ask the maximum number of slices it supports */
1063 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
1064 &cmd, 0);
1065 if (status != 0) {
1066 dev_err(&mgp->pdev->dev,
1067 "failed to get number of slices\n");
1068 }
1069
1070 /*
1071 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
1072 * to setting up the interrupt queue DMA
1073 */
1074
1075 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 1076 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
1077 if (mgp->dev->real_num_tx_queues > 1)
1078 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 1079 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
1080 &cmd, 0);
236bb5e6
BG		 1081
1082 /* Firmware older than 1.4.32 only supports multiple
1083 * RX queues, so if we get an error, first retry using a
1084 * single TX queue before giving up */
1085 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
c9920268 1086 netif_set_real_num_tx_queues(mgp->dev, 1);
236bb5e6
BG		 1087 cmd.data0 = mgp->num_slices;
1088 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
1089 status = myri10ge_send_cmd(mgp,
1090 MXGEFW_CMD_ENABLE_RSS_QUEUES,
1091 &cmd, 0);
1092 }
1093
0dcffac1
BG		 1094 if (status != 0) {
1095 dev_err(&mgp->pdev->dev,
1096 "failed to set number of slices\n");
1097
1098 return status;
1099 }
1100 }
1101 for (i = 0; i < mgp->num_slices; i++) {
1102 ss = &mgp->ss[i];
1103 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1104 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1105 cmd.data2 = i;
1106 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1107 &cmd, 0);
6403eab1 1108 }
0da34b6d
BG		 1109
1110 status |=
1111 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1112 for (i = 0; i < mgp->num_slices; i++) {
1113 ss = &mgp->ss[i];
1114 ss->irq_claim =
1115 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1116 }
df30a740
BG		 1117 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1118 &cmd, 0);
1119 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1120
0da34b6d
BG		 1121 status |= myri10ge_send_cmd
1122 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1123 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1124 if (status != 0) {
1125 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1126 return status;
1127 }
40f6cff5 1128 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1129
5dd2d332 1130#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1131 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1132 dca_tag_off = cmd.data0;
1133 for (i = 0; i < mgp->num_slices; i++) {
1134 ss = &mgp->ss[i];
1135 if (status == 0) {
1136 ss->dca_tag = (__iomem __be32 *)
1137 (mgp->sram + dca_tag_off + 4 * i);
1138 } else {
1139 ss->dca_tag = NULL;
1140 }
1141 }
4ee2ac51 1142#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1143
0da34b6d 1144 /* reset mcp/driver shared state back to 0 */
0dcffac1 1145
c58ac5ca 1146 mgp->link_changes = 0;
0dcffac1
BG		 1147 for (i = 0; i < mgp->num_slices; i++) {
1148 ss = &mgp->ss[i];
1149
1150 memset(ss->rx_done.entry, 0, bytes);
1151 ss->tx.req = 0;
1152 ss->tx.done = 0;
1153 ss->tx.pkt_start = 0;
1154 ss->tx.pkt_done = 0;
1155 ss->rx_big.cnt = 0;
1156 ss->rx_small.cnt = 0;
1157 ss->rx_done.idx = 0;
1158 ss->rx_done.cnt = 0;
1159 ss->tx.wake_queue = 0;
1160 ss->tx.stop_queue = 0;
1161 }
1162
0da34b6d 1163 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1164 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1165 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1166 return status;
1167}
1168
5dd2d332 1169#ifdef CONFIG_MYRI10GE_DCA
ef09aadf
AG		 1170static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
1171{
9503e255 1172 int ret;
ef09aadf
AG		 1173 u16 ctl;
1174
9503e255 1175 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &ctl);
b3b6ae2c 1176
ef09aadf
AG		 1177 ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
1178 if (ret != on) {
1179 ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1180 ctl |= (on << 4);
9503e255 1181 pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, ctl);
ef09aadf
AG		 1182 }
1183 return ret;
1184}
1185
981813d8
BG		 1186static void
1187myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1188{
981813d8
BG		 1189 ss->cached_dca_tag = tag;
1190 put_be32(htonl(tag), ss->dca_tag);
1191}
1192
1193static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1194{
1195 int cpu = get_cpu();
1196 int tag;
1197
1198 if (cpu != ss->cpu) {
ef09aadf 1199 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
981813d8
BG		 1200 if (ss->cached_dca_tag != tag)
1201 myri10ge_write_dca(ss, cpu, tag);
ef09aadf 1202 ss->cpu = cpu;
981813d8
BG		 1203 }
1204 put_cpu();
1205}
1206
1207static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1208{
1209 int err, i;
1210 struct pci_dev *pdev = mgp->pdev;
1211
1212 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1213 return;
1214 if (!myri10ge_dca) {
1215 dev_err(&pdev->dev, "dca disabled by administrator\n");
1216 return;
1217 }
1218 err = dca_add_requester(&pdev->dev);
1219 if (err) {
330554cb
BG		 1220 if (err != -ENODEV)
1221 dev_err(&pdev->dev,
1222 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1223 return;
1224 }
ef09aadf 1225 mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
981813d8 1226 mgp->dca_enabled = 1;
ef09aadf
AG		 1227 for (i = 0; i < mgp->num_slices; i++) {
1228 mgp->ss[i].cpu = -1;
1229 mgp->ss[i].cached_dca_tag = -1;
1230 myri10ge_update_dca(&mgp->ss[i]);
b3b6ae2c 1231 }
981813d8
BG		 1232}
1233
1234static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1235{
1236 struct pci_dev *pdev = mgp->pdev;
981813d8
BG		 1237
1238 if (!mgp->dca_enabled)
1239 return;
1240 mgp->dca_enabled = 0;
ef09aadf
AG		 1241 if (mgp->relaxed_order)
1242 myri10ge_toggle_relaxed(pdev, 1);
b3b6ae2c 1243 dca_remove_requester(&pdev->dev);
981813d8
BG		 1244}
1245
1246static int myri10ge_notify_dca_device(struct device *dev, void *data)
1247{
1248 struct myri10ge_priv *mgp;
1249 unsigned long event;
1250
1251 mgp = dev_get_drvdata(dev);
1252 event = *(unsigned long *)data;
1253
1254 if (event == DCA_PROVIDER_ADD)
1255 myri10ge_setup_dca(mgp);
1256 else if (event == DCA_PROVIDER_REMOVE)
1257 myri10ge_teardown_dca(mgp);
1258 return 0;
1259}
4ee2ac51 1260#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1261
0da34b6d
BG		 1262static inline void
1263myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1264 struct mcp_kreq_ether_recv *src)
1265{
40f6cff5 1266 __be32 low;
0da34b6d
BG		 1267
1268 low = src->addr_low;
284901a9 1269 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1270 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1271 mb();
1272 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1273 mb();
1274 src->addr_low = low;
40f6cff5 1275 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1276 mb();
1277}
1278
40f6cff5 1279static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1280{
1281 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1282
40f6cff5 1283 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1284 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1285 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1286 skb->csum = hw_csum;
84fa7933 1287 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1288 }
1289}
1290
dd50f336
BG		 1291static void
1292myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1293 int bytes, int watchdog)
1294{
1295 struct page *page;
1296 int idx;
2a3f2790
BG		 1297#if MYRI10GE_ALLOC_SIZE > 4096
1298 int end_offset;
1299#endif
dd50f336
BG		 1300
1301 if (unlikely(rx->watchdog_needed && !watchdog))
1302 return;
1303
1304 /* try to refill entire ring */
1305 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1306 idx = rx->fill_cnt & rx->mask;
ae8509b1 1307 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1308 /* we can use part of previous page */
1309 get_page(rx->page);
1310 } else {
1311 /* we need a new page */
1312 page =
1313 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1314 MYRI10GE_ALLOC_ORDER);
1315 if (unlikely(page == NULL)) {
1316 if (rx->fill_cnt - rx->cnt < 16)
1317 rx->watchdog_needed = 1;
1318 return;
1319 }
1320 rx->page = page;
1321 rx->page_offset = 0;
1322 rx->bus = pci_map_page(mgp->pdev, page, 0,
1323 MYRI10GE_ALLOC_SIZE,
1324 PCI_DMA_FROMDEVICE);
1325 }
1326 rx->info[idx].page = rx->page;
1327 rx->info[idx].page_offset = rx->page_offset;
1328 /* note that this is the address of the start of the
1329 * page */
c755b4b6 1330 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
dd50f336
BG		 1331 rx->shadow[idx].addr_low =
1332 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1333 rx->shadow[idx].addr_high =
1334 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1335
1336 /* start next packet on a cacheline boundary */
1337 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1338
1339#if MYRI10GE_ALLOC_SIZE > 4096
1340 /* don't cross a 4KB boundary */
2a3f2790
BG		 1341 end_offset = rx->page_offset + bytes - 1;
1342 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1343 rx->page_offset = end_offset & ~4095;
ae8509b1 1344#endif
dd50f336
BG		 1345 rx->fill_cnt++;
1346
1347 /* copy 8 descriptors to the firmware at a time */
1348 if ((idx & 7) == 7) {
e454e7e2
BG		 1349 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1350 &rx->shadow[idx - 7]);
dd50f336
BG		 1351 }
1352 }
1353}
1354
1355static inline void
1356myri10ge_unmap_rx_page(struct pci_dev *pdev,
1357 struct myri10ge_rx_buffer_state *info, int bytes)
1358{
1359 /* unmap the recvd page if we're the only or last user of it */
1360 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1361 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
c755b4b6 1362 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
dd50f336
BG		 1363 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1364 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1365 }
1366}
1367
1b4c44e6
AG		 1368/*
1369 * GRO does not support acceleration of tagged vlan frames, and
1370 * this NIC does not support vlan tag offload, so we must pop
1371 * the tag ourselves to be able to achieve GRO performance that
1372 * is comparable to LRO.
1373 */
1374
1375static inline void
1376myri10ge_vlan_rx(struct net_device *dev, void *addr, struct sk_buff *skb)
1377{
1378 u8 *va;
1379 struct vlan_ethhdr *veh;
1380 struct skb_frag_struct *frag;
1381 __wsum vsum;
1382
1383 va = addr;
1384 va += MXGEFW_PAD;
1385 veh = (struct vlan_ethhdr *)va;
f646968f
PM		 1386 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
1387 NETIF_F_HW_VLAN_CTAG_RX &&
30828d2b 1388 veh->h_vlan_proto == htons(ETH_P_8021Q)) {
1b4c44e6
AG		 1389 /* fixup csum if needed */
1390 if (skb->ip_summed == CHECKSUM_COMPLETE) {
1391 vsum = csum_partial(va + ETH_HLEN, VLAN_HLEN, 0);
1392 skb->csum = csum_sub(skb->csum, vsum);
1393 }
1394 /* pop tag */
86a9bad3 1395 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(veh->h_vlan_TCI));
1b4c44e6
AG		 1396 memmove(va + VLAN_HLEN, va, 2 * ETH_ALEN);
1397 skb->len -= VLAN_HLEN;
1398 skb->data_len -= VLAN_HLEN;
1399 frag = skb_shinfo(skb)->frags;
1400 frag->page_offset += VLAN_HLEN;
1401 skb_frag_size_set(frag, skb_frag_size(frag) - VLAN_HLEN);
1402 }
1403}
1404
0dde8026
HYK		 1405#define MYRI10GE_HLEN 64 /* Bytes to copy from page to skb linear memory */
1406
dd50f336 1407static inline int
4ca3221f 1408myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum)
dd50f336 1409{
b53bef84 1410 struct myri10ge_priv *mgp = ss->mgp;
dd50f336 1411 struct sk_buff *skb;
4ca3221f 1412 struct skb_frag_struct *rx_frags;
b3cd9657 1413 struct myri10ge_rx_buf *rx;
4ca3221f 1414 int i, idx, remainder, bytes;
dd50f336
BG		 1415 struct pci_dev *pdev = mgp->pdev;
1416 struct net_device *dev = mgp->dev;
1417 u8 *va;
0dde8026 1418 bool polling;
dd50f336 1419
b3cd9657
SG		 1420 if (len <= mgp->small_bytes) {
1421 rx = &ss->rx_small;
1422 bytes = mgp->small_bytes;
1423 } else {
1424 rx = &ss->rx_big;
1425 bytes = mgp->big_bytes;
1426 }
1427
dd50f336
BG		 1428 len += MXGEFW_PAD;
1429 idx = rx->cnt & rx->mask;
1430 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1431 prefetch(va);
4ca3221f 1432
0dde8026
HYK		 1433 /* When busy polling in user context, allocate skb and copy headers to
1434 * skb's linear memory ourselves. When not busy polling, use the napi
1435 * gro api.
1436 */
1437 polling = myri10ge_ss_busy_polling(ss);
1438 if (polling)
1439 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1440 else
1441 skb = napi_get_frags(&ss->napi);
4ca3221f
AG		 1442 if (unlikely(skb == NULL)) {
1443 ss->stats.rx_dropped++;
1444 for (i = 0, remainder = len; remainder > 0; i++) {
1445 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1446 put_page(rx->info[idx].page);
1447 rx->cnt++;
1448 idx = rx->cnt & rx->mask;
1449 remainder -= MYRI10GE_ALLOC_SIZE;
1450 }
1451 return 0;
1452 }
1453 rx_frags = skb_shinfo(skb)->frags;
dd50f336
BG		 1454 /* Fill skb_frag_struct(s) with data from our receive */
1455 for (i = 0, remainder = len; remainder > 0; i++) {
1456 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
4ca3221f
AG		 1457 skb_fill_page_desc(skb, i, rx->info[idx].page,
1458 rx->info[idx].page_offset,
1459 remainder < MYRI10GE_ALLOC_SIZE ?
1460 remainder : MYRI10GE_ALLOC_SIZE);
dd50f336
BG		 1461 rx->cnt++;
1462 idx = rx->cnt & rx->mask;
1463 remainder -= MYRI10GE_ALLOC_SIZE;
1464 }
1465
4ca3221f
AG		 1466 /* remove padding */
1467 rx_frags[0].page_offset += MXGEFW_PAD;
1468 rx_frags[0].size -= MXGEFW_PAD;
1469 len -= MXGEFW_PAD;
dd50f336 1470
4ca3221f
AG		 1471 skb->len = len;
1472 skb->data_len = len;
1473 skb->truesize += len;
1474 if (dev->features & NETIF_F_RXCSUM) {
1475 skb->ip_summed = CHECKSUM_COMPLETE;
1476 skb->csum = csum;
dd50f336 1477 }
1b4c44e6 1478 myri10ge_vlan_rx(mgp->dev, va, skb);
0c8dfc83 1479 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
0dde8026
HYK		 1480 skb_mark_napi_id(skb, &ss->napi);
1481
1482 if (polling) {
1483 int hlen;
1484
1485 /* myri10ge_vlan_rx might have moved the header, so compute
1486 * length and address again.
1487 */
1488 hlen = MYRI10GE_HLEN > skb->len ? skb->len : MYRI10GE_HLEN;
1489 va = page_address(skb_frag_page(&rx_frags[0])) +
1490 rx_frags[0].page_offset;
1491 /* Copy header into the skb linear memory */
1492 skb_copy_to_linear_data(skb, va, hlen);
1493 rx_frags[0].page_offset += hlen;
1494 rx_frags[0].size -= hlen;
1495 skb->data_len -= hlen;
1496 skb->tail += hlen;
1497 skb->protocol = eth_type_trans(skb, dev);
1498 netif_receive_skb(skb);
1499 }
1500 else
1501 napi_gro_frags(&ss->napi);
dd50f336 1502
dd50f336
BG		 1503 return 1;
1504}
1505
b53bef84
BG		 1506static inline void
1507myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1508{
b53bef84
BG		 1509 struct pci_dev *pdev = ss->mgp->pdev;
1510 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1511 struct netdev_queue *dev_queue;
0da34b6d
BG		 1512 struct sk_buff *skb;
1513 int idx, len;
0da34b6d
BG		 1514
1515 while (tx->pkt_done != mcp_index) {
1516 idx = tx->done & tx->mask;
1517 skb = tx->info[idx].skb;
1518
1519 /* Mark as free */
1520 tx->info[idx].skb = NULL;
1521 if (tx->info[idx].last) {
1522 tx->pkt_done++;
1523 tx->info[idx].last = 0;
1524 }
1525 tx->done++;
c755b4b6
FT		 1526 len = dma_unmap_len(&tx->info[idx], len);
1527 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 1528 if (skb) {
b53bef84
BG		 1529 ss->stats.tx_bytes += skb->len;
1530 ss->stats.tx_packets++;
0da34b6d
BG		 1531 dev_kfree_skb_irq(skb);
1532 if (len)
1533 pci_unmap_single(pdev,
c755b4b6 1534 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1535 bus), len,
1536 PCI_DMA_TODEVICE);
1537 } else {
1538 if (len)
1539 pci_unmap_page(pdev,
c755b4b6 1540 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1541 bus), len,
1542 PCI_DMA_TODEVICE);
1543 }
0da34b6d 1544 }
236bb5e6
BG		 1545
1546 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1547 /*
1548 * Make a minimal effort to prevent the NIC from polling an
1549 * idle tx queue. If we can't get the lock we leave the queue
1550 * active. In this case, either a thread was about to start
1551 * using the queue anyway, or we lost a race and the NIC will
1552 * waste some of its resources polling an inactive queue for a
1553 * while.
1554 */
1555
1556 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1557 __netif_tx_trylock(dev_queue)) {
1558 if (tx->req == tx->done) {
1559 tx->queue_active = 0;
1560 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1561 mb();
6824a105 1562 mmiowb();
236bb5e6
BG		 1563 }
1564 __netif_tx_unlock(dev_queue);
1565 }
1566
0da34b6d 1567 /* start the queue if we've stopped it */
8e95a202 1568 if (netif_tx_queue_stopped(dev_queue) &&
3b20b2dc
JM		 1569 tx->req - tx->done < (tx->mask >> 1) &&
1570 ss->mgp->running == MYRI10GE_ETH_RUNNING) {
b53bef84 1571 tx->wake_queue++;
236bb5e6 1572 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1573 }
1574}
1575
b53bef84
BG		 1576static inline int
1577myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1578{
b53bef84
BG		 1579 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1580 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1581 unsigned long rx_bytes = 0;
1582 unsigned long rx_packets = 0;
1583 unsigned long rx_ok;
0da34b6d
BG		 1584 int idx = rx_done->idx;
1585 int cnt = rx_done->cnt;
bea3348e 1586 int work_done = 0;
0da34b6d 1587 u16 length;
40f6cff5 1588 __wsum checksum;
0da34b6d 1589
c956a240 1590 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1591 length = ntohs(rx_done->entry[idx].length);
1592 rx_done->entry[idx].length = 0;
40f6cff5 1593 checksum = csum_unfold(rx_done->entry[idx].checksum);
4ca3221f 1594 rx_ok = myri10ge_rx_done(ss, length, checksum);
0da34b6d
BG		 1595 rx_packets += rx_ok;
1596 rx_bytes += rx_ok * (unsigned long)length;
1597 cnt++;
014377a1 1598 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1599 work_done++;
0da34b6d
BG		 1600 }
1601 rx_done->idx = idx;
1602 rx_done->cnt = cnt;
b53bef84
BG		 1603 ss->stats.rx_packets += rx_packets;
1604 ss->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1605
1606 /* restock receive rings if needed */
b53bef84
BG		 1607 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1608 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1609 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1610 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1611 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1612
bea3348e 1613 return work_done;
0da34b6d
BG		 1614}
1615
1616static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1617{
0dcffac1 1618 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1619
1620 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1621 unsigned link_up = ntohl(stats->link_up);
1622 if (mgp->link_state != link_up) {
1623 mgp->link_state = link_up;
1624
1625 if (mgp->link_state == MXGEFW_LINK_UP) {
b3b6ae2c 1626 netif_info(mgp, link, mgp->dev, "link up\n");
0da34b6d 1627 netif_carrier_on(mgp->dev);
c58ac5ca 1628 mgp->link_changes++;
0da34b6d 1629 } else {
b3b6ae2c
JM		 1630 netif_info(mgp, link, mgp->dev, "link %s\n",
1631 (link_up == MXGEFW_LINK_MYRINET ?
78ca90ea 1632 "mismatch (Myrinet detected)" :
b3b6ae2c 1633 "down"));
0da34b6d 1634 netif_carrier_off(mgp->dev);
c58ac5ca 1635 mgp->link_changes++;
0da34b6d
BG		 1636 }
1637 }
1638 if (mgp->rdma_tags_available !=
b53bef84 1639 ntohl(stats->rdma_tags_available)) {
0da34b6d 1640 mgp->rdma_tags_available =
b53bef84 1641 ntohl(stats->rdma_tags_available);
78ca90ea
JP		 1642 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1643 mgp->rdma_tags_available);
0da34b6d
BG		 1644 }
1645 mgp->down_cnt += stats->link_down;
1646 if (stats->link_down)
1647 wake_up(&mgp->down_wq);
1648 }
1649}
1650
bea3348e 1651static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1652{
b53bef84
BG		 1653 struct myri10ge_slice_state *ss =
1654 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1655 int work_done;
0da34b6d 1656
5dd2d332 1657#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1658 if (ss->mgp->dca_enabled)
1659 myri10ge_update_dca(ss);
1660#endif
0dde8026
HYK		 1661 /* Try later if the busy_poll handler is running. */
1662 if (!myri10ge_ss_lock_napi(ss))
1663 return budget;
981813d8 1664
0da34b6d 1665 /* process as many rx events as NAPI will allow */
b53bef84 1666 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1667
0dde8026 1668 myri10ge_ss_unlock_napi(ss);
4ec24119 1669 if (work_done < budget) {
288379f0 1670 napi_complete(napi);
b53bef84 1671 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1672 }
bea3348e 1673 return work_done;
0da34b6d
BG		 1674}
1675
0dde8026
HYK		 1676#ifdef CONFIG_NET_RX_BUSY_POLL
1677static int myri10ge_busy_poll(struct napi_struct *napi)
1678{
1679 struct myri10ge_slice_state *ss =
1680 container_of(napi, struct myri10ge_slice_state, napi);
1681 struct myri10ge_priv *mgp = ss->mgp;
1682 int work_done;
1683
1684 /* Poll only when the link is up */
1685 if (mgp->link_state != MXGEFW_LINK_UP)
1686 return LL_FLUSH_FAILED;
1687
1688 if (!myri10ge_ss_lock_poll(ss))
1689 return LL_FLUSH_BUSY;
1690
1691 /* Process a small number of packets */
1692 work_done = myri10ge_clean_rx_done(ss, 4);
1693 if (work_done)
1694 ss->busy_poll_cnt += work_done;
1695 else
1696 ss->busy_poll_miss++;
1697
1698 myri10ge_ss_unlock_poll(ss);
1699
1700 return work_done;
1701}
1702#endif /* CONFIG_NET_RX_BUSY_POLL */
1703
7d12e780 1704static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1705{
b53bef84
BG		 1706 struct myri10ge_slice_state *ss = arg;
1707 struct myri10ge_priv *mgp = ss->mgp;
1708 struct mcp_irq_data *stats = ss->fw_stats;
1709 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1710 u32 send_done_count;
1711 int i;
1712
236bb5e6
BG		 1713 /* an interrupt on a non-zero receive-only slice is implicitly
1714 * valid since MSI-X irqs are not shared */
1715 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1716 napi_schedule(&ss->napi);
807540ba 1717 return IRQ_HANDLED;
0dcffac1
BG		 1718 }
1719
0da34b6d
BG		 1720 /* make sure it is our IRQ, and that the DMA has finished */
1721 if (unlikely(!stats->valid))
807540ba 1722 return IRQ_NONE;
0da34b6d
BG		 1723
1724 /* low bit indicates receives are present, so schedule
1725 * napi poll handler */
1726 if (stats->valid & 1)
288379f0 1727 napi_schedule(&ss->napi);
0da34b6d 1728
0dcffac1 1729 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1730 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1731 if (!myri10ge_deassert_wait)
1732 stats->valid = 0;
1733 mb();
1734 } else
1735 stats->valid = 0;
1736
1737 /* Wait for IRQ line to go low, if using INTx */
1738 i = 0;
1739 while (1) {
1740 i++;
1741 /* check for transmit completes and receives */
1742 send_done_count = ntohl(stats->send_done_count);
1743 if (send_done_count != tx->pkt_done)
b53bef84 1744 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d 1745 if (unlikely(i > myri10ge_max_irq_loops)) {
b3b6ae2c 1746 netdev_warn(mgp->dev, "irq stuck?\n");
0da34b6d
BG		 1747 stats->valid = 0;
1748 schedule_work(&mgp->watchdog_work);
1749 }
1750 if (likely(stats->valid == 0))
1751 break;
1752 cpu_relax();
1753 barrier();
1754 }
1755
236bb5e6
BG		 1756 /* Only slice 0 updates stats */
1757 if (ss == mgp->ss)
1758 myri10ge_check_statblock(mgp);
0da34b6d 1759
b53bef84 1760 put_be32(htonl(3), ss->irq_claim + 1);
807540ba 1761 return IRQ_HANDLED;
0da34b6d
BG		 1762}
1763
1764static int
1765myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1766{
c0bf8801
BG		 1767 struct myri10ge_priv *mgp = netdev_priv(netdev);
1768 char *ptr;
1769 int i;
1770
0da34b6d 1771 cmd->autoneg = AUTONEG_DISABLE;
70739497 1772 ethtool_cmd_speed_set(cmd, SPEED_10000);
0da34b6d 1773 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1774
1775 /*
1776 * parse the product code to deterimine the interface type
1777 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1778 * after the 3rd dash in the driver's cached copy of the
1779 * EEPROM's product code string.
1780 */
1781 ptr = mgp->product_code_string;
1782 if (ptr == NULL) {
78ca90ea 1783 netdev_err(netdev, "Missing product code\n");
c0bf8801
BG		 1784 return 0;
1785 }
1786 for (i = 0; i < 3; i++, ptr++) {
1787 ptr = strchr(ptr, '-');
1788 if (ptr == NULL) {
78ca90ea
JP		 1789 netdev_err(netdev, "Invalid product code %s\n",
1790 mgp->product_code_string);
c0bf8801
BG		 1791 return 0;
1792 }
1793 }
196f17eb
BG		 1794 if (*ptr == '2')
1795 ptr++;
1796 if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1797 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
c0bf8801 1798 cmd->port = PORT_FIBRE;
196f17eb
BG		 1799 cmd->supported |= SUPPORTED_FIBRE;
1800 cmd->advertising |= ADVERTISED_FIBRE;
1801 } else {
1802 cmd->port = PORT_OTHER;
c0bf8801 1803 }
196f17eb
BG		 1804 if (*ptr == 'R' || *ptr == 'S')
1805 cmd->transceiver = XCVR_EXTERNAL;
1806 else
1807 cmd->transceiver = XCVR_INTERNAL;
1808
0da34b6d
BG		 1809 return 0;
1810}
1811
1812static void
1813myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1814{
1815 struct myri10ge_priv *mgp = netdev_priv(netdev);
1816
1817 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1818 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1819 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1820 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1821}
1822
1823static int
1824myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1825{
1826 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1827
0da34b6d
BG		 1828 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1829 return 0;
1830}
1831
1832static int
1833myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1834{
1835 struct myri10ge_priv *mgp = netdev_priv(netdev);
1836
1837 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1838 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1839 return 0;
1840}
1841
1842static void
1843myri10ge_get_pauseparam(struct net_device *netdev,
1844 struct ethtool_pauseparam *pause)
1845{
1846 struct myri10ge_priv *mgp = netdev_priv(netdev);
1847
1848 pause->autoneg = 0;
1849 pause->rx_pause = mgp->pause;
1850 pause->tx_pause = mgp->pause;
1851}
1852
1853static int
1854myri10ge_set_pauseparam(struct net_device *netdev,
1855 struct ethtool_pauseparam *pause)
1856{
1857 struct myri10ge_priv *mgp = netdev_priv(netdev);
1858
1859 if (pause->tx_pause != mgp->pause)
1860 return myri10ge_change_pause(mgp, pause->tx_pause);
1861 if (pause->rx_pause != mgp->pause)
2488f56d 1862 return myri10ge_change_pause(mgp, pause->rx_pause);
0da34b6d
BG		 1863 if (pause->autoneg != 0)
1864 return -EINVAL;
1865 return 0;
1866}
1867
1868static void
1869myri10ge_get_ringparam(struct net_device *netdev,
1870 struct ethtool_ringparam *ring)
1871{
1872 struct myri10ge_priv *mgp = netdev_priv(netdev);
1873
0dcffac1
BG		 1874 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1875 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1876 ring->rx_jumbo_max_pending = 0;
6498be3f 1877 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1878 ring->rx_mini_pending = ring->rx_mini_max_pending;
1879 ring->rx_pending = ring->rx_max_pending;
1880 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1881 ring->tx_pending = ring->tx_max_pending;
1882}
1883
b53bef84 1884static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1885 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1886 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1887 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1888 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1889 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1890 "tx_heartbeat_errors", "tx_window_errors",
1891 /* device-specific stats */
0dcffac1 1892 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1893 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1894 "serial_number", "watchdog_resets",
5dd2d332 1895#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1896 "dca_capable_firmware", "dca_device_present",
981813d8 1897#endif
c58ac5ca 1898 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1899 "dropped_link_error_or_filtered",
1900 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1901 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1902 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1903 "dropped_no_big_buffer"
1904};
1905
1906static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1907 "----------- slice ---------",
1908 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1909 "rx_small_cnt", "rx_big_cnt",
b3b6ae2c 1910 "wake_queue", "stop_queue", "tx_linearized",
0dde8026
HYK		 1911#ifdef CONFIG_NET_RX_BUSY_POLL
1912 "rx_lock_napi_yield", "rx_lock_poll_yield", "rx_busy_poll_miss",
1913 "rx_busy_poll_cnt",
1914#endif
0da34b6d
BG		 1915};
1916
1917#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1918#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1919#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1920
1921static void
1922myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1923{
0dcffac1
BG		 1924 struct myri10ge_priv *mgp = netdev_priv(netdev);
1925 int i;
1926
0da34b6d
BG		 1927 switch (stringset) {
1928 case ETH_SS_STATS:
b53bef84
BG		 1929 memcpy(data, *myri10ge_gstrings_main_stats,
1930 sizeof(myri10ge_gstrings_main_stats));
1931 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1932 for (i = 0; i < mgp->num_slices; i++) {
1933 memcpy(data, *myri10ge_gstrings_slice_stats,
1934 sizeof(myri10ge_gstrings_slice_stats));
1935 data += sizeof(myri10ge_gstrings_slice_stats);
1936 }
0da34b6d
BG		 1937 break;
1938 }
1939}
1940
b9f2c044 1941static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1942{
0dcffac1
BG		 1943 struct myri10ge_priv *mgp = netdev_priv(netdev);
1944
b9f2c044
JG		 1945 switch (sset) {
1946 case ETH_SS_STATS:
0dcffac1
BG		 1947 return MYRI10GE_MAIN_STATS_LEN +
1948 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1949 default:
1950 return -EOPNOTSUPP;
1951 }
0da34b6d
BG		 1952}
1953
1954static void
1955myri10ge_get_ethtool_stats(struct net_device *netdev,
1956 struct ethtool_stats *stats, u64 * data)
1957{
1958 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1959 struct myri10ge_slice_state *ss;
c5f7ef72 1960 struct rtnl_link_stats64 link_stats;
0dcffac1 1961 int slice;
0da34b6d
BG		 1962 int i;
1963
59081825 1964 /* force stats update */
306ff6eb 1965 memset(&link_stats, 0, sizeof(link_stats));
c5f7ef72 1966 (void)myri10ge_get_stats(netdev, &link_stats);
0da34b6d 1967 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
c5f7ef72 1968 data[i] = ((u64 *)&link_stats)[i];
0da34b6d 1969
b53bef84 1970 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1971 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1972 data[i++] = (unsigned int)mgp->pdev->irq;
1973 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1974 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1975 data[i++] = (unsigned int)mgp->read_dma;
1976 data[i++] = (unsigned int)mgp->write_dma;
1977 data[i++] = (unsigned int)mgp->read_write_dma;
1978 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1979 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1980#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1981 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1982 data[i++] = (unsigned int)(mgp->dca_enabled);
1983#endif
c58ac5ca 1984 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1985
1986 /* firmware stats are useful only in the first slice */
0dcffac1 1987 ss = &mgp->ss[0];
b53bef84
BG		 1988 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1989 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1990 data[i++] =
b53bef84
BG		 1991 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1992 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1993 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1994 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1995 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1996 data[i++] =
b53bef84
BG		 1997 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1998 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1999 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
2000 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
2001 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
2002
0dcffac1
BG		 2003 for (slice = 0; slice < mgp->num_slices; slice++) {
2004 ss = &mgp->ss[slice];
2005 data[i++] = slice;
2006 data[i++] = (unsigned int)ss->tx.pkt_start;
2007 data[i++] = (unsigned int)ss->tx.pkt_done;
2008 data[i++] = (unsigned int)ss->tx.req;
2009 data[i++] = (unsigned int)ss->tx.done;
2010 data[i++] = (unsigned int)ss->rx_small.cnt;
2011 data[i++] = (unsigned int)ss->rx_big.cnt;
2012 data[i++] = (unsigned int)ss->tx.wake_queue;
2013 data[i++] = (unsigned int)ss->tx.stop_queue;
2014 data[i++] = (unsigned int)ss->tx.linearized;
0dde8026
HYK		 2015#ifdef CONFIG_NET_RX_BUSY_POLL
2016 data[i++] = ss->lock_napi_yield;
2017 data[i++] = ss->lock_poll_yield;
2018 data[i++] = ss->busy_poll_miss;
2019 data[i++] = ss->busy_poll_cnt;
2020#endif
0dcffac1 2021 }
0da34b6d
BG		 2022}
2023
c58ac5ca
BG		 2024static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
2025{
2026 struct myri10ge_priv *mgp = netdev_priv(netdev);
2027 mgp->msg_enable = value;
2028}
2029
2030static u32 myri10ge_get_msglevel(struct net_device *netdev)
2031{
2032 struct myri10ge_priv *mgp = netdev_priv(netdev);
2033 return mgp->msg_enable;
2034}
2035
5dcd8467
JM		 2036/*
2037 * Use a low-level command to change the LED behavior. Rather than
2038 * blinking (which is the normal case), when identify is used, the
2039 * yellow LED turns solid.
2040 */
2041static int myri10ge_led(struct myri10ge_priv *mgp, int on)
2042{
2043 struct mcp_gen_header *hdr;
2044 struct device *dev = &mgp->pdev->dev;
2045 size_t hdr_off, pattern_off, hdr_len;
2046 u32 pattern = 0xfffffffe;
2047
2048 /* find running firmware header */
2049 hdr_off = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
2050 if ((hdr_off & 3) || hdr_off + sizeof(*hdr) > mgp->sram_size) {
2051 dev_err(dev, "Running firmware has bad header offset (%d)\n",
2052 (int)hdr_off);
2053 return -EIO;
2054 }
2055 hdr_len = swab32(readl(mgp->sram + hdr_off +
2056 offsetof(struct mcp_gen_header, header_length)));
2057 pattern_off = hdr_off + offsetof(struct mcp_gen_header, led_pattern);
2058 if (pattern_off >= (hdr_len + hdr_off)) {
2059 dev_info(dev, "Firmware does not support LED identification\n");
2060 return -EINVAL;
2061 }
2062 if (!on)
2063 pattern = swab32(readl(mgp->sram + pattern_off + 4));
59e955ed 2064 writel(swab32(pattern), mgp->sram + pattern_off);
5dcd8467
JM		 2065 return 0;
2066}
2067
2068static int
2069myri10ge_phys_id(struct net_device *netdev, enum ethtool_phys_id_state state)
2070{
2071 struct myri10ge_priv *mgp = netdev_priv(netdev);
2072 int rc;
2073
2074 switch (state) {
2075 case ETHTOOL_ID_ACTIVE:
2076 rc = myri10ge_led(mgp, 1);
2077 break;
2078
2079 case ETHTOOL_ID_INACTIVE:
2080 rc = myri10ge_led(mgp, 0);
2081 break;
2082
2083 default:
2084 rc = -EINVAL;
2085 }
2086
2087 return rc;
2088}
2089
7282d491 2090static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 2091 .get_settings = myri10ge_get_settings,
2092 .get_drvinfo = myri10ge_get_drvinfo,
2093 .get_coalesce = myri10ge_get_coalesce,
2094 .set_coalesce = myri10ge_set_coalesce,
2095 .get_pauseparam = myri10ge_get_pauseparam,
2096 .set_pauseparam = myri10ge_set_pauseparam,
2097 .get_ringparam = myri10ge_get_ringparam,
6ffdd071 2098 .get_link = ethtool_op_get_link,
0da34b6d 2099 .get_strings = myri10ge_get_strings,
b9f2c044 2100 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 2101 .get_ethtool_stats = myri10ge_get_ethtool_stats,
2102 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d 2103 .get_msglevel = myri10ge_get_msglevel,
5dcd8467 2104 .set_phys_id = myri10ge_phys_id,
0da34b6d
BG		 2105};
2106
b53bef84 2107static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 2108{
b53bef84 2109 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 2110 struct myri10ge_cmd cmd;
b53bef84 2111 struct net_device *dev = mgp->dev;
0da34b6d
BG		 2112 int tx_ring_size, rx_ring_size;
2113 int tx_ring_entries, rx_ring_entries;
0dcffac1 2114 int i, slice, status;
0da34b6d
BG		 2115 size_t bytes;
2116
0da34b6d 2117 /* get ring sizes */
0dcffac1
BG		 2118 slice = ss - mgp->ss;
2119 cmd.data0 = slice;
0da34b6d
BG		 2120 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
2121 tx_ring_size = cmd.data0;
0dcffac1 2122 cmd.data0 = slice;
0da34b6d 2123 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 2124 if (status != 0)
2125 return status;
0da34b6d
BG		 2126 rx_ring_size = cmd.data0;
2127
2128 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
2129 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 2130 ss->tx.mask = tx_ring_entries - 1;
2131 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 2132
355c7265
BG		 2133 status = -ENOMEM;
2134
0da34b6d
BG		 2135 /* allocate the host shadow rings */
2136
2137 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 2138 * sizeof(*ss->tx.req_list);
2139 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
2140 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 2141 goto abort_with_nothing;
2142
2143 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 2144 ss->tx.req_list = (struct mcp_kreq_ether_send *)
2145 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 2146 ss->tx.queue_active = 0;
0da34b6d 2147
b53bef84
BG		 2148 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
2149 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
2150 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 2151 goto abort_with_tx_req_bytes;
2152
b53bef84
BG		 2153 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
2154 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
2155 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 2156 goto abort_with_rx_small_shadow;
2157
2158 /* allocate the host info rings */
2159
b53bef84
BG		 2160 bytes = tx_ring_entries * sizeof(*ss->tx.info);
2161 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
2162 if (ss->tx.info == NULL)
0da34b6d
BG		 2163 goto abort_with_rx_big_shadow;
2164
b53bef84
BG		 2165 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
2166 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
2167 if (ss->rx_small.info == NULL)
0da34b6d
BG		 2168 goto abort_with_tx_info;
2169
b53bef84
BG		 2170 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
2171 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
2172 if (ss->rx_big.info == NULL)
0da34b6d
BG		 2173 goto abort_with_rx_small_info;
2174
2175 /* Fill the receive rings */
b53bef84
BG		 2176 ss->rx_big.cnt = 0;
2177 ss->rx_small.cnt = 0;
2178 ss->rx_big.fill_cnt = 0;
2179 ss->rx_small.fill_cnt = 0;
2180 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2181 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2182 ss->rx_small.watchdog_needed = 0;
2183 ss->rx_big.watchdog_needed = 0;
4b47638a
JM		 2184 if (mgp->small_bytes == 0) {
2185 ss->rx_small.fill_cnt = ss->rx_small.mask + 1;
2186 } else {
2187 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
2188 mgp->small_bytes + MXGEFW_PAD, 0);
2189 }
0da34b6d 2190
b53bef84 2191 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
78ca90ea
JP		 2192 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2193 slice, ss->rx_small.fill_cnt);
c7dab99b 2194 goto abort_with_rx_small_ring;
0da34b6d
BG		 2195 }
2196
b53bef84
BG		 2197 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2198 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
78ca90ea
JP		 2199 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2200 slice, ss->rx_big.fill_cnt);
c7dab99b 2201 goto abort_with_rx_big_ring;
0da34b6d
BG		 2202 }
2203
2204 return 0;
2205
2206abort_with_rx_big_ring:
b53bef84
BG		 2207 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2208 int idx = i & ss->rx_big.mask;
2209 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2210 mgp->big_bytes);
b53bef84 2211 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2212 }
2213
2214abort_with_rx_small_ring:
4b47638a
JM		 2215 if (mgp->small_bytes == 0)
2216 ss->rx_small.fill_cnt = ss->rx_small.cnt;
b53bef84
BG		 2217 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2218 int idx = i & ss->rx_small.mask;
2219 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2220 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2221 put_page(ss->rx_small.info[idx].page);
0da34b6d 2222 }
c7dab99b 2223
b53bef84 2224 kfree(ss->rx_big.info);
0da34b6d
BG		 2225
2226abort_with_rx_small_info:
b53bef84 2227 kfree(ss->rx_small.info);
0da34b6d
BG		 2228
2229abort_with_tx_info:
b53bef84 2230 kfree(ss->tx.info);
0da34b6d
BG		 2231
2232abort_with_rx_big_shadow:
b53bef84 2233 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2234
2235abort_with_rx_small_shadow:
b53bef84 2236 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2237
2238abort_with_tx_req_bytes:
b53bef84
BG		 2239 kfree(ss->tx.req_bytes);
2240 ss->tx.req_bytes = NULL;
2241 ss->tx.req_list = NULL;
0da34b6d
BG		 2242
2243abort_with_nothing:
2244 return status;
2245}
2246
b53bef84 2247static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2248{
b53bef84 2249 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2250 struct sk_buff *skb;
2251 struct myri10ge_tx_buf *tx;
2252 int i, len, idx;
2253
0dcffac1
BG		 2254 /* If not allocated, skip it */
2255 if (ss->tx.req_list == NULL)
2256 return;
2257
b53bef84
BG		 2258 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2259 idx = i & ss->rx_big.mask;
2260 if (i == ss->rx_big.fill_cnt - 1)
2261 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2262 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2263 mgp->big_bytes);
b53bef84 2264 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2265 }
2266
4b47638a
JM		 2267 if (mgp->small_bytes == 0)
2268 ss->rx_small.fill_cnt = ss->rx_small.cnt;
b53bef84
BG		 2269 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2270 idx = i & ss->rx_small.mask;
2271 if (i == ss->rx_small.fill_cnt - 1)
2272 ss->rx_small.info[idx].page_offset =
c7dab99b 2273 MYRI10GE_ALLOC_SIZE;
b53bef84 2274 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2275 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2276 put_page(ss->rx_small.info[idx].page);
c7dab99b 2277 }
b53bef84 2278 tx = &ss->tx;
0da34b6d
BG		 2279 while (tx->done != tx->req) {
2280 idx = tx->done & tx->mask;
2281 skb = tx->info[idx].skb;
2282
2283 /* Mark as free */
2284 tx->info[idx].skb = NULL;
2285 tx->done++;
c755b4b6
FT		 2286 len = dma_unmap_len(&tx->info[idx], len);
2287 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 2288 if (skb) {
b53bef84 2289 ss->stats.tx_dropped++;
0da34b6d
BG		 2290 dev_kfree_skb_any(skb);
2291 if (len)
2292 pci_unmap_single(mgp->pdev,
c755b4b6 2293 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2294 bus), len,
2295 PCI_DMA_TODEVICE);
2296 } else {
2297 if (len)
2298 pci_unmap_page(mgp->pdev,
c755b4b6 2299 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2300 bus), len,
2301 PCI_DMA_TODEVICE);
2302 }
2303 }
b53bef84 2304 kfree(ss->rx_big.info);
0da34b6d 2305
b53bef84 2306 kfree(ss->rx_small.info);
0da34b6d 2307
b53bef84 2308 kfree(ss->tx.info);
0da34b6d 2309
b53bef84 2310 kfree(ss->rx_big.shadow);
0da34b6d 2311
b53bef84 2312 kfree(ss->rx_small.shadow);
0da34b6d 2313
b53bef84
BG		 2314 kfree(ss->tx.req_bytes);
2315 ss->tx.req_bytes = NULL;
2316 ss->tx.req_list = NULL;
0da34b6d
BG		 2317}
2318
df30a740
BG		 2319static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2320{
2321 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2322 struct myri10ge_slice_state *ss;
2323 struct net_device *netdev = mgp->dev;
2324 int i;
df30a740
BG		 2325 int status;
2326
0dcffac1
BG		 2327 mgp->msi_enabled = 0;
2328 mgp->msix_enabled = 0;
2329 status = 0;
df30a740 2330 if (myri10ge_msi) {
0dcffac1 2331 if (mgp->num_slices > 1) {
0729cc0c
AG		 2332 status = pci_enable_msix_range(pdev, mgp->msix_vectors,
2333 mgp->num_slices, mgp->num_slices);
2334 if (status < 0) {
0dcffac1
BG		 2335 dev_err(&pdev->dev,
2336 "Error %d setting up MSI-X\n", status);
2337 return status;
2338 }
0729cc0c 2339 mgp->msix_enabled = 1;
0dcffac1
BG		 2340 }
2341 if (mgp->msix_enabled == 0) {
2342 status = pci_enable_msi(pdev);
2343 if (status != 0) {
2344 dev_err(&pdev->dev,
2345 "Error %d setting up MSI; falling back to xPIC\n",
2346 status);
2347 } else {
2348 mgp->msi_enabled = 1;
2349 }
2350 }
df30a740 2351 }
0dcffac1
BG		 2352 if (mgp->msix_enabled) {
2353 for (i = 0; i < mgp->num_slices; i++) {
2354 ss = &mgp->ss[i];
2355 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2356 "%s:slice-%d", netdev->name, i);
2357 status = request_irq(mgp->msix_vectors[i].vector,
2358 myri10ge_intr, 0, ss->irq_desc,
2359 ss);
2360 if (status != 0) {
2361 dev_err(&pdev->dev,
2362 "slice %d failed to allocate IRQ\n", i);
2363 i--;
2364 while (i >= 0) {
2365 free_irq(mgp->msix_vectors[i].vector,
2366 &mgp->ss[i]);
2367 i--;
2368 }
2369 pci_disable_msix(pdev);
2370 return status;
2371 }
2372 }
2373 } else {
2374 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2375 mgp->dev->name, &mgp->ss[0]);
2376 if (status != 0) {
2377 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2378 if (mgp->msi_enabled)
2379 pci_disable_msi(pdev);
2380 }
df30a740
BG		 2381 }
2382 return status;
2383}
2384
2385static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2386{
2387 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2388 int i;
df30a740 2389
0dcffac1
BG		 2390 if (mgp->msix_enabled) {
2391 for (i = 0; i < mgp->num_slices; i++)
2392 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2393 } else {
2394 free_irq(pdev->irq, &mgp->ss[0]);
2395 }
df30a740
BG		 2396 if (mgp->msi_enabled)
2397 pci_disable_msi(pdev);
0dcffac1
BG		 2398 if (mgp->msix_enabled)
2399 pci_disable_msix(pdev);
df30a740
BG		 2400}
2401
77929732
BG		 2402static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2403{
2404 struct myri10ge_cmd cmd;
2405 struct myri10ge_slice_state *ss;
2406 int status;
2407
2408 ss = &mgp->ss[slice];
236bb5e6
BG		 2409 status = 0;
2410 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2411 cmd.data0 = slice;
2412 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2413 &cmd, 0);
2414 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2415 (mgp->sram + cmd.data0);
2416 }
77929732
BG		 2417 cmd.data0 = slice;
2418 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2419 &cmd, 0);
2420 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2421 (mgp->sram + cmd.data0);
2422
2423 cmd.data0 = slice;
2424 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2425 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2426 (mgp->sram + cmd.data0);
2427
236bb5e6
BG		 2428 ss->tx.send_go = (__iomem __be32 *)
2429 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2430 ss->tx.send_stop = (__iomem __be32 *)
2431 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2432 return status;
2433
2434}
2435
2436static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2437{
2438 struct myri10ge_cmd cmd;
2439 struct myri10ge_slice_state *ss;
2440 int status;
2441
2442 ss = &mgp->ss[slice];
2443 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2444 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2445 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2446 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2447 if (status == -ENOSYS) {
2448 dma_addr_t bus = ss->fw_stats_bus;
2449 if (slice != 0)
2450 return -EINVAL;
2451 bus += offsetof(struct mcp_irq_data, send_done_count);
2452 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2453 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2454 status = myri10ge_send_cmd(mgp,
2455 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2456 &cmd, 0);
2457 /* Firmware cannot support multicast without STATS_DMA_V2 */
2458 mgp->fw_multicast_support = 0;
2459 } else {
2460 mgp->fw_multicast_support = 1;
2461 }
2462 return 0;
2463}
77929732 2464
0da34b6d
BG		 2465static int myri10ge_open(struct net_device *dev)
2466{
0dcffac1 2467 struct myri10ge_slice_state *ss;
b53bef84 2468 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2469 struct myri10ge_cmd cmd;
0dcffac1 2470 int i, status, big_pow2, slice;
59e955ed 2471 u8 __iomem *itable;
0da34b6d 2472
0da34b6d
BG		 2473 if (mgp->running != MYRI10GE_ETH_STOPPED)
2474 return -EBUSY;
2475
2476 mgp->running = MYRI10GE_ETH_STARTING;
2477 status = myri10ge_reset(mgp);
2478 if (status != 0) {
78ca90ea 2479 netdev_err(dev, "failed reset\n");
df30a740 2480 goto abort_with_nothing;
0da34b6d
BG		 2481 }
2482
0dcffac1
BG		 2483 if (mgp->num_slices > 1) {
2484 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2485 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2486 if (mgp->dev->real_num_tx_queues > 1)
2487 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2488 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2489 &cmd, 0);
2490 if (status != 0) {
78ca90ea 2491 netdev_err(dev, "failed to set number of slices\n");
0dcffac1
BG		 2492 goto abort_with_nothing;
2493 }
2494 /* setup the indirection table */
2495 cmd.data0 = mgp->num_slices;
2496 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2497 &cmd, 0);
2498
2499 status |= myri10ge_send_cmd(mgp,
2500 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2501 &cmd, 0);
2502 if (status != 0) {
78ca90ea 2503 netdev_err(dev, "failed to setup rss tables\n");
236bb5e6 2504 goto abort_with_nothing;
0dcffac1
BG		 2505 }
2506
2507 /* just enable an identity mapping */
2508 itable = mgp->sram + cmd.data0;
2509 for (i = 0; i < mgp->num_slices; i++)
2510 __raw_writeb(i, &itable[i]);
2511
2512 cmd.data0 = 1;
2513 cmd.data1 = myri10ge_rss_hash;
2514 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2515 &cmd, 0);
2516 if (status != 0) {
78ca90ea 2517 netdev_err(dev, "failed to enable slices\n");
0dcffac1
BG		 2518 goto abort_with_nothing;
2519 }
2520 }
2521
df30a740
BG		 2522 status = myri10ge_request_irq(mgp);
2523 if (status != 0)
2524 goto abort_with_nothing;
2525
0da34b6d
BG		 2526 /* decide what small buffer size to use. For good TCP rx
2527 * performance, it is important to not receive 1514 byte
2528 * frames into jumbo buffers, as it confuses the socket buffer
2529 * accounting code, leading to drops and erratic performance.
2530 */
2531
2532 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2533 /* enough for a TCP header */
2534 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2535 ? (128 - MXGEFW_PAD)
2536 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2537 else
de3c4507
BG		 2538 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2539 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2540
2541 /* Override the small buffer size? */
4b47638a 2542 if (myri10ge_small_bytes >= 0)
0da34b6d
BG		 2543 mgp->small_bytes = myri10ge_small_bytes;
2544
0da34b6d
BG		 2545 /* Firmware needs the big buff size as a power of 2. Lie and
2546 * tell him the buffer is larger, because we only use 1
2547 * buffer/pkt, and the mtu will prevent overruns.
2548 */
13348bee 2549 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2550 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2551 while (!is_power_of_2(big_pow2))
c7dab99b 2552 big_pow2++;
13348bee 2553 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2554 } else {
2555 big_pow2 = MYRI10GE_ALLOC_SIZE;
2556 mgp->big_bytes = big_pow2;
2557 }
2558
0dcffac1
BG		 2559 /* setup the per-slice data structures */
2560 for (slice = 0; slice < mgp->num_slices; slice++) {
2561 ss = &mgp->ss[slice];
2562
2563 status = myri10ge_get_txrx(mgp, slice);
2564 if (status != 0) {
78ca90ea 2565 netdev_err(dev, "failed to get ring sizes or locations\n");
0dcffac1
BG		 2566 goto abort_with_rings;
2567 }
2568 status = myri10ge_allocate_rings(ss);
2569 if (status != 0)
2570 goto abort_with_rings;
236bb5e6
BG		 2571
2572 /* only firmware which supports multiple TX queues
2573 * supports setting up the tx stats on non-zero
2574 * slices */
2575 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2576 status = myri10ge_set_stats(mgp, slice);
2577 if (status) {
78ca90ea 2578 netdev_err(dev, "Couldn't set stats DMA\n");
0dcffac1
BG		 2579 goto abort_with_rings;
2580 }
2581
0dde8026
HYK		 2582 /* Initialize the slice spinlock and state used for polling */
2583 myri10ge_ss_init_lock(ss);
2584
0dcffac1
BG		 2585 /* must happen prior to any irq */
2586 napi_enable(&(ss)->napi);
2587 }
0da34b6d
BG		 2588
2589 /* now give firmware buffers sizes, and MTU */
2590 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2591 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2592 cmd.data0 = mgp->small_bytes;
2593 status |=
2594 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2595 cmd.data0 = big_pow2;
2596 status |=
2597 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2598 if (status) {
78ca90ea 2599 netdev_err(dev, "Couldn't set buffer sizes\n");
0da34b6d
BG		 2600 goto abort_with_rings;
2601 }
2602
0dcffac1
BG		 2603 /*
2604 * Set Linux style TSO mode; this is needed only on newer
2605 * firmware versions. Older versions default to Linux
2606 * style TSO
2607 */
2608 cmd.data0 = 0;
2609 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2610 if (status && status != -ENOSYS) {
78ca90ea 2611 netdev_err(dev, "Couldn't set TSO mode\n");
0da34b6d
BG		 2612 goto abort_with_rings;
2613 }
2614
66341fff 2615 mgp->link_state = ~0U;
0da34b6d
BG		 2616 mgp->rdma_tags_available = 15;
2617
0da34b6d
BG		 2618 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2619 if (status) {
78ca90ea 2620 netdev_err(dev, "Couldn't bring up link\n");
0da34b6d
BG		 2621 goto abort_with_rings;
2622 }
2623
0da34b6d
BG		 2624 mgp->running = MYRI10GE_ETH_RUNNING;
2625 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2626 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2627 netif_tx_wake_all_queues(dev);
2628
0da34b6d
BG		 2629 return 0;
2630
2631abort_with_rings:
051d36f3
BG		 2632 while (slice) {
2633 slice--;
2634 napi_disable(&mgp->ss[slice].napi);
2635 }
0dcffac1
BG		 2636 for (i = 0; i < mgp->num_slices; i++)
2637 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2638
df30a740
BG		 2639 myri10ge_free_irq(mgp);
2640
0da34b6d
BG		 2641abort_with_nothing:
2642 mgp->running = MYRI10GE_ETH_STOPPED;
2643 return -ENOMEM;
2644}
2645
2646static int myri10ge_close(struct net_device *dev)
2647{
b53bef84 2648 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2649 struct myri10ge_cmd cmd;
2650 int status, old_down_cnt;
0dcffac1 2651 int i;
0da34b6d 2652
0da34b6d
BG		 2653 if (mgp->running != MYRI10GE_ETH_RUNNING)
2654 return 0;
2655
0dcffac1 2656 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2657 return 0;
2658
2659 del_timer_sync(&mgp->watchdog_timer);
2660 mgp->running = MYRI10GE_ETH_STOPPING;
0dde8026 2661 local_bh_disable(); /* myri10ge_ss_lock_napi needs bh disabled */
0dcffac1
BG		 2662 for (i = 0; i < mgp->num_slices; i++) {
2663 napi_disable(&mgp->ss[i].napi);
0dde8026
HYK		 2664 /* Lock the slice to prevent the busy_poll handler from
2665 * accessing it. Later when we bring the NIC up, myri10ge_open
2666 * resets the slice including this lock.
2667 */
2668 while (!myri10ge_ss_lock_napi(&mgp->ss[i])) {
2669 pr_info("Slice %d locked\n", i);
2670 mdelay(1);
2671 }
0dcffac1 2672 }
0dde8026 2673 local_bh_enable();
0da34b6d 2674 netif_carrier_off(dev);
236bb5e6
BG		 2675
2676 netif_tx_stop_all_queues(dev);
d0234215
BG		 2677 if (mgp->rebooted == 0) {
2678 old_down_cnt = mgp->down_cnt;
2679 mb();
2680 status =
2681 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2682 if (status)
78ca90ea 2683 netdev_err(dev, "Couldn't bring down link\n");
0da34b6d 2684
d0234215
BG		 2685 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2686 HZ);
2687 if (old_down_cnt == mgp->down_cnt)
78ca90ea 2688 netdev_err(dev, "never got down irq\n");
d0234215 2689 }
0da34b6d 2690 netif_tx_disable(dev);
df30a740 2691 myri10ge_free_irq(mgp);
0dcffac1
BG		 2692 for (i = 0; i < mgp->num_slices; i++)
2693 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2694
2695 mgp->running = MYRI10GE_ETH_STOPPED;
2696 return 0;
2697}
2698
2699/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2700 * backwards one at a time and handle ring wraps */
2701
2702static inline void
2703myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2704 struct mcp_kreq_ether_send *src, int cnt)
2705{
2706 int idx, starting_slot;
2707 starting_slot = tx->req;
2708 while (cnt > 1) {
2709 cnt--;
2710 idx = (starting_slot + cnt) & tx->mask;
2711 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2712 mb();
2713 }
2714}
2715
2716/*
2717 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2718 * at most 32 bytes at a time, so as to avoid involving the software
2719 * pio handler in the nic. We re-write the first segment's flags
2720 * to mark them valid only after writing the entire chain.
2721 */
2722
2723static inline void
2724myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2725 int cnt)
2726{
2727 int idx, i;
2728 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2729 struct mcp_kreq_ether_send *srcp;
2730 u8 last_flags;
2731
2732 idx = tx->req & tx->mask;
2733
2734 last_flags = src->flags;
2735 src->flags = 0;
2736 mb();
2737 dst = dstp = &tx->lanai[idx];
2738 srcp = src;
2739
2740 if ((idx + cnt) < tx->mask) {
2741 for (i = 0; i < (cnt - 1); i += 2) {
2742 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2743 mb(); /* force write every 32 bytes */
2744 srcp += 2;
2745 dstp += 2;
2746 }
2747 } else {
2748 /* submit all but the first request, and ensure
2749 * that it is submitted below */
2750 myri10ge_submit_req_backwards(tx, src, cnt);
2751 i = 0;
2752 }
2753 if (i < cnt) {
2754 /* submit the first request */
2755 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2756 mb(); /* barrier before setting valid flag */
2757 }
2758
2759 /* re-write the last 32-bits with the valid flags */
2760 src->flags = last_flags;
40f6cff5 2761 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2762 tx->req += cnt;
2763 mb();
2764}
2765
0da34b6d
BG		 2766/*
2767 * Transmit a packet. We need to split the packet so that a single
b53bef84 2768 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2769 * counting tricky. So rather than try to count segments up front, we
2770 * just give up if there are too few segments to hold a reasonably
2771 * fragmented packet currently available. If we run
2772 * out of segments while preparing a packet for DMA, we just linearize
2773 * it and try again.
2774 */
2775
61357325
SH		 2776static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2777 struct net_device *dev)
0da34b6d
BG		 2778{
2779 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2780 struct myri10ge_slice_state *ss;
0da34b6d 2781 struct mcp_kreq_ether_send *req;
b53bef84 2782 struct myri10ge_tx_buf *tx;
0da34b6d 2783 struct skb_frag_struct *frag;
236bb5e6 2784 struct netdev_queue *netdev_queue;
0da34b6d 2785 dma_addr_t bus;
40f6cff5
AV		 2786 u32 low;
2787 __be32 high_swapped;
0da34b6d
BG		 2788 unsigned int len;
2789 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2790 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2791 int cum_len, seglen, boundary, rdma_count;
2792 u8 flags, odd_flag;
2793
236bb5e6 2794 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2795 ss = &mgp->ss[queue];
2796 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2797 tx = &ss->tx;
236bb5e6 2798
0da34b6d
BG		 2799again:
2800 req = tx->req_list;
2801 avail = tx->mask - 1 - (tx->req - tx->done);
2802
2803 mss = 0;
2804 max_segments = MXGEFW_MAX_SEND_DESC;
2805
917690cd 2806 if (skb_is_gso(skb)) {
7967168c 2807 mss = skb_shinfo(skb)->gso_size;
917690cd 2808 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2809 }
0da34b6d
BG		 2810
2811 if ((unlikely(avail < max_segments))) {
2812 /* we are out of transmit resources */
b53bef84 2813 tx->stop_queue++;
236bb5e6 2814 netif_tx_stop_queue(netdev_queue);
5b548140 2815 return NETDEV_TX_BUSY;
0da34b6d
BG		 2816 }
2817
2818 /* Setup checksum offloading, if needed */
2819 cksum_offset = 0;
2820 pseudo_hdr_offset = 0;
2821 odd_flag = 0;
2822 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2823 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0d0b1672 2824 cksum_offset = skb_checksum_start_offset(skb);
ff1dcadb 2825 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2826 /* If the headers are excessively large, then we must
2827 * fall back to a software checksum */
4f93fde0
BG		 2828 if (unlikely(!mss && (cksum_offset > 255 ||
2829 pseudo_hdr_offset > 127))) {
84fa7933 2830 if (skb_checksum_help(skb))
0da34b6d
BG		 2831 goto drop;
2832 cksum_offset = 0;
2833 pseudo_hdr_offset = 0;
2834 } else {
0da34b6d
BG		 2835 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2836 flags |= MXGEFW_FLAGS_CKSUM;
2837 }
2838 }
2839
2840 cum_len = 0;
2841
0da34b6d
BG		 2842 if (mss) { /* TSO */
2843 /* this removes any CKSUM flag from before */
2844 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2845
2846 /* negative cum_len signifies to the
2847 * send loop that we are still in the
2848 * header portion of the TSO packet.
4f93fde0 2849 * TSO header can be at most 1KB long */
ab6a5bb6 2850 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2851
4f93fde0
BG		 2852 /* for IPv6 TSO, the checksum offset stores the
2853 * TCP header length, to save the firmware from
2854 * the need to parse the headers */
2855 if (skb_is_gso_v6(skb)) {
2856 cksum_offset = tcp_hdrlen(skb);
2857 /* Can only handle headers <= max_tso6 long */
2858 if (unlikely(-cum_len > mgp->max_tso6))
2859 return myri10ge_sw_tso(skb, dev);
2860 }
0da34b6d
BG		 2861 /* for TSO, pseudo_hdr_offset holds mss.
2862 * The firmware figures out where to put
2863 * the checksum by parsing the header. */
40f6cff5 2864 pseudo_hdr_offset = mss;
0da34b6d 2865 } else
0da34b6d
BG		 2866 /* Mark small packets, and pad out tiny packets */
2867 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2868 flags |= MXGEFW_FLAGS_SMALL;
2869
2870 /* pad frames to at least ETH_ZLEN bytes */
2871 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2872 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2873 /* The packet is gone, so we must
2874 * return 0 */
b53bef84 2875 ss->stats.tx_dropped += 1;
6ed10654 2876 return NETDEV_TX_OK;
0da34b6d
BG		 2877 }
2878 /* adjust the len to account for the zero pad
2879 * so that the nic can know how long it is */
2880 skb->len = ETH_ZLEN;
2881 }
2882 }
2883
2884 /* map the skb for DMA */
e743d313 2885 len = skb_headlen(skb);
0da34b6d
BG		 2886 idx = tx->req & tx->mask;
2887 tx->info[idx].skb = skb;
2888 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
c755b4b6
FT		 2889 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2890 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2891
2892 frag_cnt = skb_shinfo(skb)->nr_frags;
2893 frag_idx = 0;
2894 count = 0;
2895 rdma_count = 0;
2896
2897 /* "rdma_count" is the number of RDMAs belonging to the
2898 * current packet BEFORE the current send request. For
2899 * non-TSO packets, this is equal to "count".
2900 * For TSO packets, rdma_count needs to be reset
2901 * to 0 after a segment cut.
2902 *
2903 * The rdma_count field of the send request is
2904 * the number of RDMAs of the packet starting at
2905 * that request. For TSO send requests with one ore more cuts
2906 * in the middle, this is the number of RDMAs starting
2907 * after the last cut in the request. All previous
2908 * segments before the last cut implicitly have 1 RDMA.
2909 *
2910 * Since the number of RDMAs is not known beforehand,
2911 * it must be filled-in retroactively - after each
2912 * segmentation cut or at the end of the entire packet.
2913 */
2914
2915 while (1) {
2916 /* Break the SKB or Fragment up into pieces which
b53bef84 2917 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2918 low = MYRI10GE_LOWPART_TO_U32(bus);
2919 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2920 while (len) {
2921 u8 flags_next;
2922 int cum_len_next;
2923
2924 if (unlikely(count == max_segments))
2925 goto abort_linearize;
2926
b53bef84
BG		 2927 boundary =
2928 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2929 seglen = boundary - low;
2930 if (seglen > len)
2931 seglen = len;
2932 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2933 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2934 if (mss) { /* TSO */
2935 (req - rdma_count)->rdma_count = rdma_count + 1;
2936
2937 if (likely(cum_len >= 0)) { /* payload */
2938 int next_is_first, chop;
2939
2940 chop = (cum_len_next > mss);
2941 cum_len_next = cum_len_next % mss;
2942 next_is_first = (cum_len_next == 0);
2943 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2944 flags_next |= next_is_first *
2945 MXGEFW_FLAGS_FIRST;
2946 rdma_count |= -(chop | next_is_first);
59e955ed 2947 rdma_count += chop & ~next_is_first;
0da34b6d
BG		 2948 } else if (likely(cum_len_next >= 0)) { /* header ends */
2949 int small;
2950
2951 rdma_count = -1;
2952 cum_len_next = 0;
2953 seglen = -cum_len;
2954 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2955 flags_next = MXGEFW_FLAGS_TSO_PLD |
2956 MXGEFW_FLAGS_FIRST |
2957 (small * MXGEFW_FLAGS_SMALL);
2958 }
2959 }
0da34b6d
BG		 2960 req->addr_high = high_swapped;
2961 req->addr_low = htonl(low);
40f6cff5 2962 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2963 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2964 req->rdma_count = 1;
2965 req->length = htons(seglen);
2966 req->cksum_offset = cksum_offset;
2967 req->flags = flags | ((cum_len & 1) * odd_flag);
2968
2969 low += seglen;
2970 len -= seglen;
2971 cum_len = cum_len_next;
2972 flags = flags_next;
2973 req++;
2974 count++;
2975 rdma_count++;
4f93fde0
BG		 2976 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2977 if (unlikely(cksum_offset > seglen))
2978 cksum_offset -= seglen;
2979 else
2980 cksum_offset = 0;
2981 }
0da34b6d
BG		 2982 }
2983 if (frag_idx == frag_cnt)
2984 break;
2985
2986 /* map next fragment for DMA */
2987 idx = (count + tx->req) & tx->mask;
2988 frag = &skb_shinfo(skb)->frags[frag_idx];
2989 frag_idx++;
9e903e08 2990 len = skb_frag_size(frag);
5dc3e196 2991 bus = skb_frag_dma_map(&mgp->pdev->dev, frag, 0, len,
5d6bcdfe 2992 DMA_TO_DEVICE);
c755b4b6
FT		 2993 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2994 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2995 }
2996
2997 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2998 if (mss)
2999 do {
3000 req--;
3001 req->flags |= MXGEFW_FLAGS_TSO_LAST;
3002 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
3003 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 3004 idx = ((count - 1) + tx->req) & tx->mask;
3005 tx->info[idx].last = 1;
e454e7e2 3006 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 3007 /* if using multiple tx queues, make sure NIC polls the
3008 * current slice */
3009 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
3010 tx->queue_active = 1;
3011 put_be32(htonl(1), tx->send_go);
8c2f5fa5 3012 mb();
6824a105 3013 mmiowb();
236bb5e6 3014 }
0da34b6d
BG		 3015 tx->pkt_start++;
3016 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 3017 tx->stop_queue++;
236bb5e6 3018 netif_tx_stop_queue(netdev_queue);
0da34b6d 3019 }
6ed10654 3020 return NETDEV_TX_OK;
0da34b6d
BG		 3021
3022abort_linearize:
3023 /* Free any DMA resources we've alloced and clear out the skb
3024 * slot so as to not trip up assertions, and to avoid a
3025 * double-free if linearizing fails */
3026
3027 last_idx = (idx + 1) & tx->mask;
3028 idx = tx->req & tx->mask;
3029 tx->info[idx].skb = NULL;
3030 do {
c755b4b6 3031 len = dma_unmap_len(&tx->info[idx], len);
0da34b6d
BG		 3032 if (len) {
3033 if (tx->info[idx].skb != NULL)
3034 pci_unmap_single(mgp->pdev,
c755b4b6 3035 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 3036 bus), len,
3037 PCI_DMA_TODEVICE);
3038 else
3039 pci_unmap_page(mgp->pdev,
c755b4b6 3040 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 3041 bus), len,
3042 PCI_DMA_TODEVICE);
c755b4b6 3043 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d
BG		 3044 tx->info[idx].skb = NULL;
3045 }
3046 idx = (idx + 1) & tx->mask;
3047 } while (idx != last_idx);
89114afd 3048 if (skb_is_gso(skb)) {
78ca90ea 3049 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
0da34b6d
BG		 3050 goto drop;
3051 }
3052
bec0e859 3053 if (skb_linearize(skb))
0da34b6d
BG		 3054 goto drop;
3055
b53bef84 3056 tx->linearized++;
0da34b6d
BG		 3057 goto again;
3058
3059drop:
3060 dev_kfree_skb_any(skb);
b53bef84 3061 ss->stats.tx_dropped += 1;
6ed10654 3062 return NETDEV_TX_OK;
0da34b6d
BG		 3063
3064}
3065
61357325
SH		 3066static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
3067 struct net_device *dev)
4f93fde0
BG		 3068{
3069 struct sk_buff *segs, *curr;
b53bef84 3070 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 3071 struct myri10ge_slice_state *ss;
61357325 3072 netdev_tx_t status;
4f93fde0
BG		 3073
3074 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 3075 if (IS_ERR(segs))
4f93fde0
BG		 3076 goto drop;
3077
3078 while (segs) {
3079 curr = segs;
3080 segs = segs->next;
3081 curr->next = NULL;
3082 status = myri10ge_xmit(curr, dev);
3083 if (status != 0) {
3084 dev_kfree_skb_any(curr);
3085 if (segs != NULL) {
3086 curr = segs;
3087 segs = segs->next;
3088 curr->next = NULL;
3089 dev_kfree_skb_any(segs);
3090 }
3091 goto drop;
3092 }
3093 }
3094 dev_kfree_skb_any(skb);
ec634fe3 3095 return NETDEV_TX_OK;
4f93fde0
BG		 3096
3097drop:
d6279c88 3098 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 3099 dev_kfree_skb_any(skb);
d6279c88 3100 ss->stats.tx_dropped += 1;
ec634fe3 3101 return NETDEV_TX_OK;
4f93fde0
BG		 3102}
3103
c5f7ef72 3104static struct rtnl_link_stats64 *myri10ge_get_stats(struct net_device *dev,
3105 struct rtnl_link_stats64 *stats)
0da34b6d 3106{
306ff6eb
ED		 3107 const struct myri10ge_priv *mgp = netdev_priv(dev);
3108 const struct myri10ge_slice_netstats *slice_stats;
0dcffac1
BG		 3109 int i;
3110
0dcffac1
BG		 3111 for (i = 0; i < mgp->num_slices; i++) {
3112 slice_stats = &mgp->ss[i].stats;
3113 stats->rx_packets += slice_stats->rx_packets;
3114 stats->tx_packets += slice_stats->tx_packets;
3115 stats->rx_bytes += slice_stats->rx_bytes;
3116 stats->tx_bytes += slice_stats->tx_bytes;
3117 stats->rx_dropped += slice_stats->rx_dropped;
3118 stats->tx_dropped += slice_stats->tx_dropped;
3119 }
3120 return stats;
0da34b6d
BG		 3121}
3122
3123static void myri10ge_set_multicast_list(struct net_device *dev)
3124{
b53bef84 3125 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 3126 struct myri10ge_cmd cmd;
22bedad3 3127 struct netdev_hw_addr *ha;
6250223e 3128 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 3129 int err;
3130
0da34b6d
BG		 3131 /* can be called from atomic contexts,
3132 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 3133 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3134
3135 /* This firmware is known to not support multicast */
2f76216f 3136 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 3137 return;
3138
3139 /* Disable multicast filtering */
3140
3141 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3142 if (err != 0) {
78ca90ea
JP		 3143 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3144 err);
85a7ea1b
BG		 3145 goto abort;
3146 }
3147
2f76216f 3148 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3149 /* request to disable multicast filtering, so quit here */
3150 return;
3151 }
3152
3153 /* Flush the filters */
3154
3155 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3156 &cmd, 1);
3157 if (err != 0) {
78ca90ea
JP		 3158 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3159 err);
85a7ea1b
BG		 3160 goto abort;
3161 }
3162
3163 /* Walk the multicast list, and add each address */
22bedad3 3164 netdev_for_each_mc_addr(ha, dev) {
d458cdf7 3165 memcpy(data, &ha->addr, ETH_ALEN);
40f6cff5
AV		 3166 cmd.data0 = ntohl(data[0]);
3167 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3168 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3169 &cmd, 1);
3170
3171 if (err != 0) {
78ca90ea 3172 netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
22bedad3 3173 err, ha->addr);
85a7ea1b
BG		 3174 goto abort;
3175 }
3176 }
3177 /* Enable multicast filtering */
3178 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3179 if (err != 0) {
78ca90ea
JP		 3180 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3181 err);
85a7ea1b
BG		 3182 goto abort;
3183 }
3184
3185 return;
3186
3187abort:
3188 return;
0da34b6d
BG		 3189}
3190
3191static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3192{
3193 struct sockaddr *sa = addr;
3194 struct myri10ge_priv *mgp = netdev_priv(dev);
3195 int status;
3196
3197 if (!is_valid_ether_addr(sa->sa_data))
3198 return -EADDRNOTAVAIL;
3199
3200 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3201 if (status != 0) {
78ca90ea
JP		 3202 netdev_err(dev, "changing mac address failed with %d\n",
3203 status);
0da34b6d
BG		 3204 return status;
3205 }
3206
3207 /* change the dev structure */
d458cdf7 3208 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
0da34b6d
BG		 3209 return 0;
3210}
3211
3212static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3213{
3214 struct myri10ge_priv *mgp = netdev_priv(dev);
3215 int error = 0;
3216
3217 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
78ca90ea 3218 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
0da34b6d
BG		 3219 return -EINVAL;
3220 }
78ca90ea 3221 netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
0da34b6d
BG		 3222 if (mgp->running) {
3223 /* if we change the mtu on an active device, we must
3224 * reset the device so the firmware sees the change */
3225 myri10ge_close(dev);
3226 dev->mtu = new_mtu;
3227 myri10ge_open(dev);
3228 } else
3229 dev->mtu = new_mtu;
3230
3231 return error;
3232}
3233
3234/*
3235 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3236 * Only do it if the bridge is a root port since we don't want to disturb
3237 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3238 */
3239
0da34b6d
BG		 3240static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3241{
3242 struct pci_dev *bridge = mgp->pdev->bus->self;
3243 struct device *dev = &mgp->pdev->dev;
effd1eda 3244 int cap;
0da34b6d 3245 unsigned err_cap;
0da34b6d
BG		 3246 int ret;
3247
3248 if (!myri10ge_ecrc_enable || !bridge)
3249 return;
3250
3251 /* check that the bridge is a root port */
9503e255 3252 if (pci_pcie_type(bridge) != PCI_EXP_TYPE_ROOT_PORT) {
0da34b6d 3253 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3254 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3255
3256 /* Walk the hierarchy up to the root port
3257 * where ECRC has to be enabled */
3258 do {
eca3fd83 3259 prev_bridge = bridge;
0da34b6d 3260 bridge = bridge->bus->self;
eca3fd83 3261 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3262 dev_err(dev,
3263 "Failed to find root port"
3264 " to force ECRC\n");
3265 return;
3266 }
9503e255
JL		 3267 } while (pci_pcie_type(bridge) !=
3268 PCI_EXP_TYPE_ROOT_PORT);
0da34b6d
BG		 3269
3270 dev_info(dev,
3271 "Forcing ECRC on non-root port %s"
3272 " (enabling on root port %s)\n",
3273 pci_name(old_bridge), pci_name(bridge));
3274 } else {
3275 dev_err(dev,
3276 "Not enabling ECRC on non-root port %s\n",
3277 pci_name(bridge));
3278 return;
3279 }
3280 }
3281
3282 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3283 if (!cap)
3284 return;
3285
3286 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3287 if (ret) {
3288 dev_err(dev, "failed reading ext-conf-space of %s\n",
3289 pci_name(bridge));
3290 dev_err(dev, "\t pci=nommconf in use? "
3291 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3292 return;
3293 }
3294 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3295 return;
3296
3297 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3298 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3299 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3300}
3301
3302/*
3303 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3304 * when the PCI-E Completion packets are aligned on an 8-byte
3305 * boundary. Some PCI-E chip sets always align Completion packets; on
3306 * the ones that do not, the alignment can be enforced by enabling
3307 * ECRC generation (if supported).
3308 *
3309 * When PCI-E Completion packets are not aligned, it is actually more
3310 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3311 *
3312 * If the driver can neither enable ECRC nor verify that it has
3313 * already been enabled, then it must use a firmware image which works
0dcffac1 3314 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3315 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3316 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3317 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3318 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3319 */
3320
5443e9ea 3321static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3322{
5443e9ea
BG		 3323 struct pci_dev *pdev = mgp->pdev;
3324 struct device *dev = &pdev->dev;
302d242c 3325 int status;
0da34b6d 3326
b53bef84 3327 mgp->tx_boundary = 4096;
5443e9ea
BG		 3328 /*
3329 * Verify the max read request size was set to 4KB
3330 * before trying the test with 4KB.
3331 */
302d242c
BG		 3332 status = pcie_get_readrq(pdev);
3333 if (status < 0) {
5443e9ea
BG		 3334 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3335 goto abort;
3336 }
302d242c
BG		 3337 if (status != 4096) {
3338 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3339 mgp->tx_boundary = 2048;
5443e9ea
BG		 3340 }
3341 /*
3342 * load the optimized firmware (which assumes aligned PCIe
3343 * completions) in order to see if it works on this host.
3344 */
7d351035 3345 set_fw_name(mgp, myri10ge_fw_aligned, false);
0dcffac1 3346 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3347 if (status != 0) {
3348 goto abort;
3349 }
3350
3351 /*
3352 * Enable ECRC if possible
3353 */
3354 myri10ge_enable_ecrc(mgp);
3355
3356 /*
3357 * Run a DMA test which watches for unaligned completions and
3358 * aborts on the first one seen.
3359 */
3360
3361 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3362 if (status == 0)
3363 return; /* keep the aligned firmware */
3364
3365 if (status != -E2BIG)
3366 dev_warn(dev, "DMA test failed: %d\n", status);
3367 if (status == -ENOSYS)
3368 dev_warn(dev, "Falling back to ethp! "
3369 "Please install up to date fw\n");
3370abort:
3371 /* fall back to using the unaligned firmware */
b53bef84 3372 mgp->tx_boundary = 2048;
7d351035 3373 set_fw_name(mgp, myri10ge_fw_unaligned, false);
5443e9ea
BG		 3374}
3375
3376static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3377{
2d90b0aa
BG		 3378 int overridden = 0;
3379
0da34b6d 3380 if (myri10ge_force_firmware == 0) {
9503e255 3381 int link_width;
ce7f9368
BG		 3382 u16 lnk;
3383
9503e255 3384 pcie_capability_read_word(mgp->pdev, PCI_EXP_LNKSTA, &lnk);
ce7f9368
BG		 3385 link_width = (lnk >> 4) & 0x3f;
3386
ce7f9368
BG		 3387 /* Check to see if Link is less than 8 or if the
3388 * upstream bridge is known to provide aligned
3389 * completions */
3390 if (link_width < 8) {
3391 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3392 link_width);
b53bef84 3393 mgp->tx_boundary = 4096;
7d351035 3394 set_fw_name(mgp, myri10ge_fw_aligned, false);
5443e9ea
BG		 3395 } else {
3396 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3397 }
3398 } else {
3399 if (myri10ge_force_firmware == 1) {
3400 dev_info(&mgp->pdev->dev,
3401 "Assuming aligned completions (forced)\n");
b53bef84 3402 mgp->tx_boundary = 4096;
7d351035 3403 set_fw_name(mgp, myri10ge_fw_aligned, false);
0da34b6d
BG		 3404 } else {
3405 dev_info(&mgp->pdev->dev,
3406 "Assuming unaligned completions (forced)\n");
b53bef84 3407 mgp->tx_boundary = 2048;
7d351035 3408 set_fw_name(mgp, myri10ge_fw_unaligned, false);
0da34b6d
BG		 3409 }
3410 }
7d351035
RR		 3411
3412 kparam_block_sysfs_write(myri10ge_fw_name);
0da34b6d 3413 if (myri10ge_fw_name != NULL) {
7d351035
RR		 3414 char *fw_name = kstrdup(myri10ge_fw_name, GFP_KERNEL);
3415 if (fw_name) {
3416 overridden = 1;
3417 set_fw_name(mgp, fw_name, true);
3418 }
0da34b6d 3419 }
7d351035
RR		 3420 kparam_unblock_sysfs_write(myri10ge_fw_name);
3421
2d90b0aa
BG		 3422 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3423 myri10ge_fw_names[mgp->board_number] != NULL &&
3424 strlen(myri10ge_fw_names[mgp->board_number])) {
7d351035 3425 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
2d90b0aa
BG		 3426 overridden = 1;
3427 }
3428 if (overridden)
3429 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3430 mgp->fw_name);
0da34b6d
BG		 3431}
3432
7539a613
JM		 3433static void myri10ge_mask_surprise_down(struct pci_dev *pdev)
3434{
3435 struct pci_dev *bridge = pdev->bus->self;
3436 int cap;
3437 u32 mask;
3438
3439 if (bridge == NULL)
3440 return;
3441
3442 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3443 if (cap) {
3444 /* a sram parity error can cause a surprise link
3445 * down; since we expect and can recover from sram
3446 * parity errors, mask surprise link down events */
3447 pci_read_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, &mask);
3448 mask |= 0x20;
3449 pci_write_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, mask);
3450 }
3451}
3452
0da34b6d 3453#ifdef CONFIG_PM
0da34b6d
BG		 3454static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3455{
3456 struct myri10ge_priv *mgp;
3457 struct net_device *netdev;
3458
3459 mgp = pci_get_drvdata(pdev);
3460 if (mgp == NULL)
3461 return -EINVAL;
3462 netdev = mgp->dev;
3463
3464 netif_device_detach(netdev);
3465 if (netif_running(netdev)) {
78ca90ea 3466 netdev_info(netdev, "closing\n");
0da34b6d
BG		 3467 rtnl_lock();
3468 myri10ge_close(netdev);
3469 rtnl_unlock();
3470 }
3471 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3472 pci_save_state(pdev);
0da34b6d 3473 pci_disable_device(pdev);
1a63e846
BG		 3474
3475 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3476}
3477
3478static int myri10ge_resume(struct pci_dev *pdev)
3479{
3480 struct myri10ge_priv *mgp;
3481 struct net_device *netdev;
3482 int status;
3483 u16 vendor;
3484
3485 mgp = pci_get_drvdata(pdev);
3486 if (mgp == NULL)
3487 return -EINVAL;
3488 netdev = mgp->dev;
1ca01512 3489 pci_set_power_state(pdev, PCI_D0); /* zeros conf space as a side effect */
0da34b6d
BG		 3490 msleep(5); /* give card time to respond */
3491 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3492 if (vendor == 0xffff) {
78ca90ea 3493 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3494 return -EIO;
3495 }
83f6e152 3496
1d3c16a8 3497 pci_restore_state(pdev);
4c2248cc
BG		 3498
3499 status = pci_enable_device(pdev);
1a63e846 3500 if (status) {
4c2248cc 3501 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3502 return status;
4c2248cc
BG		 3503 }
3504
0da34b6d
BG		 3505 pci_set_master(pdev);
3506
0da34b6d 3507 myri10ge_reset(mgp);
013b68bf 3508 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3509
3510 /* Save configuration space to be restored if the
3511 * nic resets due to a parity error */
83f6e152 3512 pci_save_state(pdev);
0da34b6d
BG		 3513
3514 if (netif_running(netdev)) {
3515 rtnl_lock();
df30a740 3516 status = myri10ge_open(netdev);
0da34b6d 3517 rtnl_unlock();
df30a740
BG		 3518 if (status != 0)
3519 goto abort_with_enabled;
3520
0da34b6d
BG		 3521 }
3522 netif_device_attach(netdev);
3523
3524 return 0;
3525
4c2248cc
BG		 3526abort_with_enabled:
3527 pci_disable_device(pdev);
0da34b6d
BG		 3528 return -EIO;
3529
3530}
0da34b6d
BG		 3531#endif /* CONFIG_PM */
3532
3533static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3534{
3535 struct pci_dev *pdev = mgp->pdev;
3536 int vs = mgp->vendor_specific_offset;
3537 u32 reboot;
3538
3539 /*enter read32 mode */
3540 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3541
3542 /*read REBOOT_STATUS (0xfffffff0) */
3543 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3544 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3545 return reboot;
3546}
3547
c689b81b
JM		 3548static void
3549myri10ge_check_slice(struct myri10ge_slice_state *ss, int *reset_needed,
3550 int *busy_slice_cnt, u32 rx_pause_cnt)
3551{
3552 struct myri10ge_priv *mgp = ss->mgp;
3553 int slice = ss - mgp->ss;
3554
3555 if (ss->tx.req != ss->tx.done &&
3556 ss->tx.done == ss->watchdog_tx_done &&
3557 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3558 /* nic seems like it might be stuck.. */
3559 if (rx_pause_cnt != mgp->watchdog_pause) {
3560 if (net_ratelimit())
3561 netdev_warn(mgp->dev, "slice %d: TX paused, "
3562 "check link partner\n", slice);
3563 } else {
3564 netdev_warn(mgp->dev,
3565 "slice %d: TX stuck %d %d %d %d %d %d\n",
3566 slice, ss->tx.queue_active, ss->tx.req,
3567 ss->tx.done, ss->tx.pkt_start,
3568 ss->tx.pkt_done,
3569 (int)ntohl(mgp->ss[slice].fw_stats->
3570 send_done_count));
3571 *reset_needed = 1;
3572 ss->stuck = 1;
3573 }
3574 }
3575 if (ss->watchdog_tx_done != ss->tx.done ||
3576 ss->watchdog_rx_done != ss->rx_done.cnt) {
3577 *busy_slice_cnt += 1;
3578 }
3579 ss->watchdog_tx_done = ss->tx.done;
3580 ss->watchdog_tx_req = ss->tx.req;
3581 ss->watchdog_rx_done = ss->rx_done.cnt;
3582}
3583
0da34b6d
BG		 3584/*
3585 * This watchdog is used to check whether the board has suffered
3586 * from a parity error and needs to be recovered.
3587 */
c4028958 3588static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3589{
c4028958 3590 struct myri10ge_priv *mgp =
6250223e 3591 container_of(work, struct myri10ge_priv, watchdog_work);
c689b81b
JM		 3592 struct myri10ge_slice_state *ss;
3593 u32 reboot, rx_pause_cnt;
d0234215 3594 int status, rebooted;
0dcffac1 3595 int i;
c689b81b
JM		 3596 int reset_needed = 0;
3597 int busy_slice_cnt = 0;
0da34b6d
BG		 3598 u16 cmd, vendor;
3599
3600 mgp->watchdog_resets++;
3601 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
d0234215 3602 rebooted = 0;
0da34b6d
BG		 3603 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3604 /* Bus master DMA disabled? Check to see
3605 * if the card rebooted due to a parity error
3606 * For now, just report it */
3607 reboot = myri10ge_read_reboot(mgp);
78ca90ea 3608 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
c689b81b 3609 reboot, myri10ge_reset_recover ? "" : " not");
f181137f
BG		 3610 if (myri10ge_reset_recover == 0)
3611 return;
d0234215
BG		 3612 rtnl_lock();
3613 mgp->rebooted = 1;
3614 rebooted = 1;
3615 myri10ge_close(mgp->dev);
f181137f 3616 myri10ge_reset_recover--;
d0234215 3617 mgp->rebooted = 0;
0da34b6d
BG		 3618 /*
3619 * A rebooted nic will come back with config space as
3620 * it was after power was applied to PCIe bus.
3621 * Attempt to restore config space which was saved
3622 * when the driver was loaded, or the last time the
3623 * nic was resumed from power saving mode.
3624 */
83f6e152 3625 pci_restore_state(mgp->pdev);
7adda30c
BG		 3626
3627 /* save state again for accounting reasons */
83f6e152 3628 pci_save_state(mgp->pdev);
7adda30c 3629
0da34b6d
BG		 3630 } else {
3631 /* if we get back -1's from our slot, perhaps somebody
3632 * powered off our card. Don't try to reset it in
3633 * this case */
3634 if (cmd == 0xffff) {
3635 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3636 if (vendor == 0xffff) {
78ca90ea 3637 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3638 return;
3639 }
3640 }
c689b81b
JM		 3641 /* Perhaps it is a software error. See if stuck slice
3642 * has recovered, reset if not */
3643 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
0dcffac1 3644 for (i = 0; i < mgp->num_slices; i++) {
c689b81b
JM		 3645 ss = mgp->ss;
3646 if (ss->stuck) {
3647 myri10ge_check_slice(ss, &reset_needed,
3648 &busy_slice_cnt,
3649 rx_pause_cnt);
3650 ss->stuck = 0;
3651 }
0dcffac1 3652 }
c689b81b
JM		 3653 if (!reset_needed) {
3654 netdev_dbg(mgp->dev, "not resetting\n");
3655 return;
3656 }
3657
3658 netdev_err(mgp->dev, "device timeout, resetting\n");
0da34b6d 3659 }
236bb5e6 3660
d0234215
BG		 3661 if (!rebooted) {
3662 rtnl_lock();
3663 myri10ge_close(mgp->dev);
3664 }
0dcffac1 3665 status = myri10ge_load_firmware(mgp, 1);
0da34b6d 3666 if (status != 0)
78ca90ea 3667 netdev_err(mgp->dev, "failed to load firmware\n");
0da34b6d
BG		 3668 else
3669 myri10ge_open(mgp->dev);
3670 rtnl_unlock();
3671}
3672
3673/*
3674 * We use our own timer routine rather than relying upon
3675 * netdev->tx_timeout because we have a very large hardware transmit
3676 * queue. Due to the large queue, the netdev->tx_timeout function
3677 * cannot detect a NIC with a parity error in a timely fashion if the
3678 * NIC is lightly loaded.
3679 */
3680static void myri10ge_watchdog_timer(unsigned long arg)
3681{
3682 struct myri10ge_priv *mgp;
b53bef84 3683 struct myri10ge_slice_state *ss;
d0234215 3684 int i, reset_needed, busy_slice_cnt;
626fda94 3685 u32 rx_pause_cnt;
d0234215 3686 u16 cmd;
0da34b6d
BG		 3687
3688 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3689
0dcffac1 3690 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
d0234215 3691 busy_slice_cnt = 0;
0dcffac1
BG		 3692 for (i = 0, reset_needed = 0;
3693 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3694
0dcffac1
BG		 3695 ss = &mgp->ss[i];
3696 if (ss->rx_small.watchdog_needed) {
3697 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3698 mgp->small_bytes + MXGEFW_PAD,
3699 1);
3700 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3701 myri10ge_fill_thresh)
3702 ss->rx_small.watchdog_needed = 0;
3703 }
3704 if (ss->rx_big.watchdog_needed) {
3705 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3706 mgp->big_bytes, 1);
3707 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3708 myri10ge_fill_thresh)
3709 ss->rx_big.watchdog_needed = 0;
3710 }
c689b81b
JM		 3711 myri10ge_check_slice(ss, &reset_needed, &busy_slice_cnt,
3712 rx_pause_cnt);
d0234215
BG		 3713 }
3714 /* if we've sent or received no traffic, poll the NIC to
3715 * ensure it is still there. Otherwise, we risk not noticing
3716 * an error in a timely fashion */
3717 if (busy_slice_cnt == 0) {
3718 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3719 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3720 reset_needed = 1;
3721 }
626fda94 3722 }
626fda94 3723 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3724
3725 if (reset_needed) {
3726 schedule_work(&mgp->watchdog_work);
3727 } else {
3728 /* rearm timer */
3729 mod_timer(&mgp->watchdog_timer,
3730 jiffies + myri10ge_watchdog_timeout * HZ);
3731 }
0da34b6d
BG		 3732}
3733
77929732
BG		 3734static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3735{
3736 struct myri10ge_slice_state *ss;
3737 struct pci_dev *pdev = mgp->pdev;
3738 size_t bytes;
3739 int i;
3740
3741 if (mgp->ss == NULL)
3742 return;
3743
3744 for (i = 0; i < mgp->num_slices; i++) {
3745 ss = &mgp->ss[i];
3746 if (ss->rx_done.entry != NULL) {
3747 bytes = mgp->max_intr_slots *
3748 sizeof(*ss->rx_done.entry);
3749 dma_free_coherent(&pdev->dev, bytes,
3750 ss->rx_done.entry, ss->rx_done.bus);
3751 ss->rx_done.entry = NULL;
3752 }
3753 if (ss->fw_stats != NULL) {
3754 bytes = sizeof(*ss->fw_stats);
3755 dma_free_coherent(&pdev->dev, bytes,
3756 ss->fw_stats, ss->fw_stats_bus);
3757 ss->fw_stats = NULL;
3758 }
0dde8026 3759 napi_hash_del(&ss->napi);
b3b6ae2c 3760 netif_napi_del(&ss->napi);
77929732 3761 }
0dde8026
HYK		 3762 /* Wait till napi structs are no longer used, and then free ss. */
3763 synchronize_rcu();
77929732
BG		 3764 kfree(mgp->ss);
3765 mgp->ss = NULL;
3766}
3767
3768static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3769{
3770 struct myri10ge_slice_state *ss;
3771 struct pci_dev *pdev = mgp->pdev;
3772 size_t bytes;
3773 int i;
3774
3775 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3776 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3777 if (mgp->ss == NULL) {
3778 return -ENOMEM;
3779 }
3780
3781 for (i = 0; i < mgp->num_slices; i++) {
3782 ss = &mgp->ss[i];
3783 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
ede23fa8
JP		 3784 ss->rx_done.entry = dma_zalloc_coherent(&pdev->dev, bytes,
3785 &ss->rx_done.bus,
3786 GFP_KERNEL);
77929732
BG		 3787 if (ss->rx_done.entry == NULL)
3788 goto abort;
77929732
BG		 3789 bytes = sizeof(*ss->fw_stats);
3790 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3791 &ss->fw_stats_bus,
3792 GFP_KERNEL);
3793 if (ss->fw_stats == NULL)
3794 goto abort;
3795 ss->mgp = mgp;
3796 ss->dev = mgp->dev;
3797 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3798 myri10ge_napi_weight);
0dde8026 3799 napi_hash_add(&ss->napi);
77929732
BG		 3800 }
3801 return 0;
3802abort:
3803 myri10ge_free_slices(mgp);
3804 return -ENOMEM;
3805}
3806
3807/*
3808 * This function determines the number of slices supported.
25985edc 3809 * The number slices is the minimum of the number of CPUS,
77929732
BG		 3810 * the number of MSI-X irqs supported, the number of slices
3811 * supported by the firmware
3812 */
3813static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3814{
3815 struct myri10ge_cmd cmd;
3816 struct pci_dev *pdev = mgp->pdev;
3817 char *old_fw;
7d351035 3818 bool old_allocated;
40b29562 3819 int i, status, ncpus;
77929732
BG		 3820
3821 mgp->num_slices = 1;
98f2d21f 3822 ncpus = netif_get_num_default_rss_queues();
77929732 3823
40b29562 3824 if (myri10ge_max_slices == 1 || !pdev->msix_cap ||
77929732
BG		 3825 (myri10ge_max_slices == -1 && ncpus < 2))
3826 return;
3827
3828 /* try to load the slice aware rss firmware */
3829 old_fw = mgp->fw_name;
7d351035
RR		 3830 old_allocated = mgp->fw_name_allocated;
3831 /* don't free old_fw if we override it. */
3832 mgp->fw_name_allocated = false;
3833
13b2738c
BG		 3834 if (myri10ge_fw_name != NULL) {
3835 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3836 myri10ge_fw_name);
7d351035 3837 set_fw_name(mgp, myri10ge_fw_name, false);
13b2738c 3838 } else if (old_fw == myri10ge_fw_aligned)
7d351035 3839 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
77929732 3840 else
7d351035 3841 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
77929732
BG		 3842 status = myri10ge_load_firmware(mgp, 0);
3843 if (status != 0) {
3844 dev_info(&pdev->dev, "Rss firmware not found\n");
7d351035
RR		 3845 if (old_allocated)
3846 kfree(old_fw);
77929732
BG		 3847 return;
3848 }
3849
3850 /* hit the board with a reset to ensure it is alive */
3851 memset(&cmd, 0, sizeof(cmd));
3852 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3853 if (status != 0) {
3854 dev_err(&mgp->pdev->dev, "failed reset\n");
3855 goto abort_with_fw;
77929732
BG		 3856 }
3857
3858 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3859
3860 /* tell it the size of the interrupt queues */
3861 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3862 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3863 if (status != 0) {
3864 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3865 goto abort_with_fw;
3866 }
3867
3868 /* ask the maximum number of slices it supports */
3869 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3870 if (status != 0)
3871 goto abort_with_fw;
3872 else
3873 mgp->num_slices = cmd.data0;
3874
3875 /* Only allow multiple slices if MSI-X is usable */
3876 if (!myri10ge_msi) {
3877 goto abort_with_fw;
3878 }
3879
3880 /* if the admin did not specify a limit to how many
3881 * slices we should use, cap it automatically to the
3882 * number of CPUs currently online */
3883 if (myri10ge_max_slices == -1)
3884 myri10ge_max_slices = ncpus;
3885
3886 if (mgp->num_slices > myri10ge_max_slices)
3887 mgp->num_slices = myri10ge_max_slices;
3888
3889 /* Now try to allocate as many MSI-X vectors as we have
3890 * slices. We give up on MSI-X if we can only get a single
3891 * vector. */
3892
baeb2ffa
JP		 3893 mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3894 GFP_KERNEL);
77929732 3895 if (mgp->msix_vectors == NULL)
0729cc0c 3896 goto no_msix;
77929732
BG		 3897 for (i = 0; i < mgp->num_slices; i++) {
3898 mgp->msix_vectors[i].entry = i;
3899 }
3900
3901 while (mgp->num_slices > 1) {
0729cc0c 3902 mgp->num_slices = rounddown_pow_of_two(mgp->num_slices);
77929732 3903 if (mgp->num_slices == 1)
0729cc0c
AG		 3904 goto no_msix;
3905 status = pci_enable_msix_range(pdev,
3906 mgp->msix_vectors,
3907 mgp->num_slices,
3908 mgp->num_slices);
3909 if (status < 0)
3910 goto no_msix;
3911
3912 pci_disable_msix(pdev);
3913
3914 if (status == mgp->num_slices) {
7d351035
RR		 3915 if (old_allocated)
3916 kfree(old_fw);
77929732 3917 return;
0729cc0c 3918 } else {
77929732 3919 mgp->num_slices = status;
0729cc0c 3920 }
77929732
BG		 3921 }
3922
0729cc0c 3923no_msix:
77929732
BG		 3924 if (mgp->msix_vectors != NULL) {
3925 kfree(mgp->msix_vectors);
3926 mgp->msix_vectors = NULL;
3927 }
3928
3929abort_with_fw:
3930 mgp->num_slices = 1;
7d351035 3931 set_fw_name(mgp, old_fw, old_allocated);
77929732
BG		 3932 myri10ge_load_firmware(mgp, 0);
3933}
77929732 3934
8126089f
SH		 3935static const struct net_device_ops myri10ge_netdev_ops = {
3936 .ndo_open = myri10ge_open,
3937 .ndo_stop = myri10ge_close,
3938 .ndo_start_xmit = myri10ge_xmit,
c5f7ef72 3939 .ndo_get_stats64 = myri10ge_get_stats,
8126089f
SH		 3940 .ndo_validate_addr = eth_validate_addr,
3941 .ndo_change_mtu = myri10ge_change_mtu,
afc4b13d 3942 .ndo_set_rx_mode = myri10ge_set_multicast_list,
8126089f 3943 .ndo_set_mac_address = myri10ge_set_mac_address,
0dde8026
HYK		 3944#ifdef CONFIG_NET_RX_BUSY_POLL
3945 .ndo_busy_poll = myri10ge_busy_poll,
3946#endif
8126089f
SH		 3947};
3948
0da34b6d
BG		 3949static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3950{
3951 struct net_device *netdev;
3952 struct myri10ge_priv *mgp;
3953 struct device *dev = &pdev->dev;
0da34b6d
BG		 3954 int i;
3955 int status = -ENXIO;
0da34b6d 3956 int dac_enabled;
00b5e505 3957 unsigned hdr_offset, ss_offset;
2d90b0aa 3958 static int board_number;
0da34b6d 3959
236bb5e6 3960 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
41de8d4c 3961 if (netdev == NULL)
0da34b6d 3962 return -ENOMEM;
0da34b6d 3963
b245fb67
MH		 3964 SET_NETDEV_DEV(netdev, &pdev->dev);
3965
0da34b6d 3966 mgp = netdev_priv(netdev);
0da34b6d
BG		 3967 mgp->dev = netdev;
3968 mgp->pdev = pdev;
0da34b6d
BG		 3969 mgp->pause = myri10ge_flow_control;
3970 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3971 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3972 mgp->board_number = board_number;
0da34b6d
BG		 3973 init_waitqueue_head(&mgp->down_wq);
3974
3975 if (pci_enable_device(pdev)) {
3976 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3977 status = -ENODEV;
3978 goto abort_with_netdev;
3979 }
0da34b6d
BG		 3980
3981 /* Find the vendor-specific cap so we can check
3982 * the reboot register later on */
3983 mgp->vendor_specific_offset
3984 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3985
3986 /* Set our max read request to 4KB */
302d242c 3987 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3988 if (status != 0) {
3989 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3990 status);
e3fd5534 3991 goto abort_with_enabled;
0da34b6d
BG		 3992 }
3993
7539a613 3994 myri10ge_mask_surprise_down(pdev);
0da34b6d
BG		 3995 pci_set_master(pdev);
3996 dac_enabled = 1;
6a35528a 3997 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3998 if (status != 0) {
3999 dac_enabled = 0;
4000 dev_err(&pdev->dev,
898eb71c
JP		 4001 "64-bit pci address mask was refused, "
4002 "trying 32-bit\n");
284901a9 4003 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 4004 }
4005 if (status != 0) {
4006 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 4007 goto abort_with_enabled;
0da34b6d 4008 }
6a35528a 4009 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 4010 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
4011 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 4012 if (mgp->cmd == NULL)
e3fd5534 4013 goto abort_with_enabled;
0da34b6d 4014
0da34b6d
BG		 4015 mgp->board_span = pci_resource_len(pdev, 0);
4016 mgp->iomem_base = pci_resource_start(pdev, 0);
4017 mgp->mtrr = -1;
276e26c3 4018 mgp->wc_enabled = 0;
0da34b6d
BG		 4019#ifdef CONFIG_MTRR
4020 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
4021 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 4022 if (mgp->mtrr >= 0)
4023 mgp->wc_enabled = 1;
0da34b6d 4024#endif
c7f80993 4025 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 4026 if (mgp->sram == NULL) {
4027 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
4028 mgp->board_span, mgp->iomem_base);
4029 status = -ENXIO;
c7f80993 4030 goto abort_with_mtrr;
0da34b6d 4031 }
00b5e505 4032 hdr_offset =
59e955ed 4033 swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
00b5e505 4034 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
59e955ed 4035 mgp->sram_size = swab32(readl(mgp->sram + ss_offset));
00b5e505
BG		 4036 if (mgp->sram_size > mgp->board_span ||
4037 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
4038 dev_err(&pdev->dev,
4039 "invalid sram_size %dB or board span %ldB\n",
4040 mgp->sram_size, mgp->board_span);
4041 goto abort_with_ioremap;
4042 }
0da34b6d 4043 memcpy_fromio(mgp->eeprom_strings,
00b5e505 4044 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 4045 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
4046 status = myri10ge_read_mac_addr(mgp);
4047 if (status)
4048 goto abort_with_ioremap;
4049
4050 for (i = 0; i < ETH_ALEN; i++)
4051 netdev->dev_addr[i] = mgp->mac_addr[i];
4052
5443e9ea
BG		 4053 myri10ge_select_firmware(mgp);
4054
0dcffac1 4055 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 4056 if (status != 0) {
4057 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 4058 goto abort_with_ioremap;
4059 }
4060 myri10ge_probe_slices(mgp);
4061 status = myri10ge_alloc_slices(mgp);
4062 if (status != 0) {
4063 dev_err(&pdev->dev, "failed to alloc slice state\n");
4064 goto abort_with_firmware;
0da34b6d 4065 }
c9920268
BH		 4066 netif_set_real_num_tx_queues(netdev, mgp->num_slices);
4067 netif_set_real_num_rx_queues(netdev, mgp->num_slices);
0da34b6d
BG		 4068 status = myri10ge_reset(mgp);
4069 if (status != 0) {
4070 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 4071 goto abort_with_slices;
0da34b6d 4072 }
5dd2d332 4073#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4074 myri10ge_setup_dca(mgp);
4075#endif
0da34b6d
BG		 4076 pci_set_drvdata(pdev, mgp);
4077 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
4078 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
4079 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
4080 myri10ge_initial_mtu = 68;
8126089f
SH		 4081
4082 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 4083 netdev->mtu = myri10ge_initial_mtu;
4ca3221f 4084 netdev->hw_features = mgp->features | NETIF_F_RXCSUM;
1b4c44e6 4085
f646968f
PM		 4086 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
4087 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1b4c44e6 4088
47c2cdf5 4089 netdev->features = netdev->hw_features;
236bb5e6 4090
0da34b6d
BG		 4091 if (dac_enabled)
4092 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 4093
dddc045e
BG		 4094 netdev->vlan_features |= mgp->features;
4095 if (mgp->fw_ver_tiny < 37)
4096 netdev->vlan_features &= ~NETIF_F_TSO6;
4097 if (mgp->fw_ver_tiny < 32)
4098 netdev->vlan_features &= ~NETIF_F_TSO;
4099
21d05db1 4100 /* make sure we can get an irq, and that MSI can be
a7425458 4101 * setup (if available). */
21d05db1
BG		 4102 status = myri10ge_request_irq(mgp);
4103 if (status != 0)
4104 goto abort_with_firmware;
21d05db1
BG		 4105 myri10ge_free_irq(mgp);
4106
0da34b6d
BG		 4107 /* Save configuration space to be restored if the
4108 * nic resets due to a parity error */
83f6e152 4109 pci_save_state(pdev);
0da34b6d
BG		 4110
4111 /* Setup the watchdog timer */
4112 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
4113 (unsigned long)mgp);
4114
7ad24ea4 4115 netdev->ethtool_ops = &myri10ge_ethtool_ops;
c4028958 4116 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 4117 status = register_netdev(netdev);
4118 if (status != 0) {
4119 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 4120 goto abort_with_state;
0da34b6d 4121 }
0dcffac1
BG		 4122 if (mgp->msix_enabled)
4123 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
4124 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
4125 (mgp->wc_enabled ? "Enabled" : "Disabled"));
4126 else
4127 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
4128 mgp->msi_enabled ? "MSI" : "xPIC",
a7425458 4129 pdev->irq, mgp->tx_boundary, mgp->fw_name,
0dcffac1 4130 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 4131
2d90b0aa 4132 board_number++;
0da34b6d
BG		 4133 return 0;
4134
7adda30c 4135abort_with_state:
83f6e152 4136 pci_restore_state(pdev);
0da34b6d 4137
0dcffac1
BG		 4138abort_with_slices:
4139 myri10ge_free_slices(mgp);
4140
0da34b6d
BG		 4141abort_with_firmware:
4142 myri10ge_dummy_rdma(mgp, 0);
4143
0da34b6d 4144abort_with_ioremap:
0f840011
BG		 4145 if (mgp->mac_addr_string != NULL)
4146 dev_err(&pdev->dev,
4147 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
4148 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 4149 iounmap(mgp->sram);
4150
c7f80993 4151abort_with_mtrr:
0da34b6d
BG		 4152#ifdef CONFIG_MTRR
4153 if (mgp->mtrr >= 0)
4154 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4155#endif
b10c0668
BG		 4156 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4157 mgp->cmd, mgp->cmd_bus);
0da34b6d 4158
e3fd5534
BG		 4159abort_with_enabled:
4160 pci_disable_device(pdev);
0da34b6d 4161
e3fd5534 4162abort_with_netdev:
7d351035 4163 set_fw_name(mgp, NULL, false);
0da34b6d
BG		 4164 free_netdev(netdev);
4165 return status;
4166}
4167
4168/*
4169 * myri10ge_remove
4170 *
4171 * Does what is necessary to shutdown one Myrinet device. Called
4172 * once for each Myrinet card by the kernel when a module is
4173 * unloaded.
4174 */
4175static void myri10ge_remove(struct pci_dev *pdev)
4176{
4177 struct myri10ge_priv *mgp;
4178 struct net_device *netdev;
0da34b6d
BG		 4179
4180 mgp = pci_get_drvdata(pdev);
4181 if (mgp == NULL)
4182 return;
4183
23f333a2 4184 cancel_work_sync(&mgp->watchdog_work);
0da34b6d
BG		 4185 netdev = mgp->dev;
4186 unregister_netdev(netdev);
0da34b6d 4187
5dd2d332 4188#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4189 myri10ge_teardown_dca(mgp);
4190#endif
0da34b6d
BG		 4191 myri10ge_dummy_rdma(mgp, 0);
4192
7adda30c 4193 /* avoid a memory leak */
83f6e152 4194 pci_restore_state(pdev);
7adda30c 4195
0da34b6d
BG		 4196 iounmap(mgp->sram);
4197
4198#ifdef CONFIG_MTRR
4199 if (mgp->mtrr >= 0)
4200 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4201#endif
0dcffac1
BG		 4202 myri10ge_free_slices(mgp);
4203 if (mgp->msix_vectors != NULL)
4204 kfree(mgp->msix_vectors);
b10c0668
BG		 4205 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4206 mgp->cmd, mgp->cmd_bus);
0da34b6d 4207
7d351035 4208 set_fw_name(mgp, NULL, false);
0da34b6d 4209 free_netdev(netdev);
e3fd5534 4210 pci_disable_device(pdev);
0da34b6d
BG		 4211}
4212
b10c0668 4213#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4214#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d 4215
a3aa1884 4216static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
b10c0668 4217 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4218 {PCI_DEVICE
4219 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4220 {0},
4221};
4222
97131079
BG		 4223MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4224
0da34b6d
BG		 4225static struct pci_driver myri10ge_driver = {
4226 .name = "myri10ge",
4227 .probe = myri10ge_probe,
4228 .remove = myri10ge_remove,
4229 .id_table = myri10ge_pci_tbl,
4230#ifdef CONFIG_PM
4231 .suspend = myri10ge_suspend,
4232 .resume = myri10ge_resume,
4233#endif
4234};
4235
5dd2d332 4236#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4237static int
4238myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4239{
4240 int err = driver_for_each_device(&myri10ge_driver.driver,
4241 NULL, &event,
4242 myri10ge_notify_dca_device);
4243
4244 if (err)
4245 return NOTIFY_BAD;
4246 return NOTIFY_DONE;
4247}
4248
4249static struct notifier_block myri10ge_dca_notifier = {
4250 .notifier_call = myri10ge_notify_dca,
4251 .next = NULL,
4252 .priority = 0,
4253};
4ee2ac51 4254#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4255
0da34b6d
BG		 4256static __init int myri10ge_init_module(void)
4257{
78ca90ea 4258 pr_info("Version %s\n", MYRI10GE_VERSION_STR);
0dcffac1 4259
236bb5e6 4260 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
78ca90ea
JP		 4261 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4262 myri10ge_rss_hash);
0dcffac1
BG		 4263 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4264 }
5dd2d332 4265#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4266 dca_register_notify(&myri10ge_dca_notifier);
4267#endif
236bb5e6
BG		 4268 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4269 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4270
0da34b6d
BG		 4271 return pci_register_driver(&myri10ge_driver);
4272}
4273
4274module_init(myri10ge_init_module);
4275
4276static __exit void myri10ge_cleanup_module(void)
4277{
5dd2d332 4278#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4279 dca_unregister_notify(&myri10ge_dca_notifier);
4280#endif
0da34b6d
BG		 4281 pci_unregister_driver(&myri10ge_driver);
4282}
4283
4284module_exit(myri10ge_cleanup_module);
Linux 6.x block layer and io_uring tree(s)