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myri10ge: Convert from LRO to GRO
[linux-2.6-block.git] / drivers / net / ethernet / myricom / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
3bea1237 4 * Copyright (C) 2005 - 2011 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
78ca90ea
JP		 41#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42
0da34b6d
BG		 43#include <linux/tcp.h>
44#include <linux/netdevice.h>
45#include <linux/skbuff.h>
46#include <linux/string.h>
47#include <linux/module.h>
48#include <linux/pci.h>
b10c0668 49#include <linux/dma-mapping.h>
0da34b6d
BG		 50#include <linux/etherdevice.h>
51#include <linux/if_ether.h>
52#include <linux/if_vlan.h>
981813d8 53#include <linux/dca.h>
0da34b6d
BG		 54#include <linux/ip.h>
55#include <linux/inet.h>
56#include <linux/in.h>
57#include <linux/ethtool.h>
58#include <linux/firmware.h>
59#include <linux/delay.h>
0da34b6d
BG		 60#include <linux/timer.h>
61#include <linux/vmalloc.h>
62#include <linux/crc32.h>
63#include <linux/moduleparam.h>
64#include <linux/io.h>
199126a2 65#include <linux/log2.h>
5a0e3ad6 66#include <linux/slab.h>
70c71606 67#include <linux/prefetch.h>
0da34b6d 68#include <net/checksum.h>
1e6e9342
AG		 69#include <net/ip.h>
70#include <net/tcp.h>
0da34b6d
BG		 71#include <asm/byteorder.h>
72#include <asm/io.h>
0da34b6d
BG		 73#include <asm/processor.h>
74#ifdef CONFIG_MTRR
75#include <asm/mtrr.h>
76#endif
77
78#include "myri10ge_mcp.h"
79#include "myri10ge_mcp_gen_header.h"
80
3bea1237 81#define MYRI10GE_VERSION_STR "1.5.3-1.534"
0da34b6d
BG		 82
83MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
84MODULE_AUTHOR("Maintainer: help@myri.com");
85MODULE_VERSION(MYRI10GE_VERSION_STR);
86MODULE_LICENSE("Dual BSD/GPL");
87
88#define MYRI10GE_MAX_ETHER_MTU 9014
89
90#define MYRI10GE_ETH_STOPPED 0
91#define MYRI10GE_ETH_STOPPING 1
92#define MYRI10GE_ETH_STARTING 2
93#define MYRI10GE_ETH_RUNNING 3
94#define MYRI10GE_ETH_OPEN_FAILED 4
95
96#define MYRI10GE_EEPROM_STRINGS_SIZE 256
97#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
98
40f6cff5 99#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 100#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
101
dd50f336
BG		 102#define MYRI10GE_ALLOC_ORDER 0
103#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
104#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
105
236bb5e6
BG		 106#define MYRI10GE_MAX_SLICES 32
107
0da34b6d 108struct myri10ge_rx_buffer_state {
dd50f336
BG		 109 struct page *page;
110 int page_offset;
c755b4b6
FT		 111 DEFINE_DMA_UNMAP_ADDR(bus);
112 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 113};
114
115struct myri10ge_tx_buffer_state {
116 struct sk_buff *skb;
117 int last;
c755b4b6
FT		 118 DEFINE_DMA_UNMAP_ADDR(bus);
119 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 120};
121
122struct myri10ge_cmd {
123 u32 data0;
124 u32 data1;
125 u32 data2;
126};
127
128struct myri10ge_rx_buf {
129 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 130 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
131 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 132 struct page *page;
133 dma_addr_t bus;
134 int page_offset;
0da34b6d 135 int cnt;
dd50f336 136 int fill_cnt;
0da34b6d
BG		 137 int alloc_fail;
138 int mask; /* number of rx slots -1 */
dd50f336 139 int watchdog_needed;
0da34b6d
BG		 140};
141
142struct myri10ge_tx_buf {
143 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 144 __be32 __iomem *send_go; /* "go" doorbell ptr */
145 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 146 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
147 char *req_bytes;
148 struct myri10ge_tx_buffer_state *info;
149 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 150 int req ____cacheline_aligned; /* transmit slots submitted */
151 int pkt_start; /* packets started */
b53bef84
BG		 152 int stop_queue;
153 int linearized;
0da34b6d
BG		 154 int done ____cacheline_aligned; /* transmit slots completed */
155 int pkt_done; /* packets completed */
b53bef84 156 int wake_queue;
236bb5e6 157 int queue_active;
0da34b6d
BG		 158};
159
160struct myri10ge_rx_done {
161 struct mcp_slot *entry;
162 dma_addr_t bus;
163 int cnt;
164 int idx;
165};
166
b53bef84
BG		 167struct myri10ge_slice_netstats {
168 unsigned long rx_packets;
169 unsigned long tx_packets;
170 unsigned long rx_bytes;
171 unsigned long tx_bytes;
172 unsigned long rx_dropped;
173 unsigned long tx_dropped;
174};
175
176struct myri10ge_slice_state {
0da34b6d
BG		 177 struct myri10ge_tx_buf tx; /* transmit ring */
178 struct myri10ge_rx_buf rx_small;
179 struct myri10ge_rx_buf rx_big;
180 struct myri10ge_rx_done rx_done;
b53bef84
BG		 181 struct net_device *dev;
182 struct napi_struct napi;
183 struct myri10ge_priv *mgp;
184 struct myri10ge_slice_netstats stats;
185 __be32 __iomem *irq_claim;
186 struct mcp_irq_data *fw_stats;
187 dma_addr_t fw_stats_bus;
188 int watchdog_tx_done;
189 int watchdog_tx_req;
d0234215 190 int watchdog_rx_done;
c689b81b 191 int stuck;
5dd2d332 192#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 193 int cached_dca_tag;
194 int cpu;
195 __be32 __iomem *dca_tag;
196#endif
0dcffac1 197 char irq_desc[32];
b53bef84
BG		 198};
199
200struct myri10ge_priv {
0dcffac1 201 struct myri10ge_slice_state *ss;
b53bef84 202 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 203 int num_slices;
b53bef84 204 int running; /* running? */
0da34b6d 205 int small_bytes;
dd50f336 206 int big_bytes;
fa0a90d9 207 int max_intr_slots;
0da34b6d 208 struct net_device *dev;
0da34b6d
BG		 209 u8 __iomem *sram;
210 int sram_size;
211 unsigned long board_span;
212 unsigned long iomem_base;
40f6cff5 213 __be32 __iomem *irq_deassert;
0da34b6d
BG		 214 char *mac_addr_string;
215 struct mcp_cmd_response *cmd;
216 dma_addr_t cmd_bus;
0da34b6d
BG		 217 struct pci_dev *pdev;
218 int msi_enabled;
0dcffac1
BG		 219 int msix_enabled;
220 struct msix_entry *msix_vectors;
5dd2d332 221#ifdef CONFIG_MYRI10GE_DCA
981813d8 222 int dca_enabled;
ef09aadf 223 int relaxed_order;
981813d8 224#endif
66341fff 225 u32 link_state;
0da34b6d
BG		 226 unsigned int rdma_tags_available;
227 int intr_coal_delay;
40f6cff5 228 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 229 int mtrr;
276e26c3 230 int wc_enabled;
0da34b6d
BG		 231 int down_cnt;
232 wait_queue_head_t down_wq;
233 struct work_struct watchdog_work;
234 struct timer_list watchdog_timer;
0da34b6d 235 int watchdog_resets;
b53bef84 236 int watchdog_pause;
0da34b6d 237 int pause;
7d351035 238 bool fw_name_allocated;
0da34b6d
BG		 239 char *fw_name;
240 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 241 char *product_code_string;
0da34b6d 242 char fw_version[128];
9dc6f0e7
BG		 243 int fw_ver_major;
244 int fw_ver_minor;
245 int fw_ver_tiny;
246 int adopted_rx_filter_bug;
0da34b6d
BG		 247 u8 mac_addr[6]; /* eeprom mac address */
248 unsigned long serial_number;
249 int vendor_specific_offset;
85a7ea1b 250 int fw_multicast_support;
04ed3e74 251 u32 features;
4f93fde0 252 u32 max_tso6;
0da34b6d
BG		 253 u32 read_dma;
254 u32 write_dma;
255 u32 read_write_dma;
c58ac5ca
BG		 256 u32 link_changes;
257 u32 msg_enable;
2d90b0aa 258 unsigned int board_number;
d0234215 259 int rebooted;
0da34b6d
BG		 260};
261
262static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
263static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 264static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
265static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
b9721d5a
BH		 266MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
267MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
268MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
269MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
0da34b6d 270
7d351035 271/* Careful: must be accessed under kparam_block_sysfs_write */
0da34b6d
BG		 272static char *myri10ge_fw_name = NULL;
273module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 274MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 275
2d90b0aa
BG		 276#define MYRI10GE_MAX_BOARDS 8
277static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 278 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 279module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
280 0444);
281MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
282
0da34b6d
BG		 283static int myri10ge_ecrc_enable = 1;
284module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 285MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 286
0da34b6d
BG		 287static int myri10ge_small_bytes = -1; /* -1 == auto */
288module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 289MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 290
291static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 292module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 293MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 294
f761fae1 295static int myri10ge_intr_coal_delay = 75;
0da34b6d 296module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 297MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 298
299static int myri10ge_flow_control = 1;
300module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 301MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 302
303static int myri10ge_deassert_wait = 1;
304module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
305MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 306 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 307
308static int myri10ge_force_firmware = 0;
309module_param(myri10ge_force_firmware, int, S_IRUGO);
310MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 311 "Force firmware to assume aligned completions");
0da34b6d 312
0da34b6d
BG		 313static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
314module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 315MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 316
317static int myri10ge_napi_weight = 64;
318module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 319MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 320
321static int myri10ge_watchdog_timeout = 1;
322module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 323MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 324
325static int myri10ge_max_irq_loops = 1048576;
326module_param(myri10ge_max_irq_loops, int, S_IRUGO);
327MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 328 "Set stuck legacy IRQ detection threshold");
0da34b6d 329
c58ac5ca
BG		 330#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
331
332static int myri10ge_debug = -1; /* defaults above */
333module_param(myri10ge_debug, int, 0);
334MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
335
dd50f336
BG		 336static int myri10ge_fill_thresh = 256;
337module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 338MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 339
f181137f
BG		 340static int myri10ge_reset_recover = 1;
341
0dcffac1
BG		 342static int myri10ge_max_slices = 1;
343module_param(myri10ge_max_slices, int, S_IRUGO);
344MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
345
4b860abf 346static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
0dcffac1
BG		 347module_param(myri10ge_rss_hash, int, S_IRUGO);
348MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
349
981813d8
BG		 350static int myri10ge_dca = 1;
351module_param(myri10ge_dca, int, S_IRUGO);
352MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
353
0da34b6d
BG		 354#define MYRI10GE_FW_OFFSET 1024*1024
355#define MYRI10GE_HIGHPART_TO_U32(X) \
356(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
357#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
358
359#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
360
2f76216f 361static void myri10ge_set_multicast_list(struct net_device *dev);
61357325
SH		 362static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
363 struct net_device *dev);
2f76216f 364
6250223e 365static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 366{
6250223e 367 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 368}
369
c5f7ef72 370static struct rtnl_link_stats64 *myri10ge_get_stats(struct net_device *dev,
371 struct rtnl_link_stats64 *stats);
59081825 372
7d351035
RR		 373static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
374{
375 if (mgp->fw_name_allocated)
376 kfree(mgp->fw_name);
377 mgp->fw_name = name;
378 mgp->fw_name_allocated = allocated;
379}
380
0da34b6d
BG		 381static int
382myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
383 struct myri10ge_cmd *data, int atomic)
384{
385 struct mcp_cmd *buf;
386 char buf_bytes[sizeof(*buf) + 8];
387 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 388 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 389 u32 dma_low, dma_high, result, value;
390 int sleep_total = 0;
391
392 /* ensure buf is aligned to 8 bytes */
393 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
394
395 buf->data0 = htonl(data->data0);
396 buf->data1 = htonl(data->data1);
397 buf->data2 = htonl(data->data2);
398 buf->cmd = htonl(cmd);
399 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
400 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
401
402 buf->response_addr.low = htonl(dma_low);
403 buf->response_addr.high = htonl(dma_high);
40f6cff5 404 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 405 mb();
406 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
407
408 /* wait up to 15ms. Longest command is the DMA benchmark,
409 * which is capped at 5ms, but runs from a timeout handler
410 * that runs every 7.8ms. So a 15ms timeout leaves us with
411 * a 2.2ms margin
412 */
413 if (atomic) {
414 /* if atomic is set, do not sleep,
415 * and try to get the completion quickly
416 * (1ms will be enough for those commands) */
417 for (sleep_total = 0;
8e95a202
JP		 418 sleep_total < 1000 &&
419 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 420 sleep_total += 10) {
0da34b6d 421 udelay(10);
bd2db0cf
BG		 422 mb();
423 }
0da34b6d
BG		 424 } else {
425 /* use msleep for most command */
426 for (sleep_total = 0;
8e95a202
JP		 427 sleep_total < 15 &&
428 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 429 sleep_total++)
430 msleep(1);
431 }
432
433 result = ntohl(response->result);
434 value = ntohl(response->data);
435 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
436 if (result == 0) {
437 data->data0 = value;
438 return 0;
85a7ea1b
BG		 439 } else if (result == MXGEFW_CMD_UNKNOWN) {
440 return -ENOSYS;
5443e9ea
BG		 441 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
442 return -E2BIG;
236bb5e6
BG		 443 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
444 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
445 (data->
446 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
447 0) {
448 return -ERANGE;
0da34b6d
BG		 449 } else {
450 dev_err(&mgp->pdev->dev,
451 "command %d failed, result = %d\n",
452 cmd, result);
453 return -ENXIO;
454 }
455 }
456
457 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
458 cmd, result);
459 return -EAGAIN;
460}
461
462/*
463 * The eeprom strings on the lanaiX have the format
464 * SN=x\0
465 * MAC=x:x:x:x:x:x\0
466 * PT:ddd mmm xx xx:xx:xx xx\0
467 * PV:ddd mmm xx xx:xx:xx xx\0
468 */
469static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
470{
471 char *ptr, *limit;
472 int i;
473
474 ptr = mgp->eeprom_strings;
475 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
476
477 while (*ptr != '\0' && ptr < limit) {
478 if (memcmp(ptr, "MAC=", 4) == 0) {
479 ptr += 4;
480 mgp->mac_addr_string = ptr;
481 for (i = 0; i < 6; i++) {
482 if ((ptr + 2) > limit)
483 goto abort;
484 mgp->mac_addr[i] =
485 simple_strtoul(ptr, &ptr, 16);
486 ptr += 1;
487 }
488 }
c0bf8801
BG		 489 if (memcmp(ptr, "PC=", 3) == 0) {
490 ptr += 3;
491 mgp->product_code_string = ptr;
492 }
0da34b6d
BG		 493 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
494 ptr += 3;
495 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
496 }
497 while (ptr < limit && *ptr++) ;
498 }
499
500 return 0;
501
502abort:
503 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
504 return -ENXIO;
505}
506
507/*
508 * Enable or disable periodic RDMAs from the host to make certain
509 * chipsets resend dropped PCIe messages
510 */
511
512static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
513{
514 char __iomem *submit;
f8fd57c1 515 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 516 u32 dma_low, dma_high;
517 int i;
518
519 /* clear confirmation addr */
520 mgp->cmd->data = 0;
521 mb();
522
523 /* send a rdma command to the PCIe engine, and wait for the
524 * response in the confirmation address. The firmware should
525 * write a -1 there to indicate it is alive and well
526 */
527 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
528 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
529
530 buf[0] = htonl(dma_high); /* confirm addr MSW */
531 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 532 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 533 buf[3] = htonl(dma_high); /* dummy addr MSW */
534 buf[4] = htonl(dma_low); /* dummy addr LSW */
535 buf[5] = htonl(enable); /* enable? */
536
e700f9f4 537 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 538
539 myri10ge_pio_copy(submit, &buf, sizeof(buf));
540 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
541 msleep(1);
542 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
543 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
544 (enable ? "enable" : "disable"));
545}
546
547static int
548myri10ge_validate_firmware(struct myri10ge_priv *mgp,
549 struct mcp_gen_header *hdr)
550{
551 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 552
553 /* check firmware type */
554 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
555 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
556 return -EINVAL;
557 }
558
559 /* save firmware version for ethtool */
560 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
561
9dc6f0e7
BG		 562 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
563 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 564
8e95a202
JP		 565 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
566 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 567 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
568 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
569 MXGEFW_VERSION_MINOR);
570 return -EINVAL;
571 }
572 return 0;
573}
574
575static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
576{
577 unsigned crc, reread_crc;
578 const struct firmware *fw;
579 struct device *dev = &mgp->pdev->dev;
b0d31d6b 580 unsigned char *fw_readback;
0da34b6d
BG		 581 struct mcp_gen_header *hdr;
582 size_t hdr_offset;
583 int status;
e454358a 584 unsigned i;
0da34b6d
BG		 585
586 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
587 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
588 mgp->fw_name);
589 status = -EINVAL;
590 goto abort_with_nothing;
591 }
592
593 /* check size */
594
595 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
596 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
597 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
598 status = -EINVAL;
599 goto abort_with_fw;
600 }
601
602 /* check id */
40f6cff5 603 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 604 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
605 dev_err(dev, "Bad firmware file\n");
606 status = -EINVAL;
607 goto abort_with_fw;
608 }
609 hdr = (void *)(fw->data + hdr_offset);
610
611 status = myri10ge_validate_firmware(mgp, hdr);
612 if (status != 0)
613 goto abort_with_fw;
614
615 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 616 for (i = 0; i < fw->size; i += 256) {
617 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
618 fw->data + i,
619 min(256U, (unsigned)(fw->size - i)));
620 mb();
621 readb(mgp->sram);
b10c0668 622 }
b0d31d6b
DW		 623 fw_readback = vmalloc(fw->size);
624 if (!fw_readback) {
625 status = -ENOMEM;
626 goto abort_with_fw;
627 }
0da34b6d 628 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 629 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
630 reread_crc = crc32(~0, fw_readback, fw->size);
631 vfree(fw_readback);
0da34b6d
BG		 632 if (crc != reread_crc) {
633 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
634 (unsigned)fw->size, reread_crc, crc);
635 status = -EIO;
636 goto abort_with_fw;
637 }
638 *size = (u32) fw->size;
639
640abort_with_fw:
641 release_firmware(fw);
642
643abort_with_nothing:
644 return status;
645}
646
647static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
648{
649 struct mcp_gen_header *hdr;
650 struct device *dev = &mgp->pdev->dev;
651 const size_t bytes = sizeof(struct mcp_gen_header);
652 size_t hdr_offset;
653 int status;
654
655 /* find running firmware header */
66341fff 656 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 657
658 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
659 dev_err(dev, "Running firmware has bad header offset (%d)\n",
660 (int)hdr_offset);
661 return -EIO;
662 }
663
664 /* copy header of running firmware from SRAM to host memory to
665 * validate firmware */
666 hdr = kmalloc(bytes, GFP_KERNEL);
667 if (hdr == NULL) {
668 dev_err(dev, "could not malloc firmware hdr\n");
669 return -ENOMEM;
670 }
671 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
672 status = myri10ge_validate_firmware(mgp, hdr);
673 kfree(hdr);
9dc6f0e7
BG		 674
675 /* check to see if adopted firmware has bug where adopting
676 * it will cause broadcasts to be filtered unless the NIC
677 * is kept in ALLMULTI mode */
678 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
679 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
680 mgp->adopted_rx_filter_bug = 1;
681 dev_warn(dev, "Adopting fw %d.%d.%d: "
682 "working around rx filter bug\n",
683 mgp->fw_ver_major, mgp->fw_ver_minor,
684 mgp->fw_ver_tiny);
685 }
0da34b6d
BG		 686 return status;
687}
688
0178ec3d 689static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 690{
691 struct myri10ge_cmd cmd;
692 int status;
693
694 /* probe for IPv6 TSO support */
695 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
696 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
697 &cmd, 0);
698 if (status == 0) {
699 mgp->max_tso6 = cmd.data0;
700 mgp->features |= NETIF_F_TSO6;
701 }
702
703 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
704 if (status != 0) {
705 dev_err(&mgp->pdev->dev,
706 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
707 return -ENXIO;
708 }
709
710 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
711
712 return 0;
713}
714
0dcffac1 715static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 716{
717 char __iomem *submit;
f8fd57c1 718 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 719 u32 dma_low, dma_high, size;
720 int status, i;
721
b10c0668 722 size = 0;
0da34b6d
BG		 723 status = myri10ge_load_hotplug_firmware(mgp, &size);
724 if (status) {
0dcffac1
BG		 725 if (!adopt)
726 return status;
0da34b6d
BG		 727 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
728
729 /* Do not attempt to adopt firmware if there
730 * was a bad crc */
731 if (status == -EIO)
732 return status;
733
734 status = myri10ge_adopt_running_firmware(mgp);
735 if (status != 0) {
736 dev_err(&mgp->pdev->dev,
737 "failed to adopt running firmware\n");
738 return status;
739 }
740 dev_info(&mgp->pdev->dev,
741 "Successfully adopted running firmware\n");
b53bef84 742 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 743 dev_warn(&mgp->pdev->dev,
744 "Using firmware currently running on NIC"
745 ". For optimal\n");
746 dev_warn(&mgp->pdev->dev,
747 "performance consider loading optimized "
748 "firmware\n");
749 dev_warn(&mgp->pdev->dev, "via hotplug\n");
750 }
751
7d351035 752 set_fw_name(mgp, "adopted", false);
b53bef84 753 mgp->tx_boundary = 2048;
fa0a90d9
BG		 754 myri10ge_dummy_rdma(mgp, 1);
755 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 756 return status;
757 }
758
759 /* clear confirmation addr */
760 mgp->cmd->data = 0;
761 mb();
762
763 /* send a reload command to the bootstrap MCP, and wait for the
764 * response in the confirmation address. The firmware should
765 * write a -1 there to indicate it is alive and well
766 */
767 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
768 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
769
770 buf[0] = htonl(dma_high); /* confirm addr MSW */
771 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 772 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 773
774 /* FIX: All newest firmware should un-protect the bottom of
775 * the sram before handoff. However, the very first interfaces
776 * do not. Therefore the handoff copy must skip the first 8 bytes
777 */
778 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
779 buf[4] = htonl(size - 8); /* length of code */
780 buf[5] = htonl(8); /* where to copy to */
781 buf[6] = htonl(0); /* where to jump to */
782
e700f9f4 783 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 784
785 myri10ge_pio_copy(submit, &buf, sizeof(buf));
786 mb();
787 msleep(1);
788 mb();
789 i = 0;
d93ca2a4
BG		 790 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
791 msleep(1 << i);
0da34b6d
BG		 792 i++;
793 }
794 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
795 dev_err(&mgp->pdev->dev, "handoff failed\n");
796 return -ENXIO;
797 }
9a71db72 798 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 799 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 800
fa0a90d9 801 return status;
0da34b6d
BG		 802}
803
804static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
805{
806 struct myri10ge_cmd cmd;
807 int status;
808
809 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
810 | (addr[2] << 8) | addr[3]);
811
812 cmd.data1 = ((addr[4] << 8) | (addr[5]));
813
814 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
815 return status;
816}
817
818static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
819{
820 struct myri10ge_cmd cmd;
821 int status, ctl;
822
823 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
824 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
825
826 if (status) {
78ca90ea 827 netdev_err(mgp->dev, "Failed to set flow control mode\n");
0da34b6d
BG		 828 return status;
829 }
830 mgp->pause = pause;
831 return 0;
832}
833
834static void
835myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
836{
837 struct myri10ge_cmd cmd;
838 int status, ctl;
839
840 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
841 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
842 if (status)
78ca90ea 843 netdev_err(mgp->dev, "Failed to set promisc mode\n");
0da34b6d
BG		 844}
845
0d6ac257 846static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 847{
848 struct myri10ge_cmd cmd;
849 int status;
0da34b6d 850 u32 len;
34fdccea
BG		 851 struct page *dmatest_page;
852 dma_addr_t dmatest_bus;
0d6ac257
BG		 853 char *test = " ";
854
855 dmatest_page = alloc_page(GFP_KERNEL);
856 if (!dmatest_page)
857 return -ENOMEM;
858 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
859 DMA_BIDIRECTIONAL);
860
861 /* Run a small DMA test.
862 * The magic multipliers to the length tell the firmware
863 * to do DMA read, write, or read+write tests. The
864 * results are returned in cmd.data0. The upper 16
865 * bits or the return is the number of transfers completed.
866 * The lower 16 bits is the time in 0.5us ticks that the
867 * transfers took to complete.
868 */
869
b53bef84 870 len = mgp->tx_boundary;
0d6ac257
BG		 871
872 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
873 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
874 cmd.data2 = len * 0x10000;
875 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
876 if (status != 0) {
877 test = "read";
878 goto abort;
879 }
880 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
881 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
882 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
883 cmd.data2 = len * 0x1;
884 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
885 if (status != 0) {
886 test = "write";
887 goto abort;
888 }
889 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
890
891 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
892 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
893 cmd.data2 = len * 0x10001;
894 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
895 if (status != 0) {
896 test = "read/write";
897 goto abort;
898 }
899 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
900 (cmd.data0 & 0xffff);
901
902abort:
903 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
904 put_page(dmatest_page);
905
906 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
907 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
908 test, status);
909
910 return status;
911}
912
913static int myri10ge_reset(struct myri10ge_priv *mgp)
914{
915 struct myri10ge_cmd cmd;
0dcffac1
BG		 916 struct myri10ge_slice_state *ss;
917 int i, status;
0d6ac257 918 size_t bytes;
5dd2d332 919#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 920 unsigned long dca_tag_off;
921#endif
0da34b6d
BG		 922
923 /* try to send a reset command to the card to see if it
924 * is alive */
925 memset(&cmd, 0, sizeof(cmd));
926 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
927 if (status != 0) {
928 dev_err(&mgp->pdev->dev, "failed reset\n");
929 return -ENXIO;
930 }
0d6ac257
BG		 931
932 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 933 /*
934 * Use non-ndis mcp_slot (eg, 4 bytes total,
935 * no toeplitz hash value returned. Older firmware will
936 * not understand this command, but will use the correct
937 * sized mcp_slot, so we ignore error returns
938 */
939 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
940 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 941
942 /* Now exchange information about interrupts */
943
0dcffac1 944 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 945 cmd.data0 = (u32) bytes;
946 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 947
948 /*
949 * Even though we already know how many slices are supported
950 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
951 * has magic side effects, and must be called after a reset.
952 * It must be called prior to calling any RSS related cmds,
953 * including assigning an interrupt queue for anything but
954 * slice 0. It must also be called *after*
955 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
956 * the firmware to compute offsets.
957 */
958
959 if (mgp->num_slices > 1) {
960
961 /* ask the maximum number of slices it supports */
962 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
963 &cmd, 0);
964 if (status != 0) {
965 dev_err(&mgp->pdev->dev,
966 "failed to get number of slices\n");
967 }
968
969 /*
970 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
971 * to setting up the interrupt queue DMA
972 */
973
974 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 975 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
976 if (mgp->dev->real_num_tx_queues > 1)
977 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 978 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
979 &cmd, 0);
236bb5e6
BG		 980
981 /* Firmware older than 1.4.32 only supports multiple
982 * RX queues, so if we get an error, first retry using a
983 * single TX queue before giving up */
984 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
c9920268 985 netif_set_real_num_tx_queues(mgp->dev, 1);
236bb5e6
BG		 986 cmd.data0 = mgp->num_slices;
987 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
988 status = myri10ge_send_cmd(mgp,
989 MXGEFW_CMD_ENABLE_RSS_QUEUES,
990 &cmd, 0);
991 }
992
0dcffac1
BG		 993 if (status != 0) {
994 dev_err(&mgp->pdev->dev,
995 "failed to set number of slices\n");
996
997 return status;
998 }
999 }
1000 for (i = 0; i < mgp->num_slices; i++) {
1001 ss = &mgp->ss[i];
1002 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1003 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1004 cmd.data2 = i;
1005 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1006 &cmd, 0);
6403eab1 1007 }
0da34b6d
BG		 1008
1009 status |=
1010 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1011 for (i = 0; i < mgp->num_slices; i++) {
1012 ss = &mgp->ss[i];
1013 ss->irq_claim =
1014 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1015 }
df30a740
BG		 1016 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1017 &cmd, 0);
1018 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1019
0da34b6d
BG		 1020 status |= myri10ge_send_cmd
1021 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1022 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1023 if (status != 0) {
1024 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1025 return status;
1026 }
40f6cff5 1027 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1028
5dd2d332 1029#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1030 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1031 dca_tag_off = cmd.data0;
1032 for (i = 0; i < mgp->num_slices; i++) {
1033 ss = &mgp->ss[i];
1034 if (status == 0) {
1035 ss->dca_tag = (__iomem __be32 *)
1036 (mgp->sram + dca_tag_off + 4 * i);
1037 } else {
1038 ss->dca_tag = NULL;
1039 }
1040 }
4ee2ac51 1041#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1042
0da34b6d 1043 /* reset mcp/driver shared state back to 0 */
0dcffac1 1044
c58ac5ca 1045 mgp->link_changes = 0;
0dcffac1
BG		 1046 for (i = 0; i < mgp->num_slices; i++) {
1047 ss = &mgp->ss[i];
1048
1049 memset(ss->rx_done.entry, 0, bytes);
1050 ss->tx.req = 0;
1051 ss->tx.done = 0;
1052 ss->tx.pkt_start = 0;
1053 ss->tx.pkt_done = 0;
1054 ss->rx_big.cnt = 0;
1055 ss->rx_small.cnt = 0;
1056 ss->rx_done.idx = 0;
1057 ss->rx_done.cnt = 0;
1058 ss->tx.wake_queue = 0;
1059 ss->tx.stop_queue = 0;
1060 }
1061
0da34b6d 1062 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1063 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1064 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1065 return status;
1066}
1067
5dd2d332 1068#ifdef CONFIG_MYRI10GE_DCA
ef09aadf
AG		 1069static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
1070{
9503e255 1071 int ret;
ef09aadf
AG		 1072 u16 ctl;
1073
9503e255 1074 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &ctl);
b3b6ae2c 1075
ef09aadf
AG		 1076 ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
1077 if (ret != on) {
1078 ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1079 ctl |= (on << 4);
9503e255 1080 pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, ctl);
ef09aadf
AG		 1081 }
1082 return ret;
1083}
1084
981813d8
BG		 1085static void
1086myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1087{
981813d8
BG		 1088 ss->cached_dca_tag = tag;
1089 put_be32(htonl(tag), ss->dca_tag);
1090}
1091
1092static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1093{
1094 int cpu = get_cpu();
1095 int tag;
1096
1097 if (cpu != ss->cpu) {
ef09aadf 1098 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
981813d8
BG		 1099 if (ss->cached_dca_tag != tag)
1100 myri10ge_write_dca(ss, cpu, tag);
ef09aadf 1101 ss->cpu = cpu;
981813d8
BG		 1102 }
1103 put_cpu();
1104}
1105
1106static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1107{
1108 int err, i;
1109 struct pci_dev *pdev = mgp->pdev;
1110
1111 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1112 return;
1113 if (!myri10ge_dca) {
1114 dev_err(&pdev->dev, "dca disabled by administrator\n");
1115 return;
1116 }
1117 err = dca_add_requester(&pdev->dev);
1118 if (err) {
330554cb
BG		 1119 if (err != -ENODEV)
1120 dev_err(&pdev->dev,
1121 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1122 return;
1123 }
ef09aadf 1124 mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
981813d8 1125 mgp->dca_enabled = 1;
ef09aadf
AG		 1126 for (i = 0; i < mgp->num_slices; i++) {
1127 mgp->ss[i].cpu = -1;
1128 mgp->ss[i].cached_dca_tag = -1;
1129 myri10ge_update_dca(&mgp->ss[i]);
b3b6ae2c 1130 }
981813d8
BG		 1131}
1132
1133static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1134{
1135 struct pci_dev *pdev = mgp->pdev;
981813d8
BG		 1136
1137 if (!mgp->dca_enabled)
1138 return;
1139 mgp->dca_enabled = 0;
ef09aadf
AG		 1140 if (mgp->relaxed_order)
1141 myri10ge_toggle_relaxed(pdev, 1);
b3b6ae2c 1142 dca_remove_requester(&pdev->dev);
981813d8
BG		 1143}
1144
1145static int myri10ge_notify_dca_device(struct device *dev, void *data)
1146{
1147 struct myri10ge_priv *mgp;
1148 unsigned long event;
1149
1150 mgp = dev_get_drvdata(dev);
1151 event = *(unsigned long *)data;
1152
1153 if (event == DCA_PROVIDER_ADD)
1154 myri10ge_setup_dca(mgp);
1155 else if (event == DCA_PROVIDER_REMOVE)
1156 myri10ge_teardown_dca(mgp);
1157 return 0;
1158}
4ee2ac51 1159#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1160
0da34b6d
BG		 1161static inline void
1162myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1163 struct mcp_kreq_ether_recv *src)
1164{
40f6cff5 1165 __be32 low;
0da34b6d
BG		 1166
1167 low = src->addr_low;
284901a9 1168 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1169 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1170 mb();
1171 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1172 mb();
1173 src->addr_low = low;
40f6cff5 1174 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1175 mb();
1176}
1177
40f6cff5 1178static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1179{
1180 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1181
40f6cff5 1182 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1183 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1184 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1185 skb->csum = hw_csum;
84fa7933 1186 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1187 }
1188}
1189
dd50f336
BG		 1190static void
1191myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1192 int bytes, int watchdog)
1193{
1194 struct page *page;
1195 int idx;
2a3f2790
BG		 1196#if MYRI10GE_ALLOC_SIZE > 4096
1197 int end_offset;
1198#endif
dd50f336
BG		 1199
1200 if (unlikely(rx->watchdog_needed && !watchdog))
1201 return;
1202
1203 /* try to refill entire ring */
1204 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1205 idx = rx->fill_cnt & rx->mask;
ae8509b1 1206 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1207 /* we can use part of previous page */
1208 get_page(rx->page);
1209 } else {
1210 /* we need a new page */
1211 page =
1212 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1213 MYRI10GE_ALLOC_ORDER);
1214 if (unlikely(page == NULL)) {
1215 if (rx->fill_cnt - rx->cnt < 16)
1216 rx->watchdog_needed = 1;
1217 return;
1218 }
1219 rx->page = page;
1220 rx->page_offset = 0;
1221 rx->bus = pci_map_page(mgp->pdev, page, 0,
1222 MYRI10GE_ALLOC_SIZE,
1223 PCI_DMA_FROMDEVICE);
1224 }
1225 rx->info[idx].page = rx->page;
1226 rx->info[idx].page_offset = rx->page_offset;
1227 /* note that this is the address of the start of the
1228 * page */
c755b4b6 1229 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
dd50f336
BG		 1230 rx->shadow[idx].addr_low =
1231 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1232 rx->shadow[idx].addr_high =
1233 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1234
1235 /* start next packet on a cacheline boundary */
1236 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1237
1238#if MYRI10GE_ALLOC_SIZE > 4096
1239 /* don't cross a 4KB boundary */
2a3f2790
BG		 1240 end_offset = rx->page_offset + bytes - 1;
1241 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1242 rx->page_offset = end_offset & ~4095;
ae8509b1 1243#endif
dd50f336
BG		 1244 rx->fill_cnt++;
1245
1246 /* copy 8 descriptors to the firmware at a time */
1247 if ((idx & 7) == 7) {
e454e7e2
BG		 1248 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1249 &rx->shadow[idx - 7]);
dd50f336
BG		 1250 }
1251 }
1252}
1253
1254static inline void
1255myri10ge_unmap_rx_page(struct pci_dev *pdev,
1256 struct myri10ge_rx_buffer_state *info, int bytes)
1257{
1258 /* unmap the recvd page if we're the only or last user of it */
1259 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1260 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
c755b4b6 1261 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
dd50f336
BG		 1262 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1263 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1264 }
1265}
1266
dd50f336 1267static inline int
4ca3221f 1268myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum)
dd50f336 1269{
b53bef84 1270 struct myri10ge_priv *mgp = ss->mgp;
dd50f336 1271 struct sk_buff *skb;
4ca3221f 1272 struct skb_frag_struct *rx_frags;
b3cd9657 1273 struct myri10ge_rx_buf *rx;
4ca3221f 1274 int i, idx, remainder, bytes;
dd50f336
BG		 1275 struct pci_dev *pdev = mgp->pdev;
1276 struct net_device *dev = mgp->dev;
1277 u8 *va;
1278
b3cd9657
SG		 1279 if (len <= mgp->small_bytes) {
1280 rx = &ss->rx_small;
1281 bytes = mgp->small_bytes;
1282 } else {
1283 rx = &ss->rx_big;
1284 bytes = mgp->big_bytes;
1285 }
1286
dd50f336
BG		 1287 len += MXGEFW_PAD;
1288 idx = rx->cnt & rx->mask;
1289 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1290 prefetch(va);
4ca3221f
AG		 1291
1292 skb = napi_get_frags(&ss->napi);
1293 if (unlikely(skb == NULL)) {
1294 ss->stats.rx_dropped++;
1295 for (i = 0, remainder = len; remainder > 0; i++) {
1296 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1297 put_page(rx->info[idx].page);
1298 rx->cnt++;
1299 idx = rx->cnt & rx->mask;
1300 remainder -= MYRI10GE_ALLOC_SIZE;
1301 }
1302 return 0;
1303 }
1304 rx_frags = skb_shinfo(skb)->frags;
dd50f336
BG		 1305 /* Fill skb_frag_struct(s) with data from our receive */
1306 for (i = 0, remainder = len; remainder > 0; i++) {
1307 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
4ca3221f
AG		 1308 skb_fill_page_desc(skb, i, rx->info[idx].page,
1309 rx->info[idx].page_offset,
1310 remainder < MYRI10GE_ALLOC_SIZE ?
1311 remainder : MYRI10GE_ALLOC_SIZE);
dd50f336
BG		 1312 rx->cnt++;
1313 idx = rx->cnt & rx->mask;
1314 remainder -= MYRI10GE_ALLOC_SIZE;
1315 }
1316
4ca3221f
AG		 1317 /* remove padding */
1318 rx_frags[0].page_offset += MXGEFW_PAD;
1319 rx_frags[0].size -= MXGEFW_PAD;
1320 len -= MXGEFW_PAD;
dd50f336 1321
4ca3221f
AG		 1322 skb->len = len;
1323 skb->data_len = len;
1324 skb->truesize += len;
1325 if (dev->features & NETIF_F_RXCSUM) {
1326 skb->ip_summed = CHECKSUM_COMPLETE;
1327 skb->csum = csum;
dd50f336 1328 }
0c8dfc83 1329 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
dd50f336 1330
4ca3221f 1331 napi_gro_frags(&ss->napi);
dd50f336
BG		 1332 return 1;
1333}
1334
b53bef84
BG		 1335static inline void
1336myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1337{
b53bef84
BG		 1338 struct pci_dev *pdev = ss->mgp->pdev;
1339 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1340 struct netdev_queue *dev_queue;
0da34b6d
BG		 1341 struct sk_buff *skb;
1342 int idx, len;
0da34b6d
BG		 1343
1344 while (tx->pkt_done != mcp_index) {
1345 idx = tx->done & tx->mask;
1346 skb = tx->info[idx].skb;
1347
1348 /* Mark as free */
1349 tx->info[idx].skb = NULL;
1350 if (tx->info[idx].last) {
1351 tx->pkt_done++;
1352 tx->info[idx].last = 0;
1353 }
1354 tx->done++;
c755b4b6
FT		 1355 len = dma_unmap_len(&tx->info[idx], len);
1356 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 1357 if (skb) {
b53bef84
BG		 1358 ss->stats.tx_bytes += skb->len;
1359 ss->stats.tx_packets++;
0da34b6d
BG		 1360 dev_kfree_skb_irq(skb);
1361 if (len)
1362 pci_unmap_single(pdev,
c755b4b6 1363 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1364 bus), len,
1365 PCI_DMA_TODEVICE);
1366 } else {
1367 if (len)
1368 pci_unmap_page(pdev,
c755b4b6 1369 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1370 bus), len,
1371 PCI_DMA_TODEVICE);
1372 }
0da34b6d 1373 }
236bb5e6
BG		 1374
1375 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1376 /*
1377 * Make a minimal effort to prevent the NIC from polling an
1378 * idle tx queue. If we can't get the lock we leave the queue
1379 * active. In this case, either a thread was about to start
1380 * using the queue anyway, or we lost a race and the NIC will
1381 * waste some of its resources polling an inactive queue for a
1382 * while.
1383 */
1384
1385 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1386 __netif_tx_trylock(dev_queue)) {
1387 if (tx->req == tx->done) {
1388 tx->queue_active = 0;
1389 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1390 mb();
6824a105 1391 mmiowb();
236bb5e6
BG		 1392 }
1393 __netif_tx_unlock(dev_queue);
1394 }
1395
0da34b6d 1396 /* start the queue if we've stopped it */
8e95a202 1397 if (netif_tx_queue_stopped(dev_queue) &&
3b20b2dc
JM		 1398 tx->req - tx->done < (tx->mask >> 1) &&
1399 ss->mgp->running == MYRI10GE_ETH_RUNNING) {
b53bef84 1400 tx->wake_queue++;
236bb5e6 1401 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1402 }
1403}
1404
b53bef84
BG		 1405static inline int
1406myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1407{
b53bef84
BG		 1408 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1409 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1410 unsigned long rx_bytes = 0;
1411 unsigned long rx_packets = 0;
1412 unsigned long rx_ok;
0da34b6d
BG		 1413 int idx = rx_done->idx;
1414 int cnt = rx_done->cnt;
bea3348e 1415 int work_done = 0;
0da34b6d 1416 u16 length;
40f6cff5 1417 __wsum checksum;
0da34b6d 1418
c956a240 1419 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1420 length = ntohs(rx_done->entry[idx].length);
1421 rx_done->entry[idx].length = 0;
40f6cff5 1422 checksum = csum_unfold(rx_done->entry[idx].checksum);
4ca3221f 1423 rx_ok = myri10ge_rx_done(ss, length, checksum);
0da34b6d
BG		 1424 rx_packets += rx_ok;
1425 rx_bytes += rx_ok * (unsigned long)length;
1426 cnt++;
014377a1 1427 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1428 work_done++;
0da34b6d
BG		 1429 }
1430 rx_done->idx = idx;
1431 rx_done->cnt = cnt;
b53bef84
BG		 1432 ss->stats.rx_packets += rx_packets;
1433 ss->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1434
1435 /* restock receive rings if needed */
b53bef84
BG		 1436 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1437 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1438 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1439 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1440 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1441
bea3348e 1442 return work_done;
0da34b6d
BG		 1443}
1444
1445static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1446{
0dcffac1 1447 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1448
1449 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1450 unsigned link_up = ntohl(stats->link_up);
1451 if (mgp->link_state != link_up) {
1452 mgp->link_state = link_up;
1453
1454 if (mgp->link_state == MXGEFW_LINK_UP) {
b3b6ae2c 1455 netif_info(mgp, link, mgp->dev, "link up\n");
0da34b6d 1456 netif_carrier_on(mgp->dev);
c58ac5ca 1457 mgp->link_changes++;
0da34b6d 1458 } else {
b3b6ae2c
JM		 1459 netif_info(mgp, link, mgp->dev, "link %s\n",
1460 (link_up == MXGEFW_LINK_MYRINET ?
78ca90ea 1461 "mismatch (Myrinet detected)" :
b3b6ae2c 1462 "down"));
0da34b6d 1463 netif_carrier_off(mgp->dev);
c58ac5ca 1464 mgp->link_changes++;
0da34b6d
BG		 1465 }
1466 }
1467 if (mgp->rdma_tags_available !=
b53bef84 1468 ntohl(stats->rdma_tags_available)) {
0da34b6d 1469 mgp->rdma_tags_available =
b53bef84 1470 ntohl(stats->rdma_tags_available);
78ca90ea
JP		 1471 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1472 mgp->rdma_tags_available);
0da34b6d
BG		 1473 }
1474 mgp->down_cnt += stats->link_down;
1475 if (stats->link_down)
1476 wake_up(&mgp->down_wq);
1477 }
1478}
1479
bea3348e 1480static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1481{
b53bef84
BG		 1482 struct myri10ge_slice_state *ss =
1483 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1484 int work_done;
0da34b6d 1485
5dd2d332 1486#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1487 if (ss->mgp->dca_enabled)
1488 myri10ge_update_dca(ss);
1489#endif
1490
0da34b6d 1491 /* process as many rx events as NAPI will allow */
b53bef84 1492 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1493
4ec24119 1494 if (work_done < budget) {
288379f0 1495 napi_complete(napi);
b53bef84 1496 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1497 }
bea3348e 1498 return work_done;
0da34b6d
BG		 1499}
1500
7d12e780 1501static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1502{
b53bef84
BG		 1503 struct myri10ge_slice_state *ss = arg;
1504 struct myri10ge_priv *mgp = ss->mgp;
1505 struct mcp_irq_data *stats = ss->fw_stats;
1506 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1507 u32 send_done_count;
1508 int i;
1509
236bb5e6
BG		 1510 /* an interrupt on a non-zero receive-only slice is implicitly
1511 * valid since MSI-X irqs are not shared */
1512 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1513 napi_schedule(&ss->napi);
807540ba 1514 return IRQ_HANDLED;
0dcffac1
BG		 1515 }
1516
0da34b6d
BG		 1517 /* make sure it is our IRQ, and that the DMA has finished */
1518 if (unlikely(!stats->valid))
807540ba 1519 return IRQ_NONE;
0da34b6d
BG		 1520
1521 /* low bit indicates receives are present, so schedule
1522 * napi poll handler */
1523 if (stats->valid & 1)
288379f0 1524 napi_schedule(&ss->napi);
0da34b6d 1525
0dcffac1 1526 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1527 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1528 if (!myri10ge_deassert_wait)
1529 stats->valid = 0;
1530 mb();
1531 } else
1532 stats->valid = 0;
1533
1534 /* Wait for IRQ line to go low, if using INTx */
1535 i = 0;
1536 while (1) {
1537 i++;
1538 /* check for transmit completes and receives */
1539 send_done_count = ntohl(stats->send_done_count);
1540 if (send_done_count != tx->pkt_done)
b53bef84 1541 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d 1542 if (unlikely(i > myri10ge_max_irq_loops)) {
b3b6ae2c 1543 netdev_warn(mgp->dev, "irq stuck?\n");
0da34b6d
BG		 1544 stats->valid = 0;
1545 schedule_work(&mgp->watchdog_work);
1546 }
1547 if (likely(stats->valid == 0))
1548 break;
1549 cpu_relax();
1550 barrier();
1551 }
1552
236bb5e6
BG		 1553 /* Only slice 0 updates stats */
1554 if (ss == mgp->ss)
1555 myri10ge_check_statblock(mgp);
0da34b6d 1556
b53bef84 1557 put_be32(htonl(3), ss->irq_claim + 1);
807540ba 1558 return IRQ_HANDLED;
0da34b6d
BG		 1559}
1560
1561static int
1562myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1563{
c0bf8801
BG		 1564 struct myri10ge_priv *mgp = netdev_priv(netdev);
1565 char *ptr;
1566 int i;
1567
0da34b6d 1568 cmd->autoneg = AUTONEG_DISABLE;
70739497 1569 ethtool_cmd_speed_set(cmd, SPEED_10000);
0da34b6d 1570 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1571
1572 /*
1573 * parse the product code to deterimine the interface type
1574 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1575 * after the 3rd dash in the driver's cached copy of the
1576 * EEPROM's product code string.
1577 */
1578 ptr = mgp->product_code_string;
1579 if (ptr == NULL) {
78ca90ea 1580 netdev_err(netdev, "Missing product code\n");
c0bf8801
BG		 1581 return 0;
1582 }
1583 for (i = 0; i < 3; i++, ptr++) {
1584 ptr = strchr(ptr, '-');
1585 if (ptr == NULL) {
78ca90ea
JP		 1586 netdev_err(netdev, "Invalid product code %s\n",
1587 mgp->product_code_string);
c0bf8801
BG		 1588 return 0;
1589 }
1590 }
196f17eb
BG		 1591 if (*ptr == '2')
1592 ptr++;
1593 if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1594 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
c0bf8801 1595 cmd->port = PORT_FIBRE;
196f17eb
BG		 1596 cmd->supported |= SUPPORTED_FIBRE;
1597 cmd->advertising |= ADVERTISED_FIBRE;
1598 } else {
1599 cmd->port = PORT_OTHER;
c0bf8801 1600 }
196f17eb
BG		 1601 if (*ptr == 'R' || *ptr == 'S')
1602 cmd->transceiver = XCVR_EXTERNAL;
1603 else
1604 cmd->transceiver = XCVR_INTERNAL;
1605
0da34b6d
BG		 1606 return 0;
1607}
1608
1609static void
1610myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1611{
1612 struct myri10ge_priv *mgp = netdev_priv(netdev);
1613
1614 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1615 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1616 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1617 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1618}
1619
1620static int
1621myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1622{
1623 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1624
0da34b6d
BG		 1625 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1626 return 0;
1627}
1628
1629static int
1630myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1631{
1632 struct myri10ge_priv *mgp = netdev_priv(netdev);
1633
1634 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1635 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1636 return 0;
1637}
1638
1639static void
1640myri10ge_get_pauseparam(struct net_device *netdev,
1641 struct ethtool_pauseparam *pause)
1642{
1643 struct myri10ge_priv *mgp = netdev_priv(netdev);
1644
1645 pause->autoneg = 0;
1646 pause->rx_pause = mgp->pause;
1647 pause->tx_pause = mgp->pause;
1648}
1649
1650static int
1651myri10ge_set_pauseparam(struct net_device *netdev,
1652 struct ethtool_pauseparam *pause)
1653{
1654 struct myri10ge_priv *mgp = netdev_priv(netdev);
1655
1656 if (pause->tx_pause != mgp->pause)
1657 return myri10ge_change_pause(mgp, pause->tx_pause);
1658 if (pause->rx_pause != mgp->pause)
2488f56d 1659 return myri10ge_change_pause(mgp, pause->rx_pause);
0da34b6d
BG		 1660 if (pause->autoneg != 0)
1661 return -EINVAL;
1662 return 0;
1663}
1664
1665static void
1666myri10ge_get_ringparam(struct net_device *netdev,
1667 struct ethtool_ringparam *ring)
1668{
1669 struct myri10ge_priv *mgp = netdev_priv(netdev);
1670
0dcffac1
BG		 1671 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1672 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1673 ring->rx_jumbo_max_pending = 0;
6498be3f 1674 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1675 ring->rx_mini_pending = ring->rx_mini_max_pending;
1676 ring->rx_pending = ring->rx_max_pending;
1677 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1678 ring->tx_pending = ring->tx_max_pending;
1679}
1680
b53bef84 1681static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1682 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1683 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1684 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1685 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1686 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1687 "tx_heartbeat_errors", "tx_window_errors",
1688 /* device-specific stats */
0dcffac1 1689 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1690 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1691 "serial_number", "watchdog_resets",
5dd2d332 1692#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1693 "dca_capable_firmware", "dca_device_present",
981813d8 1694#endif
c58ac5ca 1695 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1696 "dropped_link_error_or_filtered",
1697 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1698 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1699 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1700 "dropped_no_big_buffer"
1701};
1702
1703static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1704 "----------- slice ---------",
1705 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1706 "rx_small_cnt", "rx_big_cnt",
b3b6ae2c 1707 "wake_queue", "stop_queue", "tx_linearized",
0da34b6d
BG		 1708};
1709
1710#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1711#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1712#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1713
1714static void
1715myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1716{
0dcffac1
BG		 1717 struct myri10ge_priv *mgp = netdev_priv(netdev);
1718 int i;
1719
0da34b6d
BG		 1720 switch (stringset) {
1721 case ETH_SS_STATS:
b53bef84
BG		 1722 memcpy(data, *myri10ge_gstrings_main_stats,
1723 sizeof(myri10ge_gstrings_main_stats));
1724 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1725 for (i = 0; i < mgp->num_slices; i++) {
1726 memcpy(data, *myri10ge_gstrings_slice_stats,
1727 sizeof(myri10ge_gstrings_slice_stats));
1728 data += sizeof(myri10ge_gstrings_slice_stats);
1729 }
0da34b6d
BG		 1730 break;
1731 }
1732}
1733
b9f2c044 1734static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1735{
0dcffac1
BG		 1736 struct myri10ge_priv *mgp = netdev_priv(netdev);
1737
b9f2c044
JG		 1738 switch (sset) {
1739 case ETH_SS_STATS:
0dcffac1
BG		 1740 return MYRI10GE_MAIN_STATS_LEN +
1741 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1742 default:
1743 return -EOPNOTSUPP;
1744 }
0da34b6d
BG		 1745}
1746
1747static void
1748myri10ge_get_ethtool_stats(struct net_device *netdev,
1749 struct ethtool_stats *stats, u64 * data)
1750{
1751 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1752 struct myri10ge_slice_state *ss;
c5f7ef72 1753 struct rtnl_link_stats64 link_stats;
0dcffac1 1754 int slice;
0da34b6d
BG		 1755 int i;
1756
59081825 1757 /* force stats update */
306ff6eb 1758 memset(&link_stats, 0, sizeof(link_stats));
c5f7ef72 1759 (void)myri10ge_get_stats(netdev, &link_stats);
0da34b6d 1760 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
c5f7ef72 1761 data[i] = ((u64 *)&link_stats)[i];
0da34b6d 1762
b53bef84 1763 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1764 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1765 data[i++] = (unsigned int)mgp->pdev->irq;
1766 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1767 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1768 data[i++] = (unsigned int)mgp->read_dma;
1769 data[i++] = (unsigned int)mgp->write_dma;
1770 data[i++] = (unsigned int)mgp->read_write_dma;
1771 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1772 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1773#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1774 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1775 data[i++] = (unsigned int)(mgp->dca_enabled);
1776#endif
c58ac5ca 1777 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1778
1779 /* firmware stats are useful only in the first slice */
0dcffac1 1780 ss = &mgp->ss[0];
b53bef84
BG		 1781 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1782 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1783 data[i++] =
b53bef84
BG		 1784 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1785 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1786 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1787 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1788 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1789 data[i++] =
b53bef84
BG		 1790 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1791 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1792 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1793 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1794 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1795
0dcffac1
BG		 1796 for (slice = 0; slice < mgp->num_slices; slice++) {
1797 ss = &mgp->ss[slice];
1798 data[i++] = slice;
1799 data[i++] = (unsigned int)ss->tx.pkt_start;
1800 data[i++] = (unsigned int)ss->tx.pkt_done;
1801 data[i++] = (unsigned int)ss->tx.req;
1802 data[i++] = (unsigned int)ss->tx.done;
1803 data[i++] = (unsigned int)ss->rx_small.cnt;
1804 data[i++] = (unsigned int)ss->rx_big.cnt;
1805 data[i++] = (unsigned int)ss->tx.wake_queue;
1806 data[i++] = (unsigned int)ss->tx.stop_queue;
1807 data[i++] = (unsigned int)ss->tx.linearized;
0dcffac1 1808 }
0da34b6d
BG		 1809}
1810
c58ac5ca
BG		 1811static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1812{
1813 struct myri10ge_priv *mgp = netdev_priv(netdev);
1814 mgp->msg_enable = value;
1815}
1816
1817static u32 myri10ge_get_msglevel(struct net_device *netdev)
1818{
1819 struct myri10ge_priv *mgp = netdev_priv(netdev);
1820 return mgp->msg_enable;
1821}
1822
5dcd8467
JM		 1823/*
1824 * Use a low-level command to change the LED behavior. Rather than
1825 * blinking (which is the normal case), when identify is used, the
1826 * yellow LED turns solid.
1827 */
1828static int myri10ge_led(struct myri10ge_priv *mgp, int on)
1829{
1830 struct mcp_gen_header *hdr;
1831 struct device *dev = &mgp->pdev->dev;
1832 size_t hdr_off, pattern_off, hdr_len;
1833 u32 pattern = 0xfffffffe;
1834
1835 /* find running firmware header */
1836 hdr_off = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
1837 if ((hdr_off & 3) || hdr_off + sizeof(*hdr) > mgp->sram_size) {
1838 dev_err(dev, "Running firmware has bad header offset (%d)\n",
1839 (int)hdr_off);
1840 return -EIO;
1841 }
1842 hdr_len = swab32(readl(mgp->sram + hdr_off +
1843 offsetof(struct mcp_gen_header, header_length)));
1844 pattern_off = hdr_off + offsetof(struct mcp_gen_header, led_pattern);
1845 if (pattern_off >= (hdr_len + hdr_off)) {
1846 dev_info(dev, "Firmware does not support LED identification\n");
1847 return -EINVAL;
1848 }
1849 if (!on)
1850 pattern = swab32(readl(mgp->sram + pattern_off + 4));
1851 writel(htonl(pattern), mgp->sram + pattern_off);
1852 return 0;
1853}
1854
1855static int
1856myri10ge_phys_id(struct net_device *netdev, enum ethtool_phys_id_state state)
1857{
1858 struct myri10ge_priv *mgp = netdev_priv(netdev);
1859 int rc;
1860
1861 switch (state) {
1862 case ETHTOOL_ID_ACTIVE:
1863 rc = myri10ge_led(mgp, 1);
1864 break;
1865
1866 case ETHTOOL_ID_INACTIVE:
1867 rc = myri10ge_led(mgp, 0);
1868 break;
1869
1870 default:
1871 rc = -EINVAL;
1872 }
1873
1874 return rc;
1875}
1876
7282d491 1877static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1878 .get_settings = myri10ge_get_settings,
1879 .get_drvinfo = myri10ge_get_drvinfo,
1880 .get_coalesce = myri10ge_get_coalesce,
1881 .set_coalesce = myri10ge_set_coalesce,
1882 .get_pauseparam = myri10ge_get_pauseparam,
1883 .set_pauseparam = myri10ge_set_pauseparam,
1884 .get_ringparam = myri10ge_get_ringparam,
6ffdd071 1885 .get_link = ethtool_op_get_link,
0da34b6d 1886 .get_strings = myri10ge_get_strings,
b9f2c044 1887 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1888 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1889 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d 1890 .get_msglevel = myri10ge_get_msglevel,
5dcd8467 1891 .set_phys_id = myri10ge_phys_id,
0da34b6d
BG		 1892};
1893
b53bef84 1894static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1895{
b53bef84 1896 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1897 struct myri10ge_cmd cmd;
b53bef84 1898 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1899 int tx_ring_size, rx_ring_size;
1900 int tx_ring_entries, rx_ring_entries;
0dcffac1 1901 int i, slice, status;
0da34b6d
BG		 1902 size_t bytes;
1903
0da34b6d 1904 /* get ring sizes */
0dcffac1
BG		 1905 slice = ss - mgp->ss;
1906 cmd.data0 = slice;
0da34b6d
BG		 1907 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1908 tx_ring_size = cmd.data0;
0dcffac1 1909 cmd.data0 = slice;
0da34b6d 1910 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1911 if (status != 0)
1912 return status;
0da34b6d
BG		 1913 rx_ring_size = cmd.data0;
1914
1915 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1916 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1917 ss->tx.mask = tx_ring_entries - 1;
1918 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1919
355c7265
BG		 1920 status = -ENOMEM;
1921
0da34b6d
BG		 1922 /* allocate the host shadow rings */
1923
1924 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1925 * sizeof(*ss->tx.req_list);
1926 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1927 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1928 goto abort_with_nothing;
1929
1930 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1931 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1932 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 1933 ss->tx.queue_active = 0;
0da34b6d 1934
b53bef84
BG		 1935 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1936 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1937 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1938 goto abort_with_tx_req_bytes;
1939
b53bef84
BG		 1940 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1941 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1942 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1943 goto abort_with_rx_small_shadow;
1944
1945 /* allocate the host info rings */
1946
b53bef84
BG		 1947 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1948 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1949 if (ss->tx.info == NULL)
0da34b6d
BG		 1950 goto abort_with_rx_big_shadow;
1951
b53bef84
BG		 1952 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1953 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1954 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1955 goto abort_with_tx_info;
1956
b53bef84
BG		 1957 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1958 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1959 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1960 goto abort_with_rx_small_info;
1961
1962 /* Fill the receive rings */
b53bef84
BG		 1963 ss->rx_big.cnt = 0;
1964 ss->rx_small.cnt = 0;
1965 ss->rx_big.fill_cnt = 0;
1966 ss->rx_small.fill_cnt = 0;
1967 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1968 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1969 ss->rx_small.watchdog_needed = 0;
1970 ss->rx_big.watchdog_needed = 0;
4b47638a
JM		 1971 if (mgp->small_bytes == 0) {
1972 ss->rx_small.fill_cnt = ss->rx_small.mask + 1;
1973 } else {
1974 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1975 mgp->small_bytes + MXGEFW_PAD, 0);
1976 }
0da34b6d 1977
b53bef84 1978 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
78ca90ea
JP		 1979 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
1980 slice, ss->rx_small.fill_cnt);
c7dab99b 1981 goto abort_with_rx_small_ring;
0da34b6d
BG		 1982 }
1983
b53bef84
BG		 1984 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1985 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
78ca90ea
JP		 1986 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
1987 slice, ss->rx_big.fill_cnt);
c7dab99b 1988 goto abort_with_rx_big_ring;
0da34b6d
BG		 1989 }
1990
1991 return 0;
1992
1993abort_with_rx_big_ring:
b53bef84
BG		 1994 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1995 int idx = i & ss->rx_big.mask;
1996 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 1997 mgp->big_bytes);
b53bef84 1998 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 1999 }
2000
2001abort_with_rx_small_ring:
4b47638a
JM		 2002 if (mgp->small_bytes == 0)
2003 ss->rx_small.fill_cnt = ss->rx_small.cnt;
b53bef84
BG		 2004 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2005 int idx = i & ss->rx_small.mask;
2006 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2007 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2008 put_page(ss->rx_small.info[idx].page);
0da34b6d 2009 }
c7dab99b 2010
b53bef84 2011 kfree(ss->rx_big.info);
0da34b6d
BG		 2012
2013abort_with_rx_small_info:
b53bef84 2014 kfree(ss->rx_small.info);
0da34b6d
BG		 2015
2016abort_with_tx_info:
b53bef84 2017 kfree(ss->tx.info);
0da34b6d
BG		 2018
2019abort_with_rx_big_shadow:
b53bef84 2020 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2021
2022abort_with_rx_small_shadow:
b53bef84 2023 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2024
2025abort_with_tx_req_bytes:
b53bef84
BG		 2026 kfree(ss->tx.req_bytes);
2027 ss->tx.req_bytes = NULL;
2028 ss->tx.req_list = NULL;
0da34b6d
BG		 2029
2030abort_with_nothing:
2031 return status;
2032}
2033
b53bef84 2034static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2035{
b53bef84 2036 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2037 struct sk_buff *skb;
2038 struct myri10ge_tx_buf *tx;
2039 int i, len, idx;
2040
0dcffac1
BG		 2041 /* If not allocated, skip it */
2042 if (ss->tx.req_list == NULL)
2043 return;
2044
b53bef84
BG		 2045 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2046 idx = i & ss->rx_big.mask;
2047 if (i == ss->rx_big.fill_cnt - 1)
2048 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2049 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2050 mgp->big_bytes);
b53bef84 2051 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2052 }
2053
4b47638a
JM		 2054 if (mgp->small_bytes == 0)
2055 ss->rx_small.fill_cnt = ss->rx_small.cnt;
b53bef84
BG		 2056 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2057 idx = i & ss->rx_small.mask;
2058 if (i == ss->rx_small.fill_cnt - 1)
2059 ss->rx_small.info[idx].page_offset =
c7dab99b 2060 MYRI10GE_ALLOC_SIZE;
b53bef84 2061 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2062 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2063 put_page(ss->rx_small.info[idx].page);
c7dab99b 2064 }
b53bef84 2065 tx = &ss->tx;
0da34b6d
BG		 2066 while (tx->done != tx->req) {
2067 idx = tx->done & tx->mask;
2068 skb = tx->info[idx].skb;
2069
2070 /* Mark as free */
2071 tx->info[idx].skb = NULL;
2072 tx->done++;
c755b4b6
FT		 2073 len = dma_unmap_len(&tx->info[idx], len);
2074 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 2075 if (skb) {
b53bef84 2076 ss->stats.tx_dropped++;
0da34b6d
BG		 2077 dev_kfree_skb_any(skb);
2078 if (len)
2079 pci_unmap_single(mgp->pdev,
c755b4b6 2080 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2081 bus), len,
2082 PCI_DMA_TODEVICE);
2083 } else {
2084 if (len)
2085 pci_unmap_page(mgp->pdev,
c755b4b6 2086 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2087 bus), len,
2088 PCI_DMA_TODEVICE);
2089 }
2090 }
b53bef84 2091 kfree(ss->rx_big.info);
0da34b6d 2092
b53bef84 2093 kfree(ss->rx_small.info);
0da34b6d 2094
b53bef84 2095 kfree(ss->tx.info);
0da34b6d 2096
b53bef84 2097 kfree(ss->rx_big.shadow);
0da34b6d 2098
b53bef84 2099 kfree(ss->rx_small.shadow);
0da34b6d 2100
b53bef84
BG		 2101 kfree(ss->tx.req_bytes);
2102 ss->tx.req_bytes = NULL;
2103 ss->tx.req_list = NULL;
0da34b6d
BG		 2104}
2105
df30a740
BG		 2106static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2107{
2108 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2109 struct myri10ge_slice_state *ss;
2110 struct net_device *netdev = mgp->dev;
2111 int i;
df30a740
BG		 2112 int status;
2113
0dcffac1
BG		 2114 mgp->msi_enabled = 0;
2115 mgp->msix_enabled = 0;
2116 status = 0;
df30a740 2117 if (myri10ge_msi) {
0dcffac1
BG		 2118 if (mgp->num_slices > 1) {
2119 status =
2120 pci_enable_msix(pdev, mgp->msix_vectors,
2121 mgp->num_slices);
2122 if (status == 0) {
2123 mgp->msix_enabled = 1;
2124 } else {
2125 dev_err(&pdev->dev,
2126 "Error %d setting up MSI-X\n", status);
2127 return status;
2128 }
2129 }
2130 if (mgp->msix_enabled == 0) {
2131 status = pci_enable_msi(pdev);
2132 if (status != 0) {
2133 dev_err(&pdev->dev,
2134 "Error %d setting up MSI; falling back to xPIC\n",
2135 status);
2136 } else {
2137 mgp->msi_enabled = 1;
2138 }
2139 }
df30a740 2140 }
0dcffac1
BG		 2141 if (mgp->msix_enabled) {
2142 for (i = 0; i < mgp->num_slices; i++) {
2143 ss = &mgp->ss[i];
2144 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2145 "%s:slice-%d", netdev->name, i);
2146 status = request_irq(mgp->msix_vectors[i].vector,
2147 myri10ge_intr, 0, ss->irq_desc,
2148 ss);
2149 if (status != 0) {
2150 dev_err(&pdev->dev,
2151 "slice %d failed to allocate IRQ\n", i);
2152 i--;
2153 while (i >= 0) {
2154 free_irq(mgp->msix_vectors[i].vector,
2155 &mgp->ss[i]);
2156 i--;
2157 }
2158 pci_disable_msix(pdev);
2159 return status;
2160 }
2161 }
2162 } else {
2163 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2164 mgp->dev->name, &mgp->ss[0]);
2165 if (status != 0) {
2166 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2167 if (mgp->msi_enabled)
2168 pci_disable_msi(pdev);
2169 }
df30a740
BG		 2170 }
2171 return status;
2172}
2173
2174static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2175{
2176 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2177 int i;
df30a740 2178
0dcffac1
BG		 2179 if (mgp->msix_enabled) {
2180 for (i = 0; i < mgp->num_slices; i++)
2181 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2182 } else {
2183 free_irq(pdev->irq, &mgp->ss[0]);
2184 }
df30a740
BG		 2185 if (mgp->msi_enabled)
2186 pci_disable_msi(pdev);
0dcffac1
BG		 2187 if (mgp->msix_enabled)
2188 pci_disable_msix(pdev);
df30a740
BG		 2189}
2190
77929732
BG		 2191static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2192{
2193 struct myri10ge_cmd cmd;
2194 struct myri10ge_slice_state *ss;
2195 int status;
2196
2197 ss = &mgp->ss[slice];
236bb5e6
BG		 2198 status = 0;
2199 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2200 cmd.data0 = slice;
2201 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2202 &cmd, 0);
2203 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2204 (mgp->sram + cmd.data0);
2205 }
77929732
BG		 2206 cmd.data0 = slice;
2207 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2208 &cmd, 0);
2209 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2210 (mgp->sram + cmd.data0);
2211
2212 cmd.data0 = slice;
2213 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2214 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2215 (mgp->sram + cmd.data0);
2216
236bb5e6
BG		 2217 ss->tx.send_go = (__iomem __be32 *)
2218 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2219 ss->tx.send_stop = (__iomem __be32 *)
2220 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2221 return status;
2222
2223}
2224
2225static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2226{
2227 struct myri10ge_cmd cmd;
2228 struct myri10ge_slice_state *ss;
2229 int status;
2230
2231 ss = &mgp->ss[slice];
2232 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2233 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2234 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2235 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2236 if (status == -ENOSYS) {
2237 dma_addr_t bus = ss->fw_stats_bus;
2238 if (slice != 0)
2239 return -EINVAL;
2240 bus += offsetof(struct mcp_irq_data, send_done_count);
2241 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2242 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2243 status = myri10ge_send_cmd(mgp,
2244 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2245 &cmd, 0);
2246 /* Firmware cannot support multicast without STATS_DMA_V2 */
2247 mgp->fw_multicast_support = 0;
2248 } else {
2249 mgp->fw_multicast_support = 1;
2250 }
2251 return 0;
2252}
77929732 2253
0da34b6d
BG		 2254static int myri10ge_open(struct net_device *dev)
2255{
0dcffac1 2256 struct myri10ge_slice_state *ss;
b53bef84 2257 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2258 struct myri10ge_cmd cmd;
0dcffac1
BG		 2259 int i, status, big_pow2, slice;
2260 u8 *itable;
0da34b6d 2261
0da34b6d
BG		 2262 if (mgp->running != MYRI10GE_ETH_STOPPED)
2263 return -EBUSY;
2264
2265 mgp->running = MYRI10GE_ETH_STARTING;
2266 status = myri10ge_reset(mgp);
2267 if (status != 0) {
78ca90ea 2268 netdev_err(dev, "failed reset\n");
df30a740 2269 goto abort_with_nothing;
0da34b6d
BG		 2270 }
2271
0dcffac1
BG		 2272 if (mgp->num_slices > 1) {
2273 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2274 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2275 if (mgp->dev->real_num_tx_queues > 1)
2276 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2277 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2278 &cmd, 0);
2279 if (status != 0) {
78ca90ea 2280 netdev_err(dev, "failed to set number of slices\n");
0dcffac1
BG		 2281 goto abort_with_nothing;
2282 }
2283 /* setup the indirection table */
2284 cmd.data0 = mgp->num_slices;
2285 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2286 &cmd, 0);
2287
2288 status |= myri10ge_send_cmd(mgp,
2289 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2290 &cmd, 0);
2291 if (status != 0) {
78ca90ea 2292 netdev_err(dev, "failed to setup rss tables\n");
236bb5e6 2293 goto abort_with_nothing;
0dcffac1
BG		 2294 }
2295
2296 /* just enable an identity mapping */
2297 itable = mgp->sram + cmd.data0;
2298 for (i = 0; i < mgp->num_slices; i++)
2299 __raw_writeb(i, &itable[i]);
2300
2301 cmd.data0 = 1;
2302 cmd.data1 = myri10ge_rss_hash;
2303 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2304 &cmd, 0);
2305 if (status != 0) {
78ca90ea 2306 netdev_err(dev, "failed to enable slices\n");
0dcffac1
BG		 2307 goto abort_with_nothing;
2308 }
2309 }
2310
df30a740
BG		 2311 status = myri10ge_request_irq(mgp);
2312 if (status != 0)
2313 goto abort_with_nothing;
2314
0da34b6d
BG		 2315 /* decide what small buffer size to use. For good TCP rx
2316 * performance, it is important to not receive 1514 byte
2317 * frames into jumbo buffers, as it confuses the socket buffer
2318 * accounting code, leading to drops and erratic performance.
2319 */
2320
2321 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2322 /* enough for a TCP header */
2323 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2324 ? (128 - MXGEFW_PAD)
2325 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2326 else
de3c4507
BG		 2327 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2328 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2329
2330 /* Override the small buffer size? */
4b47638a 2331 if (myri10ge_small_bytes >= 0)
0da34b6d
BG		 2332 mgp->small_bytes = myri10ge_small_bytes;
2333
0da34b6d
BG		 2334 /* Firmware needs the big buff size as a power of 2. Lie and
2335 * tell him the buffer is larger, because we only use 1
2336 * buffer/pkt, and the mtu will prevent overruns.
2337 */
13348bee 2338 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2339 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2340 while (!is_power_of_2(big_pow2))
c7dab99b 2341 big_pow2++;
13348bee 2342 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2343 } else {
2344 big_pow2 = MYRI10GE_ALLOC_SIZE;
2345 mgp->big_bytes = big_pow2;
2346 }
2347
0dcffac1
BG		 2348 /* setup the per-slice data structures */
2349 for (slice = 0; slice < mgp->num_slices; slice++) {
2350 ss = &mgp->ss[slice];
2351
2352 status = myri10ge_get_txrx(mgp, slice);
2353 if (status != 0) {
78ca90ea 2354 netdev_err(dev, "failed to get ring sizes or locations\n");
0dcffac1
BG		 2355 goto abort_with_rings;
2356 }
2357 status = myri10ge_allocate_rings(ss);
2358 if (status != 0)
2359 goto abort_with_rings;
236bb5e6
BG		 2360
2361 /* only firmware which supports multiple TX queues
2362 * supports setting up the tx stats on non-zero
2363 * slices */
2364 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2365 status = myri10ge_set_stats(mgp, slice);
2366 if (status) {
78ca90ea 2367 netdev_err(dev, "Couldn't set stats DMA\n");
0dcffac1
BG		 2368 goto abort_with_rings;
2369 }
2370
0dcffac1
BG		 2371 /* must happen prior to any irq */
2372 napi_enable(&(ss)->napi);
2373 }
0da34b6d
BG		 2374
2375 /* now give firmware buffers sizes, and MTU */
2376 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2377 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2378 cmd.data0 = mgp->small_bytes;
2379 status |=
2380 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2381 cmd.data0 = big_pow2;
2382 status |=
2383 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2384 if (status) {
78ca90ea 2385 netdev_err(dev, "Couldn't set buffer sizes\n");
0da34b6d
BG		 2386 goto abort_with_rings;
2387 }
2388
0dcffac1
BG		 2389 /*
2390 * Set Linux style TSO mode; this is needed only on newer
2391 * firmware versions. Older versions default to Linux
2392 * style TSO
2393 */
2394 cmd.data0 = 0;
2395 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2396 if (status && status != -ENOSYS) {
78ca90ea 2397 netdev_err(dev, "Couldn't set TSO mode\n");
0da34b6d
BG		 2398 goto abort_with_rings;
2399 }
2400
66341fff 2401 mgp->link_state = ~0U;
0da34b6d
BG		 2402 mgp->rdma_tags_available = 15;
2403
0da34b6d
BG		 2404 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2405 if (status) {
78ca90ea 2406 netdev_err(dev, "Couldn't bring up link\n");
0da34b6d
BG		 2407 goto abort_with_rings;
2408 }
2409
0da34b6d
BG		 2410 mgp->running = MYRI10GE_ETH_RUNNING;
2411 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2412 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2413 netif_tx_wake_all_queues(dev);
2414
0da34b6d
BG		 2415 return 0;
2416
2417abort_with_rings:
051d36f3
BG		 2418 while (slice) {
2419 slice--;
2420 napi_disable(&mgp->ss[slice].napi);
2421 }
0dcffac1
BG		 2422 for (i = 0; i < mgp->num_slices; i++)
2423 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2424
df30a740
BG		 2425 myri10ge_free_irq(mgp);
2426
0da34b6d
BG		 2427abort_with_nothing:
2428 mgp->running = MYRI10GE_ETH_STOPPED;
2429 return -ENOMEM;
2430}
2431
2432static int myri10ge_close(struct net_device *dev)
2433{
b53bef84 2434 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2435 struct myri10ge_cmd cmd;
2436 int status, old_down_cnt;
0dcffac1 2437 int i;
0da34b6d 2438
0da34b6d
BG		 2439 if (mgp->running != MYRI10GE_ETH_RUNNING)
2440 return 0;
2441
0dcffac1 2442 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2443 return 0;
2444
2445 del_timer_sync(&mgp->watchdog_timer);
2446 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2447 for (i = 0; i < mgp->num_slices; i++) {
2448 napi_disable(&mgp->ss[i].napi);
2449 }
0da34b6d 2450 netif_carrier_off(dev);
236bb5e6
BG		 2451
2452 netif_tx_stop_all_queues(dev);
d0234215
BG		 2453 if (mgp->rebooted == 0) {
2454 old_down_cnt = mgp->down_cnt;
2455 mb();
2456 status =
2457 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2458 if (status)
78ca90ea 2459 netdev_err(dev, "Couldn't bring down link\n");
0da34b6d 2460
d0234215
BG		 2461 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2462 HZ);
2463 if (old_down_cnt == mgp->down_cnt)
78ca90ea 2464 netdev_err(dev, "never got down irq\n");
d0234215 2465 }
0da34b6d 2466 netif_tx_disable(dev);
df30a740 2467 myri10ge_free_irq(mgp);
0dcffac1
BG		 2468 for (i = 0; i < mgp->num_slices; i++)
2469 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2470
2471 mgp->running = MYRI10GE_ETH_STOPPED;
2472 return 0;
2473}
2474
2475/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2476 * backwards one at a time and handle ring wraps */
2477
2478static inline void
2479myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2480 struct mcp_kreq_ether_send *src, int cnt)
2481{
2482 int idx, starting_slot;
2483 starting_slot = tx->req;
2484 while (cnt > 1) {
2485 cnt--;
2486 idx = (starting_slot + cnt) & tx->mask;
2487 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2488 mb();
2489 }
2490}
2491
2492/*
2493 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2494 * at most 32 bytes at a time, so as to avoid involving the software
2495 * pio handler in the nic. We re-write the first segment's flags
2496 * to mark them valid only after writing the entire chain.
2497 */
2498
2499static inline void
2500myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2501 int cnt)
2502{
2503 int idx, i;
2504 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2505 struct mcp_kreq_ether_send *srcp;
2506 u8 last_flags;
2507
2508 idx = tx->req & tx->mask;
2509
2510 last_flags = src->flags;
2511 src->flags = 0;
2512 mb();
2513 dst = dstp = &tx->lanai[idx];
2514 srcp = src;
2515
2516 if ((idx + cnt) < tx->mask) {
2517 for (i = 0; i < (cnt - 1); i += 2) {
2518 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2519 mb(); /* force write every 32 bytes */
2520 srcp += 2;
2521 dstp += 2;
2522 }
2523 } else {
2524 /* submit all but the first request, and ensure
2525 * that it is submitted below */
2526 myri10ge_submit_req_backwards(tx, src, cnt);
2527 i = 0;
2528 }
2529 if (i < cnt) {
2530 /* submit the first request */
2531 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2532 mb(); /* barrier before setting valid flag */
2533 }
2534
2535 /* re-write the last 32-bits with the valid flags */
2536 src->flags = last_flags;
40f6cff5 2537 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2538 tx->req += cnt;
2539 mb();
2540}
2541
0da34b6d
BG		 2542/*
2543 * Transmit a packet. We need to split the packet so that a single
b53bef84 2544 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2545 * counting tricky. So rather than try to count segments up front, we
2546 * just give up if there are too few segments to hold a reasonably
2547 * fragmented packet currently available. If we run
2548 * out of segments while preparing a packet for DMA, we just linearize
2549 * it and try again.
2550 */
2551
61357325
SH		 2552static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2553 struct net_device *dev)
0da34b6d
BG		 2554{
2555 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2556 struct myri10ge_slice_state *ss;
0da34b6d 2557 struct mcp_kreq_ether_send *req;
b53bef84 2558 struct myri10ge_tx_buf *tx;
0da34b6d 2559 struct skb_frag_struct *frag;
236bb5e6 2560 struct netdev_queue *netdev_queue;
0da34b6d 2561 dma_addr_t bus;
40f6cff5
AV		 2562 u32 low;
2563 __be32 high_swapped;
0da34b6d
BG		 2564 unsigned int len;
2565 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2566 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2567 int cum_len, seglen, boundary, rdma_count;
2568 u8 flags, odd_flag;
2569
236bb5e6 2570 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2571 ss = &mgp->ss[queue];
2572 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2573 tx = &ss->tx;
236bb5e6 2574
0da34b6d
BG		 2575again:
2576 req = tx->req_list;
2577 avail = tx->mask - 1 - (tx->req - tx->done);
2578
2579 mss = 0;
2580 max_segments = MXGEFW_MAX_SEND_DESC;
2581
917690cd 2582 if (skb_is_gso(skb)) {
7967168c 2583 mss = skb_shinfo(skb)->gso_size;
917690cd 2584 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2585 }
0da34b6d
BG		 2586
2587 if ((unlikely(avail < max_segments))) {
2588 /* we are out of transmit resources */
b53bef84 2589 tx->stop_queue++;
236bb5e6 2590 netif_tx_stop_queue(netdev_queue);
5b548140 2591 return NETDEV_TX_BUSY;
0da34b6d
BG		 2592 }
2593
2594 /* Setup checksum offloading, if needed */
2595 cksum_offset = 0;
2596 pseudo_hdr_offset = 0;
2597 odd_flag = 0;
2598 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2599 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0d0b1672 2600 cksum_offset = skb_checksum_start_offset(skb);
ff1dcadb 2601 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2602 /* If the headers are excessively large, then we must
2603 * fall back to a software checksum */
4f93fde0
BG		 2604 if (unlikely(!mss && (cksum_offset > 255 ||
2605 pseudo_hdr_offset > 127))) {
84fa7933 2606 if (skb_checksum_help(skb))
0da34b6d
BG		 2607 goto drop;
2608 cksum_offset = 0;
2609 pseudo_hdr_offset = 0;
2610 } else {
0da34b6d
BG		 2611 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2612 flags |= MXGEFW_FLAGS_CKSUM;
2613 }
2614 }
2615
2616 cum_len = 0;
2617
0da34b6d
BG		 2618 if (mss) { /* TSO */
2619 /* this removes any CKSUM flag from before */
2620 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2621
2622 /* negative cum_len signifies to the
2623 * send loop that we are still in the
2624 * header portion of the TSO packet.
4f93fde0 2625 * TSO header can be at most 1KB long */
ab6a5bb6 2626 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2627
4f93fde0
BG		 2628 /* for IPv6 TSO, the checksum offset stores the
2629 * TCP header length, to save the firmware from
2630 * the need to parse the headers */
2631 if (skb_is_gso_v6(skb)) {
2632 cksum_offset = tcp_hdrlen(skb);
2633 /* Can only handle headers <= max_tso6 long */
2634 if (unlikely(-cum_len > mgp->max_tso6))
2635 return myri10ge_sw_tso(skb, dev);
2636 }
0da34b6d
BG		 2637 /* for TSO, pseudo_hdr_offset holds mss.
2638 * The firmware figures out where to put
2639 * the checksum by parsing the header. */
40f6cff5 2640 pseudo_hdr_offset = mss;
0da34b6d 2641 } else
0da34b6d
BG		 2642 /* Mark small packets, and pad out tiny packets */
2643 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2644 flags |= MXGEFW_FLAGS_SMALL;
2645
2646 /* pad frames to at least ETH_ZLEN bytes */
2647 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2648 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2649 /* The packet is gone, so we must
2650 * return 0 */
b53bef84 2651 ss->stats.tx_dropped += 1;
6ed10654 2652 return NETDEV_TX_OK;
0da34b6d
BG		 2653 }
2654 /* adjust the len to account for the zero pad
2655 * so that the nic can know how long it is */
2656 skb->len = ETH_ZLEN;
2657 }
2658 }
2659
2660 /* map the skb for DMA */
e743d313 2661 len = skb_headlen(skb);
0da34b6d
BG		 2662 idx = tx->req & tx->mask;
2663 tx->info[idx].skb = skb;
2664 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
c755b4b6
FT		 2665 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2666 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2667
2668 frag_cnt = skb_shinfo(skb)->nr_frags;
2669 frag_idx = 0;
2670 count = 0;
2671 rdma_count = 0;
2672
2673 /* "rdma_count" is the number of RDMAs belonging to the
2674 * current packet BEFORE the current send request. For
2675 * non-TSO packets, this is equal to "count".
2676 * For TSO packets, rdma_count needs to be reset
2677 * to 0 after a segment cut.
2678 *
2679 * The rdma_count field of the send request is
2680 * the number of RDMAs of the packet starting at
2681 * that request. For TSO send requests with one ore more cuts
2682 * in the middle, this is the number of RDMAs starting
2683 * after the last cut in the request. All previous
2684 * segments before the last cut implicitly have 1 RDMA.
2685 *
2686 * Since the number of RDMAs is not known beforehand,
2687 * it must be filled-in retroactively - after each
2688 * segmentation cut or at the end of the entire packet.
2689 */
2690
2691 while (1) {
2692 /* Break the SKB or Fragment up into pieces which
b53bef84 2693 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2694 low = MYRI10GE_LOWPART_TO_U32(bus);
2695 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2696 while (len) {
2697 u8 flags_next;
2698 int cum_len_next;
2699
2700 if (unlikely(count == max_segments))
2701 goto abort_linearize;
2702
b53bef84
BG		 2703 boundary =
2704 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2705 seglen = boundary - low;
2706 if (seglen > len)
2707 seglen = len;
2708 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2709 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2710 if (mss) { /* TSO */
2711 (req - rdma_count)->rdma_count = rdma_count + 1;
2712
2713 if (likely(cum_len >= 0)) { /* payload */
2714 int next_is_first, chop;
2715
2716 chop = (cum_len_next > mss);
2717 cum_len_next = cum_len_next % mss;
2718 next_is_first = (cum_len_next == 0);
2719 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2720 flags_next |= next_is_first *
2721 MXGEFW_FLAGS_FIRST;
2722 rdma_count |= -(chop | next_is_first);
2723 rdma_count += chop & !next_is_first;
2724 } else if (likely(cum_len_next >= 0)) { /* header ends */
2725 int small;
2726
2727 rdma_count = -1;
2728 cum_len_next = 0;
2729 seglen = -cum_len;
2730 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2731 flags_next = MXGEFW_FLAGS_TSO_PLD |
2732 MXGEFW_FLAGS_FIRST |
2733 (small * MXGEFW_FLAGS_SMALL);
2734 }
2735 }
0da34b6d
BG		 2736 req->addr_high = high_swapped;
2737 req->addr_low = htonl(low);
40f6cff5 2738 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2739 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2740 req->rdma_count = 1;
2741 req->length = htons(seglen);
2742 req->cksum_offset = cksum_offset;
2743 req->flags = flags | ((cum_len & 1) * odd_flag);
2744
2745 low += seglen;
2746 len -= seglen;
2747 cum_len = cum_len_next;
2748 flags = flags_next;
2749 req++;
2750 count++;
2751 rdma_count++;
4f93fde0
BG		 2752 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2753 if (unlikely(cksum_offset > seglen))
2754 cksum_offset -= seglen;
2755 else
2756 cksum_offset = 0;
2757 }
0da34b6d
BG		 2758 }
2759 if (frag_idx == frag_cnt)
2760 break;
2761
2762 /* map next fragment for DMA */
2763 idx = (count + tx->req) & tx->mask;
2764 frag = &skb_shinfo(skb)->frags[frag_idx];
2765 frag_idx++;
9e903e08 2766 len = skb_frag_size(frag);
5dc3e196 2767 bus = skb_frag_dma_map(&mgp->pdev->dev, frag, 0, len,
5d6bcdfe 2768 DMA_TO_DEVICE);
c755b4b6
FT		 2769 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2770 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2771 }
2772
2773 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2774 if (mss)
2775 do {
2776 req--;
2777 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2778 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2779 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2780 idx = ((count - 1) + tx->req) & tx->mask;
2781 tx->info[idx].last = 1;
e454e7e2 2782 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2783 /* if using multiple tx queues, make sure NIC polls the
2784 * current slice */
2785 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2786 tx->queue_active = 1;
2787 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2788 mb();
6824a105 2789 mmiowb();
236bb5e6 2790 }
0da34b6d
BG		 2791 tx->pkt_start++;
2792 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2793 tx->stop_queue++;
236bb5e6 2794 netif_tx_stop_queue(netdev_queue);
0da34b6d 2795 }
6ed10654 2796 return NETDEV_TX_OK;
0da34b6d
BG		 2797
2798abort_linearize:
2799 /* Free any DMA resources we've alloced and clear out the skb
2800 * slot so as to not trip up assertions, and to avoid a
2801 * double-free if linearizing fails */
2802
2803 last_idx = (idx + 1) & tx->mask;
2804 idx = tx->req & tx->mask;
2805 tx->info[idx].skb = NULL;
2806 do {
c755b4b6 2807 len = dma_unmap_len(&tx->info[idx], len);
0da34b6d
BG		 2808 if (len) {
2809 if (tx->info[idx].skb != NULL)
2810 pci_unmap_single(mgp->pdev,
c755b4b6 2811 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2812 bus), len,
2813 PCI_DMA_TODEVICE);
2814 else
2815 pci_unmap_page(mgp->pdev,
c755b4b6 2816 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2817 bus), len,
2818 PCI_DMA_TODEVICE);
c755b4b6 2819 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d
BG		 2820 tx->info[idx].skb = NULL;
2821 }
2822 idx = (idx + 1) & tx->mask;
2823 } while (idx != last_idx);
89114afd 2824 if (skb_is_gso(skb)) {
78ca90ea 2825 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
0da34b6d
BG		 2826 goto drop;
2827 }
2828
bec0e859 2829 if (skb_linearize(skb))
0da34b6d
BG		 2830 goto drop;
2831
b53bef84 2832 tx->linearized++;
0da34b6d
BG		 2833 goto again;
2834
2835drop:
2836 dev_kfree_skb_any(skb);
b53bef84 2837 ss->stats.tx_dropped += 1;
6ed10654 2838 return NETDEV_TX_OK;
0da34b6d
BG		 2839
2840}
2841
61357325
SH		 2842static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2843 struct net_device *dev)
4f93fde0
BG		 2844{
2845 struct sk_buff *segs, *curr;
b53bef84 2846 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 2847 struct myri10ge_slice_state *ss;
61357325 2848 netdev_tx_t status;
4f93fde0
BG		 2849
2850 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2851 if (IS_ERR(segs))
4f93fde0
BG		 2852 goto drop;
2853
2854 while (segs) {
2855 curr = segs;
2856 segs = segs->next;
2857 curr->next = NULL;
2858 status = myri10ge_xmit(curr, dev);
2859 if (status != 0) {
2860 dev_kfree_skb_any(curr);
2861 if (segs != NULL) {
2862 curr = segs;
2863 segs = segs->next;
2864 curr->next = NULL;
2865 dev_kfree_skb_any(segs);
2866 }
2867 goto drop;
2868 }
2869 }
2870 dev_kfree_skb_any(skb);
ec634fe3 2871 return NETDEV_TX_OK;
4f93fde0
BG		 2872
2873drop:
d6279c88 2874 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 2875 dev_kfree_skb_any(skb);
d6279c88 2876 ss->stats.tx_dropped += 1;
ec634fe3 2877 return NETDEV_TX_OK;
4f93fde0
BG		 2878}
2879
c5f7ef72 2880static struct rtnl_link_stats64 *myri10ge_get_stats(struct net_device *dev,
2881 struct rtnl_link_stats64 *stats)
0da34b6d 2882{
306ff6eb
ED		 2883 const struct myri10ge_priv *mgp = netdev_priv(dev);
2884 const struct myri10ge_slice_netstats *slice_stats;
0dcffac1
BG		 2885 int i;
2886
0dcffac1
BG		 2887 for (i = 0; i < mgp->num_slices; i++) {
2888 slice_stats = &mgp->ss[i].stats;
2889 stats->rx_packets += slice_stats->rx_packets;
2890 stats->tx_packets += slice_stats->tx_packets;
2891 stats->rx_bytes += slice_stats->rx_bytes;
2892 stats->tx_bytes += slice_stats->tx_bytes;
2893 stats->rx_dropped += slice_stats->rx_dropped;
2894 stats->tx_dropped += slice_stats->tx_dropped;
2895 }
2896 return stats;
0da34b6d
BG		 2897}
2898
2899static void myri10ge_set_multicast_list(struct net_device *dev)
2900{
b53bef84 2901 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 2902 struct myri10ge_cmd cmd;
22bedad3 2903 struct netdev_hw_addr *ha;
6250223e 2904 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 2905 int err;
2906
0da34b6d
BG		 2907 /* can be called from atomic contexts,
2908 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2909 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2910
2911 /* This firmware is known to not support multicast */
2f76216f 2912 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2913 return;
2914
2915 /* Disable multicast filtering */
2916
2917 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2918 if (err != 0) {
78ca90ea
JP		 2919 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
2920 err);
85a7ea1b
BG		 2921 goto abort;
2922 }
2923
2f76216f 2924 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2925 /* request to disable multicast filtering, so quit here */
2926 return;
2927 }
2928
2929 /* Flush the filters */
2930
2931 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2932 &cmd, 1);
2933 if (err != 0) {
78ca90ea
JP		 2934 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
2935 err);
85a7ea1b
BG		 2936 goto abort;
2937 }
2938
2939 /* Walk the multicast list, and add each address */
22bedad3
JP		 2940 netdev_for_each_mc_addr(ha, dev) {
2941 memcpy(data, &ha->addr, 6);
40f6cff5
AV		 2942 cmd.data0 = ntohl(data[0]);
2943 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2944 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2945 &cmd, 1);
2946
2947 if (err != 0) {
78ca90ea 2948 netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
22bedad3 2949 err, ha->addr);
85a7ea1b
BG		 2950 goto abort;
2951 }
2952 }
2953 /* Enable multicast filtering */
2954 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2955 if (err != 0) {
78ca90ea
JP		 2956 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
2957 err);
85a7ea1b
BG		 2958 goto abort;
2959 }
2960
2961 return;
2962
2963abort:
2964 return;
0da34b6d
BG		 2965}
2966
2967static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2968{
2969 struct sockaddr *sa = addr;
2970 struct myri10ge_priv *mgp = netdev_priv(dev);
2971 int status;
2972
2973 if (!is_valid_ether_addr(sa->sa_data))
2974 return -EADDRNOTAVAIL;
2975
2976 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2977 if (status != 0) {
78ca90ea
JP		 2978 netdev_err(dev, "changing mac address failed with %d\n",
2979 status);
0da34b6d
BG		 2980 return status;
2981 }
2982
2983 /* change the dev structure */
2984 memcpy(dev->dev_addr, sa->sa_data, 6);
2985 return 0;
2986}
2987
2988static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2989{
2990 struct myri10ge_priv *mgp = netdev_priv(dev);
2991 int error = 0;
2992
2993 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
78ca90ea 2994 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
0da34b6d
BG		 2995 return -EINVAL;
2996 }
78ca90ea 2997 netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
0da34b6d
BG		 2998 if (mgp->running) {
2999 /* if we change the mtu on an active device, we must
3000 * reset the device so the firmware sees the change */
3001 myri10ge_close(dev);
3002 dev->mtu = new_mtu;
3003 myri10ge_open(dev);
3004 } else
3005 dev->mtu = new_mtu;
3006
3007 return error;
3008}
3009
3010/*
3011 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3012 * Only do it if the bridge is a root port since we don't want to disturb
3013 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3014 */
3015
0da34b6d
BG		 3016static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3017{
3018 struct pci_dev *bridge = mgp->pdev->bus->self;
3019 struct device *dev = &mgp->pdev->dev;
effd1eda 3020 int cap;
0da34b6d 3021 unsigned err_cap;
0da34b6d
BG		 3022 int ret;
3023
3024 if (!myri10ge_ecrc_enable || !bridge)
3025 return;
3026
3027 /* check that the bridge is a root port */
9503e255 3028 if (pci_pcie_type(bridge) != PCI_EXP_TYPE_ROOT_PORT) {
0da34b6d 3029 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3030 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3031
3032 /* Walk the hierarchy up to the root port
3033 * where ECRC has to be enabled */
3034 do {
eca3fd83 3035 prev_bridge = bridge;
0da34b6d 3036 bridge = bridge->bus->self;
eca3fd83 3037 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3038 dev_err(dev,
3039 "Failed to find root port"
3040 " to force ECRC\n");
3041 return;
3042 }
9503e255
JL		 3043 } while (pci_pcie_type(bridge) !=
3044 PCI_EXP_TYPE_ROOT_PORT);
0da34b6d
BG		 3045
3046 dev_info(dev,
3047 "Forcing ECRC on non-root port %s"
3048 " (enabling on root port %s)\n",
3049 pci_name(old_bridge), pci_name(bridge));
3050 } else {
3051 dev_err(dev,
3052 "Not enabling ECRC on non-root port %s\n",
3053 pci_name(bridge));
3054 return;
3055 }
3056 }
3057
3058 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3059 if (!cap)
3060 return;
3061
3062 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3063 if (ret) {
3064 dev_err(dev, "failed reading ext-conf-space of %s\n",
3065 pci_name(bridge));
3066 dev_err(dev, "\t pci=nommconf in use? "
3067 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3068 return;
3069 }
3070 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3071 return;
3072
3073 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3074 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3075 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3076}
3077
3078/*
3079 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3080 * when the PCI-E Completion packets are aligned on an 8-byte
3081 * boundary. Some PCI-E chip sets always align Completion packets; on
3082 * the ones that do not, the alignment can be enforced by enabling
3083 * ECRC generation (if supported).
3084 *
3085 * When PCI-E Completion packets are not aligned, it is actually more
3086 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3087 *
3088 * If the driver can neither enable ECRC nor verify that it has
3089 * already been enabled, then it must use a firmware image which works
0dcffac1 3090 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3091 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3092 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3093 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3094 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3095 */
3096
5443e9ea 3097static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3098{
5443e9ea
BG		 3099 struct pci_dev *pdev = mgp->pdev;
3100 struct device *dev = &pdev->dev;
302d242c 3101 int status;
0da34b6d 3102
b53bef84 3103 mgp->tx_boundary = 4096;
5443e9ea
BG		 3104 /*
3105 * Verify the max read request size was set to 4KB
3106 * before trying the test with 4KB.
3107 */
302d242c
BG		 3108 status = pcie_get_readrq(pdev);
3109 if (status < 0) {
5443e9ea
BG		 3110 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3111 goto abort;
3112 }
302d242c
BG		 3113 if (status != 4096) {
3114 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3115 mgp->tx_boundary = 2048;
5443e9ea
BG		 3116 }
3117 /*
3118 * load the optimized firmware (which assumes aligned PCIe
3119 * completions) in order to see if it works on this host.
3120 */
7d351035 3121 set_fw_name(mgp, myri10ge_fw_aligned, false);
0dcffac1 3122 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3123 if (status != 0) {
3124 goto abort;
3125 }
3126
3127 /*
3128 * Enable ECRC if possible
3129 */
3130 myri10ge_enable_ecrc(mgp);
3131
3132 /*
3133 * Run a DMA test which watches for unaligned completions and
3134 * aborts on the first one seen.
3135 */
3136
3137 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3138 if (status == 0)
3139 return; /* keep the aligned firmware */
3140
3141 if (status != -E2BIG)
3142 dev_warn(dev, "DMA test failed: %d\n", status);
3143 if (status == -ENOSYS)
3144 dev_warn(dev, "Falling back to ethp! "
3145 "Please install up to date fw\n");
3146abort:
3147 /* fall back to using the unaligned firmware */
b53bef84 3148 mgp->tx_boundary = 2048;
7d351035 3149 set_fw_name(mgp, myri10ge_fw_unaligned, false);
5443e9ea
BG		 3150}
3151
3152static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3153{
2d90b0aa
BG		 3154 int overridden = 0;
3155
0da34b6d 3156 if (myri10ge_force_firmware == 0) {
9503e255 3157 int link_width;
ce7f9368
BG		 3158 u16 lnk;
3159
9503e255 3160 pcie_capability_read_word(mgp->pdev, PCI_EXP_LNKSTA, &lnk);
ce7f9368
BG		 3161 link_width = (lnk >> 4) & 0x3f;
3162
ce7f9368
BG		 3163 /* Check to see if Link is less than 8 or if the
3164 * upstream bridge is known to provide aligned
3165 * completions */
3166 if (link_width < 8) {
3167 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3168 link_width);
b53bef84 3169 mgp->tx_boundary = 4096;
7d351035 3170 set_fw_name(mgp, myri10ge_fw_aligned, false);
5443e9ea
BG		 3171 } else {
3172 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3173 }
3174 } else {
3175 if (myri10ge_force_firmware == 1) {
3176 dev_info(&mgp->pdev->dev,
3177 "Assuming aligned completions (forced)\n");
b53bef84 3178 mgp->tx_boundary = 4096;
7d351035 3179 set_fw_name(mgp, myri10ge_fw_aligned, false);
0da34b6d
BG		 3180 } else {
3181 dev_info(&mgp->pdev->dev,
3182 "Assuming unaligned completions (forced)\n");
b53bef84 3183 mgp->tx_boundary = 2048;
7d351035 3184 set_fw_name(mgp, myri10ge_fw_unaligned, false);
0da34b6d
BG		 3185 }
3186 }
7d351035
RR		 3187
3188 kparam_block_sysfs_write(myri10ge_fw_name);
0da34b6d 3189 if (myri10ge_fw_name != NULL) {
7d351035
RR		 3190 char *fw_name = kstrdup(myri10ge_fw_name, GFP_KERNEL);
3191 if (fw_name) {
3192 overridden = 1;
3193 set_fw_name(mgp, fw_name, true);
3194 }
0da34b6d 3195 }
7d351035
RR		 3196 kparam_unblock_sysfs_write(myri10ge_fw_name);
3197
2d90b0aa
BG		 3198 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3199 myri10ge_fw_names[mgp->board_number] != NULL &&
3200 strlen(myri10ge_fw_names[mgp->board_number])) {
7d351035 3201 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
2d90b0aa
BG		 3202 overridden = 1;
3203 }
3204 if (overridden)
3205 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3206 mgp->fw_name);
0da34b6d
BG		 3207}
3208
7539a613
JM		 3209static void myri10ge_mask_surprise_down(struct pci_dev *pdev)
3210{
3211 struct pci_dev *bridge = pdev->bus->self;
3212 int cap;
3213 u32 mask;
3214
3215 if (bridge == NULL)
3216 return;
3217
3218 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3219 if (cap) {
3220 /* a sram parity error can cause a surprise link
3221 * down; since we expect and can recover from sram
3222 * parity errors, mask surprise link down events */
3223 pci_read_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, &mask);
3224 mask |= 0x20;
3225 pci_write_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, mask);
3226 }
3227}
3228
0da34b6d 3229#ifdef CONFIG_PM
0da34b6d
BG		 3230static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3231{
3232 struct myri10ge_priv *mgp;
3233 struct net_device *netdev;
3234
3235 mgp = pci_get_drvdata(pdev);
3236 if (mgp == NULL)
3237 return -EINVAL;
3238 netdev = mgp->dev;
3239
3240 netif_device_detach(netdev);
3241 if (netif_running(netdev)) {
78ca90ea 3242 netdev_info(netdev, "closing\n");
0da34b6d
BG		 3243 rtnl_lock();
3244 myri10ge_close(netdev);
3245 rtnl_unlock();
3246 }
3247 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3248 pci_save_state(pdev);
0da34b6d 3249 pci_disable_device(pdev);
1a63e846
BG		 3250
3251 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3252}
3253
3254static int myri10ge_resume(struct pci_dev *pdev)
3255{
3256 struct myri10ge_priv *mgp;
3257 struct net_device *netdev;
3258 int status;
3259 u16 vendor;
3260
3261 mgp = pci_get_drvdata(pdev);
3262 if (mgp == NULL)
3263 return -EINVAL;
3264 netdev = mgp->dev;
3265 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3266 msleep(5); /* give card time to respond */
3267 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3268 if (vendor == 0xffff) {
78ca90ea 3269 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3270 return -EIO;
3271 }
83f6e152 3272
1d3c16a8 3273 pci_restore_state(pdev);
4c2248cc
BG		 3274
3275 status = pci_enable_device(pdev);
1a63e846 3276 if (status) {
4c2248cc 3277 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3278 return status;
4c2248cc
BG		 3279 }
3280
0da34b6d
BG		 3281 pci_set_master(pdev);
3282
0da34b6d 3283 myri10ge_reset(mgp);
013b68bf 3284 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3285
3286 /* Save configuration space to be restored if the
3287 * nic resets due to a parity error */
83f6e152 3288 pci_save_state(pdev);
0da34b6d
BG		 3289
3290 if (netif_running(netdev)) {
3291 rtnl_lock();
df30a740 3292 status = myri10ge_open(netdev);
0da34b6d 3293 rtnl_unlock();
df30a740
BG		 3294 if (status != 0)
3295 goto abort_with_enabled;
3296
0da34b6d
BG		 3297 }
3298 netif_device_attach(netdev);
3299
3300 return 0;
3301
4c2248cc
BG		 3302abort_with_enabled:
3303 pci_disable_device(pdev);
0da34b6d
BG		 3304 return -EIO;
3305
3306}
0da34b6d
BG		 3307#endif /* CONFIG_PM */
3308
3309static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3310{
3311 struct pci_dev *pdev = mgp->pdev;
3312 int vs = mgp->vendor_specific_offset;
3313 u32 reboot;
3314
3315 /*enter read32 mode */
3316 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3317
3318 /*read REBOOT_STATUS (0xfffffff0) */
3319 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3320 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3321 return reboot;
3322}
3323
c689b81b
JM		 3324static void
3325myri10ge_check_slice(struct myri10ge_slice_state *ss, int *reset_needed,
3326 int *busy_slice_cnt, u32 rx_pause_cnt)
3327{
3328 struct myri10ge_priv *mgp = ss->mgp;
3329 int slice = ss - mgp->ss;
3330
3331 if (ss->tx.req != ss->tx.done &&
3332 ss->tx.done == ss->watchdog_tx_done &&
3333 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3334 /* nic seems like it might be stuck.. */
3335 if (rx_pause_cnt != mgp->watchdog_pause) {
3336 if (net_ratelimit())
3337 netdev_warn(mgp->dev, "slice %d: TX paused, "
3338 "check link partner\n", slice);
3339 } else {
3340 netdev_warn(mgp->dev,
3341 "slice %d: TX stuck %d %d %d %d %d %d\n",
3342 slice, ss->tx.queue_active, ss->tx.req,
3343 ss->tx.done, ss->tx.pkt_start,
3344 ss->tx.pkt_done,
3345 (int)ntohl(mgp->ss[slice].fw_stats->
3346 send_done_count));
3347 *reset_needed = 1;
3348 ss->stuck = 1;
3349 }
3350 }
3351 if (ss->watchdog_tx_done != ss->tx.done ||
3352 ss->watchdog_rx_done != ss->rx_done.cnt) {
3353 *busy_slice_cnt += 1;
3354 }
3355 ss->watchdog_tx_done = ss->tx.done;
3356 ss->watchdog_tx_req = ss->tx.req;
3357 ss->watchdog_rx_done = ss->rx_done.cnt;
3358}
3359
0da34b6d
BG		 3360/*
3361 * This watchdog is used to check whether the board has suffered
3362 * from a parity error and needs to be recovered.
3363 */
c4028958 3364static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3365{
c4028958 3366 struct myri10ge_priv *mgp =
6250223e 3367 container_of(work, struct myri10ge_priv, watchdog_work);
c689b81b
JM		 3368 struct myri10ge_slice_state *ss;
3369 u32 reboot, rx_pause_cnt;
d0234215 3370 int status, rebooted;
0dcffac1 3371 int i;
c689b81b
JM		 3372 int reset_needed = 0;
3373 int busy_slice_cnt = 0;
0da34b6d
BG		 3374 u16 cmd, vendor;
3375
3376 mgp->watchdog_resets++;
3377 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
d0234215 3378 rebooted = 0;
0da34b6d
BG		 3379 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3380 /* Bus master DMA disabled? Check to see
3381 * if the card rebooted due to a parity error
3382 * For now, just report it */
3383 reboot = myri10ge_read_reboot(mgp);
78ca90ea 3384 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
c689b81b 3385 reboot, myri10ge_reset_recover ? "" : " not");
f181137f
BG		 3386 if (myri10ge_reset_recover == 0)
3387 return;
d0234215
BG		 3388 rtnl_lock();
3389 mgp->rebooted = 1;
3390 rebooted = 1;
3391 myri10ge_close(mgp->dev);
f181137f 3392 myri10ge_reset_recover--;
d0234215 3393 mgp->rebooted = 0;
0da34b6d
BG		 3394 /*
3395 * A rebooted nic will come back with config space as
3396 * it was after power was applied to PCIe bus.
3397 * Attempt to restore config space which was saved
3398 * when the driver was loaded, or the last time the
3399 * nic was resumed from power saving mode.
3400 */
83f6e152 3401 pci_restore_state(mgp->pdev);
7adda30c
BG		 3402
3403 /* save state again for accounting reasons */
83f6e152 3404 pci_save_state(mgp->pdev);
7adda30c 3405
0da34b6d
BG		 3406 } else {
3407 /* if we get back -1's from our slot, perhaps somebody
3408 * powered off our card. Don't try to reset it in
3409 * this case */
3410 if (cmd == 0xffff) {
3411 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3412 if (vendor == 0xffff) {
78ca90ea 3413 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3414 return;
3415 }
3416 }
c689b81b
JM		 3417 /* Perhaps it is a software error. See if stuck slice
3418 * has recovered, reset if not */
3419 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
0dcffac1 3420 for (i = 0; i < mgp->num_slices; i++) {
c689b81b
JM		 3421 ss = mgp->ss;
3422 if (ss->stuck) {
3423 myri10ge_check_slice(ss, &reset_needed,
3424 &busy_slice_cnt,
3425 rx_pause_cnt);
3426 ss->stuck = 0;
3427 }
0dcffac1 3428 }
c689b81b
JM		 3429 if (!reset_needed) {
3430 netdev_dbg(mgp->dev, "not resetting\n");
3431 return;
3432 }
3433
3434 netdev_err(mgp->dev, "device timeout, resetting\n");
0da34b6d 3435 }
236bb5e6 3436
d0234215
BG		 3437 if (!rebooted) {
3438 rtnl_lock();
3439 myri10ge_close(mgp->dev);
3440 }
0dcffac1 3441 status = myri10ge_load_firmware(mgp, 1);
0da34b6d 3442 if (status != 0)
78ca90ea 3443 netdev_err(mgp->dev, "failed to load firmware\n");
0da34b6d
BG		 3444 else
3445 myri10ge_open(mgp->dev);
3446 rtnl_unlock();
3447}
3448
3449/*
3450 * We use our own timer routine rather than relying upon
3451 * netdev->tx_timeout because we have a very large hardware transmit
3452 * queue. Due to the large queue, the netdev->tx_timeout function
3453 * cannot detect a NIC with a parity error in a timely fashion if the
3454 * NIC is lightly loaded.
3455 */
3456static void myri10ge_watchdog_timer(unsigned long arg)
3457{
3458 struct myri10ge_priv *mgp;
b53bef84 3459 struct myri10ge_slice_state *ss;
d0234215 3460 int i, reset_needed, busy_slice_cnt;
626fda94 3461 u32 rx_pause_cnt;
d0234215 3462 u16 cmd;
0da34b6d
BG		 3463
3464 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3465
0dcffac1 3466 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
d0234215 3467 busy_slice_cnt = 0;
0dcffac1
BG		 3468 for (i = 0, reset_needed = 0;
3469 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3470
0dcffac1
BG		 3471 ss = &mgp->ss[i];
3472 if (ss->rx_small.watchdog_needed) {
3473 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3474 mgp->small_bytes + MXGEFW_PAD,
3475 1);
3476 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3477 myri10ge_fill_thresh)
3478 ss->rx_small.watchdog_needed = 0;
3479 }
3480 if (ss->rx_big.watchdog_needed) {
3481 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3482 mgp->big_bytes, 1);
3483 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3484 myri10ge_fill_thresh)
3485 ss->rx_big.watchdog_needed = 0;
3486 }
c689b81b
JM		 3487 myri10ge_check_slice(ss, &reset_needed, &busy_slice_cnt,
3488 rx_pause_cnt);
d0234215
BG		 3489 }
3490 /* if we've sent or received no traffic, poll the NIC to
3491 * ensure it is still there. Otherwise, we risk not noticing
3492 * an error in a timely fashion */
3493 if (busy_slice_cnt == 0) {
3494 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3495 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3496 reset_needed = 1;
3497 }
626fda94 3498 }
626fda94 3499 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3500
3501 if (reset_needed) {
3502 schedule_work(&mgp->watchdog_work);
3503 } else {
3504 /* rearm timer */
3505 mod_timer(&mgp->watchdog_timer,
3506 jiffies + myri10ge_watchdog_timeout * HZ);
3507 }
0da34b6d
BG		 3508}
3509
77929732
BG		 3510static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3511{
3512 struct myri10ge_slice_state *ss;
3513 struct pci_dev *pdev = mgp->pdev;
3514 size_t bytes;
3515 int i;
3516
3517 if (mgp->ss == NULL)
3518 return;
3519
3520 for (i = 0; i < mgp->num_slices; i++) {
3521 ss = &mgp->ss[i];
3522 if (ss->rx_done.entry != NULL) {
3523 bytes = mgp->max_intr_slots *
3524 sizeof(*ss->rx_done.entry);
3525 dma_free_coherent(&pdev->dev, bytes,
3526 ss->rx_done.entry, ss->rx_done.bus);
3527 ss->rx_done.entry = NULL;
3528 }
3529 if (ss->fw_stats != NULL) {
3530 bytes = sizeof(*ss->fw_stats);
3531 dma_free_coherent(&pdev->dev, bytes,
3532 ss->fw_stats, ss->fw_stats_bus);
3533 ss->fw_stats = NULL;
3534 }
b3b6ae2c 3535 netif_napi_del(&ss->napi);
77929732
BG		 3536 }
3537 kfree(mgp->ss);
3538 mgp->ss = NULL;
3539}
3540
3541static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3542{
3543 struct myri10ge_slice_state *ss;
3544 struct pci_dev *pdev = mgp->pdev;
3545 size_t bytes;
3546 int i;
3547
3548 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3549 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3550 if (mgp->ss == NULL) {
3551 return -ENOMEM;
3552 }
3553
3554 for (i = 0; i < mgp->num_slices; i++) {
3555 ss = &mgp->ss[i];
3556 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3557 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3558 &ss->rx_done.bus,
3559 GFP_KERNEL);
3560 if (ss->rx_done.entry == NULL)
3561 goto abort;
3562 memset(ss->rx_done.entry, 0, bytes);
3563 bytes = sizeof(*ss->fw_stats);
3564 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3565 &ss->fw_stats_bus,
3566 GFP_KERNEL);
3567 if (ss->fw_stats == NULL)
3568 goto abort;
3569 ss->mgp = mgp;
3570 ss->dev = mgp->dev;
3571 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3572 myri10ge_napi_weight);
3573 }
3574 return 0;
3575abort:
3576 myri10ge_free_slices(mgp);
3577 return -ENOMEM;
3578}
3579
3580/*
3581 * This function determines the number of slices supported.
25985edc 3582 * The number slices is the minimum of the number of CPUS,
77929732
BG		 3583 * the number of MSI-X irqs supported, the number of slices
3584 * supported by the firmware
3585 */
3586static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3587{
3588 struct myri10ge_cmd cmd;
3589 struct pci_dev *pdev = mgp->pdev;
3590 char *old_fw;
7d351035 3591 bool old_allocated;
77929732
BG		 3592 int i, status, ncpus, msix_cap;
3593
3594 mgp->num_slices = 1;
3595 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
98f2d21f 3596 ncpus = netif_get_num_default_rss_queues();
77929732
BG		 3597
3598 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3599 (myri10ge_max_slices == -1 && ncpus < 2))
3600 return;
3601
3602 /* try to load the slice aware rss firmware */
3603 old_fw = mgp->fw_name;
7d351035
RR		 3604 old_allocated = mgp->fw_name_allocated;
3605 /* don't free old_fw if we override it. */
3606 mgp->fw_name_allocated = false;
3607
13b2738c
BG		 3608 if (myri10ge_fw_name != NULL) {
3609 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3610 myri10ge_fw_name);
7d351035 3611 set_fw_name(mgp, myri10ge_fw_name, false);
13b2738c 3612 } else if (old_fw == myri10ge_fw_aligned)
7d351035 3613 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
77929732 3614 else
7d351035 3615 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
77929732
BG		 3616 status = myri10ge_load_firmware(mgp, 0);
3617 if (status != 0) {
3618 dev_info(&pdev->dev, "Rss firmware not found\n");
7d351035
RR		 3619 if (old_allocated)
3620 kfree(old_fw);
77929732
BG		 3621 return;
3622 }
3623
3624 /* hit the board with a reset to ensure it is alive */
3625 memset(&cmd, 0, sizeof(cmd));
3626 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3627 if (status != 0) {
3628 dev_err(&mgp->pdev->dev, "failed reset\n");
3629 goto abort_with_fw;
77929732
BG		 3630 }
3631
3632 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3633
3634 /* tell it the size of the interrupt queues */
3635 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3636 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3637 if (status != 0) {
3638 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3639 goto abort_with_fw;
3640 }
3641
3642 /* ask the maximum number of slices it supports */
3643 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3644 if (status != 0)
3645 goto abort_with_fw;
3646 else
3647 mgp->num_slices = cmd.data0;
3648
3649 /* Only allow multiple slices if MSI-X is usable */
3650 if (!myri10ge_msi) {
3651 goto abort_with_fw;
3652 }
3653
3654 /* if the admin did not specify a limit to how many
3655 * slices we should use, cap it automatically to the
3656 * number of CPUs currently online */
3657 if (myri10ge_max_slices == -1)
3658 myri10ge_max_slices = ncpus;
3659
3660 if (mgp->num_slices > myri10ge_max_slices)
3661 mgp->num_slices = myri10ge_max_slices;
3662
3663 /* Now try to allocate as many MSI-X vectors as we have
3664 * slices. We give up on MSI-X if we can only get a single
3665 * vector. */
3666
baeb2ffa
JP		 3667 mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3668 GFP_KERNEL);
77929732
BG		 3669 if (mgp->msix_vectors == NULL)
3670 goto disable_msix;
3671 for (i = 0; i < mgp->num_slices; i++) {
3672 mgp->msix_vectors[i].entry = i;
3673 }
3674
3675 while (mgp->num_slices > 1) {
3676 /* make sure it is a power of two */
3677 while (!is_power_of_2(mgp->num_slices))
3678 mgp->num_slices--;
3679 if (mgp->num_slices == 1)
3680 goto disable_msix;
3681 status = pci_enable_msix(pdev, mgp->msix_vectors,
3682 mgp->num_slices);
3683 if (status == 0) {
3684 pci_disable_msix(pdev);
7d351035
RR		 3685 if (old_allocated)
3686 kfree(old_fw);
77929732
BG		 3687 return;
3688 }
3689 if (status > 0)
3690 mgp->num_slices = status;
3691 else
3692 goto disable_msix;
3693 }
3694
3695disable_msix:
3696 if (mgp->msix_vectors != NULL) {
3697 kfree(mgp->msix_vectors);
3698 mgp->msix_vectors = NULL;
3699 }
3700
3701abort_with_fw:
3702 mgp->num_slices = 1;
7d351035 3703 set_fw_name(mgp, old_fw, old_allocated);
77929732
BG		 3704 myri10ge_load_firmware(mgp, 0);
3705}
77929732 3706
8126089f
SH		 3707static const struct net_device_ops myri10ge_netdev_ops = {
3708 .ndo_open = myri10ge_open,
3709 .ndo_stop = myri10ge_close,
3710 .ndo_start_xmit = myri10ge_xmit,
c5f7ef72 3711 .ndo_get_stats64 = myri10ge_get_stats,
8126089f
SH		 3712 .ndo_validate_addr = eth_validate_addr,
3713 .ndo_change_mtu = myri10ge_change_mtu,
afc4b13d 3714 .ndo_set_rx_mode = myri10ge_set_multicast_list,
8126089f
SH		 3715 .ndo_set_mac_address = myri10ge_set_mac_address,
3716};
3717
0da34b6d
BG		 3718static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3719{
3720 struct net_device *netdev;
3721 struct myri10ge_priv *mgp;
3722 struct device *dev = &pdev->dev;
0da34b6d
BG		 3723 int i;
3724 int status = -ENXIO;
0da34b6d 3725 int dac_enabled;
00b5e505 3726 unsigned hdr_offset, ss_offset;
2d90b0aa 3727 static int board_number;
0da34b6d 3728
236bb5e6 3729 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
41de8d4c 3730 if (netdev == NULL)
0da34b6d 3731 return -ENOMEM;
0da34b6d 3732
b245fb67
MH		 3733 SET_NETDEV_DEV(netdev, &pdev->dev);
3734
0da34b6d 3735 mgp = netdev_priv(netdev);
0da34b6d
BG		 3736 mgp->dev = netdev;
3737 mgp->pdev = pdev;
0da34b6d
BG		 3738 mgp->pause = myri10ge_flow_control;
3739 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3740 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3741 mgp->board_number = board_number;
0da34b6d
BG		 3742 init_waitqueue_head(&mgp->down_wq);
3743
3744 if (pci_enable_device(pdev)) {
3745 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3746 status = -ENODEV;
3747 goto abort_with_netdev;
3748 }
0da34b6d
BG		 3749
3750 /* Find the vendor-specific cap so we can check
3751 * the reboot register later on */
3752 mgp->vendor_specific_offset
3753 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3754
3755 /* Set our max read request to 4KB */
302d242c 3756 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3757 if (status != 0) {
3758 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3759 status);
e3fd5534 3760 goto abort_with_enabled;
0da34b6d
BG		 3761 }
3762
7539a613 3763 myri10ge_mask_surprise_down(pdev);
0da34b6d
BG		 3764 pci_set_master(pdev);
3765 dac_enabled = 1;
6a35528a 3766 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3767 if (status != 0) {
3768 dac_enabled = 0;
3769 dev_err(&pdev->dev,
898eb71c
JP		 3770 "64-bit pci address mask was refused, "
3771 "trying 32-bit\n");
284901a9 3772 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 3773 }
3774 if (status != 0) {
3775 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 3776 goto abort_with_enabled;
0da34b6d 3777 }
6a35528a 3778 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 3779 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3780 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 3781 if (mgp->cmd == NULL)
e3fd5534 3782 goto abort_with_enabled;
0da34b6d 3783
0da34b6d
BG		 3784 mgp->board_span = pci_resource_len(pdev, 0);
3785 mgp->iomem_base = pci_resource_start(pdev, 0);
3786 mgp->mtrr = -1;
276e26c3 3787 mgp->wc_enabled = 0;
0da34b6d
BG		 3788#ifdef CONFIG_MTRR
3789 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3790 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3791 if (mgp->mtrr >= 0)
3792 mgp->wc_enabled = 1;
0da34b6d 3793#endif
c7f80993 3794 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3795 if (mgp->sram == NULL) {
3796 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3797 mgp->board_span, mgp->iomem_base);
3798 status = -ENXIO;
c7f80993 3799 goto abort_with_mtrr;
0da34b6d 3800 }
00b5e505
BG		 3801 hdr_offset =
3802 ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3803 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3804 mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3805 if (mgp->sram_size > mgp->board_span ||
3806 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3807 dev_err(&pdev->dev,
3808 "invalid sram_size %dB or board span %ldB\n",
3809 mgp->sram_size, mgp->board_span);
3810 goto abort_with_ioremap;
3811 }
0da34b6d 3812 memcpy_fromio(mgp->eeprom_strings,
00b5e505 3813 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 3814 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3815 status = myri10ge_read_mac_addr(mgp);
3816 if (status)
3817 goto abort_with_ioremap;
3818
3819 for (i = 0; i < ETH_ALEN; i++)
3820 netdev->dev_addr[i] = mgp->mac_addr[i];
3821
5443e9ea
BG		 3822 myri10ge_select_firmware(mgp);
3823
0dcffac1 3824 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3825 if (status != 0) {
3826 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3827 goto abort_with_ioremap;
3828 }
3829 myri10ge_probe_slices(mgp);
3830 status = myri10ge_alloc_slices(mgp);
3831 if (status != 0) {
3832 dev_err(&pdev->dev, "failed to alloc slice state\n");
3833 goto abort_with_firmware;
0da34b6d 3834 }
c9920268
BH		 3835 netif_set_real_num_tx_queues(netdev, mgp->num_slices);
3836 netif_set_real_num_rx_queues(netdev, mgp->num_slices);
0da34b6d
BG		 3837 status = myri10ge_reset(mgp);
3838 if (status != 0) {
3839 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3840 goto abort_with_slices;
0da34b6d 3841 }
5dd2d332 3842#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3843 myri10ge_setup_dca(mgp);
3844#endif
0da34b6d
BG		 3845 pci_set_drvdata(pdev, mgp);
3846 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3847 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3848 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3849 myri10ge_initial_mtu = 68;
8126089f
SH		 3850
3851 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 3852 netdev->mtu = myri10ge_initial_mtu;
4ca3221f 3853 netdev->hw_features = mgp->features | NETIF_F_RXCSUM;
47c2cdf5 3854 netdev->features = netdev->hw_features;
236bb5e6 3855
0da34b6d
BG		 3856 if (dac_enabled)
3857 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3858
dddc045e
BG		 3859 netdev->vlan_features |= mgp->features;
3860 if (mgp->fw_ver_tiny < 37)
3861 netdev->vlan_features &= ~NETIF_F_TSO6;
3862 if (mgp->fw_ver_tiny < 32)
3863 netdev->vlan_features &= ~NETIF_F_TSO;
3864
21d05db1 3865 /* make sure we can get an irq, and that MSI can be
a7425458 3866 * setup (if available). */
21d05db1
BG		 3867 status = myri10ge_request_irq(mgp);
3868 if (status != 0)
3869 goto abort_with_firmware;
21d05db1
BG		 3870 myri10ge_free_irq(mgp);
3871
0da34b6d
BG		 3872 /* Save configuration space to be restored if the
3873 * nic resets due to a parity error */
83f6e152 3874 pci_save_state(pdev);
0da34b6d
BG		 3875
3876 /* Setup the watchdog timer */
3877 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3878 (unsigned long)mgp);
3879
3880 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3881 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3882 status = register_netdev(netdev);
3883 if (status != 0) {
3884 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3885 goto abort_with_state;
0da34b6d 3886 }
0dcffac1
BG		 3887 if (mgp->msix_enabled)
3888 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3889 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3890 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3891 else
3892 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3893 mgp->msi_enabled ? "MSI" : "xPIC",
a7425458 3894 pdev->irq, mgp->tx_boundary, mgp->fw_name,
0dcffac1 3895 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 3896
2d90b0aa 3897 board_number++;
0da34b6d
BG		 3898 return 0;
3899
7adda30c 3900abort_with_state:
83f6e152 3901 pci_restore_state(pdev);
0da34b6d 3902
0dcffac1
BG		 3903abort_with_slices:
3904 myri10ge_free_slices(mgp);
3905
0da34b6d
BG		 3906abort_with_firmware:
3907 myri10ge_dummy_rdma(mgp, 0);
3908
0da34b6d 3909abort_with_ioremap:
0f840011
BG		 3910 if (mgp->mac_addr_string != NULL)
3911 dev_err(&pdev->dev,
3912 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3913 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 3914 iounmap(mgp->sram);
3915
c7f80993 3916abort_with_mtrr:
0da34b6d
BG		 3917#ifdef CONFIG_MTRR
3918 if (mgp->mtrr >= 0)
3919 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3920#endif
b10c0668
BG		 3921 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3922 mgp->cmd, mgp->cmd_bus);
0da34b6d 3923
e3fd5534
BG		 3924abort_with_enabled:
3925 pci_disable_device(pdev);
0da34b6d 3926
e3fd5534 3927abort_with_netdev:
7d351035 3928 set_fw_name(mgp, NULL, false);
0da34b6d
BG		 3929 free_netdev(netdev);
3930 return status;
3931}
3932
3933/*
3934 * myri10ge_remove
3935 *
3936 * Does what is necessary to shutdown one Myrinet device. Called
3937 * once for each Myrinet card by the kernel when a module is
3938 * unloaded.
3939 */
3940static void myri10ge_remove(struct pci_dev *pdev)
3941{
3942 struct myri10ge_priv *mgp;
3943 struct net_device *netdev;
0da34b6d
BG		 3944
3945 mgp = pci_get_drvdata(pdev);
3946 if (mgp == NULL)
3947 return;
3948
23f333a2 3949 cancel_work_sync(&mgp->watchdog_work);
0da34b6d
BG		 3950 netdev = mgp->dev;
3951 unregister_netdev(netdev);
0da34b6d 3952
5dd2d332 3953#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3954 myri10ge_teardown_dca(mgp);
3955#endif
0da34b6d
BG		 3956 myri10ge_dummy_rdma(mgp, 0);
3957
7adda30c 3958 /* avoid a memory leak */
83f6e152 3959 pci_restore_state(pdev);
7adda30c 3960
0da34b6d
BG		 3961 iounmap(mgp->sram);
3962
3963#ifdef CONFIG_MTRR
3964 if (mgp->mtrr >= 0)
3965 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3966#endif
0dcffac1
BG		 3967 myri10ge_free_slices(mgp);
3968 if (mgp->msix_vectors != NULL)
3969 kfree(mgp->msix_vectors);
b10c0668
BG		 3970 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3971 mgp->cmd, mgp->cmd_bus);
0da34b6d 3972
7d351035 3973 set_fw_name(mgp, NULL, false);
0da34b6d 3974 free_netdev(netdev);
e3fd5534 3975 pci_disable_device(pdev);
0da34b6d
BG		 3976 pci_set_drvdata(pdev, NULL);
3977}
3978
b10c0668 3979#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3980#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d 3981
a3aa1884 3982static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
b10c0668 3983 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3984 {PCI_DEVICE
3985 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3986 {0},
3987};
3988
97131079
BG		 3989MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
3990
0da34b6d
BG		 3991static struct pci_driver myri10ge_driver = {
3992 .name = "myri10ge",
3993 .probe = myri10ge_probe,
3994 .remove = myri10ge_remove,
3995 .id_table = myri10ge_pci_tbl,
3996#ifdef CONFIG_PM
3997 .suspend = myri10ge_suspend,
3998 .resume = myri10ge_resume,
3999#endif
4000};
4001
5dd2d332 4002#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4003static int
4004myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4005{
4006 int err = driver_for_each_device(&myri10ge_driver.driver,
4007 NULL, &event,
4008 myri10ge_notify_dca_device);
4009
4010 if (err)
4011 return NOTIFY_BAD;
4012 return NOTIFY_DONE;
4013}
4014
4015static struct notifier_block myri10ge_dca_notifier = {
4016 .notifier_call = myri10ge_notify_dca,
4017 .next = NULL,
4018 .priority = 0,
4019};
4ee2ac51 4020#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4021
0da34b6d
BG		 4022static __init int myri10ge_init_module(void)
4023{
78ca90ea 4024 pr_info("Version %s\n", MYRI10GE_VERSION_STR);
0dcffac1 4025
236bb5e6 4026 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
78ca90ea
JP		 4027 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4028 myri10ge_rss_hash);
0dcffac1
BG		 4029 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4030 }
5dd2d332 4031#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4032 dca_register_notify(&myri10ge_dca_notifier);
4033#endif
236bb5e6
BG		 4034 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4035 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4036
0da34b6d
BG		 4037 return pci_register_driver(&myri10ge_driver);
4038}
4039
4040module_init(myri10ge_init_module);
4041
4042static __exit void myri10ge_cleanup_module(void)
4043{
5dd2d332 4044#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4045 dca_unregister_notify(&myri10ge_dca_notifier);
4046#endif
0da34b6d
BG		 4047 pci_unregister_driver(&myri10ge_driver);
4048}
4049
4050module_exit(myri10ge_cleanup_module);
Linux 6.x block layer and io_uring tree(s)