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IB/mlx5: Add CQE version 1 support to user QPs and SRQs
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e3297246 42#include <linux/delay.h>
e126ba97
EC		 43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
f66f049f 48#include <linux/kmod.h>
89d44f0a 49#include <linux/delay.h>
b775516b 50#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 51#include "mlx5_core.h"
52
e126ba97 53MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 54MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRIVER_VERSION);
57
58int mlx5_core_debug_mask;
59module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
60MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
61
9603b61d
JM		 62#define MLX5_DEFAULT_PROF 2
63static int prof_sel = MLX5_DEFAULT_PROF;
64module_param_named(prof_sel, prof_sel, int, 0444);
65MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
66
9603b61d
JM		 67static LIST_HEAD(intf_list);
68static LIST_HEAD(dev_list);
69static DEFINE_MUTEX(intf_mutex);
70
71struct mlx5_device_context {
72 struct list_head list;
73 struct mlx5_interface *intf;
74 void *context;
75};
76
f91e6d89
EBE		 77enum {
78 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
79 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
80};
81
9603b61d
JM		 82static struct mlx5_profile profile[] = {
83 [0] = {
84 .mask = 0,
85 },
86 [1] = {
87 .mask = MLX5_PROF_MASK_QP_SIZE,
88 .log_max_qp = 12,
89 },
90 [2] = {
91 .mask = MLX5_PROF_MASK_QP_SIZE |
92 MLX5_PROF_MASK_MR_CACHE,
93 .log_max_qp = 17,
94 .mr_cache[0] = {
95 .size = 500,
96 .limit = 250
97 },
98 .mr_cache[1] = {
99 .size = 500,
100 .limit = 250
101 },
102 .mr_cache[2] = {
103 .size = 500,
104 .limit = 250
105 },
106 .mr_cache[3] = {
107 .size = 500,
108 .limit = 250
109 },
110 .mr_cache[4] = {
111 .size = 500,
112 .limit = 250
113 },
114 .mr_cache[5] = {
115 .size = 500,
116 .limit = 250
117 },
118 .mr_cache[6] = {
119 .size = 500,
120 .limit = 250
121 },
122 .mr_cache[7] = {
123 .size = 500,
124 .limit = 250
125 },
126 .mr_cache[8] = {
127 .size = 500,
128 .limit = 250
129 },
130 .mr_cache[9] = {
131 .size = 500,
132 .limit = 250
133 },
134 .mr_cache[10] = {
135 .size = 500,
136 .limit = 250
137 },
138 .mr_cache[11] = {
139 .size = 500,
140 .limit = 250
141 },
142 .mr_cache[12] = {
143 .size = 64,
144 .limit = 32
145 },
146 .mr_cache[13] = {
147 .size = 32,
148 .limit = 16
149 },
150 .mr_cache[14] = {
151 .size = 16,
152 .limit = 8
153 },
154 .mr_cache[15] = {
155 .size = 8,
156 .limit = 4
157 },
158 },
159};
e126ba97 160
e3297246
EC		 161#define FW_INIT_TIMEOUT_MILI 2000
162#define FW_INIT_WAIT_MS 2
163
164static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
165{
166 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
167 int err = 0;
168
169 while (fw_initializing(dev)) {
170 if (time_after(jiffies, end)) {
171 err = -EBUSY;
172 break;
173 }
174 msleep(FW_INIT_WAIT_MS);
175 }
176
177 return err;
178}
179
e126ba97
EC		 180static int set_dma_caps(struct pci_dev *pdev)
181{
182 int err;
183
184 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
185 if (err) {
1a91de28 186 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 187 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
188 if (err) {
1a91de28 189 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 190 return err;
191 }
192 }
193
194 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
195 if (err) {
196 dev_warn(&pdev->dev,
1a91de28 197 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 198 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
199 if (err) {
200 dev_err(&pdev->dev,
1a91de28 201 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 202 return err;
203 }
204 }
205
206 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
207 return err;
208}
209
89d44f0a
MD		 210static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
211{
212 struct pci_dev *pdev = dev->pdev;
213 int err = 0;
214
215 mutex_lock(&dev->pci_status_mutex);
216 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
217 err = pci_enable_device(pdev);
218 if (!err)
219 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
220 }
221 mutex_unlock(&dev->pci_status_mutex);
222
223 return err;
224}
225
226static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
227{
228 struct pci_dev *pdev = dev->pdev;
229
230 mutex_lock(&dev->pci_status_mutex);
231 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
232 pci_disable_device(pdev);
233 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
234 }
235 mutex_unlock(&dev->pci_status_mutex);
236}
237
e126ba97
EC		 238static int request_bar(struct pci_dev *pdev)
239{
240 int err = 0;
241
242 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 243 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 244 return -ENODEV;
245 }
246
247 err = pci_request_regions(pdev, DRIVER_NAME);
248 if (err)
249 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
250
251 return err;
252}
253
254static void release_bar(struct pci_dev *pdev)
255{
256 pci_release_regions(pdev);
257}
258
259static int mlx5_enable_msix(struct mlx5_core_dev *dev)
260{
db058a18
SM		 261 struct mlx5_priv *priv = &dev->priv;
262 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 263 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 264 int nvec;
e126ba97
EC		 265 int i;
266
938fe83c
SM		 267 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
268 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 269 nvec = min_t(int, nvec, num_eqs);
270 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
271 return -ENOMEM;
272
db058a18
SM		 273 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
274
275 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
276 if (!priv->msix_arr || !priv->irq_info)
277 goto err_free_msix;
e126ba97
EC		 278
279 for (i = 0; i < nvec; i++)
db058a18 280 priv->msix_arr[i].entry = i;
e126ba97 281
db058a18 282 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 283 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 284 if (nvec < 0)
285 return nvec;
e126ba97 286
f3c9407b 287 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 288
289 return 0;
db058a18
SM		 290
291err_free_msix:
292 kfree(priv->irq_info);
293 kfree(priv->msix_arr);
294 return -ENOMEM;
e126ba97
EC		 295}
296
297static void mlx5_disable_msix(struct mlx5_core_dev *dev)
298{
db058a18 299 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 300
301 pci_disable_msix(dev->pdev);
db058a18
SM		 302 kfree(priv->irq_info);
303 kfree(priv->msix_arr);
e126ba97
EC		 304}
305
306struct mlx5_reg_host_endianess {
307 u8 he;
308 u8 rsvd[15];
309};
310
87b8de49
EC		 311
312#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
313
314enum {
c7a08ac7
EC		 315 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
316 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 317};
318
c7a08ac7
EC		 319static u16 to_fw_pkey_sz(u32 size)
320{
321 switch (size) {
322 case 128:
323 return 0;
324 case 256:
325 return 1;
326 case 512:
327 return 2;
328 case 1024:
329 return 3;
330 case 2048:
331 return 4;
332 case 4096:
333 return 5;
334 default:
335 pr_warn("invalid pkey table size %d\n", size);
336 return 0;
337 }
338}
339
938fe83c
SM		 340int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
341 enum mlx5_cap_mode cap_mode)
c7a08ac7 342{
b775516b
EC		 343 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
344 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 345 void *out, *hca_caps;
346 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 347 int err;
348
b775516b
EC		 349 memset(in, 0, sizeof(in));
350 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 351 if (!out)
e126ba97 352 return -ENOMEM;
938fe83c 353
b775516b
EC		 354 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
355 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
356 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
357 if (err)
358 goto query_ex;
e126ba97 359
b775516b 360 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7 361 if (err) {
938fe83c
SM		 362 mlx5_core_warn(dev,
363 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
364 cap_type, cap_mode, err);
e126ba97
EC		 365 goto query_ex;
366 }
c7a08ac7 367
938fe83c
SM		 368 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
369
370 switch (cap_mode) {
371 case HCA_CAP_OPMOD_GET_MAX:
372 memcpy(dev->hca_caps_max[cap_type], hca_caps,
373 MLX5_UN_SZ_BYTES(hca_cap_union));
374 break;
375 case HCA_CAP_OPMOD_GET_CUR:
376 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
377 MLX5_UN_SZ_BYTES(hca_cap_union));
378 break;
379 default:
380 mlx5_core_warn(dev,
381 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
382 cap_type, cap_mode);
383 err = -EINVAL;
384 break;
385 }
c7a08ac7
EC		 386query_ex:
387 kfree(out);
388 return err;
389}
390
f91e6d89 391static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
c7a08ac7 392{
b775516b 393 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 394 int err;
395
b775516b 396 memset(out, 0, sizeof(out));
e126ba97 397
b775516b 398 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
f91e6d89 399 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
b775516b 400 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 401 if (err)
c7a08ac7 402 return err;
e126ba97 403
b775516b 404 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 405
406 return err;
407}
408
f91e6d89
EBE		 409static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
410{
411 void *set_ctx;
412 void *set_hca_cap;
413 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
414 int req_endianness;
415 int err;
416
417 if (MLX5_CAP_GEN(dev, atomic)) {
418 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
419 HCA_CAP_OPMOD_GET_CUR);
420 if (err)
421 return err;
422 } else {
423 return 0;
424 }
425
426 req_endianness =
427 MLX5_CAP_ATOMIC(dev,
428 supported_atomic_req_8B_endianess_mode_1);
429
430 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
431 return 0;
432
433 set_ctx = kzalloc(set_sz, GFP_KERNEL);
434 if (!set_ctx)
435 return -ENOMEM;
436
437 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
438
439 /* Set requestor to host endianness */
440 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
441 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
442
443 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
444
445 kfree(set_ctx);
446 return err;
447}
448
c7a08ac7
EC		 449static int handle_hca_cap(struct mlx5_core_dev *dev)
450{
b775516b 451 void *set_ctx = NULL;
c7a08ac7 452 struct mlx5_profile *prof = dev->profile;
c7a08ac7 453 int err = -ENOMEM;
b775516b 454 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 455 void *set_hca_cap;
c7a08ac7 456
b775516b 457 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 458 if (!set_ctx)
e126ba97 459 goto query_ex;
e126ba97 460
938fe83c 461 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
c7a08ac7 462 if (err)
e126ba97 463 goto query_ex;
e126ba97 464
938fe83c 465 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 466 if (err)
467 goto query_ex;
468
938fe83c
SM		 469 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
470 capability);
471 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
472 MLX5_ST_SZ_BYTES(cmd_hca_cap));
473
474 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 475 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 476 128);
c7a08ac7 477 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 478 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
479 to_fw_pkey_sz(128));
c7a08ac7
EC		 480
481 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 482 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
483 prof->log_max_qp);
c7a08ac7 484
938fe83c
SM		 485 /* disable cmdif checksum */
486 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 487
fe1e1876
CS		 488 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
489
f91e6d89
EBE		 490 err = set_caps(dev, set_ctx, set_sz,
491 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
c7a08ac7 492
e126ba97 493query_ex:
e126ba97 494 kfree(set_ctx);
e126ba97
EC		 495 return err;
496}
497
498static int set_hca_ctrl(struct mlx5_core_dev *dev)
499{
500 struct mlx5_reg_host_endianess he_in;
501 struct mlx5_reg_host_endianess he_out;
502 int err;
503
504 memset(&he_in, 0, sizeof(he_in));
505 he_in.he = MLX5_SET_HOST_ENDIANNESS;
506 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
507 &he_out, sizeof(he_out),
508 MLX5_REG_HOST_ENDIANNESS, 0, 1);
509 return err;
510}
511
cd23b14b
EC		 512static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
513{
514 int err;
515 struct mlx5_enable_hca_mbox_in in;
516 struct mlx5_enable_hca_mbox_out out;
517
518 memset(&in, 0, sizeof(in));
519 memset(&out, 0, sizeof(out));
520 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
521 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
522 if (err)
523 return err;
524
525 if (out.hdr.status)
526 return mlx5_cmd_status_to_err(&out.hdr);
527
528 return 0;
529}
530
531static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
532{
533 int err;
534 struct mlx5_disable_hca_mbox_in in;
535 struct mlx5_disable_hca_mbox_out out;
536
537 memset(&in, 0, sizeof(in));
538 memset(&out, 0, sizeof(out));
539 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
540 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
541 if (err)
542 return err;
543
544 if (out.hdr.status)
545 return mlx5_cmd_status_to_err(&out.hdr);
546
547 return 0;
548}
549
db058a18
SM		 550static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
551{
552 struct mlx5_priv *priv = &mdev->priv;
553 struct msix_entry *msix = priv->msix_arr;
554 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
311c7c71 555 int numa_node = priv->numa_node;
db058a18
SM		 556 int err;
557
558 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
559 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
560 return -ENOMEM;
561 }
562
dda922c8
DM		 563 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
564 priv->irq_info[i].mask);
db058a18
SM		 565
566 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
567 if (err) {
568 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
569 irq);
570 goto err_clear_mask;
571 }
572
573 return 0;
574
575err_clear_mask:
576 free_cpumask_var(priv->irq_info[i].mask);
577 return err;
578}
579
580static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
581{
582 struct mlx5_priv *priv = &mdev->priv;
583 struct msix_entry *msix = priv->msix_arr;
584 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
585
586 irq_set_affinity_hint(irq, NULL);
587 free_cpumask_var(priv->irq_info[i].mask);
588}
589
590static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
591{
592 int err;
593 int i;
594
595 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
596 err = mlx5_irq_set_affinity_hint(mdev, i);
597 if (err)
598 goto err_out;
599 }
600
601 return 0;
602
603err_out:
604 for (i--; i >= 0; i--)
605 mlx5_irq_clear_affinity_hint(mdev, i);
606
607 return err;
608}
609
610static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
611{
612 int i;
613
614 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
615 mlx5_irq_clear_affinity_hint(mdev, i);
616}
617
233d05d2
SM		 618int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
619{
620 struct mlx5_eq_table *table = &dev->priv.eq_table;
621 struct mlx5_eq *eq, *n;
622 int err = -ENOENT;
623
624 spin_lock(&table->lock);
625 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
626 if (eq->index == vector) {
627 *eqn = eq->eqn;
628 *irqn = eq->irqn;
629 err = 0;
630 break;
631 }
632 }
633 spin_unlock(&table->lock);
634
635 return err;
636}
637EXPORT_SYMBOL(mlx5_vector2eqn);
638
639static void free_comp_eqs(struct mlx5_core_dev *dev)
640{
641 struct mlx5_eq_table *table = &dev->priv.eq_table;
642 struct mlx5_eq *eq, *n;
643
644 spin_lock(&table->lock);
645 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
646 list_del(&eq->list);
647 spin_unlock(&table->lock);
648 if (mlx5_destroy_unmap_eq(dev, eq))
649 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
650 eq->eqn);
651 kfree(eq);
652 spin_lock(&table->lock);
653 }
654 spin_unlock(&table->lock);
655}
656
657static int alloc_comp_eqs(struct mlx5_core_dev *dev)
658{
659 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 660 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 661 struct mlx5_eq *eq;
662 int ncomp_vec;
663 int nent;
664 int err;
665 int i;
666
667 INIT_LIST_HEAD(&table->comp_eqs_list);
668 ncomp_vec = table->num_comp_vectors;
669 nent = MLX5_COMP_EQ_SIZE;
670 for (i = 0; i < ncomp_vec; i++) {
671 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
672 if (!eq) {
673 err = -ENOMEM;
674 goto clean;
675 }
676
db058a18 677 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 678 err = mlx5_create_map_eq(dev, eq,
679 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
680 name, &dev->priv.uuari.uars[0]);
681 if (err) {
682 kfree(eq);
683 goto clean;
684 }
685 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
686 eq->index = i;
687 spin_lock(&table->lock);
688 list_add_tail(&eq->list, &table->comp_eqs_list);
689 spin_unlock(&table->lock);
690 }
691
692 return 0;
693
694clean:
695 free_comp_eqs(dev);
696 return err;
697}
698
f62b8bb8
AV		 699static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
700{
701 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
702 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
703 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
704 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
705 int err;
706 u32 sup_issi;
707
708 memset(query_in, 0, sizeof(query_in));
709 memset(query_out, 0, sizeof(query_out));
710
711 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
712
713 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
714 query_out, sizeof(query_out));
715 if (err) {
716 if (((struct mlx5_outbox_hdr *)query_out)->status ==
717 MLX5_CMD_STAT_BAD_OP_ERR) {
718 pr_debug("Only ISSI 0 is supported\n");
719 return 0;
720 }
721
722 pr_err("failed to query ISSI\n");
723 return err;
724 }
725
726 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
727
728 if (sup_issi & (1 << 1)) {
729 memset(set_in, 0, sizeof(set_in));
730 memset(set_out, 0, sizeof(set_out));
731
732 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
733 MLX5_SET(set_issi_in, set_in, current_issi, 1);
734
735 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
736 set_out, sizeof(set_out));
737 if (err) {
738 pr_err("failed to set ISSI=1\n");
739 return err;
740 }
741
742 dev->issi = 1;
743
744 return 0;
e74a1db0 745 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 746 return 0;
747 }
748
749 return -ENOTSUPP;
750}
f62b8bb8 751
88a85f99
AS		 752static int map_bf_area(struct mlx5_core_dev *dev)
753{
754 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
755 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
756
757 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
758
759 return dev->priv.bf_mapping ? 0 : -ENOMEM;
760}
761
762static void unmap_bf_area(struct mlx5_core_dev *dev)
763{
764 if (dev->priv.bf_mapping)
765 io_mapping_free(dev->priv.bf_mapping);
766}
767
a31208b1
MD		 768static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
769{
770 struct mlx5_device_context *dev_ctx;
771 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
772
773 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
774 if (!dev_ctx)
775 return;
776
777 dev_ctx->intf = intf;
778 dev_ctx->context = intf->add(dev);
779
780 if (dev_ctx->context) {
781 spin_lock_irq(&priv->ctx_lock);
782 list_add_tail(&dev_ctx->list, &priv->ctx_list);
783 spin_unlock_irq(&priv->ctx_lock);
784 } else {
785 kfree(dev_ctx);
786 }
787}
788
789static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
790{
791 struct mlx5_device_context *dev_ctx;
792 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
793
794 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
795 if (dev_ctx->intf == intf) {
796 spin_lock_irq(&priv->ctx_lock);
797 list_del(&dev_ctx->list);
798 spin_unlock_irq(&priv->ctx_lock);
799
800 intf->remove(dev, dev_ctx->context);
801 kfree(dev_ctx);
802 return;
803 }
804}
805
806static int mlx5_register_device(struct mlx5_core_dev *dev)
e126ba97
EC		 807{
808 struct mlx5_priv *priv = &dev->priv;
a31208b1
MD		 809 struct mlx5_interface *intf;
810
811 mutex_lock(&intf_mutex);
812 list_add_tail(&priv->dev_list, &dev_list);
813 list_for_each_entry(intf, &intf_list, list)
814 mlx5_add_device(intf, priv);
815 mutex_unlock(&intf_mutex);
816
817 return 0;
818}
819
820static void mlx5_unregister_device(struct mlx5_core_dev *dev)
821{
822 struct mlx5_priv *priv = &dev->priv;
823 struct mlx5_interface *intf;
824
825 mutex_lock(&intf_mutex);
826 list_for_each_entry(intf, &intf_list, list)
827 mlx5_remove_device(intf, priv);
828 list_del(&priv->dev_list);
829 mutex_unlock(&intf_mutex);
830}
831
832int mlx5_register_interface(struct mlx5_interface *intf)
833{
834 struct mlx5_priv *priv;
835
836 if (!intf->add || !intf->remove)
837 return -EINVAL;
838
839 mutex_lock(&intf_mutex);
840 list_add_tail(&intf->list, &intf_list);
841 list_for_each_entry(priv, &dev_list, dev_list)
842 mlx5_add_device(intf, priv);
843 mutex_unlock(&intf_mutex);
844
845 return 0;
846}
847EXPORT_SYMBOL(mlx5_register_interface);
848
849void mlx5_unregister_interface(struct mlx5_interface *intf)
850{
851 struct mlx5_priv *priv;
852
853 mutex_lock(&intf_mutex);
854 list_for_each_entry(priv, &dev_list, dev_list)
855 mlx5_remove_device(intf, priv);
856 list_del(&intf->list);
857 mutex_unlock(&intf_mutex);
858}
859EXPORT_SYMBOL(mlx5_unregister_interface);
860
861void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
862{
863 struct mlx5_priv *priv = &mdev->priv;
864 struct mlx5_device_context *dev_ctx;
865 unsigned long flags;
866 void *result = NULL;
867
868 spin_lock_irqsave(&priv->ctx_lock, flags);
869
870 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
871 if ((dev_ctx->intf->protocol == protocol) &&
872 dev_ctx->intf->get_dev) {
873 result = dev_ctx->intf->get_dev(dev_ctx->context);
874 break;
875 }
876
877 spin_unlock_irqrestore(&priv->ctx_lock, flags);
878
879 return result;
880}
881EXPORT_SYMBOL(mlx5_get_protocol_dev);
882
883static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
884{
885 struct pci_dev *pdev = dev->pdev;
886 int err = 0;
e126ba97 887
e126ba97
EC		 888 pci_set_drvdata(dev->pdev, dev);
889 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
890 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
891
892 mutex_init(&priv->pgdir_mutex);
893 INIT_LIST_HEAD(&priv->pgdir_list);
894 spin_lock_init(&priv->mkey_lock);
895
311c7c71
SM		 896 mutex_init(&priv->alloc_mutex);
897
898 priv->numa_node = dev_to_node(&dev->pdev->dev);
899
e126ba97
EC		 900 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
901 if (!priv->dbg_root)
902 return -ENOMEM;
903
89d44f0a 904 err = mlx5_pci_enable_device(dev);
e126ba97 905 if (err) {
1a91de28 906 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 907 goto err_dbg;
908 }
909
910 err = request_bar(pdev);
911 if (err) {
1a91de28 912 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 913 goto err_disable;
914 }
915
916 pci_set_master(pdev);
917
918 err = set_dma_caps(pdev);
919 if (err) {
920 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
921 goto err_clr_master;
922 }
923
924 dev->iseg_base = pci_resource_start(dev->pdev, 0);
925 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
926 if (!dev->iseg) {
927 err = -ENOMEM;
928 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
929 goto err_clr_master;
930 }
a31208b1
MD		 931
932 return 0;
933
934err_clr_master:
935 pci_clear_master(dev->pdev);
936 release_bar(dev->pdev);
937err_disable:
89d44f0a 938 mlx5_pci_disable_device(dev);
a31208b1
MD		 939
940err_dbg:
941 debugfs_remove(priv->dbg_root);
942 return err;
943}
944
945static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
946{
947 iounmap(dev->iseg);
948 pci_clear_master(dev->pdev);
949 release_bar(dev->pdev);
89d44f0a 950 mlx5_pci_disable_device(dev);
a31208b1
MD		 951 debugfs_remove(priv->dbg_root);
952}
953
954#define MLX5_IB_MOD "mlx5_ib"
955static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
956{
957 struct pci_dev *pdev = dev->pdev;
958 int err;
959
89d44f0a
MD		 960 mutex_lock(&dev->intf_state_mutex);
961 if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
962 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
963 __func__);
964 goto out;
965 }
966
e126ba97
EC		 967 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
968 fw_rev_min(dev), fw_rev_sub(dev));
969
89d44f0a
MD		 970 /* on load removing any previous indication of internal error, device is
971 * up
972 */
973 dev->state = MLX5_DEVICE_STATE_UP;
974
e126ba97
EC		 975 err = mlx5_cmd_init(dev);
976 if (err) {
977 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
89d44f0a 978 goto out_err;
e126ba97
EC		 979 }
980
e3297246
EC		 981 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
982 if (err) {
983 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
984 FW_INIT_TIMEOUT_MILI);
985 goto out_err;
986 }
987
e126ba97 988 mlx5_pagealloc_init(dev);
cd23b14b
EC		 989
990 err = mlx5_core_enable_hca(dev);
991 if (err) {
992 dev_err(&pdev->dev, "enable hca failed\n");
993 goto err_pagealloc_cleanup;
994 }
995
f62b8bb8
AV		 996 err = mlx5_core_set_issi(dev);
997 if (err) {
998 dev_err(&pdev->dev, "failed to set issi\n");
999 goto err_disable_hca;
1000 }
f62b8bb8 1001
cd23b14b
EC		 1002 err = mlx5_satisfy_startup_pages(dev, 1);
1003 if (err) {
1004 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1005 goto err_disable_hca;
1006 }
1007
e126ba97
EC		 1008 err = set_hca_ctrl(dev);
1009 if (err) {
1010 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 1011 goto reclaim_boot_pages;
e126ba97
EC		 1012 }
1013
1014 err = handle_hca_cap(dev);
1015 if (err) {
1016 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 1017 goto reclaim_boot_pages;
f91e6d89
EBE		 1018 }
1019
1020 err = handle_hca_cap_atomic(dev);
1021 if (err) {
1022 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1023 goto reclaim_boot_pages;
e126ba97
EC		 1024 }
1025
cd23b14b 1026 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 1027 if (err) {
cd23b14b
EC		 1028 dev_err(&pdev->dev, "failed to allocate init pages\n");
1029 goto reclaim_boot_pages;
e126ba97
EC		 1030 }
1031
1032 err = mlx5_pagealloc_start(dev);
1033 if (err) {
1034 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 1035 goto reclaim_boot_pages;
e126ba97
EC		 1036 }
1037
1038 err = mlx5_cmd_init_hca(dev);
1039 if (err) {
1040 dev_err(&pdev->dev, "init hca failed\n");
1041 goto err_pagealloc_stop;
1042 }
1043
1044 mlx5_start_health_poll(dev);
1045
938fe83c 1046 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 1047 if (err) {
1048 dev_err(&pdev->dev, "query hca failed\n");
1049 goto err_stop_poll;
1050 }
1051
211e6c80 1052 err = mlx5_query_board_id(dev);
e126ba97 1053 if (err) {
211e6c80 1054 dev_err(&pdev->dev, "query board id failed\n");
e126ba97
EC		 1055 goto err_stop_poll;
1056 }
1057
1058 err = mlx5_enable_msix(dev);
1059 if (err) {
1060 dev_err(&pdev->dev, "enable msix failed\n");
1061 goto err_stop_poll;
1062 }
1063
1064 err = mlx5_eq_init(dev);
1065 if (err) {
1066 dev_err(&pdev->dev, "failed to initialize eq\n");
1067 goto disable_msix;
1068 }
1069
1070 err = mlx5_alloc_uuars(dev, &priv->uuari);
1071 if (err) {
1072 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1073 goto err_eq_cleanup;
1074 }
1075
1076 err = mlx5_start_eqs(dev);
1077 if (err) {
1078 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1079 goto err_free_uar;
1080 }
1081
233d05d2
SM		 1082 err = alloc_comp_eqs(dev);
1083 if (err) {
1084 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1085 goto err_stop_eqs;
1086 }
1087
88a85f99
AS		 1088 if (map_bf_area(dev))
1089 dev_err(&pdev->dev, "Failed to map blue flame area\n");
1090
db058a18
SM		 1091 err = mlx5_irq_set_affinity_hints(dev);
1092 if (err) {
1093 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
88a85f99 1094 goto err_unmap_bf_area;
db058a18
SM		 1095 }
1096
e126ba97
EC		 1097 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1098
1099 mlx5_init_cq_table(dev);
1100 mlx5_init_qp_table(dev);
1101 mlx5_init_srq_table(dev);
3bcdb17a 1102 mlx5_init_mr_table(dev);
e126ba97 1103
a31208b1
MD		 1104 err = mlx5_register_device(dev);
1105 if (err) {
1106 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1107 goto err_reg_dev;
1108 }
1109
1110 err = request_module_nowait(MLX5_IB_MOD);
1111 if (err)
1112 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1113
89d44f0a
MD		 1114 dev->interface_state = MLX5_INTERFACE_STATE_UP;
1115out:
1116 mutex_unlock(&dev->intf_state_mutex);
1117
e126ba97
EC		 1118 return 0;
1119
a31208b1
MD		 1120err_reg_dev:
1121 mlx5_cleanup_mr_table(dev);
1122 mlx5_cleanup_srq_table(dev);
1123 mlx5_cleanup_qp_table(dev);
1124 mlx5_cleanup_cq_table(dev);
1125 mlx5_irq_clear_affinity_hints(dev);
1126
88a85f99
AS		 1127err_unmap_bf_area:
1128 unmap_bf_area(dev);
1129
db058a18
SM		 1130 free_comp_eqs(dev);
1131
233d05d2
SM		 1132err_stop_eqs:
1133 mlx5_stop_eqs(dev);
1134
e126ba97
EC		 1135err_free_uar:
1136 mlx5_free_uuars(dev, &priv->uuari);
1137
1138err_eq_cleanup:
1139 mlx5_eq_cleanup(dev);
1140
1141disable_msix:
1142 mlx5_disable_msix(dev);
1143
1144err_stop_poll:
1145 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1146 if (mlx5_cmd_teardown_hca(dev)) {
1147 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
89d44f0a 1148 goto out_err;
1bde6e30 1149 }
e126ba97
EC		 1150
1151err_pagealloc_stop:
1152 mlx5_pagealloc_stop(dev);
1153
cd23b14b 1154reclaim_boot_pages:
e126ba97
EC		 1155 mlx5_reclaim_startup_pages(dev);
1156
cd23b14b
EC		 1157err_disable_hca:
1158 mlx5_core_disable_hca(dev);
1159
e126ba97
EC		 1160err_pagealloc_cleanup:
1161 mlx5_pagealloc_cleanup(dev);
1162 mlx5_cmd_cleanup(dev);
1163
89d44f0a
MD		 1164out_err:
1165 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1166 mutex_unlock(&dev->intf_state_mutex);
1167
e126ba97
EC		 1168 return err;
1169}
e126ba97 1170
a31208b1 1171static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
e126ba97 1172{
89d44f0a 1173 int err = 0;
e126ba97 1174
89d44f0a
MD		 1175 mutex_lock(&dev->intf_state_mutex);
1176 if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
1177 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1178 __func__);
1179 goto out;
1180 }
a31208b1
MD		 1181 mlx5_unregister_device(dev);
1182 mlx5_cleanup_mr_table(dev);
e126ba97
EC		 1183 mlx5_cleanup_srq_table(dev);
1184 mlx5_cleanup_qp_table(dev);
1185 mlx5_cleanup_cq_table(dev);
db058a18 1186 mlx5_irq_clear_affinity_hints(dev);
88a85f99 1187 unmap_bf_area(dev);
233d05d2 1188 free_comp_eqs(dev);
e126ba97
EC		 1189 mlx5_stop_eqs(dev);
1190 mlx5_free_uuars(dev, &priv->uuari);
1191 mlx5_eq_cleanup(dev);
1192 mlx5_disable_msix(dev);
1193 mlx5_stop_health_poll(dev);
ac6ea6e8
EC		 1194 err = mlx5_cmd_teardown_hca(dev);
1195 if (err) {
1bde6e30 1196 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1197 goto out;
1bde6e30 1198 }
e126ba97
EC		 1199 mlx5_pagealloc_stop(dev);
1200 mlx5_reclaim_startup_pages(dev);
cd23b14b 1201 mlx5_core_disable_hca(dev);
e126ba97
EC		 1202 mlx5_pagealloc_cleanup(dev);
1203 mlx5_cmd_cleanup(dev);
9603b61d 1204
ac6ea6e8 1205out:
89d44f0a
MD		 1206 dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
1207 mutex_unlock(&dev->intf_state_mutex);
ac6ea6e8 1208 return err;
9603b61d 1209}
64613d94 1210
89d44f0a 1211void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
ac6ea6e8 1212 unsigned long param)
9603b61d
JM		 1213{
1214 struct mlx5_priv *priv = &dev->priv;
1215 struct mlx5_device_context *dev_ctx;
1216 unsigned long flags;
1217
1218 spin_lock_irqsave(&priv->ctx_lock, flags);
1219
1220 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1221 if (dev_ctx->intf->event)
4d2f9bbb 1222 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1223
1224 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1225}
1226
1227struct mlx5_core_event_handler {
1228 void (*event)(struct mlx5_core_dev *dev,
1229 enum mlx5_dev_event event,
1230 void *data);
1231};
1232
f66f049f 1233
9603b61d
JM		 1234static int init_one(struct pci_dev *pdev,
1235 const struct pci_device_id *id)
1236{
1237 struct mlx5_core_dev *dev;
1238 struct mlx5_priv *priv;
1239 int err;
1240
1241 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1242 if (!dev) {
1243 dev_err(&pdev->dev, "kzalloc failed\n");
1244 return -ENOMEM;
1245 }
1246 priv = &dev->priv;
1247
1248 pci_set_drvdata(pdev, dev);
1249
1250 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1251 pr_warn("selected profile out of range, selecting default (%d)\n",
1252 MLX5_DEFAULT_PROF);
1253 prof_sel = MLX5_DEFAULT_PROF;
1254 }
1255 dev->profile = &profile[prof_sel];
a31208b1 1256 dev->pdev = pdev;
9603b61d
JM		 1257 dev->event = mlx5_core_event;
1258
364d1798
EC		 1259 INIT_LIST_HEAD(&priv->ctx_list);
1260 spin_lock_init(&priv->ctx_lock);
89d44f0a
MD		 1261 mutex_init(&dev->pci_status_mutex);
1262 mutex_init(&dev->intf_state_mutex);
a31208b1 1263 err = mlx5_pci_init(dev, priv);
9603b61d 1264 if (err) {
a31208b1
MD		 1265 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1266 goto clean_dev;
9603b61d
JM		 1267 }
1268
ac6ea6e8
EC		 1269 err = mlx5_health_init(dev);
1270 if (err) {
1271 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1272 goto close_pci;
1273 }
1274
a31208b1 1275 err = mlx5_load_one(dev, priv);
9603b61d 1276 if (err) {
a31208b1 1277 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1278 goto clean_health;
9603b61d
JM		 1279 }
1280
1281 return 0;
1282
ac6ea6e8
EC		 1283clean_health:
1284 mlx5_health_cleanup(dev);
a31208b1
MD		 1285close_pci:
1286 mlx5_pci_close(dev, priv);
1287clean_dev:
1288 pci_set_drvdata(pdev, NULL);
9603b61d 1289 kfree(dev);
a31208b1 1290
9603b61d
JM		 1291 return err;
1292}
a31208b1 1293
9603b61d
JM		 1294static void remove_one(struct pci_dev *pdev)
1295{
1296 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
a31208b1 1297 struct mlx5_priv *priv = &dev->priv;
9603b61d 1298
a31208b1
MD		 1299 if (mlx5_unload_one(dev, priv)) {
1300 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1301 mlx5_health_cleanup(dev);
a31208b1
MD		 1302 return;
1303 }
ac6ea6e8 1304 mlx5_health_cleanup(dev);
a31208b1
MD		 1305 mlx5_pci_close(dev, priv);
1306 pci_set_drvdata(pdev, NULL);
9603b61d
JM		 1307 kfree(dev);
1308}
1309
89d44f0a
MD		 1310static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1311 pci_channel_state_t state)
1312{
1313 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1314 struct mlx5_priv *priv = &dev->priv;
1315
1316 dev_info(&pdev->dev, "%s was called\n", __func__);
1317 mlx5_enter_error_state(dev);
1318 mlx5_unload_one(dev, priv);
1319 mlx5_pci_disable_device(dev);
1320 return state == pci_channel_io_perm_failure ?
1321 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1322}
1323
1324static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1325{
1326 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1327 int err = 0;
1328
1329 dev_info(&pdev->dev, "%s was called\n", __func__);
1330
1331 err = mlx5_pci_enable_device(dev);
1332 if (err) {
1333 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1334 , __func__, err);
1335 return PCI_ERS_RESULT_DISCONNECT;
1336 }
1337 pci_set_master(pdev);
1338 pci_set_power_state(pdev, PCI_D0);
1339 pci_restore_state(pdev);
1340
1341 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1342}
1343
1344void mlx5_disable_device(struct mlx5_core_dev *dev)
1345{
1346 mlx5_pci_err_detected(dev->pdev, 0);
1347}
1348
1349/* wait for the device to show vital signs. For now we check
1350 * that we can read the device ID and that the health buffer
1351 * shows a non zero value which is different than 0xffffffff
1352 */
1353static void wait_vital(struct pci_dev *pdev)
1354{
1355 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1356 struct mlx5_core_health *health = &dev->priv.health;
1357 const int niter = 100;
1358 u32 count;
1359 u16 did;
1360 int i;
1361
1362 /* Wait for firmware to be ready after reset */
1363 msleep(1000);
1364 for (i = 0; i < niter; i++) {
1365 if (pci_read_config_word(pdev, 2, &did)) {
1366 dev_warn(&pdev->dev, "failed reading config word\n");
1367 break;
1368 }
1369 if (did == pdev->device) {
1370 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1371 break;
1372 }
1373 msleep(50);
1374 }
1375 if (i == niter)
1376 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1377
1378 for (i = 0; i < niter; i++) {
1379 count = ioread32be(health->health_counter);
1380 if (count && count != 0xffffffff) {
1381 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1382 break;
1383 }
1384 msleep(50);
1385 }
1386
1387 if (i == niter)
1388 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1389}
1390
1391static void mlx5_pci_resume(struct pci_dev *pdev)
1392{
1393 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1394 struct mlx5_priv *priv = &dev->priv;
1395 int err;
1396
1397 dev_info(&pdev->dev, "%s was called\n", __func__);
1398
1399 pci_save_state(pdev);
1400 wait_vital(pdev);
1401
1402 err = mlx5_load_one(dev, priv);
1403 if (err)
1404 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1405 , __func__, err);
1406 else
1407 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1408}
1409
1410static const struct pci_error_handlers mlx5_err_handler = {
1411 .error_detected = mlx5_pci_err_detected,
1412 .slot_reset = mlx5_pci_slot_reset,
1413 .resume = mlx5_pci_resume
1414};
1415
9603b61d 1416static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 1417 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1418 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1419 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1420 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1421 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1422 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1423 { 0, }
1424};
1425
1426MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1427
1428static struct pci_driver mlx5_core_driver = {
1429 .name = DRIVER_NAME,
1430 .id_table = mlx5_core_pci_table,
1431 .probe = init_one,
89d44f0a
MD		 1432 .remove = remove_one,
1433 .err_handler = &mlx5_err_handler
9603b61d 1434};
e126ba97
EC		 1435
1436static int __init init(void)
1437{
1438 int err;
1439
1440 mlx5_register_debugfs();
e126ba97 1441
9603b61d
JM		 1442 err = pci_register_driver(&mlx5_core_driver);
1443 if (err)
ac6ea6e8 1444 goto err_debug;
9603b61d 1445
f62b8bb8
AV		 1446#ifdef CONFIG_MLX5_CORE_EN
1447 mlx5e_init();
1448#endif
1449
e126ba97
EC		 1450 return 0;
1451
e126ba97
EC		 1452err_debug:
1453 mlx5_unregister_debugfs();
1454 return err;
1455}
1456
1457static void __exit cleanup(void)
1458{
f62b8bb8
AV		 1459#ifdef CONFIG_MLX5_CORE_EN
1460 mlx5e_cleanup();
1461#endif
9603b61d 1462 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1463 mlx5_unregister_debugfs();
1464}
1465
1466module_init(init);
1467module_exit(cleanup);
Linux 6.x block layer and io_uring tree(s)