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Merge tag 'mfd-fixes-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rx.c
CommitLineData
e586b3b0
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/ip.h>
34#include <linux/ipv6.h>
35#include <linux/tcp.h>
7ae92ae5 36#include <net/busy_poll.h>
e586b3b0 37#include "en.h"
12185a9f 38#include "en_tc.h"
e586b3b0 39
ef9814de
EBE		 40static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
41{
42 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
43}
44
7219ab34
TT		 45static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
46 void *data)
47{
48 u32 ci = cqcc & cq->wq.sz_m1;
49
50 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
51}
52
53static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
54 struct mlx5e_cq *cq, u32 cqcc)
55{
56 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
57 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
58 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
59 rq->stats.cqe_compress_blks++;
60}
61
62static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
63{
64 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
65 cq->mini_arr_idx = 0;
66}
67
68static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
69{
70 u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
71 u32 wq_sz = 1 << cq->wq.log_sz;
72 u32 ci = cqcc & cq->wq.sz_m1;
73 u32 ci_top = min_t(u32, wq_sz, ci + n);
74
75 for (; ci < ci_top; ci++, n--) {
76 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
77
78 cqe->op_own = op_own;
79 }
80
81 if (unlikely(ci == wq_sz)) {
82 op_own = !op_own;
83 for (ci = 0; ci < n; ci++) {
84 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
85
86 cqe->op_own = op_own;
87 }
88 }
89}
90
91static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
92 struct mlx5e_cq *cq, u32 cqcc)
93{
94 u16 wqe_cnt_step;
95
96 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
97 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
98 cq->title.op_own &= 0xf0;
99 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz);
100 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
101
102 wqe_cnt_step =
103 rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
104 mpwrq_get_cqe_consumed_strides(&cq->title) : 1;
105 cq->decmprs_wqe_counter =
106 (cq->decmprs_wqe_counter + wqe_cnt_step) & rq->wq.sz_m1;
107}
108
109static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
110 struct mlx5e_cq *cq, u32 cqcc)
111{
112 mlx5e_decompress_cqe(rq, cq, cqcc);
113 cq->title.rss_hash_type = 0;
114 cq->title.rss_hash_result = 0;
115}
116
117static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
118 struct mlx5e_cq *cq,
119 int update_owner_only,
120 int budget_rem)
121{
122 u32 cqcc = cq->wq.cc + update_owner_only;
123 u32 cqe_count;
124 u32 i;
125
126 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
127
128 for (i = update_owner_only; i < cqe_count;
129 i++, cq->mini_arr_idx++, cqcc++) {
d9d9f156 130 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
7219ab34
TT		 131 mlx5e_read_mini_arr_slot(cq, cqcc);
132
133 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
134 rq->handle_rx_cqe(rq, &cq->title);
135 }
136 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
137 cq->wq.cc = cqcc;
138 cq->decmprs_left -= cqe_count;
139 rq->stats.cqe_compress_pkts += cqe_count;
140
141 return cqe_count;
142}
143
144static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
145 struct mlx5e_cq *cq,
146 int budget_rem)
147{
148 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
149 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
150 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
151 rq->handle_rx_cqe(rq, &cq->title);
152 cq->mini_arr_idx++;
153
154 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
155}
156
157void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val)
158{
159 bool was_opened;
160
161 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
162 return;
163
164 mutex_lock(&priv->state_lock);
165
166 if (priv->params.rx_cqe_compress == val)
167 goto unlock;
168
169 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
170 if (was_opened)
171 mlx5e_close_locked(priv->netdev);
172
173 priv->params.rx_cqe_compress = val;
174
175 if (was_opened)
176 mlx5e_open_locked(priv->netdev);
177
178unlock:
179 mutex_unlock(&priv->state_lock);
180}
181
2f48af12 182int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
e586b3b0
AV		 183{
184 struct sk_buff *skb;
185 dma_addr_t dma_addr;
186
c5adb96f 187 skb = napi_alloc_skb(rq->cq.napi, rq->wqe_sz);
e586b3b0
AV		 188 if (unlikely(!skb))
189 return -ENOMEM;
190
e586b3b0
AV		 191 dma_addr = dma_map_single(rq->pdev,
192 /* hw start padding */
fc11fbf9
SM		 193 skb->data,
194 /* hw end padding */
e586b3b0
AV		 195 rq->wqe_sz,
196 DMA_FROM_DEVICE);
197
198 if (unlikely(dma_mapping_error(rq->pdev, dma_addr)))
199 goto err_free_skb;
200
201 *((dma_addr_t *)skb->cb) = dma_addr;
c5adb96f 202 wqe->data.addr = cpu_to_be64(dma_addr);
bc77b240 203 wqe->data.lkey = rq->mkey_be;
e586b3b0
AV		 204
205 rq->skb[ix] = skb;
206
207 return 0;
208
209err_free_skb:
210 dev_kfree_skb(skb);
211
212 return -ENOMEM;
213}
214
d9d9f156
TT		 215static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
216{
217 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
218}
219
bc77b240
TT		 220static inline void
221mlx5e_dma_pre_sync_linear_mpwqe(struct device *pdev,
222 struct mlx5e_mpw_info *wi,
223 u32 wqe_offset, u32 len)
224{
225 dma_sync_single_for_cpu(pdev, wi->dma_info.addr + wqe_offset,
226 len, DMA_FROM_DEVICE);
227}
228
229static inline void
230mlx5e_dma_pre_sync_fragmented_mpwqe(struct device *pdev,
231 struct mlx5e_mpw_info *wi,
232 u32 wqe_offset, u32 len)
233{
234 /* No dma pre sync for fragmented MPWQE */
235}
236
237static inline void
d9d9f156 238mlx5e_add_skb_frag_linear_mpwqe(struct mlx5e_rq *rq,
bc77b240
TT		 239 struct sk_buff *skb,
240 struct mlx5e_mpw_info *wi,
241 u32 page_idx, u32 frag_offset,
242 u32 len)
243{
d9d9f156 244 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
bc77b240
TT		 245
246 wi->skbs_frags[page_idx]++;
247 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
248 &wi->dma_info.page[page_idx], frag_offset,
249 len, truesize);
250}
251
252static inline void
d9d9f156 253mlx5e_add_skb_frag_fragmented_mpwqe(struct mlx5e_rq *rq,
bc77b240
TT		 254 struct sk_buff *skb,
255 struct mlx5e_mpw_info *wi,
256 u32 page_idx, u32 frag_offset,
257 u32 len)
258{
d9d9f156 259 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
bc77b240 260
d9d9f156 261 dma_sync_single_for_cpu(rq->pdev,
bc77b240
TT		 262 wi->umr.dma_info[page_idx].addr + frag_offset,
263 len, DMA_FROM_DEVICE);
264 wi->skbs_frags[page_idx]++;
265 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
266 wi->umr.dma_info[page_idx].page, frag_offset,
267 len, truesize);
268}
269
270static inline void
271mlx5e_copy_skb_header_linear_mpwqe(struct device *pdev,
272 struct sk_buff *skb,
273 struct mlx5e_mpw_info *wi,
274 u32 page_idx, u32 offset,
275 u32 headlen)
276{
277 struct page *page = &wi->dma_info.page[page_idx];
278
279 skb_copy_to_linear_data(skb, page_address(page) + offset,
280 ALIGN(headlen, sizeof(long)));
281}
282
283static inline void
284mlx5e_copy_skb_header_fragmented_mpwqe(struct device *pdev,
285 struct sk_buff *skb,
286 struct mlx5e_mpw_info *wi,
287 u32 page_idx, u32 offset,
288 u32 headlen)
289{
290 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
291 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
292 unsigned int len;
293
294 /* Aligning len to sizeof(long) optimizes memcpy performance */
295 len = ALIGN(headlen_pg, sizeof(long));
296 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
297 DMA_FROM_DEVICE);
298 skb_copy_to_linear_data_offset(skb, 0,
299 page_address(dma_info->page) + offset,
300 len);
bc77b240
TT		 301 if (unlikely(offset + headlen > PAGE_SIZE)) {
302 dma_info++;
303 headlen_pg = len;
304 len = ALIGN(headlen - headlen_pg, sizeof(long));
305 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
306 DMA_FROM_DEVICE);
307 skb_copy_to_linear_data_offset(skb, headlen_pg,
308 page_address(dma_info->page),
309 len);
310 }
bc77b240
TT		 311}
312
313static u16 mlx5e_get_wqe_mtt_offset(u16 rq_ix, u16 wqe_ix)
314{
315 return rq_ix * MLX5_CHANNEL_MAX_NUM_MTTS +
316 wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
317}
318
319static void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
320 struct mlx5e_sq *sq,
321 struct mlx5e_umr_wqe *wqe,
322 u16 ix)
323{
324 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
325 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
326 struct mlx5_wqe_data_seg *dseg = &wqe->data;
327 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
328 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
329 u16 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq->ix, ix);
330
331 memset(wqe, 0, sizeof(*wqe));
332 cseg->opmod_idx_opcode =
333 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
334 MLX5_OPCODE_UMR);
335 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
336 ds_cnt);
337 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
338 cseg->imm = rq->umr_mkey_be;
339
340 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
341 ucseg->klm_octowords =
342 cpu_to_be16(mlx5e_get_mtt_octw(MLX5_MPWRQ_PAGES_PER_WQE));
343 ucseg->bsf_octowords =
344 cpu_to_be16(mlx5e_get_mtt_octw(umr_wqe_mtt_offset));
345 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
346
347 dseg->lkey = sq->mkey_be;
348 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
349}
350
351static void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
352{
353 struct mlx5e_sq *sq = &rq->channel->icosq;
354 struct mlx5_wq_cyc *wq = &sq->wq;
355 struct mlx5e_umr_wqe *wqe;
356 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
357 u16 pi;
358
359 /* fill sq edge with nops to avoid wqe wrap around */
360 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
361 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
362 sq->ico_wqe_info[pi].num_wqebbs = 1;
363 mlx5e_send_nop(sq, true);
364 }
365
366 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
367 mlx5e_build_umr_wqe(rq, sq, wqe, ix);
368 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_UMR;
369 sq->ico_wqe_info[pi].num_wqebbs = num_wqebbs;
370 sq->pc += num_wqebbs;
371 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
372}
373
374static inline int mlx5e_get_wqe_mtt_sz(void)
375{
376 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
377 * To avoid copying garbage after the mtt array, we allocate
378 * a little more.
379 */
380 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
381 MLX5_UMR_MTT_ALIGNMENT);
382}
383
384static int mlx5e_alloc_and_map_page(struct mlx5e_rq *rq,
385 struct mlx5e_mpw_info *wi,
386 int i)
387{
388 struct page *page;
389
390 page = dev_alloc_page();
391 if (unlikely(!page))
392 return -ENOMEM;
393
394 wi->umr.dma_info[i].page = page;
395 wi->umr.dma_info[i].addr = dma_map_page(rq->pdev, page, 0, PAGE_SIZE,
396 PCI_DMA_FROMDEVICE);
397 if (unlikely(dma_mapping_error(rq->pdev, wi->umr.dma_info[i].addr))) {
398 put_page(page);
399 return -ENOMEM;
400 }
401 wi->umr.mtt[i] = cpu_to_be64(wi->umr.dma_info[i].addr | MLX5_EN_WR);
402
403 return 0;
404}
405
406static int mlx5e_alloc_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
407 struct mlx5e_rx_wqe *wqe,
408 u16 ix)
409{
410 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
411 int mtt_sz = mlx5e_get_wqe_mtt_sz();
412 u32 dma_offset = mlx5e_get_wqe_mtt_offset(rq->ix, ix) << PAGE_SHIFT;
413 int i;
414
415 wi->umr.dma_info = kmalloc(sizeof(*wi->umr.dma_info) *
416 MLX5_MPWRQ_PAGES_PER_WQE,
417 GFP_ATOMIC);
418 if (unlikely(!wi->umr.dma_info))
419 goto err_out;
420
421 /* We allocate more than mtt_sz as we will align the pointer */
422 wi->umr.mtt_no_align = kzalloc(mtt_sz + MLX5_UMR_ALIGN - 1,
423 GFP_ATOMIC);
424 if (unlikely(!wi->umr.mtt_no_align))
425 goto err_free_umr;
426
427 wi->umr.mtt = PTR_ALIGN(wi->umr.mtt_no_align, MLX5_UMR_ALIGN);
428 wi->umr.mtt_addr = dma_map_single(rq->pdev, wi->umr.mtt, mtt_sz,
429 PCI_DMA_TODEVICE);
430 if (unlikely(dma_mapping_error(rq->pdev, wi->umr.mtt_addr)))
431 goto err_free_mtt;
432
433 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
434 if (unlikely(mlx5e_alloc_and_map_page(rq, wi, i)))
435 goto err_unmap;
0139aa7b
JK		 436 page_ref_add(wi->umr.dma_info[i].page,
437 mlx5e_mpwqe_strides_per_page(rq));
bc77b240
TT		 438 wi->skbs_frags[i] = 0;
439 }
440
441 wi->consumed_strides = 0;
442 wi->dma_pre_sync = mlx5e_dma_pre_sync_fragmented_mpwqe;
443 wi->add_skb_frag = mlx5e_add_skb_frag_fragmented_mpwqe;
444 wi->copy_skb_header = mlx5e_copy_skb_header_fragmented_mpwqe;
445 wi->free_wqe = mlx5e_free_rx_fragmented_mpwqe;
446 wqe->data.lkey = rq->umr_mkey_be;
447 wqe->data.addr = cpu_to_be64(dma_offset);
448
449 return 0;
450
451err_unmap:
452 while (--i >= 0) {
453 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE,
454 PCI_DMA_FROMDEVICE);
0139aa7b
JK		 455 page_ref_sub(wi->umr.dma_info[i].page,
456 mlx5e_mpwqe_strides_per_page(rq));
bc77b240
TT		 457 put_page(wi->umr.dma_info[i].page);
458 }
459 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE);
460
461err_free_mtt:
462 kfree(wi->umr.mtt_no_align);
463
464err_free_umr:
465 kfree(wi->umr.dma_info);
466
467err_out:
468 return -ENOMEM;
469}
470
471void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
472 struct mlx5e_mpw_info *wi)
473{
474 int mtt_sz = mlx5e_get_wqe_mtt_sz();
475 int i;
476
477 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
478 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE,
479 PCI_DMA_FROMDEVICE);
0139aa7b
JK		 480 page_ref_sub(wi->umr.dma_info[i].page,
481 mlx5e_mpwqe_strides_per_page(rq) - wi->skbs_frags[i]);
bc77b240
TT		 482 put_page(wi->umr.dma_info[i].page);
483 }
484 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE);
485 kfree(wi->umr.mtt_no_align);
486 kfree(wi->umr.dma_info);
487}
488
489void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq)
490{
491 struct mlx5_wq_ll *wq = &rq->wq;
492 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
493
494 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
495 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
496 rq->stats.mpwqe_frag++;
497
498 /* ensure wqes are visible to device before updating doorbell record */
499 dma_wmb();
500
501 mlx5_wq_ll_update_db_record(wq);
502}
503
504static int mlx5e_alloc_rx_linear_mpwqe(struct mlx5e_rq *rq,
505 struct mlx5e_rx_wqe *wqe,
506 u16 ix)
461017cb
TT		 507{
508 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
509 gfp_t gfp_mask;
510 int i;
511
512 gfp_mask = GFP_ATOMIC | __GFP_COLD | __GFP_MEMALLOC;
513 wi->dma_info.page = alloc_pages_node(NUMA_NO_NODE, gfp_mask,
514 MLX5_MPWRQ_WQE_PAGE_ORDER);
515 if (unlikely(!wi->dma_info.page))
516 return -ENOMEM;
517
518 wi->dma_info.addr = dma_map_page(rq->pdev, wi->dma_info.page, 0,
519 rq->wqe_sz, PCI_DMA_FROMDEVICE);
520 if (unlikely(dma_mapping_error(rq->pdev, wi->dma_info.addr))) {
521 put_page(wi->dma_info.page);
522 return -ENOMEM;
523 }
524
525 /* We split the high-order page into order-0 ones and manage their
526 * reference counter to minimize the memory held by small skb fragments
527 */
528 split_page(wi->dma_info.page, MLX5_MPWRQ_WQE_PAGE_ORDER);
529 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
0139aa7b
JK		 530 page_ref_add(&wi->dma_info.page[i],
531 mlx5e_mpwqe_strides_per_page(rq));
461017cb
TT		 532 wi->skbs_frags[i] = 0;
533 }
534
535 wi->consumed_strides = 0;
bc77b240
TT		 536 wi->dma_pre_sync = mlx5e_dma_pre_sync_linear_mpwqe;
537 wi->add_skb_frag = mlx5e_add_skb_frag_linear_mpwqe;
538 wi->copy_skb_header = mlx5e_copy_skb_header_linear_mpwqe;
539 wi->free_wqe = mlx5e_free_rx_linear_mpwqe;
540 wqe->data.lkey = rq->mkey_be;
541 wqe->data.addr = cpu_to_be64(wi->dma_info.addr);
542
543 return 0;
544}
545
546void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
547 struct mlx5e_mpw_info *wi)
548{
549 int i;
550
551 dma_unmap_page(rq->pdev, wi->dma_info.addr, rq->wqe_sz,
552 PCI_DMA_FROMDEVICE);
553 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
0139aa7b
JK		 554 page_ref_sub(&wi->dma_info.page[i],
555 mlx5e_mpwqe_strides_per_page(rq) - wi->skbs_frags[i]);
bc77b240
TT		 556 put_page(&wi->dma_info.page[i]);
557 }
558}
559
560int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
561{
562 int err;
563
564 err = mlx5e_alloc_rx_linear_mpwqe(rq, wqe, ix);
565 if (unlikely(err)) {
566 err = mlx5e_alloc_rx_fragmented_mpwqe(rq, wqe, ix);
567 if (unlikely(err))
568 return err;
569 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
570 mlx5e_post_umr_wqe(rq, ix);
571 return -EBUSY;
572 }
461017cb
TT		 573
574 return 0;
575}
576
bc77b240
TT		 577#define RQ_CANNOT_POST(rq) \
578 (!test_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state) || \
579 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
580
e586b3b0
AV		 581bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
582{
583 struct mlx5_wq_ll *wq = &rq->wq;
584
bc77b240 585 if (unlikely(RQ_CANNOT_POST(rq)))
e586b3b0
AV		 586 return false;
587
588 while (!mlx5_wq_ll_is_full(wq)) {
589 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
54984407 590 int err;
e586b3b0 591
54984407
TT		 592 err = rq->alloc_wqe(rq, wqe, wq->head);
593 if (unlikely(err)) {
594 if (err != -EBUSY)
595 rq->stats.buff_alloc_err++;
e586b3b0 596 break;
54984407 597 }
e586b3b0
AV		 598
599 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
600 }
601
602 /* ensure wqes are visible to device before updating doorbell record */
603 dma_wmb();
604
605 mlx5_wq_ll_update_db_record(wq);
606
607 return !mlx5_wq_ll_is_full(wq);
608}
609
461017cb
TT		 610static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
611 u32 cqe_bcnt)
e586b3b0
AV		 612{
613 struct ethhdr *eth = (struct ethhdr *)(skb->data);
614 struct iphdr *ipv4 = (struct iphdr *)(skb->data + ETH_HLEN);
615 struct ipv6hdr *ipv6 = (struct ipv6hdr *)(skb->data + ETH_HLEN);
616 struct tcphdr *tcp;
617
618 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
619 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
620 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
621
461017cb 622 u16 tot_len = cqe_bcnt - ETH_HLEN;
e586b3b0
AV		 623
624 if (eth->h_proto == htons(ETH_P_IP)) {
625 tcp = (struct tcphdr *)(skb->data + ETH_HLEN +
626 sizeof(struct iphdr));
627 ipv6 = NULL;
d9a40271 628 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
e586b3b0
AV		 629 } else {
630 tcp = (struct tcphdr *)(skb->data + ETH_HLEN +
631 sizeof(struct ipv6hdr));
632 ipv4 = NULL;
d9a40271 633 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
e586b3b0
AV		 634 }
635
636 if (get_cqe_lro_tcppsh(cqe))
637 tcp->psh = 1;
638
639 if (tcp_ack) {
640 tcp->ack = 1;
641 tcp->ack_seq = cqe->lro_ack_seq_num;
642 tcp->window = cqe->lro_tcp_win;
643 }
644
645 if (ipv4) {
646 ipv4->ttl = cqe->lro_min_ttl;
647 ipv4->tot_len = cpu_to_be16(tot_len);
648 ipv4->check = 0;
649 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
650 ipv4->ihl);
651 } else {
652 ipv6->hop_limit = cqe->lro_min_ttl;
653 ipv6->payload_len = cpu_to_be16(tot_len -
654 sizeof(struct ipv6hdr));
655 }
656}
657
658static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
659 struct sk_buff *skb)
660{
661 u8 cht = cqe->rss_hash_type;
662 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
663 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
664 PKT_HASH_TYPE_NONE;
665 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
666}
667
bbceefce
AS		 668static inline bool is_first_ethertype_ip(struct sk_buff *skb)
669{
670 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
671
672 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
673}
674
675static inline void mlx5e_handle_csum(struct net_device *netdev,
676 struct mlx5_cqe64 *cqe,
677 struct mlx5e_rq *rq,
5f6d12d1
MF		 678 struct sk_buff *skb,
679 bool lro)
bbceefce
AS		 680{
681 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
682 goto csum_none;
683
5f6d12d1 684 if (lro) {
bbceefce 685 skb->ip_summed = CHECKSUM_UNNECESSARY;
1b223dd3
SM		 686 return;
687 }
688
689 if (is_first_ethertype_ip(skb)) {
bbceefce 690 skb->ip_summed = CHECKSUM_COMPLETE;
ecf842f6 691 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
bfe6d8d1 692 rq->stats.csum_complete++;
1b223dd3 693 return;
bbceefce
AS		 694 }
695
1b223dd3
SM		 696 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
697 (cqe->hds_ip_ext & CQE_L4_OK))) {
698 skb->ip_summed = CHECKSUM_UNNECESSARY;
699 if (cqe_is_tunneled(cqe)) {
700 skb->csum_level = 1;
701 skb->encapsulation = 1;
bfe6d8d1 702 rq->stats.csum_unnecessary_inner++;
1b223dd3
SM		 703 }
704 return;
705 }
bbceefce
AS		 706csum_none:
707 skb->ip_summed = CHECKSUM_NONE;
708 rq->stats.csum_none++;
709}
710
e586b3b0 711static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
461017cb 712 u32 cqe_bcnt,
e586b3b0
AV		 713 struct mlx5e_rq *rq,
714 struct sk_buff *skb)
715{
716 struct net_device *netdev = rq->netdev;
ef9814de 717 struct mlx5e_tstamp *tstamp = rq->tstamp;
e586b3b0
AV		 718 int lro_num_seg;
719
e586b3b0
AV		 720 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
721 if (lro_num_seg > 1) {
461017cb 722 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
d9a40271 723 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
e586b3b0
AV		 724 rq->stats.lro_packets++;
725 rq->stats.lro_bytes += cqe_bcnt;
726 }
727
ef9814de
EBE		 728 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
729 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
730
e586b3b0
AV		 731 skb_record_rx_queue(skb, rq->ix);
732
733 if (likely(netdev->features & NETIF_F_RXHASH))
734 mlx5e_skb_set_hash(cqe, skb);
735
736 if (cqe_has_vlan(cqe))
737 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
738 be16_to_cpu(cqe->vlan_info));
12185a9f
AV		 739
740 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
e20a0db3
SM		 741
742 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
743 skb->protocol = eth_type_trans(skb, netdev);
e586b3b0
AV		 744}
745
461017cb
TT		 746static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
747 struct mlx5_cqe64 *cqe,
748 u32 cqe_bcnt,
749 struct sk_buff *skb)
750{
751 rq->stats.packets++;
752 rq->stats.bytes += cqe_bcnt;
753 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
754 napi_gro_receive(rq->cq.napi, skb);
755}
756
2f48af12
TT		 757void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
758{
759 struct mlx5e_rx_wqe *wqe;
760 struct sk_buff *skb;
761 __be16 wqe_counter_be;
762 u16 wqe_counter;
461017cb 763 u32 cqe_bcnt;
2f48af12
TT		 764
765 wqe_counter_be = cqe->wqe_counter;
766 wqe_counter = be16_to_cpu(wqe_counter_be);
767 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
768 skb = rq->skb[wqe_counter];
769 prefetch(skb->data);
770 rq->skb[wqe_counter] = NULL;
771
772 dma_unmap_single(rq->pdev,
773 *((dma_addr_t *)skb->cb),
774 rq->wqe_sz,
775 DMA_FROM_DEVICE);
776
777 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
778 rq->stats.wqe_err++;
779 dev_kfree_skb(skb);
780 goto wq_ll_pop;
781 }
782
461017cb
TT		 783 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
784 skb_put(skb, cqe_bcnt);
785
786 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
2f48af12
TT		 787
788wq_ll_pop:
789 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
790 &wqe->next.next_wqe_index);
791}
792
bc77b240
TT		 793static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
794 struct mlx5_cqe64 *cqe,
795 struct mlx5e_mpw_info *wi,
796 u32 cqe_bcnt,
797 struct sk_buff *skb)
798{
d9d9f156 799 u32 consumed_bytes = ALIGN(cqe_bcnt, rq->mpwqe_stride_sz);
bc77b240 800 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
d9d9f156 801 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz;
bc77b240
TT		 802 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
803 u32 page_idx = wqe_offset >> PAGE_SHIFT;
804 u32 head_page_idx = page_idx;
805 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
806 u32 frag_offset = head_offset + headlen;
807 u16 byte_cnt = cqe_bcnt - headlen;
808
bc77b240
TT		 809 if (unlikely(frag_offset >= PAGE_SIZE)) {
810 page_idx++;
811 frag_offset -= PAGE_SIZE;
812 }
bc77b240
TT		 813 wi->dma_pre_sync(rq->pdev, wi, wqe_offset, consumed_bytes);
814
815 while (byte_cnt) {
816 u32 pg_consumed_bytes =
817 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
818
d9d9f156 819 wi->add_skb_frag(rq, skb, wi, page_idx, frag_offset,
bc77b240
TT		 820 pg_consumed_bytes);
821 byte_cnt -= pg_consumed_bytes;
822 frag_offset = 0;
823 page_idx++;
824 }
825 /* copy header */
826 wi->copy_skb_header(rq->pdev, skb, wi, head_page_idx, head_offset,
827 headlen);
828 /* skb linear part was allocated with headlen and aligned to long */
829 skb->tail += headlen;
830 skb->len += headlen;
831}
832
461017cb
TT		 833void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
834{
835 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
461017cb
TT		 836 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
837 struct mlx5e_mpw_info *wi = &rq->wqe_info[wqe_id];
838 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
839 struct sk_buff *skb;
461017cb 840 u16 cqe_bcnt;
461017cb
TT		 841
842 wi->consumed_strides += cstrides;
843
844 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
845 rq->stats.wqe_err++;
846 goto mpwrq_cqe_out;
847 }
848
849 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
850 rq->stats.mpwqe_filler++;
851 goto mpwrq_cqe_out;
852 }
853
c5adb96f
TT		 854 skb = napi_alloc_skb(rq->cq.napi,
855 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
856 sizeof(long)));
54984407
TT		 857 if (unlikely(!skb)) {
858 rq->stats.buff_alloc_err++;
461017cb 859 goto mpwrq_cqe_out;
54984407 860 }
461017cb
TT		 861
862 prefetch(skb->data);
461017cb 863 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
461017cb 864
bc77b240 865 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
461017cb
TT		 866 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
867
868mpwrq_cqe_out:
d9d9f156 869 if (likely(wi->consumed_strides < rq->mpwqe_num_strides))
461017cb
TT		 870 return;
871
bc77b240 872 wi->free_wqe(rq, wi);
461017cb
TT		 873 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
874}
875
44fb6fbb 876int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
e586b3b0 877{
e3391054 878 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
7219ab34 879 int work_done = 0;
e586b3b0 880
7219ab34
TT		 881 if (cq->decmprs_left)
882 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
883
884 for (; work_done < budget; work_done++) {
2f48af12 885 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
e586b3b0 886
e586b3b0
AV		 887 if (!cqe)
888 break;
889
7219ab34
TT		 890 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
891 work_done +=
892 mlx5e_decompress_cqes_start(rq, cq,
893 budget - work_done);
894 continue;
895 }
896
a1f5a1a8
AS		 897 mlx5_cqwq_pop(&cq->wq);
898
2f48af12 899 rq->handle_rx_cqe(rq, cqe);
e586b3b0
AV		 900 }
901
902 mlx5_cqwq_update_db_record(&cq->wq);
903
904 /* ensure cq space is freed before enabling more cqes */
905 wmb();
906
44fb6fbb 907 return work_done;
e586b3b0 908}
Linux 6.x block layer and io_uring tree(s)