projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5e: Move common case counters within sq_stats struct
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
86d722ad 33#include <linux/mlx5/fs.h>
b3f63c3d 34#include <net/vxlan.h>
f62b8bb8 35#include "en.h"
66e49ded 36#include "eswitch.h"
b3f63c3d 37#include "vxlan.h"
f62b8bb8
AV		 38
39struct mlx5e_rq_param {
40 u32 rqc[MLX5_ST_SZ_DW(rqc)];
41 struct mlx5_wq_param wq;
42};
43
44struct mlx5e_sq_param {
45 u32 sqc[MLX5_ST_SZ_DW(sqc)];
46 struct mlx5_wq_param wq;
58d52291 47 u16 max_inline;
f62b8bb8
AV		 48};
49
50struct mlx5e_cq_param {
51 u32 cqc[MLX5_ST_SZ_DW(cqc)];
52 struct mlx5_wq_param wq;
53 u16 eq_ix;
54};
55
56struct mlx5e_channel_param {
57 struct mlx5e_rq_param rq;
58 struct mlx5e_sq_param sq;
59 struct mlx5e_cq_param rx_cq;
60 struct mlx5e_cq_param tx_cq;
61};
62
63static void mlx5e_update_carrier(struct mlx5e_priv *priv)
64{
65 struct mlx5_core_dev *mdev = priv->mdev;
66 u8 port_state;
67
68 port_state = mlx5_query_vport_state(mdev,
e7546514 69 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 70
71 if (port_state == VPORT_STATE_UP)
72 netif_carrier_on(priv->netdev);
73 else
74 netif_carrier_off(priv->netdev);
75}
76
77static void mlx5e_update_carrier_work(struct work_struct *work)
78{
79 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
80 update_carrier_work);
81
82 mutex_lock(&priv->state_lock);
83 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
84 mlx5e_update_carrier(priv);
85 mutex_unlock(&priv->state_lock);
86}
87
efea389d
GP		 88static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
89{
90 struct mlx5_core_dev *mdev = priv->mdev;
91 struct mlx5e_pport_stats *s = &priv->stats.pport;
92 u32 *in;
93 u32 *out;
94 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
95
96 in = mlx5_vzalloc(sz);
97 out = mlx5_vzalloc(sz);
98 if (!in || !out)
99 goto free_out;
100
101 MLX5_SET(ppcnt_reg, in, local_port, 1);
102
103 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
104 mlx5_core_access_reg(mdev, in, sz, out,
105 sz, MLX5_REG_PPCNT, 0, 0);
106 memcpy(s->IEEE_802_3_counters,
107 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
108 sizeof(s->IEEE_802_3_counters));
109
110 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
111 mlx5_core_access_reg(mdev, in, sz, out,
112 sz, MLX5_REG_PPCNT, 0, 0);
113 memcpy(s->RFC_2863_counters,
114 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
115 sizeof(s->RFC_2863_counters));
116
117 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
118 mlx5_core_access_reg(mdev, in, sz, out,
119 sz, MLX5_REG_PPCNT, 0, 0);
120 memcpy(s->RFC_2819_counters,
121 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
122 sizeof(s->RFC_2819_counters));
123
124free_out:
125 kvfree(in);
126 kvfree(out);
127}
128
f62b8bb8
AV		 129void mlx5e_update_stats(struct mlx5e_priv *priv)
130{
131 struct mlx5_core_dev *mdev = priv->mdev;
132 struct mlx5e_vport_stats *s = &priv->stats.vport;
133 struct mlx5e_rq_stats *rq_stats;
134 struct mlx5e_sq_stats *sq_stats;
135 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
136 u32 *out;
137 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
138 u64 tx_offload_none;
139 int i, j;
140
141 out = mlx5_vzalloc(outlen);
142 if (!out)
143 return;
144
145 /* Collect firts the SW counters and then HW for consistency */
146 s->tso_packets = 0;
147 s->tso_bytes = 0;
89db09eb
MF		 148 s->tso_inner_packets = 0;
149 s->tso_inner_bytes = 0;
f62b8bb8
AV		 150 s->tx_queue_stopped = 0;
151 s->tx_queue_wake = 0;
152 s->tx_queue_dropped = 0;
89db09eb 153 s->tx_csum_inner = 0;
f62b8bb8
AV		 154 tx_offload_none = 0;
155 s->lro_packets = 0;
156 s->lro_bytes = 0;
157 s->rx_csum_none = 0;
bbceefce 158 s->rx_csum_sw = 0;
f62b8bb8
AV		 159 s->rx_wqe_err = 0;
160 for (i = 0; i < priv->params.num_channels; i++) {
161 rq_stats = &priv->channel[i]->rq.stats;
162
163 s->lro_packets += rq_stats->lro_packets;
164 s->lro_bytes += rq_stats->lro_bytes;
165 s->rx_csum_none += rq_stats->csum_none;
bbceefce 166 s->rx_csum_sw += rq_stats->csum_sw;
f62b8bb8
AV		 167 s->rx_wqe_err += rq_stats->wqe_err;
168
a4418a6c 169 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 170 sq_stats = &priv->channel[i]->sq[j].stats;
171
172 s->tso_packets += sq_stats->tso_packets;
173 s->tso_bytes += sq_stats->tso_bytes;
89db09eb
MF		 174 s->tso_inner_packets += sq_stats->tso_inner_packets;
175 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 176 s->tx_queue_stopped += sq_stats->stopped;
177 s->tx_queue_wake += sq_stats->wake;
178 s->tx_queue_dropped += sq_stats->dropped;
89db09eb 179 s->tx_csum_inner += sq_stats->csum_offload_inner;
f62b8bb8
AV		 180 tx_offload_none += sq_stats->csum_offload_none;
181 }
182 }
183
184 /* HW counters */
185 memset(in, 0, sizeof(in));
186
187 MLX5_SET(query_vport_counter_in, in, opcode,
188 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
189 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
190 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
191
192 memset(out, 0, outlen);
193
194 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
195 goto free_out;
196
197#define MLX5_GET_CTR(p, x) \
198 MLX5_GET64(query_vport_counter_out, p, x)
199
200 s->rx_error_packets =
201 MLX5_GET_CTR(out, received_errors.packets);
202 s->rx_error_bytes =
203 MLX5_GET_CTR(out, received_errors.octets);
204 s->tx_error_packets =
205 MLX5_GET_CTR(out, transmit_errors.packets);
206 s->tx_error_bytes =
207 MLX5_GET_CTR(out, transmit_errors.octets);
208
209 s->rx_unicast_packets =
210 MLX5_GET_CTR(out, received_eth_unicast.packets);
211 s->rx_unicast_bytes =
212 MLX5_GET_CTR(out, received_eth_unicast.octets);
213 s->tx_unicast_packets =
214 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
215 s->tx_unicast_bytes =
216 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
217
218 s->rx_multicast_packets =
219 MLX5_GET_CTR(out, received_eth_multicast.packets);
220 s->rx_multicast_bytes =
221 MLX5_GET_CTR(out, received_eth_multicast.octets);
222 s->tx_multicast_packets =
223 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
224 s->tx_multicast_bytes =
225 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
226
227 s->rx_broadcast_packets =
228 MLX5_GET_CTR(out, received_eth_broadcast.packets);
229 s->rx_broadcast_bytes =
230 MLX5_GET_CTR(out, received_eth_broadcast.octets);
231 s->tx_broadcast_packets =
232 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
233 s->tx_broadcast_bytes =
234 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
235
236 s->rx_packets =
237 s->rx_unicast_packets +
238 s->rx_multicast_packets +
239 s->rx_broadcast_packets;
240 s->rx_bytes =
241 s->rx_unicast_bytes +
242 s->rx_multicast_bytes +
243 s->rx_broadcast_bytes;
244 s->tx_packets =
245 s->tx_unicast_packets +
246 s->tx_multicast_packets +
247 s->tx_broadcast_packets;
248 s->tx_bytes =
249 s->tx_unicast_bytes +
250 s->tx_multicast_bytes +
251 s->tx_broadcast_bytes;
252
253 /* Update calculated offload counters */
89db09eb 254 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
bbceefce
AS		 255 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
256 s->rx_csum_sw;
f62b8bb8 257
efea389d 258 mlx5e_update_pport_counters(priv);
f62b8bb8
AV		 259free_out:
260 kvfree(out);
261}
262
263static void mlx5e_update_stats_work(struct work_struct *work)
264{
265 struct delayed_work *dwork = to_delayed_work(work);
266 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
267 update_stats_work);
268 mutex_lock(&priv->state_lock);
269 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
270 mlx5e_update_stats(priv);
271 schedule_delayed_work(dwork,
272 msecs_to_jiffies(
273 MLX5E_UPDATE_STATS_INTERVAL));
274 }
275 mutex_unlock(&priv->state_lock);
276}
277
daa21560
TT		 278static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
279 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 280{
daa21560
TT		 281 struct mlx5e_priv *priv = vpriv;
282
283 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
284 return;
285
f62b8bb8
AV		 286 switch (event) {
287 case MLX5_DEV_EVENT_PORT_UP:
288 case MLX5_DEV_EVENT_PORT_DOWN:
289 schedule_work(&priv->update_carrier_work);
290 break;
291
292 default:
293 break;
294 }
295}
296
f62b8bb8
AV		 297static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
298{
299 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
300}
301
302static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
303{
f62b8bb8 304 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
daa21560 305 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 306}
307
facc9699
SM		 308#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
309#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
310
f62b8bb8
AV		 311static int mlx5e_create_rq(struct mlx5e_channel *c,
312 struct mlx5e_rq_param *param,
313 struct mlx5e_rq *rq)
314{
315 struct mlx5e_priv *priv = c->priv;
316 struct mlx5_core_dev *mdev = priv->mdev;
317 void *rqc = param->rqc;
318 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
319 int wq_sz;
320 int err;
321 int i;
322
311c7c71
SM		 323 param->wq.db_numa_node = cpu_to_node(c->cpu);
324
f62b8bb8
AV		 325 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
326 &rq->wq_ctrl);
327 if (err)
328 return err;
329
330 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
331
332 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
333 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
334 cpu_to_node(c->cpu));
335 if (!rq->skb) {
336 err = -ENOMEM;
337 goto err_rq_wq_destroy;
338 }
339
340 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
facc9699 341 MLX5E_SW2HW_MTU(priv->netdev->mtu);
fc11fbf9 342 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
f62b8bb8
AV		 343
344 for (i = 0; i < wq_sz; i++) {
345 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
fc11fbf9 346 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
f62b8bb8
AV		 347
348 wqe->data.lkey = c->mkey_be;
fc11fbf9
SM		 349 wqe->data.byte_count =
350 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
f62b8bb8
AV		 351 }
352
353 rq->pdev = c->pdev;
354 rq->netdev = c->netdev;
ef9814de 355 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 356 rq->channel = c;
357 rq->ix = c->ix;
50cfa25a 358 rq->priv = c->priv;
f62b8bb8
AV		 359
360 return 0;
361
362err_rq_wq_destroy:
363 mlx5_wq_destroy(&rq->wq_ctrl);
364
365 return err;
366}
367
368static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
369{
370 kfree(rq->skb);
371 mlx5_wq_destroy(&rq->wq_ctrl);
372}
373
374static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
375{
50cfa25a 376 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 377 struct mlx5_core_dev *mdev = priv->mdev;
378
379 void *in;
380 void *rqc;
381 void *wq;
382 int inlen;
383 int err;
384
385 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
386 sizeof(u64) * rq->wq_ctrl.buf.npages;
387 in = mlx5_vzalloc(inlen);
388 if (!in)
389 return -ENOMEM;
390
391 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
392 wq = MLX5_ADDR_OF(rqc, rqc, wq);
393
394 memcpy(rqc, param->rqc, sizeof(param->rqc));
395
97de9f31 396 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 397 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
398 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
f62b8bb8 399 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 400 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 401 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
402
403 mlx5_fill_page_array(&rq->wq_ctrl.buf,
404 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
405
7db22ffb 406 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 407
408 kvfree(in);
409
410 return err;
411}
412
413static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
414{
415 struct mlx5e_channel *c = rq->channel;
416 struct mlx5e_priv *priv = c->priv;
417 struct mlx5_core_dev *mdev = priv->mdev;
418
419 void *in;
420 void *rqc;
421 int inlen;
422 int err;
423
424 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
425 in = mlx5_vzalloc(inlen);
426 if (!in)
427 return -ENOMEM;
428
429 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
430
431 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
432 MLX5_SET(rqc, rqc, state, next_state);
433
7db22ffb 434 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 435
436 kvfree(in);
437
438 return err;
439}
440
441static void mlx5e_disable_rq(struct mlx5e_rq *rq)
442{
50cfa25a 443 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 444}
445
446static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
447{
01c196a2 448 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 449 struct mlx5e_channel *c = rq->channel;
450 struct mlx5e_priv *priv = c->priv;
451 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 452
01c196a2 453 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 454 if (wq->cur_sz >= priv->params.min_rx_wqes)
455 return 0;
456
457 msleep(20);
458 }
459
460 return -ETIMEDOUT;
461}
462
463static int mlx5e_open_rq(struct mlx5e_channel *c,
464 struct mlx5e_rq_param *param,
465 struct mlx5e_rq *rq)
466{
467 int err;
468
469 err = mlx5e_create_rq(c, param, rq);
470 if (err)
471 return err;
472
473 err = mlx5e_enable_rq(rq, param);
474 if (err)
475 goto err_destroy_rq;
476
477 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
478 if (err)
479 goto err_disable_rq;
480
481 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
12be4b21 482 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 483
484 return 0;
485
486err_disable_rq:
487 mlx5e_disable_rq(rq);
488err_destroy_rq:
489 mlx5e_destroy_rq(rq);
490
491 return err;
492}
493
494static void mlx5e_close_rq(struct mlx5e_rq *rq)
495{
496 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
497 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
498
499 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
500 while (!mlx5_wq_ll_is_empty(&rq->wq))
501 msleep(20);
502
503 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
504 napi_synchronize(&rq->channel->napi);
505
506 mlx5e_disable_rq(rq);
507 mlx5e_destroy_rq(rq);
508}
509
510static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
511{
34802a42 512 kfree(sq->wqe_info);
f62b8bb8
AV		 513 kfree(sq->dma_fifo);
514 kfree(sq->skb);
515}
516
517static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
518{
519 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
520 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
521
522 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
523 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
524 numa);
34802a42
AS		 525 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
526 numa);
f62b8bb8 527
34802a42 528 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 529 mlx5e_free_sq_db(sq);
530 return -ENOMEM;
531 }
532
533 sq->dma_fifo_mask = df_sz - 1;
534
535 return 0;
536}
537
538static int mlx5e_create_sq(struct mlx5e_channel *c,
539 int tc,
540 struct mlx5e_sq_param *param,
541 struct mlx5e_sq *sq)
542{
543 struct mlx5e_priv *priv = c->priv;
544 struct mlx5_core_dev *mdev = priv->mdev;
545
546 void *sqc = param->sqc;
547 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
03289b88 548 int txq_ix;
f62b8bb8
AV		 549 int err;
550
551 err = mlx5_alloc_map_uar(mdev, &sq->uar);
552 if (err)
553 return err;
554
311c7c71
SM		 555 param->wq.db_numa_node = cpu_to_node(c->cpu);
556
f62b8bb8
AV		 557 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
558 &sq->wq_ctrl);
559 if (err)
560 goto err_unmap_free_uar;
561
562 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
563 sq->uar_map = sq->uar.map;
88a85f99 564 sq->uar_bf_map = sq->uar.bf_map;
f62b8bb8 565 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 566 sq->max_inline = param->max_inline;
f62b8bb8 567
7ec0bb22
DC		 568 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
569 if (err)
f62b8bb8
AV		 570 goto err_sq_wq_destroy;
571
03289b88
SM		 572 txq_ix = c->ix + tc * priv->params.num_channels;
573 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
f62b8bb8 574
88a85f99 575 sq->pdev = c->pdev;
ef9814de 576 sq->tstamp = &priv->tstamp;
88a85f99
AS		 577 sq->mkey_be = c->mkey_be;
578 sq->channel = c;
579 sq->tc = tc;
580 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
581 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
03289b88 582 priv->txq_to_sq_map[txq_ix] = sq;
f62b8bb8
AV		 583
584 return 0;
585
586err_sq_wq_destroy:
587 mlx5_wq_destroy(&sq->wq_ctrl);
588
589err_unmap_free_uar:
590 mlx5_unmap_free_uar(mdev, &sq->uar);
591
592 return err;
593}
594
595static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
596{
597 struct mlx5e_channel *c = sq->channel;
598 struct mlx5e_priv *priv = c->priv;
599
600 mlx5e_free_sq_db(sq);
601 mlx5_wq_destroy(&sq->wq_ctrl);
602 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
603}
604
605static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
606{
607 struct mlx5e_channel *c = sq->channel;
608 struct mlx5e_priv *priv = c->priv;
609 struct mlx5_core_dev *mdev = priv->mdev;
610
611 void *in;
612 void *sqc;
613 void *wq;
614 int inlen;
615 int err;
616
617 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
618 sizeof(u64) * sq->wq_ctrl.buf.npages;
619 in = mlx5_vzalloc(inlen);
620 if (!in)
621 return -ENOMEM;
622
623 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
624 wq = MLX5_ADDR_OF(sqc, sqc, wq);
625
626 memcpy(sqc, param->sqc, sizeof(param->sqc));
627
f62b8bb8
AV		 628 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
629 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
630 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
631 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
632 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
633
634 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
635 MLX5_SET(wq, wq, uar_page, sq->uar.index);
636 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 637 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 638 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
639
640 mlx5_fill_page_array(&sq->wq_ctrl.buf,
641 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
642
7db22ffb 643 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 644
645 kvfree(in);
646
647 return err;
648}
649
650static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
651{
652 struct mlx5e_channel *c = sq->channel;
653 struct mlx5e_priv *priv = c->priv;
654 struct mlx5_core_dev *mdev = priv->mdev;
655
656 void *in;
657 void *sqc;
658 int inlen;
659 int err;
660
661 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
662 in = mlx5_vzalloc(inlen);
663 if (!in)
664 return -ENOMEM;
665
666 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
667
668 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
669 MLX5_SET(sqc, sqc, state, next_state);
670
7db22ffb 671 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 672
673 kvfree(in);
674
675 return err;
676}
677
678static void mlx5e_disable_sq(struct mlx5e_sq *sq)
679{
680 struct mlx5e_channel *c = sq->channel;
681 struct mlx5e_priv *priv = c->priv;
682 struct mlx5_core_dev *mdev = priv->mdev;
683
7db22ffb 684 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 685}
686
687static int mlx5e_open_sq(struct mlx5e_channel *c,
688 int tc,
689 struct mlx5e_sq_param *param,
690 struct mlx5e_sq *sq)
691{
692 int err;
693
694 err = mlx5e_create_sq(c, tc, param, sq);
695 if (err)
696 return err;
697
698 err = mlx5e_enable_sq(sq, param);
699 if (err)
700 goto err_destroy_sq;
701
702 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
703 if (err)
704 goto err_disable_sq;
705
706 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
707 netdev_tx_reset_queue(sq->txq);
708 netif_tx_start_queue(sq->txq);
709
710 return 0;
711
712err_disable_sq:
713 mlx5e_disable_sq(sq);
714err_destroy_sq:
715 mlx5e_destroy_sq(sq);
716
717 return err;
718}
719
720static inline void netif_tx_disable_queue(struct netdev_queue *txq)
721{
722 __netif_tx_lock_bh(txq);
723 netif_tx_stop_queue(txq);
724 __netif_tx_unlock_bh(txq);
725}
726
727static void mlx5e_close_sq(struct mlx5e_sq *sq)
728{
729 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
730 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
731 netif_tx_disable_queue(sq->txq);
732
733 /* ensure hw is notified of all pending wqes */
734 if (mlx5e_sq_has_room_for(sq, 1))
12be4b21 735 mlx5e_send_nop(sq, true);
f62b8bb8
AV		 736
737 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
738 while (sq->cc != sq->pc) /* wait till sq is empty */
739 msleep(20);
740
741 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
742 napi_synchronize(&sq->channel->napi);
743
744 mlx5e_disable_sq(sq);
745 mlx5e_destroy_sq(sq);
746}
747
748static int mlx5e_create_cq(struct mlx5e_channel *c,
749 struct mlx5e_cq_param *param,
750 struct mlx5e_cq *cq)
751{
752 struct mlx5e_priv *priv = c->priv;
753 struct mlx5_core_dev *mdev = priv->mdev;
754 struct mlx5_core_cq *mcq = &cq->mcq;
755 int eqn_not_used;
0b6e26ce 756 unsigned int irqn;
f62b8bb8
AV		 757 int err;
758 u32 i;
759
311c7c71
SM		 760 param->wq.buf_numa_node = cpu_to_node(c->cpu);
761 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 762 param->eq_ix = c->ix;
763
764 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
765 &cq->wq_ctrl);
766 if (err)
767 return err;
768
769 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
770
771 cq->napi = &c->napi;
772
773 mcq->cqe_sz = 64;
774 mcq->set_ci_db = cq->wq_ctrl.db.db;
775 mcq->arm_db = cq->wq_ctrl.db.db + 1;
776 *mcq->set_ci_db = 0;
777 *mcq->arm_db = 0;
778 mcq->vector = param->eq_ix;
779 mcq->comp = mlx5e_completion_event;
780 mcq->event = mlx5e_cq_error_event;
781 mcq->irqn = irqn;
782 mcq->uar = &priv->cq_uar;
783
784 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
785 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
786
787 cqe->op_own = 0xf1;
788 }
789
790 cq->channel = c;
50cfa25a 791 cq->priv = priv;
f62b8bb8
AV		 792
793 return 0;
794}
795
796static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
797{
798 mlx5_wq_destroy(&cq->wq_ctrl);
799}
800
801static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
802{
50cfa25a 803 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 804 struct mlx5_core_dev *mdev = priv->mdev;
805 struct mlx5_core_cq *mcq = &cq->mcq;
806
807 void *in;
808 void *cqc;
809 int inlen;
0b6e26ce 810 unsigned int irqn_not_used;
f62b8bb8
AV		 811 int eqn;
812 int err;
813
814 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
815 sizeof(u64) * cq->wq_ctrl.buf.npages;
816 in = mlx5_vzalloc(inlen);
817 if (!in)
818 return -ENOMEM;
819
820 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
821
822 memcpy(cqc, param->cqc, sizeof(param->cqc));
823
824 mlx5_fill_page_array(&cq->wq_ctrl.buf,
825 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
826
827 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
828
829 MLX5_SET(cqc, cqc, c_eqn, eqn);
830 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
831 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 832 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 833 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
834
835 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
836
837 kvfree(in);
838
839 if (err)
840 return err;
841
842 mlx5e_cq_arm(cq);
843
844 return 0;
845}
846
847static void mlx5e_disable_cq(struct mlx5e_cq *cq)
848{
50cfa25a 849 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 850 struct mlx5_core_dev *mdev = priv->mdev;
851
852 mlx5_core_destroy_cq(mdev, &cq->mcq);
853}
854
855static int mlx5e_open_cq(struct mlx5e_channel *c,
856 struct mlx5e_cq_param *param,
857 struct mlx5e_cq *cq,
858 u16 moderation_usecs,
859 u16 moderation_frames)
860{
861 int err;
862 struct mlx5e_priv *priv = c->priv;
863 struct mlx5_core_dev *mdev = priv->mdev;
864
865 err = mlx5e_create_cq(c, param, cq);
866 if (err)
867 return err;
868
869 err = mlx5e_enable_cq(cq, param);
870 if (err)
871 goto err_destroy_cq;
872
873 err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
874 moderation_usecs,
875 moderation_frames);
876 if (err)
877 goto err_destroy_cq;
878
879 return 0;
880
881err_destroy_cq:
882 mlx5e_destroy_cq(cq);
883
884 return err;
885}
886
887static void mlx5e_close_cq(struct mlx5e_cq *cq)
888{
889 mlx5e_disable_cq(cq);
890 mlx5e_destroy_cq(cq);
891}
892
893static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
894{
895 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
896}
897
898static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
899 struct mlx5e_channel_param *cparam)
900{
901 struct mlx5e_priv *priv = c->priv;
902 int err;
903 int tc;
904
905 for (tc = 0; tc < c->num_tc; tc++) {
906 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
907 priv->params.tx_cq_moderation_usec,
908 priv->params.tx_cq_moderation_pkts);
909 if (err)
910 goto err_close_tx_cqs;
f62b8bb8
AV		 911 }
912
913 return 0;
914
915err_close_tx_cqs:
916 for (tc--; tc >= 0; tc--)
917 mlx5e_close_cq(&c->sq[tc].cq);
918
919 return err;
920}
921
922static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
923{
924 int tc;
925
926 for (tc = 0; tc < c->num_tc; tc++)
927 mlx5e_close_cq(&c->sq[tc].cq);
928}
929
930static int mlx5e_open_sqs(struct mlx5e_channel *c,
931 struct mlx5e_channel_param *cparam)
932{
933 int err;
934 int tc;
935
936 for (tc = 0; tc < c->num_tc; tc++) {
937 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
938 if (err)
939 goto err_close_sqs;
940 }
941
942 return 0;
943
944err_close_sqs:
945 for (tc--; tc >= 0; tc--)
946 mlx5e_close_sq(&c->sq[tc]);
947
948 return err;
949}
950
951static void mlx5e_close_sqs(struct mlx5e_channel *c)
952{
953 int tc;
954
955 for (tc = 0; tc < c->num_tc; tc++)
956 mlx5e_close_sq(&c->sq[tc]);
957}
958
5283af89 959static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 960{
961 int i;
962
963 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
5283af89
RS		 964 priv->channeltc_to_txq_map[ix][i] =
965 ix + i * priv->params.num_channels;
03289b88
SM		 966}
967
f62b8bb8
AV		 968static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
969 struct mlx5e_channel_param *cparam,
970 struct mlx5e_channel **cp)
971{
972 struct net_device *netdev = priv->netdev;
973 int cpu = mlx5e_get_cpu(priv, ix);
974 struct mlx5e_channel *c;
975 int err;
976
977 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
978 if (!c)
979 return -ENOMEM;
980
981 c->priv = priv;
982 c->ix = ix;
983 c->cpu = cpu;
984 c->pdev = &priv->mdev->pdev->dev;
985 c->netdev = priv->netdev;
986 c->mkey_be = cpu_to_be32(priv->mr.key);
a4418a6c 987 c->num_tc = priv->params.num_tc;
f62b8bb8 988
5283af89 989 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 990
f62b8bb8
AV		 991 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
992
993 err = mlx5e_open_tx_cqs(c, cparam);
994 if (err)
995 goto err_napi_del;
996
997 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
998 priv->params.rx_cq_moderation_usec,
999 priv->params.rx_cq_moderation_pkts);
1000 if (err)
1001 goto err_close_tx_cqs;
f62b8bb8
AV		 1002
1003 napi_enable(&c->napi);
1004
1005 err = mlx5e_open_sqs(c, cparam);
1006 if (err)
1007 goto err_disable_napi;
1008
1009 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1010 if (err)
1011 goto err_close_sqs;
1012
1013 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1014 *cp = c;
1015
1016 return 0;
1017
1018err_close_sqs:
1019 mlx5e_close_sqs(c);
1020
1021err_disable_napi:
1022 napi_disable(&c->napi);
1023 mlx5e_close_cq(&c->rq.cq);
1024
1025err_close_tx_cqs:
1026 mlx5e_close_tx_cqs(c);
1027
1028err_napi_del:
1029 netif_napi_del(&c->napi);
7ae92ae5 1030 napi_hash_del(&c->napi);
f62b8bb8
AV		 1031 kfree(c);
1032
1033 return err;
1034}
1035
1036static void mlx5e_close_channel(struct mlx5e_channel *c)
1037{
1038 mlx5e_close_rq(&c->rq);
1039 mlx5e_close_sqs(c);
1040 napi_disable(&c->napi);
1041 mlx5e_close_cq(&c->rq.cq);
1042 mlx5e_close_tx_cqs(c);
1043 netif_napi_del(&c->napi);
7ae92ae5
ED		 1044
1045 napi_hash_del(&c->napi);
1046 synchronize_rcu();
1047
f62b8bb8
AV		 1048 kfree(c);
1049}
1050
1051static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1052 struct mlx5e_rq_param *param)
1053{
1054 void *rqc = param->rqc;
1055 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1056
1057 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1058 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1059 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1060 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1061 MLX5_SET(wq, wq, pd, priv->pdn);
1062
311c7c71 1063 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1064 param->wq.linear = 1;
1065}
1066
1067static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1068 struct mlx5e_sq_param *param)
1069{
1070 void *sqc = param->sqc;
1071 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1072
1073 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1074 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1075 MLX5_SET(wq, wq, pd, priv->pdn);
1076
311c7c71 1077 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
58d52291 1078 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1079}
1080
1081static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1082 struct mlx5e_cq_param *param)
1083{
1084 void *cqc = param->cqc;
1085
1086 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1087}
1088
1089static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1090 struct mlx5e_cq_param *param)
1091{
1092 void *cqc = param->cqc;
1093
1094 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1095
1096 mlx5e_build_common_cq_param(priv, param);
1097}
1098
1099static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1100 struct mlx5e_cq_param *param)
1101{
1102 void *cqc = param->cqc;
1103
1104 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1105
1106 mlx5e_build_common_cq_param(priv, param);
1107}
1108
1109static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1110 struct mlx5e_channel_param *cparam)
1111{
1112 memset(cparam, 0, sizeof(*cparam));
1113
1114 mlx5e_build_rq_param(priv, &cparam->rq);
1115 mlx5e_build_sq_param(priv, &cparam->sq);
1116 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1117 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1118}
1119
1120static int mlx5e_open_channels(struct mlx5e_priv *priv)
1121{
1122 struct mlx5e_channel_param cparam;
a4418a6c 1123 int nch = priv->params.num_channels;
03289b88 1124 int err = -ENOMEM;
f62b8bb8
AV		 1125 int i;
1126 int j;
1127
a4418a6c
AS		 1128 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1129 GFP_KERNEL);
03289b88 1130
a4418a6c 1131 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1132 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1133
1134 if (!priv->channel || !priv->txq_to_sq_map)
1135 goto err_free_txq_to_sq_map;
f62b8bb8
AV		 1136
1137 mlx5e_build_channel_param(priv, &cparam);
a4418a6c 1138 for (i = 0; i < nch; i++) {
f62b8bb8
AV		 1139 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1140 if (err)
1141 goto err_close_channels;
1142 }
1143
a4418a6c 1144 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1145 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1146 if (err)
1147 goto err_close_channels;
1148 }
1149
1150 return 0;
1151
1152err_close_channels:
1153 for (i--; i >= 0; i--)
1154 mlx5e_close_channel(priv->channel[i]);
1155
03289b88
SM		 1156err_free_txq_to_sq_map:
1157 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1158 kfree(priv->channel);
1159
1160 return err;
1161}
1162
1163static void mlx5e_close_channels(struct mlx5e_priv *priv)
1164{
1165 int i;
1166
1167 for (i = 0; i < priv->params.num_channels; i++)
1168 mlx5e_close_channel(priv->channel[i]);
1169
03289b88 1170 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1171 kfree(priv->channel);
1172}
1173
2be6967c
SM		 1174static int mlx5e_rx_hash_fn(int hfunc)
1175{
1176 return (hfunc == ETH_RSS_HASH_TOP) ?
1177 MLX5_RX_HASH_FN_TOEPLITZ :
1178 MLX5_RX_HASH_FN_INVERTED_XOR8;
1179}
1180
1181static int mlx5e_bits_invert(unsigned long a, int size)
1182{
1183 int inv = 0;
1184 int i;
1185
1186 for (i = 0; i < size; i++)
1187 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1188
1189 return inv;
1190}
1191
936896e9
AS		 1192static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1193{
1194 int i;
1195
1196 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1197 int ix = i;
1198
1199 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1200 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1201
2d75b2bc 1202 ix = priv->params.indirection_rqt[ix];
936896e9
AS		 1203 ix = ix % priv->params.num_channels;
1204 MLX5_SET(rqtc, rqtc, rq_num[i],
1205 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1206 priv->channel[ix]->rq.rqn :
1207 priv->drop_rq.rqn);
1208 }
1209}
1210
4cbeaff5
AS		 1211static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1212 enum mlx5e_rqt_ix rqt_ix)
1213{
4cbeaff5
AS		 1214
1215 switch (rqt_ix) {
1216 case MLX5E_INDIRECTION_RQT:
936896e9 1217 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
4cbeaff5
AS		 1218
1219 break;
1220
1221 default: /* MLX5E_SINGLE_RQ_RQT */
1222 MLX5_SET(rqtc, rqtc, rq_num[0],
5c50368f
AS		 1223 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1224 priv->channel[0]->rq.rqn :
1225 priv->drop_rq.rqn);
4cbeaff5
AS		 1226
1227 break;
1228 }
1229}
1230
40ab6a6e 1231static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8
AV		 1232{
1233 struct mlx5_core_dev *mdev = priv->mdev;
1234 u32 *in;
f62b8bb8
AV		 1235 void *rqtc;
1236 int inlen;
4cbeaff5 1237 int sz;
f62b8bb8 1238 int err;
4cbeaff5 1239
936896e9 1240 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
f62b8bb8 1241
f62b8bb8
AV		 1242 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1243 in = mlx5_vzalloc(inlen);
1244 if (!in)
1245 return -ENOMEM;
1246
1247 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1248
1249 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1250 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1251
4cbeaff5 1252 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
2be6967c 1253
4cbeaff5 1254 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1255
1256 kvfree(in);
1257
1258 return err;
1259}
1260
2d75b2bc 1261int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
5c50368f
AS		 1262{
1263 struct mlx5_core_dev *mdev = priv->mdev;
1264 u32 *in;
1265 void *rqtc;
1266 int inlen;
5c50368f
AS		 1267 int sz;
1268 int err;
1269
936896e9 1270 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
5c50368f
AS		 1271
1272 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1273 in = mlx5_vzalloc(inlen);
1274 if (!in)
1275 return -ENOMEM;
1276
1277 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1278
1279 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1280
1281 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1282
1283 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1284
1285 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1286
1287 kvfree(in);
1288
1289 return err;
1290}
1291
40ab6a6e 1292static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8 1293{
4cbeaff5 1294 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1295}
1296
40ab6a6e
AS		 1297static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1298{
1299 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1300 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1301}
1302
5c50368f
AS		 1303static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1304{
1305 if (!priv->params.lro_en)
1306 return;
1307
1308#define ROUGH_MAX_L2_L3_HDR_SZ 256
1309
1310 MLX5_SET(tirc, tirc, lro_enable_mask,
1311 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1312 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1313 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1314 (priv->params.lro_wqe_sz -
1315 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1316 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1317 MLX5_CAP_ETH(priv->mdev,
d9a40271 1318 lro_timer_supported_periods[2]));
5c50368f
AS		 1319}
1320
1321static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt)
1322{
1323 struct mlx5_core_dev *mdev = priv->mdev;
1324
1325 void *in;
1326 void *tirc;
1327 int inlen;
1328 int err;
1329
1330 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1331 in = mlx5_vzalloc(inlen);
1332 if (!in)
1333 return -ENOMEM;
1334
1335 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1336 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1337
1338 mlx5e_build_tir_ctx_lro(tirc, priv);
1339
1340 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1341
1342 kvfree(in);
1343
1344 return err;
1345}
1346
66189961
TT		 1347static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1348 u32 tirn)
1349{
1350 void *in;
1351 int inlen;
1352 int err;
1353
1354 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1355 in = mlx5_vzalloc(inlen);
1356 if (!in)
1357 return -ENOMEM;
1358
1359 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1360
1361 err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1362
1363 kvfree(in);
1364
1365 return err;
1366}
1367
1368static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1369{
1370 int err;
1371 int i;
1372
1373 for (i = 0; i < MLX5E_NUM_TT; i++) {
1374 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1375 priv->tirn[i]);
1376 if (err)
1377 return err;
1378 }
1379
1380 return 0;
1381}
1382
40ab6a6e
AS		 1383static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1384{
1385 struct mlx5e_priv *priv = netdev_priv(netdev);
1386 struct mlx5_core_dev *mdev = priv->mdev;
1387 int hw_mtu;
1388 int err;
1389
1390 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1391 if (err)
1392 return err;
1393
1394 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1395
1396 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1397 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1398 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1399
1400 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1401 return 0;
1402}
1403
08fb1dac
SM		 1404static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1405{
1406 struct mlx5e_priv *priv = netdev_priv(netdev);
1407 int nch = priv->params.num_channels;
1408 int ntc = priv->params.num_tc;
1409 int tc;
1410
1411 netdev_reset_tc(netdev);
1412
1413 if (ntc == 1)
1414 return;
1415
1416 netdev_set_num_tc(netdev, ntc);
1417
1418 for (tc = 0; tc < ntc; tc++)
1419 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1420}
1421
40ab6a6e
AS		 1422int mlx5e_open_locked(struct net_device *netdev)
1423{
1424 struct mlx5e_priv *priv = netdev_priv(netdev);
1425 int num_txqs;
1426 int err;
1427
1428 set_bit(MLX5E_STATE_OPENED, &priv->state);
1429
08fb1dac
SM		 1430 mlx5e_netdev_set_tcs(netdev);
1431
40ab6a6e
AS		 1432 num_txqs = priv->params.num_channels * priv->params.num_tc;
1433 netif_set_real_num_tx_queues(netdev, num_txqs);
1434 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1435
1436 err = mlx5e_set_dev_port_mtu(netdev);
1437 if (err)
343b29f3 1438 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1439
1440 err = mlx5e_open_channels(priv);
1441 if (err) {
1442 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1443 __func__, err);
343b29f3 1444 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1445 }
1446
66189961
TT		 1447 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1448 if (err) {
1449 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1450 __func__, err);
1451 goto err_close_channels;
1452 }
1453
40ab6a6e 1454 mlx5e_redirect_rqts(priv);
ce89ef36 1455 mlx5e_update_carrier(priv);
ef9814de 1456 mlx5e_timestamp_init(priv);
40ab6a6e
AS		 1457
1458 schedule_delayed_work(&priv->update_stats_work, 0);
40ab6a6e 1459
9b37b07f 1460 return 0;
343b29f3 1461
66189961
TT		 1462err_close_channels:
1463 mlx5e_close_channels(priv);
343b29f3
AS		 1464err_clear_state_opened_flag:
1465 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1466 return err;
40ab6a6e
AS		 1467}
1468
1469static int mlx5e_open(struct net_device *netdev)
1470{
1471 struct mlx5e_priv *priv = netdev_priv(netdev);
1472 int err;
1473
1474 mutex_lock(&priv->state_lock);
1475 err = mlx5e_open_locked(netdev);
1476 mutex_unlock(&priv->state_lock);
1477
1478 return err;
1479}
1480
1481int mlx5e_close_locked(struct net_device *netdev)
1482{
1483 struct mlx5e_priv *priv = netdev_priv(netdev);
1484
a1985740
AS		 1485 /* May already be CLOSED in case a previous configuration operation
1486 * (e.g RX/TX queue size change) that involves close&open failed.
1487 */
1488 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1489 return 0;
1490
40ab6a6e
AS		 1491 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1492
ef9814de 1493 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1494 netif_carrier_off(priv->netdev);
ce89ef36 1495 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1496 mlx5e_close_channels(priv);
1497
1498 return 0;
1499}
1500
1501static int mlx5e_close(struct net_device *netdev)
1502{
1503 struct mlx5e_priv *priv = netdev_priv(netdev);
1504 int err;
1505
1506 mutex_lock(&priv->state_lock);
1507 err = mlx5e_close_locked(netdev);
1508 mutex_unlock(&priv->state_lock);
1509
1510 return err;
1511}
1512
1513static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1514 struct mlx5e_rq *rq,
1515 struct mlx5e_rq_param *param)
1516{
1517 struct mlx5_core_dev *mdev = priv->mdev;
1518 void *rqc = param->rqc;
1519 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1520 int err;
1521
1522 param->wq.db_numa_node = param->wq.buf_numa_node;
1523
1524 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1525 &rq->wq_ctrl);
1526 if (err)
1527 return err;
1528
1529 rq->priv = priv;
1530
1531 return 0;
1532}
1533
1534static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1535 struct mlx5e_cq *cq,
1536 struct mlx5e_cq_param *param)
1537{
1538 struct mlx5_core_dev *mdev = priv->mdev;
1539 struct mlx5_core_cq *mcq = &cq->mcq;
1540 int eqn_not_used;
0b6e26ce 1541 unsigned int irqn;
40ab6a6e
AS		 1542 int err;
1543
1544 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1545 &cq->wq_ctrl);
1546 if (err)
1547 return err;
1548
1549 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1550
1551 mcq->cqe_sz = 64;
1552 mcq->set_ci_db = cq->wq_ctrl.db.db;
1553 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1554 *mcq->set_ci_db = 0;
1555 *mcq->arm_db = 0;
1556 mcq->vector = param->eq_ix;
1557 mcq->comp = mlx5e_completion_event;
1558 mcq->event = mlx5e_cq_error_event;
1559 mcq->irqn = irqn;
1560 mcq->uar = &priv->cq_uar;
1561
1562 cq->priv = priv;
1563
1564 return 0;
1565}
1566
1567static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1568{
1569 struct mlx5e_cq_param cq_param;
1570 struct mlx5e_rq_param rq_param;
1571 struct mlx5e_rq *rq = &priv->drop_rq;
1572 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1573 int err;
1574
1575 memset(&cq_param, 0, sizeof(cq_param));
1576 memset(&rq_param, 0, sizeof(rq_param));
1577 mlx5e_build_rx_cq_param(priv, &cq_param);
1578 mlx5e_build_rq_param(priv, &rq_param);
1579
1580 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1581 if (err)
1582 return err;
1583
1584 err = mlx5e_enable_cq(cq, &cq_param);
1585 if (err)
1586 goto err_destroy_cq;
1587
1588 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1589 if (err)
1590 goto err_disable_cq;
1591
1592 err = mlx5e_enable_rq(rq, &rq_param);
1593 if (err)
1594 goto err_destroy_rq;
1595
1596 return 0;
1597
1598err_destroy_rq:
1599 mlx5e_destroy_rq(&priv->drop_rq);
1600
1601err_disable_cq:
1602 mlx5e_disable_cq(&priv->drop_rq.cq);
1603
1604err_destroy_cq:
1605 mlx5e_destroy_cq(&priv->drop_rq.cq);
1606
1607 return err;
1608}
1609
1610static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1611{
1612 mlx5e_disable_rq(&priv->drop_rq);
1613 mlx5e_destroy_rq(&priv->drop_rq);
1614 mlx5e_disable_cq(&priv->drop_rq.cq);
1615 mlx5e_destroy_cq(&priv->drop_rq.cq);
1616}
1617
1618static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1619{
1620 struct mlx5_core_dev *mdev = priv->mdev;
1621 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1622 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1623
1624 memset(in, 0, sizeof(in));
1625
08fb1dac 1626 MLX5_SET(tisc, tisc, prio, tc << 1);
40ab6a6e
AS		 1627 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1628
1629 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1630}
1631
1632static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1633{
1634 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1635}
1636
1637static int mlx5e_create_tises(struct mlx5e_priv *priv)
1638{
1639 int err;
1640 int tc;
1641
08fb1dac 1642 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
40ab6a6e
AS		 1643 err = mlx5e_create_tis(priv, tc);
1644 if (err)
1645 goto err_close_tises;
1646 }
1647
1648 return 0;
1649
1650err_close_tises:
1651 for (tc--; tc >= 0; tc--)
1652 mlx5e_destroy_tis(priv, tc);
1653
1654 return err;
1655}
1656
1657static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1658{
1659 int tc;
1660
08fb1dac 1661 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
40ab6a6e
AS		 1662 mlx5e_destroy_tis(priv, tc);
1663}
1664
f62b8bb8
AV		 1665static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1666{
1667 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1668
3191e05f
AS		 1669 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1670
5a6f8aef
AS		 1671#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1672 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1673
5a6f8aef
AS		 1674#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1675 MLX5_HASH_FIELD_SEL_DST_IP |\
1676 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1677 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1678
a741749f
AS		 1679#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1680 MLX5_HASH_FIELD_SEL_DST_IP |\
1681 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1682
5c50368f 1683 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 1684
4cbeaff5
AS		 1685 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1686
f62b8bb8
AV		 1687 switch (tt) {
1688 case MLX5E_TT_ANY:
4cbeaff5
AS		 1689 MLX5_SET(tirc, tirc, indirect_table,
1690 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1691 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
f62b8bb8
AV		 1692 break;
1693 default:
f62b8bb8 1694 MLX5_SET(tirc, tirc, indirect_table,
4cbeaff5 1695 priv->rqtn[MLX5E_INDIRECTION_RQT]);
f62b8bb8 1696 MLX5_SET(tirc, tirc, rx_hash_fn,
2be6967c
SM		 1697 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1698 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1699 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1700 rx_hash_toeplitz_key);
1701 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1702 rx_hash_toeplitz_key);
1703
1704 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
57afead5 1705 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2be6967c 1706 }
f62b8bb8
AV		 1707 break;
1708 }
1709
1710 switch (tt) {
1711 case MLX5E_TT_IPV4_TCP:
1712 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1713 MLX5_L3_PROT_TYPE_IPV4);
1714 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1715 MLX5_L4_PROT_TYPE_TCP);
1716 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1717 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1718 break;
1719
1720 case MLX5E_TT_IPV6_TCP:
1721 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1722 MLX5_L3_PROT_TYPE_IPV6);
1723 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1724 MLX5_L4_PROT_TYPE_TCP);
1725 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1726 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1727 break;
1728
1729 case MLX5E_TT_IPV4_UDP:
1730 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1731 MLX5_L3_PROT_TYPE_IPV4);
1732 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1733 MLX5_L4_PROT_TYPE_UDP);
1734 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1735 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1736 break;
1737
1738 case MLX5E_TT_IPV6_UDP:
1739 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1740 MLX5_L3_PROT_TYPE_IPV6);
1741 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1742 MLX5_L4_PROT_TYPE_UDP);
1743 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1744 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1745 break;
1746
a741749f
AS		 1747 case MLX5E_TT_IPV4_IPSEC_AH:
1748 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1749 MLX5_L3_PROT_TYPE_IPV4);
1750 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1751 MLX5_HASH_IP_IPSEC_SPI);
1752 break;
1753
1754 case MLX5E_TT_IPV6_IPSEC_AH:
1755 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1756 MLX5_L3_PROT_TYPE_IPV6);
1757 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1758 MLX5_HASH_IP_IPSEC_SPI);
1759 break;
1760
1761 case MLX5E_TT_IPV4_IPSEC_ESP:
1762 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1763 MLX5_L3_PROT_TYPE_IPV4);
1764 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1765 MLX5_HASH_IP_IPSEC_SPI);
1766 break;
1767
1768 case MLX5E_TT_IPV6_IPSEC_ESP:
1769 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1770 MLX5_L3_PROT_TYPE_IPV6);
1771 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1772 MLX5_HASH_IP_IPSEC_SPI);
1773 break;
1774
f62b8bb8
AV		 1775 case MLX5E_TT_IPV4:
1776 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1777 MLX5_L3_PROT_TYPE_IPV4);
1778 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1779 MLX5_HASH_IP);
1780 break;
1781
1782 case MLX5E_TT_IPV6:
1783 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1784 MLX5_L3_PROT_TYPE_IPV6);
1785 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1786 MLX5_HASH_IP);
1787 break;
1788 }
1789}
1790
40ab6a6e 1791static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8
AV		 1792{
1793 struct mlx5_core_dev *mdev = priv->mdev;
1794 u32 *in;
1795 void *tirc;
1796 int inlen;
1797 int err;
1798
1799 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1800 in = mlx5_vzalloc(inlen);
1801 if (!in)
1802 return -ENOMEM;
1803
1804 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1805
1806 mlx5e_build_tir_ctx(priv, tirc, tt);
1807
7db22ffb 1808 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
f62b8bb8
AV		 1809
1810 kvfree(in);
1811
1812 return err;
1813}
1814
40ab6a6e 1815static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8 1816{
7db22ffb 1817 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
f62b8bb8
AV		 1818}
1819
40ab6a6e 1820static int mlx5e_create_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1821{
1822 int err;
1823 int i;
1824
1825 for (i = 0; i < MLX5E_NUM_TT; i++) {
40ab6a6e 1826 err = mlx5e_create_tir(priv, i);
f62b8bb8 1827 if (err)
40ab6a6e 1828 goto err_destroy_tirs;
f62b8bb8
AV		 1829 }
1830
1831 return 0;
1832
40ab6a6e 1833err_destroy_tirs:
f62b8bb8 1834 for (i--; i >= 0; i--)
40ab6a6e 1835 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1836
1837 return err;
1838}
1839
40ab6a6e 1840static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1841{
1842 int i;
1843
1844 for (i = 0; i < MLX5E_NUM_TT; i++)
40ab6a6e 1845 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1846}
1847
08fb1dac
SM		 1848static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1849{
1850 struct mlx5e_priv *priv = netdev_priv(netdev);
1851 bool was_opened;
1852 int err = 0;
1853
1854 if (tc && tc != MLX5E_MAX_NUM_TC)
1855 return -EINVAL;
1856
1857 mutex_lock(&priv->state_lock);
1858
1859 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1860 if (was_opened)
1861 mlx5e_close_locked(priv->netdev);
1862
1863 priv->params.num_tc = tc ? tc : 1;
1864
1865 if (was_opened)
1866 err = mlx5e_open_locked(priv->netdev);
1867
1868 mutex_unlock(&priv->state_lock);
1869
1870 return err;
1871}
1872
1873static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1874 __be16 proto, struct tc_to_netdev *tc)
1875{
1876 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
1877 return -EINVAL;
1878
1879 return mlx5e_setup_tc(dev, tc->tc);
1880}
1881
f62b8bb8
AV		 1882static struct rtnl_link_stats64 *
1883mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1884{
1885 struct mlx5e_priv *priv = netdev_priv(dev);
1886 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1887
1888 stats->rx_packets = vstats->rx_packets;
1889 stats->rx_bytes = vstats->rx_bytes;
1890 stats->tx_packets = vstats->tx_packets;
1891 stats->tx_bytes = vstats->tx_bytes;
1892 stats->multicast = vstats->rx_multicast_packets +
1893 vstats->tx_multicast_packets;
1894 stats->tx_errors = vstats->tx_error_packets;
1895 stats->rx_errors = vstats->rx_error_packets;
1896 stats->tx_dropped = vstats->tx_queue_dropped;
1897 stats->rx_crc_errors = 0;
1898 stats->rx_length_errors = 0;
1899
1900 return stats;
1901}
1902
1903static void mlx5e_set_rx_mode(struct net_device *dev)
1904{
1905 struct mlx5e_priv *priv = netdev_priv(dev);
1906
1907 schedule_work(&priv->set_rx_mode_work);
1908}
1909
1910static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1911{
1912 struct mlx5e_priv *priv = netdev_priv(netdev);
1913 struct sockaddr *saddr = addr;
1914
1915 if (!is_valid_ether_addr(saddr->sa_data))
1916 return -EADDRNOTAVAIL;
1917
1918 netif_addr_lock_bh(netdev);
1919 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1920 netif_addr_unlock_bh(netdev);
1921
1922 schedule_work(&priv->set_rx_mode_work);
1923
1924 return 0;
1925}
1926
1927static int mlx5e_set_features(struct net_device *netdev,
1928 netdev_features_t features)
1929{
1930 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 1931 int err = 0;
f62b8bb8 1932 netdev_features_t changes = features ^ netdev->features;
f62b8bb8
AV		 1933
1934 mutex_lock(&priv->state_lock);
f62b8bb8
AV		 1935
1936 if (changes & NETIF_F_LRO) {
98e81b0a
AS		 1937 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1938
1939 if (was_opened)
1940 mlx5e_close_locked(priv->netdev);
f62b8bb8 1941
98e81b0a 1942 priv->params.lro_en = !!(features & NETIF_F_LRO);
5c50368f
AS		 1943 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV4_TCP);
1944 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV6_TCP);
98e81b0a
AS		 1945
1946 if (was_opened)
1947 err = mlx5e_open_locked(priv->netdev);
1948 }
f62b8bb8 1949
9b37b07f
AS		 1950 mutex_unlock(&priv->state_lock);
1951
f62b8bb8
AV		 1952 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1953 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1954 mlx5e_enable_vlan_filter(priv);
1955 else
1956 mlx5e_disable_vlan_filter(priv);
1957 }
1958
fe9f4fe5 1959 return err;
f62b8bb8
AV		 1960}
1961
1962static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1963{
1964 struct mlx5e_priv *priv = netdev_priv(netdev);
1965 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 1966 bool was_opened;
f62b8bb8 1967 int max_mtu;
98e81b0a 1968 int err = 0;
f62b8bb8 1969
facc9699 1970 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 1971
50a9eea6
DT		 1972 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1973
facc9699
SM		 1974 if (new_mtu > max_mtu) {
1975 netdev_err(netdev,
1976 "%s: Bad MTU (%d) > (%d) Max\n",
1977 __func__, new_mtu, max_mtu);
f62b8bb8
AV		 1978 return -EINVAL;
1979 }
1980
1981 mutex_lock(&priv->state_lock);
98e81b0a
AS		 1982
1983 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1984 if (was_opened)
1985 mlx5e_close_locked(netdev);
1986
f62b8bb8 1987 netdev->mtu = new_mtu;
98e81b0a
AS		 1988
1989 if (was_opened)
1990 err = mlx5e_open_locked(netdev);
1991
f62b8bb8
AV		 1992 mutex_unlock(&priv->state_lock);
1993
1994 return err;
1995}
1996
ef9814de
EBE		 1997static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1998{
1999 switch (cmd) {
2000 case SIOCSHWTSTAMP:
2001 return mlx5e_hwstamp_set(dev, ifr);
2002 case SIOCGHWTSTAMP:
2003 return mlx5e_hwstamp_get(dev, ifr);
2004 default:
2005 return -EOPNOTSUPP;
2006 }
2007}
2008
66e49ded
SM		 2009static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2010{
2011 struct mlx5e_priv *priv = netdev_priv(dev);
2012 struct mlx5_core_dev *mdev = priv->mdev;
2013
2014 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2015}
2016
2017static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2018{
2019 struct mlx5e_priv *priv = netdev_priv(dev);
2020 struct mlx5_core_dev *mdev = priv->mdev;
2021
2022 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2023 vlan, qos);
2024}
2025
2026static int mlx5_vport_link2ifla(u8 esw_link)
2027{
2028 switch (esw_link) {
2029 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2030 return IFLA_VF_LINK_STATE_DISABLE;
2031 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2032 return IFLA_VF_LINK_STATE_ENABLE;
2033 }
2034 return IFLA_VF_LINK_STATE_AUTO;
2035}
2036
2037static int mlx5_ifla_link2vport(u8 ifla_link)
2038{
2039 switch (ifla_link) {
2040 case IFLA_VF_LINK_STATE_DISABLE:
2041 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2042 case IFLA_VF_LINK_STATE_ENABLE:
2043 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2044 }
2045 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2046}
2047
2048static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2049 int link_state)
2050{
2051 struct mlx5e_priv *priv = netdev_priv(dev);
2052 struct mlx5_core_dev *mdev = priv->mdev;
2053
2054 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2055 mlx5_ifla_link2vport(link_state));
2056}
2057
2058static int mlx5e_get_vf_config(struct net_device *dev,
2059 int vf, struct ifla_vf_info *ivi)
2060{
2061 struct mlx5e_priv *priv = netdev_priv(dev);
2062 struct mlx5_core_dev *mdev = priv->mdev;
2063 int err;
2064
2065 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2066 if (err)
2067 return err;
2068 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2069 return 0;
2070}
2071
2072static int mlx5e_get_vf_stats(struct net_device *dev,
2073 int vf, struct ifla_vf_stats *vf_stats)
2074{
2075 struct mlx5e_priv *priv = netdev_priv(dev);
2076 struct mlx5_core_dev *mdev = priv->mdev;
2077
2078 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2079 vf_stats);
2080}
2081
b3f63c3d
MF		 2082static void mlx5e_add_vxlan_port(struct net_device *netdev,
2083 sa_family_t sa_family, __be16 port)
2084{
2085 struct mlx5e_priv *priv = netdev_priv(netdev);
2086
2087 if (!mlx5e_vxlan_allowed(priv->mdev))
2088 return;
2089
2090 mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2091}
2092
2093static void mlx5e_del_vxlan_port(struct net_device *netdev,
2094 sa_family_t sa_family, __be16 port)
2095{
2096 struct mlx5e_priv *priv = netdev_priv(netdev);
2097
2098 if (!mlx5e_vxlan_allowed(priv->mdev))
2099 return;
2100
2101 mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2102}
2103
2104static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2105 struct sk_buff *skb,
2106 netdev_features_t features)
2107{
2108 struct udphdr *udph;
2109 u16 proto;
2110 u16 port = 0;
2111
2112 switch (vlan_get_protocol(skb)) {
2113 case htons(ETH_P_IP):
2114 proto = ip_hdr(skb)->protocol;
2115 break;
2116 case htons(ETH_P_IPV6):
2117 proto = ipv6_hdr(skb)->nexthdr;
2118 break;
2119 default:
2120 goto out;
2121 }
2122
2123 if (proto == IPPROTO_UDP) {
2124 udph = udp_hdr(skb);
2125 port = be16_to_cpu(udph->dest);
2126 }
2127
2128 /* Verify if UDP port is being offloaded by HW */
2129 if (port && mlx5e_vxlan_lookup_port(priv, port))
2130 return features;
2131
2132out:
2133 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2134 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2135}
2136
2137static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2138 struct net_device *netdev,
2139 netdev_features_t features)
2140{
2141 struct mlx5e_priv *priv = netdev_priv(netdev);
2142
2143 features = vlan_features_check(skb, features);
2144 features = vxlan_features_check(skb, features);
2145
2146 /* Validate if the tunneled packet is being offloaded by HW */
2147 if (skb->encapsulation &&
2148 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2149 return mlx5e_vxlan_features_check(priv, skb, features);
2150
2151 return features;
2152}
2153
b0eed40e 2154static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2155 .ndo_open = mlx5e_open,
2156 .ndo_stop = mlx5e_close,
2157 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2158 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2159 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2160 .ndo_get_stats64 = mlx5e_get_stats,
2161 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2162 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2163 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2164 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2165 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2166 .ndo_change_mtu = mlx5e_change_mtu,
2167 .ndo_do_ioctl = mlx5e_ioctl,
2168};
2169
2170static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2171 .ndo_open = mlx5e_open,
2172 .ndo_stop = mlx5e_close,
2173 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2174 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2175 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2176 .ndo_get_stats64 = mlx5e_get_stats,
2177 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2178 .ndo_set_mac_address = mlx5e_set_mac,
2179 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2180 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2181 .ndo_set_features = mlx5e_set_features,
2182 .ndo_change_mtu = mlx5e_change_mtu,
2183 .ndo_do_ioctl = mlx5e_ioctl,
b3f63c3d
MF		 2184 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2185 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2186 .ndo_features_check = mlx5e_features_check,
b0eed40e
SM		 2187 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2188 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2189 .ndo_get_vf_config = mlx5e_get_vf_config,
2190 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2191 .ndo_get_vf_stats = mlx5e_get_vf_stats,
f62b8bb8
AV		 2192};
2193
2194static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2195{
2196 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2197 return -ENOTSUPP;
2198 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2199 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2200 !MLX5_CAP_ETH(mdev, csum_cap) ||
2201 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2202 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2203 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2204 MLX5_CAP_FLOWTABLE(mdev,
2205 flow_table_properties_nic_receive.max_ft_level)
2206 < 3) {
f62b8bb8
AV		 2207 mlx5_core_warn(mdev,
2208 "Not creating net device, some required device capabilities are missing\n");
2209 return -ENOTSUPP;
2210 }
66189961
TT		 2211 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2212 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2213
f62b8bb8
AV		 2214 return 0;
2215}
2216
58d52291
AS		 2217u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2218{
2219 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2220
2221 return bf_buf_size -
2222 sizeof(struct mlx5e_tx_wqe) +
2223 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2224}
2225
08fb1dac
SM		 2226#ifdef CONFIG_MLX5_CORE_EN_DCB
2227static void mlx5e_ets_init(struct mlx5e_priv *priv)
2228{
2229 int i;
2230
2231 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2232 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2233 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2234 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2235 priv->params.ets.prio_tc[i] = i;
2236 }
2237
2238 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2239 priv->params.ets.prio_tc[0] = 1;
2240 priv->params.ets.prio_tc[1] = 0;
2241}
2242#endif
2243
f62b8bb8
AV		 2244static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2245 struct net_device *netdev,
936896e9 2246 int num_channels)
f62b8bb8
AV		 2247{
2248 struct mlx5e_priv *priv = netdev_priv(netdev);
2d75b2bc 2249 int i;
f62b8bb8
AV		 2250
2251 priv->params.log_sq_size =
2252 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2253 priv->params.log_rq_size =
2254 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2255 priv->params.rx_cq_moderation_usec =
2256 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2257 priv->params.rx_cq_moderation_pkts =
2258 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2259 priv->params.tx_cq_moderation_usec =
2260 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2261 priv->params.tx_cq_moderation_pkts =
2262 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2263 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8
AV		 2264 priv->params.min_rx_wqes =
2265 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
f62b8bb8 2266 priv->params.num_tc = 1;
2be6967c 2267 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2268
57afead5
AS		 2269 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2270 sizeof(priv->params.toeplitz_hash_key));
2271
2d75b2bc
AS		 2272 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++)
2273 priv->params.indirection_rqt[i] = i % num_channels;
2274
f62b8bb8
AV		 2275 priv->params.lro_wqe_sz =
2276 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2277
2278 priv->mdev = mdev;
2279 priv->netdev = netdev;
936896e9 2280 priv->params.num_channels = num_channels;
08fb1dac
SM		 2281
2282#ifdef CONFIG_MLX5_CORE_EN_DCB
2283 mlx5e_ets_init(priv);
2284#endif
f62b8bb8 2285
f62b8bb8
AV		 2286 mutex_init(&priv->state_lock);
2287
2288 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2289 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2290 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2291}
2292
2293static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2294{
2295 struct mlx5e_priv *priv = netdev_priv(netdev);
2296
e1d7d349 2297 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2298 if (is_zero_ether_addr(netdev->dev_addr) &&
2299 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2300 eth_hw_addr_random(netdev);
2301 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2302 }
f62b8bb8
AV		 2303}
2304
2305static void mlx5e_build_netdev(struct net_device *netdev)
2306{
2307 struct mlx5e_priv *priv = netdev_priv(netdev);
2308 struct mlx5_core_dev *mdev = priv->mdev;
2309
2310 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2311
08fb1dac 2312 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 2313 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 2314#ifdef CONFIG_MLX5_CORE_EN_DCB
2315 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2316#endif
2317 } else {
b0eed40e 2318 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 2319 }
66e49ded 2320
f62b8bb8
AV		 2321 netdev->watchdog_timeo = 15 * HZ;
2322
2323 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2324
12be4b21 2325 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 2326 netdev->vlan_features |= NETIF_F_IP_CSUM;
2327 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2328 netdev->vlan_features |= NETIF_F_GRO;
2329 netdev->vlan_features |= NETIF_F_TSO;
2330 netdev->vlan_features |= NETIF_F_TSO6;
2331 netdev->vlan_features |= NETIF_F_RXCSUM;
2332 netdev->vlan_features |= NETIF_F_RXHASH;
2333
2334 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2335 netdev->vlan_features |= NETIF_F_LRO;
2336
2337 netdev->hw_features = netdev->vlan_features;
e4cf27bd 2338 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 2339 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2340 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2341
b3f63c3d
MF		 2342 if (mlx5e_vxlan_allowed(mdev)) {
2343 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2344 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2345 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2346 netdev->hw_enc_features |= NETIF_F_TSO;
2347 netdev->hw_enc_features |= NETIF_F_TSO6;
2348 netdev->hw_enc_features |= NETIF_F_RXHASH;
2349 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2350 }
2351
f62b8bb8
AV		 2352 netdev->features = netdev->hw_features;
2353 if (!priv->params.lro_en)
2354 netdev->features &= ~NETIF_F_LRO;
2355
2356 netdev->features |= NETIF_F_HIGHDMA;
2357
2358 netdev->priv_flags |= IFF_UNICAST_FLT;
2359
2360 mlx5e_set_netdev_dev_addr(netdev);
2361}
2362
2363static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2364 struct mlx5_core_mr *mr)
2365{
2366 struct mlx5_core_dev *mdev = priv->mdev;
2367 struct mlx5_create_mkey_mbox_in *in;
2368 int err;
2369
2370 in = mlx5_vzalloc(sizeof(*in));
2371 if (!in)
2372 return -ENOMEM;
2373
2374 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2375 MLX5_PERM_LOCAL_READ |
2376 MLX5_ACCESS_MODE_PA;
2377 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2378 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2379
2380 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2381 NULL);
2382
2383 kvfree(in);
2384
2385 return err;
2386}
2387
2388static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2389{
2390 struct net_device *netdev;
2391 struct mlx5e_priv *priv;
3435ab59 2392 int nch = mlx5e_get_max_num_channels(mdev);
f62b8bb8
AV		 2393 int err;
2394
2395 if (mlx5e_check_required_hca_cap(mdev))
2396 return NULL;
2397
08fb1dac
SM		 2398 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2399 nch * MLX5E_MAX_NUM_TC,
2400 nch);
f62b8bb8
AV		 2401 if (!netdev) {
2402 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2403 return NULL;
2404 }
2405
936896e9 2406 mlx5e_build_netdev_priv(mdev, netdev, nch);
f62b8bb8
AV		 2407 mlx5e_build_netdev(netdev);
2408
2409 netif_carrier_off(netdev);
2410
2411 priv = netdev_priv(netdev);
2412
2413 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2414 if (err) {
1f2a3003 2415 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
f62b8bb8
AV		 2416 goto err_free_netdev;
2417 }
2418
2419 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2420 if (err) {
1f2a3003 2421 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 2422 goto err_unmap_free_uar;
2423 }
2424
8d7f9ecb 2425 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3191e05f 2426 if (err) {
1f2a3003 2427 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 2428 goto err_dealloc_pd;
2429 }
2430
f62b8bb8
AV		 2431 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2432 if (err) {
1f2a3003 2433 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 2434 goto err_dealloc_transport_domain;
f62b8bb8
AV		 2435 }
2436
40ab6a6e 2437 err = mlx5e_create_tises(priv);
5c50368f 2438 if (err) {
40ab6a6e 2439 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
5c50368f
AS		 2440 goto err_destroy_mkey;
2441 }
2442
2443 err = mlx5e_open_drop_rq(priv);
2444 if (err) {
2445 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 2446 goto err_destroy_tises;
5c50368f
AS		 2447 }
2448
40ab6a6e 2449 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2450 if (err) {
40ab6a6e 2451 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
5c50368f
AS		 2452 goto err_close_drop_rq;
2453 }
2454
40ab6a6e 2455 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2456 if (err) {
40ab6a6e
AS		 2457 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2458 goto err_destroy_rqt_indir;
5c50368f
AS		 2459 }
2460
40ab6a6e 2461 err = mlx5e_create_tirs(priv);
5c50368f 2462 if (err) {
40ab6a6e
AS		 2463 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2464 goto err_destroy_rqt_single;
5c50368f
AS		 2465 }
2466
40ab6a6e 2467 err = mlx5e_create_flow_tables(priv);
5c50368f 2468 if (err) {
40ab6a6e
AS		 2469 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2470 goto err_destroy_tirs;
5c50368f
AS		 2471 }
2472
2473 mlx5e_init_eth_addr(priv);
2474
b3f63c3d
MF		 2475 mlx5e_vxlan_init(priv);
2476
08fb1dac
SM		 2477#ifdef CONFIG_MLX5_CORE_EN_DCB
2478 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2479#endif
2480
f62b8bb8
AV		 2481 err = register_netdev(netdev);
2482 if (err) {
1f2a3003 2483 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
40ab6a6e 2484 goto err_destroy_flow_tables;
f62b8bb8
AV		 2485 }
2486
b3f63c3d
MF		 2487 if (mlx5e_vxlan_allowed(mdev))
2488 vxlan_get_rx_port(netdev);
2489
f62b8bb8 2490 mlx5e_enable_async_events(priv);
9b37b07f 2491 schedule_work(&priv->set_rx_mode_work);
f62b8bb8
AV		 2492
2493 return priv;
2494
40ab6a6e
AS		 2495err_destroy_flow_tables:
2496 mlx5e_destroy_flow_tables(priv);
5c50368f 2497
40ab6a6e
AS		 2498err_destroy_tirs:
2499 mlx5e_destroy_tirs(priv);
5c50368f 2500
40ab6a6e
AS		 2501err_destroy_rqt_single:
2502 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2503
40ab6a6e
AS		 2504err_destroy_rqt_indir:
2505 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f
AS		 2506
2507err_close_drop_rq:
2508 mlx5e_close_drop_rq(priv);
2509
40ab6a6e
AS		 2510err_destroy_tises:
2511 mlx5e_destroy_tises(priv);
5c50368f 2512
f62b8bb8
AV		 2513err_destroy_mkey:
2514 mlx5_core_destroy_mkey(mdev, &priv->mr);
2515
3191e05f 2516err_dealloc_transport_domain:
8d7f9ecb 2517 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3191e05f 2518
f62b8bb8
AV		 2519err_dealloc_pd:
2520 mlx5_core_dealloc_pd(mdev, priv->pdn);
2521
2522err_unmap_free_uar:
2523 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2524
2525err_free_netdev:
2526 free_netdev(netdev);
2527
2528 return NULL;
2529}
2530
2531static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2532{
2533 struct mlx5e_priv *priv = vpriv;
2534 struct net_device *netdev = priv->netdev;
2535
9b37b07f
AS		 2536 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2537
2538 schedule_work(&priv->set_rx_mode_work);
1cefa326
AS		 2539 mlx5e_disable_async_events(priv);
2540 flush_scheduled_work();
f62b8bb8 2541 unregister_netdev(netdev);
b3f63c3d 2542 mlx5e_vxlan_cleanup(priv);
40ab6a6e
AS		 2543 mlx5e_destroy_flow_tables(priv);
2544 mlx5e_destroy_tirs(priv);
2545 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2546 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2547 mlx5e_close_drop_rq(priv);
40ab6a6e 2548 mlx5e_destroy_tises(priv);
f62b8bb8 2549 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
8d7f9ecb 2550 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 2551 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2552 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
f62b8bb8
AV		 2553 free_netdev(netdev);
2554}
2555
2556static void *mlx5e_get_netdev(void *vpriv)
2557{
2558 struct mlx5e_priv *priv = vpriv;
2559
2560 return priv->netdev;
2561}
2562
2563static struct mlx5_interface mlx5e_interface = {
2564 .add = mlx5e_create_netdev,
2565 .remove = mlx5e_destroy_netdev,
2566 .event = mlx5e_async_event,
2567 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2568 .get_dev = mlx5e_get_netdev,
2569};
2570
2571void mlx5e_init(void)
2572{
2573 mlx5_register_interface(&mlx5e_interface);
2574}
2575
2576void mlx5e_cleanup(void)
2577{
2578 mlx5_unregister_interface(&mlx5e_interface);
2579}
Linux 6.x block layer and io_uring tree(s)