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f62b8bb8 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/if_vlan.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/mlx5/driver.h> | |
36 | #include <linux/mlx5/qp.h> | |
37 | #include <linux/mlx5/cq.h> | |
d18a9470 | 38 | #include <linux/mlx5/vport.h> |
f62b8bb8 AV |
39 | #include "wq.h" |
40 | #include "transobj.h" | |
41 | #include "mlx5_core.h" | |
42 | ||
43 | #define MLX5E_MAX_NUM_TC 8 | |
44 | ||
e842b100 | 45 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
46 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
47 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
48 | ||
e842b100 | 49 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
50 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
51 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
52 | ||
53 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (16 * 1024) | |
54 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 | |
55 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 | |
56 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
57 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
58 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
f62b8bb8 | 59 | |
936896e9 AS |
60 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
61 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
62 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
f62b8bb8 AV |
63 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
64 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 65 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 AV |
66 | |
67 | static const char vport_strings[][ETH_GSTRING_LEN] = { | |
68 | /* vport statistics */ | |
69 | "rx_packets", | |
70 | "rx_bytes", | |
71 | "tx_packets", | |
72 | "tx_bytes", | |
73 | "rx_error_packets", | |
74 | "rx_error_bytes", | |
75 | "tx_error_packets", | |
76 | "tx_error_bytes", | |
77 | "rx_unicast_packets", | |
78 | "rx_unicast_bytes", | |
79 | "tx_unicast_packets", | |
80 | "tx_unicast_bytes", | |
81 | "rx_multicast_packets", | |
82 | "rx_multicast_bytes", | |
83 | "tx_multicast_packets", | |
84 | "tx_multicast_bytes", | |
85 | "rx_broadcast_packets", | |
86 | "rx_broadcast_bytes", | |
87 | "tx_broadcast_packets", | |
88 | "tx_broadcast_bytes", | |
89 | ||
90 | /* SW counters */ | |
91 | "tso_packets", | |
92 | "tso_bytes", | |
93 | "lro_packets", | |
94 | "lro_bytes", | |
95 | "rx_csum_good", | |
96 | "rx_csum_none", | |
97 | "tx_csum_offload", | |
98 | "tx_queue_stopped", | |
99 | "tx_queue_wake", | |
100 | "tx_queue_dropped", | |
101 | "rx_wqe_err", | |
102 | }; | |
103 | ||
104 | struct mlx5e_vport_stats { | |
105 | /* HW counters */ | |
106 | u64 rx_packets; | |
107 | u64 rx_bytes; | |
108 | u64 tx_packets; | |
109 | u64 tx_bytes; | |
110 | u64 rx_error_packets; | |
111 | u64 rx_error_bytes; | |
112 | u64 tx_error_packets; | |
113 | u64 tx_error_bytes; | |
114 | u64 rx_unicast_packets; | |
115 | u64 rx_unicast_bytes; | |
116 | u64 tx_unicast_packets; | |
117 | u64 tx_unicast_bytes; | |
118 | u64 rx_multicast_packets; | |
119 | u64 rx_multicast_bytes; | |
120 | u64 tx_multicast_packets; | |
121 | u64 tx_multicast_bytes; | |
122 | u64 rx_broadcast_packets; | |
123 | u64 rx_broadcast_bytes; | |
124 | u64 tx_broadcast_packets; | |
125 | u64 tx_broadcast_bytes; | |
126 | ||
127 | /* SW counters */ | |
128 | u64 tso_packets; | |
129 | u64 tso_bytes; | |
130 | u64 lro_packets; | |
131 | u64 lro_bytes; | |
132 | u64 rx_csum_good; | |
133 | u64 rx_csum_none; | |
134 | u64 tx_csum_offload; | |
135 | u64 tx_queue_stopped; | |
136 | u64 tx_queue_wake; | |
137 | u64 tx_queue_dropped; | |
138 | u64 rx_wqe_err; | |
139 | ||
140 | #define NUM_VPORT_COUNTERS 31 | |
141 | }; | |
142 | ||
efea389d GP |
143 | static const char pport_strings[][ETH_GSTRING_LEN] = { |
144 | /* IEEE802.3 counters */ | |
145 | "frames_tx", | |
146 | "frames_rx", | |
147 | "check_seq_err", | |
148 | "alignment_err", | |
149 | "octets_tx", | |
150 | "octets_received", | |
151 | "multicast_xmitted", | |
152 | "broadcast_xmitted", | |
153 | "multicast_rx", | |
154 | "broadcast_rx", | |
155 | "in_range_len_errors", | |
156 | "out_of_range_len", | |
157 | "too_long_errors", | |
158 | "symbol_err", | |
159 | "mac_control_tx", | |
160 | "mac_control_rx", | |
161 | "unsupported_op_rx", | |
162 | "pause_ctrl_rx", | |
163 | "pause_ctrl_tx", | |
164 | ||
165 | /* RFC2863 counters */ | |
166 | "in_octets", | |
167 | "in_ucast_pkts", | |
168 | "in_discards", | |
169 | "in_errors", | |
170 | "in_unknown_protos", | |
171 | "out_octets", | |
172 | "out_ucast_pkts", | |
173 | "out_discards", | |
174 | "out_errors", | |
175 | "in_multicast_pkts", | |
176 | "in_broadcast_pkts", | |
177 | "out_multicast_pkts", | |
178 | "out_broadcast_pkts", | |
179 | ||
180 | /* RFC2819 counters */ | |
181 | "drop_events", | |
182 | "octets", | |
183 | "pkts", | |
184 | "broadcast_pkts", | |
185 | "multicast_pkts", | |
186 | "crc_align_errors", | |
187 | "undersize_pkts", | |
188 | "oversize_pkts", | |
189 | "fragments", | |
190 | "jabbers", | |
191 | "collisions", | |
192 | "p64octets", | |
193 | "p65to127octets", | |
194 | "p128to255octets", | |
195 | "p256to511octets", | |
196 | "p512to1023octets", | |
197 | "p1024to1518octets", | |
198 | "p1519to2047octets", | |
199 | "p2048to4095octets", | |
200 | "p4096to8191octets", | |
201 | "p8192to10239octets", | |
202 | }; | |
203 | ||
204 | #define NUM_IEEE_802_3_COUNTERS 19 | |
205 | #define NUM_RFC_2863_COUNTERS 13 | |
206 | #define NUM_RFC_2819_COUNTERS 21 | |
207 | #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \ | |
208 | NUM_RFC_2863_COUNTERS + \ | |
209 | NUM_RFC_2819_COUNTERS) | |
210 | ||
211 | struct mlx5e_pport_stats { | |
212 | __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS]; | |
213 | __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS]; | |
214 | __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS]; | |
215 | }; | |
216 | ||
f62b8bb8 AV |
217 | static const char rq_stats_strings[][ETH_GSTRING_LEN] = { |
218 | "packets", | |
219 | "csum_none", | |
220 | "lro_packets", | |
221 | "lro_bytes", | |
222 | "wqe_err" | |
223 | }; | |
224 | ||
225 | struct mlx5e_rq_stats { | |
226 | u64 packets; | |
227 | u64 csum_none; | |
228 | u64 lro_packets; | |
229 | u64 lro_bytes; | |
230 | u64 wqe_err; | |
231 | #define NUM_RQ_STATS 5 | |
232 | }; | |
233 | ||
234 | static const char sq_stats_strings[][ETH_GSTRING_LEN] = { | |
235 | "packets", | |
236 | "tso_packets", | |
237 | "tso_bytes", | |
238 | "csum_offload_none", | |
239 | "stopped", | |
240 | "wake", | |
241 | "dropped", | |
242 | "nop" | |
243 | }; | |
244 | ||
245 | struct mlx5e_sq_stats { | |
246 | u64 packets; | |
247 | u64 tso_packets; | |
248 | u64 tso_bytes; | |
249 | u64 csum_offload_none; | |
250 | u64 stopped; | |
251 | u64 wake; | |
252 | u64 dropped; | |
253 | u64 nop; | |
254 | #define NUM_SQ_STATS 8 | |
255 | }; | |
256 | ||
257 | struct mlx5e_stats { | |
258 | struct mlx5e_vport_stats vport; | |
efea389d | 259 | struct mlx5e_pport_stats pport; |
f62b8bb8 AV |
260 | }; |
261 | ||
262 | struct mlx5e_params { | |
263 | u8 log_sq_size; | |
264 | u8 log_rq_size; | |
265 | u16 num_channels; | |
266 | u8 default_vlan_prio; | |
267 | u8 num_tc; | |
268 | u16 rx_cq_moderation_usec; | |
269 | u16 rx_cq_moderation_pkts; | |
270 | u16 tx_cq_moderation_usec; | |
271 | u16 tx_cq_moderation_pkts; | |
272 | u16 min_rx_wqes; | |
f62b8bb8 AV |
273 | bool lro_en; |
274 | u32 lro_wqe_sz; | |
58d52291 | 275 | u16 tx_max_inline; |
2d75b2bc AS |
276 | u8 rss_hfunc; |
277 | u8 toeplitz_hash_key[40]; | |
278 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
f62b8bb8 AV |
279 | }; |
280 | ||
281 | enum { | |
282 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
283 | }; | |
284 | ||
285 | enum cq_flags { | |
286 | MLX5E_CQ_HAS_CQES = 1, | |
287 | }; | |
288 | ||
289 | struct mlx5e_cq { | |
290 | /* data path - accessed per cqe */ | |
291 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
292 | unsigned long flags; |
293 | ||
294 | /* data path - accessed per napi poll */ | |
295 | struct napi_struct *napi; | |
296 | struct mlx5_core_cq mcq; | |
297 | struct mlx5e_channel *channel; | |
50cfa25a | 298 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
299 | |
300 | /* control */ | |
301 | struct mlx5_wq_ctrl wq_ctrl; | |
302 | } ____cacheline_aligned_in_smp; | |
303 | ||
304 | struct mlx5e_rq { | |
305 | /* data path */ | |
306 | struct mlx5_wq_ll wq; | |
307 | u32 wqe_sz; | |
308 | struct sk_buff **skb; | |
309 | ||
310 | struct device *pdev; | |
311 | struct net_device *netdev; | |
312 | struct mlx5e_rq_stats stats; | |
313 | struct mlx5e_cq cq; | |
314 | ||
315 | unsigned long state; | |
316 | int ix; | |
317 | ||
318 | /* control */ | |
319 | struct mlx5_wq_ctrl wq_ctrl; | |
320 | u32 rqn; | |
321 | struct mlx5e_channel *channel; | |
50cfa25a | 322 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
323 | } ____cacheline_aligned_in_smp; |
324 | ||
325 | struct mlx5e_tx_skb_cb { | |
326 | u32 num_bytes; | |
327 | u8 num_wqebbs; | |
328 | u8 num_dma; | |
329 | }; | |
330 | ||
331 | #define MLX5E_TX_SKB_CB(__skb) ((struct mlx5e_tx_skb_cb *)__skb->cb) | |
332 | ||
333 | struct mlx5e_sq_dma { | |
334 | dma_addr_t addr; | |
335 | u32 size; | |
336 | }; | |
337 | ||
338 | enum { | |
339 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
340 | }; | |
341 | ||
342 | struct mlx5e_sq { | |
343 | /* data path */ | |
344 | ||
345 | /* dirtied @completion */ | |
346 | u16 cc; | |
347 | u32 dma_fifo_cc; | |
348 | ||
349 | /* dirtied @xmit */ | |
350 | u16 pc ____cacheline_aligned_in_smp; | |
351 | u32 dma_fifo_pc; | |
88a85f99 AS |
352 | u16 bf_offset; |
353 | u16 prev_cc; | |
354 | u8 bf_budget; | |
f62b8bb8 AV |
355 | struct mlx5e_sq_stats stats; |
356 | ||
357 | struct mlx5e_cq cq; | |
358 | ||
359 | /* pointers to per packet info: write@xmit, read@completion */ | |
360 | struct sk_buff **skb; | |
361 | struct mlx5e_sq_dma *dma_fifo; | |
362 | ||
363 | /* read only */ | |
364 | struct mlx5_wq_cyc wq; | |
365 | u32 dma_fifo_mask; | |
366 | void __iomem *uar_map; | |
88a85f99 | 367 | void __iomem *uar_bf_map; |
f62b8bb8 AV |
368 | struct netdev_queue *txq; |
369 | u32 sqn; | |
88a85f99 | 370 | u16 bf_buf_size; |
12be4b21 SM |
371 | u16 max_inline; |
372 | u16 edge; | |
f62b8bb8 AV |
373 | struct device *pdev; |
374 | __be32 mkey_be; | |
375 | unsigned long state; | |
376 | ||
377 | /* control path */ | |
378 | struct mlx5_wq_ctrl wq_ctrl; | |
379 | struct mlx5_uar uar; | |
380 | struct mlx5e_channel *channel; | |
381 | int tc; | |
382 | } ____cacheline_aligned_in_smp; | |
383 | ||
384 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
385 | { | |
386 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
387 | (sq->cc == sq->pc)); | |
388 | } | |
389 | ||
390 | enum channel_flags { | |
391 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
392 | }; | |
393 | ||
394 | struct mlx5e_channel { | |
395 | /* data path */ | |
396 | struct mlx5e_rq rq; | |
397 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
398 | struct napi_struct napi; | |
399 | struct device *pdev; | |
400 | struct net_device *netdev; | |
401 | __be32 mkey_be; | |
402 | u8 num_tc; | |
403 | unsigned long flags; | |
03289b88 | 404 | int tc_to_txq_map[MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
405 | |
406 | /* control */ | |
407 | struct mlx5e_priv *priv; | |
408 | int ix; | |
409 | int cpu; | |
410 | }; | |
411 | ||
412 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
413 | MLX5E_TT_IPV4_TCP, |
414 | MLX5E_TT_IPV6_TCP, | |
415 | MLX5E_TT_IPV4_UDP, | |
416 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
417 | MLX5E_TT_IPV4_IPSEC_AH, |
418 | MLX5E_TT_IPV6_IPSEC_AH, | |
419 | MLX5E_TT_IPV4_IPSEC_ESP, | |
420 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
421 | MLX5E_TT_IPV4, |
422 | MLX5E_TT_IPV6, | |
423 | MLX5E_TT_ANY, | |
424 | MLX5E_NUM_TT, | |
f62b8bb8 AV |
425 | }; |
426 | ||
4cbeaff5 AS |
427 | enum mlx5e_rqt_ix { |
428 | MLX5E_INDIRECTION_RQT, | |
429 | MLX5E_SINGLE_RQ_RQT, | |
430 | MLX5E_NUM_RQT, | |
f62b8bb8 AV |
431 | }; |
432 | ||
433 | struct mlx5e_eth_addr_info { | |
434 | u8 addr[ETH_ALEN + 2]; | |
435 | u32 tt_vec; | |
436 | u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */ | |
437 | }; | |
438 | ||
439 | #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) | |
440 | ||
441 | struct mlx5e_eth_addr_db { | |
442 | struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
443 | struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
444 | struct mlx5e_eth_addr_info broadcast; | |
445 | struct mlx5e_eth_addr_info allmulti; | |
446 | struct mlx5e_eth_addr_info promisc; | |
447 | bool broadcast_enabled; | |
448 | bool allmulti_enabled; | |
449 | bool promisc_enabled; | |
450 | }; | |
451 | ||
452 | enum { | |
453 | MLX5E_STATE_ASYNC_EVENTS_ENABLE, | |
454 | MLX5E_STATE_OPENED, | |
9b37b07f | 455 | MLX5E_STATE_DESTROYING, |
f62b8bb8 AV |
456 | }; |
457 | ||
458 | struct mlx5e_vlan_db { | |
f62b8bb8 AV |
459 | u32 active_vlans_ft_ix[VLAN_N_VID]; |
460 | u32 untagged_rule_ft_ix; | |
461 | u32 any_vlan_rule_ft_ix; | |
462 | bool filter_disabled; | |
463 | }; | |
464 | ||
465 | struct mlx5e_flow_table { | |
466 | void *vlan; | |
467 | void *main; | |
468 | }; | |
469 | ||
470 | struct mlx5e_priv { | |
471 | /* priv data path fields - start */ | |
f62b8bb8 | 472 | int default_vlan_prio; |
03289b88 | 473 | struct mlx5e_sq **txq_to_sq_map; |
f62b8bb8 AV |
474 | /* priv data path fields - end */ |
475 | ||
476 | unsigned long state; | |
477 | struct mutex state_lock; /* Protects Interface state */ | |
478 | struct mlx5_uar cq_uar; | |
479 | u32 pdn; | |
3191e05f | 480 | u32 tdn; |
f62b8bb8 | 481 | struct mlx5_core_mr mr; |
50cfa25a | 482 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
483 | |
484 | struct mlx5e_channel **channel; | |
485 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
4cbeaff5 | 486 | u32 rqtn[MLX5E_NUM_RQT]; |
f62b8bb8 AV |
487 | u32 tirn[MLX5E_NUM_TT]; |
488 | ||
489 | struct mlx5e_flow_table ft; | |
490 | struct mlx5e_eth_addr_db eth_addr; | |
491 | struct mlx5e_vlan_db vlan; | |
492 | ||
493 | struct mlx5e_params params; | |
494 | spinlock_t async_events_spinlock; /* sync hw events */ | |
495 | struct work_struct update_carrier_work; | |
496 | struct work_struct set_rx_mode_work; | |
497 | struct delayed_work update_stats_work; | |
498 | ||
499 | struct mlx5_core_dev *mdev; | |
500 | struct net_device *netdev; | |
501 | struct mlx5e_stats stats; | |
502 | }; | |
503 | ||
504 | #define MLX5E_NET_IP_ALIGN 2 | |
505 | ||
506 | struct mlx5e_tx_wqe { | |
507 | struct mlx5_wqe_ctrl_seg ctrl; | |
508 | struct mlx5_wqe_eth_seg eth; | |
509 | }; | |
510 | ||
511 | struct mlx5e_rx_wqe { | |
512 | struct mlx5_wqe_srq_next_seg next; | |
513 | struct mlx5_wqe_data_seg data; | |
514 | }; | |
515 | ||
516 | enum mlx5e_link_mode { | |
517 | MLX5E_1000BASE_CX_SGMII = 0, | |
518 | MLX5E_1000BASE_KX = 1, | |
519 | MLX5E_10GBASE_CX4 = 2, | |
520 | MLX5E_10GBASE_KX4 = 3, | |
521 | MLX5E_10GBASE_KR = 4, | |
522 | MLX5E_20GBASE_KR2 = 5, | |
523 | MLX5E_40GBASE_CR4 = 6, | |
524 | MLX5E_40GBASE_KR4 = 7, | |
525 | MLX5E_56GBASE_R4 = 8, | |
526 | MLX5E_10GBASE_CR = 12, | |
527 | MLX5E_10GBASE_SR = 13, | |
528 | MLX5E_10GBASE_ER = 14, | |
529 | MLX5E_40GBASE_SR4 = 15, | |
530 | MLX5E_40GBASE_LR4 = 16, | |
531 | MLX5E_100GBASE_CR4 = 20, | |
532 | MLX5E_100GBASE_SR4 = 21, | |
533 | MLX5E_100GBASE_KR4 = 22, | |
534 | MLX5E_100GBASE_LR4 = 23, | |
535 | MLX5E_100BASE_TX = 24, | |
536 | MLX5E_100BASE_T = 25, | |
537 | MLX5E_10GBASE_T = 26, | |
538 | MLX5E_25GBASE_CR = 27, | |
539 | MLX5E_25GBASE_KR = 28, | |
540 | MLX5E_25GBASE_SR = 29, | |
541 | MLX5E_50GBASE_CR2 = 30, | |
542 | MLX5E_50GBASE_KR2 = 31, | |
543 | MLX5E_LINK_MODES_NUMBER, | |
544 | }; | |
545 | ||
546 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
547 | ||
12be4b21 | 548 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
549 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
550 | void *accel_priv, select_queue_fallback_t fallback); | |
551 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
552 | |
553 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
554 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
555 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
556 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq); | |
557 | bool mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); | |
558 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); | |
559 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); | |
560 | ||
561 | void mlx5e_update_stats(struct mlx5e_priv *priv); | |
562 | ||
40ab6a6e AS |
563 | int mlx5e_create_flow_tables(struct mlx5e_priv *priv); |
564 | void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv); | |
f62b8bb8 | 565 | void mlx5e_init_eth_addr(struct mlx5e_priv *priv); |
f62b8bb8 AV |
566 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
567 | ||
568 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, | |
569 | u16 vid); | |
570 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
571 | u16 vid); | |
572 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
573 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 574 | |
2d75b2bc AS |
575 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix); |
576 | ||
f62b8bb8 AV |
577 | int mlx5e_open_locked(struct net_device *netdev); |
578 | int mlx5e_close_locked(struct net_device *netdev); | |
f62b8bb8 AV |
579 | |
580 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, | |
88a85f99 | 581 | struct mlx5e_tx_wqe *wqe, int bf_sz) |
f62b8bb8 | 582 | { |
88a85f99 AS |
583 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
584 | ||
f62b8bb8 AV |
585 | /* ensure wqe is visible to device before updating doorbell record */ |
586 | dma_wmb(); | |
587 | ||
588 | *sq->wq.db = cpu_to_be32(sq->pc); | |
589 | ||
590 | /* ensure doorbell record is visible to device before ringing the | |
591 | * doorbell | |
592 | */ | |
593 | wmb(); | |
594 | ||
88a85f99 AS |
595 | if (bf_sz) { |
596 | __iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz); | |
597 | ||
598 | /* flush the write-combining mapped buffer */ | |
599 | wmb(); | |
600 | ||
601 | } else { | |
602 | mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL); | |
603 | } | |
f62b8bb8 AV |
604 | |
605 | sq->bf_offset ^= sq->bf_buf_size; | |
606 | } | |
607 | ||
608 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
609 | { | |
610 | struct mlx5_core_cq *mcq; | |
611 | ||
612 | mcq = &cq->mcq; | |
613 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
614 | } | |
615 | ||
616 | extern const struct ethtool_ops mlx5e_ethtool_ops; | |
58d52291 | 617 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |