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net: mvneta: read MAC address from hardware when available
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4_en.h
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#ifndef _MLX4_EN_H_
35#define _MLX4_EN_H_
36
f1b553fb 37#include <linux/bitops.h>
c27a02cd
YP		 38#include <linux/compiler.h>
39#include <linux/list.h>
40#include <linux/mutex.h>
41#include <linux/netdevice.h>
f1b553fb 42#include <linux/if_vlan.h>
ec693d47 43#include <linux/net_tstamp.h>
564c274c
AV		 44#ifdef CONFIG_MLX4_EN_DCB
45#include <linux/dcbnl.h>
46#endif
1eb8c695 47#include <linux/cpu_rmap.h>
c27a02cd
YP		 48
49#include <linux/mlx4/device.h>
50#include <linux/mlx4/qp.h>
51#include <linux/mlx4/cq.h>
52#include <linux/mlx4/srq.h>
53#include <linux/mlx4/doorbell.h>
e7c1c2c4 54#include <linux/mlx4/cmd.h>
c27a02cd
YP		 55
56#include "en_port.h"
57
58#define DRV_NAME "mlx4_en"
6edf91da
YP		 59#define DRV_VERSION "2.0"
60#define DRV_RELDATE "Dec 2011"
c27a02cd 61
c27a02cd
YP		 62#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
63
c27a02cd
YP		 64/*
65 * Device constants
66 */
67
68
69#define MLX4_EN_PAGE_SHIFT 12
70#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
d317966b
AV		 71#define DEF_RX_RINGS 16
72#define MAX_RX_RINGS 128
1fb9876e 73#define MIN_RX_RINGS 4
c27a02cd
YP		 74#define TXBB_SIZE 64
75#define HEADROOM (2048 / TXBB_SIZE + 1)
c27a02cd
YP		 76#define STAMP_STRIDE 64
77#define STAMP_DWORDS (STAMP_STRIDE / 4)
78#define STAMP_SHIFT 31
79#define STAMP_VAL 0x7fffffff
80#define STATS_DELAY (HZ / 4)
b6c39bfc 81#define SERVICE_TASK_DELAY (HZ / 4)
82067281 82#define MAX_NUM_OF_FS_RULES 256
c27a02cd 83
1eb8c695
AV		 84#define MLX4_EN_FILTER_HASH_SHIFT 4
85#define MLX4_EN_FILTER_EXPIRY_QUOTA 60
86
c27a02cd
YP		 87/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
88#define MAX_DESC_SIZE 512
89#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
90
91/*
92 * OS related constants and tunables
93 */
94
95#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
96
117980c4
TLSC		 97/* Use the maximum between 16384 and a single page */
98#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
99#define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
c27a02cd 100
c27a02cd
YP		 101/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
102 * and 4K allocations) */
103enum {
104 FRAG_SZ0 = 512 - NET_IP_ALIGN,
105 FRAG_SZ1 = 1024,
106 FRAG_SZ2 = 4096,
107 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
108};
109#define MLX4_EN_MAX_RX_FRAGS 4
110
bd531e36
YP		 111/* Maximum ring sizes */
112#define MLX4_EN_MAX_TX_SIZE 8192
113#define MLX4_EN_MAX_RX_SIZE 8192
114
4cce66cd 115/* Minimum ring size for our page-allocation scheme to work */
c27a02cd
YP		 116#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
117#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
118
f813cad8 119#define MLX4_EN_SMALL_PKT_SIZE 64
bc6a4744 120#define MLX4_EN_MAX_TX_RING_P_UP 32
564c274c 121#define MLX4_EN_NUM_UP 8
f813cad8 122#define MLX4_EN_DEF_TX_RING_SIZE 512
c27a02cd 123#define MLX4_EN_DEF_RX_RING_SIZE 1024
d317966b
AV		 124#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
125 MLX4_EN_NUM_UP)
c27a02cd 126
3db36fb2
YP		 127/* Target number of packets to coalesce with interrupt moderation */
128#define MLX4_EN_RX_COAL_TARGET 44
c27a02cd
YP		 129#define MLX4_EN_RX_COAL_TIME 0x10
130
e22979d9 131#define MLX4_EN_TX_COAL_PKTS 16
ecfd2ce1 132#define MLX4_EN_TX_COAL_TIME 0x10
c27a02cd
YP		 133
134#define MLX4_EN_RX_RATE_LOW 400000
135#define MLX4_EN_RX_COAL_TIME_LOW 0
136#define MLX4_EN_RX_RATE_HIGH 450000
137#define MLX4_EN_RX_COAL_TIME_HIGH 128
138#define MLX4_EN_RX_SIZE_THRESH 1024
139#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
140#define MLX4_EN_SAMPLE_INTERVAL 0
46afd0fb 141#define MLX4_EN_AVG_PKT_SMALL 256
c27a02cd
YP		 142
143#define MLX4_EN_AUTO_CONF 0xffff
144
145#define MLX4_EN_DEF_RX_PAUSE 1
146#define MLX4_EN_DEF_TX_PAUSE 1
147
af901ca1 148/* Interval between successive polls in the Tx routine when polling is used
c27a02cd
YP		 149 instead of interrupts (in per-core Tx rings) - should be power of 2 */
150#define MLX4_EN_TX_POLL_MODER 16
151#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
152
153#define ETH_LLC_SNAP_SIZE 8
154
155#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
156#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
e7c1c2c4 157#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
c27a02cd
YP		 158
159#define MLX4_EN_MIN_MTU 46
160#define ETH_BCAST 0xffffffffffffULL
161
e7c1c2c4
YP		 162#define MLX4_EN_LOOPBACK_RETRIES 5
163#define MLX4_EN_LOOPBACK_TIMEOUT 100
164
c27a02cd
YP		 165#ifdef MLX4_EN_PERF_STAT
166/* Number of samples to 'average' */
167#define AVG_SIZE 128
168#define AVG_FACTOR 1024
169#define NUM_PERF_STATS NUM_PERF_COUNTERS
170
171#define INC_PERF_COUNTER(cnt) (++(cnt))
172#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
173#define AVG_PERF_COUNTER(cnt, sample) \
174 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
175#define GET_PERF_COUNTER(cnt) (cnt)
176#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
177
178#else
179
180#define NUM_PERF_STATS 0
181#define INC_PERF_COUNTER(cnt) do {} while (0)
182#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
183#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
184#define GET_PERF_COUNTER(cnt) (0)
185#define GET_AVG_PERF_COUNTER(cnt) (0)
186#endif /* MLX4_EN_PERF_STAT */
187
188/*
189 * Configurables
190 */
191
192enum cq_type {
193 RX = 0,
194 TX = 1,
195};
196
197
198/*
199 * Useful macros
200 */
201#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
202#define XNOR(x, y) (!(x) == !(y))
c27a02cd
YP		 203
204
205struct mlx4_en_tx_info {
206 struct sk_buff *skb;
207 u32 nr_txbb;
5b263f53 208 u32 nr_bytes;
c27a02cd
YP		 209 u8 linear;
210 u8 data_offset;
41efea5a 211 u8 inl;
ec693d47 212 u8 ts_requested;
c27a02cd
YP		 213};
214
215
216#define MLX4_EN_BIT_DESC_OWN 0x80000000
217#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
218#define MLX4_EN_MEMTYPE_PAD 0x100
219#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
220
221
222struct mlx4_en_tx_desc {
223 struct mlx4_wqe_ctrl_seg ctrl;
224 union {
225 struct mlx4_wqe_data_seg data; /* at least one data segment */
226 struct mlx4_wqe_lso_seg lso;
227 struct mlx4_wqe_inline_seg inl;
228 };
229};
230
231#define MLX4_EN_USE_SRQ 0x01000000
232
725c8999
YP		 233#define MLX4_EN_CX3_LOW_ID 0x1000
234#define MLX4_EN_CX3_HIGH_ID 0x1005
235
c27a02cd
YP		 236struct mlx4_en_rx_alloc {
237 struct page *page;
4cce66cd 238 dma_addr_t dma;
c27a02cd
YP		 239 u16 offset;
240};
241
242struct mlx4_en_tx_ring {
243 struct mlx4_hwq_resources wqres;
244 u32 size ; /* number of TXBBs */
245 u32 size_mask;
246 u16 stride;
247 u16 cqn; /* index of port CQ associated with this ring */
248 u32 prod;
249 u32 cons;
250 u32 buf_size;
251 u32 doorbell_qpn;
252 void *buf;
253 u16 poll_cnt;
c27a02cd
YP		 254 struct mlx4_en_tx_info *tx_info;
255 u8 *bounce_buf;
256 u32 last_nr_txbb;
257 struct mlx4_qp qp;
258 struct mlx4_qp_context context;
259 int qpn;
260 enum mlx4_qp_state qp_state;
261 struct mlx4_srq dummy;
262 unsigned long bytes;
263 unsigned long packets;
ad04378c 264 unsigned long tx_csum;
87a5c389
YP		 265 struct mlx4_bf bf;
266 bool bf_enabled;
5b263f53 267 struct netdev_queue *tx_queue;
ec693d47 268 int hwtstamp_tx_type;
c27a02cd
YP		 269};
270
271struct mlx4_en_rx_desc {
c27a02cd
YP		 272 /* actual number of entries depends on rx ring stride */
273 struct mlx4_wqe_data_seg data[0];
274};
275
276struct mlx4_en_rx_ring {
c27a02cd
YP		 277 struct mlx4_hwq_resources wqres;
278 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
c27a02cd
YP		 279 u32 size ; /* number of Rx descs*/
280 u32 actual_size;
281 u32 size_mask;
282 u16 stride;
283 u16 log_stride;
284 u16 cqn; /* index of port CQ associated with this ring */
285 u32 prod;
286 u32 cons;
287 u32 buf_size;
4a5f4dd8 288 u8 fcs_del;
c27a02cd
YP		 289 void *buf;
290 void *rx_info;
291 unsigned long bytes;
292 unsigned long packets;
ad04378c
YP		 293 unsigned long csum_ok;
294 unsigned long csum_none;
ec693d47 295 int hwtstamp_rx_filter;
c27a02cd
YP		 296};
297
c27a02cd
YP		 298struct mlx4_en_cq {
299 struct mlx4_cq mcq;
300 struct mlx4_hwq_resources wqres;
301 int ring;
302 spinlock_t lock;
303 struct net_device *dev;
304 struct napi_struct napi;
c27a02cd
YP		 305 int size;
306 int buf_size;
307 unsigned vector;
308 enum cq_type is_tx;
309 u16 moder_time;
310 u16 moder_cnt;
c27a02cd
YP		 311 struct mlx4_cqe *buf;
312#define MLX4_EN_OPCODE_ERROR 0x1e
313};
314
315struct mlx4_en_port_profile {
316 u32 flags;
317 u32 tx_ring_num;
318 u32 rx_ring_num;
319 u32 tx_ring_size;
320 u32 rx_ring_size;
d53b93f2
YP		 321 u8 rx_pause;
322 u8 rx_ppp;
323 u8 tx_pause;
324 u8 tx_ppp;
93d3e367 325 int rss_rings;
c27a02cd
YP		 326};
327
328struct mlx4_en_profile {
329 int rss_xor;
0533943c 330 int udp_rss;
c27a02cd
YP		 331 u8 rss_mask;
332 u32 active_ports;
333 u32 small_pkt_int;
c27a02cd 334 u8 no_reset;
bc6a4744 335 u8 num_tx_rings_p_up;
c27a02cd
YP		 336 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
337};
338
339struct mlx4_en_dev {
340 struct mlx4_dev *dev;
341 struct pci_dev *pdev;
342 struct mutex state_lock;
343 struct net_device *pndev[MLX4_MAX_PORTS + 1];
344 u32 port_cnt;
345 bool device_up;
346 struct mlx4_en_profile profile;
347 u32 LSO_support;
348 struct workqueue_struct *workqueue;
349 struct device *dma_device;
350 void __iomem *uar_map;
351 struct mlx4_uar priv_uar;
352 struct mlx4_mr mr;
353 u32 priv_pdn;
354 spinlock_t uar_lock;
d7e1a487 355 u8 mac_removed[MLX4_MAX_PORTS + 1];
ec693d47
AV		 356 struct cyclecounter cycles;
357 struct timecounter clock;
358 unsigned long last_overflow_check;
b6c39bfc 359 unsigned long overflow_period;
c27a02cd
YP		 360};
361
362
363struct mlx4_en_rss_map {
c27a02cd 364 int base_qpn;
b6b912e0
YP		 365 struct mlx4_qp qps[MAX_RX_RINGS];
366 enum mlx4_qp_state state[MAX_RX_RINGS];
c27a02cd
YP		 367 struct mlx4_qp indir_qp;
368 enum mlx4_qp_state indir_state;
369};
370
e7c1c2c4
YP		 371struct mlx4_en_port_state {
372 int link_state;
373 int link_speed;
374 int transciver;
375};
376
c27a02cd
YP		 377struct mlx4_en_pkt_stats {
378 unsigned long broadcast;
379 unsigned long rx_prio[8];
380 unsigned long tx_prio[8];
381#define NUM_PKT_STATS 17
382};
383
384struct mlx4_en_port_stats {
c27a02cd
YP		 385 unsigned long tso_packets;
386 unsigned long queue_stopped;
387 unsigned long wake_queue;
388 unsigned long tx_timeout;
389 unsigned long rx_alloc_failed;
390 unsigned long rx_chksum_good;
391 unsigned long rx_chksum_none;
392 unsigned long tx_chksum_offload;
d61702f1 393#define NUM_PORT_STATS 8
c27a02cd
YP		 394};
395
396struct mlx4_en_perf_stats {
397 u32 tx_poll;
398 u64 tx_pktsz_avg;
399 u32 inflight_avg;
400 u16 tx_coal_avg;
401 u16 rx_coal_avg;
402 u32 napi_quota;
403#define NUM_PERF_COUNTERS 6
404};
405
6d199937
YP		 406enum mlx4_en_mclist_act {
407 MCLIST_NONE,
408 MCLIST_REM,
409 MCLIST_ADD,
410};
411
412struct mlx4_en_mc_list {
413 struct list_head list;
414 enum mlx4_en_mclist_act action;
415 u8 addr[ETH_ALEN];
0ff1fb65 416 u64 reg_id;
6d199937
YP		 417};
418
c27a02cd
YP		 419struct mlx4_en_frag_info {
420 u16 frag_size;
421 u16 frag_prefix_size;
422 u16 frag_stride;
423 u16 frag_align;
424 u16 last_offset;
425
426};
427
564c274c
AV		 428#ifdef CONFIG_MLX4_EN_DCB
429/* Minimal TC BW - setting to 0 will block traffic */
430#define MLX4_EN_BW_MIN 1
431#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
432
433#define MLX4_EN_TC_ETS 7
434
435#endif
436
82067281 437struct ethtool_flow_id {
0d256c0e 438 struct list_head list;
82067281
HHZ		 439 struct ethtool_rx_flow_spec flow_spec;
440 u64 id;
441};
442
79aeaccd
YB		 443enum {
444 MLX4_EN_FLAG_PROMISC = (1 << 0),
445 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
446 /* whether we need to enable hardware loopback by putting dmac
447 * in Tx WQE
448 */
449 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
450 /* whether we need to drop packets that hardware loopback-ed */
cc5387f7
YB		 451 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
452 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4)
79aeaccd
YB		 453};
454
c07cb4b0
YB		 455#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
456#define MLX4_EN_MAC_HASH_IDX 5
457
c27a02cd
YP		 458struct mlx4_en_priv {
459 struct mlx4_en_dev *mdev;
460 struct mlx4_en_port_profile *prof;
461 struct net_device *dev;
f1b553fb 462 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
c27a02cd
YP		 463 struct net_device_stats stats;
464 struct net_device_stats ret_stats;
e7c1c2c4 465 struct mlx4_en_port_state port_state;
c27a02cd 466 spinlock_t stats_lock;
82067281 467 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
0d256c0e
HHZ		 468 /* To allow rules removal while port is going down */
469 struct list_head ethtool_list;
c27a02cd 470
6b4d8d9f 471 unsigned long last_moder_packets[MAX_RX_RINGS];
c27a02cd 472 unsigned long last_moder_tx_packets;
6b4d8d9f 473 unsigned long last_moder_bytes[MAX_RX_RINGS];
c27a02cd 474 unsigned long last_moder_jiffies;
6b4d8d9f 475 int last_moder_time[MAX_RX_RINGS];
c27a02cd
YP		 476 u16 rx_usecs;
477 u16 rx_frames;
478 u16 tx_usecs;
479 u16 tx_frames;
480 u32 pkt_rate_low;
481 u16 rx_usecs_low;
482 u32 pkt_rate_high;
483 u16 rx_usecs_high;
484 u16 sample_interval;
485 u16 adaptive_rx_coal;
486 u32 msg_enable;
e7c1c2c4
YP		 487 u32 loopback_ok;
488 u32 validate_loopback;
c27a02cd
YP		 489
490 struct mlx4_hwq_resources res;
491 int link_state;
492 int last_link_state;
493 bool port_up;
494 int port;
495 int registered;
496 int allocated;
497 int stride;
6bbb6d99 498 unsigned char prev_mac[ETH_ALEN + 2];
c27a02cd
YP		 499 int mac_index;
500 unsigned max_mtu;
501 int base_qpn;
08ff3235 502 int cqe_factor;
c27a02cd
YP		 503
504 struct mlx4_en_rss_map rss_map;
4ef2a435 505 __be32 ctrl_flags;
c27a02cd 506 u32 flags;
d317966b 507 u8 num_tx_rings_p_up;
c27a02cd
YP		 508 u32 tx_ring_num;
509 u32 rx_ring_num;
510 u32 rx_skb_size;
511 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
512 u16 num_frags;
513 u16 log_rx_info;
514
bc6a4744 515 struct mlx4_en_tx_ring *tx_ring;
c27a02cd 516 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
bc6a4744 517 struct mlx4_en_cq *tx_cq;
c27a02cd 518 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
cabdc8ee 519 struct mlx4_qp drop_qp;
0eb74fdd 520 struct work_struct rx_mode_task;
c27a02cd
YP		 521 struct work_struct watchdog_task;
522 struct work_struct linkstate_task;
523 struct delayed_work stats_task;
b6c39bfc 524 struct delayed_work service_task;
c27a02cd
YP		 525 struct mlx4_en_perf_stats pstats;
526 struct mlx4_en_pkt_stats pkstats;
527 struct mlx4_en_port_stats port_stats;
93ece0c1 528 u64 stats_bitmap;
6d199937
YP		 529 struct list_head mc_list;
530 struct list_head curr_list;
0ff1fb65 531 u64 broadcast_id;
c27a02cd 532 struct mlx4_en_stat_out_mbox hw_stats;
4c3eb3ca 533 int vids[128];
14c07b13 534 bool wol;
ebf8c9aa 535 struct device *ddev;
044ca2a5 536 int base_tx_qpn;
c07cb4b0 537 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
ec693d47 538 struct hwtstamp_config hwtstamp_config;
564c274c
AV		 539
540#ifdef CONFIG_MLX4_EN_DCB
541 struct ieee_ets ets;
109d2446 542 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
564c274c 543#endif
1eb8c695
AV		 544#ifdef CONFIG_RFS_ACCEL
545 spinlock_t filters_lock;
546 int last_filter_id;
547 struct list_head filters;
548 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
549#endif
550
14c07b13
YP		 551};
552
553enum mlx4_en_wol {
554 MLX4_EN_WOL_MAGIC = (1ULL << 61),
555 MLX4_EN_WOL_ENABLED = (1ULL << 62),
c27a02cd
YP		 556};
557
16a10ffd 558struct mlx4_mac_entry {
c07cb4b0 559 struct hlist_node hlist;
16a10ffd
YB		 560 unsigned char mac[ETH_ALEN + 2];
561 u64 reg_id;
c07cb4b0 562 struct rcu_head rcu;
16a10ffd
YB		 563};
564
0d9fdaa9 565#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
c27a02cd 566
79aeaccd
YB		 567void mlx4_en_update_loopback_state(struct net_device *dev,
568 netdev_features_t features);
569
c27a02cd
YP		 570void mlx4_en_destroy_netdev(struct net_device *dev);
571int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
572 struct mlx4_en_port_profile *prof);
573
18cc42a3 574int mlx4_en_start_port(struct net_device *dev);
3484aac1 575void mlx4_en_stop_port(struct net_device *dev, int detach);
18cc42a3 576
fe0af03c 577void mlx4_en_free_resources(struct mlx4_en_priv *priv);
18cc42a3
YP		 578int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
579
c27a02cd
YP		 580int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
581 int entries, int ring, enum cq_type mode);
fe0af03c 582void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
76532d0c
AG		 583int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
584 int cq_idx);
c27a02cd
YP		 585void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
586int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
587int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
588
c27a02cd 589void mlx4_en_tx_irq(struct mlx4_cq *mcq);
f813cad8 590u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
61357325 591netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
c27a02cd
YP		 592
593int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
87a5c389 594 int qpn, u32 size, u16 stride);
c27a02cd
YP		 595void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
596int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
597 struct mlx4_en_tx_ring *ring,
0e98b523 598 int cq, int user_prio);
c27a02cd
YP		 599void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
600 struct mlx4_en_tx_ring *ring);
601
602int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
603 struct mlx4_en_rx_ring *ring,
604 u32 size, u16 stride);
605void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
68355f71
TLSC		 606 struct mlx4_en_rx_ring *ring,
607 u32 size, u16 stride);
c27a02cd
YP		 608int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
609void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
610 struct mlx4_en_rx_ring *ring);
611int mlx4_en_process_rx_cq(struct net_device *dev,
612 struct mlx4_en_cq *cq,
613 int budget);
614int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
615void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
0e98b523
AV		 616 int is_tx, int rss, int qpn, int cqn, int user_prio,
617 struct mlx4_qp_context *context);
966508f7 618void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
c27a02cd
YP		 619int mlx4_en_map_buffer(struct mlx4_buf *buf);
620void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
621
622void mlx4_en_calc_rx_buf(struct net_device *dev);
c27a02cd
YP		 623int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
624void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
cabdc8ee
HHZ		 625int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
626void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
c27a02cd 627int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
c27a02cd
YP		 628void mlx4_en_rx_irq(struct mlx4_cq *mcq);
629
630int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
f1b553fb 631int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
c27a02cd
YP		 632
633int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
e7c1c2c4
YP		 634int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
635
564c274c
AV		 636#ifdef CONFIG_MLX4_EN_DCB
637extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
540b3a39 638extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
564c274c
AV		 639#endif
640
d317966b
AV		 641int mlx4_en_setup_tc(struct net_device *dev, u8 up);
642
1eb8c695
AV		 643#ifdef CONFIG_RFS_ACCEL
644void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
645 struct mlx4_en_rx_ring *rx_ring);
646#endif
647
e7c1c2c4
YP		 648#define MLX4_EN_NUM_SELF_TEST 5
649void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
650u64 mlx4_en_mac_to_u64(u8 *addr);
b6c39bfc 651void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
c27a02cd
YP		 652
653/*
ec693d47
AV		 654 * Functions for time stamping
655 */
656u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
657void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
658 struct skb_shared_hwtstamps *hwts,
659 u64 timestamp);
660void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
661int mlx4_en_timestamp_config(struct net_device *dev,
662 int tx_type,
663 int rx_filter);
664
665/* Globals
c27a02cd
YP		 666 */
667extern const struct ethtool_ops mlx4_en_ethtool_ops;
0a645e80
JP		 668
669
670
671/*
672 * printk / logging functions
673 */
674
b9075fa9 675__printf(3, 4)
0a645e80 676int en_print(const char *level, const struct mlx4_en_priv *priv,
b9075fa9 677 const char *format, ...);
0a645e80
JP		 678
679#define en_dbg(mlevel, priv, format, arg...) \
680do { \
681 if (NETIF_MSG_##mlevel & priv->msg_enable) \
682 en_print(KERN_DEBUG, priv, format, ##arg); \
683} while (0)
684#define en_warn(priv, format, arg...) \
685 en_print(KERN_WARNING, priv, format, ##arg)
686#define en_err(priv, format, arg...) \
687 en_print(KERN_ERR, priv, format, ##arg)
e5cc44b2
YP		 688#define en_info(priv, format, arg...) \
689 en_print(KERN_INFO, priv, format, ## arg)
0a645e80
JP		 690
691#define mlx4_err(mdev, format, arg...) \
692 pr_err("%s %s: " format, DRV_NAME, \
693 dev_name(&mdev->pdev->dev), ##arg)
694#define mlx4_info(mdev, format, arg...) \
695 pr_info("%s %s: " format, DRV_NAME, \
696 dev_name(&mdev->pdev->dev), ##arg)
697#define mlx4_warn(mdev, format, arg...) \
698 pr_warning("%s %s: " format, DRV_NAME, \
699 dev_name(&mdev->pdev->dev), ##arg)
700
c27a02cd 701#endif
Linux 6.x block layer and io_uring tree(s)