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net/mlx4_core: Refactor mlx4_cmd_init and mlx4_cmd_cleanup
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
dd41cc3b 80static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 81static int num_vfs_argc;
dd41cc3b
MB		 82module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 87static int probe_vfs_argc;
dd41cc3b
MB		 88module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
ab9c17a0 91
3c439b55 92int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 93module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
3c439b55 97 " 10 gives 248.range: 7 <="
0ff1fb65 98 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 99 " To activate device managed"
100 " flow steering when available, set to -1");
0ec2c0f8 101
be902ab1 102static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 103module_param(enable_64b_cqe_eqe, bool, 0444);
104MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 106
77507aa2
IS		 107#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
108 MLX4_FUNC_CAP_EQE_CQE_STRIDE)
ab9c17a0 109
f57e6848 110static char mlx4_version[] =
225c7b1f
RD		 111 DRV_NAME ": Mellanox ConnectX core driver v"
112 DRV_VERSION " (" DRV_RELDATE ")\n";
113
114static struct mlx4_profile default_profile = {
ab9c17a0 115 .num_qp = 1 << 18,
225c7b1f 116 .num_srq = 1 << 16,
c9f2ba5e 117 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 118 .num_cq = 1 << 16,
119 .num_mcg = 1 << 13,
ab9c17a0 120 .num_mpt = 1 << 19,
9fd7a1e1 121 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 122};
123
2599d858
AV		 124static struct mlx4_profile low_mem_profile = {
125 .num_qp = 1 << 17,
126 .num_srq = 1 << 6,
127 .rdmarc_per_qp = 1 << 4,
128 .num_cq = 1 << 8,
129 .num_mcg = 1 << 8,
130 .num_mpt = 1 << 9,
131 .num_mtt = 1 << 7,
132};
133
ab9c17a0 134static int log_num_mac = 7;
93fc9e1b
YP		 135module_param_named(log_num_mac, log_num_mac, int, 0444);
136MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
137
138static int log_num_vlan;
139module_param_named(log_num_vlan, log_num_vlan, int, 0444);
140MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 141/* Log2 max number of VLANs per ETH port (0-7) */
142#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 143#define MLX4_MIN_LOG_NUM_VLANS 0
144#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 145
eb939922 146static bool use_prio;
93fc9e1b 147module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 148MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 149
2b8fb286 150int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 151module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 152MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 153
8d0fc7b6 154static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 155static int arr_argc = 2;
156module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 157MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
158 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 159
160struct mlx4_port_config {
161 struct list_head list;
162 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
163 struct pci_dev *pdev;
164};
165
97989356
AV		 166static atomic_t pf_loading = ATOMIC_INIT(0);
167
27bf91d6
YP		 168int mlx4_check_port_params(struct mlx4_dev *dev,
169 enum mlx4_port_type *port_type)
7ff93f8b
YP		 170{
171 int i;
172
173 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 174 if (port_type[i] != port_type[i + 1]) {
175 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
1a91de28 176 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 177 return -EINVAL;
178 }
7ff93f8b
YP		 179 }
180 }
7ff93f8b
YP		 181
182 for (i = 0; i < dev->caps.num_ports; i++) {
183 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 184 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
185 i + 1);
7ff93f8b
YP		 186 return -EINVAL;
187 }
188 }
189 return 0;
190}
191
192static void mlx4_set_port_mask(struct mlx4_dev *dev)
193{
194 int i;
195
7ff93f8b 196 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 197 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 198}
f2a3f6a3 199
77507aa2
IS		 200static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
201{
202 struct mlx4_caps *dev_cap = &dev->caps;
203
204 /* FW not supporting or cancelled by user */
205 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
206 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
207 return;
208
209 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
210 * When FW has NCSI it may decide not to report 64B CQE/EQEs
211 */
212 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
213 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
214 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
215 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
216 return;
217 }
218
219 if (cache_line_size() == 128 || cache_line_size() == 256) {
220 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
221 /* Changing the real data inside CQE size to 32B */
222 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
223 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
224
225 if (mlx4_is_master(dev))
226 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
227 } else {
228 mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n");
229 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
230 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
231 }
232}
233
3d73c288 234static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 235{
236 int err;
5ae2a7a8 237 int i;
225c7b1f
RD		 238
239 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
240 if (err) {
1a91de28 241 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 242 return err;
243 }
244
245 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 246 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 247 dev_cap->min_page_sz, PAGE_SIZE);
248 return -ENODEV;
249 }
250 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 251 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 252 dev_cap->num_ports, MLX4_MAX_PORTS);
253 return -ENODEV;
254 }
255
256 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
1a91de28 257 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f
RD		 258 dev_cap->uar_size,
259 (unsigned long long) pci_resource_len(dev->pdev, 2));
260 return -ENODEV;
261 }
262
263 dev->caps.num_ports = dev_cap->num_ports;
3fc929e2 264 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
5ae2a7a8
RD		 265 for (i = 1; i <= dev->caps.num_ports; ++i) {
266 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 267 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
6634961c
JM		 268 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
269 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
270 /* set gid and pkey table operating lengths by default
271 * to non-sriov values */
5ae2a7a8
RD		 272 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
273 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
274 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 275 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
276 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 277 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 278 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
279 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 280 dev->caps.trans_type[i] = dev_cap->trans_type[i];
281 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
282 dev->caps.wavelength[i] = dev_cap->wavelength[i];
283 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 284 }
285
ab9c17a0 286 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 287 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 288 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
289 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
290 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
291 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
292 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
293 dev->caps.max_wqes = dev_cap->max_qp_sz;
294 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 295 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
296 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
297 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
298 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
299 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 300 /*
301 * Subtract 1 from the limit because we need to allocate a
302 * spare CQE so the HCA HW can tell the difference between an
303 * empty CQ and a full CQ.
304 */
305 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
306 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
307 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 308 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 309 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 310
311 /* The first 128 UARs are used for EQ doorbells */
312 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 313 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 314 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
315 dev_cap->reserved_xrcds : 0;
316 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
317 dev_cap->max_xrcds : 0;
2b8fb286
MA		 318 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
319
149983af 320 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 321 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
322 dev->caps.flags = dev_cap->flags;
b3416f44 323 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 324 dev->caps.bmme_flags = dev_cap->bmme_flags;
325 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 326 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 327 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 328 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 329
ca3e57a5
RD		 330 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
331 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 332 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 333 /* Don't do sense port on multifunction devices (for now at least) */
334 if (mlx4_is_mfunc(dev))
335 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 336
2599d858
AV		 337 if (mlx4_low_memory_profile()) {
338 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
339 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
340 } else {
341 dev->caps.log_num_macs = log_num_mac;
342 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
343 }
93fc9e1b
YP		 344
345 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 346 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
347 if (dev->caps.supported_type[i]) {
348 /* if only ETH is supported - assign ETH */
349 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
350 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 351 /* if only IB is supported, assign IB */
ab9c17a0 352 else if (dev->caps.supported_type[i] ==
105c320f
JM		 353 MLX4_PORT_TYPE_IB)
354 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 355 else {
105c320f
JM		 356 /* if IB and ETH are supported, we set the port
357 * type according to user selection of port type;
358 * if user selected none, take the FW hint */
359 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 360 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
361 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 362 else
105c320f 363 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 364 }
365 }
8d0fc7b6
YP		 366 /*
367 * Link sensing is allowed on the port if 3 conditions are true:
368 * 1. Both protocols are supported on the port.
369 * 2. Different types are supported on the port
370 * 3. FW declared that it supports link sensing
371 */
27bf91d6 372 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 373 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 374 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 375 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 376
8d0fc7b6
YP		 377 /*
378 * If "default_sense" bit is set, we move the port to "AUTO" mode
379 * and perform sense_port FW command to try and set the correct
380 * port type from beginning
381 */
46c46747 382 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 383 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
384 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
385 mlx4_SENSE_PORT(dev, i, &sensed_port);
386 if (sensed_port != MLX4_PORT_TYPE_NONE)
387 dev->caps.port_type[i] = sensed_port;
388 } else {
389 dev->caps.possible_type[i] = dev->caps.port_type[i];
390 }
391
93fc9e1b
YP		 392 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
393 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
1a91de28 394 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 395 i, 1 << dev->caps.log_num_macs);
396 }
397 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
398 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
1a91de28 399 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 400 i, 1 << dev->caps.log_num_vlans);
401 }
402 }
403
f2a3f6a3
OG		 404 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
405
93fc9e1b
YP		 406 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
407 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
408 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
409 (1 << dev->caps.log_num_macs) *
410 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 411 dev->caps.num_ports;
412 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
413
414 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
415 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
416 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
417 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
418
e2c76824 419 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 420
b3051320 421 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 422 if (dev_cap->flags &
423 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
424 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
425 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
426 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
427 }
77507aa2
IS		 428
429 if (dev_cap->flags2 &
430 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
431 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
432 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
433 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
434 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
435 }
08ff3235
OG		 436 }
437
f97b4b5d 438 if ((dev->caps.flags &
08ff3235
OG		 439 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
440 mlx4_is_master(dev))
441 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
442
77507aa2
IS		 443 if (!mlx4_is_slave(dev))
444 mlx4_enable_cqe_eqe_stride(dev);
445
225c7b1f
RD		 446 return 0;
447}
b912b2f8
EP		 448
449static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
450 enum pci_bus_speed *speed,
451 enum pcie_link_width *width)
452{
453 u32 lnkcap1, lnkcap2;
454 int err1, err2;
455
456#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
457
458 *speed = PCI_SPEED_UNKNOWN;
459 *width = PCIE_LNK_WIDTH_UNKNOWN;
460
461 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
462 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
463 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
464 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
465 *speed = PCIE_SPEED_8_0GT;
466 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
467 *speed = PCIE_SPEED_5_0GT;
468 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
469 *speed = PCIE_SPEED_2_5GT;
470 }
471 if (!err1) {
472 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
473 if (!lnkcap2) { /* pre-r3.0 */
474 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
475 *speed = PCIE_SPEED_5_0GT;
476 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
477 *speed = PCIE_SPEED_2_5GT;
478 }
479 }
480
481 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
482 return err1 ? err1 :
483 err2 ? err2 : -EINVAL;
484 }
485 return 0;
486}
487
488static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
489{
490 enum pcie_link_width width, width_cap;
491 enum pci_bus_speed speed, speed_cap;
492 int err;
493
494#define PCIE_SPEED_STR(speed) \
495 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
496 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
497 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
498 "Unknown")
499
500 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
501 if (err) {
502 mlx4_warn(dev,
503 "Unable to determine PCIe device BW capabilities\n");
504 return;
505 }
506
507 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
508 if (err || speed == PCI_SPEED_UNKNOWN ||
509 width == PCIE_LNK_WIDTH_UNKNOWN) {
510 mlx4_warn(dev,
511 "Unable to determine PCI device chain minimum BW\n");
512 return;
513 }
514
515 if (width != width_cap || speed != speed_cap)
516 mlx4_warn(dev,
517 "PCIe BW is different than device's capability\n");
518
519 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
520 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
521 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
522 width, width_cap);
523 return;
524}
525
ab9c17a0
JM		 526/*The function checks if there are live vf, return the num of them*/
527static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
528{
529 struct mlx4_priv *priv = mlx4_priv(dev);
530 struct mlx4_slave_state *s_state;
531 int i;
532 int ret = 0;
533
534 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
535 s_state = &priv->mfunc.master.slave_state[i];
536 if (s_state->active && s_state->last_cmd !=
537 MLX4_COMM_CMD_RESET) {
538 mlx4_warn(dev, "%s: slave: %d is still active\n",
539 __func__, i);
540 ret++;
541 }
542 }
543 return ret;
544}
545
396f2feb
JM		 546int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
547{
548 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 549
550 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
551 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 552 return -EINVAL;
553
47605df9 554 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 555 /* tunnel qp */
47605df9 556 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 557 else
47605df9 558 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 559 *qkey = qk;
560 return 0;
561}
562EXPORT_SYMBOL(mlx4_get_parav_qkey);
563
54679e14
JM		 564void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
565{
566 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
567
568 if (!mlx4_is_master(dev))
569 return;
570
571 priv->virt2phys_pkey[slave][port - 1][i] = val;
572}
573EXPORT_SYMBOL(mlx4_sync_pkey_table);
574
afa8fd1d
JM		 575void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
576{
577 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
578
579 if (!mlx4_is_master(dev))
580 return;
581
582 priv->slave_node_guids[slave] = guid;
583}
584EXPORT_SYMBOL(mlx4_put_slave_node_guid);
585
586__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
587{
588 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
589
590 if (!mlx4_is_master(dev))
591 return 0;
592
593 return priv->slave_node_guids[slave];
594}
595EXPORT_SYMBOL(mlx4_get_slave_node_guid);
596
e10903b0 597int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 598{
599 struct mlx4_priv *priv = mlx4_priv(dev);
600 struct mlx4_slave_state *s_slave;
601
602 if (!mlx4_is_master(dev))
603 return 0;
604
605 s_slave = &priv->mfunc.master.slave_state[slave];
606 return !!s_slave->active;
607}
608EXPORT_SYMBOL(mlx4_is_slave_active);
609
7b8157be
JM		 610static void slave_adjust_steering_mode(struct mlx4_dev *dev,
611 struct mlx4_dev_cap *dev_cap,
612 struct mlx4_init_hca_param *hca_param)
613{
614 dev->caps.steering_mode = hca_param->steering_mode;
615 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
616 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
617 dev->caps.fs_log_max_ucast_qp_range_size =
618 dev_cap->fs_log_max_ucast_qp_range_size;
619 } else
620 dev->caps.num_qp_per_mgm =
621 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
622
623 mlx4_dbg(dev, "Steering mode is: %s\n",
624 mlx4_steering_mode_str(dev->caps.steering_mode));
625}
626
ab9c17a0
JM		 627static int mlx4_slave_cap(struct mlx4_dev *dev)
628{
629 int err;
630 u32 page_size;
631 struct mlx4_dev_cap dev_cap;
632 struct mlx4_func_cap func_cap;
633 struct mlx4_init_hca_param hca_param;
225c6c8c 634 u8 i;
ab9c17a0
JM		 635
636 memset(&hca_param, 0, sizeof(hca_param));
637 err = mlx4_QUERY_HCA(dev, &hca_param);
638 if (err) {
1a91de28 639 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
ab9c17a0
JM		 640 return err;
641 }
642
483e0132
EP		 643 /* fail if the hca has an unknown global capability
644 * at this time global_caps should be always zeroed
645 */
646 if (hca_param.global_caps) {
ab9c17a0
JM		 647 mlx4_err(dev, "Unknown hca global capabilities\n");
648 return -ENOSYS;
649 }
650
651 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
652
ddd8a6c1
EE		 653 dev->caps.hca_core_clock = hca_param.hca_core_clock;
654
ab9c17a0 655 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 656 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 657 err = mlx4_dev_cap(dev, &dev_cap);
658 if (err) {
1a91de28 659 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 660 return err;
661 }
662
b91cb3eb
JM		 663 err = mlx4_QUERY_FW(dev);
664 if (err)
1a91de28 665 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 666
ab9c17a0
JM		 667 page_size = ~dev->caps.page_size_cap + 1;
668 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
669 if (page_size > PAGE_SIZE) {
1a91de28 670 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0
JM		 671 page_size, PAGE_SIZE);
672 return -ENODEV;
673 }
674
675 /* slave gets uar page size from QUERY_HCA fw command */
676 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
677
678 /* TODO: relax this assumption */
679 if (dev->caps.uar_page_size != PAGE_SIZE) {
680 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
681 dev->caps.uar_page_size, PAGE_SIZE);
682 return -ENODEV;
683 }
684
685 memset(&func_cap, 0, sizeof(func_cap));
47605df9 686 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 687 if (err) {
1a91de28
JP		 688 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
689 err);
ab9c17a0
JM		 690 return err;
691 }
692
693 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
694 PF_CONTEXT_BEHAVIOUR_MASK) {
695 mlx4_err(dev, "Unknown pf context behaviour\n");
696 return -ENOSYS;
697 }
698
ab9c17a0 699 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 700 dev->quotas.qp = func_cap.qp_quota;
701 dev->quotas.srq = func_cap.srq_quota;
702 dev->quotas.cq = func_cap.cq_quota;
703 dev->quotas.mpt = func_cap.mpt_quota;
704 dev->quotas.mtt = func_cap.mtt_quota;
705 dev->caps.num_qps = 1 << hca_param.log_num_qps;
706 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
707 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
708 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
709 dev->caps.num_eqs = func_cap.max_eq;
710 dev->caps.reserved_eqs = func_cap.reserved_eq;
ab9c17a0
JM		 711 dev->caps.num_pds = MLX4_NUM_PDS;
712 dev->caps.num_mgms = 0;
713 dev->caps.num_amgms = 0;
714
ab9c17a0 715 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 716 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
717 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 718 return -ENODEV;
719 }
720
99ec41d0 721 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
47605df9
JM		 722 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
723 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
724 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
725 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
726
727 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
99ec41d0
JM		 728 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
729 !dev->caps.qp0_qkey) {
47605df9
JM		 730 err = -ENOMEM;
731 goto err_mem;
732 }
733
6634961c 734 for (i = 1; i <= dev->caps.num_ports; ++i) {
225c6c8c 735 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
47605df9 736 if (err) {
1a91de28
JP		 737 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
738 i, err);
47605df9
JM		 739 goto err_mem;
740 }
99ec41d0 741 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
47605df9
JM		 742 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
743 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
744 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
745 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 746 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 747 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 748 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
749 &dev->caps.gid_table_len[i],
750 &dev->caps.pkey_table_len[i]))
47605df9 751 goto err_mem;
6634961c 752 }
6230bb23 753
ab9c17a0
JM		 754 if (dev->caps.uar_page_size * (dev->caps.num_uars -
755 dev->caps.reserved_uars) >
756 pci_resource_len(dev->pdev, 2)) {
1a91de28 757 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0
JM		 758 dev->caps.uar_page_size * dev->caps.num_uars,
759 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 760 goto err_mem;
ab9c17a0
JM		 761 }
762
08ff3235
OG		 763 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
764 dev->caps.eqe_size = 64;
765 dev->caps.eqe_factor = 1;
766 } else {
767 dev->caps.eqe_size = 32;
768 dev->caps.eqe_factor = 0;
769 }
770
771 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
772 dev->caps.cqe_size = 64;
77507aa2 773 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 774 } else {
775 dev->caps.cqe_size = 32;
776 }
777
77507aa2
IS		 778 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
779 dev->caps.eqe_size = hca_param.eqe_size;
780 dev->caps.eqe_factor = 0;
781 }
782
783 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
784 dev->caps.cqe_size = hca_param.cqe_size;
785 /* User still need to know when CQE > 32B */
786 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
787 }
788
f9bd2d7f 789 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 790 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 791
7b8157be
JM		 792 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
793
ab9c17a0 794 return 0;
47605df9
JM		 795
796err_mem:
99ec41d0 797 kfree(dev->caps.qp0_qkey);
47605df9
JM		 798 kfree(dev->caps.qp0_tunnel);
799 kfree(dev->caps.qp0_proxy);
800 kfree(dev->caps.qp1_tunnel);
801 kfree(dev->caps.qp1_proxy);
99ec41d0
JM		 802 dev->caps.qp0_qkey = NULL;
803 dev->caps.qp0_tunnel = NULL;
804 dev->caps.qp0_proxy = NULL;
805 dev->caps.qp1_tunnel = NULL;
806 dev->caps.qp1_proxy = NULL;
47605df9
JM		 807
808 return err;
ab9c17a0 809}
225c7b1f 810
b046ffe5
EP		 811static void mlx4_request_modules(struct mlx4_dev *dev)
812{
813 int port;
814 int has_ib_port = false;
815 int has_eth_port = false;
816#define EN_DRV_NAME "mlx4_en"
817#define IB_DRV_NAME "mlx4_ib"
818
819 for (port = 1; port <= dev->caps.num_ports; port++) {
820 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
821 has_ib_port = true;
822 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
823 has_eth_port = true;
824 }
825
b046ffe5
EP		 826 if (has_eth_port)
827 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 828 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
829 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 830}
831
7ff93f8b
YP		 832/*
833 * Change the port configuration of the device.
834 * Every user of this function must hold the port mutex.
835 */
27bf91d6
YP		 836int mlx4_change_port_types(struct mlx4_dev *dev,
837 enum mlx4_port_type *port_types)
7ff93f8b
YP		 838{
839 int err = 0;
840 int change = 0;
841 int port;
842
843 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 844 /* Change the port type only if the new type is different
845 * from the current, and not set to Auto */
3d8f9308 846 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 847 change = 1;
7ff93f8b
YP		 848 }
849 if (change) {
850 mlx4_unregister_device(dev);
851 for (port = 1; port <= dev->caps.num_ports; port++) {
852 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 853 dev->caps.port_type[port] = port_types[port - 1];
6634961c 854 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 855 if (err) {
1a91de28
JP		 856 mlx4_err(dev, "Failed to set port %d, aborting\n",
857 port);
7ff93f8b
YP		 858 goto out;
859 }
860 }
861 mlx4_set_port_mask(dev);
862 err = mlx4_register_device(dev);
b046ffe5
EP		 863 if (err) {
864 mlx4_err(dev, "Failed to register device\n");
865 goto out;
866 }
867 mlx4_request_modules(dev);
7ff93f8b
YP		 868 }
869
870out:
871 return err;
872}
873
874static ssize_t show_port_type(struct device *dev,
875 struct device_attribute *attr,
876 char *buf)
877{
878 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
879 port_attr);
880 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 881 char type[8];
882
883 sprintf(type, "%s",
884 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
885 "ib" : "eth");
886 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
887 sprintf(buf, "auto (%s)\n", type);
888 else
889 sprintf(buf, "%s\n", type);
7ff93f8b 890
27bf91d6 891 return strlen(buf);
7ff93f8b
YP		 892}
893
894static ssize_t set_port_type(struct device *dev,
895 struct device_attribute *attr,
896 const char *buf, size_t count)
897{
898 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
899 port_attr);
900 struct mlx4_dev *mdev = info->dev;
901 struct mlx4_priv *priv = mlx4_priv(mdev);
902 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 903 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
0a984556 904 static DEFINE_MUTEX(set_port_type_mutex);
7ff93f8b
YP		 905 int i;
906 int err = 0;
907
0a984556
AV		 908 mutex_lock(&set_port_type_mutex);
909
7ff93f8b
YP		 910 if (!strcmp(buf, "ib\n"))
911 info->tmp_type = MLX4_PORT_TYPE_IB;
912 else if (!strcmp(buf, "eth\n"))
913 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 914 else if (!strcmp(buf, "auto\n"))
915 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 916 else {
917 mlx4_err(mdev, "%s is not supported port type\n", buf);
0a984556
AV		 918 err = -EINVAL;
919 goto err_out;
7ff93f8b
YP		 920 }
921
27bf91d6 922 mlx4_stop_sense(mdev);
7ff93f8b 923 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 924 /* Possible type is always the one that was delivered */
925 mdev->caps.possible_type[info->port] = info->tmp_type;
926
927 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 928 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 929 mdev->caps.possible_type[i+1];
930 if (types[i] == MLX4_PORT_TYPE_AUTO)
931 types[i] = mdev->caps.port_type[i+1];
932 }
7ff93f8b 933
58a60168
YP		 934 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
935 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 936 for (i = 1; i <= mdev->caps.num_ports; i++) {
937 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
938 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
939 err = -EINVAL;
940 }
941 }
942 }
943 if (err) {
1a91de28 944 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 945 goto out;
946 }
947
948 mlx4_do_sense_ports(mdev, new_types, types);
949
950 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 951 if (err)
952 goto out;
953
27bf91d6
YP		 954 /* We are about to apply the changes after the configuration
955 * was verified, no need to remember the temporary types
956 * any more */
957 for (i = 0; i < mdev->caps.num_ports; i++)
958 priv->port[i + 1].tmp_type = 0;
7ff93f8b 959
27bf91d6 960 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 961
962out:
27bf91d6 963 mlx4_start_sense(mdev);
7ff93f8b 964 mutex_unlock(&priv->port_mutex);
0a984556
AV		 965err_out:
966 mutex_unlock(&set_port_type_mutex);
967
7ff93f8b
YP		 968 return err ? err : count;
969}
970
096335b3
OG		 971enum ibta_mtu {
972 IB_MTU_256 = 1,
973 IB_MTU_512 = 2,
974 IB_MTU_1024 = 3,
975 IB_MTU_2048 = 4,
976 IB_MTU_4096 = 5
977};
978
979static inline int int_to_ibta_mtu(int mtu)
980{
981 switch (mtu) {
982 case 256: return IB_MTU_256;
983 case 512: return IB_MTU_512;
984 case 1024: return IB_MTU_1024;
985 case 2048: return IB_MTU_2048;
986 case 4096: return IB_MTU_4096;
987 default: return -1;
988 }
989}
990
991static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
992{
993 switch (mtu) {
994 case IB_MTU_256: return 256;
995 case IB_MTU_512: return 512;
996 case IB_MTU_1024: return 1024;
997 case IB_MTU_2048: return 2048;
998 case IB_MTU_4096: return 4096;
999 default: return -1;
1000 }
1001}
1002
1003static ssize_t show_port_ib_mtu(struct device *dev,
1004 struct device_attribute *attr,
1005 char *buf)
1006{
1007 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1008 port_mtu_attr);
1009 struct mlx4_dev *mdev = info->dev;
1010
1011 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1012 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1013
1014 sprintf(buf, "%d\n",
1015 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1016 return strlen(buf);
1017}
1018
1019static ssize_t set_port_ib_mtu(struct device *dev,
1020 struct device_attribute *attr,
1021 const char *buf, size_t count)
1022{
1023 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1024 port_mtu_attr);
1025 struct mlx4_dev *mdev = info->dev;
1026 struct mlx4_priv *priv = mlx4_priv(mdev);
1027 int err, port, mtu, ibta_mtu = -1;
1028
1029 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1030 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1031 return -EINVAL;
1032 }
1033
618fad95
DB		 1034 err = kstrtoint(buf, 0, &mtu);
1035 if (!err)
096335b3
OG		 1036 ibta_mtu = int_to_ibta_mtu(mtu);
1037
618fad95 1038 if (err || ibta_mtu < 0) {
096335b3
OG		 1039 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1040 return -EINVAL;
1041 }
1042
1043 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1044
1045 mlx4_stop_sense(mdev);
1046 mutex_lock(&priv->port_mutex);
1047 mlx4_unregister_device(mdev);
1048 for (port = 1; port <= mdev->caps.num_ports; port++) {
1049 mlx4_CLOSE_PORT(mdev, port);
6634961c 1050 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1051 if (err) {
1a91de28
JP		 1052 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1053 port);
096335b3
OG		 1054 goto err_set_port;
1055 }
1056 }
1057 err = mlx4_register_device(mdev);
1058err_set_port:
1059 mutex_unlock(&priv->port_mutex);
1060 mlx4_start_sense(mdev);
1061 return err ? err : count;
1062}
1063
e8f9b2ed 1064static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1065{
1066 struct mlx4_priv *priv = mlx4_priv(dev);
1067 int err;
1068
1069 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1070 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1071 if (!priv->fw.fw_icm) {
1a91de28 1072 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1073 return -ENOMEM;
1074 }
1075
1076 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1077 if (err) {
1a91de28 1078 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1079 goto err_free;
1080 }
1081
1082 err = mlx4_RUN_FW(dev);
1083 if (err) {
1a91de28 1084 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1085 goto err_unmap_fa;
1086 }
1087
1088 return 0;
1089
1090err_unmap_fa:
1091 mlx4_UNMAP_FA(dev);
1092
1093err_free:
5b0bf5e2 1094 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1095 return err;
1096}
1097
e8f9b2ed
RD		 1098static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1099 int cmpt_entry_sz)
225c7b1f
RD		 1100{
1101 struct mlx4_priv *priv = mlx4_priv(dev);
1102 int err;
ab9c17a0 1103 int num_eqs;
225c7b1f
RD		 1104
1105 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1106 cmpt_base +
1107 ((u64) (MLX4_CMPT_TYPE_QP *
1108 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1109 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1110 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1111 0, 0);
225c7b1f
RD		 1112 if (err)
1113 goto err;
1114
1115 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1116 cmpt_base +
1117 ((u64) (MLX4_CMPT_TYPE_SRQ *
1118 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1119 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1120 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1121 if (err)
1122 goto err_qp;
1123
1124 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1125 cmpt_base +
1126 ((u64) (MLX4_CMPT_TYPE_CQ *
1127 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1128 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1129 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1130 if (err)
1131 goto err_srq;
1132
3fc929e2
MA		 1133 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1134 dev->caps.num_eqs;
225c7b1f
RD		 1135 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1136 cmpt_base +
1137 ((u64) (MLX4_CMPT_TYPE_EQ *
1138 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1139 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1140 if (err)
1141 goto err_cq;
1142
1143 return 0;
1144
1145err_cq:
1146 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1147
1148err_srq:
1149 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1150
1151err_qp:
1152 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1153
1154err:
1155 return err;
1156}
1157
3d73c288
RD		 1158static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1159 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1160{
1161 struct mlx4_priv *priv = mlx4_priv(dev);
1162 u64 aux_pages;
ab9c17a0 1163 int num_eqs;
225c7b1f
RD		 1164 int err;
1165
1166 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1167 if (err) {
1a91de28 1168 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1169 return err;
1170 }
1171
1a91de28 1172 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1173 (unsigned long long) icm_size >> 10,
1174 (unsigned long long) aux_pages << 2);
1175
1176 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1177 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1178 if (!priv->fw.aux_icm) {
1a91de28 1179 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1180 return -ENOMEM;
1181 }
1182
1183 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1184 if (err) {
1a91de28 1185 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1186 goto err_free_aux;
1187 }
1188
1189 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1190 if (err) {
1a91de28 1191 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1192 goto err_unmap_aux;
1193 }
1194
ab9c17a0 1195
3fc929e2
MA		 1196 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1197 dev->caps.num_eqs;
fa0681d2
RD		 1198 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1199 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1200 num_eqs, num_eqs, 0, 0);
225c7b1f 1201 if (err) {
1a91de28 1202 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1203 goto err_unmap_cmpt;
1204 }
1205
d7bb58fb
JM		 1206 /*
1207 * Reserved MTT entries must be aligned up to a cacheline
1208 * boundary, since the FW will write to them, while the driver
1209 * writes to all other MTT entries. (The variable
1210 * dev->caps.mtt_entry_sz below is really the MTT segment
1211 * size, not the raw entry size)
1212 */
1213 dev->caps.reserved_mtts =
1214 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1215 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1216
225c7b1f
RD		 1217 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1218 init_hca->mtt_base,
1219 dev->caps.mtt_entry_sz,
2b8fb286 1220 dev->caps.num_mtts,
5b0bf5e2 1221 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1222 if (err) {
1a91de28 1223 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1224 goto err_unmap_eq;
1225 }
1226
1227 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1228 init_hca->dmpt_base,
1229 dev_cap->dmpt_entry_sz,
1230 dev->caps.num_mpts,
5b0bf5e2 1231 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1232 if (err) {
1a91de28 1233 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1234 goto err_unmap_mtt;
1235 }
1236
1237 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1238 init_hca->qpc_base,
1239 dev_cap->qpc_entry_sz,
1240 dev->caps.num_qps,
93fc9e1b
YP		 1241 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1242 0, 0);
225c7b1f 1243 if (err) {
1a91de28 1244 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1245 goto err_unmap_dmpt;
1246 }
1247
1248 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1249 init_hca->auxc_base,
1250 dev_cap->aux_entry_sz,
1251 dev->caps.num_qps,
93fc9e1b
YP		 1252 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1253 0, 0);
225c7b1f 1254 if (err) {
1a91de28 1255 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1256 goto err_unmap_qp;
1257 }
1258
1259 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1260 init_hca->altc_base,
1261 dev_cap->altc_entry_sz,
1262 dev->caps.num_qps,
93fc9e1b
YP		 1263 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1264 0, 0);
225c7b1f 1265 if (err) {
1a91de28 1266 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1267 goto err_unmap_auxc;
1268 }
1269
1270 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1271 init_hca->rdmarc_base,
1272 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1273 dev->caps.num_qps,
93fc9e1b
YP		 1274 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1275 0, 0);
225c7b1f
RD		 1276 if (err) {
1277 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1278 goto err_unmap_altc;
1279 }
1280
1281 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1282 init_hca->cqc_base,
1283 dev_cap->cqc_entry_sz,
1284 dev->caps.num_cqs,
5b0bf5e2 1285 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1286 if (err) {
1a91de28 1287 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1288 goto err_unmap_rdmarc;
1289 }
1290
1291 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1292 init_hca->srqc_base,
1293 dev_cap->srq_entry_sz,
1294 dev->caps.num_srqs,
5b0bf5e2 1295 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1296 if (err) {
1a91de28 1297 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1298 goto err_unmap_cq;
1299 }
1300
1301 /*
0ff1fb65
HHZ		 1302 * For flow steering device managed mode it is required to use
1303 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1304 * required, but for simplicity just map the whole multicast
1305 * group table now. The table isn't very big and it's a lot
1306 * easier than trying to track ref counts.
225c7b1f
RD		 1307 */
1308 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1309 init_hca->mc_base,
1310 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1311 dev->caps.num_mgms + dev->caps.num_amgms,
1312 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1313 0, 0);
225c7b1f 1314 if (err) {
1a91de28 1315 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1316 goto err_unmap_srq;
1317 }
1318
1319 return 0;
1320
1321err_unmap_srq:
1322 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1323
1324err_unmap_cq:
1325 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1326
1327err_unmap_rdmarc:
1328 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1329
1330err_unmap_altc:
1331 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1332
1333err_unmap_auxc:
1334 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1335
1336err_unmap_qp:
1337 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1338
1339err_unmap_dmpt:
1340 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1341
1342err_unmap_mtt:
1343 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1344
1345err_unmap_eq:
fa0681d2 1346 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1347
1348err_unmap_cmpt:
1349 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1350 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1351 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1352 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1353
1354err_unmap_aux:
1355 mlx4_UNMAP_ICM_AUX(dev);
1356
1357err_free_aux:
5b0bf5e2 1358 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1359
1360 return err;
1361}
1362
1363static void mlx4_free_icms(struct mlx4_dev *dev)
1364{
1365 struct mlx4_priv *priv = mlx4_priv(dev);
1366
1367 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1368 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1369 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1370 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1371 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1372 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1373 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1374 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1375 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1376 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1377 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1378 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1379 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1380 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1381
1382 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1383 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1384}
1385
ab9c17a0
JM		 1386static void mlx4_slave_exit(struct mlx4_dev *dev)
1387{
1388 struct mlx4_priv *priv = mlx4_priv(dev);
1389
f3d4c89e 1390 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1391 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1a91de28 1392 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1393 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1394}
1395
c1b43dca
EC		 1396static int map_bf_area(struct mlx4_dev *dev)
1397{
1398 struct mlx4_priv *priv = mlx4_priv(dev);
1399 resource_size_t bf_start;
1400 resource_size_t bf_len;
1401 int err = 0;
1402
3d747473
JM		 1403 if (!dev->caps.bf_reg_size)
1404 return -ENXIO;
1405
ab9c17a0
JM		 1406 bf_start = pci_resource_start(dev->pdev, 2) +
1407 (dev->caps.num_uars << PAGE_SHIFT);
1408 bf_len = pci_resource_len(dev->pdev, 2) -
1409 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1410 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1411 if (!priv->bf_mapping)
1412 err = -ENOMEM;
1413
1414 return err;
1415}
1416
1417static void unmap_bf_area(struct mlx4_dev *dev)
1418{
1419 if (mlx4_priv(dev)->bf_mapping)
1420 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1421}
1422
ec693d47
AV		 1423cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1424{
1425 u32 clockhi, clocklo, clockhi1;
1426 cycle_t cycles;
1427 int i;
1428 struct mlx4_priv *priv = mlx4_priv(dev);
1429
1430 for (i = 0; i < 10; i++) {
1431 clockhi = swab32(readl(priv->clock_mapping));
1432 clocklo = swab32(readl(priv->clock_mapping + 4));
1433 clockhi1 = swab32(readl(priv->clock_mapping));
1434 if (clockhi == clockhi1)
1435 break;
1436 }
1437
1438 cycles = (u64) clockhi << 32 | (u64) clocklo;
1439
1440 return cycles;
1441}
1442EXPORT_SYMBOL_GPL(mlx4_read_clock);
1443
1444
ddd8a6c1
EE		 1445static int map_internal_clock(struct mlx4_dev *dev)
1446{
1447 struct mlx4_priv *priv = mlx4_priv(dev);
1448
1449 priv->clock_mapping =
1450 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1451 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1452
1453 if (!priv->clock_mapping)
1454 return -ENOMEM;
1455
1456 return 0;
1457}
1458
1459static void unmap_internal_clock(struct mlx4_dev *dev)
1460{
1461 struct mlx4_priv *priv = mlx4_priv(dev);
1462
1463 if (priv->clock_mapping)
1464 iounmap(priv->clock_mapping);
1465}
1466
225c7b1f
RD		 1467static void mlx4_close_hca(struct mlx4_dev *dev)
1468{
ddd8a6c1 1469 unmap_internal_clock(dev);
c1b43dca 1470 unmap_bf_area(dev);
ab9c17a0
JM		 1471 if (mlx4_is_slave(dev))
1472 mlx4_slave_exit(dev);
1473 else {
1474 mlx4_CLOSE_HCA(dev, 0);
1475 mlx4_free_icms(dev);
1476 mlx4_UNMAP_FA(dev);
1477 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1478 }
1479}
1480
1481static int mlx4_init_slave(struct mlx4_dev *dev)
1482{
1483 struct mlx4_priv *priv = mlx4_priv(dev);
1484 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1485 int ret_from_reset = 0;
1486 u32 slave_read;
1487 u32 cmd_channel_ver;
1488
97989356 1489 if (atomic_read(&pf_loading)) {
1a91de28 1490 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 1491 return -EPROBE_DEFER;
1492 }
1493
f3d4c89e 1494 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1495 priv->cmd.max_cmds = 1;
1496 mlx4_warn(dev, "Sending reset\n");
1497 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1498 MLX4_COMM_TIME);
1499 /* if we are in the middle of flr the slave will try
1500 * NUM_OF_RESET_RETRIES times before leaving.*/
1501 if (ret_from_reset) {
1502 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 1503 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 1504 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1505 return -EPROBE_DEFER;
ab9c17a0
JM		 1506 } else
1507 goto err;
1508 }
1509
1510 /* check the driver version - the slave I/F revision
1511 * must match the master's */
1512 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1513 cmd_channel_ver = mlx4_comm_get_version();
1514
1515 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1516 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 1517 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 1518 goto err;
1519 }
1520
1521 mlx4_warn(dev, "Sending vhcr0\n");
1522 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1523 MLX4_COMM_TIME))
1524 goto err;
1525 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1526 MLX4_COMM_TIME))
1527 goto err;
1528 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1529 MLX4_COMM_TIME))
1530 goto err;
1531 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1532 goto err;
f3d4c89e
RD		 1533
1534 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1535 return 0;
1536
1537err:
1538 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1539 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1540 return -EIO;
225c7b1f
RD		 1541}
1542
6634961c
JM		 1543static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1544{
1545 int i;
1546
1547 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1548 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1549 dev->caps.gid_table_len[i] =
449fc488 1550 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1551 else
1552 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1553 dev->caps.pkey_table_len[i] =
1554 dev->phys_caps.pkey_phys_table_len[i] - 1;
1555 }
1556}
1557
3c439b55
JM		 1558static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1559{
1560 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1561
1562 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1563 i++) {
1564 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1565 break;
1566 }
1567
1568 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1569}
1570
7b8157be
JM		 1571static void choose_steering_mode(struct mlx4_dev *dev,
1572 struct mlx4_dev_cap *dev_cap)
1573{
3c439b55
JM		 1574 if (mlx4_log_num_mgm_entry_size == -1 &&
1575 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1576 (!mlx4_is_mfunc(dev) ||
449fc488 1577 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) &&
3c439b55
JM		 1578 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1579 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1580 dev->oper_log_mgm_entry_size =
1581 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1582 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1583 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1584 dev->caps.fs_log_max_ucast_qp_range_size =
1585 dev_cap->fs_log_max_ucast_qp_range_size;
1586 } else {
1587 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1588 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1589 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1590 else {
1591 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1592
1593 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1594 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 1595 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 1596 }
3c439b55
JM		 1597 dev->oper_log_mgm_entry_size =
1598 mlx4_log_num_mgm_entry_size > 0 ?
1599 mlx4_log_num_mgm_entry_size :
1600 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1601 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1602 }
1a91de28 1603 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 1604 mlx4_steering_mode_str(dev->caps.steering_mode),
1605 dev->oper_log_mgm_entry_size,
1606 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1607}
1608
7ffdf726
OG		 1609static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1610 struct mlx4_dev_cap *dev_cap)
1611{
1612 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1613 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1614 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1615 else
1616 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1617
1618 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1619 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1620}
1621
3d73c288 1622static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1623{
1624 struct mlx4_priv *priv = mlx4_priv(dev);
1625 struct mlx4_adapter adapter;
1626 struct mlx4_dev_cap dev_cap;
2d928651 1627 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1628 struct mlx4_profile profile;
1629 struct mlx4_init_hca_param init_hca;
1630 u64 icm_size;
1631 int err;
f8c6455b 1632 struct mlx4_config_dev_params params;
225c7b1f 1633
ab9c17a0
JM		 1634 if (!mlx4_is_slave(dev)) {
1635 err = mlx4_QUERY_FW(dev);
1636 if (err) {
1637 if (err == -EACCES)
1a91de28 1638 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 1639 else
1a91de28 1640 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 1641 return err;
ab9c17a0 1642 }
225c7b1f 1643
ab9c17a0
JM		 1644 err = mlx4_load_fw(dev);
1645 if (err) {
1a91de28 1646 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 1647 return err;
ab9c17a0 1648 }
225c7b1f 1649
ab9c17a0
JM		 1650 mlx4_cfg.log_pg_sz_m = 1;
1651 mlx4_cfg.log_pg_sz = 0;
1652 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1653 if (err)
1654 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1655
ab9c17a0
JM		 1656 err = mlx4_dev_cap(dev, &dev_cap);
1657 if (err) {
1a91de28 1658 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 1659 goto err_stop_fw;
1660 }
225c7b1f 1661
7b8157be 1662 choose_steering_mode(dev, &dev_cap);
7ffdf726 1663 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1664
8e1a28e8
HHZ		 1665 err = mlx4_get_phys_port_id(dev);
1666 if (err)
1667 mlx4_err(dev, "Fail to get physical port id\n");
1668
6634961c
JM		 1669 if (mlx4_is_master(dev))
1670 mlx4_parav_master_pf_caps(dev);
1671
2599d858
AV		 1672 if (mlx4_low_memory_profile()) {
1673 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
1674 profile = low_mem_profile;
1675 } else {
1676 profile = default_profile;
1677 }
0ff1fb65
HHZ		 1678 if (dev->caps.steering_mode ==
1679 MLX4_STEERING_MODE_DEVICE_MANAGED)
1680 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1681
ab9c17a0
JM		 1682 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1683 &init_hca);
1684 if ((long long) icm_size < 0) {
1685 err = icm_size;
1686 goto err_stop_fw;
1687 }
225c7b1f 1688
a5bbe892
EC		 1689 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1690
ab9c17a0
JM		 1691 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1692 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1693 init_hca.mw_enabled = 0;
1694 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1695 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1696 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1697
ab9c17a0
JM		 1698 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1699 if (err)
1700 goto err_stop_fw;
225c7b1f 1701
ab9c17a0
JM		 1702 err = mlx4_INIT_HCA(dev, &init_hca);
1703 if (err) {
1a91de28 1704 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 1705 goto err_free_icm;
1706 }
ddd8a6c1
EE		 1707 /*
1708 * If TS is supported by FW
1709 * read HCA frequency by QUERY_HCA command
1710 */
1711 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1712 memset(&init_hca, 0, sizeof(init_hca));
1713 err = mlx4_QUERY_HCA(dev, &init_hca);
1714 if (err) {
1a91de28 1715 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 1716 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1717 } else {
1718 dev->caps.hca_core_clock =
1719 init_hca.hca_core_clock;
1720 }
1721
1722 /* In case we got HCA frequency 0 - disable timestamping
1723 * to avoid dividing by zero
1724 */
1725 if (!dev->caps.hca_core_clock) {
1726 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1727 mlx4_err(dev,
1a91de28 1728 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 1729 } else if (map_internal_clock(dev)) {
1730 /*
1731 * Map internal clock,
1732 * in case of failure disable timestamping
1733 */
1734 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1735 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 1736 }
1737 }
ab9c17a0
JM		 1738 } else {
1739 err = mlx4_init_slave(dev);
1740 if (err) {
5efe5355
JM		 1741 if (err != -EPROBE_DEFER)
1742 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1743 return err;
ab9c17a0 1744 }
225c7b1f 1745
ab9c17a0
JM		 1746 err = mlx4_slave_cap(dev);
1747 if (err) {
1748 mlx4_err(dev, "Failed to obtain slave caps\n");
1749 goto err_close;
1750 }
225c7b1f
RD		 1751 }
1752
ab9c17a0
JM		 1753 if (map_bf_area(dev))
1754 mlx4_dbg(dev, "Failed to map blue flame area\n");
1755
1756 /*Only the master set the ports, all the rest got it from it.*/
1757 if (!mlx4_is_slave(dev))
1758 mlx4_set_port_mask(dev);
1759
225c7b1f
RD		 1760 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1761 if (err) {
1a91de28 1762 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 1763 goto unmap_bf;
225c7b1f
RD		 1764 }
1765
f8c6455b
SM		 1766 /* Query CONFIG_DEV parameters */
1767 err = mlx4_config_dev_retrieval(dev, &params);
1768 if (err && err != -ENOTSUPP) {
1769 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
1770 } else if (!err) {
1771 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
1772 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
1773 }
225c7b1f 1774 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1775 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1776
1777 return 0;
1778
bef772eb 1779unmap_bf:
ddd8a6c1 1780 unmap_internal_clock(dev);
bef772eb
AY		 1781 unmap_bf_area(dev);
1782
b38f2879 1783 if (mlx4_is_slave(dev)) {
99ec41d0 1784 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 1785 kfree(dev->caps.qp0_tunnel);
1786 kfree(dev->caps.qp0_proxy);
1787 kfree(dev->caps.qp1_tunnel);
1788 kfree(dev->caps.qp1_proxy);
1789 }
1790
225c7b1f 1791err_close:
41929ed2
DB		 1792 if (mlx4_is_slave(dev))
1793 mlx4_slave_exit(dev);
1794 else
1795 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 1796
1797err_free_icm:
ab9c17a0
JM		 1798 if (!mlx4_is_slave(dev))
1799 mlx4_free_icms(dev);
225c7b1f
RD		 1800
1801err_stop_fw:
ab9c17a0
JM		 1802 if (!mlx4_is_slave(dev)) {
1803 mlx4_UNMAP_FA(dev);
1804 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1805 }
225c7b1f
RD		 1806 return err;
1807}
1808
f2a3f6a3
OG		 1809static int mlx4_init_counters_table(struct mlx4_dev *dev)
1810{
1811 struct mlx4_priv *priv = mlx4_priv(dev);
1812 int nent;
1813
1814 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1815 return -ENOENT;
1816
1817 nent = dev->caps.max_counters;
1818 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1819}
1820
1821static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1822{
1823 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1824}
1825
ba062d52 1826int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1827{
1828 struct mlx4_priv *priv = mlx4_priv(dev);
1829
1830 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1831 return -ENOENT;
1832
1833 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1834 if (*idx == -1)
1835 return -ENOMEM;
1836
1837 return 0;
1838}
ba062d52
JM		 1839
1840int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1841{
1842 u64 out_param;
1843 int err;
1844
1845 if (mlx4_is_mfunc(dev)) {
1846 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1847 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1848 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1849 if (!err)
1850 *idx = get_param_l(&out_param);
1851
1852 return err;
1853 }
1854 return __mlx4_counter_alloc(dev, idx);
1855}
f2a3f6a3
OG		 1856EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1857
ba062d52 1858void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 1859{
7c6d74d2 1860 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 1861 return;
1862}
ba062d52
JM		 1863
1864void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1865{
e7dbeba8 1866 u64 in_param = 0;
ba062d52
JM		 1867
1868 if (mlx4_is_mfunc(dev)) {
1869 set_param_l(&in_param, idx);
1870 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1871 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1872 MLX4_CMD_WRAPPED);
1873 return;
1874 }
1875 __mlx4_counter_free(dev, idx);
1876}
f2a3f6a3
OG		 1877EXPORT_SYMBOL_GPL(mlx4_counter_free);
1878
3d73c288 1879static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1880{
1881 struct mlx4_priv *priv = mlx4_priv(dev);
1882 int err;
7ff93f8b 1883 int port;
9a5aa622 1884 __be32 ib_port_default_caps;
225c7b1f 1885
225c7b1f
RD		 1886 err = mlx4_init_uar_table(dev);
1887 if (err) {
1a91de28
JP		 1888 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
1889 return err;
225c7b1f
RD		 1890 }
1891
1892 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1893 if (err) {
1a91de28 1894 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 1895 goto err_uar_table_free;
1896 }
1897
4979d18f 1898 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 1899 if (!priv->kar) {
1a91de28 1900 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 1901 err = -ENOMEM;
1902 goto err_uar_free;
1903 }
1904
1905 err = mlx4_init_pd_table(dev);
1906 if (err) {
1a91de28 1907 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 1908 goto err_kar_unmap;
1909 }
1910
012a8ff5
SH		 1911 err = mlx4_init_xrcd_table(dev);
1912 if (err) {
1a91de28 1913 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 1914 goto err_pd_table_free;
1915 }
1916
225c7b1f
RD		 1917 err = mlx4_init_mr_table(dev);
1918 if (err) {
1a91de28 1919 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 1920 goto err_xrcd_table_free;
225c7b1f
RD		 1921 }
1922
fe6f700d
YP		 1923 if (!mlx4_is_slave(dev)) {
1924 err = mlx4_init_mcg_table(dev);
1925 if (err) {
1a91de28 1926 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 1927 goto err_mr_table_free;
1928 }
114840c3
JM		 1929 err = mlx4_config_mad_demux(dev);
1930 if (err) {
1931 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
1932 goto err_mcg_table_free;
1933 }
fe6f700d
YP		 1934 }
1935
225c7b1f
RD		 1936 err = mlx4_init_eq_table(dev);
1937 if (err) {
1a91de28 1938 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 1939 goto err_mcg_table_free;
225c7b1f
RD		 1940 }
1941
1942 err = mlx4_cmd_use_events(dev);
1943 if (err) {
1a91de28 1944 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 1945 goto err_eq_table_free;
1946 }
1947
1948 err = mlx4_NOP(dev);
1949 if (err) {
08fb1055 1950 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 1951 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
b8dd786f 1952 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1a91de28 1953 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 1954 } else {
1a91de28 1955 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
b8dd786f 1956 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1957 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1958 }
225c7b1f
RD		 1959
1960 goto err_cmd_poll;
1961 }
1962
1963 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1964
1965 err = mlx4_init_cq_table(dev);
1966 if (err) {
1a91de28 1967 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 1968 goto err_cmd_poll;
1969 }
1970
1971 err = mlx4_init_srq_table(dev);
1972 if (err) {
1a91de28 1973 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 1974 goto err_cq_table_free;
1975 }
1976
1977 err = mlx4_init_qp_table(dev);
1978 if (err) {
1a91de28 1979 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 1980 goto err_srq_table_free;
1981 }
1982
f2a3f6a3
OG		 1983 err = mlx4_init_counters_table(dev);
1984 if (err && err != -ENOENT) {
1a91de28 1985 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
fe6f700d 1986 goto err_qp_table_free;
f2a3f6a3
OG		 1987 }
1988
ab9c17a0
JM		 1989 if (!mlx4_is_slave(dev)) {
1990 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1991 ib_port_default_caps = 0;
1992 err = mlx4_get_port_ib_caps(dev, port,
1993 &ib_port_default_caps);
1994 if (err)
1a91de28
JP		 1995 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
1996 port, err);
ab9c17a0
JM		 1997 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1998
2aca1172
JM		 1999 /* initialize per-slave default ib port capabilities */
2000 if (mlx4_is_master(dev)) {
2001 int i;
2002 for (i = 0; i < dev->num_slaves; i++) {
2003 if (i == mlx4_master_func_num(dev))
2004 continue;
2005 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2006 ib_port_default_caps;
2aca1172
JM		 2007 }
2008 }
2009
096335b3
OG		 2010 if (mlx4_is_mfunc(dev))
2011 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2012 else
2013 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2014
6634961c
JM		 2015 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2016 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2017 if (err) {
2018 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2019 port);
ab9c17a0
JM		 2020 goto err_counters_table_free;
2021 }
7ff93f8b
YP		 2022 }
2023 }
2024
225c7b1f
RD		 2025 return 0;
2026
f2a3f6a3
OG		 2027err_counters_table_free:
2028 mlx4_cleanup_counters_table(dev);
2029
225c7b1f
RD		 2030err_qp_table_free:
2031 mlx4_cleanup_qp_table(dev);
2032
2033err_srq_table_free:
2034 mlx4_cleanup_srq_table(dev);
2035
2036err_cq_table_free:
2037 mlx4_cleanup_cq_table(dev);
2038
2039err_cmd_poll:
2040 mlx4_cmd_use_polling(dev);
2041
2042err_eq_table_free:
2043 mlx4_cleanup_eq_table(dev);
2044
fe6f700d
YP		 2045err_mcg_table_free:
2046 if (!mlx4_is_slave(dev))
2047 mlx4_cleanup_mcg_table(dev);
2048
ee49bd93 2049err_mr_table_free:
225c7b1f
RD		 2050 mlx4_cleanup_mr_table(dev);
2051
012a8ff5
SH		 2052err_xrcd_table_free:
2053 mlx4_cleanup_xrcd_table(dev);
2054
225c7b1f
RD		 2055err_pd_table_free:
2056 mlx4_cleanup_pd_table(dev);
2057
2058err_kar_unmap:
2059 iounmap(priv->kar);
2060
2061err_uar_free:
2062 mlx4_uar_free(dev, &priv->driver_uar);
2063
2064err_uar_table_free:
2065 mlx4_cleanup_uar_table(dev);
2066 return err;
2067}
2068
e8f9b2ed 2069static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2070{
2071 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2072 struct msix_entry *entries;
0b7ca5a9 2073 int nreq = min_t(int, dev->caps.num_ports *
bb2146bc 2074 min_t(int, num_online_cpus() + 1,
90b1ebe7 2075 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 2076 int i;
2077
2078 if (msi_x) {
ca4c7b35
OG		 2079 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2080 nreq);
ab9c17a0 2081
b8dd786f
YP		 2082 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2083 if (!entries)
2084 goto no_msi;
2085
2086 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2087 entries[i].entry = i;
2088
66e2f9c1
AG		 2089 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
2090
2091 if (nreq < 0) {
5bf0da7d 2092 kfree(entries);
225c7b1f 2093 goto no_msi;
66e2f9c1 2094 } else if (nreq < MSIX_LEGACY_SZ +
1a91de28 2095 dev->caps.num_ports * MIN_MSIX_P_PORT) {
0b7ca5a9
YP		 2096 /*Working in legacy mode , all EQ's shared*/
2097 dev->caps.comp_pool = 0;
2098 dev->caps.num_comp_vectors = nreq - 1;
2099 } else {
2100 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2101 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2102 }
b8dd786f 2103 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2104 priv->eq_table.eq[i].irq = entries[i].vector;
2105
2106 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2107
2108 kfree(entries);
225c7b1f
RD		 2109 return;
2110 }
2111
2112no_msi:
b8dd786f 2113 dev->caps.num_comp_vectors = 1;
0b7ca5a9 2114 dev->caps.comp_pool = 0;
b8dd786f
YP		 2115
2116 for (i = 0; i < 2; ++i)
225c7b1f
RD		 2117 priv->eq_table.eq[i].irq = dev->pdev->irq;
2118}
2119
7ff93f8b 2120static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2121{
2122 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2123 int err = 0;
2a2336f8
YP		 2124
2125 info->dev = dev;
2126 info->port = port;
ab9c17a0 2127 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2128 mlx4_init_mac_table(dev, &info->mac_table);
2129 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2130 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2131 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2132 }
7ff93f8b
YP		 2133
2134 sprintf(info->dev_name, "mlx4_port%d", port);
2135 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2136 if (mlx4_is_mfunc(dev))
2137 info->port_attr.attr.mode = S_IRUGO;
2138 else {
2139 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2140 info->port_attr.store = set_port_type;
2141 }
7ff93f8b 2142 info->port_attr.show = show_port_type;
3691c964 2143 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 2144
2145 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2146 if (err) {
2147 mlx4_err(dev, "Failed to create file for port %d\n", port);
2148 info->port = -1;
2149 }
2150
096335b3
OG		 2151 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2152 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2153 if (mlx4_is_mfunc(dev))
2154 info->port_mtu_attr.attr.mode = S_IRUGO;
2155 else {
2156 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2157 info->port_mtu_attr.store = set_port_ib_mtu;
2158 }
2159 info->port_mtu_attr.show = show_port_ib_mtu;
2160 sysfs_attr_init(&info->port_mtu_attr.attr);
2161
2162 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2163 if (err) {
2164 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2165 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2166 info->port = -1;
2167 }
2168
7ff93f8b
YP		 2169 return err;
2170}
2171
2172static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2173{
2174 if (info->port < 0)
2175 return;
2176
2177 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 2178 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 2179}
2180
b12d93d6
YP		 2181static int mlx4_init_steering(struct mlx4_dev *dev)
2182{
2183 struct mlx4_priv *priv = mlx4_priv(dev);
2184 int num_entries = dev->caps.num_ports;
2185 int i, j;
2186
2187 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2188 if (!priv->steer)
2189 return -ENOMEM;
2190
45b51365 2191 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2192 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2193 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2194 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2195 }
b12d93d6
YP		 2196 return 0;
2197}
2198
2199static void mlx4_clear_steering(struct mlx4_dev *dev)
2200{
2201 struct mlx4_priv *priv = mlx4_priv(dev);
2202 struct mlx4_steer_index *entry, *tmp_entry;
2203 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2204 int num_entries = dev->caps.num_ports;
2205 int i, j;
2206
2207 for (i = 0; i < num_entries; i++) {
2208 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2209 list_for_each_entry_safe(pqp, tmp_pqp,
2210 &priv->steer[i].promisc_qps[j],
2211 list) {
2212 list_del(&pqp->list);
2213 kfree(pqp);
2214 }
2215 list_for_each_entry_safe(entry, tmp_entry,
2216 &priv->steer[i].steer_entries[j],
2217 list) {
2218 list_del(&entry->list);
2219 list_for_each_entry_safe(pqp, tmp_pqp,
2220 &entry->duplicates,
2221 list) {
2222 list_del(&pqp->list);
2223 kfree(pqp);
2224 }
2225 kfree(entry);
2226 }
2227 }
2228 }
2229 kfree(priv->steer);
2230}
2231
ab9c17a0
JM		 2232static int extended_func_num(struct pci_dev *pdev)
2233{
2234 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2235}
2236
2237#define MLX4_OWNER_BASE 0x8069c
2238#define MLX4_OWNER_SIZE 4
2239
2240static int mlx4_get_ownership(struct mlx4_dev *dev)
2241{
2242 void __iomem *owner;
2243 u32 ret;
2244
57dbf29a
KSS		 2245 if (pci_channel_offline(dev->pdev))
2246 return -EIO;
2247
ab9c17a0
JM		 2248 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2249 MLX4_OWNER_SIZE);
2250 if (!owner) {
2251 mlx4_err(dev, "Failed to obtain ownership bit\n");
2252 return -ENOMEM;
2253 }
2254
2255 ret = readl(owner);
2256 iounmap(owner);
2257 return (int) !!ret;
2258}
2259
2260static void mlx4_free_ownership(struct mlx4_dev *dev)
2261{
2262 void __iomem *owner;
2263
57dbf29a
KSS		 2264 if (pci_channel_offline(dev->pdev))
2265 return;
2266
ab9c17a0
JM		 2267 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2268 MLX4_OWNER_SIZE);
2269 if (!owner) {
2270 mlx4_err(dev, "Failed to obtain ownership bit\n");
2271 return;
2272 }
2273 writel(0, owner);
2274 msleep(1000);
2275 iounmap(owner);
2276}
2277
e1c00e10
MD		 2278static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
2279 int total_vfs, int *nvfs, struct mlx4_priv *priv)
225c7b1f 2280{
225c7b1f 2281 struct mlx4_dev *dev;
e1c00e10 2282 unsigned sum = 0;
225c7b1f 2283 int err;
2a2336f8 2284 int port;
e1c00e10 2285 int i;
bbb07af4 2286 int existing_vfs = 0;
225c7b1f 2287
e1c00e10 2288 dev = &priv->dev;
225c7b1f 2289
b581401e
RD		 2290 INIT_LIST_HEAD(&priv->ctx_list);
2291 spin_lock_init(&priv->ctx_lock);
225c7b1f 2292
7ff93f8b
YP		 2293 mutex_init(&priv->port_mutex);
2294
6296883c
YP		 2295 INIT_LIST_HEAD(&priv->pgdir_list);
2296 mutex_init(&priv->pgdir_mutex);
2297
c1b43dca
EC		 2298 INIT_LIST_HEAD(&priv->bf_list);
2299 mutex_init(&priv->bf_mutex);
2300
aca7a3ac 2301 dev->rev_id = pdev->revision;
6e7136ed 2302 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 2303
ab9c17a0 2304 /* Detect if this device is a virtual function */
839f1243 2305 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2306 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2307 dev->flags |= MLX4_FLAG_SLAVE;
2308 } else {
2309 /* We reset the device and enable SRIOV only for physical
2310 * devices. Try to claim ownership on the device;
2311 * if already taken, skip -- do not allow multiple PFs */
2312 err = mlx4_get_ownership(dev);
2313 if (err) {
2314 if (err < 0)
e1c00e10 2315 return err;
ab9c17a0 2316 else {
1a91de28 2317 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 2318 return -EINVAL;
ab9c17a0
JM		 2319 }
2320 }
aca7a3ac 2321
1ab95d37
MB		 2322 if (total_vfs) {
2323 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n",
2324 total_vfs);
2325 dev->dev_vfs = kzalloc(
1a91de28
JP		 2326 total_vfs * sizeof(*dev->dev_vfs),
2327 GFP_KERNEL);
1ab95d37
MB		 2328 if (NULL == dev->dev_vfs) {
2329 mlx4_err(dev, "Failed to allocate memory for VFs\n");
e1c00e10
MD		 2330 err = -ENOMEM;
2331 goto err_free_own;
ab9c17a0 2332 } else {
1ab95d37 2333 atomic_inc(&pf_loading);
bbb07af4
JM		 2334 existing_vfs = pci_num_vf(pdev);
2335 if (existing_vfs) {
2336 err = 0;
2337 if (existing_vfs != total_vfs)
2338 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2339 existing_vfs, total_vfs);
2340 } else {
2341 err = pci_enable_sriov(pdev, total_vfs);
2342 }
1ab95d37 2343 if (err) {
1a91de28 2344 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
1ab95d37 2345 err);
e1a5ddc5 2346 atomic_dec(&pf_loading);
1ab95d37
MB		 2347 } else {
2348 mlx4_warn(dev, "Running in master mode\n");
2349 dev->flags |= MLX4_FLAG_SRIOV |
1a91de28 2350 MLX4_FLAG_MASTER;
1ab95d37 2351 dev->num_vfs = total_vfs;
1ab95d37 2352 }
ab9c17a0
JM		 2353 }
2354 }
2355
fe6f700d
YP		 2356 atomic_set(&priv->opreq_count, 0);
2357 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2358
ab9c17a0
JM		 2359 /*
2360 * Now reset the HCA before we touch the PCI capabilities or
2361 * attempt a firmware command, since a boot ROM may have left
2362 * the HCA in an undefined state.
2363 */
2364 err = mlx4_reset(dev);
2365 if (err) {
1a91de28 2366 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 2367 goto err_sriov;
ab9c17a0 2368 }
225c7b1f
RD		 2369 }
2370
ab9c17a0 2371slave_start:
521130d1
EE		 2372 err = mlx4_cmd_init(dev);
2373 if (err) {
1a91de28 2374 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 2375 goto err_sriov;
2376 }
2377
2378 /* In slave functions, the communication channel must be initialized
2379 * before posting commands. Also, init num_slaves before calling
2380 * mlx4_init_hca */
2381 if (mlx4_is_mfunc(dev)) {
2382 if (mlx4_is_master(dev))
2383 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2384 else {
2385 dev->num_slaves = 0;
f356fcbe
JM		 2386 err = mlx4_multi_func_init(dev);
2387 if (err) {
1a91de28 2388 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 2389 goto err_cmd;
2390 }
2391 }
225c7b1f
RD		 2392 }
2393
2394 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2395 if (err) {
2396 if (err == -EACCES) {
2397 /* Not primary Physical function
2398 * Running in slave mode */
ffc39f6d 2399 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
ab9c17a0
JM		 2400 dev->flags |= MLX4_FLAG_SLAVE;
2401 dev->flags &= ~MLX4_FLAG_MASTER;
2402 goto slave_start;
2403 } else
2404 goto err_mfunc;
2405 }
2406
b912b2f8
EP		 2407 /* check if the device is functioning at its maximum possible speed.
2408 * No return code for this call, just warn the user in case of PCI
2409 * express device capabilities are under-satisfied by the bus.
2410 */
83d3459a
EP		 2411 if (!mlx4_is_slave(dev))
2412 mlx4_check_pcie_caps(dev);
b912b2f8 2413
ab9c17a0
JM		 2414 /* In master functions, the communication channel must be initialized
2415 * after obtaining its address from fw */
2416 if (mlx4_is_master(dev)) {
e1c00e10
MD		 2417 int ib_ports = 0;
2418
2419 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2420 ib_ports++;
2421
2422 if (ib_ports &&
2423 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2424 mlx4_err(dev,
2425 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2426 err = -EINVAL;
2427 goto err_close;
2428 }
2429 if (dev->caps.num_ports < 2 &&
2430 num_vfs_argc > 1) {
2431 err = -EINVAL;
2432 mlx4_err(dev,
2433 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2434 dev->caps.num_ports);
ab9c17a0
JM		 2435 goto err_close;
2436 }
e1c00e10 2437 memcpy(dev->nvfs, nvfs, sizeof(dev->nvfs));
dd41cc3b 2438
e1c00e10
MD		 2439 for (i = 0; i < sizeof(dev->nvfs)/sizeof(dev->nvfs[0]); i++) {
2440 unsigned j;
2441
2442 for (j = 0; j < dev->nvfs[i]; ++sum, ++j) {
2443 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
2444 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2445 dev->caps.num_ports;
1ab95d37
MB		 2446 }
2447 }
e1c00e10
MD		 2448
2449 /* In master functions, the communication channel
2450 * must be initialized after obtaining its address from fw
2451 */
2452 err = mlx4_multi_func_init(dev);
2453 if (err) {
2454 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
2455 goto err_close;
2456 }
ab9c17a0 2457 }
225c7b1f 2458
b8dd786f
YP		 2459 err = mlx4_alloc_eq_table(dev);
2460 if (err)
ab9c17a0 2461 goto err_master_mfunc;
b8dd786f 2462
0b7ca5a9 2463 priv->msix_ctl.pool_bm = 0;
730c41d5 2464 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2465
08fb1055 2466 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2467 if ((mlx4_is_mfunc(dev)) &&
2468 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2469 err = -ENOSYS;
1a91de28 2470 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 2471 goto err_free_eq;
ab9c17a0
JM		 2472 }
2473
2474 if (!mlx4_is_slave(dev)) {
2475 err = mlx4_init_steering(dev);
2476 if (err)
e1c00e10 2477 goto err_disable_msix;
ab9c17a0 2478 }
b12d93d6 2479
225c7b1f 2480 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2481 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2482 !mlx4_is_mfunc(dev)) {
08fb1055 2483 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2484 dev->caps.num_comp_vectors = 1;
2485 dev->caps.comp_pool = 0;
08fb1055
MT		 2486 pci_disable_msix(pdev);
2487 err = mlx4_setup_hca(dev);
2488 }
2489
225c7b1f 2490 if (err)
b12d93d6 2491 goto err_steer;
225c7b1f 2492
5a0d0a61
JM		 2493 mlx4_init_quotas(dev);
2494
7ff93f8b
YP		 2495 for (port = 1; port <= dev->caps.num_ports; port++) {
2496 err = mlx4_init_port_info(dev, port);
2497 if (err)
2498 goto err_port;
2499 }
2a2336f8 2500
225c7b1f
RD		 2501 err = mlx4_register_device(dev);
2502 if (err)
7ff93f8b 2503 goto err_port;
225c7b1f 2504
b046ffe5
EP		 2505 mlx4_request_modules(dev);
2506
27bf91d6
YP		 2507 mlx4_sense_init(dev);
2508 mlx4_start_sense(dev);
2509
befdf897 2510 priv->removed = 0;
225c7b1f 2511
e1a5ddc5
AV		 2512 if (mlx4_is_master(dev) && dev->num_vfs)
2513 atomic_dec(&pf_loading);
2514
225c7b1f
RD		 2515 return 0;
2516
7ff93f8b 2517err_port:
b4f77264 2518 for (--port; port >= 1; --port)
7ff93f8b
YP		 2519 mlx4_cleanup_port_info(&priv->port[port]);
2520
f2a3f6a3 2521 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2522 mlx4_cleanup_qp_table(dev);
2523 mlx4_cleanup_srq_table(dev);
2524 mlx4_cleanup_cq_table(dev);
2525 mlx4_cmd_use_polling(dev);
2526 mlx4_cleanup_eq_table(dev);
fe6f700d 2527 mlx4_cleanup_mcg_table(dev);
225c7b1f 2528 mlx4_cleanup_mr_table(dev);
012a8ff5 2529 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2530 mlx4_cleanup_pd_table(dev);
2531 mlx4_cleanup_uar_table(dev);
2532
b12d93d6 2533err_steer:
ab9c17a0
JM		 2534 if (!mlx4_is_slave(dev))
2535 mlx4_clear_steering(dev);
b12d93d6 2536
e1c00e10
MD		 2537err_disable_msix:
2538 if (dev->flags & MLX4_FLAG_MSI_X)
2539 pci_disable_msix(pdev);
2540
b8dd786f
YP		 2541err_free_eq:
2542 mlx4_free_eq_table(dev);
2543
ab9c17a0
JM		 2544err_master_mfunc:
2545 if (mlx4_is_master(dev))
2546 mlx4_multi_func_cleanup(dev);
2547
b38f2879 2548 if (mlx4_is_slave(dev)) {
99ec41d0 2549 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2550 kfree(dev->caps.qp0_tunnel);
2551 kfree(dev->caps.qp0_proxy);
2552 kfree(dev->caps.qp1_tunnel);
2553 kfree(dev->caps.qp1_proxy);
2554 }
2555
225c7b1f
RD		 2556err_close:
2557 mlx4_close_hca(dev);
2558
ab9c17a0
JM		 2559err_mfunc:
2560 if (mlx4_is_slave(dev))
2561 mlx4_multi_func_cleanup(dev);
2562
225c7b1f 2563err_cmd:
ffc39f6d 2564 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 2565
ab9c17a0 2566err_sriov:
bbb07af4 2567 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs)
ab9c17a0
JM		 2568 pci_disable_sriov(pdev);
2569
e1a5ddc5
AV		 2570 if (mlx4_is_master(dev) && dev->num_vfs)
2571 atomic_dec(&pf_loading);
2572
1ab95d37
MB		 2573 kfree(priv->dev.dev_vfs);
2574
e1c00e10
MD		 2575err_free_own:
2576 if (!mlx4_is_slave(dev))
2577 mlx4_free_ownership(dev);
2578
2579 return err;
2580}
2581
2582static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
2583 struct mlx4_priv *priv)
2584{
2585 int err;
2586 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2587 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2588 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2589 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2590 unsigned total_vfs = 0;
2591 unsigned int i;
2592
2593 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2594
2595 err = pci_enable_device(pdev);
2596 if (err) {
2597 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
2598 return err;
2599 }
2600
2601 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2602 * per port, we must limit the number of VFs to 63 (since their are
2603 * 128 MACs)
2604 */
2605 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2606 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2607 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
2608 if (nvfs[i] < 0) {
2609 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2610 err = -EINVAL;
2611 goto err_disable_pdev;
2612 }
2613 }
2614 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2615 i++) {
2616 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
2617 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2618 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2619 err = -EINVAL;
2620 goto err_disable_pdev;
2621 }
2622 }
2623 if (total_vfs >= MLX4_MAX_NUM_VF) {
2624 dev_err(&pdev->dev,
2625 "Requested more VF's (%d) than allowed (%d)\n",
2626 total_vfs, MLX4_MAX_NUM_VF - 1);
2627 err = -EINVAL;
2628 goto err_disable_pdev;
2629 }
2630
2631 for (i = 0; i < MLX4_MAX_PORTS; i++) {
2632 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2633 dev_err(&pdev->dev,
2634 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2635 nvfs[i] + nvfs[2], i + 1,
2636 MLX4_MAX_NUM_VF_P_PORT - 1);
2637 err = -EINVAL;
2638 goto err_disable_pdev;
2639 }
2640 }
2641
2642 /* Check for BARs. */
2643 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2644 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2645 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2646 pci_dev_data, pci_resource_flags(pdev, 0));
2647 err = -ENODEV;
2648 goto err_disable_pdev;
2649 }
2650 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2651 dev_err(&pdev->dev, "Missing UAR, aborting\n");
2652 err = -ENODEV;
2653 goto err_disable_pdev;
2654 }
2655
2656 err = pci_request_regions(pdev, DRV_NAME);
2657 if (err) {
2658 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2659 goto err_disable_pdev;
2660 }
2661
2662 pci_set_master(pdev);
2663
2664 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2665 if (err) {
2666 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
2667 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2668 if (err) {
2669 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
2670 goto err_release_regions;
2671 }
2672 }
2673 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2674 if (err) {
2675 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
2676 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2677 if (err) {
2678 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
2679 goto err_release_regions;
2680 }
2681 }
2682
2683 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2684 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2685 /* Detect if this device is a virtual function */
2686 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2687 /* When acting as pf, we normally skip vfs unless explicitly
2688 * requested to probe them.
2689 */
2690 if (total_vfs) {
2691 unsigned vfs_offset = 0;
2692
2693 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
2694 vfs_offset + nvfs[i] < extended_func_num(pdev);
2695 vfs_offset += nvfs[i], i++)
2696 ;
2697 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
2698 err = -ENODEV;
2699 goto err_release_regions;
2700 }
2701 if ((extended_func_num(pdev) - vfs_offset)
2702 > prb_vf[i]) {
2703 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
2704 extended_func_num(pdev));
2705 err = -ENODEV;
2706 goto err_release_regions;
2707 }
2708 }
2709 }
2710
2711 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
2712 if (err)
2713 goto err_release_regions;
2714 return 0;
225c7b1f 2715
a01df0fe
RD		 2716err_release_regions:
2717 pci_release_regions(pdev);
225c7b1f
RD		 2718
2719err_disable_pdev:
2720 pci_disable_device(pdev);
2721 pci_set_drvdata(pdev, NULL);
2722 return err;
2723}
2724
1dd06ae8 2725static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 2726{
befdf897
WY		 2727 struct mlx4_priv *priv;
2728 struct mlx4_dev *dev;
e1c00e10 2729 int ret;
befdf897 2730
0a645e80 2731 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2732
befdf897
WY		 2733 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2734 if (!priv)
2735 return -ENOMEM;
2736
2737 dev = &priv->dev;
e1c00e10 2738 dev->pdev = pdev;
befdf897
WY		 2739 pci_set_drvdata(pdev, dev);
2740 priv->pci_dev_data = id->driver_data;
2741
e1c00e10
MD		 2742 ret = __mlx4_init_one(pdev, id->driver_data, priv);
2743 if (ret)
2744 kfree(priv);
2745
2746 return ret;
3d73c288
RD		 2747}
2748
e1c00e10 2749static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f
RD		 2750{
2751 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2752 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 2753 int pci_dev_data;
225c7b1f 2754 int p;
bbb07af4 2755 int active_vfs = 0;
225c7b1f 2756
befdf897
WY		 2757 if (priv->removed)
2758 return;
225c7b1f 2759
befdf897 2760 pci_dev_data = priv->pci_dev_data;
225c7b1f 2761
bbb07af4
JM		 2762 /* Disabling SR-IOV is not allowed while there are active vf's */
2763 if (mlx4_is_master(dev)) {
2764 active_vfs = mlx4_how_many_lives_vf(dev);
2765 if (active_vfs) {
2766 pr_warn("Removing PF when there are active VF's !!\n");
2767 pr_warn("Will not disable SR-IOV.\n");
2768 }
2769 }
befdf897
WY		 2770 mlx4_stop_sense(dev);
2771 mlx4_unregister_device(dev);
225c7b1f 2772
befdf897
WY		 2773 for (p = 1; p <= dev->caps.num_ports; p++) {
2774 mlx4_cleanup_port_info(&priv->port[p]);
2775 mlx4_CLOSE_PORT(dev, p);
2776 }
2777
2778 if (mlx4_is_master(dev))
2779 mlx4_free_resource_tracker(dev,
2780 RES_TR_FREE_SLAVES_ONLY);
2781
2782 mlx4_cleanup_counters_table(dev);
2783 mlx4_cleanup_qp_table(dev);
2784 mlx4_cleanup_srq_table(dev);
2785 mlx4_cleanup_cq_table(dev);
2786 mlx4_cmd_use_polling(dev);
2787 mlx4_cleanup_eq_table(dev);
2788 mlx4_cleanup_mcg_table(dev);
2789 mlx4_cleanup_mr_table(dev);
2790 mlx4_cleanup_xrcd_table(dev);
2791 mlx4_cleanup_pd_table(dev);
225c7b1f 2792
befdf897
WY		 2793 if (mlx4_is_master(dev))
2794 mlx4_free_resource_tracker(dev,
2795 RES_TR_FREE_STRUCTS_ONLY);
47605df9 2796
befdf897
WY		 2797 iounmap(priv->kar);
2798 mlx4_uar_free(dev, &priv->driver_uar);
2799 mlx4_cleanup_uar_table(dev);
2800 if (!mlx4_is_slave(dev))
2801 mlx4_clear_steering(dev);
2802 mlx4_free_eq_table(dev);
2803 if (mlx4_is_master(dev))
2804 mlx4_multi_func_cleanup(dev);
2805 mlx4_close_hca(dev);
2806 if (mlx4_is_slave(dev))
2807 mlx4_multi_func_cleanup(dev);
ffc39f6d 2808 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 2809
befdf897
WY		 2810 if (dev->flags & MLX4_FLAG_MSI_X)
2811 pci_disable_msix(pdev);
bbb07af4 2812 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
befdf897
WY		 2813 mlx4_warn(dev, "Disabling SR-IOV\n");
2814 pci_disable_sriov(pdev);
e1a5ddc5 2815 dev->num_vfs = 0;
225c7b1f 2816 }
befdf897
WY		 2817
2818 if (!mlx4_is_slave(dev))
2819 mlx4_free_ownership(dev);
2820
99ec41d0 2821 kfree(dev->caps.qp0_qkey);
befdf897
WY		 2822 kfree(dev->caps.qp0_tunnel);
2823 kfree(dev->caps.qp0_proxy);
2824 kfree(dev->caps.qp1_tunnel);
2825 kfree(dev->caps.qp1_proxy);
2826 kfree(dev->dev_vfs);
2827
befdf897
WY		 2828 memset(priv, 0, sizeof(*priv));
2829 priv->pci_dev_data = pci_dev_data;
2830 priv->removed = 1;
2831}
2832
2833static void mlx4_remove_one(struct pci_dev *pdev)
2834{
2835 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2836 struct mlx4_priv *priv = mlx4_priv(dev);
2837
e1c00e10
MD		 2838 mlx4_unload_one(pdev);
2839 pci_release_regions(pdev);
2840 pci_disable_device(pdev);
befdf897
WY		 2841 kfree(priv);
2842 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 2843}
2844
ee49bd93
JM		 2845int mlx4_restart_one(struct pci_dev *pdev)
2846{
839f1243
RD		 2847 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2848 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 2849 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2850 int pci_dev_data, err, total_vfs;
839f1243
RD		 2851
2852 pci_dev_data = priv->pci_dev_data;
e1c00e10
MD		 2853 total_vfs = dev->num_vfs;
2854 memcpy(nvfs, dev->nvfs, sizeof(dev->nvfs));
2855
2856 mlx4_unload_one(pdev);
2857 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
2858 if (err) {
2859 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
2860 __func__, pci_name(pdev), err);
2861 return err;
2862 }
2863
2864 return err;
ee49bd93
JM		 2865}
2866
9baa3c34 2867static const struct pci_device_id mlx4_pci_table[] = {
ab9c17a0 2868 /* MT25408 "Hermon" SDR */
ca3e57a5 2869 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2870 /* MT25408 "Hermon" DDR */
ca3e57a5 2871 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2872 /* MT25408 "Hermon" QDR */
ca3e57a5 2873 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2874 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 2875 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2876 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 2877 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2878 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 2879 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2880 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 2881 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2882 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 2883 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2884 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 2885 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2886 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 2887 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2888 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 2889 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2890 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 2891 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2892 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 2893 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2894 /* MT27500 Family [ConnectX-3] */
2895 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2896 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 2897 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2898 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2899 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2900 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2901 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2902 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2903 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2904 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2905 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2906 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2907 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2908 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2909 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2910 { 0, }
2911};
2912
2913MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2914
57dbf29a
KSS		 2915static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2916 pci_channel_state_t state)
2917{
e1c00e10 2918 mlx4_unload_one(pdev);
57dbf29a
KSS		 2919
2920 return state == pci_channel_io_perm_failure ?
2921 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2922}
2923
2924static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2925{
befdf897
WY		 2926 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2927 struct mlx4_priv *priv = mlx4_priv(dev);
2928 int ret;
97a5221f 2929
e1c00e10 2930 ret = __mlx4_init_one(pdev, priv->pci_dev_data, priv);
57dbf29a
KSS		 2931
2932 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2933}
2934
3646f0e5 2935static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 2936 .error_detected = mlx4_pci_err_detected,
2937 .slot_reset = mlx4_pci_slot_reset,
2938};
2939
225c7b1f
RD		 2940static struct pci_driver mlx4_driver = {
2941 .name = DRV_NAME,
2942 .id_table = mlx4_pci_table,
2943 .probe = mlx4_init_one,
e1c00e10 2944 .shutdown = mlx4_unload_one,
f57e6848 2945 .remove = mlx4_remove_one,
57dbf29a 2946 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 2947};
2948
7ff93f8b
YP		 2949static int __init mlx4_verify_params(void)
2950{
2951 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 2952 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2953 return -1;
2954 }
2955
cb29688a 2956 if (log_num_vlan != 0)
c20862c8
AV		 2957 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2958 MLX4_LOG_NUM_VLANS);
7ff93f8b 2959
ecc8fb11
AV		 2960 if (use_prio != 0)
2961 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 2962
0498628f 2963 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 2964 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
2965 log_mtts_per_seg);
ab6bf42e
EC		 2966 return -1;
2967 }
2968
ab9c17a0
JM		 2969 /* Check if module param for ports type has legal combination */
2970 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 2971 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 2972 port_type_array[0] = true;
2973 }
2974
3c439b55
JM		 2975 if (mlx4_log_num_mgm_entry_size != -1 &&
2976 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2977 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
1a91de28
JP		 2978 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n",
2979 mlx4_log_num_mgm_entry_size,
2980 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2981 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 2982 return -1;
2983 }
2984
7ff93f8b
YP		 2985 return 0;
2986}
2987
225c7b1f
RD		 2988static int __init mlx4_init(void)
2989{
2990 int ret;
2991
7ff93f8b
YP		 2992 if (mlx4_verify_params())
2993 return -EINVAL;
2994
27bf91d6
YP		 2995 mlx4_catas_init();
2996
2997 mlx4_wq = create_singlethread_workqueue("mlx4");
2998 if (!mlx4_wq)
2999 return -ENOMEM;
ee49bd93 3000
225c7b1f 3001 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 3002 if (ret < 0)
3003 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3004 return ret < 0 ? ret : 0;
3005}
3006
3007static void __exit mlx4_cleanup(void)
3008{
3009 pci_unregister_driver(&mlx4_driver);
27bf91d6 3010 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3011}
3012
3013module_init(mlx4_init);
3014module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)