projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
IB/mlx4: Initialize SR-IOV IB support for slaves in master context
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
90b1ebe7 44#include <linux/netdevice.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
ab9c17a0
JM		 80static int num_vfs;
81module_param(num_vfs, int, 0444);
82MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
83
84static int probe_vf;
85module_param(probe_vf, int, 0644);
86MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
87
0ec2c0f8
EE		 88int mlx4_log_num_mgm_entry_size = 10;
89module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
93 " 10 gives 248.range: 9<="
0ff1fb65
HHZ		 94 " log_num_mgm_entry_size <= 12."
95 " Not in use with device managed"
96 " flow steering");
0ec2c0f8 97
ab9c17a0
JM		 98#define MLX4_VF (1 << 0)
99
100#define HCA_GLOBAL_CAP_MASK 0
101#define PF_CONTEXT_BEHAVIOUR_MASK 0
102
f33afc26 103static char mlx4_version[] __devinitdata =
225c7b1f
RD		 104 DRV_NAME ": Mellanox ConnectX core driver v"
105 DRV_VERSION " (" DRV_RELDATE ")\n";
106
107static struct mlx4_profile default_profile = {
ab9c17a0 108 .num_qp = 1 << 18,
225c7b1f 109 .num_srq = 1 << 16,
c9f2ba5e 110 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 111 .num_cq = 1 << 16,
112 .num_mcg = 1 << 13,
ab9c17a0 113 .num_mpt = 1 << 19,
9fd7a1e1 114 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 115};
116
ab9c17a0 117static int log_num_mac = 7;
93fc9e1b
YP		 118module_param_named(log_num_mac, log_num_mac, int, 0444);
119MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
120
121static int log_num_vlan;
122module_param_named(log_num_vlan, log_num_vlan, int, 0444);
123MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 124/* Log2 max number of VLANs per ETH port (0-7) */
125#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 126
eb939922 127static bool use_prio;
93fc9e1b
YP		 128module_param_named(use_prio, use_prio, bool, 0444);
129MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
130 "(0/1, default 0)");
131
2b8fb286 132int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 133module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 134MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 135
8d0fc7b6 136static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 137static int arr_argc = 2;
138module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 139MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
140 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 141
142struct mlx4_port_config {
143 struct list_head list;
144 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
145 struct pci_dev *pdev;
146};
147
27bf91d6
YP		 148int mlx4_check_port_params(struct mlx4_dev *dev,
149 enum mlx4_port_type *port_type)
7ff93f8b
YP		 150{
151 int i;
152
153 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 154 if (port_type[i] != port_type[i + 1]) {
155 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
156 mlx4_err(dev, "Only same port types supported "
157 "on this HCA, aborting.\n");
158 return -EINVAL;
159 }
7ff93f8b
YP		 160 }
161 }
7ff93f8b
YP		 162
163 for (i = 0; i < dev->caps.num_ports; i++) {
164 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
165 mlx4_err(dev, "Requested port type for port %d is not "
166 "supported on this HCA\n", i + 1);
167 return -EINVAL;
168 }
169 }
170 return 0;
171}
172
173static void mlx4_set_port_mask(struct mlx4_dev *dev)
174{
175 int i;
176
7ff93f8b 177 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 178 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 179}
f2a3f6a3 180
3d73c288 181static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 182{
183 int err;
5ae2a7a8 184 int i;
225c7b1f
RD		 185
186 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
187 if (err) {
188 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
189 return err;
190 }
191
192 if (dev_cap->min_page_sz > PAGE_SIZE) {
193 mlx4_err(dev, "HCA minimum page size of %d bigger than "
194 "kernel PAGE_SIZE of %ld, aborting.\n",
195 dev_cap->min_page_sz, PAGE_SIZE);
196 return -ENODEV;
197 }
198 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
199 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
200 "aborting.\n",
201 dev_cap->num_ports, MLX4_MAX_PORTS);
202 return -ENODEV;
203 }
204
205 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
206 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
207 "PCI resource 2 size of 0x%llx, aborting.\n",
208 dev_cap->uar_size,
209 (unsigned long long) pci_resource_len(dev->pdev, 2));
210 return -ENODEV;
211 }
212
213 dev->caps.num_ports = dev_cap->num_ports;
3fc929e2 214 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
5ae2a7a8
RD		 215 for (i = 1; i <= dev->caps.num_ports; ++i) {
216 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 217 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
6634961c
JM		 218 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
219 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
220 /* set gid and pkey table operating lengths by default
221 * to non-sriov values */
5ae2a7a8
RD		 222 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
223 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
224 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 225 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
226 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 227 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 228 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
229 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 230 dev->caps.trans_type[i] = dev_cap->trans_type[i];
231 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
232 dev->caps.wavelength[i] = dev_cap->wavelength[i];
233 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 234 }
235
ab9c17a0 236 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 237 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 238 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
239 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
240 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
241 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
242 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
243 dev->caps.max_wqes = dev_cap->max_qp_sz;
244 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 245 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
246 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
247 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
248 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
249 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 250 /*
251 * Subtract 1 from the limit because we need to allocate a
252 * spare CQE so the HCA HW can tell the difference between an
253 * empty CQ and a full CQ.
254 */
255 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
256 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
257 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 258 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 259 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 260
261 /* The first 128 UARs are used for EQ doorbells */
262 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 263 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 264 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
265 dev_cap->reserved_xrcds : 0;
266 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
267 dev_cap->max_xrcds : 0;
2b8fb286
MA		 268 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
269
149983af 270 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 271 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
272 dev->caps.flags = dev_cap->flags;
b3416f44 273 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 274 dev->caps.bmme_flags = dev_cap->bmme_flags;
275 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 276 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 277 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 278 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 279
0ff1fb65
HHZ		 280 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
281 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
282 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
283 dev->caps.fs_log_max_ucast_qp_range_size =
284 dev_cap->fs_log_max_ucast_qp_range_size;
c96d97f4 285 } else {
0ff1fb65
HHZ		 286 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
287 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) {
288 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
289 } else {
290 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
c96d97f4 291
0ff1fb65
HHZ		 292 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
293 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
294 mlx4_warn(dev, "Must have UC_STEER and MC_STEER flags "
295 "set to use B0 steering. Falling back to A0 steering mode.\n");
296 }
297 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
c96d97f4
HHZ		 298 }
299 mlx4_dbg(dev, "Steering mode is: %s\n",
300 mlx4_steering_mode_str(dev->caps.steering_mode));
c96d97f4 301
58a60168
YP		 302 /* Sense port always allowed on supported devices for ConnectX1 and 2 */
303 if (dev->pdev->device != 0x1003)
304 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
305
93fc9e1b 306 dev->caps.log_num_macs = log_num_mac;
cb29688a 307 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 308 dev->caps.log_num_prios = use_prio ? 3 : 0;
309
310 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 311 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
312 if (dev->caps.supported_type[i]) {
313 /* if only ETH is supported - assign ETH */
314 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
315 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 316 /* if only IB is supported, assign IB */
ab9c17a0 317 else if (dev->caps.supported_type[i] ==
105c320f
JM		 318 MLX4_PORT_TYPE_IB)
319 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 320 else {
105c320f
JM		 321 /* if IB and ETH are supported, we set the port
322 * type according to user selection of port type;
323 * if user selected none, take the FW hint */
324 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 325 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
326 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 327 else
105c320f 328 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 329 }
330 }
8d0fc7b6
YP		 331 /*
332 * Link sensing is allowed on the port if 3 conditions are true:
333 * 1. Both protocols are supported on the port.
334 * 2. Different types are supported on the port
335 * 3. FW declared that it supports link sensing
336 */
27bf91d6 337 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 338 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 339 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 340 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 341
8d0fc7b6
YP		 342 /*
343 * If "default_sense" bit is set, we move the port to "AUTO" mode
344 * and perform sense_port FW command to try and set the correct
345 * port type from beginning
346 */
46c46747 347 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 348 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
349 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
350 mlx4_SENSE_PORT(dev, i, &sensed_port);
351 if (sensed_port != MLX4_PORT_TYPE_NONE)
352 dev->caps.port_type[i] = sensed_port;
353 } else {
354 dev->caps.possible_type[i] = dev->caps.port_type[i];
355 }
356
93fc9e1b
YP		 357 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
358 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
359 mlx4_warn(dev, "Requested number of MACs is too much "
360 "for port %d, reducing to %d.\n",
361 i, 1 << dev->caps.log_num_macs);
362 }
363 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
364 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
365 mlx4_warn(dev, "Requested number of VLANs is too much "
366 "for port %d, reducing to %d.\n",
367 i, 1 << dev->caps.log_num_vlans);
368 }
369 }
370
f2a3f6a3
OG		 371 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
372
93fc9e1b
YP		 373 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
374 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
375 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
376 (1 << dev->caps.log_num_macs) *
377 (1 << dev->caps.log_num_vlans) *
378 (1 << dev->caps.log_num_prios) *
379 dev->caps.num_ports;
380 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
381
382 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
383 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
384 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
385 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
386
e2c76824 387 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
225c7b1f
RD		 388 return 0;
389}
ab9c17a0
JM		 390/*The function checks if there are live vf, return the num of them*/
391static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
392{
393 struct mlx4_priv *priv = mlx4_priv(dev);
394 struct mlx4_slave_state *s_state;
395 int i;
396 int ret = 0;
397
398 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
399 s_state = &priv->mfunc.master.slave_state[i];
400 if (s_state->active && s_state->last_cmd !=
401 MLX4_COMM_CMD_RESET) {
402 mlx4_warn(dev, "%s: slave: %d is still active\n",
403 __func__, i);
404 ret++;
405 }
406 }
407 return ret;
408}
409
396f2feb
JM		 410int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
411{
412 u32 qk = MLX4_RESERVED_QKEY_BASE;
413 if (qpn >= dev->caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
414 qpn < dev->caps.sqp_start)
415 return -EINVAL;
416
417 if (qpn >= dev->caps.base_tunnel_sqpn)
418 /* tunnel qp */
419 qk += qpn - dev->caps.base_tunnel_sqpn;
420 else
421 qk += qpn - dev->caps.sqp_start;
422 *qkey = qk;
423 return 0;
424}
425EXPORT_SYMBOL(mlx4_get_parav_qkey);
426
e10903b0 427int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 428{
429 struct mlx4_priv *priv = mlx4_priv(dev);
430 struct mlx4_slave_state *s_slave;
431
432 if (!mlx4_is_master(dev))
433 return 0;
434
435 s_slave = &priv->mfunc.master.slave_state[slave];
436 return !!s_slave->active;
437}
438EXPORT_SYMBOL(mlx4_is_slave_active);
439
440static int mlx4_slave_cap(struct mlx4_dev *dev)
441{
442 int err;
443 u32 page_size;
444 struct mlx4_dev_cap dev_cap;
445 struct mlx4_func_cap func_cap;
446 struct mlx4_init_hca_param hca_param;
447 int i;
448
449 memset(&hca_param, 0, sizeof(hca_param));
450 err = mlx4_QUERY_HCA(dev, &hca_param);
451 if (err) {
452 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
453 return err;
454 }
455
456 /*fail if the hca has an unknown capability */
457 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
458 HCA_GLOBAL_CAP_MASK) {
459 mlx4_err(dev, "Unknown hca global capabilities\n");
460 return -ENOSYS;
461 }
462
463 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
464
465 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 466 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 467 err = mlx4_dev_cap(dev, &dev_cap);
468 if (err) {
469 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
470 return err;
471 }
472
b91cb3eb
JM		 473 err = mlx4_QUERY_FW(dev);
474 if (err)
475 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
476
ab9c17a0
JM		 477 page_size = ~dev->caps.page_size_cap + 1;
478 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
479 if (page_size > PAGE_SIZE) {
480 mlx4_err(dev, "HCA minimum page size of %d bigger than "
481 "kernel PAGE_SIZE of %ld, aborting.\n",
482 page_size, PAGE_SIZE);
483 return -ENODEV;
484 }
485
486 /* slave gets uar page size from QUERY_HCA fw command */
487 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
488
489 /* TODO: relax this assumption */
490 if (dev->caps.uar_page_size != PAGE_SIZE) {
491 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
492 dev->caps.uar_page_size, PAGE_SIZE);
493 return -ENODEV;
494 }
495
496 memset(&func_cap, 0, sizeof(func_cap));
497 err = mlx4_QUERY_FUNC_CAP(dev, &func_cap);
498 if (err) {
499 mlx4_err(dev, "QUERY_FUNC_CAP command failed, aborting.\n");
500 return err;
501 }
502
503 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
504 PF_CONTEXT_BEHAVIOUR_MASK) {
505 mlx4_err(dev, "Unknown pf context behaviour\n");
506 return -ENOSYS;
507 }
508
ab9c17a0
JM		 509 dev->caps.num_ports = func_cap.num_ports;
510 dev->caps.num_qps = func_cap.qp_quota;
511 dev->caps.num_srqs = func_cap.srq_quota;
512 dev->caps.num_cqs = func_cap.cq_quota;
513 dev->caps.num_eqs = func_cap.max_eq;
514 dev->caps.reserved_eqs = func_cap.reserved_eq;
515 dev->caps.num_mpts = func_cap.mpt_quota;
516 dev->caps.num_mtts = func_cap.mtt_quota;
517 dev->caps.num_pds = MLX4_NUM_PDS;
518 dev->caps.num_mgms = 0;
519 dev->caps.num_amgms = 0;
520
ab9c17a0
JM		 521 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
522 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
523 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
524 return -ENODEV;
525 }
526
6634961c 527 for (i = 1; i <= dev->caps.num_ports; ++i) {
6230bb23 528 dev->caps.port_mask[i] = dev->caps.port_type[i];
6634961c
JM		 529 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
530 &dev->caps.gid_table_len[i],
531 &dev->caps.pkey_table_len[i]))
532 return -ENODEV;
533 }
6230bb23 534
ab9c17a0
JM		 535 if (dev->caps.uar_page_size * (dev->caps.num_uars -
536 dev->caps.reserved_uars) >
537 pci_resource_len(dev->pdev, 2)) {
538 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
539 "PCI resource 2 size of 0x%llx, aborting.\n",
540 dev->caps.uar_page_size * dev->caps.num_uars,
541 (unsigned long long) pci_resource_len(dev->pdev, 2));
542 return -ENODEV;
543 }
544
e2c76824
JM		 545 /* Calculate our sqp_start */
546 dev->caps.sqp_start = func_cap.base_proxy_qpn;
547 dev->caps.base_tunnel_sqpn = func_cap.base_tunnel_qpn;
548
ab9c17a0
JM		 549 return 0;
550}
225c7b1f 551
7ff93f8b
YP		 552/*
553 * Change the port configuration of the device.
554 * Every user of this function must hold the port mutex.
555 */
27bf91d6
YP		 556int mlx4_change_port_types(struct mlx4_dev *dev,
557 enum mlx4_port_type *port_types)
7ff93f8b
YP		 558{
559 int err = 0;
560 int change = 0;
561 int port;
562
563 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 564 /* Change the port type only if the new type is different
565 * from the current, and not set to Auto */
3d8f9308 566 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 567 change = 1;
7ff93f8b
YP		 568 }
569 if (change) {
570 mlx4_unregister_device(dev);
571 for (port = 1; port <= dev->caps.num_ports; port++) {
572 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 573 dev->caps.port_type[port] = port_types[port - 1];
6634961c 574 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b
YP		 575 if (err) {
576 mlx4_err(dev, "Failed to set port %d, "
577 "aborting\n", port);
578 goto out;
579 }
580 }
581 mlx4_set_port_mask(dev);
582 err = mlx4_register_device(dev);
583 }
584
585out:
586 return err;
587}
588
589static ssize_t show_port_type(struct device *dev,
590 struct device_attribute *attr,
591 char *buf)
592{
593 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
594 port_attr);
595 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 596 char type[8];
597
598 sprintf(type, "%s",
599 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
600 "ib" : "eth");
601 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
602 sprintf(buf, "auto (%s)\n", type);
603 else
604 sprintf(buf, "%s\n", type);
7ff93f8b 605
27bf91d6 606 return strlen(buf);
7ff93f8b
YP		 607}
608
609static ssize_t set_port_type(struct device *dev,
610 struct device_attribute *attr,
611 const char *buf, size_t count)
612{
613 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
614 port_attr);
615 struct mlx4_dev *mdev = info->dev;
616 struct mlx4_priv *priv = mlx4_priv(mdev);
617 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 618 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 619 int i;
620 int err = 0;
621
622 if (!strcmp(buf, "ib\n"))
623 info->tmp_type = MLX4_PORT_TYPE_IB;
624 else if (!strcmp(buf, "eth\n"))
625 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 626 else if (!strcmp(buf, "auto\n"))
627 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 628 else {
629 mlx4_err(mdev, "%s is not supported port type\n", buf);
630 return -EINVAL;
631 }
632
27bf91d6 633 mlx4_stop_sense(mdev);
7ff93f8b 634 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 635 /* Possible type is always the one that was delivered */
636 mdev->caps.possible_type[info->port] = info->tmp_type;
637
638 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 639 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 640 mdev->caps.possible_type[i+1];
641 if (types[i] == MLX4_PORT_TYPE_AUTO)
642 types[i] = mdev->caps.port_type[i+1];
643 }
7ff93f8b 644
58a60168
YP		 645 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
646 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 647 for (i = 1; i <= mdev->caps.num_ports; i++) {
648 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
649 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
650 err = -EINVAL;
651 }
652 }
653 }
654 if (err) {
655 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
656 "Set only 'eth' or 'ib' for both ports "
657 "(should be the same)\n");
658 goto out;
659 }
660
661 mlx4_do_sense_ports(mdev, new_types, types);
662
663 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 664 if (err)
665 goto out;
666
27bf91d6
YP		 667 /* We are about to apply the changes after the configuration
668 * was verified, no need to remember the temporary types
669 * any more */
670 for (i = 0; i < mdev->caps.num_ports; i++)
671 priv->port[i + 1].tmp_type = 0;
7ff93f8b 672
27bf91d6 673 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 674
675out:
27bf91d6 676 mlx4_start_sense(mdev);
7ff93f8b
YP		 677 mutex_unlock(&priv->port_mutex);
678 return err ? err : count;
679}
680
096335b3
OG		 681enum ibta_mtu {
682 IB_MTU_256 = 1,
683 IB_MTU_512 = 2,
684 IB_MTU_1024 = 3,
685 IB_MTU_2048 = 4,
686 IB_MTU_4096 = 5
687};
688
689static inline int int_to_ibta_mtu(int mtu)
690{
691 switch (mtu) {
692 case 256: return IB_MTU_256;
693 case 512: return IB_MTU_512;
694 case 1024: return IB_MTU_1024;
695 case 2048: return IB_MTU_2048;
696 case 4096: return IB_MTU_4096;
697 default: return -1;
698 }
699}
700
701static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
702{
703 switch (mtu) {
704 case IB_MTU_256: return 256;
705 case IB_MTU_512: return 512;
706 case IB_MTU_1024: return 1024;
707 case IB_MTU_2048: return 2048;
708 case IB_MTU_4096: return 4096;
709 default: return -1;
710 }
711}
712
713static ssize_t show_port_ib_mtu(struct device *dev,
714 struct device_attribute *attr,
715 char *buf)
716{
717 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
718 port_mtu_attr);
719 struct mlx4_dev *mdev = info->dev;
720
721 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
722 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
723
724 sprintf(buf, "%d\n",
725 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
726 return strlen(buf);
727}
728
729static ssize_t set_port_ib_mtu(struct device *dev,
730 struct device_attribute *attr,
731 const char *buf, size_t count)
732{
733 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
734 port_mtu_attr);
735 struct mlx4_dev *mdev = info->dev;
736 struct mlx4_priv *priv = mlx4_priv(mdev);
737 int err, port, mtu, ibta_mtu = -1;
738
739 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
740 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
741 return -EINVAL;
742 }
743
744 err = sscanf(buf, "%d", &mtu);
745 if (err > 0)
746 ibta_mtu = int_to_ibta_mtu(mtu);
747
748 if (err <= 0 || ibta_mtu < 0) {
749 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
750 return -EINVAL;
751 }
752
753 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
754
755 mlx4_stop_sense(mdev);
756 mutex_lock(&priv->port_mutex);
757 mlx4_unregister_device(mdev);
758 for (port = 1; port <= mdev->caps.num_ports; port++) {
759 mlx4_CLOSE_PORT(mdev, port);
6634961c 760 err = mlx4_SET_PORT(mdev, port, -1);
096335b3
OG		 761 if (err) {
762 mlx4_err(mdev, "Failed to set port %d, "
763 "aborting\n", port);
764 goto err_set_port;
765 }
766 }
767 err = mlx4_register_device(mdev);
768err_set_port:
769 mutex_unlock(&priv->port_mutex);
770 mlx4_start_sense(mdev);
771 return err ? err : count;
772}
773
e8f9b2ed 774static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 775{
776 struct mlx4_priv *priv = mlx4_priv(dev);
777 int err;
778
779 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 780 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 781 if (!priv->fw.fw_icm) {
782 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
783 return -ENOMEM;
784 }
785
786 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
787 if (err) {
788 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
789 goto err_free;
790 }
791
792 err = mlx4_RUN_FW(dev);
793 if (err) {
794 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
795 goto err_unmap_fa;
796 }
797
798 return 0;
799
800err_unmap_fa:
801 mlx4_UNMAP_FA(dev);
802
803err_free:
5b0bf5e2 804 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 805 return err;
806}
807
e8f9b2ed
RD		 808static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
809 int cmpt_entry_sz)
225c7b1f
RD		 810{
811 struct mlx4_priv *priv = mlx4_priv(dev);
812 int err;
ab9c17a0 813 int num_eqs;
225c7b1f
RD		 814
815 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
816 cmpt_base +
817 ((u64) (MLX4_CMPT_TYPE_QP *
818 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
819 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 820 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
821 0, 0);
225c7b1f
RD		 822 if (err)
823 goto err;
824
825 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
826 cmpt_base +
827 ((u64) (MLX4_CMPT_TYPE_SRQ *
828 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
829 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 830 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 831 if (err)
832 goto err_qp;
833
834 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
835 cmpt_base +
836 ((u64) (MLX4_CMPT_TYPE_CQ *
837 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
838 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 839 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 840 if (err)
841 goto err_srq;
842
3fc929e2
MA		 843 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
844 dev->caps.num_eqs;
225c7b1f
RD		 845 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
846 cmpt_base +
847 ((u64) (MLX4_CMPT_TYPE_EQ *
848 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 849 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 850 if (err)
851 goto err_cq;
852
853 return 0;
854
855err_cq:
856 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
857
858err_srq:
859 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
860
861err_qp:
862 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
863
864err:
865 return err;
866}
867
3d73c288
RD		 868static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
869 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 870{
871 struct mlx4_priv *priv = mlx4_priv(dev);
872 u64 aux_pages;
ab9c17a0 873 int num_eqs;
225c7b1f
RD		 874 int err;
875
876 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
877 if (err) {
878 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
879 return err;
880 }
881
882 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
883 (unsigned long long) icm_size >> 10,
884 (unsigned long long) aux_pages << 2);
885
886 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 887 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 888 if (!priv->fw.aux_icm) {
889 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
890 return -ENOMEM;
891 }
892
893 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
894 if (err) {
895 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
896 goto err_free_aux;
897 }
898
899 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
900 if (err) {
901 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
902 goto err_unmap_aux;
903 }
904
ab9c17a0 905
3fc929e2
MA		 906 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
907 dev->caps.num_eqs;
fa0681d2
RD		 908 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
909 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 910 num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 911 if (err) {
912 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
913 goto err_unmap_cmpt;
914 }
915
d7bb58fb
JM		 916 /*
917 * Reserved MTT entries must be aligned up to a cacheline
918 * boundary, since the FW will write to them, while the driver
919 * writes to all other MTT entries. (The variable
920 * dev->caps.mtt_entry_sz below is really the MTT segment
921 * size, not the raw entry size)
922 */
923 dev->caps.reserved_mtts =
924 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
925 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
926
225c7b1f
RD		 927 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
928 init_hca->mtt_base,
929 dev->caps.mtt_entry_sz,
2b8fb286 930 dev->caps.num_mtts,
5b0bf5e2 931 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 932 if (err) {
933 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
934 goto err_unmap_eq;
935 }
936
937 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
938 init_hca->dmpt_base,
939 dev_cap->dmpt_entry_sz,
940 dev->caps.num_mpts,
5b0bf5e2 941 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 942 if (err) {
943 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
944 goto err_unmap_mtt;
945 }
946
947 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
948 init_hca->qpc_base,
949 dev_cap->qpc_entry_sz,
950 dev->caps.num_qps,
93fc9e1b
YP		 951 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
952 0, 0);
225c7b1f
RD		 953 if (err) {
954 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
955 goto err_unmap_dmpt;
956 }
957
958 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
959 init_hca->auxc_base,
960 dev_cap->aux_entry_sz,
961 dev->caps.num_qps,
93fc9e1b
YP		 962 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
963 0, 0);
225c7b1f
RD		 964 if (err) {
965 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
966 goto err_unmap_qp;
967 }
968
969 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
970 init_hca->altc_base,
971 dev_cap->altc_entry_sz,
972 dev->caps.num_qps,
93fc9e1b
YP		 973 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
974 0, 0);
225c7b1f
RD		 975 if (err) {
976 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
977 goto err_unmap_auxc;
978 }
979
980 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
981 init_hca->rdmarc_base,
982 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
983 dev->caps.num_qps,
93fc9e1b
YP		 984 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
985 0, 0);
225c7b1f
RD		 986 if (err) {
987 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
988 goto err_unmap_altc;
989 }
990
991 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
992 init_hca->cqc_base,
993 dev_cap->cqc_entry_sz,
994 dev->caps.num_cqs,
5b0bf5e2 995 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 996 if (err) {
997 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
998 goto err_unmap_rdmarc;
999 }
1000
1001 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1002 init_hca->srqc_base,
1003 dev_cap->srq_entry_sz,
1004 dev->caps.num_srqs,
5b0bf5e2 1005 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1006 if (err) {
1007 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1008 goto err_unmap_cq;
1009 }
1010
1011 /*
0ff1fb65
HHZ		 1012 * For flow steering device managed mode it is required to use
1013 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1014 * required, but for simplicity just map the whole multicast
1015 * group table now. The table isn't very big and it's a lot
1016 * easier than trying to track ref counts.
225c7b1f
RD		 1017 */
1018 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1019 init_hca->mc_base,
1020 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1021 dev->caps.num_mgms + dev->caps.num_amgms,
1022 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1023 0, 0);
225c7b1f
RD		 1024 if (err) {
1025 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1026 goto err_unmap_srq;
1027 }
1028
1029 return 0;
1030
1031err_unmap_srq:
1032 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1033
1034err_unmap_cq:
1035 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1036
1037err_unmap_rdmarc:
1038 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1039
1040err_unmap_altc:
1041 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1042
1043err_unmap_auxc:
1044 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1045
1046err_unmap_qp:
1047 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1048
1049err_unmap_dmpt:
1050 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1051
1052err_unmap_mtt:
1053 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1054
1055err_unmap_eq:
fa0681d2 1056 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1057
1058err_unmap_cmpt:
1059 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1060 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1061 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1062 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1063
1064err_unmap_aux:
1065 mlx4_UNMAP_ICM_AUX(dev);
1066
1067err_free_aux:
5b0bf5e2 1068 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1069
1070 return err;
1071}
1072
1073static void mlx4_free_icms(struct mlx4_dev *dev)
1074{
1075 struct mlx4_priv *priv = mlx4_priv(dev);
1076
1077 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1078 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1079 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1080 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1081 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1082 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1083 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1084 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1085 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1086 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1087 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1088 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1089 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1090 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1091
1092 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1093 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1094}
1095
ab9c17a0
JM		 1096static void mlx4_slave_exit(struct mlx4_dev *dev)
1097{
1098 struct mlx4_priv *priv = mlx4_priv(dev);
1099
1100 down(&priv->cmd.slave_sem);
1101 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1102 mlx4_warn(dev, "Failed to close slave function.\n");
1103 up(&priv->cmd.slave_sem);
1104}
1105
c1b43dca
EC		 1106static int map_bf_area(struct mlx4_dev *dev)
1107{
1108 struct mlx4_priv *priv = mlx4_priv(dev);
1109 resource_size_t bf_start;
1110 resource_size_t bf_len;
1111 int err = 0;
1112
3d747473
JM		 1113 if (!dev->caps.bf_reg_size)
1114 return -ENXIO;
1115
ab9c17a0
JM		 1116 bf_start = pci_resource_start(dev->pdev, 2) +
1117 (dev->caps.num_uars << PAGE_SHIFT);
1118 bf_len = pci_resource_len(dev->pdev, 2) -
1119 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1120 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1121 if (!priv->bf_mapping)
1122 err = -ENOMEM;
1123
1124 return err;
1125}
1126
1127static void unmap_bf_area(struct mlx4_dev *dev)
1128{
1129 if (mlx4_priv(dev)->bf_mapping)
1130 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1131}
1132
225c7b1f
RD		 1133static void mlx4_close_hca(struct mlx4_dev *dev)
1134{
c1b43dca 1135 unmap_bf_area(dev);
ab9c17a0
JM		 1136 if (mlx4_is_slave(dev))
1137 mlx4_slave_exit(dev);
1138 else {
1139 mlx4_CLOSE_HCA(dev, 0);
1140 mlx4_free_icms(dev);
1141 mlx4_UNMAP_FA(dev);
1142 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1143 }
1144}
1145
1146static int mlx4_init_slave(struct mlx4_dev *dev)
1147{
1148 struct mlx4_priv *priv = mlx4_priv(dev);
1149 u64 dma = (u64) priv->mfunc.vhcr_dma;
1150 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1151 int ret_from_reset = 0;
1152 u32 slave_read;
1153 u32 cmd_channel_ver;
1154
1155 down(&priv->cmd.slave_sem);
1156 priv->cmd.max_cmds = 1;
1157 mlx4_warn(dev, "Sending reset\n");
1158 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1159 MLX4_COMM_TIME);
1160 /* if we are in the middle of flr the slave will try
1161 * NUM_OF_RESET_RETRIES times before leaving.*/
1162 if (ret_from_reset) {
1163 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1164 msleep(SLEEP_TIME_IN_RESET);
1165 while (ret_from_reset && num_of_reset_retries) {
1166 mlx4_warn(dev, "slave is currently in the"
1167 "middle of FLR. retrying..."
1168 "(try num:%d)\n",
1169 (NUM_OF_RESET_RETRIES -
1170 num_of_reset_retries + 1));
1171 ret_from_reset =
1172 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1173 0, MLX4_COMM_TIME);
1174 num_of_reset_retries = num_of_reset_retries - 1;
1175 }
1176 } else
1177 goto err;
1178 }
1179
1180 /* check the driver version - the slave I/F revision
1181 * must match the master's */
1182 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1183 cmd_channel_ver = mlx4_comm_get_version();
1184
1185 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1186 MLX4_COMM_GET_IF_REV(slave_read)) {
1187 mlx4_err(dev, "slave driver version is not supported"
1188 " by the master\n");
1189 goto err;
1190 }
1191
1192 mlx4_warn(dev, "Sending vhcr0\n");
1193 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1194 MLX4_COMM_TIME))
1195 goto err;
1196 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1197 MLX4_COMM_TIME))
1198 goto err;
1199 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1200 MLX4_COMM_TIME))
1201 goto err;
1202 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1203 goto err;
1204 up(&priv->cmd.slave_sem);
1205 return 0;
1206
1207err:
1208 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1209 up(&priv->cmd.slave_sem);
1210 return -EIO;
225c7b1f
RD		 1211}
1212
6634961c
JM		 1213static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1214{
1215 int i;
1216
1217 for (i = 1; i <= dev->caps.num_ports; i++) {
1218 dev->caps.gid_table_len[i] = 1;
1219 dev->caps.pkey_table_len[i] =
1220 dev->phys_caps.pkey_phys_table_len[i] - 1;
1221 }
1222}
1223
3d73c288 1224static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1225{
1226 struct mlx4_priv *priv = mlx4_priv(dev);
1227 struct mlx4_adapter adapter;
1228 struct mlx4_dev_cap dev_cap;
2d928651 1229 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1230 struct mlx4_profile profile;
1231 struct mlx4_init_hca_param init_hca;
1232 u64 icm_size;
1233 int err;
1234
ab9c17a0
JM		 1235 if (!mlx4_is_slave(dev)) {
1236 err = mlx4_QUERY_FW(dev);
1237 if (err) {
1238 if (err == -EACCES)
1239 mlx4_info(dev, "non-primary physical function, skipping.\n");
1240 else
1241 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
bef772eb 1242 return err;
ab9c17a0 1243 }
225c7b1f 1244
ab9c17a0
JM		 1245 err = mlx4_load_fw(dev);
1246 if (err) {
1247 mlx4_err(dev, "Failed to start FW, aborting.\n");
bef772eb 1248 return err;
ab9c17a0 1249 }
225c7b1f 1250
ab9c17a0
JM		 1251 mlx4_cfg.log_pg_sz_m = 1;
1252 mlx4_cfg.log_pg_sz = 0;
1253 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1254 if (err)
1255 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1256
ab9c17a0
JM		 1257 err = mlx4_dev_cap(dev, &dev_cap);
1258 if (err) {
1259 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1260 goto err_stop_fw;
1261 }
225c7b1f 1262
6634961c
JM		 1263 if (mlx4_is_master(dev))
1264 mlx4_parav_master_pf_caps(dev);
1265
0ff1fb65
HHZ		 1266 priv->fs_hash_mode = MLX4_FS_L2_HASH;
1267
1268 switch (priv->fs_hash_mode) {
1269 case MLX4_FS_L2_HASH:
1270 init_hca.fs_hash_enable_bits = 0;
1271 break;
1272
1273 case MLX4_FS_L2_L3_L4_HASH:
1274 /* Enable flow steering with
1275 * udp unicast and tcp unicast
1276 */
1277 init_hca.fs_hash_enable_bits =
1278 MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN;
1279 break;
1280 }
1281
ab9c17a0 1282 profile = default_profile;
0ff1fb65
HHZ		 1283 if (dev->caps.steering_mode ==
1284 MLX4_STEERING_MODE_DEVICE_MANAGED)
1285 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1286
ab9c17a0
JM		 1287 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1288 &init_hca);
1289 if ((long long) icm_size < 0) {
1290 err = icm_size;
1291 goto err_stop_fw;
1292 }
225c7b1f 1293
a5bbe892
EC		 1294 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1295
ab9c17a0
JM		 1296 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1297 init_hca.uar_page_sz = PAGE_SHIFT - 12;
c1b43dca 1298
ab9c17a0
JM		 1299 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1300 if (err)
1301 goto err_stop_fw;
225c7b1f 1302
ab9c17a0
JM		 1303 err = mlx4_INIT_HCA(dev, &init_hca);
1304 if (err) {
1305 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1306 goto err_free_icm;
1307 }
1308 } else {
1309 err = mlx4_init_slave(dev);
1310 if (err) {
1311 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1312 return err;
ab9c17a0 1313 }
225c7b1f 1314
ab9c17a0
JM		 1315 err = mlx4_slave_cap(dev);
1316 if (err) {
1317 mlx4_err(dev, "Failed to obtain slave caps\n");
1318 goto err_close;
1319 }
225c7b1f
RD		 1320 }
1321
ab9c17a0
JM		 1322 if (map_bf_area(dev))
1323 mlx4_dbg(dev, "Failed to map blue flame area\n");
1324
1325 /*Only the master set the ports, all the rest got it from it.*/
1326 if (!mlx4_is_slave(dev))
1327 mlx4_set_port_mask(dev);
1328
225c7b1f
RD		 1329 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1330 if (err) {
1331 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
bef772eb 1332 goto unmap_bf;
225c7b1f
RD		 1333 }
1334
1335 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1336 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1337
1338 return 0;
1339
bef772eb
AY		 1340unmap_bf:
1341 unmap_bf_area(dev);
1342
225c7b1f 1343err_close:
ab9c17a0 1344 mlx4_close_hca(dev);
225c7b1f
RD		 1345
1346err_free_icm:
ab9c17a0
JM		 1347 if (!mlx4_is_slave(dev))
1348 mlx4_free_icms(dev);
225c7b1f
RD		 1349
1350err_stop_fw:
ab9c17a0
JM		 1351 if (!mlx4_is_slave(dev)) {
1352 mlx4_UNMAP_FA(dev);
1353 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1354 }
225c7b1f
RD		 1355 return err;
1356}
1357
f2a3f6a3
OG		 1358static int mlx4_init_counters_table(struct mlx4_dev *dev)
1359{
1360 struct mlx4_priv *priv = mlx4_priv(dev);
1361 int nent;
1362
1363 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1364 return -ENOENT;
1365
1366 nent = dev->caps.max_counters;
1367 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1368}
1369
1370static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1371{
1372 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1373}
1374
ba062d52 1375int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1376{
1377 struct mlx4_priv *priv = mlx4_priv(dev);
1378
1379 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1380 return -ENOENT;
1381
1382 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1383 if (*idx == -1)
1384 return -ENOMEM;
1385
1386 return 0;
1387}
ba062d52
JM		 1388
1389int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1390{
1391 u64 out_param;
1392 int err;
1393
1394 if (mlx4_is_mfunc(dev)) {
1395 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1396 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1397 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1398 if (!err)
1399 *idx = get_param_l(&out_param);
1400
1401 return err;
1402 }
1403 return __mlx4_counter_alloc(dev, idx);
1404}
f2a3f6a3
OG		 1405EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1406
ba062d52 1407void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3
OG		 1408{
1409 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1410 return;
1411}
ba062d52
JM		 1412
1413void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1414{
1415 u64 in_param;
1416
1417 if (mlx4_is_mfunc(dev)) {
1418 set_param_l(&in_param, idx);
1419 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1420 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1421 MLX4_CMD_WRAPPED);
1422 return;
1423 }
1424 __mlx4_counter_free(dev, idx);
1425}
f2a3f6a3
OG		 1426EXPORT_SYMBOL_GPL(mlx4_counter_free);
1427
3d73c288 1428static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1429{
1430 struct mlx4_priv *priv = mlx4_priv(dev);
1431 int err;
7ff93f8b 1432 int port;
9a5aa622 1433 __be32 ib_port_default_caps;
225c7b1f 1434
225c7b1f
RD		 1435 err = mlx4_init_uar_table(dev);
1436 if (err) {
1437 mlx4_err(dev, "Failed to initialize "
1438 "user access region table, aborting.\n");
1439 return err;
1440 }
1441
1442 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1443 if (err) {
1444 mlx4_err(dev, "Failed to allocate driver access region, "
1445 "aborting.\n");
1446 goto err_uar_table_free;
1447 }
1448
4979d18f 1449 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f
RD		 1450 if (!priv->kar) {
1451 mlx4_err(dev, "Couldn't map kernel access region, "
1452 "aborting.\n");
1453 err = -ENOMEM;
1454 goto err_uar_free;
1455 }
1456
1457 err = mlx4_init_pd_table(dev);
1458 if (err) {
1459 mlx4_err(dev, "Failed to initialize "
1460 "protection domain table, aborting.\n");
1461 goto err_kar_unmap;
1462 }
1463
012a8ff5
SH		 1464 err = mlx4_init_xrcd_table(dev);
1465 if (err) {
1466 mlx4_err(dev, "Failed to initialize "
1467 "reliable connection domain table, aborting.\n");
1468 goto err_pd_table_free;
1469 }
1470
225c7b1f
RD		 1471 err = mlx4_init_mr_table(dev);
1472 if (err) {
1473 mlx4_err(dev, "Failed to initialize "
1474 "memory region table, aborting.\n");
012a8ff5 1475 goto err_xrcd_table_free;
225c7b1f
RD		 1476 }
1477
225c7b1f
RD		 1478 err = mlx4_init_eq_table(dev);
1479 if (err) {
1480 mlx4_err(dev, "Failed to initialize "
1481 "event queue table, aborting.\n");
ee49bd93 1482 goto err_mr_table_free;
225c7b1f
RD		 1483 }
1484
1485 err = mlx4_cmd_use_events(dev);
1486 if (err) {
1487 mlx4_err(dev, "Failed to switch to event-driven "
1488 "firmware commands, aborting.\n");
1489 goto err_eq_table_free;
1490 }
1491
1492 err = mlx4_NOP(dev);
1493 if (err) {
08fb1055
MT		 1494 if (dev->flags & MLX4_FLAG_MSI_X) {
1495 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1496 "interrupt IRQ %d).\n",
b8dd786f 1497 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 1498 mlx4_warn(dev, "Trying again without MSI-X.\n");
1499 } else {
1500 mlx4_err(dev, "NOP command failed to generate interrupt "
1501 "(IRQ %d), aborting.\n",
b8dd786f 1502 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1503 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1504 }
225c7b1f
RD		 1505
1506 goto err_cmd_poll;
1507 }
1508
1509 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1510
1511 err = mlx4_init_cq_table(dev);
1512 if (err) {
1513 mlx4_err(dev, "Failed to initialize "
1514 "completion queue table, aborting.\n");
1515 goto err_cmd_poll;
1516 }
1517
1518 err = mlx4_init_srq_table(dev);
1519 if (err) {
1520 mlx4_err(dev, "Failed to initialize "
1521 "shared receive queue table, aborting.\n");
1522 goto err_cq_table_free;
1523 }
1524
1525 err = mlx4_init_qp_table(dev);
1526 if (err) {
1527 mlx4_err(dev, "Failed to initialize "
1528 "queue pair table, aborting.\n");
1529 goto err_srq_table_free;
1530 }
1531
ab9c17a0
JM		 1532 if (!mlx4_is_slave(dev)) {
1533 err = mlx4_init_mcg_table(dev);
1534 if (err) {
1535 mlx4_err(dev, "Failed to initialize "
1536 "multicast group table, aborting.\n");
1537 goto err_qp_table_free;
1538 }
225c7b1f
RD		 1539 }
1540
f2a3f6a3
OG		 1541 err = mlx4_init_counters_table(dev);
1542 if (err && err != -ENOENT) {
1543 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
ab9c17a0 1544 goto err_mcg_table_free;
f2a3f6a3
OG		 1545 }
1546
ab9c17a0
JM		 1547 if (!mlx4_is_slave(dev)) {
1548 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1549 ib_port_default_caps = 0;
1550 err = mlx4_get_port_ib_caps(dev, port,
1551 &ib_port_default_caps);
1552 if (err)
1553 mlx4_warn(dev, "failed to get port %d default "
1554 "ib capabilities (%d). Continuing "
1555 "with caps = 0\n", port, err);
1556 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1557
2aca1172
JM		 1558 /* initialize per-slave default ib port capabilities */
1559 if (mlx4_is_master(dev)) {
1560 int i;
1561 for (i = 0; i < dev->num_slaves; i++) {
1562 if (i == mlx4_master_func_num(dev))
1563 continue;
1564 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1565 ib_port_default_caps;
1566 }
1567 }
1568
096335b3
OG		 1569 if (mlx4_is_mfunc(dev))
1570 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1571 else
1572 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 1573
6634961c
JM		 1574 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1575 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 1576 if (err) {
1577 mlx4_err(dev, "Failed to set port %d, aborting\n",
1578 port);
1579 goto err_counters_table_free;
1580 }
7ff93f8b
YP		 1581 }
1582 }
1583
225c7b1f
RD		 1584 return 0;
1585
f2a3f6a3
OG		 1586err_counters_table_free:
1587 mlx4_cleanup_counters_table(dev);
1588
ab9c17a0
JM		 1589err_mcg_table_free:
1590 mlx4_cleanup_mcg_table(dev);
1591
225c7b1f
RD		 1592err_qp_table_free:
1593 mlx4_cleanup_qp_table(dev);
1594
1595err_srq_table_free:
1596 mlx4_cleanup_srq_table(dev);
1597
1598err_cq_table_free:
1599 mlx4_cleanup_cq_table(dev);
1600
1601err_cmd_poll:
1602 mlx4_cmd_use_polling(dev);
1603
1604err_eq_table_free:
1605 mlx4_cleanup_eq_table(dev);
1606
ee49bd93 1607err_mr_table_free:
225c7b1f
RD		 1608 mlx4_cleanup_mr_table(dev);
1609
012a8ff5
SH		 1610err_xrcd_table_free:
1611 mlx4_cleanup_xrcd_table(dev);
1612
225c7b1f
RD		 1613err_pd_table_free:
1614 mlx4_cleanup_pd_table(dev);
1615
1616err_kar_unmap:
1617 iounmap(priv->kar);
1618
1619err_uar_free:
1620 mlx4_uar_free(dev, &priv->driver_uar);
1621
1622err_uar_table_free:
1623 mlx4_cleanup_uar_table(dev);
1624 return err;
1625}
1626
e8f9b2ed 1627static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 1628{
1629 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 1630 struct msix_entry *entries;
0b7ca5a9 1631 int nreq = min_t(int, dev->caps.num_ports *
90b1ebe7
YM		 1632 min_t(int, netif_get_num_default_rss_queues() + 1,
1633 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 1634 int err;
1635 int i;
1636
1637 if (msi_x) {
ab9c17a0
JM		 1638 /* In multifunction mode each function gets 2 msi-X vectors
1639 * one for data path completions anf the other for asynch events
1640 * or command completions */
1641 if (mlx4_is_mfunc(dev)) {
1642 nreq = 2;
1643 } else {
1644 nreq = min_t(int, dev->caps.num_eqs -
1645 dev->caps.reserved_eqs, nreq);
1646 }
1647
b8dd786f
YP		 1648 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1649 if (!entries)
1650 goto no_msi;
1651
1652 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1653 entries[i].entry = i;
1654
b8dd786f
YP		 1655 retry:
1656 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 1657 if (err) {
b8dd786f
YP		 1658 /* Try again if at least 2 vectors are available */
1659 if (err > 1) {
1660 mlx4_info(dev, "Requested %d vectors, "
1661 "but only %d MSI-X vectors available, "
1662 "trying again\n", nreq, err);
1663 nreq = err;
1664 goto retry;
1665 }
5bf0da7d 1666 kfree(entries);
225c7b1f
RD		 1667 goto no_msi;
1668 }
1669
0b7ca5a9
YP		 1670 if (nreq <
1671 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1672 /*Working in legacy mode , all EQ's shared*/
1673 dev->caps.comp_pool = 0;
1674 dev->caps.num_comp_vectors = nreq - 1;
1675 } else {
1676 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1677 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1678 }
b8dd786f 1679 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1680 priv->eq_table.eq[i].irq = entries[i].vector;
1681
1682 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 1683
1684 kfree(entries);
225c7b1f
RD		 1685 return;
1686 }
1687
1688no_msi:
b8dd786f 1689 dev->caps.num_comp_vectors = 1;
0b7ca5a9 1690 dev->caps.comp_pool = 0;
b8dd786f
YP		 1691
1692 for (i = 0; i < 2; ++i)
225c7b1f
RD		 1693 priv->eq_table.eq[i].irq = dev->pdev->irq;
1694}
1695
7ff93f8b 1696static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 1697{
1698 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 1699 int err = 0;
2a2336f8
YP		 1700
1701 info->dev = dev;
1702 info->port = port;
ab9c17a0
JM		 1703 if (!mlx4_is_slave(dev)) {
1704 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL);
1705 mlx4_init_mac_table(dev, &info->mac_table);
1706 mlx4_init_vlan_table(dev, &info->vlan_table);
1707 info->base_qpn =
1708 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
06fa0a88 1709 (port - 1) * (1 << log_num_mac);
ab9c17a0 1710 }
7ff93f8b
YP		 1711
1712 sprintf(info->dev_name, "mlx4_port%d", port);
1713 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 1714 if (mlx4_is_mfunc(dev))
1715 info->port_attr.attr.mode = S_IRUGO;
1716 else {
1717 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1718 info->port_attr.store = set_port_type;
1719 }
7ff93f8b 1720 info->port_attr.show = show_port_type;
3691c964 1721 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 1722
1723 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1724 if (err) {
1725 mlx4_err(dev, "Failed to create file for port %d\n", port);
1726 info->port = -1;
1727 }
1728
096335b3
OG		 1729 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1730 info->port_mtu_attr.attr.name = info->dev_mtu_name;
1731 if (mlx4_is_mfunc(dev))
1732 info->port_mtu_attr.attr.mode = S_IRUGO;
1733 else {
1734 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1735 info->port_mtu_attr.store = set_port_ib_mtu;
1736 }
1737 info->port_mtu_attr.show = show_port_ib_mtu;
1738 sysfs_attr_init(&info->port_mtu_attr.attr);
1739
1740 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1741 if (err) {
1742 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1743 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1744 info->port = -1;
1745 }
1746
7ff93f8b
YP		 1747 return err;
1748}
1749
1750static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1751{
1752 if (info->port < 0)
1753 return;
1754
1755 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 1756 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 1757}
1758
b12d93d6
YP		 1759static int mlx4_init_steering(struct mlx4_dev *dev)
1760{
1761 struct mlx4_priv *priv = mlx4_priv(dev);
1762 int num_entries = dev->caps.num_ports;
1763 int i, j;
1764
1765 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1766 if (!priv->steer)
1767 return -ENOMEM;
1768
45b51365 1769 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 1770 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1771 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1772 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1773 }
b12d93d6
YP		 1774 return 0;
1775}
1776
1777static void mlx4_clear_steering(struct mlx4_dev *dev)
1778{
1779 struct mlx4_priv *priv = mlx4_priv(dev);
1780 struct mlx4_steer_index *entry, *tmp_entry;
1781 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1782 int num_entries = dev->caps.num_ports;
1783 int i, j;
1784
1785 for (i = 0; i < num_entries; i++) {
1786 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1787 list_for_each_entry_safe(pqp, tmp_pqp,
1788 &priv->steer[i].promisc_qps[j],
1789 list) {
1790 list_del(&pqp->list);
1791 kfree(pqp);
1792 }
1793 list_for_each_entry_safe(entry, tmp_entry,
1794 &priv->steer[i].steer_entries[j],
1795 list) {
1796 list_del(&entry->list);
1797 list_for_each_entry_safe(pqp, tmp_pqp,
1798 &entry->duplicates,
1799 list) {
1800 list_del(&pqp->list);
1801 kfree(pqp);
1802 }
1803 kfree(entry);
1804 }
1805 }
1806 }
1807 kfree(priv->steer);
1808}
1809
ab9c17a0
JM		 1810static int extended_func_num(struct pci_dev *pdev)
1811{
1812 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
1813}
1814
1815#define MLX4_OWNER_BASE 0x8069c
1816#define MLX4_OWNER_SIZE 4
1817
1818static int mlx4_get_ownership(struct mlx4_dev *dev)
1819{
1820 void __iomem *owner;
1821 u32 ret;
1822
57dbf29a
KSS		 1823 if (pci_channel_offline(dev->pdev))
1824 return -EIO;
1825
ab9c17a0
JM		 1826 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1827 MLX4_OWNER_SIZE);
1828 if (!owner) {
1829 mlx4_err(dev, "Failed to obtain ownership bit\n");
1830 return -ENOMEM;
1831 }
1832
1833 ret = readl(owner);
1834 iounmap(owner);
1835 return (int) !!ret;
1836}
1837
1838static void mlx4_free_ownership(struct mlx4_dev *dev)
1839{
1840 void __iomem *owner;
1841
57dbf29a
KSS		 1842 if (pci_channel_offline(dev->pdev))
1843 return;
1844
ab9c17a0
JM		 1845 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1846 MLX4_OWNER_SIZE);
1847 if (!owner) {
1848 mlx4_err(dev, "Failed to obtain ownership bit\n");
1849 return;
1850 }
1851 writel(0, owner);
1852 msleep(1000);
1853 iounmap(owner);
1854}
1855
3d73c288 1856static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
225c7b1f 1857{
225c7b1f
RD		 1858 struct mlx4_priv *priv;
1859 struct mlx4_dev *dev;
1860 int err;
2a2336f8 1861 int port;
225c7b1f 1862
0a645e80 1863 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 1864
1865 err = pci_enable_device(pdev);
1866 if (err) {
1867 dev_err(&pdev->dev, "Cannot enable PCI device, "
1868 "aborting.\n");
1869 return err;
1870 }
ab9c17a0
JM		 1871 if (num_vfs > MLX4_MAX_NUM_VF) {
1872 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
1873 num_vfs, MLX4_MAX_NUM_VF);
1874 return -EINVAL;
1875 }
225c7b1f 1876 /*
ab9c17a0 1877 * Check for BARs.
225c7b1f 1878 */
ab9c17a0
JM		 1879 if (((id == NULL) || !(id->driver_data & MLX4_VF)) &&
1880 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1881 dev_err(&pdev->dev, "Missing DCS, aborting."
1882 "(id == 0X%p, id->driver_data: 0x%lx,"
1883 " pci_resource_flags(pdev, 0):0x%lx)\n", id,
1884 id ? id->driver_data : 0, pci_resource_flags(pdev, 0));
225c7b1f
RD		 1885 err = -ENODEV;
1886 goto err_disable_pdev;
1887 }
1888 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1889 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1890 err = -ENODEV;
1891 goto err_disable_pdev;
1892 }
1893
a01df0fe 1894 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 1895 if (err) {
a01df0fe 1896 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 1897 goto err_disable_pdev;
1898 }
1899
225c7b1f
RD		 1900 pci_set_master(pdev);
1901
6a35528a 1902 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1903 if (err) {
1904 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 1905 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1906 if (err) {
1907 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 1908 goto err_release_regions;
225c7b1f
RD		 1909 }
1910 }
6a35528a 1911 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1912 if (err) {
1913 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1914 "consistent PCI DMA mask.\n");
284901a9 1915 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1916 if (err) {
1917 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1918 "aborting.\n");
a01df0fe 1919 goto err_release_regions;
225c7b1f
RD		 1920 }
1921 }
1922
7f9e5c48
DD		 1923 /* Allow large DMA segments, up to the firmware limit of 1 GB */
1924 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1925
225c7b1f
RD		 1926 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1927 if (!priv) {
1928 dev_err(&pdev->dev, "Device struct alloc failed, "
1929 "aborting.\n");
1930 err = -ENOMEM;
a01df0fe 1931 goto err_release_regions;
225c7b1f
RD		 1932 }
1933
1934 dev = &priv->dev;
1935 dev->pdev = pdev;
b581401e
RD		 1936 INIT_LIST_HEAD(&priv->ctx_list);
1937 spin_lock_init(&priv->ctx_lock);
225c7b1f 1938
7ff93f8b
YP		 1939 mutex_init(&priv->port_mutex);
1940
6296883c
YP		 1941 INIT_LIST_HEAD(&priv->pgdir_list);
1942 mutex_init(&priv->pgdir_mutex);
1943
c1b43dca
EC		 1944 INIT_LIST_HEAD(&priv->bf_list);
1945 mutex_init(&priv->bf_mutex);
1946
aca7a3ac 1947 dev->rev_id = pdev->revision;
ab9c17a0
JM		 1948 /* Detect if this device is a virtual function */
1949 if (id && id->driver_data & MLX4_VF) {
1950 /* When acting as pf, we normally skip vfs unless explicitly
1951 * requested to probe them. */
1952 if (num_vfs && extended_func_num(pdev) > probe_vf) {
1953 mlx4_warn(dev, "Skipping virtual function:%d\n",
1954 extended_func_num(pdev));
1955 err = -ENODEV;
1956 goto err_free_dev;
1957 }
1958 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
1959 dev->flags |= MLX4_FLAG_SLAVE;
1960 } else {
1961 /* We reset the device and enable SRIOV only for physical
1962 * devices. Try to claim ownership on the device;
1963 * if already taken, skip -- do not allow multiple PFs */
1964 err = mlx4_get_ownership(dev);
1965 if (err) {
1966 if (err < 0)
1967 goto err_free_dev;
1968 else {
1969 mlx4_warn(dev, "Multiple PFs not yet supported."
1970 " Skipping PF.\n");
1971 err = -EINVAL;
1972 goto err_free_dev;
1973 }
1974 }
aca7a3ac 1975
ab9c17a0
JM		 1976 if (num_vfs) {
1977 mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs);
1978 err = pci_enable_sriov(pdev, num_vfs);
1979 if (err) {
1980 mlx4_err(dev, "Failed to enable sriov,"
1981 "continuing without sriov enabled"
1982 " (err = %d).\n", err);
ab9c17a0
JM		 1983 err = 0;
1984 } else {
1985 mlx4_warn(dev, "Running in master mode\n");
1986 dev->flags |= MLX4_FLAG_SRIOV |
1987 MLX4_FLAG_MASTER;
1988 dev->num_vfs = num_vfs;
1989 }
1990 }
1991
1992 /*
1993 * Now reset the HCA before we touch the PCI capabilities or
1994 * attempt a firmware command, since a boot ROM may have left
1995 * the HCA in an undefined state.
1996 */
1997 err = mlx4_reset(dev);
1998 if (err) {
1999 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2000 goto err_rel_own;
2001 }
225c7b1f
RD		 2002 }
2003
ab9c17a0 2004slave_start:
521130d1
EE		 2005 err = mlx4_cmd_init(dev);
2006 if (err) {
225c7b1f 2007 mlx4_err(dev, "Failed to init command interface, aborting.\n");
ab9c17a0
JM		 2008 goto err_sriov;
2009 }
2010
2011 /* In slave functions, the communication channel must be initialized
2012 * before posting commands. Also, init num_slaves before calling
2013 * mlx4_init_hca */
2014 if (mlx4_is_mfunc(dev)) {
2015 if (mlx4_is_master(dev))
2016 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2017 else {
2018 dev->num_slaves = 0;
2019 if (mlx4_multi_func_init(dev)) {
2020 mlx4_err(dev, "Failed to init slave mfunc"
2021 " interface, aborting.\n");
2022 goto err_cmd;
2023 }
2024 }
225c7b1f
RD		 2025 }
2026
2027 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2028 if (err) {
2029 if (err == -EACCES) {
2030 /* Not primary Physical function
2031 * Running in slave mode */
2032 mlx4_cmd_cleanup(dev);
2033 dev->flags |= MLX4_FLAG_SLAVE;
2034 dev->flags &= ~MLX4_FLAG_MASTER;
2035 goto slave_start;
2036 } else
2037 goto err_mfunc;
2038 }
2039
2040 /* In master functions, the communication channel must be initialized
2041 * after obtaining its address from fw */
2042 if (mlx4_is_master(dev)) {
2043 if (mlx4_multi_func_init(dev)) {
2044 mlx4_err(dev, "Failed to init master mfunc"
2045 "interface, aborting.\n");
2046 goto err_close;
2047 }
2048 }
225c7b1f 2049
b8dd786f
YP		 2050 err = mlx4_alloc_eq_table(dev);
2051 if (err)
ab9c17a0 2052 goto err_master_mfunc;
b8dd786f 2053
0b7ca5a9 2054 priv->msix_ctl.pool_bm = 0;
730c41d5 2055 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2056
08fb1055 2057 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2058 if ((mlx4_is_mfunc(dev)) &&
2059 !(dev->flags & MLX4_FLAG_MSI_X)) {
2060 mlx4_err(dev, "INTx is not supported in multi-function mode."
2061 " aborting.\n");
b12d93d6 2062 goto err_free_eq;
ab9c17a0
JM		 2063 }
2064
2065 if (!mlx4_is_slave(dev)) {
2066 err = mlx4_init_steering(dev);
2067 if (err)
2068 goto err_free_eq;
2069 }
b12d93d6 2070
225c7b1f 2071 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2072 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2073 !mlx4_is_mfunc(dev)) {
08fb1055 2074 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2075 dev->caps.num_comp_vectors = 1;
2076 dev->caps.comp_pool = 0;
08fb1055
MT		 2077 pci_disable_msix(pdev);
2078 err = mlx4_setup_hca(dev);
2079 }
2080
225c7b1f 2081 if (err)
b12d93d6 2082 goto err_steer;
225c7b1f 2083
7ff93f8b
YP		 2084 for (port = 1; port <= dev->caps.num_ports; port++) {
2085 err = mlx4_init_port_info(dev, port);
2086 if (err)
2087 goto err_port;
2088 }
2a2336f8 2089
225c7b1f
RD		 2090 err = mlx4_register_device(dev);
2091 if (err)
7ff93f8b 2092 goto err_port;
225c7b1f 2093
27bf91d6
YP		 2094 mlx4_sense_init(dev);
2095 mlx4_start_sense(dev);
2096
225c7b1f
RD		 2097 pci_set_drvdata(pdev, dev);
2098
2099 return 0;
2100
7ff93f8b 2101err_port:
b4f77264 2102 for (--port; port >= 1; --port)
7ff93f8b
YP		 2103 mlx4_cleanup_port_info(&priv->port[port]);
2104
f2a3f6a3 2105 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2106 mlx4_cleanup_mcg_table(dev);
2107 mlx4_cleanup_qp_table(dev);
2108 mlx4_cleanup_srq_table(dev);
2109 mlx4_cleanup_cq_table(dev);
2110 mlx4_cmd_use_polling(dev);
2111 mlx4_cleanup_eq_table(dev);
225c7b1f 2112 mlx4_cleanup_mr_table(dev);
012a8ff5 2113 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2114 mlx4_cleanup_pd_table(dev);
2115 mlx4_cleanup_uar_table(dev);
2116
b12d93d6 2117err_steer:
ab9c17a0
JM		 2118 if (!mlx4_is_slave(dev))
2119 mlx4_clear_steering(dev);
b12d93d6 2120
b8dd786f
YP		 2121err_free_eq:
2122 mlx4_free_eq_table(dev);
2123
ab9c17a0
JM		 2124err_master_mfunc:
2125 if (mlx4_is_master(dev))
2126 mlx4_multi_func_cleanup(dev);
2127
225c7b1f 2128err_close:
08fb1055
MT		 2129 if (dev->flags & MLX4_FLAG_MSI_X)
2130 pci_disable_msix(pdev);
2131
225c7b1f
RD		 2132 mlx4_close_hca(dev);
2133
ab9c17a0
JM		 2134err_mfunc:
2135 if (mlx4_is_slave(dev))
2136 mlx4_multi_func_cleanup(dev);
2137
225c7b1f
RD		 2138err_cmd:
2139 mlx4_cmd_cleanup(dev);
2140
ab9c17a0 2141err_sriov:
681372a7 2142 if (dev->flags & MLX4_FLAG_SRIOV)
ab9c17a0
JM		 2143 pci_disable_sriov(pdev);
2144
2145err_rel_own:
2146 if (!mlx4_is_slave(dev))
2147 mlx4_free_ownership(dev);
2148
225c7b1f 2149err_free_dev:
225c7b1f
RD		 2150 kfree(priv);
2151
a01df0fe
RD		 2152err_release_regions:
2153 pci_release_regions(pdev);
225c7b1f
RD		 2154
2155err_disable_pdev:
2156 pci_disable_device(pdev);
2157 pci_set_drvdata(pdev, NULL);
2158 return err;
2159}
2160
3d73c288
RD		 2161static int __devinit mlx4_init_one(struct pci_dev *pdev,
2162 const struct pci_device_id *id)
2163{
0a645e80 2164 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2165
b027cacd 2166 return __mlx4_init_one(pdev, id);
3d73c288
RD		 2167}
2168
2169static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 2170{
2171 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2172 struct mlx4_priv *priv = mlx4_priv(dev);
2173 int p;
2174
2175 if (dev) {
ab9c17a0
JM		 2176 /* in SRIOV it is not allowed to unload the pf's
2177 * driver while there are alive vf's */
2178 if (mlx4_is_master(dev)) {
2179 if (mlx4_how_many_lives_vf(dev))
2180 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2181 }
27bf91d6 2182 mlx4_stop_sense(dev);
225c7b1f
RD		 2183 mlx4_unregister_device(dev);
2184
7ff93f8b
YP		 2185 for (p = 1; p <= dev->caps.num_ports; p++) {
2186 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 2187 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 2188 }
225c7b1f 2189
b8924951
JM		 2190 if (mlx4_is_master(dev))
2191 mlx4_free_resource_tracker(dev,
2192 RES_TR_FREE_SLAVES_ONLY);
2193
f2a3f6a3 2194 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2195 mlx4_cleanup_mcg_table(dev);
2196 mlx4_cleanup_qp_table(dev);
2197 mlx4_cleanup_srq_table(dev);
2198 mlx4_cleanup_cq_table(dev);
2199 mlx4_cmd_use_polling(dev);
2200 mlx4_cleanup_eq_table(dev);
225c7b1f 2201 mlx4_cleanup_mr_table(dev);
012a8ff5 2202 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2203 mlx4_cleanup_pd_table(dev);
2204
ab9c17a0 2205 if (mlx4_is_master(dev))
b8924951
JM		 2206 mlx4_free_resource_tracker(dev,
2207 RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 2208
225c7b1f
RD		 2209 iounmap(priv->kar);
2210 mlx4_uar_free(dev, &priv->driver_uar);
2211 mlx4_cleanup_uar_table(dev);
ab9c17a0
JM		 2212 if (!mlx4_is_slave(dev))
2213 mlx4_clear_steering(dev);
b8dd786f 2214 mlx4_free_eq_table(dev);
ab9c17a0
JM		 2215 if (mlx4_is_master(dev))
2216 mlx4_multi_func_cleanup(dev);
225c7b1f 2217 mlx4_close_hca(dev);
ab9c17a0
JM		 2218 if (mlx4_is_slave(dev))
2219 mlx4_multi_func_cleanup(dev);
225c7b1f
RD		 2220 mlx4_cmd_cleanup(dev);
2221
2222 if (dev->flags & MLX4_FLAG_MSI_X)
2223 pci_disable_msix(pdev);
681372a7 2224 if (dev->flags & MLX4_FLAG_SRIOV) {
ab9c17a0
JM		 2225 mlx4_warn(dev, "Disabling sriov\n");
2226 pci_disable_sriov(pdev);
2227 }
225c7b1f 2228
ab9c17a0
JM		 2229 if (!mlx4_is_slave(dev))
2230 mlx4_free_ownership(dev);
225c7b1f 2231 kfree(priv);
a01df0fe 2232 pci_release_regions(pdev);
225c7b1f
RD		 2233 pci_disable_device(pdev);
2234 pci_set_drvdata(pdev, NULL);
2235 }
2236}
2237
ee49bd93
JM		 2238int mlx4_restart_one(struct pci_dev *pdev)
2239{
2240 mlx4_remove_one(pdev);
3d73c288 2241 return __mlx4_init_one(pdev, NULL);
ee49bd93
JM		 2242}
2243
a3aa1884 2244static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0
JM		 2245 /* MT25408 "Hermon" SDR */
2246 { PCI_VDEVICE(MELLANOX, 0x6340), 0 },
2247 /* MT25408 "Hermon" DDR */
2248 { PCI_VDEVICE(MELLANOX, 0x634a), 0 },
2249 /* MT25408 "Hermon" QDR */
2250 { PCI_VDEVICE(MELLANOX, 0x6354), 0 },
2251 /* MT25408 "Hermon" DDR PCIe gen2 */
2252 { PCI_VDEVICE(MELLANOX, 0x6732), 0 },
2253 /* MT25408 "Hermon" QDR PCIe gen2 */
2254 { PCI_VDEVICE(MELLANOX, 0x673c), 0 },
2255 /* MT25408 "Hermon" EN 10GigE */
2256 { PCI_VDEVICE(MELLANOX, 0x6368), 0 },
2257 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2258 { PCI_VDEVICE(MELLANOX, 0x6750), 0 },
2259 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2260 { PCI_VDEVICE(MELLANOX, 0x6372), 0 },
2261 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2262 { PCI_VDEVICE(MELLANOX, 0x675a), 0 },
2263 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2264 { PCI_VDEVICE(MELLANOX, 0x6764), 0 },
2265 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2266 { PCI_VDEVICE(MELLANOX, 0x6746), 0 },
2267 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2268 { PCI_VDEVICE(MELLANOX, 0x676e), 0 },
2269 /* MT25400 Family [ConnectX-2 Virtual Function] */
2270 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_VF },
2271 /* MT27500 Family [ConnectX-3] */
2272 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2273 /* MT27500 Family [ConnectX-3 Virtual Function] */
2274 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_VF },
2275 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2276 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2277 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2278 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2279 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2280 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2281 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2282 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2283 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2284 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2285 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2286 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2287 { 0, }
2288};
2289
2290MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2291
57dbf29a
KSS		 2292static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2293 pci_channel_state_t state)
2294{
2295 mlx4_remove_one(pdev);
2296
2297 return state == pci_channel_io_perm_failure ?
2298 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2299}
2300
2301static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2302{
2303 int ret = __mlx4_init_one(pdev, NULL);
2304
2305 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2306}
2307
2308static struct pci_error_handlers mlx4_err_handler = {
2309 .error_detected = mlx4_pci_err_detected,
2310 .slot_reset = mlx4_pci_slot_reset,
2311};
2312
225c7b1f
RD		 2313static struct pci_driver mlx4_driver = {
2314 .name = DRV_NAME,
2315 .id_table = mlx4_pci_table,
2316 .probe = mlx4_init_one,
57dbf29a
KSS		 2317 .remove = __devexit_p(mlx4_remove_one),
2318 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 2319};
2320
7ff93f8b
YP		 2321static int __init mlx4_verify_params(void)
2322{
2323 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2324 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2325 return -1;
2326 }
2327
cb29688a
OG		 2328 if (log_num_vlan != 0)
2329 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2330 MLX4_LOG_NUM_VLANS);
7ff93f8b 2331
0498628f 2332 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2333 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2334 return -1;
2335 }
2336
ab9c17a0
JM		 2337 /* Check if module param for ports type has legal combination */
2338 if (port_type_array[0] == false && port_type_array[1] == true) {
2339 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2340 port_type_array[0] = true;
2341 }
2342
7ff93f8b
YP		 2343 return 0;
2344}
2345
225c7b1f
RD		 2346static int __init mlx4_init(void)
2347{
2348 int ret;
2349
7ff93f8b
YP		 2350 if (mlx4_verify_params())
2351 return -EINVAL;
2352
27bf91d6
YP		 2353 mlx4_catas_init();
2354
2355 mlx4_wq = create_singlethread_workqueue("mlx4");
2356 if (!mlx4_wq)
2357 return -ENOMEM;
ee49bd93 2358
225c7b1f
RD		 2359 ret = pci_register_driver(&mlx4_driver);
2360 return ret < 0 ? ret : 0;
2361}
2362
2363static void __exit mlx4_cleanup(void)
2364{
2365 pci_unregister_driver(&mlx4_driver);
27bf91d6 2366 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2367}
2368
2369module_init(mlx4_init);
2370module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)