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cdc-ncm: tag Ericsson WWAN devices (eg F5521gw) with FLAG_WWAN
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
90b1ebe7 44#include <linux/netdevice.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
ab9c17a0
JM		 80static int num_vfs;
81module_param(num_vfs, int, 0444);
82MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
83
84static int probe_vf;
85module_param(probe_vf, int, 0644);
86MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
87
0ec2c0f8
EE		 88int mlx4_log_num_mgm_entry_size = 10;
89module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
93 " 10 gives 248.range: 9<="
0ff1fb65
HHZ		 94 " log_num_mgm_entry_size <= 12."
95 " Not in use with device managed"
96 " flow steering");
0ec2c0f8 97
ab9c17a0
JM		 98#define MLX4_VF (1 << 0)
99
100#define HCA_GLOBAL_CAP_MASK 0
101#define PF_CONTEXT_BEHAVIOUR_MASK 0
102
f33afc26 103static char mlx4_version[] __devinitdata =
225c7b1f
RD		 104 DRV_NAME ": Mellanox ConnectX core driver v"
105 DRV_VERSION " (" DRV_RELDATE ")\n";
106
107static struct mlx4_profile default_profile = {
ab9c17a0 108 .num_qp = 1 << 18,
225c7b1f 109 .num_srq = 1 << 16,
c9f2ba5e 110 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 111 .num_cq = 1 << 16,
112 .num_mcg = 1 << 13,
ab9c17a0 113 .num_mpt = 1 << 19,
9fd7a1e1 114 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 115};
116
ab9c17a0 117static int log_num_mac = 7;
93fc9e1b
YP		 118module_param_named(log_num_mac, log_num_mac, int, 0444);
119MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
120
121static int log_num_vlan;
122module_param_named(log_num_vlan, log_num_vlan, int, 0444);
123MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 124/* Log2 max number of VLANs per ETH port (0-7) */
125#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 126
eb939922 127static bool use_prio;
93fc9e1b
YP		 128module_param_named(use_prio, use_prio, bool, 0444);
129MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
130 "(0/1, default 0)");
131
2b8fb286 132int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 133module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 134MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 135
8d0fc7b6 136static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 137static int arr_argc = 2;
138module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 139MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
140 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 141
142struct mlx4_port_config {
143 struct list_head list;
144 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
145 struct pci_dev *pdev;
146};
147
27bf91d6
YP		 148int mlx4_check_port_params(struct mlx4_dev *dev,
149 enum mlx4_port_type *port_type)
7ff93f8b
YP		 150{
151 int i;
152
153 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 154 if (port_type[i] != port_type[i + 1]) {
155 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
156 mlx4_err(dev, "Only same port types supported "
157 "on this HCA, aborting.\n");
158 return -EINVAL;
159 }
160 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
161 port_type[i + 1] == MLX4_PORT_TYPE_IB)
162 return -EINVAL;
7ff93f8b
YP		 163 }
164 }
7ff93f8b
YP		 165
166 for (i = 0; i < dev->caps.num_ports; i++) {
167 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
168 mlx4_err(dev, "Requested port type for port %d is not "
169 "supported on this HCA\n", i + 1);
170 return -EINVAL;
171 }
172 }
173 return 0;
174}
175
176static void mlx4_set_port_mask(struct mlx4_dev *dev)
177{
178 int i;
179
7ff93f8b 180 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 181 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 182}
f2a3f6a3 183
3d73c288 184static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 185{
186 int err;
5ae2a7a8 187 int i;
225c7b1f
RD		 188
189 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
190 if (err) {
191 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
192 return err;
193 }
194
195 if (dev_cap->min_page_sz > PAGE_SIZE) {
196 mlx4_err(dev, "HCA minimum page size of %d bigger than "
197 "kernel PAGE_SIZE of %ld, aborting.\n",
198 dev_cap->min_page_sz, PAGE_SIZE);
199 return -ENODEV;
200 }
201 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
202 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
203 "aborting.\n",
204 dev_cap->num_ports, MLX4_MAX_PORTS);
205 return -ENODEV;
206 }
207
208 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
209 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
210 "PCI resource 2 size of 0x%llx, aborting.\n",
211 dev_cap->uar_size,
212 (unsigned long long) pci_resource_len(dev->pdev, 2));
213 return -ENODEV;
214 }
215
216 dev->caps.num_ports = dev_cap->num_ports;
3fc929e2 217 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
5ae2a7a8
RD		 218 for (i = 1; i <= dev->caps.num_ports; ++i) {
219 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 220 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
5ae2a7a8
RD		 221 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
222 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
223 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 224 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
225 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 226 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 227 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
228 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 229 dev->caps.trans_type[i] = dev_cap->trans_type[i];
230 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
231 dev->caps.wavelength[i] = dev_cap->wavelength[i];
232 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 233 }
234
ab9c17a0 235 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 236 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 237 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
238 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
239 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
240 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
241 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
242 dev->caps.max_wqes = dev_cap->max_qp_sz;
243 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 244 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
245 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
246 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
247 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
248 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 249 /*
250 * Subtract 1 from the limit because we need to allocate a
251 * spare CQE so the HCA HW can tell the difference between an
252 * empty CQ and a full CQ.
253 */
254 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
255 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
256 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 257 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 258 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 259
260 /* The first 128 UARs are used for EQ doorbells */
261 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 262 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 263 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
264 dev_cap->reserved_xrcds : 0;
265 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
266 dev_cap->max_xrcds : 0;
2b8fb286
MA		 267 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
268
149983af 269 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 270 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
271 dev->caps.flags = dev_cap->flags;
b3416f44 272 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 273 dev->caps.bmme_flags = dev_cap->bmme_flags;
274 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 275 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 276 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 277 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 278
0ff1fb65
HHZ		 279 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
280 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
281 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
282 dev->caps.fs_log_max_ucast_qp_range_size =
283 dev_cap->fs_log_max_ucast_qp_range_size;
c96d97f4 284 } else {
0ff1fb65
HHZ		 285 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
286 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) {
287 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
288 } else {
289 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
c96d97f4 290
0ff1fb65
HHZ		 291 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
292 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
293 mlx4_warn(dev, "Must have UC_STEER and MC_STEER flags "
294 "set to use B0 steering. Falling back to A0 steering mode.\n");
295 }
296 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
c96d97f4
HHZ		 297 }
298 mlx4_dbg(dev, "Steering mode is: %s\n",
299 mlx4_steering_mode_str(dev->caps.steering_mode));
c96d97f4 300
58a60168
YP		 301 /* Sense port always allowed on supported devices for ConnectX1 and 2 */
302 if (dev->pdev->device != 0x1003)
303 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
304
93fc9e1b 305 dev->caps.log_num_macs = log_num_mac;
cb29688a 306 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 307 dev->caps.log_num_prios = use_prio ? 3 : 0;
308
309 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 310 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
311 if (dev->caps.supported_type[i]) {
312 /* if only ETH is supported - assign ETH */
313 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
314 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
315 /* if only IB is supported,
316 * assign IB only if SRIOV is off*/
317 else if (dev->caps.supported_type[i] ==
318 MLX4_PORT_TYPE_IB) {
319 if (dev->flags & MLX4_FLAG_SRIOV)
320 dev->caps.port_type[i] =
321 MLX4_PORT_TYPE_NONE;
322 else
323 dev->caps.port_type[i] =
324 MLX4_PORT_TYPE_IB;
325 /* if IB and ETH are supported,
326 * first of all check if SRIOV is on */
327 } else if (dev->flags & MLX4_FLAG_SRIOV)
328 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
ab9c17a0 329 else {
8d0fc7b6
YP		 330 /* In non-SRIOV mode, we set the port type
331 * according to user selection of port type,
332 * if usere selected none, take the FW hint */
333 if (port_type_array[i-1] == MLX4_PORT_TYPE_NONE)
334 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
335 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 336 else
8d0fc7b6 337 dev->caps.port_type[i] = port_type_array[i-1];
ab9c17a0
JM		 338 }
339 }
8d0fc7b6
YP		 340 /*
341 * Link sensing is allowed on the port if 3 conditions are true:
342 * 1. Both protocols are supported on the port.
343 * 2. Different types are supported on the port
344 * 3. FW declared that it supports link sensing
345 */
27bf91d6 346 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 347 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 348 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 349 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 350
8d0fc7b6
YP		 351 /*
352 * If "default_sense" bit is set, we move the port to "AUTO" mode
353 * and perform sense_port FW command to try and set the correct
354 * port type from beginning
355 */
46c46747 356 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 357 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
358 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
359 mlx4_SENSE_PORT(dev, i, &sensed_port);
360 if (sensed_port != MLX4_PORT_TYPE_NONE)
361 dev->caps.port_type[i] = sensed_port;
362 } else {
363 dev->caps.possible_type[i] = dev->caps.port_type[i];
364 }
365
93fc9e1b
YP		 366 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
367 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
368 mlx4_warn(dev, "Requested number of MACs is too much "
369 "for port %d, reducing to %d.\n",
370 i, 1 << dev->caps.log_num_macs);
371 }
372 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
373 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
374 mlx4_warn(dev, "Requested number of VLANs is too much "
375 "for port %d, reducing to %d.\n",
376 i, 1 << dev->caps.log_num_vlans);
377 }
378 }
379
f2a3f6a3
OG		 380 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
381
93fc9e1b
YP		 382 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
383 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
384 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
385 (1 << dev->caps.log_num_macs) *
386 (1 << dev->caps.log_num_vlans) *
387 (1 << dev->caps.log_num_prios) *
388 dev->caps.num_ports;
389 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
390
391 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
392 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
393 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
394 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
395
225c7b1f
RD		 396 return 0;
397}
ab9c17a0
JM		 398/*The function checks if there are live vf, return the num of them*/
399static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
400{
401 struct mlx4_priv *priv = mlx4_priv(dev);
402 struct mlx4_slave_state *s_state;
403 int i;
404 int ret = 0;
405
406 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
407 s_state = &priv->mfunc.master.slave_state[i];
408 if (s_state->active && s_state->last_cmd !=
409 MLX4_COMM_CMD_RESET) {
410 mlx4_warn(dev, "%s: slave: %d is still active\n",
411 __func__, i);
412 ret++;
413 }
414 }
415 return ret;
416}
417
e10903b0 418int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 419{
420 struct mlx4_priv *priv = mlx4_priv(dev);
421 struct mlx4_slave_state *s_slave;
422
423 if (!mlx4_is_master(dev))
424 return 0;
425
426 s_slave = &priv->mfunc.master.slave_state[slave];
427 return !!s_slave->active;
428}
429EXPORT_SYMBOL(mlx4_is_slave_active);
430
431static int mlx4_slave_cap(struct mlx4_dev *dev)
432{
433 int err;
434 u32 page_size;
435 struct mlx4_dev_cap dev_cap;
436 struct mlx4_func_cap func_cap;
437 struct mlx4_init_hca_param hca_param;
438 int i;
439
440 memset(&hca_param, 0, sizeof(hca_param));
441 err = mlx4_QUERY_HCA(dev, &hca_param);
442 if (err) {
443 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
444 return err;
445 }
446
447 /*fail if the hca has an unknown capability */
448 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
449 HCA_GLOBAL_CAP_MASK) {
450 mlx4_err(dev, "Unknown hca global capabilities\n");
451 return -ENOSYS;
452 }
453
454 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
455
456 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 457 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 458 err = mlx4_dev_cap(dev, &dev_cap);
459 if (err) {
460 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
461 return err;
462 }
463
b91cb3eb
JM		 464 err = mlx4_QUERY_FW(dev);
465 if (err)
466 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
467
ab9c17a0
JM		 468 page_size = ~dev->caps.page_size_cap + 1;
469 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
470 if (page_size > PAGE_SIZE) {
471 mlx4_err(dev, "HCA minimum page size of %d bigger than "
472 "kernel PAGE_SIZE of %ld, aborting.\n",
473 page_size, PAGE_SIZE);
474 return -ENODEV;
475 }
476
477 /* slave gets uar page size from QUERY_HCA fw command */
478 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
479
480 /* TODO: relax this assumption */
481 if (dev->caps.uar_page_size != PAGE_SIZE) {
482 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
483 dev->caps.uar_page_size, PAGE_SIZE);
484 return -ENODEV;
485 }
486
487 memset(&func_cap, 0, sizeof(func_cap));
488 err = mlx4_QUERY_FUNC_CAP(dev, &func_cap);
489 if (err) {
490 mlx4_err(dev, "QUERY_FUNC_CAP command failed, aborting.\n");
491 return err;
492 }
493
494 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
495 PF_CONTEXT_BEHAVIOUR_MASK) {
496 mlx4_err(dev, "Unknown pf context behaviour\n");
497 return -ENOSYS;
498 }
499
ab9c17a0
JM		 500 dev->caps.num_ports = func_cap.num_ports;
501 dev->caps.num_qps = func_cap.qp_quota;
502 dev->caps.num_srqs = func_cap.srq_quota;
503 dev->caps.num_cqs = func_cap.cq_quota;
504 dev->caps.num_eqs = func_cap.max_eq;
505 dev->caps.reserved_eqs = func_cap.reserved_eq;
506 dev->caps.num_mpts = func_cap.mpt_quota;
507 dev->caps.num_mtts = func_cap.mtt_quota;
508 dev->caps.num_pds = MLX4_NUM_PDS;
509 dev->caps.num_mgms = 0;
510 dev->caps.num_amgms = 0;
511
ab9c17a0
JM		 512 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
513 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
514 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
515 return -ENODEV;
516 }
517
6230bb23
JM		 518 for (i = 1; i <= dev->caps.num_ports; ++i)
519 dev->caps.port_mask[i] = dev->caps.port_type[i];
520
ab9c17a0
JM		 521 if (dev->caps.uar_page_size * (dev->caps.num_uars -
522 dev->caps.reserved_uars) >
523 pci_resource_len(dev->pdev, 2)) {
524 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
525 "PCI resource 2 size of 0x%llx, aborting.\n",
526 dev->caps.uar_page_size * dev->caps.num_uars,
527 (unsigned long long) pci_resource_len(dev->pdev, 2));
528 return -ENODEV;
529 }
530
ab9c17a0
JM		 531 return 0;
532}
225c7b1f 533
7ff93f8b
YP		 534/*
535 * Change the port configuration of the device.
536 * Every user of this function must hold the port mutex.
537 */
27bf91d6
YP		 538int mlx4_change_port_types(struct mlx4_dev *dev,
539 enum mlx4_port_type *port_types)
7ff93f8b
YP		 540{
541 int err = 0;
542 int change = 0;
543 int port;
544
545 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 546 /* Change the port type only if the new type is different
547 * from the current, and not set to Auto */
3d8f9308 548 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 549 change = 1;
7ff93f8b
YP		 550 }
551 if (change) {
552 mlx4_unregister_device(dev);
553 for (port = 1; port <= dev->caps.num_ports; port++) {
554 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 555 dev->caps.port_type[port] = port_types[port - 1];
7ff93f8b
YP		 556 err = mlx4_SET_PORT(dev, port);
557 if (err) {
558 mlx4_err(dev, "Failed to set port %d, "
559 "aborting\n", port);
560 goto out;
561 }
562 }
563 mlx4_set_port_mask(dev);
564 err = mlx4_register_device(dev);
565 }
566
567out:
568 return err;
569}
570
571static ssize_t show_port_type(struct device *dev,
572 struct device_attribute *attr,
573 char *buf)
574{
575 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
576 port_attr);
577 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 578 char type[8];
579
580 sprintf(type, "%s",
581 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
582 "ib" : "eth");
583 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
584 sprintf(buf, "auto (%s)\n", type);
585 else
586 sprintf(buf, "%s\n", type);
7ff93f8b 587
27bf91d6 588 return strlen(buf);
7ff93f8b
YP		 589}
590
591static ssize_t set_port_type(struct device *dev,
592 struct device_attribute *attr,
593 const char *buf, size_t count)
594{
595 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
596 port_attr);
597 struct mlx4_dev *mdev = info->dev;
598 struct mlx4_priv *priv = mlx4_priv(mdev);
599 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 600 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 601 int i;
602 int err = 0;
603
604 if (!strcmp(buf, "ib\n"))
605 info->tmp_type = MLX4_PORT_TYPE_IB;
606 else if (!strcmp(buf, "eth\n"))
607 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 608 else if (!strcmp(buf, "auto\n"))
609 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 610 else {
611 mlx4_err(mdev, "%s is not supported port type\n", buf);
612 return -EINVAL;
613 }
614
27bf91d6 615 mlx4_stop_sense(mdev);
7ff93f8b 616 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 617 /* Possible type is always the one that was delivered */
618 mdev->caps.possible_type[info->port] = info->tmp_type;
619
620 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 621 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 622 mdev->caps.possible_type[i+1];
623 if (types[i] == MLX4_PORT_TYPE_AUTO)
624 types[i] = mdev->caps.port_type[i+1];
625 }
7ff93f8b 626
58a60168
YP		 627 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
628 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 629 for (i = 1; i <= mdev->caps.num_ports; i++) {
630 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
631 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
632 err = -EINVAL;
633 }
634 }
635 }
636 if (err) {
637 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
638 "Set only 'eth' or 'ib' for both ports "
639 "(should be the same)\n");
640 goto out;
641 }
642
643 mlx4_do_sense_ports(mdev, new_types, types);
644
645 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 646 if (err)
647 goto out;
648
27bf91d6
YP		 649 /* We are about to apply the changes after the configuration
650 * was verified, no need to remember the temporary types
651 * any more */
652 for (i = 0; i < mdev->caps.num_ports; i++)
653 priv->port[i + 1].tmp_type = 0;
7ff93f8b 654
27bf91d6 655 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 656
657out:
27bf91d6 658 mlx4_start_sense(mdev);
7ff93f8b
YP		 659 mutex_unlock(&priv->port_mutex);
660 return err ? err : count;
661}
662
096335b3
OG		 663enum ibta_mtu {
664 IB_MTU_256 = 1,
665 IB_MTU_512 = 2,
666 IB_MTU_1024 = 3,
667 IB_MTU_2048 = 4,
668 IB_MTU_4096 = 5
669};
670
671static inline int int_to_ibta_mtu(int mtu)
672{
673 switch (mtu) {
674 case 256: return IB_MTU_256;
675 case 512: return IB_MTU_512;
676 case 1024: return IB_MTU_1024;
677 case 2048: return IB_MTU_2048;
678 case 4096: return IB_MTU_4096;
679 default: return -1;
680 }
681}
682
683static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
684{
685 switch (mtu) {
686 case IB_MTU_256: return 256;
687 case IB_MTU_512: return 512;
688 case IB_MTU_1024: return 1024;
689 case IB_MTU_2048: return 2048;
690 case IB_MTU_4096: return 4096;
691 default: return -1;
692 }
693}
694
695static ssize_t show_port_ib_mtu(struct device *dev,
696 struct device_attribute *attr,
697 char *buf)
698{
699 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
700 port_mtu_attr);
701 struct mlx4_dev *mdev = info->dev;
702
703 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
704 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
705
706 sprintf(buf, "%d\n",
707 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
708 return strlen(buf);
709}
710
711static ssize_t set_port_ib_mtu(struct device *dev,
712 struct device_attribute *attr,
713 const char *buf, size_t count)
714{
715 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
716 port_mtu_attr);
717 struct mlx4_dev *mdev = info->dev;
718 struct mlx4_priv *priv = mlx4_priv(mdev);
719 int err, port, mtu, ibta_mtu = -1;
720
721 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
722 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
723 return -EINVAL;
724 }
725
726 err = sscanf(buf, "%d", &mtu);
727 if (err > 0)
728 ibta_mtu = int_to_ibta_mtu(mtu);
729
730 if (err <= 0 || ibta_mtu < 0) {
731 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
732 return -EINVAL;
733 }
734
735 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
736
737 mlx4_stop_sense(mdev);
738 mutex_lock(&priv->port_mutex);
739 mlx4_unregister_device(mdev);
740 for (port = 1; port <= mdev->caps.num_ports; port++) {
741 mlx4_CLOSE_PORT(mdev, port);
742 err = mlx4_SET_PORT(mdev, port);
743 if (err) {
744 mlx4_err(mdev, "Failed to set port %d, "
745 "aborting\n", port);
746 goto err_set_port;
747 }
748 }
749 err = mlx4_register_device(mdev);
750err_set_port:
751 mutex_unlock(&priv->port_mutex);
752 mlx4_start_sense(mdev);
753 return err ? err : count;
754}
755
e8f9b2ed 756static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 757{
758 struct mlx4_priv *priv = mlx4_priv(dev);
759 int err;
760
761 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 762 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 763 if (!priv->fw.fw_icm) {
764 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
765 return -ENOMEM;
766 }
767
768 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
769 if (err) {
770 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
771 goto err_free;
772 }
773
774 err = mlx4_RUN_FW(dev);
775 if (err) {
776 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
777 goto err_unmap_fa;
778 }
779
780 return 0;
781
782err_unmap_fa:
783 mlx4_UNMAP_FA(dev);
784
785err_free:
5b0bf5e2 786 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 787 return err;
788}
789
e8f9b2ed
RD		 790static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
791 int cmpt_entry_sz)
225c7b1f
RD		 792{
793 struct mlx4_priv *priv = mlx4_priv(dev);
794 int err;
ab9c17a0 795 int num_eqs;
225c7b1f
RD		 796
797 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
798 cmpt_base +
799 ((u64) (MLX4_CMPT_TYPE_QP *
800 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
801 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 802 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
803 0, 0);
225c7b1f
RD		 804 if (err)
805 goto err;
806
807 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
808 cmpt_base +
809 ((u64) (MLX4_CMPT_TYPE_SRQ *
810 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
811 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 812 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 813 if (err)
814 goto err_qp;
815
816 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
817 cmpt_base +
818 ((u64) (MLX4_CMPT_TYPE_CQ *
819 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
820 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 821 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 822 if (err)
823 goto err_srq;
824
3fc929e2
MA		 825 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
826 dev->caps.num_eqs;
225c7b1f
RD		 827 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
828 cmpt_base +
829 ((u64) (MLX4_CMPT_TYPE_EQ *
830 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 831 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 832 if (err)
833 goto err_cq;
834
835 return 0;
836
837err_cq:
838 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
839
840err_srq:
841 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
842
843err_qp:
844 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
845
846err:
847 return err;
848}
849
3d73c288
RD		 850static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
851 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 852{
853 struct mlx4_priv *priv = mlx4_priv(dev);
854 u64 aux_pages;
ab9c17a0 855 int num_eqs;
225c7b1f
RD		 856 int err;
857
858 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
859 if (err) {
860 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
861 return err;
862 }
863
864 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
865 (unsigned long long) icm_size >> 10,
866 (unsigned long long) aux_pages << 2);
867
868 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 869 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 870 if (!priv->fw.aux_icm) {
871 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
872 return -ENOMEM;
873 }
874
875 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
876 if (err) {
877 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
878 goto err_free_aux;
879 }
880
881 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
882 if (err) {
883 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
884 goto err_unmap_aux;
885 }
886
ab9c17a0 887
3fc929e2
MA		 888 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
889 dev->caps.num_eqs;
fa0681d2
RD		 890 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
891 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 892 num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 893 if (err) {
894 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
895 goto err_unmap_cmpt;
896 }
897
d7bb58fb
JM		 898 /*
899 * Reserved MTT entries must be aligned up to a cacheline
900 * boundary, since the FW will write to them, while the driver
901 * writes to all other MTT entries. (The variable
902 * dev->caps.mtt_entry_sz below is really the MTT segment
903 * size, not the raw entry size)
904 */
905 dev->caps.reserved_mtts =
906 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
907 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
908
225c7b1f
RD		 909 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
910 init_hca->mtt_base,
911 dev->caps.mtt_entry_sz,
2b8fb286 912 dev->caps.num_mtts,
5b0bf5e2 913 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 914 if (err) {
915 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
916 goto err_unmap_eq;
917 }
918
919 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
920 init_hca->dmpt_base,
921 dev_cap->dmpt_entry_sz,
922 dev->caps.num_mpts,
5b0bf5e2 923 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 924 if (err) {
925 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
926 goto err_unmap_mtt;
927 }
928
929 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
930 init_hca->qpc_base,
931 dev_cap->qpc_entry_sz,
932 dev->caps.num_qps,
93fc9e1b
YP		 933 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
934 0, 0);
225c7b1f
RD		 935 if (err) {
936 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
937 goto err_unmap_dmpt;
938 }
939
940 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
941 init_hca->auxc_base,
942 dev_cap->aux_entry_sz,
943 dev->caps.num_qps,
93fc9e1b
YP		 944 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
945 0, 0);
225c7b1f
RD		 946 if (err) {
947 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
948 goto err_unmap_qp;
949 }
950
951 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
952 init_hca->altc_base,
953 dev_cap->altc_entry_sz,
954 dev->caps.num_qps,
93fc9e1b
YP		 955 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
956 0, 0);
225c7b1f
RD		 957 if (err) {
958 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
959 goto err_unmap_auxc;
960 }
961
962 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
963 init_hca->rdmarc_base,
964 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
965 dev->caps.num_qps,
93fc9e1b
YP		 966 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
967 0, 0);
225c7b1f
RD		 968 if (err) {
969 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
970 goto err_unmap_altc;
971 }
972
973 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
974 init_hca->cqc_base,
975 dev_cap->cqc_entry_sz,
976 dev->caps.num_cqs,
5b0bf5e2 977 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 978 if (err) {
979 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
980 goto err_unmap_rdmarc;
981 }
982
983 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
984 init_hca->srqc_base,
985 dev_cap->srq_entry_sz,
986 dev->caps.num_srqs,
5b0bf5e2 987 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 988 if (err) {
989 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
990 goto err_unmap_cq;
991 }
992
993 /*
0ff1fb65
HHZ		 994 * For flow steering device managed mode it is required to use
995 * mlx4_init_icm_table. For B0 steering mode it's not strictly
996 * required, but for simplicity just map the whole multicast
997 * group table now. The table isn't very big and it's a lot
998 * easier than trying to track ref counts.
225c7b1f
RD		 999 */
1000 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1001 init_hca->mc_base,
1002 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1003 dev->caps.num_mgms + dev->caps.num_amgms,
1004 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1005 0, 0);
225c7b1f
RD		 1006 if (err) {
1007 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1008 goto err_unmap_srq;
1009 }
1010
1011 return 0;
1012
1013err_unmap_srq:
1014 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1015
1016err_unmap_cq:
1017 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1018
1019err_unmap_rdmarc:
1020 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1021
1022err_unmap_altc:
1023 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1024
1025err_unmap_auxc:
1026 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1027
1028err_unmap_qp:
1029 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1030
1031err_unmap_dmpt:
1032 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1033
1034err_unmap_mtt:
1035 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1036
1037err_unmap_eq:
fa0681d2 1038 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1039
1040err_unmap_cmpt:
1041 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1042 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1043 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1044 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1045
1046err_unmap_aux:
1047 mlx4_UNMAP_ICM_AUX(dev);
1048
1049err_free_aux:
5b0bf5e2 1050 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1051
1052 return err;
1053}
1054
1055static void mlx4_free_icms(struct mlx4_dev *dev)
1056{
1057 struct mlx4_priv *priv = mlx4_priv(dev);
1058
1059 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1060 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1061 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1062 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1063 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1064 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1065 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1066 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1067 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1068 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1069 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1070 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1071 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1072 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1073
1074 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1075 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1076}
1077
ab9c17a0
JM		 1078static void mlx4_slave_exit(struct mlx4_dev *dev)
1079{
1080 struct mlx4_priv *priv = mlx4_priv(dev);
1081
1082 down(&priv->cmd.slave_sem);
1083 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1084 mlx4_warn(dev, "Failed to close slave function.\n");
1085 up(&priv->cmd.slave_sem);
1086}
1087
c1b43dca
EC		 1088static int map_bf_area(struct mlx4_dev *dev)
1089{
1090 struct mlx4_priv *priv = mlx4_priv(dev);
1091 resource_size_t bf_start;
1092 resource_size_t bf_len;
1093 int err = 0;
1094
3d747473
JM		 1095 if (!dev->caps.bf_reg_size)
1096 return -ENXIO;
1097
ab9c17a0
JM		 1098 bf_start = pci_resource_start(dev->pdev, 2) +
1099 (dev->caps.num_uars << PAGE_SHIFT);
1100 bf_len = pci_resource_len(dev->pdev, 2) -
1101 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1102 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1103 if (!priv->bf_mapping)
1104 err = -ENOMEM;
1105
1106 return err;
1107}
1108
1109static void unmap_bf_area(struct mlx4_dev *dev)
1110{
1111 if (mlx4_priv(dev)->bf_mapping)
1112 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1113}
1114
225c7b1f
RD		 1115static void mlx4_close_hca(struct mlx4_dev *dev)
1116{
c1b43dca 1117 unmap_bf_area(dev);
ab9c17a0
JM		 1118 if (mlx4_is_slave(dev))
1119 mlx4_slave_exit(dev);
1120 else {
1121 mlx4_CLOSE_HCA(dev, 0);
1122 mlx4_free_icms(dev);
1123 mlx4_UNMAP_FA(dev);
1124 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1125 }
1126}
1127
1128static int mlx4_init_slave(struct mlx4_dev *dev)
1129{
1130 struct mlx4_priv *priv = mlx4_priv(dev);
1131 u64 dma = (u64) priv->mfunc.vhcr_dma;
1132 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1133 int ret_from_reset = 0;
1134 u32 slave_read;
1135 u32 cmd_channel_ver;
1136
1137 down(&priv->cmd.slave_sem);
1138 priv->cmd.max_cmds = 1;
1139 mlx4_warn(dev, "Sending reset\n");
1140 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1141 MLX4_COMM_TIME);
1142 /* if we are in the middle of flr the slave will try
1143 * NUM_OF_RESET_RETRIES times before leaving.*/
1144 if (ret_from_reset) {
1145 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1146 msleep(SLEEP_TIME_IN_RESET);
1147 while (ret_from_reset && num_of_reset_retries) {
1148 mlx4_warn(dev, "slave is currently in the"
1149 "middle of FLR. retrying..."
1150 "(try num:%d)\n",
1151 (NUM_OF_RESET_RETRIES -
1152 num_of_reset_retries + 1));
1153 ret_from_reset =
1154 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1155 0, MLX4_COMM_TIME);
1156 num_of_reset_retries = num_of_reset_retries - 1;
1157 }
1158 } else
1159 goto err;
1160 }
1161
1162 /* check the driver version - the slave I/F revision
1163 * must match the master's */
1164 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1165 cmd_channel_ver = mlx4_comm_get_version();
1166
1167 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1168 MLX4_COMM_GET_IF_REV(slave_read)) {
1169 mlx4_err(dev, "slave driver version is not supported"
1170 " by the master\n");
1171 goto err;
1172 }
1173
1174 mlx4_warn(dev, "Sending vhcr0\n");
1175 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1176 MLX4_COMM_TIME))
1177 goto err;
1178 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1179 MLX4_COMM_TIME))
1180 goto err;
1181 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1182 MLX4_COMM_TIME))
1183 goto err;
1184 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1185 goto err;
1186 up(&priv->cmd.slave_sem);
1187 return 0;
1188
1189err:
1190 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1191 up(&priv->cmd.slave_sem);
1192 return -EIO;
225c7b1f
RD		 1193}
1194
3d73c288 1195static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1196{
1197 struct mlx4_priv *priv = mlx4_priv(dev);
1198 struct mlx4_adapter adapter;
1199 struct mlx4_dev_cap dev_cap;
2d928651 1200 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1201 struct mlx4_profile profile;
1202 struct mlx4_init_hca_param init_hca;
1203 u64 icm_size;
1204 int err;
1205
ab9c17a0
JM		 1206 if (!mlx4_is_slave(dev)) {
1207 err = mlx4_QUERY_FW(dev);
1208 if (err) {
1209 if (err == -EACCES)
1210 mlx4_info(dev, "non-primary physical function, skipping.\n");
1211 else
1212 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1213 goto unmap_bf;
1214 }
225c7b1f 1215
ab9c17a0
JM		 1216 err = mlx4_load_fw(dev);
1217 if (err) {
1218 mlx4_err(dev, "Failed to start FW, aborting.\n");
1219 goto unmap_bf;
1220 }
225c7b1f 1221
ab9c17a0
JM		 1222 mlx4_cfg.log_pg_sz_m = 1;
1223 mlx4_cfg.log_pg_sz = 0;
1224 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1225 if (err)
1226 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1227
ab9c17a0
JM		 1228 err = mlx4_dev_cap(dev, &dev_cap);
1229 if (err) {
1230 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1231 goto err_stop_fw;
1232 }
225c7b1f 1233
0ff1fb65
HHZ		 1234 priv->fs_hash_mode = MLX4_FS_L2_HASH;
1235
1236 switch (priv->fs_hash_mode) {
1237 case MLX4_FS_L2_HASH:
1238 init_hca.fs_hash_enable_bits = 0;
1239 break;
1240
1241 case MLX4_FS_L2_L3_L4_HASH:
1242 /* Enable flow steering with
1243 * udp unicast and tcp unicast
1244 */
1245 init_hca.fs_hash_enable_bits =
1246 MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN;
1247 break;
1248 }
1249
ab9c17a0 1250 profile = default_profile;
0ff1fb65
HHZ		 1251 if (dev->caps.steering_mode ==
1252 MLX4_STEERING_MODE_DEVICE_MANAGED)
1253 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1254
ab9c17a0
JM		 1255 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1256 &init_hca);
1257 if ((long long) icm_size < 0) {
1258 err = icm_size;
1259 goto err_stop_fw;
1260 }
225c7b1f 1261
a5bbe892
EC		 1262 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1263
ab9c17a0
JM		 1264 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1265 init_hca.uar_page_sz = PAGE_SHIFT - 12;
c1b43dca 1266
ab9c17a0
JM		 1267 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1268 if (err)
1269 goto err_stop_fw;
225c7b1f 1270
ab9c17a0
JM		 1271 err = mlx4_INIT_HCA(dev, &init_hca);
1272 if (err) {
1273 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1274 goto err_free_icm;
1275 }
1276 } else {
1277 err = mlx4_init_slave(dev);
1278 if (err) {
1279 mlx4_err(dev, "Failed to initialize slave\n");
1280 goto unmap_bf;
1281 }
225c7b1f 1282
ab9c17a0
JM		 1283 err = mlx4_slave_cap(dev);
1284 if (err) {
1285 mlx4_err(dev, "Failed to obtain slave caps\n");
1286 goto err_close;
1287 }
225c7b1f
RD		 1288 }
1289
ab9c17a0
JM		 1290 if (map_bf_area(dev))
1291 mlx4_dbg(dev, "Failed to map blue flame area\n");
1292
1293 /*Only the master set the ports, all the rest got it from it.*/
1294 if (!mlx4_is_slave(dev))
1295 mlx4_set_port_mask(dev);
1296
225c7b1f
RD		 1297 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1298 if (err) {
1299 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1300 goto err_close;
1301 }
1302
1303 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1304 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1305
1306 return 0;
1307
1308err_close:
ab9c17a0 1309 mlx4_close_hca(dev);
225c7b1f
RD		 1310
1311err_free_icm:
ab9c17a0
JM		 1312 if (!mlx4_is_slave(dev))
1313 mlx4_free_icms(dev);
225c7b1f
RD		 1314
1315err_stop_fw:
ab9c17a0
JM		 1316 if (!mlx4_is_slave(dev)) {
1317 mlx4_UNMAP_FA(dev);
1318 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1319 }
1320unmap_bf:
c1b43dca 1321 unmap_bf_area(dev);
225c7b1f
RD		 1322 return err;
1323}
1324
f2a3f6a3
OG		 1325static int mlx4_init_counters_table(struct mlx4_dev *dev)
1326{
1327 struct mlx4_priv *priv = mlx4_priv(dev);
1328 int nent;
1329
1330 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1331 return -ENOENT;
1332
1333 nent = dev->caps.max_counters;
1334 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1335}
1336
1337static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1338{
1339 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1340}
1341
ba062d52 1342int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1343{
1344 struct mlx4_priv *priv = mlx4_priv(dev);
1345
1346 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1347 return -ENOENT;
1348
1349 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1350 if (*idx == -1)
1351 return -ENOMEM;
1352
1353 return 0;
1354}
ba062d52
JM		 1355
1356int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1357{
1358 u64 out_param;
1359 int err;
1360
1361 if (mlx4_is_mfunc(dev)) {
1362 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1363 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1364 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1365 if (!err)
1366 *idx = get_param_l(&out_param);
1367
1368 return err;
1369 }
1370 return __mlx4_counter_alloc(dev, idx);
1371}
f2a3f6a3
OG		 1372EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1373
ba062d52 1374void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3
OG		 1375{
1376 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1377 return;
1378}
ba062d52
JM		 1379
1380void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1381{
1382 u64 in_param;
1383
1384 if (mlx4_is_mfunc(dev)) {
1385 set_param_l(&in_param, idx);
1386 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1387 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1388 MLX4_CMD_WRAPPED);
1389 return;
1390 }
1391 __mlx4_counter_free(dev, idx);
1392}
f2a3f6a3
OG		 1393EXPORT_SYMBOL_GPL(mlx4_counter_free);
1394
3d73c288 1395static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1396{
1397 struct mlx4_priv *priv = mlx4_priv(dev);
1398 int err;
7ff93f8b 1399 int port;
9a5aa622 1400 __be32 ib_port_default_caps;
225c7b1f 1401
225c7b1f
RD		 1402 err = mlx4_init_uar_table(dev);
1403 if (err) {
1404 mlx4_err(dev, "Failed to initialize "
1405 "user access region table, aborting.\n");
1406 return err;
1407 }
1408
1409 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1410 if (err) {
1411 mlx4_err(dev, "Failed to allocate driver access region, "
1412 "aborting.\n");
1413 goto err_uar_table_free;
1414 }
1415
4979d18f 1416 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f
RD		 1417 if (!priv->kar) {
1418 mlx4_err(dev, "Couldn't map kernel access region, "
1419 "aborting.\n");
1420 err = -ENOMEM;
1421 goto err_uar_free;
1422 }
1423
1424 err = mlx4_init_pd_table(dev);
1425 if (err) {
1426 mlx4_err(dev, "Failed to initialize "
1427 "protection domain table, aborting.\n");
1428 goto err_kar_unmap;
1429 }
1430
012a8ff5
SH		 1431 err = mlx4_init_xrcd_table(dev);
1432 if (err) {
1433 mlx4_err(dev, "Failed to initialize "
1434 "reliable connection domain table, aborting.\n");
1435 goto err_pd_table_free;
1436 }
1437
225c7b1f
RD		 1438 err = mlx4_init_mr_table(dev);
1439 if (err) {
1440 mlx4_err(dev, "Failed to initialize "
1441 "memory region table, aborting.\n");
012a8ff5 1442 goto err_xrcd_table_free;
225c7b1f
RD		 1443 }
1444
225c7b1f
RD		 1445 err = mlx4_init_eq_table(dev);
1446 if (err) {
1447 mlx4_err(dev, "Failed to initialize "
1448 "event queue table, aborting.\n");
ee49bd93 1449 goto err_mr_table_free;
225c7b1f
RD		 1450 }
1451
1452 err = mlx4_cmd_use_events(dev);
1453 if (err) {
1454 mlx4_err(dev, "Failed to switch to event-driven "
1455 "firmware commands, aborting.\n");
1456 goto err_eq_table_free;
1457 }
1458
1459 err = mlx4_NOP(dev);
1460 if (err) {
08fb1055
MT		 1461 if (dev->flags & MLX4_FLAG_MSI_X) {
1462 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1463 "interrupt IRQ %d).\n",
b8dd786f 1464 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 1465 mlx4_warn(dev, "Trying again without MSI-X.\n");
1466 } else {
1467 mlx4_err(dev, "NOP command failed to generate interrupt "
1468 "(IRQ %d), aborting.\n",
b8dd786f 1469 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1470 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1471 }
225c7b1f
RD		 1472
1473 goto err_cmd_poll;
1474 }
1475
1476 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1477
1478 err = mlx4_init_cq_table(dev);
1479 if (err) {
1480 mlx4_err(dev, "Failed to initialize "
1481 "completion queue table, aborting.\n");
1482 goto err_cmd_poll;
1483 }
1484
1485 err = mlx4_init_srq_table(dev);
1486 if (err) {
1487 mlx4_err(dev, "Failed to initialize "
1488 "shared receive queue table, aborting.\n");
1489 goto err_cq_table_free;
1490 }
1491
1492 err = mlx4_init_qp_table(dev);
1493 if (err) {
1494 mlx4_err(dev, "Failed to initialize "
1495 "queue pair table, aborting.\n");
1496 goto err_srq_table_free;
1497 }
1498
ab9c17a0
JM		 1499 if (!mlx4_is_slave(dev)) {
1500 err = mlx4_init_mcg_table(dev);
1501 if (err) {
1502 mlx4_err(dev, "Failed to initialize "
1503 "multicast group table, aborting.\n");
1504 goto err_qp_table_free;
1505 }
225c7b1f
RD		 1506 }
1507
f2a3f6a3
OG		 1508 err = mlx4_init_counters_table(dev);
1509 if (err && err != -ENOENT) {
1510 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
ab9c17a0 1511 goto err_mcg_table_free;
f2a3f6a3
OG		 1512 }
1513
ab9c17a0
JM		 1514 if (!mlx4_is_slave(dev)) {
1515 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1516 ib_port_default_caps = 0;
1517 err = mlx4_get_port_ib_caps(dev, port,
1518 &ib_port_default_caps);
1519 if (err)
1520 mlx4_warn(dev, "failed to get port %d default "
1521 "ib capabilities (%d). Continuing "
1522 "with caps = 0\n", port, err);
1523 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1524
096335b3
OG		 1525 if (mlx4_is_mfunc(dev))
1526 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1527 else
1528 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 1529
ab9c17a0
JM		 1530 err = mlx4_SET_PORT(dev, port);
1531 if (err) {
1532 mlx4_err(dev, "Failed to set port %d, aborting\n",
1533 port);
1534 goto err_counters_table_free;
1535 }
7ff93f8b
YP		 1536 }
1537 }
1538
225c7b1f
RD		 1539 return 0;
1540
f2a3f6a3
OG		 1541err_counters_table_free:
1542 mlx4_cleanup_counters_table(dev);
1543
ab9c17a0
JM		 1544err_mcg_table_free:
1545 mlx4_cleanup_mcg_table(dev);
1546
225c7b1f
RD		 1547err_qp_table_free:
1548 mlx4_cleanup_qp_table(dev);
1549
1550err_srq_table_free:
1551 mlx4_cleanup_srq_table(dev);
1552
1553err_cq_table_free:
1554 mlx4_cleanup_cq_table(dev);
1555
1556err_cmd_poll:
1557 mlx4_cmd_use_polling(dev);
1558
1559err_eq_table_free:
1560 mlx4_cleanup_eq_table(dev);
1561
ee49bd93 1562err_mr_table_free:
225c7b1f
RD		 1563 mlx4_cleanup_mr_table(dev);
1564
012a8ff5
SH		 1565err_xrcd_table_free:
1566 mlx4_cleanup_xrcd_table(dev);
1567
225c7b1f
RD		 1568err_pd_table_free:
1569 mlx4_cleanup_pd_table(dev);
1570
1571err_kar_unmap:
1572 iounmap(priv->kar);
1573
1574err_uar_free:
1575 mlx4_uar_free(dev, &priv->driver_uar);
1576
1577err_uar_table_free:
1578 mlx4_cleanup_uar_table(dev);
1579 return err;
1580}
1581
e8f9b2ed 1582static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 1583{
1584 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 1585 struct msix_entry *entries;
0b7ca5a9 1586 int nreq = min_t(int, dev->caps.num_ports *
90b1ebe7
YM		 1587 min_t(int, netif_get_num_default_rss_queues() + 1,
1588 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 1589 int err;
1590 int i;
1591
1592 if (msi_x) {
ab9c17a0
JM		 1593 /* In multifunction mode each function gets 2 msi-X vectors
1594 * one for data path completions anf the other for asynch events
1595 * or command completions */
1596 if (mlx4_is_mfunc(dev)) {
1597 nreq = 2;
1598 } else {
1599 nreq = min_t(int, dev->caps.num_eqs -
1600 dev->caps.reserved_eqs, nreq);
1601 }
1602
b8dd786f
YP		 1603 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1604 if (!entries)
1605 goto no_msi;
1606
1607 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1608 entries[i].entry = i;
1609
b8dd786f
YP		 1610 retry:
1611 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 1612 if (err) {
b8dd786f
YP		 1613 /* Try again if at least 2 vectors are available */
1614 if (err > 1) {
1615 mlx4_info(dev, "Requested %d vectors, "
1616 "but only %d MSI-X vectors available, "
1617 "trying again\n", nreq, err);
1618 nreq = err;
1619 goto retry;
1620 }
5bf0da7d 1621 kfree(entries);
225c7b1f
RD		 1622 goto no_msi;
1623 }
1624
0b7ca5a9
YP		 1625 if (nreq <
1626 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1627 /*Working in legacy mode , all EQ's shared*/
1628 dev->caps.comp_pool = 0;
1629 dev->caps.num_comp_vectors = nreq - 1;
1630 } else {
1631 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1632 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1633 }
b8dd786f 1634 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1635 priv->eq_table.eq[i].irq = entries[i].vector;
1636
1637 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 1638
1639 kfree(entries);
225c7b1f
RD		 1640 return;
1641 }
1642
1643no_msi:
b8dd786f 1644 dev->caps.num_comp_vectors = 1;
0b7ca5a9 1645 dev->caps.comp_pool = 0;
b8dd786f
YP		 1646
1647 for (i = 0; i < 2; ++i)
225c7b1f
RD		 1648 priv->eq_table.eq[i].irq = dev->pdev->irq;
1649}
1650
7ff93f8b 1651static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 1652{
1653 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 1654 int err = 0;
2a2336f8
YP		 1655
1656 info->dev = dev;
1657 info->port = port;
ab9c17a0
JM		 1658 if (!mlx4_is_slave(dev)) {
1659 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL);
1660 mlx4_init_mac_table(dev, &info->mac_table);
1661 mlx4_init_vlan_table(dev, &info->vlan_table);
1662 info->base_qpn =
1663 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
06fa0a88 1664 (port - 1) * (1 << log_num_mac);
ab9c17a0 1665 }
7ff93f8b
YP		 1666
1667 sprintf(info->dev_name, "mlx4_port%d", port);
1668 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 1669 if (mlx4_is_mfunc(dev))
1670 info->port_attr.attr.mode = S_IRUGO;
1671 else {
1672 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1673 info->port_attr.store = set_port_type;
1674 }
7ff93f8b 1675 info->port_attr.show = show_port_type;
3691c964 1676 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 1677
1678 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1679 if (err) {
1680 mlx4_err(dev, "Failed to create file for port %d\n", port);
1681 info->port = -1;
1682 }
1683
096335b3
OG		 1684 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1685 info->port_mtu_attr.attr.name = info->dev_mtu_name;
1686 if (mlx4_is_mfunc(dev))
1687 info->port_mtu_attr.attr.mode = S_IRUGO;
1688 else {
1689 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1690 info->port_mtu_attr.store = set_port_ib_mtu;
1691 }
1692 info->port_mtu_attr.show = show_port_ib_mtu;
1693 sysfs_attr_init(&info->port_mtu_attr.attr);
1694
1695 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1696 if (err) {
1697 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1698 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1699 info->port = -1;
1700 }
1701
7ff93f8b
YP		 1702 return err;
1703}
1704
1705static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1706{
1707 if (info->port < 0)
1708 return;
1709
1710 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 1711 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 1712}
1713
b12d93d6
YP		 1714static int mlx4_init_steering(struct mlx4_dev *dev)
1715{
1716 struct mlx4_priv *priv = mlx4_priv(dev);
1717 int num_entries = dev->caps.num_ports;
1718 int i, j;
1719
1720 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1721 if (!priv->steer)
1722 return -ENOMEM;
1723
45b51365 1724 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 1725 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1726 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1727 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1728 }
b12d93d6
YP		 1729 return 0;
1730}
1731
1732static void mlx4_clear_steering(struct mlx4_dev *dev)
1733{
1734 struct mlx4_priv *priv = mlx4_priv(dev);
1735 struct mlx4_steer_index *entry, *tmp_entry;
1736 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1737 int num_entries = dev->caps.num_ports;
1738 int i, j;
1739
1740 for (i = 0; i < num_entries; i++) {
1741 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1742 list_for_each_entry_safe(pqp, tmp_pqp,
1743 &priv->steer[i].promisc_qps[j],
1744 list) {
1745 list_del(&pqp->list);
1746 kfree(pqp);
1747 }
1748 list_for_each_entry_safe(entry, tmp_entry,
1749 &priv->steer[i].steer_entries[j],
1750 list) {
1751 list_del(&entry->list);
1752 list_for_each_entry_safe(pqp, tmp_pqp,
1753 &entry->duplicates,
1754 list) {
1755 list_del(&pqp->list);
1756 kfree(pqp);
1757 }
1758 kfree(entry);
1759 }
1760 }
1761 }
1762 kfree(priv->steer);
1763}
1764
ab9c17a0
JM		 1765static int extended_func_num(struct pci_dev *pdev)
1766{
1767 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
1768}
1769
1770#define MLX4_OWNER_BASE 0x8069c
1771#define MLX4_OWNER_SIZE 4
1772
1773static int mlx4_get_ownership(struct mlx4_dev *dev)
1774{
1775 void __iomem *owner;
1776 u32 ret;
1777
1778 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1779 MLX4_OWNER_SIZE);
1780 if (!owner) {
1781 mlx4_err(dev, "Failed to obtain ownership bit\n");
1782 return -ENOMEM;
1783 }
1784
1785 ret = readl(owner);
1786 iounmap(owner);
1787 return (int) !!ret;
1788}
1789
1790static void mlx4_free_ownership(struct mlx4_dev *dev)
1791{
1792 void __iomem *owner;
1793
1794 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1795 MLX4_OWNER_SIZE);
1796 if (!owner) {
1797 mlx4_err(dev, "Failed to obtain ownership bit\n");
1798 return;
1799 }
1800 writel(0, owner);
1801 msleep(1000);
1802 iounmap(owner);
1803}
1804
3d73c288 1805static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
225c7b1f 1806{
225c7b1f
RD		 1807 struct mlx4_priv *priv;
1808 struct mlx4_dev *dev;
1809 int err;
2a2336f8 1810 int port;
225c7b1f 1811
0a645e80 1812 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 1813
1814 err = pci_enable_device(pdev);
1815 if (err) {
1816 dev_err(&pdev->dev, "Cannot enable PCI device, "
1817 "aborting.\n");
1818 return err;
1819 }
ab9c17a0
JM		 1820 if (num_vfs > MLX4_MAX_NUM_VF) {
1821 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
1822 num_vfs, MLX4_MAX_NUM_VF);
1823 return -EINVAL;
1824 }
225c7b1f 1825 /*
ab9c17a0 1826 * Check for BARs.
225c7b1f 1827 */
ab9c17a0
JM		 1828 if (((id == NULL) || !(id->driver_data & MLX4_VF)) &&
1829 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1830 dev_err(&pdev->dev, "Missing DCS, aborting."
1831 "(id == 0X%p, id->driver_data: 0x%lx,"
1832 " pci_resource_flags(pdev, 0):0x%lx)\n", id,
1833 id ? id->driver_data : 0, pci_resource_flags(pdev, 0));
225c7b1f
RD		 1834 err = -ENODEV;
1835 goto err_disable_pdev;
1836 }
1837 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1838 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1839 err = -ENODEV;
1840 goto err_disable_pdev;
1841 }
1842
a01df0fe 1843 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 1844 if (err) {
a01df0fe 1845 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 1846 goto err_disable_pdev;
1847 }
1848
225c7b1f
RD		 1849 pci_set_master(pdev);
1850
6a35528a 1851 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1852 if (err) {
1853 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 1854 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1855 if (err) {
1856 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 1857 goto err_release_regions;
225c7b1f
RD		 1858 }
1859 }
6a35528a 1860 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1861 if (err) {
1862 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1863 "consistent PCI DMA mask.\n");
284901a9 1864 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1865 if (err) {
1866 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1867 "aborting.\n");
a01df0fe 1868 goto err_release_regions;
225c7b1f
RD		 1869 }
1870 }
1871
7f9e5c48
DD		 1872 /* Allow large DMA segments, up to the firmware limit of 1 GB */
1873 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1874
225c7b1f
RD		 1875 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1876 if (!priv) {
1877 dev_err(&pdev->dev, "Device struct alloc failed, "
1878 "aborting.\n");
1879 err = -ENOMEM;
a01df0fe 1880 goto err_release_regions;
225c7b1f
RD		 1881 }
1882
1883 dev = &priv->dev;
1884 dev->pdev = pdev;
b581401e
RD		 1885 INIT_LIST_HEAD(&priv->ctx_list);
1886 spin_lock_init(&priv->ctx_lock);
225c7b1f 1887
7ff93f8b
YP		 1888 mutex_init(&priv->port_mutex);
1889
6296883c
YP		 1890 INIT_LIST_HEAD(&priv->pgdir_list);
1891 mutex_init(&priv->pgdir_mutex);
1892
c1b43dca
EC		 1893 INIT_LIST_HEAD(&priv->bf_list);
1894 mutex_init(&priv->bf_mutex);
1895
aca7a3ac 1896 dev->rev_id = pdev->revision;
ab9c17a0
JM		 1897 /* Detect if this device is a virtual function */
1898 if (id && id->driver_data & MLX4_VF) {
1899 /* When acting as pf, we normally skip vfs unless explicitly
1900 * requested to probe them. */
1901 if (num_vfs && extended_func_num(pdev) > probe_vf) {
1902 mlx4_warn(dev, "Skipping virtual function:%d\n",
1903 extended_func_num(pdev));
1904 err = -ENODEV;
1905 goto err_free_dev;
1906 }
1907 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
1908 dev->flags |= MLX4_FLAG_SLAVE;
1909 } else {
1910 /* We reset the device and enable SRIOV only for physical
1911 * devices. Try to claim ownership on the device;
1912 * if already taken, skip -- do not allow multiple PFs */
1913 err = mlx4_get_ownership(dev);
1914 if (err) {
1915 if (err < 0)
1916 goto err_free_dev;
1917 else {
1918 mlx4_warn(dev, "Multiple PFs not yet supported."
1919 " Skipping PF.\n");
1920 err = -EINVAL;
1921 goto err_free_dev;
1922 }
1923 }
aca7a3ac 1924
ab9c17a0
JM		 1925 if (num_vfs) {
1926 mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs);
1927 err = pci_enable_sriov(pdev, num_vfs);
1928 if (err) {
1929 mlx4_err(dev, "Failed to enable sriov,"
1930 "continuing without sriov enabled"
1931 " (err = %d).\n", err);
ab9c17a0
JM		 1932 err = 0;
1933 } else {
1934 mlx4_warn(dev, "Running in master mode\n");
1935 dev->flags |= MLX4_FLAG_SRIOV |
1936 MLX4_FLAG_MASTER;
1937 dev->num_vfs = num_vfs;
1938 }
1939 }
1940
1941 /*
1942 * Now reset the HCA before we touch the PCI capabilities or
1943 * attempt a firmware command, since a boot ROM may have left
1944 * the HCA in an undefined state.
1945 */
1946 err = mlx4_reset(dev);
1947 if (err) {
1948 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1949 goto err_rel_own;
1950 }
225c7b1f
RD		 1951 }
1952
ab9c17a0 1953slave_start:
225c7b1f
RD		 1954 if (mlx4_cmd_init(dev)) {
1955 mlx4_err(dev, "Failed to init command interface, aborting.\n");
ab9c17a0
JM		 1956 goto err_sriov;
1957 }
1958
1959 /* In slave functions, the communication channel must be initialized
1960 * before posting commands. Also, init num_slaves before calling
1961 * mlx4_init_hca */
1962 if (mlx4_is_mfunc(dev)) {
1963 if (mlx4_is_master(dev))
1964 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
1965 else {
1966 dev->num_slaves = 0;
1967 if (mlx4_multi_func_init(dev)) {
1968 mlx4_err(dev, "Failed to init slave mfunc"
1969 " interface, aborting.\n");
1970 goto err_cmd;
1971 }
1972 }
225c7b1f
RD		 1973 }
1974
1975 err = mlx4_init_hca(dev);
ab9c17a0
JM		 1976 if (err) {
1977 if (err == -EACCES) {
1978 /* Not primary Physical function
1979 * Running in slave mode */
1980 mlx4_cmd_cleanup(dev);
1981 dev->flags |= MLX4_FLAG_SLAVE;
1982 dev->flags &= ~MLX4_FLAG_MASTER;
1983 goto slave_start;
1984 } else
1985 goto err_mfunc;
1986 }
1987
1988 /* In master functions, the communication channel must be initialized
1989 * after obtaining its address from fw */
1990 if (mlx4_is_master(dev)) {
1991 if (mlx4_multi_func_init(dev)) {
1992 mlx4_err(dev, "Failed to init master mfunc"
1993 "interface, aborting.\n");
1994 goto err_close;
1995 }
1996 }
225c7b1f 1997
b8dd786f
YP		 1998 err = mlx4_alloc_eq_table(dev);
1999 if (err)
ab9c17a0 2000 goto err_master_mfunc;
b8dd786f 2001
0b7ca5a9 2002 priv->msix_ctl.pool_bm = 0;
730c41d5 2003 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2004
08fb1055 2005 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2006 if ((mlx4_is_mfunc(dev)) &&
2007 !(dev->flags & MLX4_FLAG_MSI_X)) {
2008 mlx4_err(dev, "INTx is not supported in multi-function mode."
2009 " aborting.\n");
b12d93d6 2010 goto err_free_eq;
ab9c17a0
JM		 2011 }
2012
2013 if (!mlx4_is_slave(dev)) {
2014 err = mlx4_init_steering(dev);
2015 if (err)
2016 goto err_free_eq;
2017 }
b12d93d6 2018
225c7b1f 2019 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2020 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2021 !mlx4_is_mfunc(dev)) {
08fb1055 2022 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2023 dev->caps.num_comp_vectors = 1;
2024 dev->caps.comp_pool = 0;
08fb1055
MT		 2025 pci_disable_msix(pdev);
2026 err = mlx4_setup_hca(dev);
2027 }
2028
225c7b1f 2029 if (err)
b12d93d6 2030 goto err_steer;
225c7b1f 2031
7ff93f8b
YP		 2032 for (port = 1; port <= dev->caps.num_ports; port++) {
2033 err = mlx4_init_port_info(dev, port);
2034 if (err)
2035 goto err_port;
2036 }
2a2336f8 2037
225c7b1f
RD		 2038 err = mlx4_register_device(dev);
2039 if (err)
7ff93f8b 2040 goto err_port;
225c7b1f 2041
27bf91d6
YP		 2042 mlx4_sense_init(dev);
2043 mlx4_start_sense(dev);
2044
225c7b1f
RD		 2045 pci_set_drvdata(pdev, dev);
2046
2047 return 0;
2048
7ff93f8b 2049err_port:
b4f77264 2050 for (--port; port >= 1; --port)
7ff93f8b
YP		 2051 mlx4_cleanup_port_info(&priv->port[port]);
2052
f2a3f6a3 2053 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2054 mlx4_cleanup_mcg_table(dev);
2055 mlx4_cleanup_qp_table(dev);
2056 mlx4_cleanup_srq_table(dev);
2057 mlx4_cleanup_cq_table(dev);
2058 mlx4_cmd_use_polling(dev);
2059 mlx4_cleanup_eq_table(dev);
225c7b1f 2060 mlx4_cleanup_mr_table(dev);
012a8ff5 2061 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2062 mlx4_cleanup_pd_table(dev);
2063 mlx4_cleanup_uar_table(dev);
2064
b12d93d6 2065err_steer:
ab9c17a0
JM		 2066 if (!mlx4_is_slave(dev))
2067 mlx4_clear_steering(dev);
b12d93d6 2068
b8dd786f
YP		 2069err_free_eq:
2070 mlx4_free_eq_table(dev);
2071
ab9c17a0
JM		 2072err_master_mfunc:
2073 if (mlx4_is_master(dev))
2074 mlx4_multi_func_cleanup(dev);
2075
225c7b1f 2076err_close:
08fb1055
MT		 2077 if (dev->flags & MLX4_FLAG_MSI_X)
2078 pci_disable_msix(pdev);
2079
225c7b1f
RD		 2080 mlx4_close_hca(dev);
2081
ab9c17a0
JM		 2082err_mfunc:
2083 if (mlx4_is_slave(dev))
2084 mlx4_multi_func_cleanup(dev);
2085
225c7b1f
RD		 2086err_cmd:
2087 mlx4_cmd_cleanup(dev);
2088
ab9c17a0 2089err_sriov:
681372a7 2090 if (dev->flags & MLX4_FLAG_SRIOV)
ab9c17a0
JM		 2091 pci_disable_sriov(pdev);
2092
2093err_rel_own:
2094 if (!mlx4_is_slave(dev))
2095 mlx4_free_ownership(dev);
2096
225c7b1f 2097err_free_dev:
225c7b1f
RD		 2098 kfree(priv);
2099
a01df0fe
RD		 2100err_release_regions:
2101 pci_release_regions(pdev);
225c7b1f
RD		 2102
2103err_disable_pdev:
2104 pci_disable_device(pdev);
2105 pci_set_drvdata(pdev, NULL);
2106 return err;
2107}
2108
3d73c288
RD		 2109static int __devinit mlx4_init_one(struct pci_dev *pdev,
2110 const struct pci_device_id *id)
2111{
0a645e80 2112 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2113
b027cacd 2114 return __mlx4_init_one(pdev, id);
3d73c288
RD		 2115}
2116
2117static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 2118{
2119 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2120 struct mlx4_priv *priv = mlx4_priv(dev);
2121 int p;
2122
2123 if (dev) {
ab9c17a0
JM		 2124 /* in SRIOV it is not allowed to unload the pf's
2125 * driver while there are alive vf's */
2126 if (mlx4_is_master(dev)) {
2127 if (mlx4_how_many_lives_vf(dev))
2128 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2129 }
27bf91d6 2130 mlx4_stop_sense(dev);
225c7b1f
RD		 2131 mlx4_unregister_device(dev);
2132
7ff93f8b
YP		 2133 for (p = 1; p <= dev->caps.num_ports; p++) {
2134 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 2135 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 2136 }
225c7b1f 2137
b8924951
JM		 2138 if (mlx4_is_master(dev))
2139 mlx4_free_resource_tracker(dev,
2140 RES_TR_FREE_SLAVES_ONLY);
2141
f2a3f6a3 2142 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2143 mlx4_cleanup_mcg_table(dev);
2144 mlx4_cleanup_qp_table(dev);
2145 mlx4_cleanup_srq_table(dev);
2146 mlx4_cleanup_cq_table(dev);
2147 mlx4_cmd_use_polling(dev);
2148 mlx4_cleanup_eq_table(dev);
225c7b1f 2149 mlx4_cleanup_mr_table(dev);
012a8ff5 2150 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2151 mlx4_cleanup_pd_table(dev);
2152
ab9c17a0 2153 if (mlx4_is_master(dev))
b8924951
JM		 2154 mlx4_free_resource_tracker(dev,
2155 RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 2156
225c7b1f
RD		 2157 iounmap(priv->kar);
2158 mlx4_uar_free(dev, &priv->driver_uar);
2159 mlx4_cleanup_uar_table(dev);
ab9c17a0
JM		 2160 if (!mlx4_is_slave(dev))
2161 mlx4_clear_steering(dev);
b8dd786f 2162 mlx4_free_eq_table(dev);
ab9c17a0
JM		 2163 if (mlx4_is_master(dev))
2164 mlx4_multi_func_cleanup(dev);
225c7b1f 2165 mlx4_close_hca(dev);
ab9c17a0
JM		 2166 if (mlx4_is_slave(dev))
2167 mlx4_multi_func_cleanup(dev);
225c7b1f
RD		 2168 mlx4_cmd_cleanup(dev);
2169
2170 if (dev->flags & MLX4_FLAG_MSI_X)
2171 pci_disable_msix(pdev);
681372a7 2172 if (dev->flags & MLX4_FLAG_SRIOV) {
ab9c17a0
JM		 2173 mlx4_warn(dev, "Disabling sriov\n");
2174 pci_disable_sriov(pdev);
2175 }
225c7b1f 2176
ab9c17a0
JM		 2177 if (!mlx4_is_slave(dev))
2178 mlx4_free_ownership(dev);
225c7b1f 2179 kfree(priv);
a01df0fe 2180 pci_release_regions(pdev);
225c7b1f
RD		 2181 pci_disable_device(pdev);
2182 pci_set_drvdata(pdev, NULL);
2183 }
2184}
2185
ee49bd93
JM		 2186int mlx4_restart_one(struct pci_dev *pdev)
2187{
2188 mlx4_remove_one(pdev);
3d73c288 2189 return __mlx4_init_one(pdev, NULL);
ee49bd93
JM		 2190}
2191
a3aa1884 2192static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0
JM		 2193 /* MT25408 "Hermon" SDR */
2194 { PCI_VDEVICE(MELLANOX, 0x6340), 0 },
2195 /* MT25408 "Hermon" DDR */
2196 { PCI_VDEVICE(MELLANOX, 0x634a), 0 },
2197 /* MT25408 "Hermon" QDR */
2198 { PCI_VDEVICE(MELLANOX, 0x6354), 0 },
2199 /* MT25408 "Hermon" DDR PCIe gen2 */
2200 { PCI_VDEVICE(MELLANOX, 0x6732), 0 },
2201 /* MT25408 "Hermon" QDR PCIe gen2 */
2202 { PCI_VDEVICE(MELLANOX, 0x673c), 0 },
2203 /* MT25408 "Hermon" EN 10GigE */
2204 { PCI_VDEVICE(MELLANOX, 0x6368), 0 },
2205 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2206 { PCI_VDEVICE(MELLANOX, 0x6750), 0 },
2207 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2208 { PCI_VDEVICE(MELLANOX, 0x6372), 0 },
2209 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2210 { PCI_VDEVICE(MELLANOX, 0x675a), 0 },
2211 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2212 { PCI_VDEVICE(MELLANOX, 0x6764), 0 },
2213 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2214 { PCI_VDEVICE(MELLANOX, 0x6746), 0 },
2215 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2216 { PCI_VDEVICE(MELLANOX, 0x676e), 0 },
2217 /* MT25400 Family [ConnectX-2 Virtual Function] */
2218 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_VF },
2219 /* MT27500 Family [ConnectX-3] */
2220 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2221 /* MT27500 Family [ConnectX-3 Virtual Function] */
2222 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_VF },
2223 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2224 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2225 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2226 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2227 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2228 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2229 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2230 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2231 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2232 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2233 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2234 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2235 { 0, }
2236};
2237
2238MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2239
2240static struct pci_driver mlx4_driver = {
2241 .name = DRV_NAME,
2242 .id_table = mlx4_pci_table,
2243 .probe = mlx4_init_one,
2244 .remove = __devexit_p(mlx4_remove_one)
2245};
2246
7ff93f8b
YP		 2247static int __init mlx4_verify_params(void)
2248{
2249 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2250 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2251 return -1;
2252 }
2253
cb29688a
OG		 2254 if (log_num_vlan != 0)
2255 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2256 MLX4_LOG_NUM_VLANS);
7ff93f8b 2257
0498628f 2258 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2259 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2260 return -1;
2261 }
2262
ab9c17a0
JM		 2263 /* Check if module param for ports type has legal combination */
2264 if (port_type_array[0] == false && port_type_array[1] == true) {
2265 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2266 port_type_array[0] = true;
2267 }
2268
7ff93f8b
YP		 2269 return 0;
2270}
2271
225c7b1f
RD		 2272static int __init mlx4_init(void)
2273{
2274 int ret;
2275
7ff93f8b
YP		 2276 if (mlx4_verify_params())
2277 return -EINVAL;
2278
27bf91d6
YP		 2279 mlx4_catas_init();
2280
2281 mlx4_wq = create_singlethread_workqueue("mlx4");
2282 if (!mlx4_wq)
2283 return -ENOMEM;
ee49bd93 2284
225c7b1f
RD		 2285 ret = pci_register_driver(&mlx4_driver);
2286 return ret < 0 ? ret : 0;
2287}
2288
2289static void __exit mlx4_cleanup(void)
2290{
2291 pci_unregister_driver(&mlx4_driver);
27bf91d6 2292 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2293}
2294
2295module_init(mlx4_init);
2296module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)