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phy: IC+101G and PHY_HAS_INTERRUPT flag
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
225c7b1f
RD		 44
45#include <linux/mlx4/device.h>
46#include <linux/mlx4/doorbell.h>
47
48#include "mlx4.h"
49#include "fw.h"
50#include "icm.h"
51
52MODULE_AUTHOR("Roland Dreier");
53MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
54MODULE_LICENSE("Dual BSD/GPL");
55MODULE_VERSION(DRV_VERSION);
56
27bf91d6
YP		 57struct workqueue_struct *mlx4_wq;
58
225c7b1f
RD		 59#ifdef CONFIG_MLX4_DEBUG
60
61int mlx4_debug_level = 0;
62module_param_named(debug_level, mlx4_debug_level, int, 0644);
63MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
64
65#endif /* CONFIG_MLX4_DEBUG */
66
67#ifdef CONFIG_PCI_MSI
68
08fb1055 69static int msi_x = 1;
225c7b1f
RD		 70module_param(msi_x, int, 0444);
71MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
72
73#else /* CONFIG_PCI_MSI */
74
75#define msi_x (0)
76
77#endif /* CONFIG_PCI_MSI */
78
ab9c17a0
JM		 79static int num_vfs;
80module_param(num_vfs, int, 0444);
81MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
82
83static int probe_vf;
84module_param(probe_vf, int, 0644);
85MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
86
0ec2c0f8
EE		 87int mlx4_log_num_mgm_entry_size = 10;
88module_param_named(log_num_mgm_entry_size,
89 mlx4_log_num_mgm_entry_size, int, 0444);
90MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
91 " of qp per mcg, for example:"
92 " 10 gives 248.range: 9<="
93 " log_num_mgm_entry_size <= 12");
94
ab9c17a0
JM		 95#define MLX4_VF (1 << 0)
96
97#define HCA_GLOBAL_CAP_MASK 0
98#define PF_CONTEXT_BEHAVIOUR_MASK 0
99
f33afc26 100static char mlx4_version[] __devinitdata =
225c7b1f
RD		 101 DRV_NAME ": Mellanox ConnectX core driver v"
102 DRV_VERSION " (" DRV_RELDATE ")\n";
103
104static struct mlx4_profile default_profile = {
ab9c17a0 105 .num_qp = 1 << 18,
225c7b1f 106 .num_srq = 1 << 16,
c9f2ba5e 107 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 108 .num_cq = 1 << 16,
109 .num_mcg = 1 << 13,
ab9c17a0 110 .num_mpt = 1 << 19,
9fd7a1e1 111 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 112};
113
ab9c17a0 114static int log_num_mac = 7;
93fc9e1b
YP		 115module_param_named(log_num_mac, log_num_mac, int, 0444);
116MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
117
118static int log_num_vlan;
119module_param_named(log_num_vlan, log_num_vlan, int, 0444);
120MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 121/* Log2 max number of VLANs per ETH port (0-7) */
122#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 123
eb939922 124static bool use_prio;
93fc9e1b
YP		 125module_param_named(use_prio, use_prio, bool, 0444);
126MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
127 "(0/1, default 0)");
128
2b8fb286 129int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 130module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 131MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 132
8d0fc7b6 133static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 134static int arr_argc = 2;
135module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 136MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
137 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 138
139struct mlx4_port_config {
140 struct list_head list;
141 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
142 struct pci_dev *pdev;
143};
144
145static inline int mlx4_master_get_num_eqs(struct mlx4_dev *dev)
146{
147 return dev->caps.reserved_eqs +
148 MLX4_MFUNC_EQ_NUM * (dev->num_slaves + 1);
149}
150
27bf91d6
YP		 151int mlx4_check_port_params(struct mlx4_dev *dev,
152 enum mlx4_port_type *port_type)
7ff93f8b
YP		 153{
154 int i;
155
156 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 157 if (port_type[i] != port_type[i + 1]) {
158 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
159 mlx4_err(dev, "Only same port types supported "
160 "on this HCA, aborting.\n");
161 return -EINVAL;
162 }
163 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
164 port_type[i + 1] == MLX4_PORT_TYPE_IB)
165 return -EINVAL;
7ff93f8b
YP		 166 }
167 }
7ff93f8b
YP		 168
169 for (i = 0; i < dev->caps.num_ports; i++) {
170 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
171 mlx4_err(dev, "Requested port type for port %d is not "
172 "supported on this HCA\n", i + 1);
173 return -EINVAL;
174 }
175 }
176 return 0;
177}
178
179static void mlx4_set_port_mask(struct mlx4_dev *dev)
180{
181 int i;
182
7ff93f8b 183 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 184 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 185}
f2a3f6a3 186
3d73c288 187static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 188{
189 int err;
5ae2a7a8 190 int i;
225c7b1f
RD		 191
192 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
193 if (err) {
194 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
195 return err;
196 }
197
198 if (dev_cap->min_page_sz > PAGE_SIZE) {
199 mlx4_err(dev, "HCA minimum page size of %d bigger than "
200 "kernel PAGE_SIZE of %ld, aborting.\n",
201 dev_cap->min_page_sz, PAGE_SIZE);
202 return -ENODEV;
203 }
204 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
205 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
206 "aborting.\n",
207 dev_cap->num_ports, MLX4_MAX_PORTS);
208 return -ENODEV;
209 }
210
211 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
212 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
213 "PCI resource 2 size of 0x%llx, aborting.\n",
214 dev_cap->uar_size,
215 (unsigned long long) pci_resource_len(dev->pdev, 2));
216 return -ENODEV;
217 }
218
219 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 220 for (i = 1; i <= dev->caps.num_ports; ++i) {
221 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 222 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
5ae2a7a8
RD		 223 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
224 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
225 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 226 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
227 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 228 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 229 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
230 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 231 dev->caps.trans_type[i] = dev_cap->trans_type[i];
232 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
233 dev->caps.wavelength[i] = dev_cap->wavelength[i];
234 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 235 }
236
ab9c17a0 237 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 238 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 239 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
240 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
241 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
242 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
243 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
244 dev->caps.max_wqes = dev_cap->max_qp_sz;
245 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 246 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
247 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
248 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
249 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
250 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
0ec2c0f8 251 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
225c7b1f
RD		 252 /*
253 * Subtract 1 from the limit because we need to allocate a
254 * spare CQE so the HCA HW can tell the difference between an
255 * empty CQ and a full CQ.
256 */
257 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
258 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
259 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 260 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 261 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 262
263 /* The first 128 UARs are used for EQ doorbells */
264 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 265 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 266 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
267 dev_cap->reserved_xrcds : 0;
268 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
269 dev_cap->max_xrcds : 0;
2b8fb286
MA		 270 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
271
149983af 272 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 273 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
274 dev->caps.flags = dev_cap->flags;
95d04f07
RD		 275 dev->caps.bmme_flags = dev_cap->bmme_flags;
276 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 277 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 278 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
225c7b1f 279
58a60168
YP		 280 /* Sense port always allowed on supported devices for ConnectX1 and 2 */
281 if (dev->pdev->device != 0x1003)
282 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
283
93fc9e1b 284 dev->caps.log_num_macs = log_num_mac;
cb29688a 285 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 286 dev->caps.log_num_prios = use_prio ? 3 : 0;
287
288 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 289 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
290 if (dev->caps.supported_type[i]) {
291 /* if only ETH is supported - assign ETH */
292 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
293 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
294 /* if only IB is supported,
295 * assign IB only if SRIOV is off*/
296 else if (dev->caps.supported_type[i] ==
297 MLX4_PORT_TYPE_IB) {
298 if (dev->flags & MLX4_FLAG_SRIOV)
299 dev->caps.port_type[i] =
300 MLX4_PORT_TYPE_NONE;
301 else
302 dev->caps.port_type[i] =
303 MLX4_PORT_TYPE_IB;
304 /* if IB and ETH are supported,
305 * first of all check if SRIOV is on */
306 } else if (dev->flags & MLX4_FLAG_SRIOV)
307 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
ab9c17a0 308 else {
8d0fc7b6
YP		 309 /* In non-SRIOV mode, we set the port type
310 * according to user selection of port type,
311 * if usere selected none, take the FW hint */
312 if (port_type_array[i-1] == MLX4_PORT_TYPE_NONE)
313 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
314 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 315 else
8d0fc7b6 316 dev->caps.port_type[i] = port_type_array[i-1];
ab9c17a0
JM		 317 }
318 }
8d0fc7b6
YP		 319 /*
320 * Link sensing is allowed on the port if 3 conditions are true:
321 * 1. Both protocols are supported on the port.
322 * 2. Different types are supported on the port
323 * 3. FW declared that it supports link sensing
324 */
27bf91d6 325 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 326 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 327 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 328 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 329
8d0fc7b6
YP		 330 /*
331 * If "default_sense" bit is set, we move the port to "AUTO" mode
332 * and perform sense_port FW command to try and set the correct
333 * port type from beginning
334 */
46c46747 335 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 336 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
337 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
338 mlx4_SENSE_PORT(dev, i, &sensed_port);
339 if (sensed_port != MLX4_PORT_TYPE_NONE)
340 dev->caps.port_type[i] = sensed_port;
341 } else {
342 dev->caps.possible_type[i] = dev->caps.port_type[i];
343 }
344
93fc9e1b
YP		 345 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
346 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
347 mlx4_warn(dev, "Requested number of MACs is too much "
348 "for port %d, reducing to %d.\n",
349 i, 1 << dev->caps.log_num_macs);
350 }
351 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
352 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
353 mlx4_warn(dev, "Requested number of VLANs is too much "
354 "for port %d, reducing to %d.\n",
355 i, 1 << dev->caps.log_num_vlans);
356 }
357 }
358
f2a3f6a3
OG		 359 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
360
93fc9e1b
YP		 361 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
362 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
363 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
364 (1 << dev->caps.log_num_macs) *
365 (1 << dev->caps.log_num_vlans) *
366 (1 << dev->caps.log_num_prios) *
367 dev->caps.num_ports;
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
369
370 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
371 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
372 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
373 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
374
225c7b1f
RD		 375 return 0;
376}
ab9c17a0
JM		 377/*The function checks if there are live vf, return the num of them*/
378static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
379{
380 struct mlx4_priv *priv = mlx4_priv(dev);
381 struct mlx4_slave_state *s_state;
382 int i;
383 int ret = 0;
384
385 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
386 s_state = &priv->mfunc.master.slave_state[i];
387 if (s_state->active && s_state->last_cmd !=
388 MLX4_COMM_CMD_RESET) {
389 mlx4_warn(dev, "%s: slave: %d is still active\n",
390 __func__, i);
391 ret++;
392 }
393 }
394 return ret;
395}
396
397static int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
398{
399 struct mlx4_priv *priv = mlx4_priv(dev);
400 struct mlx4_slave_state *s_slave;
401
402 if (!mlx4_is_master(dev))
403 return 0;
404
405 s_slave = &priv->mfunc.master.slave_state[slave];
406 return !!s_slave->active;
407}
408EXPORT_SYMBOL(mlx4_is_slave_active);
409
410static int mlx4_slave_cap(struct mlx4_dev *dev)
411{
412 int err;
413 u32 page_size;
414 struct mlx4_dev_cap dev_cap;
415 struct mlx4_func_cap func_cap;
416 struct mlx4_init_hca_param hca_param;
417 int i;
418
419 memset(&hca_param, 0, sizeof(hca_param));
420 err = mlx4_QUERY_HCA(dev, &hca_param);
421 if (err) {
422 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
423 return err;
424 }
425
426 /*fail if the hca has an unknown capability */
427 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
428 HCA_GLOBAL_CAP_MASK) {
429 mlx4_err(dev, "Unknown hca global capabilities\n");
430 return -ENOSYS;
431 }
432
433 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
434
435 memset(&dev_cap, 0, sizeof(dev_cap));
436 err = mlx4_dev_cap(dev, &dev_cap);
437 if (err) {
438 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
439 return err;
440 }
441
442 page_size = ~dev->caps.page_size_cap + 1;
443 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
444 if (page_size > PAGE_SIZE) {
445 mlx4_err(dev, "HCA minimum page size of %d bigger than "
446 "kernel PAGE_SIZE of %ld, aborting.\n",
447 page_size, PAGE_SIZE);
448 return -ENODEV;
449 }
450
451 /* slave gets uar page size from QUERY_HCA fw command */
452 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
453
454 /* TODO: relax this assumption */
455 if (dev->caps.uar_page_size != PAGE_SIZE) {
456 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
457 dev->caps.uar_page_size, PAGE_SIZE);
458 return -ENODEV;
459 }
460
461 memset(&func_cap, 0, sizeof(func_cap));
462 err = mlx4_QUERY_FUNC_CAP(dev, &func_cap);
463 if (err) {
464 mlx4_err(dev, "QUERY_FUNC_CAP command failed, aborting.\n");
465 return err;
466 }
467
468 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
469 PF_CONTEXT_BEHAVIOUR_MASK) {
470 mlx4_err(dev, "Unknown pf context behaviour\n");
471 return -ENOSYS;
472 }
473
ab9c17a0
JM		 474 dev->caps.num_ports = func_cap.num_ports;
475 dev->caps.num_qps = func_cap.qp_quota;
476 dev->caps.num_srqs = func_cap.srq_quota;
477 dev->caps.num_cqs = func_cap.cq_quota;
478 dev->caps.num_eqs = func_cap.max_eq;
479 dev->caps.reserved_eqs = func_cap.reserved_eq;
480 dev->caps.num_mpts = func_cap.mpt_quota;
481 dev->caps.num_mtts = func_cap.mtt_quota;
482 dev->caps.num_pds = MLX4_NUM_PDS;
483 dev->caps.num_mgms = 0;
484 dev->caps.num_amgms = 0;
485
486 for (i = 1; i <= dev->caps.num_ports; ++i)
487 dev->caps.port_mask[i] = dev->caps.port_type[i];
488
489 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
490 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
491 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
492 return -ENODEV;
493 }
494
495 if (dev->caps.uar_page_size * (dev->caps.num_uars -
496 dev->caps.reserved_uars) >
497 pci_resource_len(dev->pdev, 2)) {
498 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
499 "PCI resource 2 size of 0x%llx, aborting.\n",
500 dev->caps.uar_page_size * dev->caps.num_uars,
501 (unsigned long long) pci_resource_len(dev->pdev, 2));
502 return -ENODEV;
503 }
504
505#if 0
506 mlx4_warn(dev, "sqp_demux:%d\n", dev->caps.sqp_demux);
507 mlx4_warn(dev, "num_uars:%d reserved_uars:%d uar region:0x%x bar2:0x%llx\n",
508 dev->caps.num_uars, dev->caps.reserved_uars,
509 dev->caps.uar_page_size * dev->caps.num_uars,
510 pci_resource_len(dev->pdev, 2));
511 mlx4_warn(dev, "num_eqs:%d reserved_eqs:%d\n", dev->caps.num_eqs,
512 dev->caps.reserved_eqs);
513 mlx4_warn(dev, "num_pds:%d reserved_pds:%d slave_pd_shift:%d pd_base:%d\n",
514 dev->caps.num_pds, dev->caps.reserved_pds,
515 dev->caps.slave_pd_shift, dev->caps.pd_base);
516#endif
517 return 0;
518}
225c7b1f 519
7ff93f8b
YP		 520/*
521 * Change the port configuration of the device.
522 * Every user of this function must hold the port mutex.
523 */
27bf91d6
YP		 524int mlx4_change_port_types(struct mlx4_dev *dev,
525 enum mlx4_port_type *port_types)
7ff93f8b
YP		 526{
527 int err = 0;
528 int change = 0;
529 int port;
530
531 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 532 /* Change the port type only if the new type is different
533 * from the current, and not set to Auto */
3d8f9308 534 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 535 change = 1;
7ff93f8b
YP		 536 }
537 if (change) {
538 mlx4_unregister_device(dev);
539 for (port = 1; port <= dev->caps.num_ports; port++) {
540 mlx4_CLOSE_PORT(dev, port);
3d8f9308 541 dev->caps.port_type[port + 1] = port_types[port];
7ff93f8b
YP		 542 err = mlx4_SET_PORT(dev, port);
543 if (err) {
544 mlx4_err(dev, "Failed to set port %d, "
545 "aborting\n", port);
546 goto out;
547 }
548 }
549 mlx4_set_port_mask(dev);
550 err = mlx4_register_device(dev);
551 }
552
553out:
554 return err;
555}
556
557static ssize_t show_port_type(struct device *dev,
558 struct device_attribute *attr,
559 char *buf)
560{
561 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
562 port_attr);
563 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 564 char type[8];
565
566 sprintf(type, "%s",
567 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
568 "ib" : "eth");
569 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
570 sprintf(buf, "auto (%s)\n", type);
571 else
572 sprintf(buf, "%s\n", type);
7ff93f8b 573
27bf91d6 574 return strlen(buf);
7ff93f8b
YP		 575}
576
577static ssize_t set_port_type(struct device *dev,
578 struct device_attribute *attr,
579 const char *buf, size_t count)
580{
581 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
582 port_attr);
583 struct mlx4_dev *mdev = info->dev;
584 struct mlx4_priv *priv = mlx4_priv(mdev);
585 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 586 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 587 int i;
588 int err = 0;
589
590 if (!strcmp(buf, "ib\n"))
591 info->tmp_type = MLX4_PORT_TYPE_IB;
592 else if (!strcmp(buf, "eth\n"))
593 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 594 else if (!strcmp(buf, "auto\n"))
595 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 596 else {
597 mlx4_err(mdev, "%s is not supported port type\n", buf);
598 return -EINVAL;
599 }
600
27bf91d6 601 mlx4_stop_sense(mdev);
7ff93f8b 602 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 603 /* Possible type is always the one that was delivered */
604 mdev->caps.possible_type[info->port] = info->tmp_type;
605
606 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 607 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 608 mdev->caps.possible_type[i+1];
609 if (types[i] == MLX4_PORT_TYPE_AUTO)
610 types[i] = mdev->caps.port_type[i+1];
611 }
7ff93f8b 612
58a60168
YP		 613 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
614 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 615 for (i = 1; i <= mdev->caps.num_ports; i++) {
616 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
617 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
618 err = -EINVAL;
619 }
620 }
621 }
622 if (err) {
623 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
624 "Set only 'eth' or 'ib' for both ports "
625 "(should be the same)\n");
626 goto out;
627 }
628
629 mlx4_do_sense_ports(mdev, new_types, types);
630
631 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 632 if (err)
633 goto out;
634
27bf91d6
YP		 635 /* We are about to apply the changes after the configuration
636 * was verified, no need to remember the temporary types
637 * any more */
638 for (i = 0; i < mdev->caps.num_ports; i++)
639 priv->port[i + 1].tmp_type = 0;
7ff93f8b 640
27bf91d6 641 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 642
643out:
27bf91d6 644 mlx4_start_sense(mdev);
7ff93f8b
YP		 645 mutex_unlock(&priv->port_mutex);
646 return err ? err : count;
647}
648
e8f9b2ed 649static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 650{
651 struct mlx4_priv *priv = mlx4_priv(dev);
652 int err;
653
654 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 655 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 656 if (!priv->fw.fw_icm) {
657 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
658 return -ENOMEM;
659 }
660
661 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
662 if (err) {
663 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
664 goto err_free;
665 }
666
667 err = mlx4_RUN_FW(dev);
668 if (err) {
669 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
670 goto err_unmap_fa;
671 }
672
673 return 0;
674
675err_unmap_fa:
676 mlx4_UNMAP_FA(dev);
677
678err_free:
5b0bf5e2 679 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 680 return err;
681}
682
e8f9b2ed
RD		 683static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
684 int cmpt_entry_sz)
225c7b1f
RD		 685{
686 struct mlx4_priv *priv = mlx4_priv(dev);
687 int err;
ab9c17a0 688 int num_eqs;
225c7b1f
RD		 689
690 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
691 cmpt_base +
692 ((u64) (MLX4_CMPT_TYPE_QP *
693 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
694 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 695 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
696 0, 0);
225c7b1f
RD		 697 if (err)
698 goto err;
699
700 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
701 cmpt_base +
702 ((u64) (MLX4_CMPT_TYPE_SRQ *
703 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
704 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 705 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 706 if (err)
707 goto err_qp;
708
709 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
710 cmpt_base +
711 ((u64) (MLX4_CMPT_TYPE_CQ *
712 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
713 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 714 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 715 if (err)
716 goto err_srq;
717
ab9c17a0
JM		 718 num_eqs = (mlx4_is_master(dev)) ?
719 roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) :
720 dev->caps.num_eqs;
225c7b1f
RD		 721 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
722 cmpt_base +
723 ((u64) (MLX4_CMPT_TYPE_EQ *
724 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 725 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 726 if (err)
727 goto err_cq;
728
729 return 0;
730
731err_cq:
732 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
733
734err_srq:
735 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
736
737err_qp:
738 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
739
740err:
741 return err;
742}
743
3d73c288
RD		 744static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
745 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 746{
747 struct mlx4_priv *priv = mlx4_priv(dev);
748 u64 aux_pages;
ab9c17a0 749 int num_eqs;
225c7b1f
RD		 750 int err;
751
752 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
753 if (err) {
754 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
755 return err;
756 }
757
758 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
759 (unsigned long long) icm_size >> 10,
760 (unsigned long long) aux_pages << 2);
761
762 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 763 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 764 if (!priv->fw.aux_icm) {
765 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
766 return -ENOMEM;
767 }
768
769 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
770 if (err) {
771 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
772 goto err_free_aux;
773 }
774
775 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
776 if (err) {
777 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
778 goto err_unmap_aux;
779 }
780
ab9c17a0
JM		 781
782 num_eqs = (mlx4_is_master(dev)) ?
783 roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) :
784 dev->caps.num_eqs;
fa0681d2
RD		 785 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
786 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 787 num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 788 if (err) {
789 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
790 goto err_unmap_cmpt;
791 }
792
d7bb58fb
JM		 793 /*
794 * Reserved MTT entries must be aligned up to a cacheline
795 * boundary, since the FW will write to them, while the driver
796 * writes to all other MTT entries. (The variable
797 * dev->caps.mtt_entry_sz below is really the MTT segment
798 * size, not the raw entry size)
799 */
800 dev->caps.reserved_mtts =
801 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
802 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
803
225c7b1f
RD		 804 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
805 init_hca->mtt_base,
806 dev->caps.mtt_entry_sz,
2b8fb286 807 dev->caps.num_mtts,
5b0bf5e2 808 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 809 if (err) {
810 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
811 goto err_unmap_eq;
812 }
813
814 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
815 init_hca->dmpt_base,
816 dev_cap->dmpt_entry_sz,
817 dev->caps.num_mpts,
5b0bf5e2 818 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 819 if (err) {
820 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
821 goto err_unmap_mtt;
822 }
823
824 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
825 init_hca->qpc_base,
826 dev_cap->qpc_entry_sz,
827 dev->caps.num_qps,
93fc9e1b
YP		 828 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
829 0, 0);
225c7b1f
RD		 830 if (err) {
831 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
832 goto err_unmap_dmpt;
833 }
834
835 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
836 init_hca->auxc_base,
837 dev_cap->aux_entry_sz,
838 dev->caps.num_qps,
93fc9e1b
YP		 839 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
840 0, 0);
225c7b1f
RD		 841 if (err) {
842 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
843 goto err_unmap_qp;
844 }
845
846 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
847 init_hca->altc_base,
848 dev_cap->altc_entry_sz,
849 dev->caps.num_qps,
93fc9e1b
YP		 850 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
851 0, 0);
225c7b1f
RD		 852 if (err) {
853 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
854 goto err_unmap_auxc;
855 }
856
857 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
858 init_hca->rdmarc_base,
859 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
860 dev->caps.num_qps,
93fc9e1b
YP		 861 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
862 0, 0);
225c7b1f
RD		 863 if (err) {
864 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
865 goto err_unmap_altc;
866 }
867
868 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
869 init_hca->cqc_base,
870 dev_cap->cqc_entry_sz,
871 dev->caps.num_cqs,
5b0bf5e2 872 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 873 if (err) {
874 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
875 goto err_unmap_rdmarc;
876 }
877
878 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
879 init_hca->srqc_base,
880 dev_cap->srq_entry_sz,
881 dev->caps.num_srqs,
5b0bf5e2 882 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 883 if (err) {
884 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
885 goto err_unmap_cq;
886 }
887
888 /*
889 * It's not strictly required, but for simplicity just map the
890 * whole multicast group table now. The table isn't very big
891 * and it's a lot easier than trying to track ref counts.
892 */
893 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 894 init_hca->mc_base,
895 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 896 dev->caps.num_mgms + dev->caps.num_amgms,
897 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 898 0, 0);
225c7b1f
RD		 899 if (err) {
900 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
901 goto err_unmap_srq;
902 }
903
904 return 0;
905
906err_unmap_srq:
907 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
908
909err_unmap_cq:
910 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
911
912err_unmap_rdmarc:
913 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
914
915err_unmap_altc:
916 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
917
918err_unmap_auxc:
919 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
920
921err_unmap_qp:
922 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
923
924err_unmap_dmpt:
925 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
926
927err_unmap_mtt:
928 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
929
930err_unmap_eq:
fa0681d2 931 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 932
933err_unmap_cmpt:
934 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
935 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
936 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
937 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
938
939err_unmap_aux:
940 mlx4_UNMAP_ICM_AUX(dev);
941
942err_free_aux:
5b0bf5e2 943 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 944
945 return err;
946}
947
948static void mlx4_free_icms(struct mlx4_dev *dev)
949{
950 struct mlx4_priv *priv = mlx4_priv(dev);
951
952 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
953 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
954 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
955 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
956 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
957 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
958 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
959 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
960 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 961 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 962 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
963 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
964 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
965 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 966
967 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 968 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 969}
970
ab9c17a0
JM		 971static void mlx4_slave_exit(struct mlx4_dev *dev)
972{
973 struct mlx4_priv *priv = mlx4_priv(dev);
974
975 down(&priv->cmd.slave_sem);
976 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
977 mlx4_warn(dev, "Failed to close slave function.\n");
978 up(&priv->cmd.slave_sem);
979}
980
c1b43dca
EC		 981static int map_bf_area(struct mlx4_dev *dev)
982{
983 struct mlx4_priv *priv = mlx4_priv(dev);
984 resource_size_t bf_start;
985 resource_size_t bf_len;
986 int err = 0;
987
3d747473
JM		 988 if (!dev->caps.bf_reg_size)
989 return -ENXIO;
990
ab9c17a0
JM		 991 bf_start = pci_resource_start(dev->pdev, 2) +
992 (dev->caps.num_uars << PAGE_SHIFT);
993 bf_len = pci_resource_len(dev->pdev, 2) -
994 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 995 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
996 if (!priv->bf_mapping)
997 err = -ENOMEM;
998
999 return err;
1000}
1001
1002static void unmap_bf_area(struct mlx4_dev *dev)
1003{
1004 if (mlx4_priv(dev)->bf_mapping)
1005 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1006}
1007
225c7b1f
RD		 1008static void mlx4_close_hca(struct mlx4_dev *dev)
1009{
c1b43dca 1010 unmap_bf_area(dev);
ab9c17a0
JM		 1011 if (mlx4_is_slave(dev))
1012 mlx4_slave_exit(dev);
1013 else {
1014 mlx4_CLOSE_HCA(dev, 0);
1015 mlx4_free_icms(dev);
1016 mlx4_UNMAP_FA(dev);
1017 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1018 }
1019}
1020
1021static int mlx4_init_slave(struct mlx4_dev *dev)
1022{
1023 struct mlx4_priv *priv = mlx4_priv(dev);
1024 u64 dma = (u64) priv->mfunc.vhcr_dma;
1025 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1026 int ret_from_reset = 0;
1027 u32 slave_read;
1028 u32 cmd_channel_ver;
1029
1030 down(&priv->cmd.slave_sem);
1031 priv->cmd.max_cmds = 1;
1032 mlx4_warn(dev, "Sending reset\n");
1033 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1034 MLX4_COMM_TIME);
1035 /* if we are in the middle of flr the slave will try
1036 * NUM_OF_RESET_RETRIES times before leaving.*/
1037 if (ret_from_reset) {
1038 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1039 msleep(SLEEP_TIME_IN_RESET);
1040 while (ret_from_reset && num_of_reset_retries) {
1041 mlx4_warn(dev, "slave is currently in the"
1042 "middle of FLR. retrying..."
1043 "(try num:%d)\n",
1044 (NUM_OF_RESET_RETRIES -
1045 num_of_reset_retries + 1));
1046 ret_from_reset =
1047 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1048 0, MLX4_COMM_TIME);
1049 num_of_reset_retries = num_of_reset_retries - 1;
1050 }
1051 } else
1052 goto err;
1053 }
1054
1055 /* check the driver version - the slave I/F revision
1056 * must match the master's */
1057 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1058 cmd_channel_ver = mlx4_comm_get_version();
1059
1060 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1061 MLX4_COMM_GET_IF_REV(slave_read)) {
1062 mlx4_err(dev, "slave driver version is not supported"
1063 " by the master\n");
1064 goto err;
1065 }
1066
1067 mlx4_warn(dev, "Sending vhcr0\n");
1068 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1069 MLX4_COMM_TIME))
1070 goto err;
1071 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1072 MLX4_COMM_TIME))
1073 goto err;
1074 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1075 MLX4_COMM_TIME))
1076 goto err;
1077 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1078 goto err;
1079 up(&priv->cmd.slave_sem);
1080 return 0;
1081
1082err:
1083 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1084 up(&priv->cmd.slave_sem);
1085 return -EIO;
225c7b1f
RD		 1086}
1087
3d73c288 1088static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1089{
1090 struct mlx4_priv *priv = mlx4_priv(dev);
1091 struct mlx4_adapter adapter;
1092 struct mlx4_dev_cap dev_cap;
2d928651 1093 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1094 struct mlx4_profile profile;
1095 struct mlx4_init_hca_param init_hca;
1096 u64 icm_size;
1097 int err;
1098
ab9c17a0
JM		 1099 if (!mlx4_is_slave(dev)) {
1100 err = mlx4_QUERY_FW(dev);
1101 if (err) {
1102 if (err == -EACCES)
1103 mlx4_info(dev, "non-primary physical function, skipping.\n");
1104 else
1105 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1106 goto unmap_bf;
1107 }
225c7b1f 1108
ab9c17a0
JM		 1109 err = mlx4_load_fw(dev);
1110 if (err) {
1111 mlx4_err(dev, "Failed to start FW, aborting.\n");
1112 goto unmap_bf;
1113 }
225c7b1f 1114
ab9c17a0
JM		 1115 mlx4_cfg.log_pg_sz_m = 1;
1116 mlx4_cfg.log_pg_sz = 0;
1117 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1118 if (err)
1119 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1120
ab9c17a0
JM		 1121 err = mlx4_dev_cap(dev, &dev_cap);
1122 if (err) {
1123 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1124 goto err_stop_fw;
1125 }
225c7b1f 1126
ab9c17a0 1127 profile = default_profile;
225c7b1f 1128
ab9c17a0
JM		 1129 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1130 &init_hca);
1131 if ((long long) icm_size < 0) {
1132 err = icm_size;
1133 goto err_stop_fw;
1134 }
225c7b1f 1135
ab9c17a0
JM		 1136 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1137 init_hca.uar_page_sz = PAGE_SHIFT - 12;
c1b43dca 1138
ab9c17a0
JM		 1139 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1140 if (err)
1141 goto err_stop_fw;
225c7b1f 1142
ab9c17a0
JM		 1143 err = mlx4_INIT_HCA(dev, &init_hca);
1144 if (err) {
1145 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1146 goto err_free_icm;
1147 }
1148 } else {
1149 err = mlx4_init_slave(dev);
1150 if (err) {
1151 mlx4_err(dev, "Failed to initialize slave\n");
1152 goto unmap_bf;
1153 }
225c7b1f 1154
ab9c17a0
JM		 1155 err = mlx4_slave_cap(dev);
1156 if (err) {
1157 mlx4_err(dev, "Failed to obtain slave caps\n");
1158 goto err_close;
1159 }
225c7b1f
RD		 1160 }
1161
ab9c17a0
JM		 1162 if (map_bf_area(dev))
1163 mlx4_dbg(dev, "Failed to map blue flame area\n");
1164
1165 /*Only the master set the ports, all the rest got it from it.*/
1166 if (!mlx4_is_slave(dev))
1167 mlx4_set_port_mask(dev);
1168
225c7b1f
RD		 1169 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1170 if (err) {
1171 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1172 goto err_close;
1173 }
1174
1175 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1176 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1177
1178 return 0;
1179
1180err_close:
ab9c17a0 1181 mlx4_close_hca(dev);
225c7b1f
RD		 1182
1183err_free_icm:
ab9c17a0
JM		 1184 if (!mlx4_is_slave(dev))
1185 mlx4_free_icms(dev);
225c7b1f
RD		 1186
1187err_stop_fw:
ab9c17a0
JM		 1188 if (!mlx4_is_slave(dev)) {
1189 mlx4_UNMAP_FA(dev);
1190 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1191 }
1192unmap_bf:
c1b43dca 1193 unmap_bf_area(dev);
225c7b1f
RD		 1194 return err;
1195}
1196
f2a3f6a3
OG		 1197static int mlx4_init_counters_table(struct mlx4_dev *dev)
1198{
1199 struct mlx4_priv *priv = mlx4_priv(dev);
1200 int nent;
1201
1202 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1203 return -ENOENT;
1204
1205 nent = dev->caps.max_counters;
1206 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1207}
1208
1209static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1210{
1211 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1212}
1213
1214int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1215{
1216 struct mlx4_priv *priv = mlx4_priv(dev);
1217
1218 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1219 return -ENOENT;
1220
1221 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1222 if (*idx == -1)
1223 return -ENOMEM;
1224
1225 return 0;
1226}
1227EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1228
1229void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1230{
1231 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1232 return;
1233}
1234EXPORT_SYMBOL_GPL(mlx4_counter_free);
1235
3d73c288 1236static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1237{
1238 struct mlx4_priv *priv = mlx4_priv(dev);
1239 int err;
7ff93f8b 1240 int port;
9a5aa622 1241 __be32 ib_port_default_caps;
225c7b1f 1242
225c7b1f
RD		 1243 err = mlx4_init_uar_table(dev);
1244 if (err) {
1245 mlx4_err(dev, "Failed to initialize "
1246 "user access region table, aborting.\n");
1247 return err;
1248 }
1249
1250 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1251 if (err) {
1252 mlx4_err(dev, "Failed to allocate driver access region, "
1253 "aborting.\n");
1254 goto err_uar_table_free;
1255 }
1256
4979d18f 1257 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f
RD		 1258 if (!priv->kar) {
1259 mlx4_err(dev, "Couldn't map kernel access region, "
1260 "aborting.\n");
1261 err = -ENOMEM;
1262 goto err_uar_free;
1263 }
1264
1265 err = mlx4_init_pd_table(dev);
1266 if (err) {
1267 mlx4_err(dev, "Failed to initialize "
1268 "protection domain table, aborting.\n");
1269 goto err_kar_unmap;
1270 }
1271
012a8ff5
SH		 1272 err = mlx4_init_xrcd_table(dev);
1273 if (err) {
1274 mlx4_err(dev, "Failed to initialize "
1275 "reliable connection domain table, aborting.\n");
1276 goto err_pd_table_free;
1277 }
1278
225c7b1f
RD		 1279 err = mlx4_init_mr_table(dev);
1280 if (err) {
1281 mlx4_err(dev, "Failed to initialize "
1282 "memory region table, aborting.\n");
012a8ff5 1283 goto err_xrcd_table_free;
225c7b1f
RD		 1284 }
1285
225c7b1f
RD		 1286 err = mlx4_init_eq_table(dev);
1287 if (err) {
1288 mlx4_err(dev, "Failed to initialize "
1289 "event queue table, aborting.\n");
ee49bd93 1290 goto err_mr_table_free;
225c7b1f
RD		 1291 }
1292
1293 err = mlx4_cmd_use_events(dev);
1294 if (err) {
1295 mlx4_err(dev, "Failed to switch to event-driven "
1296 "firmware commands, aborting.\n");
1297 goto err_eq_table_free;
1298 }
1299
1300 err = mlx4_NOP(dev);
1301 if (err) {
08fb1055
MT		 1302 if (dev->flags & MLX4_FLAG_MSI_X) {
1303 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1304 "interrupt IRQ %d).\n",
b8dd786f 1305 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 1306 mlx4_warn(dev, "Trying again without MSI-X.\n");
1307 } else {
1308 mlx4_err(dev, "NOP command failed to generate interrupt "
1309 "(IRQ %d), aborting.\n",
b8dd786f 1310 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1311 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1312 }
225c7b1f
RD		 1313
1314 goto err_cmd_poll;
1315 }
1316
1317 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1318
1319 err = mlx4_init_cq_table(dev);
1320 if (err) {
1321 mlx4_err(dev, "Failed to initialize "
1322 "completion queue table, aborting.\n");
1323 goto err_cmd_poll;
1324 }
1325
1326 err = mlx4_init_srq_table(dev);
1327 if (err) {
1328 mlx4_err(dev, "Failed to initialize "
1329 "shared receive queue table, aborting.\n");
1330 goto err_cq_table_free;
1331 }
1332
1333 err = mlx4_init_qp_table(dev);
1334 if (err) {
1335 mlx4_err(dev, "Failed to initialize "
1336 "queue pair table, aborting.\n");
1337 goto err_srq_table_free;
1338 }
1339
ab9c17a0
JM		 1340 if (!mlx4_is_slave(dev)) {
1341 err = mlx4_init_mcg_table(dev);
1342 if (err) {
1343 mlx4_err(dev, "Failed to initialize "
1344 "multicast group table, aborting.\n");
1345 goto err_qp_table_free;
1346 }
225c7b1f
RD		 1347 }
1348
f2a3f6a3
OG		 1349 err = mlx4_init_counters_table(dev);
1350 if (err && err != -ENOENT) {
1351 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
ab9c17a0 1352 goto err_mcg_table_free;
f2a3f6a3
OG		 1353 }
1354
ab9c17a0
JM		 1355 if (!mlx4_is_slave(dev)) {
1356 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1357 ib_port_default_caps = 0;
1358 err = mlx4_get_port_ib_caps(dev, port,
1359 &ib_port_default_caps);
1360 if (err)
1361 mlx4_warn(dev, "failed to get port %d default "
1362 "ib capabilities (%d). Continuing "
1363 "with caps = 0\n", port, err);
1364 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1365
1366 err = mlx4_check_ext_port_caps(dev, port);
1367 if (err)
1368 mlx4_warn(dev, "failed to get port %d extended "
1369 "port capabilities support info (%d)."
1370 " Assuming not supported\n",
1371 port, err);
97285b78 1372
ab9c17a0
JM		 1373 err = mlx4_SET_PORT(dev, port);
1374 if (err) {
1375 mlx4_err(dev, "Failed to set port %d, aborting\n",
1376 port);
1377 goto err_counters_table_free;
1378 }
7ff93f8b
YP		 1379 }
1380 }
1381
225c7b1f
RD		 1382 return 0;
1383
f2a3f6a3
OG		 1384err_counters_table_free:
1385 mlx4_cleanup_counters_table(dev);
1386
ab9c17a0
JM		 1387err_mcg_table_free:
1388 mlx4_cleanup_mcg_table(dev);
1389
225c7b1f
RD		 1390err_qp_table_free:
1391 mlx4_cleanup_qp_table(dev);
1392
1393err_srq_table_free:
1394 mlx4_cleanup_srq_table(dev);
1395
1396err_cq_table_free:
1397 mlx4_cleanup_cq_table(dev);
1398
1399err_cmd_poll:
1400 mlx4_cmd_use_polling(dev);
1401
1402err_eq_table_free:
1403 mlx4_cleanup_eq_table(dev);
1404
ee49bd93 1405err_mr_table_free:
225c7b1f
RD		 1406 mlx4_cleanup_mr_table(dev);
1407
012a8ff5
SH		 1408err_xrcd_table_free:
1409 mlx4_cleanup_xrcd_table(dev);
1410
225c7b1f
RD		 1411err_pd_table_free:
1412 mlx4_cleanup_pd_table(dev);
1413
1414err_kar_unmap:
1415 iounmap(priv->kar);
1416
1417err_uar_free:
1418 mlx4_uar_free(dev, &priv->driver_uar);
1419
1420err_uar_table_free:
1421 mlx4_cleanup_uar_table(dev);
1422 return err;
1423}
1424
e8f9b2ed 1425static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 1426{
1427 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 1428 struct msix_entry *entries;
0b7ca5a9
YP		 1429 int nreq = min_t(int, dev->caps.num_ports *
1430 min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT)
1431 + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 1432 int err;
1433 int i;
1434
1435 if (msi_x) {
ab9c17a0
JM		 1436 /* In multifunction mode each function gets 2 msi-X vectors
1437 * one for data path completions anf the other for asynch events
1438 * or command completions */
1439 if (mlx4_is_mfunc(dev)) {
1440 nreq = 2;
1441 } else {
1442 nreq = min_t(int, dev->caps.num_eqs -
1443 dev->caps.reserved_eqs, nreq);
1444 }
1445
b8dd786f
YP		 1446 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1447 if (!entries)
1448 goto no_msi;
1449
1450 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1451 entries[i].entry = i;
1452
b8dd786f
YP		 1453 retry:
1454 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 1455 if (err) {
b8dd786f
YP		 1456 /* Try again if at least 2 vectors are available */
1457 if (err > 1) {
1458 mlx4_info(dev, "Requested %d vectors, "
1459 "but only %d MSI-X vectors available, "
1460 "trying again\n", nreq, err);
1461 nreq = err;
1462 goto retry;
1463 }
5bf0da7d 1464 kfree(entries);
225c7b1f
RD		 1465 goto no_msi;
1466 }
1467
0b7ca5a9
YP		 1468 if (nreq <
1469 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1470 /*Working in legacy mode , all EQ's shared*/
1471 dev->caps.comp_pool = 0;
1472 dev->caps.num_comp_vectors = nreq - 1;
1473 } else {
1474 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1475 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1476 }
b8dd786f 1477 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1478 priv->eq_table.eq[i].irq = entries[i].vector;
1479
1480 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 1481
1482 kfree(entries);
225c7b1f
RD		 1483 return;
1484 }
1485
1486no_msi:
b8dd786f 1487 dev->caps.num_comp_vectors = 1;
0b7ca5a9 1488 dev->caps.comp_pool = 0;
b8dd786f
YP		 1489
1490 for (i = 0; i < 2; ++i)
225c7b1f
RD		 1491 priv->eq_table.eq[i].irq = dev->pdev->irq;
1492}
1493
7ff93f8b 1494static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 1495{
1496 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 1497 int err = 0;
2a2336f8
YP		 1498
1499 info->dev = dev;
1500 info->port = port;
ab9c17a0
JM		 1501 if (!mlx4_is_slave(dev)) {
1502 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL);
1503 mlx4_init_mac_table(dev, &info->mac_table);
1504 mlx4_init_vlan_table(dev, &info->vlan_table);
1505 info->base_qpn =
1506 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
06fa0a88 1507 (port - 1) * (1 << log_num_mac);
ab9c17a0 1508 }
7ff93f8b
YP		 1509
1510 sprintf(info->dev_name, "mlx4_port%d", port);
1511 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 1512 if (mlx4_is_mfunc(dev))
1513 info->port_attr.attr.mode = S_IRUGO;
1514 else {
1515 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1516 info->port_attr.store = set_port_type;
1517 }
7ff93f8b 1518 info->port_attr.show = show_port_type;
3691c964 1519 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 1520
1521 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1522 if (err) {
1523 mlx4_err(dev, "Failed to create file for port %d\n", port);
1524 info->port = -1;
1525 }
1526
1527 return err;
1528}
1529
1530static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1531{
1532 if (info->port < 0)
1533 return;
1534
1535 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2a2336f8
YP		 1536}
1537
b12d93d6
YP		 1538static int mlx4_init_steering(struct mlx4_dev *dev)
1539{
1540 struct mlx4_priv *priv = mlx4_priv(dev);
1541 int num_entries = dev->caps.num_ports;
1542 int i, j;
1543
1544 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1545 if (!priv->steer)
1546 return -ENOMEM;
1547
1548 for (i = 0; i < num_entries; i++) {
1549 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1550 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1551 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1552 }
1553 INIT_LIST_HEAD(&priv->steer[i].high_prios);
1554 }
1555 return 0;
1556}
1557
1558static void mlx4_clear_steering(struct mlx4_dev *dev)
1559{
1560 struct mlx4_priv *priv = mlx4_priv(dev);
1561 struct mlx4_steer_index *entry, *tmp_entry;
1562 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1563 int num_entries = dev->caps.num_ports;
1564 int i, j;
1565
1566 for (i = 0; i < num_entries; i++) {
1567 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1568 list_for_each_entry_safe(pqp, tmp_pqp,
1569 &priv->steer[i].promisc_qps[j],
1570 list) {
1571 list_del(&pqp->list);
1572 kfree(pqp);
1573 }
1574 list_for_each_entry_safe(entry, tmp_entry,
1575 &priv->steer[i].steer_entries[j],
1576 list) {
1577 list_del(&entry->list);
1578 list_for_each_entry_safe(pqp, tmp_pqp,
1579 &entry->duplicates,
1580 list) {
1581 list_del(&pqp->list);
1582 kfree(pqp);
1583 }
1584 kfree(entry);
1585 }
1586 }
1587 }
1588 kfree(priv->steer);
1589}
1590
ab9c17a0
JM		 1591static int extended_func_num(struct pci_dev *pdev)
1592{
1593 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
1594}
1595
1596#define MLX4_OWNER_BASE 0x8069c
1597#define MLX4_OWNER_SIZE 4
1598
1599static int mlx4_get_ownership(struct mlx4_dev *dev)
1600{
1601 void __iomem *owner;
1602 u32 ret;
1603
1604 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1605 MLX4_OWNER_SIZE);
1606 if (!owner) {
1607 mlx4_err(dev, "Failed to obtain ownership bit\n");
1608 return -ENOMEM;
1609 }
1610
1611 ret = readl(owner);
1612 iounmap(owner);
1613 return (int) !!ret;
1614}
1615
1616static void mlx4_free_ownership(struct mlx4_dev *dev)
1617{
1618 void __iomem *owner;
1619
1620 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1621 MLX4_OWNER_SIZE);
1622 if (!owner) {
1623 mlx4_err(dev, "Failed to obtain ownership bit\n");
1624 return;
1625 }
1626 writel(0, owner);
1627 msleep(1000);
1628 iounmap(owner);
1629}
1630
3d73c288 1631static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
225c7b1f 1632{
225c7b1f
RD		 1633 struct mlx4_priv *priv;
1634 struct mlx4_dev *dev;
1635 int err;
2a2336f8 1636 int port;
225c7b1f 1637
0a645e80 1638 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 1639
1640 err = pci_enable_device(pdev);
1641 if (err) {
1642 dev_err(&pdev->dev, "Cannot enable PCI device, "
1643 "aborting.\n");
1644 return err;
1645 }
ab9c17a0
JM		 1646 if (num_vfs > MLX4_MAX_NUM_VF) {
1647 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
1648 num_vfs, MLX4_MAX_NUM_VF);
1649 return -EINVAL;
1650 }
225c7b1f 1651 /*
ab9c17a0 1652 * Check for BARs.
225c7b1f 1653 */
ab9c17a0
JM		 1654 if (((id == NULL) || !(id->driver_data & MLX4_VF)) &&
1655 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1656 dev_err(&pdev->dev, "Missing DCS, aborting."
1657 "(id == 0X%p, id->driver_data: 0x%lx,"
1658 " pci_resource_flags(pdev, 0):0x%lx)\n", id,
1659 id ? id->driver_data : 0, pci_resource_flags(pdev, 0));
225c7b1f
RD		 1660 err = -ENODEV;
1661 goto err_disable_pdev;
1662 }
1663 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1664 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1665 err = -ENODEV;
1666 goto err_disable_pdev;
1667 }
1668
a01df0fe 1669 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 1670 if (err) {
a01df0fe 1671 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 1672 goto err_disable_pdev;
1673 }
1674
225c7b1f
RD		 1675 pci_set_master(pdev);
1676
6a35528a 1677 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1678 if (err) {
1679 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 1680 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1681 if (err) {
1682 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 1683 goto err_release_regions;
225c7b1f
RD		 1684 }
1685 }
6a35528a 1686 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1687 if (err) {
1688 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1689 "consistent PCI DMA mask.\n");
284901a9 1690 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1691 if (err) {
1692 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1693 "aborting.\n");
a01df0fe 1694 goto err_release_regions;
225c7b1f
RD		 1695 }
1696 }
1697
7f9e5c48
DD		 1698 /* Allow large DMA segments, up to the firmware limit of 1 GB */
1699 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1700
225c7b1f
RD		 1701 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1702 if (!priv) {
1703 dev_err(&pdev->dev, "Device struct alloc failed, "
1704 "aborting.\n");
1705 err = -ENOMEM;
a01df0fe 1706 goto err_release_regions;
225c7b1f
RD		 1707 }
1708
1709 dev = &priv->dev;
1710 dev->pdev = pdev;
b581401e
RD		 1711 INIT_LIST_HEAD(&priv->ctx_list);
1712 spin_lock_init(&priv->ctx_lock);
225c7b1f 1713
7ff93f8b
YP		 1714 mutex_init(&priv->port_mutex);
1715
6296883c
YP		 1716 INIT_LIST_HEAD(&priv->pgdir_list);
1717 mutex_init(&priv->pgdir_mutex);
1718
c1b43dca
EC		 1719 INIT_LIST_HEAD(&priv->bf_list);
1720 mutex_init(&priv->bf_mutex);
1721
aca7a3ac 1722 dev->rev_id = pdev->revision;
ab9c17a0
JM		 1723 /* Detect if this device is a virtual function */
1724 if (id && id->driver_data & MLX4_VF) {
1725 /* When acting as pf, we normally skip vfs unless explicitly
1726 * requested to probe them. */
1727 if (num_vfs && extended_func_num(pdev) > probe_vf) {
1728 mlx4_warn(dev, "Skipping virtual function:%d\n",
1729 extended_func_num(pdev));
1730 err = -ENODEV;
1731 goto err_free_dev;
1732 }
1733 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
1734 dev->flags |= MLX4_FLAG_SLAVE;
1735 } else {
1736 /* We reset the device and enable SRIOV only for physical
1737 * devices. Try to claim ownership on the device;
1738 * if already taken, skip -- do not allow multiple PFs */
1739 err = mlx4_get_ownership(dev);
1740 if (err) {
1741 if (err < 0)
1742 goto err_free_dev;
1743 else {
1744 mlx4_warn(dev, "Multiple PFs not yet supported."
1745 " Skipping PF.\n");
1746 err = -EINVAL;
1747 goto err_free_dev;
1748 }
1749 }
aca7a3ac 1750
ab9c17a0
JM		 1751 if (num_vfs) {
1752 mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs);
1753 err = pci_enable_sriov(pdev, num_vfs);
1754 if (err) {
1755 mlx4_err(dev, "Failed to enable sriov,"
1756 "continuing without sriov enabled"
1757 " (err = %d).\n", err);
1758 num_vfs = 0;
1759 err = 0;
1760 } else {
1761 mlx4_warn(dev, "Running in master mode\n");
1762 dev->flags |= MLX4_FLAG_SRIOV |
1763 MLX4_FLAG_MASTER;
1764 dev->num_vfs = num_vfs;
1765 }
1766 }
1767
1768 /*
1769 * Now reset the HCA before we touch the PCI capabilities or
1770 * attempt a firmware command, since a boot ROM may have left
1771 * the HCA in an undefined state.
1772 */
1773 err = mlx4_reset(dev);
1774 if (err) {
1775 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1776 goto err_rel_own;
1777 }
225c7b1f
RD		 1778 }
1779
ab9c17a0 1780slave_start:
225c7b1f
RD		 1781 if (mlx4_cmd_init(dev)) {
1782 mlx4_err(dev, "Failed to init command interface, aborting.\n");
ab9c17a0
JM		 1783 goto err_sriov;
1784 }
1785
1786 /* In slave functions, the communication channel must be initialized
1787 * before posting commands. Also, init num_slaves before calling
1788 * mlx4_init_hca */
1789 if (mlx4_is_mfunc(dev)) {
1790 if (mlx4_is_master(dev))
1791 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
1792 else {
1793 dev->num_slaves = 0;
1794 if (mlx4_multi_func_init(dev)) {
1795 mlx4_err(dev, "Failed to init slave mfunc"
1796 " interface, aborting.\n");
1797 goto err_cmd;
1798 }
1799 }
225c7b1f
RD		 1800 }
1801
1802 err = mlx4_init_hca(dev);
ab9c17a0
JM		 1803 if (err) {
1804 if (err == -EACCES) {
1805 /* Not primary Physical function
1806 * Running in slave mode */
1807 mlx4_cmd_cleanup(dev);
1808 dev->flags |= MLX4_FLAG_SLAVE;
1809 dev->flags &= ~MLX4_FLAG_MASTER;
1810 goto slave_start;
1811 } else
1812 goto err_mfunc;
1813 }
1814
1815 /* In master functions, the communication channel must be initialized
1816 * after obtaining its address from fw */
1817 if (mlx4_is_master(dev)) {
1818 if (mlx4_multi_func_init(dev)) {
1819 mlx4_err(dev, "Failed to init master mfunc"
1820 "interface, aborting.\n");
1821 goto err_close;
1822 }
1823 }
225c7b1f 1824
b8dd786f
YP		 1825 err = mlx4_alloc_eq_table(dev);
1826 if (err)
ab9c17a0 1827 goto err_master_mfunc;
b8dd786f 1828
0b7ca5a9 1829 priv->msix_ctl.pool_bm = 0;
730c41d5 1830 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 1831
08fb1055 1832 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 1833 if ((mlx4_is_mfunc(dev)) &&
1834 !(dev->flags & MLX4_FLAG_MSI_X)) {
1835 mlx4_err(dev, "INTx is not supported in multi-function mode."
1836 " aborting.\n");
b12d93d6 1837 goto err_free_eq;
ab9c17a0
JM		 1838 }
1839
1840 if (!mlx4_is_slave(dev)) {
1841 err = mlx4_init_steering(dev);
1842 if (err)
1843 goto err_free_eq;
1844 }
b12d93d6 1845
225c7b1f 1846 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 1847 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
1848 !mlx4_is_mfunc(dev)) {
08fb1055
MT		 1849 dev->flags &= ~MLX4_FLAG_MSI_X;
1850 pci_disable_msix(pdev);
1851 err = mlx4_setup_hca(dev);
1852 }
1853
225c7b1f 1854 if (err)
b12d93d6 1855 goto err_steer;
225c7b1f 1856
7ff93f8b
YP		 1857 for (port = 1; port <= dev->caps.num_ports; port++) {
1858 err = mlx4_init_port_info(dev, port);
1859 if (err)
1860 goto err_port;
1861 }
2a2336f8 1862
225c7b1f
RD		 1863 err = mlx4_register_device(dev);
1864 if (err)
7ff93f8b 1865 goto err_port;
225c7b1f 1866
27bf91d6
YP		 1867 mlx4_sense_init(dev);
1868 mlx4_start_sense(dev);
1869
225c7b1f
RD		 1870 pci_set_drvdata(pdev, dev);
1871
1872 return 0;
1873
7ff93f8b 1874err_port:
b4f77264 1875 for (--port; port >= 1; --port)
7ff93f8b
YP		 1876 mlx4_cleanup_port_info(&priv->port[port]);
1877
f2a3f6a3 1878 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 1879 mlx4_cleanup_mcg_table(dev);
1880 mlx4_cleanup_qp_table(dev);
1881 mlx4_cleanup_srq_table(dev);
1882 mlx4_cleanup_cq_table(dev);
1883 mlx4_cmd_use_polling(dev);
1884 mlx4_cleanup_eq_table(dev);
225c7b1f 1885 mlx4_cleanup_mr_table(dev);
012a8ff5 1886 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 1887 mlx4_cleanup_pd_table(dev);
1888 mlx4_cleanup_uar_table(dev);
1889
b12d93d6 1890err_steer:
ab9c17a0
JM		 1891 if (!mlx4_is_slave(dev))
1892 mlx4_clear_steering(dev);
b12d93d6 1893
b8dd786f
YP		 1894err_free_eq:
1895 mlx4_free_eq_table(dev);
1896
ab9c17a0
JM		 1897err_master_mfunc:
1898 if (mlx4_is_master(dev))
1899 mlx4_multi_func_cleanup(dev);
1900
225c7b1f 1901err_close:
08fb1055
MT		 1902 if (dev->flags & MLX4_FLAG_MSI_X)
1903 pci_disable_msix(pdev);
1904
225c7b1f
RD		 1905 mlx4_close_hca(dev);
1906
ab9c17a0
JM		 1907err_mfunc:
1908 if (mlx4_is_slave(dev))
1909 mlx4_multi_func_cleanup(dev);
1910
225c7b1f
RD		 1911err_cmd:
1912 mlx4_cmd_cleanup(dev);
1913
ab9c17a0
JM		 1914err_sriov:
1915 if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV))
1916 pci_disable_sriov(pdev);
1917
1918err_rel_own:
1919 if (!mlx4_is_slave(dev))
1920 mlx4_free_ownership(dev);
1921
225c7b1f 1922err_free_dev:
225c7b1f
RD		 1923 kfree(priv);
1924
a01df0fe
RD		 1925err_release_regions:
1926 pci_release_regions(pdev);
225c7b1f
RD		 1927
1928err_disable_pdev:
1929 pci_disable_device(pdev);
1930 pci_set_drvdata(pdev, NULL);
1931 return err;
1932}
1933
3d73c288
RD		 1934static int __devinit mlx4_init_one(struct pci_dev *pdev,
1935 const struct pci_device_id *id)
1936{
0a645e80 1937 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 1938
b027cacd 1939 return __mlx4_init_one(pdev, id);
3d73c288
RD		 1940}
1941
1942static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 1943{
1944 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1945 struct mlx4_priv *priv = mlx4_priv(dev);
1946 int p;
1947
1948 if (dev) {
ab9c17a0
JM		 1949 /* in SRIOV it is not allowed to unload the pf's
1950 * driver while there are alive vf's */
1951 if (mlx4_is_master(dev)) {
1952 if (mlx4_how_many_lives_vf(dev))
1953 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
1954 }
27bf91d6 1955 mlx4_stop_sense(dev);
225c7b1f
RD		 1956 mlx4_unregister_device(dev);
1957
7ff93f8b
YP		 1958 for (p = 1; p <= dev->caps.num_ports; p++) {
1959 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 1960 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 1961 }
225c7b1f 1962
f2a3f6a3 1963 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 1964 mlx4_cleanup_mcg_table(dev);
1965 mlx4_cleanup_qp_table(dev);
1966 mlx4_cleanup_srq_table(dev);
1967 mlx4_cleanup_cq_table(dev);
1968 mlx4_cmd_use_polling(dev);
1969 mlx4_cleanup_eq_table(dev);
225c7b1f 1970 mlx4_cleanup_mr_table(dev);
012a8ff5 1971 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 1972 mlx4_cleanup_pd_table(dev);
1973
ab9c17a0
JM		 1974 if (mlx4_is_master(dev))
1975 mlx4_free_resource_tracker(dev);
1976
225c7b1f
RD		 1977 iounmap(priv->kar);
1978 mlx4_uar_free(dev, &priv->driver_uar);
1979 mlx4_cleanup_uar_table(dev);
ab9c17a0
JM		 1980 if (!mlx4_is_slave(dev))
1981 mlx4_clear_steering(dev);
b8dd786f 1982 mlx4_free_eq_table(dev);
ab9c17a0
JM		 1983 if (mlx4_is_master(dev))
1984 mlx4_multi_func_cleanup(dev);
225c7b1f 1985 mlx4_close_hca(dev);
ab9c17a0
JM		 1986 if (mlx4_is_slave(dev))
1987 mlx4_multi_func_cleanup(dev);
225c7b1f
RD		 1988 mlx4_cmd_cleanup(dev);
1989
1990 if (dev->flags & MLX4_FLAG_MSI_X)
1991 pci_disable_msix(pdev);
ab9c17a0
JM		 1992 if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV)) {
1993 mlx4_warn(dev, "Disabling sriov\n");
1994 pci_disable_sriov(pdev);
1995 }
225c7b1f 1996
ab9c17a0
JM		 1997 if (!mlx4_is_slave(dev))
1998 mlx4_free_ownership(dev);
225c7b1f 1999 kfree(priv);
a01df0fe 2000 pci_release_regions(pdev);
225c7b1f
RD		 2001 pci_disable_device(pdev);
2002 pci_set_drvdata(pdev, NULL);
2003 }
2004}
2005
ee49bd93
JM		 2006int mlx4_restart_one(struct pci_dev *pdev)
2007{
2008 mlx4_remove_one(pdev);
3d73c288 2009 return __mlx4_init_one(pdev, NULL);
ee49bd93
JM		 2010}
2011
a3aa1884 2012static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0
JM		 2013 /* MT25408 "Hermon" SDR */
2014 { PCI_VDEVICE(MELLANOX, 0x6340), 0 },
2015 /* MT25408 "Hermon" DDR */
2016 { PCI_VDEVICE(MELLANOX, 0x634a), 0 },
2017 /* MT25408 "Hermon" QDR */
2018 { PCI_VDEVICE(MELLANOX, 0x6354), 0 },
2019 /* MT25408 "Hermon" DDR PCIe gen2 */
2020 { PCI_VDEVICE(MELLANOX, 0x6732), 0 },
2021 /* MT25408 "Hermon" QDR PCIe gen2 */
2022 { PCI_VDEVICE(MELLANOX, 0x673c), 0 },
2023 /* MT25408 "Hermon" EN 10GigE */
2024 { PCI_VDEVICE(MELLANOX, 0x6368), 0 },
2025 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2026 { PCI_VDEVICE(MELLANOX, 0x6750), 0 },
2027 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2028 { PCI_VDEVICE(MELLANOX, 0x6372), 0 },
2029 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2030 { PCI_VDEVICE(MELLANOX, 0x675a), 0 },
2031 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2032 { PCI_VDEVICE(MELLANOX, 0x6764), 0 },
2033 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2034 { PCI_VDEVICE(MELLANOX, 0x6746), 0 },
2035 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2036 { PCI_VDEVICE(MELLANOX, 0x676e), 0 },
2037 /* MT25400 Family [ConnectX-2 Virtual Function] */
2038 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_VF },
2039 /* MT27500 Family [ConnectX-3] */
2040 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2041 /* MT27500 Family [ConnectX-3 Virtual Function] */
2042 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_VF },
2043 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2044 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2045 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2046 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2047 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2048 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2049 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2050 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2051 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2052 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2053 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2054 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2055 { 0, }
2056};
2057
2058MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2059
2060static struct pci_driver mlx4_driver = {
2061 .name = DRV_NAME,
2062 .id_table = mlx4_pci_table,
2063 .probe = mlx4_init_one,
2064 .remove = __devexit_p(mlx4_remove_one)
2065};
2066
7ff93f8b
YP		 2067static int __init mlx4_verify_params(void)
2068{
2069 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2070 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2071 return -1;
2072 }
2073
cb29688a
OG		 2074 if (log_num_vlan != 0)
2075 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2076 MLX4_LOG_NUM_VLANS);
7ff93f8b 2077
0498628f 2078 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2079 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2080 return -1;
2081 }
2082
ab9c17a0
JM		 2083 /* Check if module param for ports type has legal combination */
2084 if (port_type_array[0] == false && port_type_array[1] == true) {
2085 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2086 port_type_array[0] = true;
2087 }
2088
7ff93f8b
YP		 2089 return 0;
2090}
2091
225c7b1f
RD		 2092static int __init mlx4_init(void)
2093{
2094 int ret;
2095
7ff93f8b
YP		 2096 if (mlx4_verify_params())
2097 return -EINVAL;
2098
27bf91d6
YP		 2099 mlx4_catas_init();
2100
2101 mlx4_wq = create_singlethread_workqueue("mlx4");
2102 if (!mlx4_wq)
2103 return -ENOMEM;
ee49bd93 2104
225c7b1f
RD		 2105 ret = pci_register_driver(&mlx4_driver);
2106 return ret < 0 ? ret : 0;
2107}
2108
2109static void __exit mlx4_cleanup(void)
2110{
2111 pci_unregister_driver(&mlx4_driver);
27bf91d6 2112 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2113}
2114
2115module_init(mlx4_init);
2116module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)