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net/mlx5_core: Wait for FW readiness on startup
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
dd41cc3b 80static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 81static int num_vfs_argc;
dd41cc3b
MB		 82module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 87static int probe_vfs_argc;
dd41cc3b
MB		 88module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
ab9c17a0 91
3c439b55 92int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 93module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
3c439b55 97 " 10 gives 248.range: 7 <="
0ff1fb65 98 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 99 " To activate device managed"
100 " flow steering when available, set to -1");
0ec2c0f8 101
be902ab1 102static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 103module_param(enable_64b_cqe_eqe, bool, 0444);
104MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 106
77507aa2 107#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
7d077cd3
MB		 108 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
109 MLX4_FUNC_CAP_DMFS_A0_STATIC)
ab9c17a0 110
55ad3592
YH		 111#define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV)
112
f57e6848 113static char mlx4_version[] =
225c7b1f
RD		 114 DRV_NAME ": Mellanox ConnectX core driver v"
115 DRV_VERSION " (" DRV_RELDATE ")\n";
116
117static struct mlx4_profile default_profile = {
ab9c17a0 118 .num_qp = 1 << 18,
225c7b1f 119 .num_srq = 1 << 16,
c9f2ba5e 120 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 121 .num_cq = 1 << 16,
122 .num_mcg = 1 << 13,
ab9c17a0 123 .num_mpt = 1 << 19,
9fd7a1e1 124 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 125};
126
2599d858
AV		 127static struct mlx4_profile low_mem_profile = {
128 .num_qp = 1 << 17,
129 .num_srq = 1 << 6,
130 .rdmarc_per_qp = 1 << 4,
131 .num_cq = 1 << 8,
132 .num_mcg = 1 << 8,
133 .num_mpt = 1 << 9,
134 .num_mtt = 1 << 7,
135};
136
ab9c17a0 137static int log_num_mac = 7;
93fc9e1b
YP		 138module_param_named(log_num_mac, log_num_mac, int, 0444);
139MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
140
141static int log_num_vlan;
142module_param_named(log_num_vlan, log_num_vlan, int, 0444);
143MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 144/* Log2 max number of VLANs per ETH port (0-7) */
145#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 146#define MLX4_MIN_LOG_NUM_VLANS 0
147#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 148
eb939922 149static bool use_prio;
93fc9e1b 150module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 151MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 152
2b8fb286 153int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 154module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 155MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 156
8d0fc7b6 157static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 158static int arr_argc = 2;
159module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 160MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
161 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 162
163struct mlx4_port_config {
164 struct list_head list;
165 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
166 struct pci_dev *pdev;
167};
168
97989356
AV		 169static atomic_t pf_loading = ATOMIC_INIT(0);
170
27bf91d6
YP		 171int mlx4_check_port_params(struct mlx4_dev *dev,
172 enum mlx4_port_type *port_type)
7ff93f8b
YP		 173{
174 int i;
175
0b997657
YS		 176 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
177 for (i = 0; i < dev->caps.num_ports - 1; i++) {
178 if (port_type[i] != port_type[i + 1]) {
1a91de28 179 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 180 return -EINVAL;
181 }
7ff93f8b
YP		 182 }
183 }
7ff93f8b
YP		 184
185 for (i = 0; i < dev->caps.num_ports; i++) {
186 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 187 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
188 i + 1);
7ff93f8b
YP		 189 return -EINVAL;
190 }
191 }
192 return 0;
193}
194
195static void mlx4_set_port_mask(struct mlx4_dev *dev)
196{
197 int i;
198
7ff93f8b 199 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 200 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 201}
f2a3f6a3 202
7ae0e400
MB		 203enum {
204 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
205};
206
207static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
208{
209 int err = 0;
210 struct mlx4_func func;
211
212 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
213 err = mlx4_QUERY_FUNC(dev, &func, 0);
214 if (err) {
215 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
216 return err;
217 }
218 dev_cap->max_eqs = func.max_eq;
219 dev_cap->reserved_eqs = func.rsvd_eqs;
220 dev_cap->reserved_uars = func.rsvd_uars;
221 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
222 }
223 return err;
224}
225
77507aa2
IS		 226static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
227{
228 struct mlx4_caps *dev_cap = &dev->caps;
229
230 /* FW not supporting or cancelled by user */
231 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
232 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
233 return;
234
235 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
236 * When FW has NCSI it may decide not to report 64B CQE/EQEs
237 */
238 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
239 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
240 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
241 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
242 return;
243 }
244
245 if (cache_line_size() == 128 || cache_line_size() == 256) {
246 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
247 /* Changing the real data inside CQE size to 32B */
248 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
249 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
250
251 if (mlx4_is_master(dev))
252 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
253 } else {
0fab541a
OG		 254 if (cache_line_size() != 32 && cache_line_size() != 64)
255 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
77507aa2
IS		 256 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
257 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
258 }
259}
260
431df8c7
MB		 261static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
262 struct mlx4_port_cap *port_cap)
263{
264 dev->caps.vl_cap[port] = port_cap->max_vl;
265 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
266 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
267 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
268 /* set gid and pkey table operating lengths by default
269 * to non-sriov values
270 */
271 dev->caps.gid_table_len[port] = port_cap->max_gids;
272 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
273 dev->caps.port_width_cap[port] = port_cap->max_port_width;
274 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
275 dev->caps.def_mac[port] = port_cap->def_mac;
276 dev->caps.supported_type[port] = port_cap->supported_port_types;
277 dev->caps.suggested_type[port] = port_cap->suggested_type;
278 dev->caps.default_sense[port] = port_cap->default_sense;
279 dev->caps.trans_type[port] = port_cap->trans_type;
280 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
281 dev->caps.wavelength[port] = port_cap->wavelength;
282 dev->caps.trans_code[port] = port_cap->trans_code;
283
284 return 0;
285}
286
287static int mlx4_dev_port(struct mlx4_dev *dev, int port,
288 struct mlx4_port_cap *port_cap)
289{
290 int err = 0;
291
292 err = mlx4_QUERY_PORT(dev, port, port_cap);
293
294 if (err)
295 mlx4_err(dev, "QUERY_PORT command failed.\n");
296
297 return err;
298}
299
78500b8c
MM		 300static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
301{
302 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
303 return;
304
305 if (mlx4_is_mfunc(dev)) {
306 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
307 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
308 return;
309 }
310
311 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
312 mlx4_dbg(dev,
313 "Keep FCS is not supported - Disabling Ignore FCS");
314 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
315 return;
316 }
317}
318
431df8c7 319#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 320static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 321{
322 int err;
5ae2a7a8 323 int i;
225c7b1f
RD		 324
325 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
326 if (err) {
1a91de28 327 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 328 return err;
329 }
c78e25ed 330 mlx4_dev_cap_dump(dev, dev_cap);
225c7b1f
RD		 331
332 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 333 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 334 dev_cap->min_page_sz, PAGE_SIZE);
335 return -ENODEV;
336 }
337 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 338 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 339 dev_cap->num_ports, MLX4_MAX_PORTS);
340 return -ENODEV;
341 }
342
872bf2fb 343 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
1a91de28 344 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f 345 dev_cap->uar_size,
872bf2fb
YH		 346 (unsigned long long)
347 pci_resource_len(dev->persist->pdev, 2));
225c7b1f
RD		 348 return -ENODEV;
349 }
350
351 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 352 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
353 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
354 dev->caps.num_sys_eqs :
355 MLX4_MAX_EQ_NUM;
5ae2a7a8 356 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 357 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
358 if (err) {
359 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
360 return err;
361 }
5ae2a7a8
RD		 362 }
363
ab9c17a0 364 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 365 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 366 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
367 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
368 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
369 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
370 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
371 dev->caps.max_wqes = dev_cap->max_qp_sz;
372 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 373 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
374 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
375 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
376 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
377 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 378 /*
379 * Subtract 1 from the limit because we need to allocate a
380 * spare CQE so the HCA HW can tell the difference between an
381 * empty CQ and a full CQ.
382 */
383 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
384 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
385 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 386 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 387 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 388
389 /* The first 128 UARs are used for EQ doorbells */
390 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 391 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 392 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
393 dev_cap->reserved_xrcds : 0;
394 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
395 dev_cap->max_xrcds : 0;
2b8fb286
MA		 396 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
397
149983af 398 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 399 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
400 dev->caps.flags = dev_cap->flags;
b3416f44 401 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 402 dev->caps.bmme_flags = dev_cap->bmme_flags;
403 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 404 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 405 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 406 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 407
77fc29c4
HHZ		 408 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
409 struct mlx4_init_hca_param hca_param;
410
411 memset(&hca_param, 0, sizeof(hca_param));
412 err = mlx4_QUERY_HCA(dev, &hca_param);
413 /* Turn off PHV_EN flag in case phv_check_en is set.
414 * phv_check_en is a HW check that parse the packet and verify
415 * phv bit was reported correctly in the wqe. To allow QinQ
416 * PHV_EN flag should be set and phv_check_en must be cleared
417 * otherwise QinQ packets will be drop by the HW.
418 */
419 if (err || hca_param.phv_check_en)
420 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
421 }
422
ca3e57a5
RD		 423 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
424 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 425 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 426 /* Don't do sense port on multifunction devices (for now at least) */
427 if (mlx4_is_mfunc(dev))
428 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 429
2599d858
AV		 430 if (mlx4_low_memory_profile()) {
431 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
432 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
433 } else {
434 dev->caps.log_num_macs = log_num_mac;
435 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
436 }
93fc9e1b
YP		 437
438 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 439 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
440 if (dev->caps.supported_type[i]) {
441 /* if only ETH is supported - assign ETH */
442 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
443 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 444 /* if only IB is supported, assign IB */
ab9c17a0 445 else if (dev->caps.supported_type[i] ==
105c320f
JM		 446 MLX4_PORT_TYPE_IB)
447 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 448 else {
105c320f
JM		 449 /* if IB and ETH are supported, we set the port
450 * type according to user selection of port type;
451 * if user selected none, take the FW hint */
452 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 453 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
454 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 455 else
105c320f 456 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 457 }
458 }
8d0fc7b6
YP		 459 /*
460 * Link sensing is allowed on the port if 3 conditions are true:
461 * 1. Both protocols are supported on the port.
462 * 2. Different types are supported on the port
463 * 3. FW declared that it supports link sensing
464 */
27bf91d6 465 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 466 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 467 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 468 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 469
8d0fc7b6
YP		 470 /*
471 * If "default_sense" bit is set, we move the port to "AUTO" mode
472 * and perform sense_port FW command to try and set the correct
473 * port type from beginning
474 */
46c46747 475 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 476 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
477 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
478 mlx4_SENSE_PORT(dev, i, &sensed_port);
479 if (sensed_port != MLX4_PORT_TYPE_NONE)
480 dev->caps.port_type[i] = sensed_port;
481 } else {
482 dev->caps.possible_type[i] = dev->caps.port_type[i];
483 }
484
431df8c7
MB		 485 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
486 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 487 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 488 i, 1 << dev->caps.log_num_macs);
489 }
431df8c7
MB		 490 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
491 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 492 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 493 i, 1 << dev->caps.log_num_vlans);
494 }
495 }
496
ac0a72a3
OG		 497 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
498 (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
499 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
500 mlx4_warn(dev,
501 "Granular QoS per VF not supported with IB/Eth configuration\n");
502 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
503 }
504
47d8417f 505 dev->caps.max_counters = dev_cap->max_counters;
f2a3f6a3 506
93fc9e1b
YP		 507 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
508 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
509 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
510 (1 << dev->caps.log_num_macs) *
511 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 512 dev->caps.num_ports;
513 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
7d077cd3
MB		 514
515 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
516 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
517 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
518 else
519 dev->caps.dmfs_high_rate_qpn_base =
520 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
521
522 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
523 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
524 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
525 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
526 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
527 } else {
528 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
529 dev->caps.dmfs_high_rate_qpn_base =
530 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
531 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
532 }
533
fc31e256
OG		 534 dev->caps.rl_caps = dev_cap->rl_caps;
535
d57febe1 536 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
7d077cd3 537 dev->caps.dmfs_high_rate_qpn_range;
93fc9e1b
YP		 538
539 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
540 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
541 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
542 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
543
e2c76824 544 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 545
b3051320 546 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 547 if (dev_cap->flags &
548 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
549 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
550 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
551 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
552 }
77507aa2
IS		 553
554 if (dev_cap->flags2 &
555 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
556 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
557 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
558 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
559 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
560 }
08ff3235
OG		 561 }
562
f97b4b5d 563 if ((dev->caps.flags &
08ff3235
OG		 564 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
565 mlx4_is_master(dev))
566 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
567
ddae0349 568 if (!mlx4_is_slave(dev)) {
77507aa2 569 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 570 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 571 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
572 MLX4_RESERVE_A0_QP;
3742cc65
IS		 573
574 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
575 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
576 mlx4_warn(dev, "Old device ETS support detected\n");
577 mlx4_warn(dev, "Consider upgrading device FW.\n");
578 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
579 }
580
ddae0349
EE		 581 } else {
582 dev->caps.alloc_res_qp_mask = 0;
583 }
77507aa2 584
78500b8c
MM		 585 mlx4_enable_ignore_fcs(dev);
586
225c7b1f
RD		 587 return 0;
588}
b912b2f8
EP		 589
590static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
591 enum pci_bus_speed *speed,
592 enum pcie_link_width *width)
593{
594 u32 lnkcap1, lnkcap2;
595 int err1, err2;
596
597#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
598
599 *speed = PCI_SPEED_UNKNOWN;
600 *width = PCIE_LNK_WIDTH_UNKNOWN;
601
872bf2fb
YH		 602 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
603 &lnkcap1);
604 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
605 &lnkcap2);
b912b2f8
EP		 606 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
607 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
608 *speed = PCIE_SPEED_8_0GT;
609 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
610 *speed = PCIE_SPEED_5_0GT;
611 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
612 *speed = PCIE_SPEED_2_5GT;
613 }
614 if (!err1) {
615 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
616 if (!lnkcap2) { /* pre-r3.0 */
617 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
618 *speed = PCIE_SPEED_5_0GT;
619 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
620 *speed = PCIE_SPEED_2_5GT;
621 }
622 }
623
624 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
625 return err1 ? err1 :
626 err2 ? err2 : -EINVAL;
627 }
628 return 0;
629}
630
631static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
632{
633 enum pcie_link_width width, width_cap;
634 enum pci_bus_speed speed, speed_cap;
635 int err;
636
637#define PCIE_SPEED_STR(speed) \
638 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
639 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
640 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
641 "Unknown")
642
643 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
644 if (err) {
645 mlx4_warn(dev,
646 "Unable to determine PCIe device BW capabilities\n");
647 return;
648 }
649
872bf2fb 650 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
b912b2f8
EP		 651 if (err || speed == PCI_SPEED_UNKNOWN ||
652 width == PCIE_LNK_WIDTH_UNKNOWN) {
653 mlx4_warn(dev,
654 "Unable to determine PCI device chain minimum BW\n");
655 return;
656 }
657
658 if (width != width_cap || speed != speed_cap)
659 mlx4_warn(dev,
660 "PCIe BW is different than device's capability\n");
661
662 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
663 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
664 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
665 width, width_cap);
666 return;
667}
668
ab9c17a0
JM		 669/*The function checks if there are live vf, return the num of them*/
670static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
671{
672 struct mlx4_priv *priv = mlx4_priv(dev);
673 struct mlx4_slave_state *s_state;
674 int i;
675 int ret = 0;
676
677 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
678 s_state = &priv->mfunc.master.slave_state[i];
679 if (s_state->active && s_state->last_cmd !=
680 MLX4_COMM_CMD_RESET) {
681 mlx4_warn(dev, "%s: slave: %d is still active\n",
682 __func__, i);
683 ret++;
684 }
685 }
686 return ret;
687}
688
396f2feb
JM		 689int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
690{
691 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 692
693 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
694 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 695 return -EINVAL;
696
47605df9 697 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 698 /* tunnel qp */
47605df9 699 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 700 else
47605df9 701 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 702 *qkey = qk;
703 return 0;
704}
705EXPORT_SYMBOL(mlx4_get_parav_qkey);
706
54679e14
JM		 707void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
708{
709 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
710
711 if (!mlx4_is_master(dev))
712 return;
713
714 priv->virt2phys_pkey[slave][port - 1][i] = val;
715}
716EXPORT_SYMBOL(mlx4_sync_pkey_table);
717
afa8fd1d
JM		 718void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
719{
720 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
721
722 if (!mlx4_is_master(dev))
723 return;
724
725 priv->slave_node_guids[slave] = guid;
726}
727EXPORT_SYMBOL(mlx4_put_slave_node_guid);
728
729__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
730{
731 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
732
733 if (!mlx4_is_master(dev))
734 return 0;
735
736 return priv->slave_node_guids[slave];
737}
738EXPORT_SYMBOL(mlx4_get_slave_node_guid);
739
e10903b0 740int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 741{
742 struct mlx4_priv *priv = mlx4_priv(dev);
743 struct mlx4_slave_state *s_slave;
744
745 if (!mlx4_is_master(dev))
746 return 0;
747
748 s_slave = &priv->mfunc.master.slave_state[slave];
749 return !!s_slave->active;
750}
751EXPORT_SYMBOL(mlx4_is_slave_active);
752
7b8157be
JM		 753static void slave_adjust_steering_mode(struct mlx4_dev *dev,
754 struct mlx4_dev_cap *dev_cap,
755 struct mlx4_init_hca_param *hca_param)
756{
757 dev->caps.steering_mode = hca_param->steering_mode;
758 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
759 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
760 dev->caps.fs_log_max_ucast_qp_range_size =
761 dev_cap->fs_log_max_ucast_qp_range_size;
762 } else
763 dev->caps.num_qp_per_mgm =
764 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
765
766 mlx4_dbg(dev, "Steering mode is: %s\n",
767 mlx4_steering_mode_str(dev->caps.steering_mode));
768}
769
ab9c17a0
JM		 770static int mlx4_slave_cap(struct mlx4_dev *dev)
771{
772 int err;
773 u32 page_size;
774 struct mlx4_dev_cap dev_cap;
775 struct mlx4_func_cap func_cap;
776 struct mlx4_init_hca_param hca_param;
225c6c8c 777 u8 i;
ab9c17a0
JM		 778
779 memset(&hca_param, 0, sizeof(hca_param));
780 err = mlx4_QUERY_HCA(dev, &hca_param);
781 if (err) {
1a91de28 782 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
ab9c17a0
JM		 783 return err;
784 }
785
483e0132
EP		 786 /* fail if the hca has an unknown global capability
787 * at this time global_caps should be always zeroed
788 */
789 if (hca_param.global_caps) {
ab9c17a0
JM		 790 mlx4_err(dev, "Unknown hca global capabilities\n");
791 return -ENOSYS;
792 }
793
794 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
795
ddd8a6c1
EE		 796 dev->caps.hca_core_clock = hca_param.hca_core_clock;
797
ab9c17a0 798 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 799 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 800 err = mlx4_dev_cap(dev, &dev_cap);
801 if (err) {
1a91de28 802 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 803 return err;
804 }
805
b91cb3eb
JM		 806 err = mlx4_QUERY_FW(dev);
807 if (err)
1a91de28 808 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 809
ab9c17a0
JM		 810 page_size = ~dev->caps.page_size_cap + 1;
811 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
812 if (page_size > PAGE_SIZE) {
1a91de28 813 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0
JM		 814 page_size, PAGE_SIZE);
815 return -ENODEV;
816 }
817
818 /* slave gets uar page size from QUERY_HCA fw command */
819 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
820
821 /* TODO: relax this assumption */
822 if (dev->caps.uar_page_size != PAGE_SIZE) {
823 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
824 dev->caps.uar_page_size, PAGE_SIZE);
825 return -ENODEV;
826 }
827
828 memset(&func_cap, 0, sizeof(func_cap));
47605df9 829 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 830 if (err) {
1a91de28
JP		 831 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
832 err);
ab9c17a0
JM		 833 return err;
834 }
835
836 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
837 PF_CONTEXT_BEHAVIOUR_MASK) {
7d077cd3
MB		 838 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
839 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
ab9c17a0
JM		 840 return -ENOSYS;
841 }
842
ab9c17a0 843 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 844 dev->quotas.qp = func_cap.qp_quota;
845 dev->quotas.srq = func_cap.srq_quota;
846 dev->quotas.cq = func_cap.cq_quota;
847 dev->quotas.mpt = func_cap.mpt_quota;
848 dev->quotas.mtt = func_cap.mtt_quota;
849 dev->caps.num_qps = 1 << hca_param.log_num_qps;
850 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
851 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
852 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
853 dev->caps.num_eqs = func_cap.max_eq;
854 dev->caps.reserved_eqs = func_cap.reserved_eq;
f0ce0615 855 dev->caps.reserved_lkey = func_cap.reserved_lkey;
ab9c17a0
JM		 856 dev->caps.num_pds = MLX4_NUM_PDS;
857 dev->caps.num_mgms = 0;
858 dev->caps.num_amgms = 0;
859
ab9c17a0 860 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 861 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
862 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 863 return -ENODEV;
864 }
865
99ec41d0 866 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
47605df9
JM		 867 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
868 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
869 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
870 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
871
872 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
99ec41d0
JM		 873 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
874 !dev->caps.qp0_qkey) {
47605df9
JM		 875 err = -ENOMEM;
876 goto err_mem;
877 }
878
6634961c 879 for (i = 1; i <= dev->caps.num_ports; ++i) {
225c6c8c 880 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
47605df9 881 if (err) {
1a91de28
JP		 882 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
883 i, err);
47605df9
JM		 884 goto err_mem;
885 }
99ec41d0 886 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
47605df9
JM		 887 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
888 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
889 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
890 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 891 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 892 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 893 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
894 &dev->caps.gid_table_len[i],
895 &dev->caps.pkey_table_len[i]))
47605df9 896 goto err_mem;
6634961c 897 }
6230bb23 898
ab9c17a0
JM		 899 if (dev->caps.uar_page_size * (dev->caps.num_uars -
900 dev->caps.reserved_uars) >
872bf2fb
YH		 901 pci_resource_len(dev->persist->pdev,
902 2)) {
1a91de28 903 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0 904 dev->caps.uar_page_size * dev->caps.num_uars,
872bf2fb
YH		 905 (unsigned long long)
906 pci_resource_len(dev->persist->pdev, 2));
47605df9 907 goto err_mem;
ab9c17a0
JM		 908 }
909
08ff3235
OG		 910 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
911 dev->caps.eqe_size = 64;
912 dev->caps.eqe_factor = 1;
913 } else {
914 dev->caps.eqe_size = 32;
915 dev->caps.eqe_factor = 0;
916 }
917
918 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
919 dev->caps.cqe_size = 64;
77507aa2 920 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 921 } else {
922 dev->caps.cqe_size = 32;
923 }
924
77507aa2
IS		 925 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
926 dev->caps.eqe_size = hca_param.eqe_size;
927 dev->caps.eqe_factor = 0;
928 }
929
930 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
931 dev->caps.cqe_size = hca_param.cqe_size;
932 /* User still need to know when CQE > 32B */
933 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
934 }
935
f9bd2d7f 936 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 937 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 938
7b8157be 939 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
802f42a8
IS		 940 mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
941 hca_param.rss_ip_frags ? "on" : "off");
7b8157be 942
ddae0349
EE		 943 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
944 dev->caps.bf_reg_size)
945 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
946
d57febe1
MB		 947 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
948 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
949
ab9c17a0 950 return 0;
47605df9
JM		 951
952err_mem:
99ec41d0 953 kfree(dev->caps.qp0_qkey);
47605df9
JM		 954 kfree(dev->caps.qp0_tunnel);
955 kfree(dev->caps.qp0_proxy);
956 kfree(dev->caps.qp1_tunnel);
957 kfree(dev->caps.qp1_proxy);
99ec41d0
JM		 958 dev->caps.qp0_qkey = NULL;
959 dev->caps.qp0_tunnel = NULL;
960 dev->caps.qp0_proxy = NULL;
961 dev->caps.qp1_tunnel = NULL;
962 dev->caps.qp1_proxy = NULL;
47605df9
JM		 963
964 return err;
ab9c17a0 965}
225c7b1f 966
b046ffe5
EP		 967static void mlx4_request_modules(struct mlx4_dev *dev)
968{
969 int port;
970 int has_ib_port = false;
971 int has_eth_port = false;
972#define EN_DRV_NAME "mlx4_en"
973#define IB_DRV_NAME "mlx4_ib"
974
975 for (port = 1; port <= dev->caps.num_ports; port++) {
976 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
977 has_ib_port = true;
978 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
979 has_eth_port = true;
980 }
981
b046ffe5
EP		 982 if (has_eth_port)
983 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 984 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
985 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 986}
987
7ff93f8b
YP		 988/*
989 * Change the port configuration of the device.
990 * Every user of this function must hold the port mutex.
991 */
27bf91d6
YP		 992int mlx4_change_port_types(struct mlx4_dev *dev,
993 enum mlx4_port_type *port_types)
7ff93f8b
YP		 994{
995 int err = 0;
996 int change = 0;
997 int port;
998
999 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 1000 /* Change the port type only if the new type is different
1001 * from the current, and not set to Auto */
3d8f9308 1002 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 1003 change = 1;
7ff93f8b
YP		 1004 }
1005 if (change) {
1006 mlx4_unregister_device(dev);
1007 for (port = 1; port <= dev->caps.num_ports; port++) {
1008 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 1009 dev->caps.port_type[port] = port_types[port - 1];
6634961c 1010 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 1011 if (err) {
1a91de28
JP		 1012 mlx4_err(dev, "Failed to set port %d, aborting\n",
1013 port);
7ff93f8b
YP		 1014 goto out;
1015 }
1016 }
1017 mlx4_set_port_mask(dev);
1018 err = mlx4_register_device(dev);
b046ffe5
EP		 1019 if (err) {
1020 mlx4_err(dev, "Failed to register device\n");
1021 goto out;
1022 }
1023 mlx4_request_modules(dev);
7ff93f8b
YP		 1024 }
1025
1026out:
1027 return err;
1028}
1029
1030static ssize_t show_port_type(struct device *dev,
1031 struct device_attribute *attr,
1032 char *buf)
1033{
1034 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1035 port_attr);
1036 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 1037 char type[8];
1038
1039 sprintf(type, "%s",
1040 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1041 "ib" : "eth");
1042 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1043 sprintf(buf, "auto (%s)\n", type);
1044 else
1045 sprintf(buf, "%s\n", type);
7ff93f8b 1046
27bf91d6 1047 return strlen(buf);
7ff93f8b
YP		 1048}
1049
1050static ssize_t set_port_type(struct device *dev,
1051 struct device_attribute *attr,
1052 const char *buf, size_t count)
1053{
1054 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1055 port_attr);
1056 struct mlx4_dev *mdev = info->dev;
1057 struct mlx4_priv *priv = mlx4_priv(mdev);
1058 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 1059 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
0a984556 1060 static DEFINE_MUTEX(set_port_type_mutex);
7ff93f8b
YP		 1061 int i;
1062 int err = 0;
1063
0a984556
AV		 1064 mutex_lock(&set_port_type_mutex);
1065
7ff93f8b
YP		 1066 if (!strcmp(buf, "ib\n"))
1067 info->tmp_type = MLX4_PORT_TYPE_IB;
1068 else if (!strcmp(buf, "eth\n"))
1069 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 1070 else if (!strcmp(buf, "auto\n"))
1071 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 1072 else {
1073 mlx4_err(mdev, "%s is not supported port type\n", buf);
0a984556
AV		 1074 err = -EINVAL;
1075 goto err_out;
7ff93f8b
YP		 1076 }
1077
27bf91d6 1078 mlx4_stop_sense(mdev);
7ff93f8b 1079 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 1080 /* Possible type is always the one that was delivered */
1081 mdev->caps.possible_type[info->port] = info->tmp_type;
1082
1083 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 1084 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 1085 mdev->caps.possible_type[i+1];
1086 if (types[i] == MLX4_PORT_TYPE_AUTO)
1087 types[i] = mdev->caps.port_type[i+1];
1088 }
7ff93f8b 1089
58a60168
YP		 1090 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1091 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1092 for (i = 1; i <= mdev->caps.num_ports; i++) {
1093 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1094 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1095 err = -EINVAL;
1096 }
1097 }
1098 }
1099 if (err) {
1a91de28 1100 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1101 goto out;
1102 }
1103
1104 mlx4_do_sense_ports(mdev, new_types, types);
1105
1106 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1107 if (err)
1108 goto out;
1109
27bf91d6
YP		 1110 /* We are about to apply the changes after the configuration
1111 * was verified, no need to remember the temporary types
1112 * any more */
1113 for (i = 0; i < mdev->caps.num_ports; i++)
1114 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1115
27bf91d6 1116 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1117
1118out:
27bf91d6 1119 mlx4_start_sense(mdev);
7ff93f8b 1120 mutex_unlock(&priv->port_mutex);
0a984556
AV		 1121err_out:
1122 mutex_unlock(&set_port_type_mutex);
1123
7ff93f8b
YP		 1124 return err ? err : count;
1125}
1126
096335b3
OG		 1127enum ibta_mtu {
1128 IB_MTU_256 = 1,
1129 IB_MTU_512 = 2,
1130 IB_MTU_1024 = 3,
1131 IB_MTU_2048 = 4,
1132 IB_MTU_4096 = 5
1133};
1134
1135static inline int int_to_ibta_mtu(int mtu)
1136{
1137 switch (mtu) {
1138 case 256: return IB_MTU_256;
1139 case 512: return IB_MTU_512;
1140 case 1024: return IB_MTU_1024;
1141 case 2048: return IB_MTU_2048;
1142 case 4096: return IB_MTU_4096;
1143 default: return -1;
1144 }
1145}
1146
1147static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1148{
1149 switch (mtu) {
1150 case IB_MTU_256: return 256;
1151 case IB_MTU_512: return 512;
1152 case IB_MTU_1024: return 1024;
1153 case IB_MTU_2048: return 2048;
1154 case IB_MTU_4096: return 4096;
1155 default: return -1;
1156 }
1157}
1158
1159static ssize_t show_port_ib_mtu(struct device *dev,
1160 struct device_attribute *attr,
1161 char *buf)
1162{
1163 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1164 port_mtu_attr);
1165 struct mlx4_dev *mdev = info->dev;
1166
1167 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1168 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1169
1170 sprintf(buf, "%d\n",
1171 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1172 return strlen(buf);
1173}
1174
1175static ssize_t set_port_ib_mtu(struct device *dev,
1176 struct device_attribute *attr,
1177 const char *buf, size_t count)
1178{
1179 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1180 port_mtu_attr);
1181 struct mlx4_dev *mdev = info->dev;
1182 struct mlx4_priv *priv = mlx4_priv(mdev);
1183 int err, port, mtu, ibta_mtu = -1;
1184
1185 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1186 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1187 return -EINVAL;
1188 }
1189
618fad95
DB		 1190 err = kstrtoint(buf, 0, &mtu);
1191 if (!err)
096335b3
OG		 1192 ibta_mtu = int_to_ibta_mtu(mtu);
1193
618fad95 1194 if (err || ibta_mtu < 0) {
096335b3
OG		 1195 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1196 return -EINVAL;
1197 }
1198
1199 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1200
1201 mlx4_stop_sense(mdev);
1202 mutex_lock(&priv->port_mutex);
1203 mlx4_unregister_device(mdev);
1204 for (port = 1; port <= mdev->caps.num_ports; port++) {
1205 mlx4_CLOSE_PORT(mdev, port);
6634961c 1206 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1207 if (err) {
1a91de28
JP		 1208 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1209 port);
096335b3
OG		 1210 goto err_set_port;
1211 }
1212 }
1213 err = mlx4_register_device(mdev);
1214err_set_port:
1215 mutex_unlock(&priv->port_mutex);
1216 mlx4_start_sense(mdev);
1217 return err ? err : count;
1218}
1219
53f33ae2
MS		 1220int mlx4_bond(struct mlx4_dev *dev)
1221{
1222 int ret = 0;
1223 struct mlx4_priv *priv = mlx4_priv(dev);
1224
1225 mutex_lock(&priv->bond_mutex);
1226
1227 if (!mlx4_is_bonded(dev))
1228 ret = mlx4_do_bond(dev, true);
1229 else
1230 ret = 0;
1231
1232 mutex_unlock(&priv->bond_mutex);
1233 if (ret)
1234 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1235 else
1236 mlx4_dbg(dev, "Device is bonded\n");
1237 return ret;
1238}
1239EXPORT_SYMBOL_GPL(mlx4_bond);
1240
1241int mlx4_unbond(struct mlx4_dev *dev)
1242{
1243 int ret = 0;
1244 struct mlx4_priv *priv = mlx4_priv(dev);
1245
1246 mutex_lock(&priv->bond_mutex);
1247
1248 if (mlx4_is_bonded(dev))
1249 ret = mlx4_do_bond(dev, false);
1250
1251 mutex_unlock(&priv->bond_mutex);
1252 if (ret)
1253 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1254 else
1255 mlx4_dbg(dev, "Device is unbonded\n");
1256 return ret;
1257}
1258EXPORT_SYMBOL_GPL(mlx4_unbond);
1259
1260
1261int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1262{
1263 u8 port1 = v2p->port1;
1264 u8 port2 = v2p->port2;
1265 struct mlx4_priv *priv = mlx4_priv(dev);
1266 int err;
1267
1268 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1269 return -ENOTSUPP;
1270
1271 mutex_lock(&priv->bond_mutex);
1272
1273 /* zero means keep current mapping for this port */
1274 if (port1 == 0)
1275 port1 = priv->v2p.port1;
1276 if (port2 == 0)
1277 port2 = priv->v2p.port2;
1278
1279 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1280 (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1281 (port1 == 2 && port2 == 1)) {
1282 /* besides boundary checks cross mapping makes
1283 * no sense and therefore not allowed */
1284 err = -EINVAL;
1285 } else if ((port1 == priv->v2p.port1) &&
1286 (port2 == priv->v2p.port2)) {
1287 err = 0;
1288 } else {
1289 err = mlx4_virt2phy_port_map(dev, port1, port2);
1290 if (!err) {
1291 mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1292 port1, port2);
1293 priv->v2p.port1 = port1;
1294 priv->v2p.port2 = port2;
1295 } else {
1296 mlx4_err(dev, "Failed to change port mape: %d\n", err);
1297 }
1298 }
1299
1300 mutex_unlock(&priv->bond_mutex);
1301 return err;
1302}
1303EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1304
e8f9b2ed 1305static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1306{
1307 struct mlx4_priv *priv = mlx4_priv(dev);
1308 int err;
1309
1310 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1311 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1312 if (!priv->fw.fw_icm) {
1a91de28 1313 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1314 return -ENOMEM;
1315 }
1316
1317 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1318 if (err) {
1a91de28 1319 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1320 goto err_free;
1321 }
1322
1323 err = mlx4_RUN_FW(dev);
1324 if (err) {
1a91de28 1325 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1326 goto err_unmap_fa;
1327 }
1328
1329 return 0;
1330
1331err_unmap_fa:
1332 mlx4_UNMAP_FA(dev);
1333
1334err_free:
5b0bf5e2 1335 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1336 return err;
1337}
1338
e8f9b2ed
RD		 1339static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1340 int cmpt_entry_sz)
225c7b1f
RD		 1341{
1342 struct mlx4_priv *priv = mlx4_priv(dev);
1343 int err;
ab9c17a0 1344 int num_eqs;
225c7b1f
RD		 1345
1346 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1347 cmpt_base +
1348 ((u64) (MLX4_CMPT_TYPE_QP *
1349 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1350 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1351 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1352 0, 0);
225c7b1f
RD		 1353 if (err)
1354 goto err;
1355
1356 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1357 cmpt_base +
1358 ((u64) (MLX4_CMPT_TYPE_SRQ *
1359 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1360 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1361 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1362 if (err)
1363 goto err_qp;
1364
1365 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1366 cmpt_base +
1367 ((u64) (MLX4_CMPT_TYPE_CQ *
1368 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1369 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1370 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1371 if (err)
1372 goto err_srq;
1373
7ae0e400 1374 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1375 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1376 cmpt_base +
1377 ((u64) (MLX4_CMPT_TYPE_EQ *
1378 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1379 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1380 if (err)
1381 goto err_cq;
1382
1383 return 0;
1384
1385err_cq:
1386 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1387
1388err_srq:
1389 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1390
1391err_qp:
1392 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1393
1394err:
1395 return err;
1396}
1397
3d73c288
RD		 1398static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1399 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1400{
1401 struct mlx4_priv *priv = mlx4_priv(dev);
1402 u64 aux_pages;
ab9c17a0 1403 int num_eqs;
225c7b1f
RD		 1404 int err;
1405
1406 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1407 if (err) {
1a91de28 1408 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1409 return err;
1410 }
1411
1a91de28 1412 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1413 (unsigned long long) icm_size >> 10,
1414 (unsigned long long) aux_pages << 2);
1415
1416 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1417 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1418 if (!priv->fw.aux_icm) {
1a91de28 1419 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1420 return -ENOMEM;
1421 }
1422
1423 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1424 if (err) {
1a91de28 1425 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1426 goto err_free_aux;
1427 }
1428
1429 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1430 if (err) {
1a91de28 1431 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1432 goto err_unmap_aux;
1433 }
1434
ab9c17a0 1435
7ae0e400 1436 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1437 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1438 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1439 num_eqs, num_eqs, 0, 0);
225c7b1f 1440 if (err) {
1a91de28 1441 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1442 goto err_unmap_cmpt;
1443 }
1444
d7bb58fb
JM		 1445 /*
1446 * Reserved MTT entries must be aligned up to a cacheline
1447 * boundary, since the FW will write to them, while the driver
1448 * writes to all other MTT entries. (The variable
1449 * dev->caps.mtt_entry_sz below is really the MTT segment
1450 * size, not the raw entry size)
1451 */
1452 dev->caps.reserved_mtts =
1453 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1454 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1455
225c7b1f
RD		 1456 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1457 init_hca->mtt_base,
1458 dev->caps.mtt_entry_sz,
2b8fb286 1459 dev->caps.num_mtts,
5b0bf5e2 1460 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1461 if (err) {
1a91de28 1462 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1463 goto err_unmap_eq;
1464 }
1465
1466 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1467 init_hca->dmpt_base,
1468 dev_cap->dmpt_entry_sz,
1469 dev->caps.num_mpts,
5b0bf5e2 1470 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1471 if (err) {
1a91de28 1472 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1473 goto err_unmap_mtt;
1474 }
1475
1476 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1477 init_hca->qpc_base,
1478 dev_cap->qpc_entry_sz,
1479 dev->caps.num_qps,
93fc9e1b
YP		 1480 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1481 0, 0);
225c7b1f 1482 if (err) {
1a91de28 1483 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1484 goto err_unmap_dmpt;
1485 }
1486
1487 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1488 init_hca->auxc_base,
1489 dev_cap->aux_entry_sz,
1490 dev->caps.num_qps,
93fc9e1b
YP		 1491 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1492 0, 0);
225c7b1f 1493 if (err) {
1a91de28 1494 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1495 goto err_unmap_qp;
1496 }
1497
1498 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1499 init_hca->altc_base,
1500 dev_cap->altc_entry_sz,
1501 dev->caps.num_qps,
93fc9e1b
YP		 1502 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1503 0, 0);
225c7b1f 1504 if (err) {
1a91de28 1505 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1506 goto err_unmap_auxc;
1507 }
1508
1509 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1510 init_hca->rdmarc_base,
1511 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1512 dev->caps.num_qps,
93fc9e1b
YP		 1513 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1514 0, 0);
225c7b1f
RD		 1515 if (err) {
1516 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1517 goto err_unmap_altc;
1518 }
1519
1520 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1521 init_hca->cqc_base,
1522 dev_cap->cqc_entry_sz,
1523 dev->caps.num_cqs,
5b0bf5e2 1524 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1525 if (err) {
1a91de28 1526 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1527 goto err_unmap_rdmarc;
1528 }
1529
1530 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1531 init_hca->srqc_base,
1532 dev_cap->srq_entry_sz,
1533 dev->caps.num_srqs,
5b0bf5e2 1534 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1535 if (err) {
1a91de28 1536 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1537 goto err_unmap_cq;
1538 }
1539
1540 /*
0ff1fb65
HHZ		 1541 * For flow steering device managed mode it is required to use
1542 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1543 * required, but for simplicity just map the whole multicast
1544 * group table now. The table isn't very big and it's a lot
1545 * easier than trying to track ref counts.
225c7b1f
RD		 1546 */
1547 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1548 init_hca->mc_base,
1549 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1550 dev->caps.num_mgms + dev->caps.num_amgms,
1551 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1552 0, 0);
225c7b1f 1553 if (err) {
1a91de28 1554 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1555 goto err_unmap_srq;
1556 }
1557
1558 return 0;
1559
1560err_unmap_srq:
1561 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1562
1563err_unmap_cq:
1564 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1565
1566err_unmap_rdmarc:
1567 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1568
1569err_unmap_altc:
1570 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1571
1572err_unmap_auxc:
1573 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1574
1575err_unmap_qp:
1576 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1577
1578err_unmap_dmpt:
1579 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1580
1581err_unmap_mtt:
1582 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1583
1584err_unmap_eq:
fa0681d2 1585 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1586
1587err_unmap_cmpt:
1588 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1589 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1590 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1591 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1592
1593err_unmap_aux:
1594 mlx4_UNMAP_ICM_AUX(dev);
1595
1596err_free_aux:
5b0bf5e2 1597 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1598
1599 return err;
1600}
1601
1602static void mlx4_free_icms(struct mlx4_dev *dev)
1603{
1604 struct mlx4_priv *priv = mlx4_priv(dev);
1605
1606 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1607 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1608 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1609 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1610 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1611 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1612 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1613 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1614 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1615 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1616 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1617 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1618 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1619 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1620
1621 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1622 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1623}
1624
ab9c17a0
JM		 1625static void mlx4_slave_exit(struct mlx4_dev *dev)
1626{
1627 struct mlx4_priv *priv = mlx4_priv(dev);
1628
f3d4c89e 1629 mutex_lock(&priv->cmd.slave_cmd_mutex);
0cd93027
YH		 1630 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1631 MLX4_COMM_TIME))
1a91de28 1632 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1633 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1634}
1635
c1b43dca
EC		 1636static int map_bf_area(struct mlx4_dev *dev)
1637{
1638 struct mlx4_priv *priv = mlx4_priv(dev);
1639 resource_size_t bf_start;
1640 resource_size_t bf_len;
1641 int err = 0;
1642
3d747473
JM		 1643 if (!dev->caps.bf_reg_size)
1644 return -ENXIO;
1645
872bf2fb 1646 bf_start = pci_resource_start(dev->persist->pdev, 2) +
ab9c17a0 1647 (dev->caps.num_uars << PAGE_SHIFT);
872bf2fb 1648 bf_len = pci_resource_len(dev->persist->pdev, 2) -
ab9c17a0 1649 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1650 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1651 if (!priv->bf_mapping)
1652 err = -ENOMEM;
1653
1654 return err;
1655}
1656
1657static void unmap_bf_area(struct mlx4_dev *dev)
1658{
1659 if (mlx4_priv(dev)->bf_mapping)
1660 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1661}
1662
ec693d47
AV		 1663cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1664{
1665 u32 clockhi, clocklo, clockhi1;
1666 cycle_t cycles;
1667 int i;
1668 struct mlx4_priv *priv = mlx4_priv(dev);
1669
1670 for (i = 0; i < 10; i++) {
1671 clockhi = swab32(readl(priv->clock_mapping));
1672 clocklo = swab32(readl(priv->clock_mapping + 4));
1673 clockhi1 = swab32(readl(priv->clock_mapping));
1674 if (clockhi == clockhi1)
1675 break;
1676 }
1677
1678 cycles = (u64) clockhi << 32 | (u64) clocklo;
1679
1680 return cycles;
1681}
1682EXPORT_SYMBOL_GPL(mlx4_read_clock);
1683
1684
ddd8a6c1
EE		 1685static int map_internal_clock(struct mlx4_dev *dev)
1686{
1687 struct mlx4_priv *priv = mlx4_priv(dev);
1688
1689 priv->clock_mapping =
872bf2fb
YH		 1690 ioremap(pci_resource_start(dev->persist->pdev,
1691 priv->fw.clock_bar) +
ddd8a6c1
EE		 1692 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1693
1694 if (!priv->clock_mapping)
1695 return -ENOMEM;
1696
1697 return 0;
1698}
1699
52033cfb
MB		 1700int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1701 struct mlx4_clock_params *params)
1702{
1703 struct mlx4_priv *priv = mlx4_priv(dev);
1704
1705 if (mlx4_is_slave(dev))
1706 return -ENOTSUPP;
1707
1708 if (!params)
1709 return -EINVAL;
1710
1711 params->bar = priv->fw.clock_bar;
1712 params->offset = priv->fw.clock_offset;
1713 params->size = MLX4_CLOCK_SIZE;
1714
1715 return 0;
1716}
1717EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1718
ddd8a6c1
EE		 1719static void unmap_internal_clock(struct mlx4_dev *dev)
1720{
1721 struct mlx4_priv *priv = mlx4_priv(dev);
1722
1723 if (priv->clock_mapping)
1724 iounmap(priv->clock_mapping);
1725}
1726
225c7b1f
RD		 1727static void mlx4_close_hca(struct mlx4_dev *dev)
1728{
ddd8a6c1 1729 unmap_internal_clock(dev);
c1b43dca 1730 unmap_bf_area(dev);
ab9c17a0
JM		 1731 if (mlx4_is_slave(dev))
1732 mlx4_slave_exit(dev);
1733 else {
1734 mlx4_CLOSE_HCA(dev, 0);
1735 mlx4_free_icms(dev);
a0eacca9
MB		 1736 }
1737}
1738
1739static void mlx4_close_fw(struct mlx4_dev *dev)
1740{
1741 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1742 mlx4_UNMAP_FA(dev);
1743 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1744 }
1745}
1746
55ad3592
YH		 1747static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1748{
1749#define COMM_CHAN_OFFLINE_OFFSET 0x09
1750
1751 u32 comm_flags;
1752 u32 offline_bit;
1753 unsigned long end;
1754 struct mlx4_priv *priv = mlx4_priv(dev);
1755
1756 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1757 while (time_before(jiffies, end)) {
1758 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1759 MLX4_COMM_CHAN_FLAGS));
1760 offline_bit = (comm_flags &
1761 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1762 if (!offline_bit)
1763 return 0;
1764 /* There are cases as part of AER/Reset flow that PF needs
1765 * around 100 msec to load. We therefore sleep for 100 msec
1766 * to allow other tasks to make use of that CPU during this
1767 * time interval.
1768 */
1769 msleep(100);
1770 }
1771 mlx4_err(dev, "Communication channel is offline.\n");
1772 return -EIO;
1773}
1774
1775static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1776{
1777#define COMM_CHAN_RST_OFFSET 0x1e
1778
1779 struct mlx4_priv *priv = mlx4_priv(dev);
1780 u32 comm_rst;
1781 u32 comm_caps;
1782
1783 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1784 MLX4_COMM_CHAN_CAPS));
1785 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1786
1787 if (comm_rst)
1788 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1789}
1790
ab9c17a0
JM		 1791static int mlx4_init_slave(struct mlx4_dev *dev)
1792{
1793 struct mlx4_priv *priv = mlx4_priv(dev);
1794 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1795 int ret_from_reset = 0;
1796 u32 slave_read;
1797 u32 cmd_channel_ver;
1798
97989356 1799 if (atomic_read(&pf_loading)) {
1a91de28 1800 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 1801 return -EPROBE_DEFER;
1802 }
1803
f3d4c89e 1804 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1805 priv->cmd.max_cmds = 1;
55ad3592
YH		 1806 if (mlx4_comm_check_offline(dev)) {
1807 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1808 goto err_offline;
1809 }
1810
1811 mlx4_reset_vf_support(dev);
ab9c17a0
JM		 1812 mlx4_warn(dev, "Sending reset\n");
1813 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
0cd93027 1814 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
ab9c17a0
JM		 1815 /* if we are in the middle of flr the slave will try
1816 * NUM_OF_RESET_RETRIES times before leaving.*/
1817 if (ret_from_reset) {
1818 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 1819 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 1820 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1821 return -EPROBE_DEFER;
ab9c17a0
JM		 1822 } else
1823 goto err;
1824 }
1825
1826 /* check the driver version - the slave I/F revision
1827 * must match the master's */
1828 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1829 cmd_channel_ver = mlx4_comm_get_version();
1830
1831 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1832 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 1833 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 1834 goto err;
1835 }
1836
1837 mlx4_warn(dev, "Sending vhcr0\n");
1838 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
0cd93027 1839 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 1840 goto err;
1841 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
0cd93027 1842 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 1843 goto err;
1844 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
0cd93027 1845 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 1846 goto err;
0cd93027
YH		 1847 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1848 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 1849 goto err;
f3d4c89e
RD		 1850
1851 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1852 return 0;
1853
1854err:
0cd93027 1855 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
55ad3592 1856err_offline:
f3d4c89e 1857 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1858 return -EIO;
225c7b1f
RD		 1859}
1860
6634961c
JM		 1861static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1862{
1863 int i;
1864
1865 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1866 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1867 dev->caps.gid_table_len[i] =
449fc488 1868 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1869 else
1870 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1871 dev->caps.pkey_table_len[i] =
1872 dev->phys_caps.pkey_phys_table_len[i] - 1;
1873 }
1874}
1875
3c439b55
JM		 1876static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1877{
1878 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1879
1880 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1881 i++) {
1882 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1883 break;
1884 }
1885
1886 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1887}
1888
7d077cd3
MB		 1889static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
1890{
1891 switch (dmfs_high_steer_mode) {
1892 case MLX4_STEERING_DMFS_A0_DEFAULT:
1893 return "default performance";
1894
1895 case MLX4_STEERING_DMFS_A0_DYNAMIC:
1896 return "dynamic hybrid mode";
1897
1898 case MLX4_STEERING_DMFS_A0_STATIC:
1899 return "performance optimized for limited rule configuration (static)";
1900
1901 case MLX4_STEERING_DMFS_A0_DISABLE:
1902 return "disabled performance optimized steering";
1903
1904 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
1905 return "performance optimized steering not supported";
1906
1907 default:
1908 return "Unrecognized mode";
1909 }
1910}
1911
1912#define MLX4_DMFS_A0_STEERING (1UL << 2)
1913
7b8157be
JM		 1914static void choose_steering_mode(struct mlx4_dev *dev,
1915 struct mlx4_dev_cap *dev_cap)
1916{
7d077cd3
MB		 1917 if (mlx4_log_num_mgm_entry_size <= 0) {
1918 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
1919 if (dev->caps.dmfs_high_steer_mode ==
1920 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1921 mlx4_err(dev, "DMFS high rate mode not supported\n");
1922 else
1923 dev->caps.dmfs_high_steer_mode =
1924 MLX4_STEERING_DMFS_A0_STATIC;
1925 }
1926 }
1927
1928 if (mlx4_log_num_mgm_entry_size <= 0 &&
3c439b55 1929 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1930 (!mlx4_is_mfunc(dev) ||
872bf2fb
YH		 1931 (dev_cap->fs_max_num_qp_per_entry >=
1932 (dev->persist->num_vfs + 1))) &&
3c439b55
JM		 1933 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1934 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1935 dev->oper_log_mgm_entry_size =
1936 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1937 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1938 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1939 dev->caps.fs_log_max_ucast_qp_range_size =
1940 dev_cap->fs_log_max_ucast_qp_range_size;
1941 } else {
7d077cd3
MB		 1942 if (dev->caps.dmfs_high_steer_mode !=
1943 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1944 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
7b8157be
JM		 1945 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1946 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1947 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1948 else {
1949 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1950
1951 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1952 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 1953 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 1954 }
3c439b55
JM		 1955 dev->oper_log_mgm_entry_size =
1956 mlx4_log_num_mgm_entry_size > 0 ?
1957 mlx4_log_num_mgm_entry_size :
1958 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1959 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1960 }
1a91de28 1961 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 1962 mlx4_steering_mode_str(dev->caps.steering_mode),
1963 dev->oper_log_mgm_entry_size,
1964 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1965}
1966
7ffdf726
OG		 1967static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1968 struct mlx4_dev_cap *dev_cap)
1969{
1970 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
5eff6dad 1971 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
7ffdf726
OG		 1972 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1973 else
1974 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1975
1976 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1977 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1978}
1979
7d077cd3
MB		 1980static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
1981{
1982 int i;
1983 struct mlx4_port_cap port_cap;
1984
1985 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1986 return -EINVAL;
1987
1988 for (i = 1; i <= dev->caps.num_ports; i++) {
1989 if (mlx4_dev_port(dev, i, &port_cap)) {
1990 mlx4_err(dev,
1991 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
1992 } else if ((dev->caps.dmfs_high_steer_mode !=
1993 MLX4_STEERING_DMFS_A0_DEFAULT) &&
1994 (port_cap.dmfs_optimized_state ==
1995 !!(dev->caps.dmfs_high_steer_mode ==
1996 MLX4_STEERING_DMFS_A0_DISABLE))) {
1997 mlx4_err(dev,
1998 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
1999 dmfs_high_rate_steering_mode_str(
2000 dev->caps.dmfs_high_steer_mode),
2001 (port_cap.dmfs_optimized_state ?
2002 "enabled" : "disabled"));
2003 }
2004 }
2005
2006 return 0;
2007}
2008
a0eacca9 2009static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 2010{
2d928651 2011 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 2012 int err = 0;
225c7b1f 2013
ab9c17a0
JM		 2014 if (!mlx4_is_slave(dev)) {
2015 err = mlx4_QUERY_FW(dev);
2016 if (err) {
2017 if (err == -EACCES)
1a91de28 2018 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 2019 else
1a91de28 2020 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 2021 return err;
ab9c17a0 2022 }
225c7b1f 2023
ab9c17a0
JM		 2024 err = mlx4_load_fw(dev);
2025 if (err) {
1a91de28 2026 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 2027 return err;
ab9c17a0 2028 }
225c7b1f 2029
ab9c17a0
JM		 2030 mlx4_cfg.log_pg_sz_m = 1;
2031 mlx4_cfg.log_pg_sz = 0;
2032 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2033 if (err)
2034 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 2035 }
2d928651 2036
a0eacca9
MB		 2037 return err;
2038}
2039
2040static int mlx4_init_hca(struct mlx4_dev *dev)
2041{
2042 struct mlx4_priv *priv = mlx4_priv(dev);
2043 struct mlx4_adapter adapter;
2044 struct mlx4_dev_cap dev_cap;
2045 struct mlx4_profile profile;
2046 struct mlx4_init_hca_param init_hca;
2047 u64 icm_size;
2048 struct mlx4_config_dev_params params;
2049 int err;
2050
2051 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2052 err = mlx4_dev_cap(dev, &dev_cap);
2053 if (err) {
1a91de28 2054 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
d0d01250 2055 return err;
ab9c17a0 2056 }
225c7b1f 2057
7b8157be 2058 choose_steering_mode(dev, &dev_cap);
7ffdf726 2059 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 2060
7d077cd3
MB		 2061 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2062 mlx4_is_master(dev))
2063 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2064
8e1a28e8
HHZ		 2065 err = mlx4_get_phys_port_id(dev);
2066 if (err)
2067 mlx4_err(dev, "Fail to get physical port id\n");
2068
6634961c
JM		 2069 if (mlx4_is_master(dev))
2070 mlx4_parav_master_pf_caps(dev);
2071
2599d858
AV		 2072 if (mlx4_low_memory_profile()) {
2073 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2074 profile = low_mem_profile;
2075 } else {
2076 profile = default_profile;
2077 }
0ff1fb65
HHZ		 2078 if (dev->caps.steering_mode ==
2079 MLX4_STEERING_MODE_DEVICE_MANAGED)
2080 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 2081
ab9c17a0
JM		 2082 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2083 &init_hca);
2084 if ((long long) icm_size < 0) {
2085 err = icm_size;
d0d01250 2086 return err;
ab9c17a0 2087 }
225c7b1f 2088
a5bbe892
EC		 2089 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2090
ab9c17a0
JM		 2091 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2092 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 2093 init_hca.mw_enabled = 0;
2094 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2095 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2096 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 2097
ab9c17a0
JM		 2098 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2099 if (err)
d0d01250 2100 return err;
225c7b1f 2101
ab9c17a0
JM		 2102 err = mlx4_INIT_HCA(dev, &init_hca);
2103 if (err) {
1a91de28 2104 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 2105 goto err_free_icm;
2106 }
7ae0e400
MB		 2107
2108 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2109 err = mlx4_query_func(dev, &dev_cap);
2110 if (err < 0) {
2111 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
d0d01250 2112 goto err_close;
7ae0e400
MB		 2113 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2114 dev->caps.num_eqs = dev_cap.max_eqs;
2115 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2116 dev->caps.reserved_uars = dev_cap.reserved_uars;
2117 }
2118 }
2119
ddd8a6c1
EE		 2120 /*
2121 * If TS is supported by FW
2122 * read HCA frequency by QUERY_HCA command
2123 */
2124 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2125 memset(&init_hca, 0, sizeof(init_hca));
2126 err = mlx4_QUERY_HCA(dev, &init_hca);
2127 if (err) {
1a91de28 2128 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 2129 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2130 } else {
2131 dev->caps.hca_core_clock =
2132 init_hca.hca_core_clock;
2133 }
2134
2135 /* In case we got HCA frequency 0 - disable timestamping
2136 * to avoid dividing by zero
2137 */
2138 if (!dev->caps.hca_core_clock) {
2139 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2140 mlx4_err(dev,
1a91de28 2141 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 2142 } else if (map_internal_clock(dev)) {
2143 /*
2144 * Map internal clock,
2145 * in case of failure disable timestamping
2146 */
2147 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 2148 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 2149 }
2150 }
7d077cd3
MB		 2151
2152 if (dev->caps.dmfs_high_steer_mode !=
2153 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2154 if (mlx4_validate_optimized_steering(dev))
2155 mlx4_warn(dev, "Optimized steering validation failed\n");
2156
2157 if (dev->caps.dmfs_high_steer_mode ==
2158 MLX4_STEERING_DMFS_A0_DISABLE) {
2159 dev->caps.dmfs_high_rate_qpn_base =
2160 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2161 dev->caps.dmfs_high_rate_qpn_range =
2162 MLX4_A0_STEERING_TABLE_SIZE;
2163 }
2164
2165 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2166 dmfs_high_rate_steering_mode_str(
2167 dev->caps.dmfs_high_steer_mode));
2168 }
ab9c17a0
JM		 2169 } else {
2170 err = mlx4_init_slave(dev);
2171 if (err) {
5efe5355
JM		 2172 if (err != -EPROBE_DEFER)
2173 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 2174 return err;
ab9c17a0 2175 }
225c7b1f 2176
ab9c17a0
JM		 2177 err = mlx4_slave_cap(dev);
2178 if (err) {
2179 mlx4_err(dev, "Failed to obtain slave caps\n");
2180 goto err_close;
2181 }
225c7b1f
RD		 2182 }
2183
ab9c17a0
JM		 2184 if (map_bf_area(dev))
2185 mlx4_dbg(dev, "Failed to map blue flame area\n");
2186
2187 /*Only the master set the ports, all the rest got it from it.*/
2188 if (!mlx4_is_slave(dev))
2189 mlx4_set_port_mask(dev);
2190
225c7b1f
RD		 2191 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2192 if (err) {
1a91de28 2193 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 2194 goto unmap_bf;
225c7b1f
RD		 2195 }
2196
f8c6455b
SM		 2197 /* Query CONFIG_DEV parameters */
2198 err = mlx4_config_dev_retrieval(dev, &params);
2199 if (err && err != -ENOTSUPP) {
2200 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2201 } else if (!err) {
2202 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2203 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2204 }
225c7b1f 2205 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 2206 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 2207
2208 return 0;
2209
bef772eb 2210unmap_bf:
ddd8a6c1 2211 unmap_internal_clock(dev);
bef772eb
AY		 2212 unmap_bf_area(dev);
2213
b38f2879 2214 if (mlx4_is_slave(dev)) {
99ec41d0 2215 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2216 kfree(dev->caps.qp0_tunnel);
2217 kfree(dev->caps.qp0_proxy);
2218 kfree(dev->caps.qp1_tunnel);
2219 kfree(dev->caps.qp1_proxy);
2220 }
2221
225c7b1f 2222err_close:
41929ed2
DB		 2223 if (mlx4_is_slave(dev))
2224 mlx4_slave_exit(dev);
2225 else
2226 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 2227
2228err_free_icm:
ab9c17a0
JM		 2229 if (!mlx4_is_slave(dev))
2230 mlx4_free_icms(dev);
225c7b1f 2231
225c7b1f
RD		 2232 return err;
2233}
2234
f2a3f6a3
OG		 2235static int mlx4_init_counters_table(struct mlx4_dev *dev)
2236{
2237 struct mlx4_priv *priv = mlx4_priv(dev);
47d8417f 2238 int nent_pow2;
f2a3f6a3
OG		 2239
2240 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2241 return -ENOENT;
2242
2632d18d
EBE		 2243 if (!dev->caps.max_counters)
2244 return -ENOSPC;
2245
47d8417f
EBE		 2246 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2247 /* reserve last counter index for sink counter */
2248 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2249 nent_pow2 - 1, 0,
2250 nent_pow2 - dev->caps.max_counters + 1);
f2a3f6a3
OG		 2251}
2252
2253static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2254{
efa6bc91
EBE		 2255 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2256 return;
2257
2632d18d
EBE		 2258 if (!dev->caps.max_counters)
2259 return;
2260
f2a3f6a3
OG		 2261 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2262}
2263
6de5f7f6
EBE		 2264static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2265{
2266 struct mlx4_priv *priv = mlx4_priv(dev);
2267 int port;
2268
2269 for (port = 0; port < dev->caps.num_ports; port++)
2270 if (priv->def_counter[port] != -1)
2271 mlx4_counter_free(dev, priv->def_counter[port]);
2272}
2273
2274static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2275{
2276 struct mlx4_priv *priv = mlx4_priv(dev);
2277 int port, err = 0;
2278 u32 idx;
2279
2280 for (port = 0; port < dev->caps.num_ports; port++)
2281 priv->def_counter[port] = -1;
2282
2283 for (port = 0; port < dev->caps.num_ports; port++) {
2284 err = mlx4_counter_alloc(dev, &idx);
2285
2286 if (!err || err == -ENOSPC) {
2287 priv->def_counter[port] = idx;
2288 } else if (err == -ENOENT) {
2289 err = 0;
2290 continue;
178d23e3
OG		 2291 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2292 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2293 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2294 MLX4_SINK_COUNTER_INDEX(dev));
2295 err = 0;
6de5f7f6
EBE		 2296 } else {
2297 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2298 __func__, port + 1, err);
2299 mlx4_cleanup_default_counters(dev);
2300 return err;
2301 }
2302
2303 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2304 __func__, priv->def_counter[port], port + 1);
2305 }
2306
2307 return err;
2308}
2309
ba062d52 2310int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 2311{
2312 struct mlx4_priv *priv = mlx4_priv(dev);
2313
2314 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2315 return -ENOENT;
2316
2317 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
6de5f7f6
EBE		 2318 if (*idx == -1) {
2319 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2320 return -ENOSPC;
2321 }
f2a3f6a3
OG		 2322
2323 return 0;
2324}
ba062d52
JM		 2325
2326int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2327{
2328 u64 out_param;
2329 int err;
2330
2331 if (mlx4_is_mfunc(dev)) {
2332 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2333 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2334 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2335 if (!err)
2336 *idx = get_param_l(&out_param);
2337
2338 return err;
2339 }
2340 return __mlx4_counter_alloc(dev, idx);
2341}
f2a3f6a3
OG		 2342EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2343
b72ca7e9
EBE		 2344static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2345 u8 counter_index)
2346{
2347 struct mlx4_cmd_mailbox *if_stat_mailbox;
2348 int err;
2349 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2350
2351 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2352 if (IS_ERR(if_stat_mailbox))
2353 return PTR_ERR(if_stat_mailbox);
2354
2355 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2356 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2357 MLX4_CMD_NATIVE);
2358
2359 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2360 return err;
2361}
2362
ba062d52 2363void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 2364{
efa6bc91
EBE		 2365 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2366 return;
2367
6de5f7f6
EBE		 2368 if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2369 return;
2370
b72ca7e9
EBE		 2371 __mlx4_clear_if_stat(dev, idx);
2372
7c6d74d2 2373 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 2374 return;
2375}
ba062d52
JM		 2376
2377void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2378{
e7dbeba8 2379 u64 in_param = 0;
ba062d52
JM		 2380
2381 if (mlx4_is_mfunc(dev)) {
2382 set_param_l(&in_param, idx);
2383 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2384 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2385 MLX4_CMD_WRAPPED);
2386 return;
2387 }
2388 __mlx4_counter_free(dev, idx);
2389}
f2a3f6a3
OG		 2390EXPORT_SYMBOL_GPL(mlx4_counter_free);
2391
6de5f7f6
EBE		 2392int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2393{
2394 struct mlx4_priv *priv = mlx4_priv(dev);
2395
2396 return priv->def_counter[port - 1];
2397}
2398EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2399
773af94e
YH		 2400void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2401{
2402 struct mlx4_priv *priv = mlx4_priv(dev);
2403
2404 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2405}
2406EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2407
2408__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2409{
2410 struct mlx4_priv *priv = mlx4_priv(dev);
2411
2412 return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2413}
2414EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2415
fb517a4f
YH		 2416void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2417{
2418 struct mlx4_priv *priv = mlx4_priv(dev);
2419 __be64 guid;
2420
2421 /* hw GUID */
2422 if (entry == 0)
2423 return;
2424
2425 get_random_bytes((char *)&guid, sizeof(guid));
2426 guid &= ~(cpu_to_be64(1ULL << 56));
2427 guid |= cpu_to_be64(1ULL << 57);
2428 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2429}
2430
3d73c288 2431static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 2432{
2433 struct mlx4_priv *priv = mlx4_priv(dev);
2434 int err;
7ff93f8b 2435 int port;
9a5aa622 2436 __be32 ib_port_default_caps;
225c7b1f 2437
225c7b1f
RD		 2438 err = mlx4_init_uar_table(dev);
2439 if (err) {
1a91de28
JP		 2440 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2441 return err;
225c7b1f
RD		 2442 }
2443
2444 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2445 if (err) {
1a91de28 2446 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 2447 goto err_uar_table_free;
2448 }
2449
4979d18f 2450 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 2451 if (!priv->kar) {
1a91de28 2452 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 2453 err = -ENOMEM;
2454 goto err_uar_free;
2455 }
2456
2457 err = mlx4_init_pd_table(dev);
2458 if (err) {
1a91de28 2459 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2460 goto err_kar_unmap;
2461 }
2462
012a8ff5
SH		 2463 err = mlx4_init_xrcd_table(dev);
2464 if (err) {
1a91de28 2465 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2466 goto err_pd_table_free;
2467 }
2468
225c7b1f
RD		 2469 err = mlx4_init_mr_table(dev);
2470 if (err) {
1a91de28 2471 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2472 goto err_xrcd_table_free;
225c7b1f
RD		 2473 }
2474
fe6f700d
YP		 2475 if (!mlx4_is_slave(dev)) {
2476 err = mlx4_init_mcg_table(dev);
2477 if (err) {
1a91de28 2478 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2479 goto err_mr_table_free;
2480 }
114840c3
JM		 2481 err = mlx4_config_mad_demux(dev);
2482 if (err) {
2483 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2484 goto err_mcg_table_free;
2485 }
fe6f700d
YP		 2486 }
2487
225c7b1f
RD		 2488 err = mlx4_init_eq_table(dev);
2489 if (err) {
1a91de28 2490 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2491 goto err_mcg_table_free;
225c7b1f
RD		 2492 }
2493
2494 err = mlx4_cmd_use_events(dev);
2495 if (err) {
1a91de28 2496 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2497 goto err_eq_table_free;
2498 }
2499
2500 err = mlx4_NOP(dev);
2501 if (err) {
08fb1055 2502 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2503 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
c66fa19c 2504 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
1a91de28 2505 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2506 } else {
1a91de28 2507 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
c66fa19c 2508 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 2509 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2510 }
225c7b1f
RD		 2511
2512 goto err_cmd_poll;
2513 }
2514
2515 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2516
2517 err = mlx4_init_cq_table(dev);
2518 if (err) {
1a91de28 2519 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2520 goto err_cmd_poll;
2521 }
2522
2523 err = mlx4_init_srq_table(dev);
2524 if (err) {
1a91de28 2525 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2526 goto err_cq_table_free;
2527 }
2528
2529 err = mlx4_init_qp_table(dev);
2530 if (err) {
1a91de28 2531 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2532 goto err_srq_table_free;
2533 }
2534
2632d18d
EBE		 2535 if (!mlx4_is_slave(dev)) {
2536 err = mlx4_init_counters_table(dev);
2537 if (err && err != -ENOENT) {
2538 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2539 goto err_qp_table_free;
2540 }
f2a3f6a3
OG		 2541 }
2542
6de5f7f6
EBE		 2543 err = mlx4_allocate_default_counters(dev);
2544 if (err) {
2545 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2546 goto err_counters_table_free;
f2a3f6a3
OG		 2547 }
2548
ab9c17a0
JM		 2549 if (!mlx4_is_slave(dev)) {
2550 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2551 ib_port_default_caps = 0;
2552 err = mlx4_get_port_ib_caps(dev, port,
2553 &ib_port_default_caps);
2554 if (err)
1a91de28
JP		 2555 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2556 port, err);
ab9c17a0
JM		 2557 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2558
2aca1172
JM		 2559 /* initialize per-slave default ib port capabilities */
2560 if (mlx4_is_master(dev)) {
2561 int i;
2562 for (i = 0; i < dev->num_slaves; i++) {
2563 if (i == mlx4_master_func_num(dev))
2564 continue;
2565 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2566 ib_port_default_caps;
2aca1172
JM		 2567 }
2568 }
2569
096335b3
OG		 2570 if (mlx4_is_mfunc(dev))
2571 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2572 else
2573 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2574
6634961c
JM		 2575 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2576 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2577 if (err) {
2578 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2579 port);
6de5f7f6 2580 goto err_default_countes_free;
ab9c17a0 2581 }
7ff93f8b
YP		 2582 }
2583 }
2584
225c7b1f
RD		 2585 return 0;
2586
6de5f7f6
EBE		 2587err_default_countes_free:
2588 mlx4_cleanup_default_counters(dev);
2589
f2a3f6a3 2590err_counters_table_free:
2632d18d
EBE		 2591 if (!mlx4_is_slave(dev))
2592 mlx4_cleanup_counters_table(dev);
f2a3f6a3 2593
225c7b1f
RD		 2594err_qp_table_free:
2595 mlx4_cleanup_qp_table(dev);
2596
2597err_srq_table_free:
2598 mlx4_cleanup_srq_table(dev);
2599
2600err_cq_table_free:
2601 mlx4_cleanup_cq_table(dev);
2602
2603err_cmd_poll:
2604 mlx4_cmd_use_polling(dev);
2605
2606err_eq_table_free:
2607 mlx4_cleanup_eq_table(dev);
2608
fe6f700d
YP		 2609err_mcg_table_free:
2610 if (!mlx4_is_slave(dev))
2611 mlx4_cleanup_mcg_table(dev);
2612
ee49bd93 2613err_mr_table_free:
225c7b1f
RD		 2614 mlx4_cleanup_mr_table(dev);
2615
012a8ff5
SH		 2616err_xrcd_table_free:
2617 mlx4_cleanup_xrcd_table(dev);
2618
225c7b1f
RD		 2619err_pd_table_free:
2620 mlx4_cleanup_pd_table(dev);
2621
2622err_kar_unmap:
2623 iounmap(priv->kar);
2624
2625err_uar_free:
2626 mlx4_uar_free(dev, &priv->driver_uar);
2627
2628err_uar_table_free:
2629 mlx4_cleanup_uar_table(dev);
2630 return err;
2631}
2632
de161803
IS		 2633static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2634{
2635 int requested_cpu = 0;
2636 struct mlx4_priv *priv = mlx4_priv(dev);
2637 struct mlx4_eq *eq;
2638 int off = 0;
2639 int i;
2640
2641 if (eqn > dev->caps.num_comp_vectors)
2642 return -EINVAL;
2643
2644 for (i = 1; i < port; i++)
2645 off += mlx4_get_eqs_per_port(dev, i);
2646
2647 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2648
2649 /* Meaning EQs are shared, and this call comes from the second port */
2650 if (requested_cpu < 0)
2651 return 0;
2652
2653 eq = &priv->eq_table.eq[eqn];
2654
2655 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2656 return -ENOMEM;
2657
2658 cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2659
2660 return 0;
2661}
2662
e8f9b2ed 2663static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2664{
2665 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2666 struct msix_entry *entries;
225c7b1f 2667 int i;
c66fa19c 2668 int port = 0;
225c7b1f
RD		 2669
2670 if (msi_x) {
c66fa19c 2671 int nreq = dev->caps.num_ports * num_online_cpus() + 1;
9293267a 2672 bool shared_ports = false;
7ae0e400 2673
ca4c7b35
OG		 2674 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2675 nreq);
9293267a
CS		 2676 if (nreq > MAX_MSIX) {
2677 nreq = MAX_MSIX;
2678 shared_ports = true;
2679 }
ab9c17a0 2680
b8dd786f
YP		 2681 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2682 if (!entries)
2683 goto no_msi;
2684
2685 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2686 entries[i].entry = i;
2687
872bf2fb
YH		 2688 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2689 nreq);
66e2f9c1 2690
c66fa19c 2691 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
5bf0da7d 2692 kfree(entries);
225c7b1f 2693 goto no_msi;
0b7ca5a9 2694 }
c66fa19c
MB		 2695 /* 1 is reserved for events (asyncrounous EQ) */
2696 dev->caps.num_comp_vectors = nreq - 1;
2697
2698 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2699 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2700 dev->caps.num_ports);
2701
9293267a
CS		 2702 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps))
2703 shared_ports = true;
2704
c66fa19c
MB		 2705 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2706 if (i == MLX4_EQ_ASYNC)
2707 continue;
2708
2709 priv->eq_table.eq[i].irq =
2710 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2711
9293267a 2712 if (shared_ports) {
c66fa19c
MB		 2713 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2714 dev->caps.num_ports);
de161803
IS		 2715 /* We don't set affinity hint when there
2716 * aren't enough EQs
2717 */
c66fa19c
MB		 2718 } else {
2719 set_bit(port,
2720 priv->eq_table.eq[i].actv_ports.ports);
de161803
IS		 2721 if (mlx4_init_affinity_hint(dev, port + 1, i))
2722 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2723 i);
c66fa19c
MB		 2724 }
2725 /* We divide the Eqs evenly between the two ports.
2726 * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2727 * refers to the number of Eqs per port
2728 * (i.e eqs_per_port). Theoretically, we would like to
2729 * write something like (i + 1) % eqs_per_port == 0.
2730 * However, since there's an asynchronous Eq, we have
2731 * to skip over it by comparing this condition to
2732 * !!((i + 1) > MLX4_EQ_ASYNC).
2733 */
2734 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2735 ((i + 1) %
2736 (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2737 !!((i + 1) > MLX4_EQ_ASYNC))
2738 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2739 * everything is shared anyway.
2740 */
2741 port++;
2742 }
225c7b1f
RD		 2743
2744 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2745
2746 kfree(entries);
225c7b1f
RD		 2747 return;
2748 }
2749
2750no_msi:
b8dd786f
YP		 2751 dev->caps.num_comp_vectors = 1;
2752
c66fa19c
MB		 2753 BUG_ON(MLX4_EQ_ASYNC >= 2);
2754 for (i = 0; i < 2; ++i) {
872bf2fb 2755 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
c66fa19c
MB		 2756 if (i != MLX4_EQ_ASYNC) {
2757 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2758 dev->caps.num_ports);
2759 }
2760 }
225c7b1f
RD		 2761}
2762
7ff93f8b 2763static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2764{
2765 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2766 int err = 0;
2a2336f8
YP		 2767
2768 info->dev = dev;
2769 info->port = port;
ab9c17a0 2770 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2771 mlx4_init_mac_table(dev, &info->mac_table);
2772 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2773 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2774 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2775 }
7ff93f8b
YP		 2776
2777 sprintf(info->dev_name, "mlx4_port%d", port);
2778 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2779 if (mlx4_is_mfunc(dev))
2780 info->port_attr.attr.mode = S_IRUGO;
2781 else {
2782 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2783 info->port_attr.store = set_port_type;
2784 }
7ff93f8b 2785 info->port_attr.show = show_port_type;
3691c964 2786 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b 2787
872bf2fb 2788 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
7ff93f8b
YP		 2789 if (err) {
2790 mlx4_err(dev, "Failed to create file for port %d\n", port);
2791 info->port = -1;
2792 }
2793
096335b3
OG		 2794 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2795 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2796 if (mlx4_is_mfunc(dev))
2797 info->port_mtu_attr.attr.mode = S_IRUGO;
2798 else {
2799 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2800 info->port_mtu_attr.store = set_port_ib_mtu;
2801 }
2802 info->port_mtu_attr.show = show_port_ib_mtu;
2803 sysfs_attr_init(&info->port_mtu_attr.attr);
2804
872bf2fb
YH		 2805 err = device_create_file(&dev->persist->pdev->dev,
2806 &info->port_mtu_attr);
096335b3
OG		 2807 if (err) {
2808 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
872bf2fb
YH		 2809 device_remove_file(&info->dev->persist->pdev->dev,
2810 &info->port_attr);
096335b3
OG		 2811 info->port = -1;
2812 }
2813
7ff93f8b
YP		 2814 return err;
2815}
2816
2817static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2818{
2819 if (info->port < 0)
2820 return;
2821
872bf2fb
YH		 2822 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2823 device_remove_file(&info->dev->persist->pdev->dev,
2824 &info->port_mtu_attr);
c66fa19c
MB		 2825#ifdef CONFIG_RFS_ACCEL
2826 free_irq_cpu_rmap(info->rmap);
2827 info->rmap = NULL;
2828#endif
2a2336f8
YP		 2829}
2830
b12d93d6
YP		 2831static int mlx4_init_steering(struct mlx4_dev *dev)
2832{
2833 struct mlx4_priv *priv = mlx4_priv(dev);
2834 int num_entries = dev->caps.num_ports;
2835 int i, j;
2836
2837 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2838 if (!priv->steer)
2839 return -ENOMEM;
2840
45b51365 2841 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2842 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2843 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2844 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2845 }
b12d93d6
YP		 2846 return 0;
2847}
2848
2849static void mlx4_clear_steering(struct mlx4_dev *dev)
2850{
2851 struct mlx4_priv *priv = mlx4_priv(dev);
2852 struct mlx4_steer_index *entry, *tmp_entry;
2853 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2854 int num_entries = dev->caps.num_ports;
2855 int i, j;
2856
2857 for (i = 0; i < num_entries; i++) {
2858 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2859 list_for_each_entry_safe(pqp, tmp_pqp,
2860 &priv->steer[i].promisc_qps[j],
2861 list) {
2862 list_del(&pqp->list);
2863 kfree(pqp);
2864 }
2865 list_for_each_entry_safe(entry, tmp_entry,
2866 &priv->steer[i].steer_entries[j],
2867 list) {
2868 list_del(&entry->list);
2869 list_for_each_entry_safe(pqp, tmp_pqp,
2870 &entry->duplicates,
2871 list) {
2872 list_del(&pqp->list);
2873 kfree(pqp);
2874 }
2875 kfree(entry);
2876 }
2877 }
2878 }
2879 kfree(priv->steer);
2880}
2881
ab9c17a0
JM		 2882static int extended_func_num(struct pci_dev *pdev)
2883{
2884 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2885}
2886
2887#define MLX4_OWNER_BASE 0x8069c
2888#define MLX4_OWNER_SIZE 4
2889
2890static int mlx4_get_ownership(struct mlx4_dev *dev)
2891{
2892 void __iomem *owner;
2893 u32 ret;
2894
872bf2fb 2895 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 2896 return -EIO;
2897
872bf2fb
YH		 2898 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2899 MLX4_OWNER_BASE,
ab9c17a0
JM		 2900 MLX4_OWNER_SIZE);
2901 if (!owner) {
2902 mlx4_err(dev, "Failed to obtain ownership bit\n");
2903 return -ENOMEM;
2904 }
2905
2906 ret = readl(owner);
2907 iounmap(owner);
2908 return (int) !!ret;
2909}
2910
2911static void mlx4_free_ownership(struct mlx4_dev *dev)
2912{
2913 void __iomem *owner;
2914
872bf2fb 2915 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 2916 return;
2917
872bf2fb
YH		 2918 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2919 MLX4_OWNER_BASE,
ab9c17a0
JM		 2920 MLX4_OWNER_SIZE);
2921 if (!owner) {
2922 mlx4_err(dev, "Failed to obtain ownership bit\n");
2923 return;
2924 }
2925 writel(0, owner);
2926 msleep(1000);
2927 iounmap(owner);
2928}
2929
a0eacca9
MB		 2930#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2931 !!((flags) & MLX4_FLAG_MASTER))
2932
2933static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
55ad3592 2934 u8 total_vfs, int existing_vfs, int reset_flow)
a0eacca9
MB		 2935{
2936 u64 dev_flags = dev->flags;
da315679 2937 int err = 0;
0beb44b0
CS		 2938 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
2939 MLX4_MAX_NUM_VF);
a0eacca9 2940
55ad3592
YH		 2941 if (reset_flow) {
2942 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
2943 GFP_KERNEL);
2944 if (!dev->dev_vfs)
2945 goto free_mem;
2946 return dev_flags;
2947 }
2948
da315679
MB		 2949 atomic_inc(&pf_loading);
2950 if (dev->flags & MLX4_FLAG_SRIOV) {
2951 if (existing_vfs != total_vfs) {
2952 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2953 existing_vfs, total_vfs);
2954 total_vfs = existing_vfs;
2955 }
2956 }
2957
2958 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
a0eacca9
MB		 2959 if (NULL == dev->dev_vfs) {
2960 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2961 goto disable_sriov;
da315679
MB		 2962 }
2963
2964 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
0beb44b0
CS		 2965 if (total_vfs > fw_enabled_sriov_vfs) {
2966 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
2967 total_vfs, fw_enabled_sriov_vfs);
2968 err = -ENOMEM;
2969 goto disable_sriov;
2970 }
da315679
MB		 2971 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2972 err = pci_enable_sriov(pdev, total_vfs);
2973 }
2974 if (err) {
2975 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2976 err);
2977 goto disable_sriov;
2978 } else {
2979 mlx4_warn(dev, "Running in master mode\n");
2980 dev_flags |= MLX4_FLAG_SRIOV |
2981 MLX4_FLAG_MASTER;
2982 dev_flags &= ~MLX4_FLAG_SLAVE;
872bf2fb 2983 dev->persist->num_vfs = total_vfs;
a0eacca9
MB		 2984 }
2985 return dev_flags;
2986
2987disable_sriov:
da315679 2988 atomic_dec(&pf_loading);
55ad3592 2989free_mem:
872bf2fb 2990 dev->persist->num_vfs = 0;
a0eacca9 2991 kfree(dev->dev_vfs);
5114a04e 2992 dev->dev_vfs = NULL;
a0eacca9
MB		 2993 return dev_flags & ~MLX4_FLAG_MASTER;
2994}
2995
de966c59
MB		 2996enum {
2997 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2998};
2999
3000static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3001 int *nvfs)
3002{
3003 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3004 /* Checking for 64 VFs as a limitation of CX2 */
3005 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3006 requested_vfs >= 64) {
3007 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3008 requested_vfs);
3009 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3010 }
3011 return 0;
3012}
3013
e1c00e10 3014static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
55ad3592
YH		 3015 int total_vfs, int *nvfs, struct mlx4_priv *priv,
3016 int reset_flow)
225c7b1f 3017{
225c7b1f 3018 struct mlx4_dev *dev;
e1c00e10 3019 unsigned sum = 0;
225c7b1f 3020 int err;
2a2336f8 3021 int port;
e1c00e10 3022 int i;
7ae0e400 3023 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 3024 int existing_vfs = 0;
225c7b1f 3025
e1c00e10 3026 dev = &priv->dev;
225c7b1f 3027
b581401e
RD		 3028 INIT_LIST_HEAD(&priv->ctx_list);
3029 spin_lock_init(&priv->ctx_lock);
225c7b1f 3030
7ff93f8b 3031 mutex_init(&priv->port_mutex);
53f33ae2 3032 mutex_init(&priv->bond_mutex);
7ff93f8b 3033
6296883c
YP		 3034 INIT_LIST_HEAD(&priv->pgdir_list);
3035 mutex_init(&priv->pgdir_mutex);
3036
c1b43dca
EC		 3037 INIT_LIST_HEAD(&priv->bf_list);
3038 mutex_init(&priv->bf_mutex);
3039
aca7a3ac 3040 dev->rev_id = pdev->revision;
6e7136ed 3041 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 3042
ab9c17a0 3043 /* Detect if this device is a virtual function */
839f1243 3044 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 3045 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3046 dev->flags |= MLX4_FLAG_SLAVE;
3047 } else {
3048 /* We reset the device and enable SRIOV only for physical
3049 * devices. Try to claim ownership on the device;
3050 * if already taken, skip -- do not allow multiple PFs */
3051 err = mlx4_get_ownership(dev);
3052 if (err) {
3053 if (err < 0)
e1c00e10 3054 return err;
ab9c17a0 3055 else {
1a91de28 3056 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 3057 return -EINVAL;
ab9c17a0
JM		 3058 }
3059 }
aca7a3ac 3060
fe6f700d
YP		 3061 atomic_set(&priv->opreq_count, 0);
3062 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3063
ab9c17a0
JM		 3064 /*
3065 * Now reset the HCA before we touch the PCI capabilities or
3066 * attempt a firmware command, since a boot ROM may have left
3067 * the HCA in an undefined state.
3068 */
3069 err = mlx4_reset(dev);
3070 if (err) {
1a91de28 3071 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 3072 goto err_sriov;
ab9c17a0 3073 }
7ae0e400
MB		 3074
3075 if (total_vfs) {
7ae0e400 3076 dev->flags = MLX4_FLAG_MASTER;
da315679
MB		 3077 existing_vfs = pci_num_vf(pdev);
3078 if (existing_vfs)
3079 dev->flags |= MLX4_FLAG_SRIOV;
872bf2fb 3080 dev->persist->num_vfs = total_vfs;
7ae0e400 3081 }
225c7b1f
RD		 3082 }
3083
f6bc11e4
YH		 3084 /* on load remove any previous indication of internal error,
3085 * device is up.
3086 */
3087 dev->persist->state = MLX4_DEVICE_STATE_UP;
3088
ab9c17a0 3089slave_start:
521130d1
EE		 3090 err = mlx4_cmd_init(dev);
3091 if (err) {
1a91de28 3092 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 3093 goto err_sriov;
3094 }
3095
3096 /* In slave functions, the communication channel must be initialized
3097 * before posting commands. Also, init num_slaves before calling
3098 * mlx4_init_hca */
3099 if (mlx4_is_mfunc(dev)) {
7ae0e400 3100 if (mlx4_is_master(dev)) {
ab9c17a0 3101 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 3102
3103 } else {
ab9c17a0 3104 dev->num_slaves = 0;
f356fcbe
JM		 3105 err = mlx4_multi_func_init(dev);
3106 if (err) {
1a91de28 3107 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 3108 goto err_cmd;
3109 }
3110 }
225c7b1f
RD		 3111 }
3112
a0eacca9
MB		 3113 err = mlx4_init_fw(dev);
3114 if (err) {
3115 mlx4_err(dev, "Failed to init fw, aborting.\n");
3116 goto err_mfunc;
3117 }
3118
7ae0e400 3119 if (mlx4_is_master(dev)) {
da315679 3120 /* when we hit the goto slave_start below, dev_cap already initialized */
7ae0e400
MB		 3121 if (!dev_cap) {
3122 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3123
3124 if (!dev_cap) {
3125 err = -ENOMEM;
3126 goto err_fw;
3127 }
3128
3129 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3130 if (err) {
3131 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3132 goto err_fw;
3133 }
3134
de966c59
MB		 3135 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3136 goto err_fw;
3137
7ae0e400 3138 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3139 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3140 total_vfs,
3141 existing_vfs,
3142 reset_flow);
7ae0e400 3143
ed3d2276 3144 mlx4_close_fw(dev);
7ae0e400
MB		 3145 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3146 dev->flags = dev_flags;
3147 if (!SRIOV_VALID_STATE(dev->flags)) {
3148 mlx4_err(dev, "Invalid SRIOV state\n");
3149 goto err_sriov;
3150 }
3151 err = mlx4_reset(dev);
3152 if (err) {
3153 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3154 goto err_sriov;
3155 }
3156 goto slave_start;
3157 }
3158 } else {
3159 /* Legacy mode FW requires SRIOV to be enabled before
3160 * doing QUERY_DEV_CAP, since max_eq's value is different if
3161 * SRIOV is enabled.
3162 */
3163 memset(dev_cap, 0, sizeof(*dev_cap));
3164 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3165 if (err) {
3166 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3167 goto err_fw;
3168 }
de966c59
MB		 3169
3170 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3171 goto err_fw;
7ae0e400
MB		 3172 }
3173 }
3174
225c7b1f 3175 err = mlx4_init_hca(dev);
ab9c17a0
JM		 3176 if (err) {
3177 if (err == -EACCES) {
3178 /* Not primary Physical function
3179 * Running in slave mode */
ffc39f6d 3180 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 3181 /* We're not a PF */
3182 if (dev->flags & MLX4_FLAG_SRIOV) {
3183 if (!existing_vfs)
3184 pci_disable_sriov(pdev);
55ad3592 3185 if (mlx4_is_master(dev) && !reset_flow)
a0eacca9
MB		 3186 atomic_dec(&pf_loading);
3187 dev->flags &= ~MLX4_FLAG_SRIOV;
3188 }
3189 if (!mlx4_is_slave(dev))
3190 mlx4_free_ownership(dev);
ab9c17a0
JM		 3191 dev->flags |= MLX4_FLAG_SLAVE;
3192 dev->flags &= ~MLX4_FLAG_MASTER;
3193 goto slave_start;
3194 } else
a0eacca9 3195 goto err_fw;
ab9c17a0
JM		 3196 }
3197
7ae0e400 3198 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3199 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3200 existing_vfs, reset_flow);
7ae0e400
MB		 3201
3202 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3203 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3204 dev->flags = dev_flags;
3205 err = mlx4_cmd_init(dev);
3206 if (err) {
3207 /* Only VHCR is cleaned up, so could still
3208 * send FW commands
3209 */
3210 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3211 goto err_close;
3212 }
3213 } else {
3214 dev->flags = dev_flags;
3215 }
3216
3217 if (!SRIOV_VALID_STATE(dev->flags)) {
3218 mlx4_err(dev, "Invalid SRIOV state\n");
3219 goto err_close;
3220 }
3221 }
3222
b912b2f8
EP		 3223 /* check if the device is functioning at its maximum possible speed.
3224 * No return code for this call, just warn the user in case of PCI
3225 * express device capabilities are under-satisfied by the bus.
3226 */
83d3459a
EP		 3227 if (!mlx4_is_slave(dev))
3228 mlx4_check_pcie_caps(dev);
b912b2f8 3229
ab9c17a0
JM		 3230 /* In master functions, the communication channel must be initialized
3231 * after obtaining its address from fw */
3232 if (mlx4_is_master(dev)) {
e1c00e10
MD		 3233 if (dev->caps.num_ports < 2 &&
3234 num_vfs_argc > 1) {
3235 err = -EINVAL;
3236 mlx4_err(dev,
3237 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3238 dev->caps.num_ports);
ab9c17a0
JM		 3239 goto err_close;
3240 }
872bf2fb 3241 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
dd41cc3b 3242
872bf2fb
YH		 3243 for (i = 0;
3244 i < sizeof(dev->persist->nvfs)/
3245 sizeof(dev->persist->nvfs[0]); i++) {
e1c00e10
MD		 3246 unsigned j;
3247
872bf2fb 3248 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
e1c00e10
MD		 3249 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3250 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3251 dev->caps.num_ports;
1ab95d37
MB		 3252 }
3253 }
e1c00e10
MD		 3254
3255 /* In master functions, the communication channel
3256 * must be initialized after obtaining its address from fw
3257 */
3258 err = mlx4_multi_func_init(dev);
3259 if (err) {
3260 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3261 goto err_close;
3262 }
ab9c17a0 3263 }
225c7b1f 3264
b8dd786f
YP		 3265 err = mlx4_alloc_eq_table(dev);
3266 if (err)
ab9c17a0 3267 goto err_master_mfunc;
b8dd786f 3268
c66fa19c 3269 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
730c41d5 3270 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 3271
08fb1055 3272 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 3273 if ((mlx4_is_mfunc(dev)) &&
3274 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 3275 err = -ENOSYS;
1a91de28 3276 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 3277 goto err_free_eq;
ab9c17a0
JM		 3278 }
3279
3280 if (!mlx4_is_slave(dev)) {
3281 err = mlx4_init_steering(dev);
3282 if (err)
e1c00e10 3283 goto err_disable_msix;
ab9c17a0 3284 }
b12d93d6 3285
225c7b1f 3286 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 3287 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3288 !mlx4_is_mfunc(dev)) {
08fb1055 3289 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1 3290 dev->caps.num_comp_vectors = 1;
08fb1055
MT		 3291 pci_disable_msix(pdev);
3292 err = mlx4_setup_hca(dev);
3293 }
3294
225c7b1f 3295 if (err)
b12d93d6 3296 goto err_steer;
225c7b1f 3297
5a0d0a61 3298 mlx4_init_quotas(dev);
55ad3592
YH		 3299 /* When PF resources are ready arm its comm channel to enable
3300 * getting commands
3301 */
3302 if (mlx4_is_master(dev)) {
3303 err = mlx4_ARM_COMM_CHANNEL(dev);
3304 if (err) {
3305 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3306 err);
3307 goto err_steer;
3308 }
3309 }
5a0d0a61 3310
7ff93f8b
YP		 3311 for (port = 1; port <= dev->caps.num_ports; port++) {
3312 err = mlx4_init_port_info(dev, port);
3313 if (err)
3314 goto err_port;
3315 }
2a2336f8 3316
53f33ae2
MS		 3317 priv->v2p.port1 = 1;
3318 priv->v2p.port2 = 2;
3319
225c7b1f
RD		 3320 err = mlx4_register_device(dev);
3321 if (err)
7ff93f8b 3322 goto err_port;
225c7b1f 3323
b046ffe5
EP		 3324 mlx4_request_modules(dev);
3325
27bf91d6
YP		 3326 mlx4_sense_init(dev);
3327 mlx4_start_sense(dev);
3328
befdf897 3329 priv->removed = 0;
225c7b1f 3330
55ad3592 3331 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3332 atomic_dec(&pf_loading);
3333
da315679 3334 kfree(dev_cap);
225c7b1f
RD		 3335 return 0;
3336
7ff93f8b 3337err_port:
b4f77264 3338 for (--port; port >= 1; --port)
7ff93f8b
YP		 3339 mlx4_cleanup_port_info(&priv->port[port]);
3340
6de5f7f6 3341 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 3342 if (!mlx4_is_slave(dev))
3343 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 3344 mlx4_cleanup_qp_table(dev);
3345 mlx4_cleanup_srq_table(dev);
3346 mlx4_cleanup_cq_table(dev);
3347 mlx4_cmd_use_polling(dev);
3348 mlx4_cleanup_eq_table(dev);
fe6f700d 3349 mlx4_cleanup_mcg_table(dev);
225c7b1f 3350 mlx4_cleanup_mr_table(dev);
012a8ff5 3351 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 3352 mlx4_cleanup_pd_table(dev);
3353 mlx4_cleanup_uar_table(dev);
3354
b12d93d6 3355err_steer:
ab9c17a0
JM		 3356 if (!mlx4_is_slave(dev))
3357 mlx4_clear_steering(dev);
b12d93d6 3358
e1c00e10
MD		 3359err_disable_msix:
3360 if (dev->flags & MLX4_FLAG_MSI_X)
3361 pci_disable_msix(pdev);
3362
b8dd786f
YP		 3363err_free_eq:
3364 mlx4_free_eq_table(dev);
3365
ab9c17a0 3366err_master_mfunc:
772103e6
JM		 3367 if (mlx4_is_master(dev)) {
3368 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 3369 mlx4_multi_func_cleanup(dev);
772103e6 3370 }
ab9c17a0 3371
b38f2879 3372 if (mlx4_is_slave(dev)) {
99ec41d0 3373 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 3374 kfree(dev->caps.qp0_tunnel);
3375 kfree(dev->caps.qp0_proxy);
3376 kfree(dev->caps.qp1_tunnel);
3377 kfree(dev->caps.qp1_proxy);
3378 }
3379
225c7b1f
RD		 3380err_close:
3381 mlx4_close_hca(dev);
3382
a0eacca9
MB		 3383err_fw:
3384 mlx4_close_fw(dev);
3385
ab9c17a0
JM		 3386err_mfunc:
3387 if (mlx4_is_slave(dev))
3388 mlx4_multi_func_cleanup(dev);
3389
225c7b1f 3390err_cmd:
ffc39f6d 3391 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 3392
ab9c17a0 3393err_sriov:
55ad3592 3394 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
ab9c17a0 3395 pci_disable_sriov(pdev);
55ad3592
YH		 3396 dev->flags &= ~MLX4_FLAG_SRIOV;
3397 }
ab9c17a0 3398
55ad3592 3399 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3400 atomic_dec(&pf_loading);
3401
1ab95d37
MB		 3402 kfree(priv->dev.dev_vfs);
3403
e1c00e10
MD		 3404 if (!mlx4_is_slave(dev))
3405 mlx4_free_ownership(dev);
3406
7ae0e400 3407 kfree(dev_cap);
e1c00e10
MD		 3408 return err;
3409}
3410
3411static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3412 struct mlx4_priv *priv)
3413{
3414 int err;
3415 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3416 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3417 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3418 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3419 unsigned total_vfs = 0;
3420 unsigned int i;
3421
3422 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3423
3424 err = pci_enable_device(pdev);
3425 if (err) {
3426 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3427 return err;
3428 }
3429
3430 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3431 * per port, we must limit the number of VFs to 63 (since their are
3432 * 128 MACs)
3433 */
3434 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3435 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3436 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3437 if (nvfs[i] < 0) {
3438 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3439 err = -EINVAL;
3440 goto err_disable_pdev;
3441 }
3442 }
3443 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3444 i++) {
3445 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3446 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3447 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3448 err = -EINVAL;
3449 goto err_disable_pdev;
3450 }
3451 }
0beb44b0 3452 if (total_vfs > MLX4_MAX_NUM_VF) {
e1c00e10 3453 dev_err(&pdev->dev,
0beb44b0
CS		 3454 "Requested more VF's (%d) than allowed by hw (%d)\n",
3455 total_vfs, MLX4_MAX_NUM_VF);
e1c00e10
MD		 3456 err = -EINVAL;
3457 goto err_disable_pdev;
3458 }
3459
3460 for (i = 0; i < MLX4_MAX_PORTS; i++) {
0beb44b0 3461 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
e1c00e10 3462 dev_err(&pdev->dev,
0beb44b0 3463 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
e1c00e10 3464 nvfs[i] + nvfs[2], i + 1,
0beb44b0 3465 MLX4_MAX_NUM_VF_P_PORT);
e1c00e10
MD		 3466 err = -EINVAL;
3467 goto err_disable_pdev;
3468 }
3469 }
3470
3471 /* Check for BARs. */
3472 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3473 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3474 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3475 pci_dev_data, pci_resource_flags(pdev, 0));
3476 err = -ENODEV;
3477 goto err_disable_pdev;
3478 }
3479 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3480 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3481 err = -ENODEV;
3482 goto err_disable_pdev;
3483 }
3484
3485 err = pci_request_regions(pdev, DRV_NAME);
3486 if (err) {
3487 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3488 goto err_disable_pdev;
3489 }
3490
3491 pci_set_master(pdev);
3492
3493 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3494 if (err) {
3495 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3496 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3497 if (err) {
3498 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3499 goto err_release_regions;
3500 }
3501 }
3502 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3503 if (err) {
3504 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3505 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3506 if (err) {
3507 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3508 goto err_release_regions;
3509 }
3510 }
3511
3512 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3513 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3514 /* Detect if this device is a virtual function */
3515 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3516 /* When acting as pf, we normally skip vfs unless explicitly
3517 * requested to probe them.
3518 */
3519 if (total_vfs) {
3520 unsigned vfs_offset = 0;
3521
3522 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3523 vfs_offset + nvfs[i] < extended_func_num(pdev);
3524 vfs_offset += nvfs[i], i++)
3525 ;
3526 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3527 err = -ENODEV;
3528 goto err_release_regions;
3529 }
3530 if ((extended_func_num(pdev) - vfs_offset)
3531 > prb_vf[i]) {
3532 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3533 extended_func_num(pdev));
3534 err = -ENODEV;
3535 goto err_release_regions;
3536 }
3537 }
3538 }
3539
ad9a0bf0 3540 err = mlx4_catas_init(&priv->dev);
e1c00e10
MD		 3541 if (err)
3542 goto err_release_regions;
ad9a0bf0 3543
55ad3592 3544 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
ad9a0bf0
YH		 3545 if (err)
3546 goto err_catas;
3547
e1c00e10 3548 return 0;
225c7b1f 3549
ad9a0bf0
YH		 3550err_catas:
3551 mlx4_catas_end(&priv->dev);
3552
a01df0fe
RD		 3553err_release_regions:
3554 pci_release_regions(pdev);
225c7b1f
RD		 3555
3556err_disable_pdev:
3557 pci_disable_device(pdev);
3558 pci_set_drvdata(pdev, NULL);
3559 return err;
3560}
3561
1dd06ae8 3562static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 3563{
befdf897
WY		 3564 struct mlx4_priv *priv;
3565 struct mlx4_dev *dev;
e1c00e10 3566 int ret;
befdf897 3567
0a645e80 3568 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 3569
befdf897
WY		 3570 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
3571 if (!priv)
3572 return -ENOMEM;
3573
3574 dev = &priv->dev;
872bf2fb
YH		 3575 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3576 if (!dev->persist) {
3577 kfree(priv);
3578 return -ENOMEM;
3579 }
3580 dev->persist->pdev = pdev;
3581 dev->persist->dev = dev;
3582 pci_set_drvdata(pdev, dev->persist);
befdf897 3583 priv->pci_dev_data = id->driver_data;
f6bc11e4 3584 mutex_init(&dev->persist->device_state_mutex);
c69453e2 3585 mutex_init(&dev->persist->interface_state_mutex);
befdf897 3586
e1c00e10 3587 ret = __mlx4_init_one(pdev, id->driver_data, priv);
872bf2fb
YH		 3588 if (ret) {
3589 kfree(dev->persist);
e1c00e10 3590 kfree(priv);
2ba5fbd6
YH		 3591 } else {
3592 pci_save_state(pdev);
872bf2fb 3593 }
2ba5fbd6 3594
e1c00e10 3595 return ret;
3d73c288
RD		 3596}
3597
dd0eefe3
YH		 3598static void mlx4_clean_dev(struct mlx4_dev *dev)
3599{
3600 struct mlx4_dev_persistent *persist = dev->persist;
3601 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 3602 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
dd0eefe3
YH		 3603
3604 memset(priv, 0, sizeof(*priv));
3605 priv->dev.persist = persist;
55ad3592 3606 priv->dev.flags = flags;
dd0eefe3
YH		 3607}
3608
e1c00e10 3609static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f 3610{
872bf2fb
YH		 3611 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3612 struct mlx4_dev *dev = persist->dev;
225c7b1f 3613 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 3614 int pci_dev_data;
dd0eefe3 3615 int p, i;
225c7b1f 3616
befdf897
WY		 3617 if (priv->removed)
3618 return;
225c7b1f 3619
dd0eefe3
YH		 3620 /* saving current ports type for further use */
3621 for (i = 0; i < dev->caps.num_ports; i++) {
3622 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3623 dev->persist->curr_port_poss_type[i] = dev->caps.
3624 possible_type[i + 1];
3625 }
3626
befdf897 3627 pci_dev_data = priv->pci_dev_data;
225c7b1f 3628
befdf897
WY		 3629 mlx4_stop_sense(dev);
3630 mlx4_unregister_device(dev);
225c7b1f 3631
befdf897
WY		 3632 for (p = 1; p <= dev->caps.num_ports; p++) {
3633 mlx4_cleanup_port_info(&priv->port[p]);
3634 mlx4_CLOSE_PORT(dev, p);
3635 }
3636
3637 if (mlx4_is_master(dev))
3638 mlx4_free_resource_tracker(dev,
3639 RES_TR_FREE_SLAVES_ONLY);
3640
6de5f7f6 3641 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 3642 if (!mlx4_is_slave(dev))
3643 mlx4_cleanup_counters_table(dev);
befdf897
WY		 3644 mlx4_cleanup_qp_table(dev);
3645 mlx4_cleanup_srq_table(dev);
3646 mlx4_cleanup_cq_table(dev);
3647 mlx4_cmd_use_polling(dev);
3648 mlx4_cleanup_eq_table(dev);
3649 mlx4_cleanup_mcg_table(dev);
3650 mlx4_cleanup_mr_table(dev);
3651 mlx4_cleanup_xrcd_table(dev);
3652 mlx4_cleanup_pd_table(dev);
225c7b1f 3653
befdf897
WY		 3654 if (mlx4_is_master(dev))
3655 mlx4_free_resource_tracker(dev,
3656 RES_TR_FREE_STRUCTS_ONLY);
47605df9 3657
befdf897
WY		 3658 iounmap(priv->kar);
3659 mlx4_uar_free(dev, &priv->driver_uar);
3660 mlx4_cleanup_uar_table(dev);
3661 if (!mlx4_is_slave(dev))
3662 mlx4_clear_steering(dev);
3663 mlx4_free_eq_table(dev);
3664 if (mlx4_is_master(dev))
3665 mlx4_multi_func_cleanup(dev);
3666 mlx4_close_hca(dev);
a0eacca9 3667 mlx4_close_fw(dev);
befdf897
WY		 3668 if (mlx4_is_slave(dev))
3669 mlx4_multi_func_cleanup(dev);
ffc39f6d 3670 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 3671
befdf897
WY		 3672 if (dev->flags & MLX4_FLAG_MSI_X)
3673 pci_disable_msix(pdev);
befdf897
WY		 3674
3675 if (!mlx4_is_slave(dev))
3676 mlx4_free_ownership(dev);
3677
99ec41d0 3678 kfree(dev->caps.qp0_qkey);
befdf897
WY		 3679 kfree(dev->caps.qp0_tunnel);
3680 kfree(dev->caps.qp0_proxy);
3681 kfree(dev->caps.qp1_tunnel);
3682 kfree(dev->caps.qp1_proxy);
3683 kfree(dev->dev_vfs);
3684
dd0eefe3 3685 mlx4_clean_dev(dev);
befdf897
WY		 3686 priv->pci_dev_data = pci_dev_data;
3687 priv->removed = 1;
3688}
3689
3690static void mlx4_remove_one(struct pci_dev *pdev)
3691{
872bf2fb
YH		 3692 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3693 struct mlx4_dev *dev = persist->dev;
befdf897 3694 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 3695 int active_vfs = 0;
befdf897 3696
c69453e2
YH		 3697 mutex_lock(&persist->interface_state_mutex);
3698 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3699 mutex_unlock(&persist->interface_state_mutex);
3700
55ad3592
YH		 3701 /* Disabling SR-IOV is not allowed while there are active vf's */
3702 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3703 active_vfs = mlx4_how_many_lives_vf(dev);
3704 if (active_vfs) {
3705 pr_warn("Removing PF when there are active VF's !!\n");
3706 pr_warn("Will not disable SR-IOV.\n");
3707 }
3708 }
3709
c69453e2
YH		 3710 /* device marked to be under deletion running now without the lock
3711 * letting other tasks to be terminated
3712 */
3713 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3714 mlx4_unload_one(pdev);
3715 else
3716 mlx4_info(dev, "%s: interface is down\n", __func__);
ad9a0bf0 3717 mlx4_catas_end(dev);
55ad3592
YH		 3718 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3719 mlx4_warn(dev, "Disabling SR-IOV\n");
3720 pci_disable_sriov(pdev);
3721 }
3722
e1c00e10
MD		 3723 pci_release_regions(pdev);
3724 pci_disable_device(pdev);
872bf2fb 3725 kfree(dev->persist);
befdf897
WY		 3726 kfree(priv);
3727 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 3728}
3729
dd0eefe3
YH		 3730static int restore_current_port_types(struct mlx4_dev *dev,
3731 enum mlx4_port_type *types,
3732 enum mlx4_port_type *poss_types)
3733{
3734 struct mlx4_priv *priv = mlx4_priv(dev);
3735 int err, i;
3736
3737 mlx4_stop_sense(dev);
3738
3739 mutex_lock(&priv->port_mutex);
3740 for (i = 0; i < dev->caps.num_ports; i++)
3741 dev->caps.possible_type[i + 1] = poss_types[i];
3742 err = mlx4_change_port_types(dev, types);
3743 mlx4_start_sense(dev);
3744 mutex_unlock(&priv->port_mutex);
3745
3746 return err;
3747}
3748
ee49bd93
JM		 3749int mlx4_restart_one(struct pci_dev *pdev)
3750{
872bf2fb
YH		 3751 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3752 struct mlx4_dev *dev = persist->dev;
839f1243 3753 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 3754 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3755 int pci_dev_data, err, total_vfs;
839f1243
RD		 3756
3757 pci_dev_data = priv->pci_dev_data;
872bf2fb
YH		 3758 total_vfs = dev->persist->num_vfs;
3759 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
e1c00e10
MD		 3760
3761 mlx4_unload_one(pdev);
55ad3592 3762 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
e1c00e10
MD		 3763 if (err) {
3764 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3765 __func__, pci_name(pdev), err);
3766 return err;
3767 }
3768
dd0eefe3
YH		 3769 err = restore_current_port_types(dev, dev->persist->curr_port_type,
3770 dev->persist->curr_port_poss_type);
3771 if (err)
3772 mlx4_err(dev, "could not restore original port types (%d)\n",
3773 err);
3774
e1c00e10 3775 return err;
ee49bd93
JM		 3776}
3777
9baa3c34 3778static const struct pci_device_id mlx4_pci_table[] = {
ab9c17a0 3779 /* MT25408 "Hermon" SDR */
ca3e57a5 3780 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3781 /* MT25408 "Hermon" DDR */
ca3e57a5 3782 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3783 /* MT25408 "Hermon" QDR */
ca3e57a5 3784 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3785 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 3786 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3787 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 3788 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3789 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 3790 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3791 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 3792 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3793 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 3794 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3795 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 3796 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3797 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 3798 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3799 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 3800 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3801 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 3802 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3803 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 3804 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3805 /* MT27500 Family [ConnectX-3] */
3806 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3807 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 3808 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3809 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3810 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3811 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3812 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3813 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3814 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3815 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3816 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3817 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3818 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3819 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3820 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 3821 { 0, }
3822};
3823
3824MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3825
57dbf29a
KSS		 3826static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3827 pci_channel_state_t state)
3828{
2ba5fbd6
YH		 3829 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3830
3831 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
3832 mlx4_enter_error_state(persist);
57dbf29a 3833
2ba5fbd6
YH		 3834 mutex_lock(&persist->interface_state_mutex);
3835 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3836 mlx4_unload_one(pdev);
3837
3838 mutex_unlock(&persist->interface_state_mutex);
3839 if (state == pci_channel_io_perm_failure)
3840 return PCI_ERS_RESULT_DISCONNECT;
3841
3842 pci_disable_device(pdev);
3843 return PCI_ERS_RESULT_NEED_RESET;
57dbf29a
KSS		 3844}
3845
3846static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3847{
2ba5fbd6
YH		 3848 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3849 struct mlx4_dev *dev = persist->dev;
befdf897
WY		 3850 struct mlx4_priv *priv = mlx4_priv(dev);
3851 int ret;
2ba5fbd6
YH		 3852 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3853 int total_vfs;
97a5221f 3854
2ba5fbd6
YH		 3855 mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
3856 ret = pci_enable_device(pdev);
3857 if (ret) {
3858 mlx4_err(dev, "Can not re-enable device, ret=%d\n", ret);
3859 return PCI_ERS_RESULT_DISCONNECT;
3860 }
3861
3862 pci_set_master(pdev);
3863 pci_restore_state(pdev);
3864 pci_save_state(pdev);
3865
3866 total_vfs = dev->persist->num_vfs;
3867 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3868
3869 mutex_lock(&persist->interface_state_mutex);
3870 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
3871 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
55ad3592 3872 priv, 1);
2ba5fbd6
YH		 3873 if (ret) {
3874 mlx4_err(dev, "%s: mlx4_load_one failed, ret=%d\n",
3875 __func__, ret);
3876 goto end;
3877 }
3878
3879 ret = restore_current_port_types(dev, dev->persist->
3880 curr_port_type, dev->persist->
3881 curr_port_poss_type);
3882 if (ret)
3883 mlx4_err(dev, "could not restore original port types (%d)\n", ret);
3884 }
3885end:
3886 mutex_unlock(&persist->interface_state_mutex);
57dbf29a
KSS		 3887
3888 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3889}
3890
2ba5fbd6
YH		 3891static void mlx4_shutdown(struct pci_dev *pdev)
3892{
3893 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3894
3895 mlx4_info(persist->dev, "mlx4_shutdown was called\n");
3896 mutex_lock(&persist->interface_state_mutex);
3897 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3898 mlx4_unload_one(pdev);
3899 mutex_unlock(&persist->interface_state_mutex);
3900}
3901
3646f0e5 3902static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 3903 .error_detected = mlx4_pci_err_detected,
3904 .slot_reset = mlx4_pci_slot_reset,
3905};
3906
225c7b1f
RD		 3907static struct pci_driver mlx4_driver = {
3908 .name = DRV_NAME,
3909 .id_table = mlx4_pci_table,
3910 .probe = mlx4_init_one,
2ba5fbd6 3911 .shutdown = mlx4_shutdown,
f57e6848 3912 .remove = mlx4_remove_one,
57dbf29a 3913 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 3914};
3915
7ff93f8b
YP		 3916static int __init mlx4_verify_params(void)
3917{
3918 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 3919 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 3920 return -1;
3921 }
3922
cb29688a 3923 if (log_num_vlan != 0)
c20862c8
AV		 3924 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3925 MLX4_LOG_NUM_VLANS);
7ff93f8b 3926
ecc8fb11
AV		 3927 if (use_prio != 0)
3928 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 3929
0498628f 3930 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 3931 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3932 log_mtts_per_seg);
ab6bf42e
EC		 3933 return -1;
3934 }
3935
ab9c17a0
JM		 3936 /* Check if module param for ports type has legal combination */
3937 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 3938 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 3939 port_type_array[0] = true;
3940 }
3941
7d077cd3
MB		 3942 if (mlx4_log_num_mgm_entry_size < -7 ||
3943 (mlx4_log_num_mgm_entry_size > 0 &&
3944 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3945 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
3946 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
1a91de28
JP		 3947 mlx4_log_num_mgm_entry_size,
3948 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3949 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 3950 return -1;
3951 }
3952
7ff93f8b
YP		 3953 return 0;
3954}
3955
225c7b1f
RD		 3956static int __init mlx4_init(void)
3957{
3958 int ret;
3959
7ff93f8b
YP		 3960 if (mlx4_verify_params())
3961 return -EINVAL;
3962
27bf91d6
YP		 3963
3964 mlx4_wq = create_singlethread_workqueue("mlx4");
3965 if (!mlx4_wq)
3966 return -ENOMEM;
ee49bd93 3967
225c7b1f 3968 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 3969 if (ret < 0)
3970 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3971 return ret < 0 ? ret : 0;
3972}
3973
3974static void __exit mlx4_cleanup(void)
3975{
3976 pci_unregister_driver(&mlx4_driver);
27bf91d6 3977 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3978}
3979
3980module_init(mlx4_init);
3981module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)