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net/mlx4_core: Read HCA frequency and map internal clock
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
90b1ebe7 44#include <linux/netdevice.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
ab9c17a0
JM		 80static int num_vfs;
81module_param(num_vfs, int, 0444);
82MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
83
84static int probe_vf;
85module_param(probe_vf, int, 0644);
86MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
87
3c439b55 88int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 89module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
3c439b55 93 " 10 gives 248.range: 7 <="
0ff1fb65 94 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 95 " To activate device managed"
96 " flow steering when available, set to -1");
0ec2c0f8 97
08ff3235
OG		 98static bool enable_64b_cqe_eqe;
99module_param(enable_64b_cqe_eqe, bool, 0444);
100MODULE_PARM_DESC(enable_64b_cqe_eqe,
101 "Enable 64 byte CQEs/EQEs when the the FW supports this");
102
ab9c17a0 103#define HCA_GLOBAL_CAP_MASK 0
08ff3235
OG		 104
105#define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
ab9c17a0 106
f57e6848 107static char mlx4_version[] =
225c7b1f
RD		 108 DRV_NAME ": Mellanox ConnectX core driver v"
109 DRV_VERSION " (" DRV_RELDATE ")\n";
110
111static struct mlx4_profile default_profile = {
ab9c17a0 112 .num_qp = 1 << 18,
225c7b1f 113 .num_srq = 1 << 16,
c9f2ba5e 114 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 115 .num_cq = 1 << 16,
116 .num_mcg = 1 << 13,
ab9c17a0 117 .num_mpt = 1 << 19,
9fd7a1e1 118 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 119};
120
ab9c17a0 121static int log_num_mac = 7;
93fc9e1b
YP		 122module_param_named(log_num_mac, log_num_mac, int, 0444);
123MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
124
125static int log_num_vlan;
126module_param_named(log_num_vlan, log_num_vlan, int, 0444);
127MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 128/* Log2 max number of VLANs per ETH port (0-7) */
129#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 130
eb939922 131static bool use_prio;
93fc9e1b
YP		 132module_param_named(use_prio, use_prio, bool, 0444);
133MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
134 "(0/1, default 0)");
135
2b8fb286 136int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 137module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 138MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 139
8d0fc7b6 140static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 141static int arr_argc = 2;
142module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 143MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
144 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 145
146struct mlx4_port_config {
147 struct list_head list;
148 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
149 struct pci_dev *pdev;
150};
151
27bf91d6
YP		 152int mlx4_check_port_params(struct mlx4_dev *dev,
153 enum mlx4_port_type *port_type)
7ff93f8b
YP		 154{
155 int i;
156
157 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 158 if (port_type[i] != port_type[i + 1]) {
159 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
160 mlx4_err(dev, "Only same port types supported "
161 "on this HCA, aborting.\n");
162 return -EINVAL;
163 }
7ff93f8b
YP		 164 }
165 }
7ff93f8b
YP		 166
167 for (i = 0; i < dev->caps.num_ports; i++) {
168 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
169 mlx4_err(dev, "Requested port type for port %d is not "
170 "supported on this HCA\n", i + 1);
171 return -EINVAL;
172 }
173 }
174 return 0;
175}
176
177static void mlx4_set_port_mask(struct mlx4_dev *dev)
178{
179 int i;
180
7ff93f8b 181 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 182 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 183}
f2a3f6a3 184
3d73c288 185static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 186{
187 int err;
5ae2a7a8 188 int i;
225c7b1f
RD		 189
190 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
191 if (err) {
192 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
193 return err;
194 }
195
196 if (dev_cap->min_page_sz > PAGE_SIZE) {
197 mlx4_err(dev, "HCA minimum page size of %d bigger than "
198 "kernel PAGE_SIZE of %ld, aborting.\n",
199 dev_cap->min_page_sz, PAGE_SIZE);
200 return -ENODEV;
201 }
202 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
203 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
204 "aborting.\n",
205 dev_cap->num_ports, MLX4_MAX_PORTS);
206 return -ENODEV;
207 }
208
209 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
210 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
211 "PCI resource 2 size of 0x%llx, aborting.\n",
212 dev_cap->uar_size,
213 (unsigned long long) pci_resource_len(dev->pdev, 2));
214 return -ENODEV;
215 }
216
217 dev->caps.num_ports = dev_cap->num_ports;
3fc929e2 218 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
5ae2a7a8
RD		 219 for (i = 1; i <= dev->caps.num_ports; ++i) {
220 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 221 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
6634961c
JM		 222 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
223 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
224 /* set gid and pkey table operating lengths by default
225 * to non-sriov values */
5ae2a7a8
RD		 226 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
227 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
228 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 229 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
230 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 231 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 232 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
233 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 234 dev->caps.trans_type[i] = dev_cap->trans_type[i];
235 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
236 dev->caps.wavelength[i] = dev_cap->wavelength[i];
237 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 238 }
239
ab9c17a0 240 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 241 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 242 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
243 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
244 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
245 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
246 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
247 dev->caps.max_wqes = dev_cap->max_qp_sz;
248 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 249 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
250 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
251 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
252 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
253 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 254 /*
255 * Subtract 1 from the limit because we need to allocate a
256 * spare CQE so the HCA HW can tell the difference between an
257 * empty CQ and a full CQ.
258 */
259 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
260 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
261 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 262 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 263 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 264
265 /* The first 128 UARs are used for EQ doorbells */
266 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 267 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 268 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
269 dev_cap->reserved_xrcds : 0;
270 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
271 dev_cap->max_xrcds : 0;
2b8fb286
MA		 272 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
273
149983af 274 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 275 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
276 dev->caps.flags = dev_cap->flags;
b3416f44 277 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 278 dev->caps.bmme_flags = dev_cap->bmme_flags;
279 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 280 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 281 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 282 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 283
ca3e57a5
RD		 284 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
285 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 286 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 287 /* Don't do sense port on multifunction devices (for now at least) */
288 if (mlx4_is_mfunc(dev))
289 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 290
93fc9e1b 291 dev->caps.log_num_macs = log_num_mac;
cb29688a 292 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 293 dev->caps.log_num_prios = use_prio ? 3 : 0;
294
295 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 296 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
297 if (dev->caps.supported_type[i]) {
298 /* if only ETH is supported - assign ETH */
299 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
300 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 301 /* if only IB is supported, assign IB */
ab9c17a0 302 else if (dev->caps.supported_type[i] ==
105c320f
JM		 303 MLX4_PORT_TYPE_IB)
304 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 305 else {
105c320f
JM		 306 /* if IB and ETH are supported, we set the port
307 * type according to user selection of port type;
308 * if user selected none, take the FW hint */
309 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 310 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
311 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 312 else
105c320f 313 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 314 }
315 }
8d0fc7b6
YP		 316 /*
317 * Link sensing is allowed on the port if 3 conditions are true:
318 * 1. Both protocols are supported on the port.
319 * 2. Different types are supported on the port
320 * 3. FW declared that it supports link sensing
321 */
27bf91d6 322 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 323 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 324 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 325 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 326
8d0fc7b6
YP		 327 /*
328 * If "default_sense" bit is set, we move the port to "AUTO" mode
329 * and perform sense_port FW command to try and set the correct
330 * port type from beginning
331 */
46c46747 332 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 333 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
334 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
335 mlx4_SENSE_PORT(dev, i, &sensed_port);
336 if (sensed_port != MLX4_PORT_TYPE_NONE)
337 dev->caps.port_type[i] = sensed_port;
338 } else {
339 dev->caps.possible_type[i] = dev->caps.port_type[i];
340 }
341
93fc9e1b
YP		 342 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
343 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
344 mlx4_warn(dev, "Requested number of MACs is too much "
345 "for port %d, reducing to %d.\n",
346 i, 1 << dev->caps.log_num_macs);
347 }
348 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
349 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
350 mlx4_warn(dev, "Requested number of VLANs is too much "
351 "for port %d, reducing to %d.\n",
352 i, 1 << dev->caps.log_num_vlans);
353 }
354 }
355
f2a3f6a3
OG		 356 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
357
93fc9e1b
YP		 358 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
359 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
360 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
361 (1 << dev->caps.log_num_macs) *
362 (1 << dev->caps.log_num_vlans) *
363 (1 << dev->caps.log_num_prios) *
364 dev->caps.num_ports;
365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
366
367 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
369 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
370 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
371
e2c76824 372 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235
OG		 373
374 if (!enable_64b_cqe_eqe) {
375 if (dev_cap->flags &
376 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
377 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
378 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
379 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
380 }
381 }
382
f97b4b5d 383 if ((dev->caps.flags &
08ff3235
OG		 384 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
385 mlx4_is_master(dev))
386 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
387
225c7b1f
RD		 388 return 0;
389}
ab9c17a0
JM		 390/*The function checks if there are live vf, return the num of them*/
391static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
392{
393 struct mlx4_priv *priv = mlx4_priv(dev);
394 struct mlx4_slave_state *s_state;
395 int i;
396 int ret = 0;
397
398 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
399 s_state = &priv->mfunc.master.slave_state[i];
400 if (s_state->active && s_state->last_cmd !=
401 MLX4_COMM_CMD_RESET) {
402 mlx4_warn(dev, "%s: slave: %d is still active\n",
403 __func__, i);
404 ret++;
405 }
406 }
407 return ret;
408}
409
396f2feb
JM		 410int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
411{
412 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 413
414 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
415 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 416 return -EINVAL;
417
47605df9 418 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 419 /* tunnel qp */
47605df9 420 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 421 else
47605df9 422 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 423 *qkey = qk;
424 return 0;
425}
426EXPORT_SYMBOL(mlx4_get_parav_qkey);
427
54679e14
JM		 428void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
429{
430 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
431
432 if (!mlx4_is_master(dev))
433 return;
434
435 priv->virt2phys_pkey[slave][port - 1][i] = val;
436}
437EXPORT_SYMBOL(mlx4_sync_pkey_table);
438
afa8fd1d
JM		 439void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
440{
441 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
442
443 if (!mlx4_is_master(dev))
444 return;
445
446 priv->slave_node_guids[slave] = guid;
447}
448EXPORT_SYMBOL(mlx4_put_slave_node_guid);
449
450__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
451{
452 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
453
454 if (!mlx4_is_master(dev))
455 return 0;
456
457 return priv->slave_node_guids[slave];
458}
459EXPORT_SYMBOL(mlx4_get_slave_node_guid);
460
e10903b0 461int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 462{
463 struct mlx4_priv *priv = mlx4_priv(dev);
464 struct mlx4_slave_state *s_slave;
465
466 if (!mlx4_is_master(dev))
467 return 0;
468
469 s_slave = &priv->mfunc.master.slave_state[slave];
470 return !!s_slave->active;
471}
472EXPORT_SYMBOL(mlx4_is_slave_active);
473
7b8157be
JM		 474static void slave_adjust_steering_mode(struct mlx4_dev *dev,
475 struct mlx4_dev_cap *dev_cap,
476 struct mlx4_init_hca_param *hca_param)
477{
478 dev->caps.steering_mode = hca_param->steering_mode;
479 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
480 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
481 dev->caps.fs_log_max_ucast_qp_range_size =
482 dev_cap->fs_log_max_ucast_qp_range_size;
483 } else
484 dev->caps.num_qp_per_mgm =
485 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
486
487 mlx4_dbg(dev, "Steering mode is: %s\n",
488 mlx4_steering_mode_str(dev->caps.steering_mode));
489}
490
ab9c17a0
JM		 491static int mlx4_slave_cap(struct mlx4_dev *dev)
492{
493 int err;
494 u32 page_size;
495 struct mlx4_dev_cap dev_cap;
496 struct mlx4_func_cap func_cap;
497 struct mlx4_init_hca_param hca_param;
498 int i;
499
500 memset(&hca_param, 0, sizeof(hca_param));
501 err = mlx4_QUERY_HCA(dev, &hca_param);
502 if (err) {
503 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
504 return err;
505 }
506
507 /*fail if the hca has an unknown capability */
508 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
509 HCA_GLOBAL_CAP_MASK) {
510 mlx4_err(dev, "Unknown hca global capabilities\n");
511 return -ENOSYS;
512 }
513
514 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
515
ddd8a6c1
EE		 516 dev->caps.hca_core_clock = hca_param.hca_core_clock;
517
ab9c17a0 518 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 519 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 520 err = mlx4_dev_cap(dev, &dev_cap);
521 if (err) {
522 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
523 return err;
524 }
525
b91cb3eb
JM		 526 err = mlx4_QUERY_FW(dev);
527 if (err)
528 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
529
ab9c17a0
JM		 530 page_size = ~dev->caps.page_size_cap + 1;
531 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
532 if (page_size > PAGE_SIZE) {
533 mlx4_err(dev, "HCA minimum page size of %d bigger than "
534 "kernel PAGE_SIZE of %ld, aborting.\n",
535 page_size, PAGE_SIZE);
536 return -ENODEV;
537 }
538
539 /* slave gets uar page size from QUERY_HCA fw command */
540 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
541
542 /* TODO: relax this assumption */
543 if (dev->caps.uar_page_size != PAGE_SIZE) {
544 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
545 dev->caps.uar_page_size, PAGE_SIZE);
546 return -ENODEV;
547 }
548
549 memset(&func_cap, 0, sizeof(func_cap));
47605df9 550 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 551 if (err) {
47605df9
JM		 552 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
553 err);
ab9c17a0
JM		 554 return err;
555 }
556
557 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
558 PF_CONTEXT_BEHAVIOUR_MASK) {
559 mlx4_err(dev, "Unknown pf context behaviour\n");
560 return -ENOSYS;
561 }
562
ab9c17a0
JM		 563 dev->caps.num_ports = func_cap.num_ports;
564 dev->caps.num_qps = func_cap.qp_quota;
565 dev->caps.num_srqs = func_cap.srq_quota;
566 dev->caps.num_cqs = func_cap.cq_quota;
567 dev->caps.num_eqs = func_cap.max_eq;
568 dev->caps.reserved_eqs = func_cap.reserved_eq;
569 dev->caps.num_mpts = func_cap.mpt_quota;
570 dev->caps.num_mtts = func_cap.mtt_quota;
571 dev->caps.num_pds = MLX4_NUM_PDS;
572 dev->caps.num_mgms = 0;
573 dev->caps.num_amgms = 0;
574
ab9c17a0
JM		 575 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
576 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
577 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
578 return -ENODEV;
579 }
580
47605df9
JM		 581 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
582 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
583 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
584 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
585
586 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
587 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
588 err = -ENOMEM;
589 goto err_mem;
590 }
591
6634961c 592 for (i = 1; i <= dev->caps.num_ports; ++i) {
47605df9
JM		 593 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
594 if (err) {
595 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
596 " port %d, aborting (%d).\n", i, err);
597 goto err_mem;
598 }
599 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
600 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
601 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
602 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 603 dev->caps.port_mask[i] = dev->caps.port_type[i];
6634961c
JM		 604 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
605 &dev->caps.gid_table_len[i],
606 &dev->caps.pkey_table_len[i]))
47605df9 607 goto err_mem;
6634961c 608 }
6230bb23 609
ab9c17a0
JM		 610 if (dev->caps.uar_page_size * (dev->caps.num_uars -
611 dev->caps.reserved_uars) >
612 pci_resource_len(dev->pdev, 2)) {
613 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
614 "PCI resource 2 size of 0x%llx, aborting.\n",
615 dev->caps.uar_page_size * dev->caps.num_uars,
616 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 617 goto err_mem;
ab9c17a0
JM		 618 }
619
08ff3235
OG		 620 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
621 dev->caps.eqe_size = 64;
622 dev->caps.eqe_factor = 1;
623 } else {
624 dev->caps.eqe_size = 32;
625 dev->caps.eqe_factor = 0;
626 }
627
628 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
629 dev->caps.cqe_size = 64;
630 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
631 } else {
632 dev->caps.cqe_size = 32;
633 }
634
7b8157be
JM		 635 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
636
ab9c17a0 637 return 0;
47605df9
JM		 638
639err_mem:
640 kfree(dev->caps.qp0_tunnel);
641 kfree(dev->caps.qp0_proxy);
642 kfree(dev->caps.qp1_tunnel);
643 kfree(dev->caps.qp1_proxy);
644 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
645 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
646
647 return err;
ab9c17a0 648}
225c7b1f 649
7ff93f8b
YP		 650/*
651 * Change the port configuration of the device.
652 * Every user of this function must hold the port mutex.
653 */
27bf91d6
YP		 654int mlx4_change_port_types(struct mlx4_dev *dev,
655 enum mlx4_port_type *port_types)
7ff93f8b
YP		 656{
657 int err = 0;
658 int change = 0;
659 int port;
660
661 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 662 /* Change the port type only if the new type is different
663 * from the current, and not set to Auto */
3d8f9308 664 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 665 change = 1;
7ff93f8b
YP		 666 }
667 if (change) {
668 mlx4_unregister_device(dev);
669 for (port = 1; port <= dev->caps.num_ports; port++) {
670 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 671 dev->caps.port_type[port] = port_types[port - 1];
6634961c 672 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b
YP		 673 if (err) {
674 mlx4_err(dev, "Failed to set port %d, "
675 "aborting\n", port);
676 goto out;
677 }
678 }
679 mlx4_set_port_mask(dev);
680 err = mlx4_register_device(dev);
681 }
682
683out:
684 return err;
685}
686
687static ssize_t show_port_type(struct device *dev,
688 struct device_attribute *attr,
689 char *buf)
690{
691 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
692 port_attr);
693 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 694 char type[8];
695
696 sprintf(type, "%s",
697 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
698 "ib" : "eth");
699 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
700 sprintf(buf, "auto (%s)\n", type);
701 else
702 sprintf(buf, "%s\n", type);
7ff93f8b 703
27bf91d6 704 return strlen(buf);
7ff93f8b
YP		 705}
706
707static ssize_t set_port_type(struct device *dev,
708 struct device_attribute *attr,
709 const char *buf, size_t count)
710{
711 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
712 port_attr);
713 struct mlx4_dev *mdev = info->dev;
714 struct mlx4_priv *priv = mlx4_priv(mdev);
715 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 716 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 717 int i;
718 int err = 0;
719
720 if (!strcmp(buf, "ib\n"))
721 info->tmp_type = MLX4_PORT_TYPE_IB;
722 else if (!strcmp(buf, "eth\n"))
723 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 724 else if (!strcmp(buf, "auto\n"))
725 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 726 else {
727 mlx4_err(mdev, "%s is not supported port type\n", buf);
728 return -EINVAL;
729 }
730
27bf91d6 731 mlx4_stop_sense(mdev);
7ff93f8b 732 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 733 /* Possible type is always the one that was delivered */
734 mdev->caps.possible_type[info->port] = info->tmp_type;
735
736 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 737 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 738 mdev->caps.possible_type[i+1];
739 if (types[i] == MLX4_PORT_TYPE_AUTO)
740 types[i] = mdev->caps.port_type[i+1];
741 }
7ff93f8b 742
58a60168
YP		 743 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
744 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 745 for (i = 1; i <= mdev->caps.num_ports; i++) {
746 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
747 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
748 err = -EINVAL;
749 }
750 }
751 }
752 if (err) {
753 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
754 "Set only 'eth' or 'ib' for both ports "
755 "(should be the same)\n");
756 goto out;
757 }
758
759 mlx4_do_sense_ports(mdev, new_types, types);
760
761 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 762 if (err)
763 goto out;
764
27bf91d6
YP		 765 /* We are about to apply the changes after the configuration
766 * was verified, no need to remember the temporary types
767 * any more */
768 for (i = 0; i < mdev->caps.num_ports; i++)
769 priv->port[i + 1].tmp_type = 0;
7ff93f8b 770
27bf91d6 771 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 772
773out:
27bf91d6 774 mlx4_start_sense(mdev);
7ff93f8b
YP		 775 mutex_unlock(&priv->port_mutex);
776 return err ? err : count;
777}
778
096335b3
OG		 779enum ibta_mtu {
780 IB_MTU_256 = 1,
781 IB_MTU_512 = 2,
782 IB_MTU_1024 = 3,
783 IB_MTU_2048 = 4,
784 IB_MTU_4096 = 5
785};
786
787static inline int int_to_ibta_mtu(int mtu)
788{
789 switch (mtu) {
790 case 256: return IB_MTU_256;
791 case 512: return IB_MTU_512;
792 case 1024: return IB_MTU_1024;
793 case 2048: return IB_MTU_2048;
794 case 4096: return IB_MTU_4096;
795 default: return -1;
796 }
797}
798
799static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
800{
801 switch (mtu) {
802 case IB_MTU_256: return 256;
803 case IB_MTU_512: return 512;
804 case IB_MTU_1024: return 1024;
805 case IB_MTU_2048: return 2048;
806 case IB_MTU_4096: return 4096;
807 default: return -1;
808 }
809}
810
811static ssize_t show_port_ib_mtu(struct device *dev,
812 struct device_attribute *attr,
813 char *buf)
814{
815 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
816 port_mtu_attr);
817 struct mlx4_dev *mdev = info->dev;
818
819 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
820 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
821
822 sprintf(buf, "%d\n",
823 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
824 return strlen(buf);
825}
826
827static ssize_t set_port_ib_mtu(struct device *dev,
828 struct device_attribute *attr,
829 const char *buf, size_t count)
830{
831 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
832 port_mtu_attr);
833 struct mlx4_dev *mdev = info->dev;
834 struct mlx4_priv *priv = mlx4_priv(mdev);
835 int err, port, mtu, ibta_mtu = -1;
836
837 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
838 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
839 return -EINVAL;
840 }
841
842 err = sscanf(buf, "%d", &mtu);
843 if (err > 0)
844 ibta_mtu = int_to_ibta_mtu(mtu);
845
846 if (err <= 0 || ibta_mtu < 0) {
847 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
848 return -EINVAL;
849 }
850
851 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
852
853 mlx4_stop_sense(mdev);
854 mutex_lock(&priv->port_mutex);
855 mlx4_unregister_device(mdev);
856 for (port = 1; port <= mdev->caps.num_ports; port++) {
857 mlx4_CLOSE_PORT(mdev, port);
6634961c 858 err = mlx4_SET_PORT(mdev, port, -1);
096335b3
OG		 859 if (err) {
860 mlx4_err(mdev, "Failed to set port %d, "
861 "aborting\n", port);
862 goto err_set_port;
863 }
864 }
865 err = mlx4_register_device(mdev);
866err_set_port:
867 mutex_unlock(&priv->port_mutex);
868 mlx4_start_sense(mdev);
869 return err ? err : count;
870}
871
e8f9b2ed 872static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 873{
874 struct mlx4_priv *priv = mlx4_priv(dev);
875 int err;
876
877 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 878 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 879 if (!priv->fw.fw_icm) {
880 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
881 return -ENOMEM;
882 }
883
884 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
885 if (err) {
886 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
887 goto err_free;
888 }
889
890 err = mlx4_RUN_FW(dev);
891 if (err) {
892 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
893 goto err_unmap_fa;
894 }
895
896 return 0;
897
898err_unmap_fa:
899 mlx4_UNMAP_FA(dev);
900
901err_free:
5b0bf5e2 902 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 903 return err;
904}
905
e8f9b2ed
RD		 906static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
907 int cmpt_entry_sz)
225c7b1f
RD		 908{
909 struct mlx4_priv *priv = mlx4_priv(dev);
910 int err;
ab9c17a0 911 int num_eqs;
225c7b1f
RD		 912
913 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
914 cmpt_base +
915 ((u64) (MLX4_CMPT_TYPE_QP *
916 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
917 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 918 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
919 0, 0);
225c7b1f
RD		 920 if (err)
921 goto err;
922
923 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
924 cmpt_base +
925 ((u64) (MLX4_CMPT_TYPE_SRQ *
926 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
927 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 928 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 929 if (err)
930 goto err_qp;
931
932 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
933 cmpt_base +
934 ((u64) (MLX4_CMPT_TYPE_CQ *
935 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
936 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 937 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 938 if (err)
939 goto err_srq;
940
3fc929e2
MA		 941 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
942 dev->caps.num_eqs;
225c7b1f
RD		 943 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
944 cmpt_base +
945 ((u64) (MLX4_CMPT_TYPE_EQ *
946 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 947 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 948 if (err)
949 goto err_cq;
950
951 return 0;
952
953err_cq:
954 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
955
956err_srq:
957 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
958
959err_qp:
960 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
961
962err:
963 return err;
964}
965
3d73c288
RD		 966static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
967 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 968{
969 struct mlx4_priv *priv = mlx4_priv(dev);
970 u64 aux_pages;
ab9c17a0 971 int num_eqs;
225c7b1f
RD		 972 int err;
973
974 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
975 if (err) {
976 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
977 return err;
978 }
979
980 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
981 (unsigned long long) icm_size >> 10,
982 (unsigned long long) aux_pages << 2);
983
984 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 985 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 986 if (!priv->fw.aux_icm) {
987 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
988 return -ENOMEM;
989 }
990
991 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
992 if (err) {
993 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
994 goto err_free_aux;
995 }
996
997 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
998 if (err) {
999 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1000 goto err_unmap_aux;
1001 }
1002
ab9c17a0 1003
3fc929e2
MA		 1004 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1005 dev->caps.num_eqs;
fa0681d2
RD		 1006 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1007 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1008 num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1009 if (err) {
1010 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1011 goto err_unmap_cmpt;
1012 }
1013
d7bb58fb
JM		 1014 /*
1015 * Reserved MTT entries must be aligned up to a cacheline
1016 * boundary, since the FW will write to them, while the driver
1017 * writes to all other MTT entries. (The variable
1018 * dev->caps.mtt_entry_sz below is really the MTT segment
1019 * size, not the raw entry size)
1020 */
1021 dev->caps.reserved_mtts =
1022 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1023 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1024
225c7b1f
RD		 1025 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1026 init_hca->mtt_base,
1027 dev->caps.mtt_entry_sz,
2b8fb286 1028 dev->caps.num_mtts,
5b0bf5e2 1029 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 1030 if (err) {
1031 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1032 goto err_unmap_eq;
1033 }
1034
1035 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1036 init_hca->dmpt_base,
1037 dev_cap->dmpt_entry_sz,
1038 dev->caps.num_mpts,
5b0bf5e2 1039 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 1040 if (err) {
1041 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1042 goto err_unmap_mtt;
1043 }
1044
1045 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1046 init_hca->qpc_base,
1047 dev_cap->qpc_entry_sz,
1048 dev->caps.num_qps,
93fc9e1b
YP		 1049 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1050 0, 0);
225c7b1f
RD		 1051 if (err) {
1052 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1053 goto err_unmap_dmpt;
1054 }
1055
1056 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1057 init_hca->auxc_base,
1058 dev_cap->aux_entry_sz,
1059 dev->caps.num_qps,
93fc9e1b
YP		 1060 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1061 0, 0);
225c7b1f
RD		 1062 if (err) {
1063 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1064 goto err_unmap_qp;
1065 }
1066
1067 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1068 init_hca->altc_base,
1069 dev_cap->altc_entry_sz,
1070 dev->caps.num_qps,
93fc9e1b
YP		 1071 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1072 0, 0);
225c7b1f
RD		 1073 if (err) {
1074 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1075 goto err_unmap_auxc;
1076 }
1077
1078 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1079 init_hca->rdmarc_base,
1080 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1081 dev->caps.num_qps,
93fc9e1b
YP		 1082 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1083 0, 0);
225c7b1f
RD		 1084 if (err) {
1085 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1086 goto err_unmap_altc;
1087 }
1088
1089 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1090 init_hca->cqc_base,
1091 dev_cap->cqc_entry_sz,
1092 dev->caps.num_cqs,
5b0bf5e2 1093 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1094 if (err) {
1095 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1096 goto err_unmap_rdmarc;
1097 }
1098
1099 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1100 init_hca->srqc_base,
1101 dev_cap->srq_entry_sz,
1102 dev->caps.num_srqs,
5b0bf5e2 1103 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1104 if (err) {
1105 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1106 goto err_unmap_cq;
1107 }
1108
1109 /*
0ff1fb65
HHZ		 1110 * For flow steering device managed mode it is required to use
1111 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1112 * required, but for simplicity just map the whole multicast
1113 * group table now. The table isn't very big and it's a lot
1114 * easier than trying to track ref counts.
225c7b1f
RD		 1115 */
1116 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1117 init_hca->mc_base,
1118 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1119 dev->caps.num_mgms + dev->caps.num_amgms,
1120 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1121 0, 0);
225c7b1f
RD		 1122 if (err) {
1123 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1124 goto err_unmap_srq;
1125 }
1126
1127 return 0;
1128
1129err_unmap_srq:
1130 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1131
1132err_unmap_cq:
1133 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1134
1135err_unmap_rdmarc:
1136 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1137
1138err_unmap_altc:
1139 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1140
1141err_unmap_auxc:
1142 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1143
1144err_unmap_qp:
1145 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1146
1147err_unmap_dmpt:
1148 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1149
1150err_unmap_mtt:
1151 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1152
1153err_unmap_eq:
fa0681d2 1154 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1155
1156err_unmap_cmpt:
1157 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1158 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1159 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1160 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1161
1162err_unmap_aux:
1163 mlx4_UNMAP_ICM_AUX(dev);
1164
1165err_free_aux:
5b0bf5e2 1166 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1167
1168 return err;
1169}
1170
1171static void mlx4_free_icms(struct mlx4_dev *dev)
1172{
1173 struct mlx4_priv *priv = mlx4_priv(dev);
1174
1175 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1176 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1177 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1178 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1179 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1180 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1181 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1182 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1183 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1184 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1185 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1186 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1187 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1188 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1189
1190 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1191 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1192}
1193
ab9c17a0
JM		 1194static void mlx4_slave_exit(struct mlx4_dev *dev)
1195{
1196 struct mlx4_priv *priv = mlx4_priv(dev);
1197
f3d4c89e 1198 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1199 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1200 mlx4_warn(dev, "Failed to close slave function.\n");
f3d4c89e 1201 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1202}
1203
c1b43dca
EC		 1204static int map_bf_area(struct mlx4_dev *dev)
1205{
1206 struct mlx4_priv *priv = mlx4_priv(dev);
1207 resource_size_t bf_start;
1208 resource_size_t bf_len;
1209 int err = 0;
1210
3d747473
JM		 1211 if (!dev->caps.bf_reg_size)
1212 return -ENXIO;
1213
ab9c17a0
JM		 1214 bf_start = pci_resource_start(dev->pdev, 2) +
1215 (dev->caps.num_uars << PAGE_SHIFT);
1216 bf_len = pci_resource_len(dev->pdev, 2) -
1217 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1218 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1219 if (!priv->bf_mapping)
1220 err = -ENOMEM;
1221
1222 return err;
1223}
1224
1225static void unmap_bf_area(struct mlx4_dev *dev)
1226{
1227 if (mlx4_priv(dev)->bf_mapping)
1228 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1229}
1230
ddd8a6c1
EE		 1231static int map_internal_clock(struct mlx4_dev *dev)
1232{
1233 struct mlx4_priv *priv = mlx4_priv(dev);
1234
1235 priv->clock_mapping =
1236 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1237 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1238
1239 if (!priv->clock_mapping)
1240 return -ENOMEM;
1241
1242 return 0;
1243}
1244
1245static void unmap_internal_clock(struct mlx4_dev *dev)
1246{
1247 struct mlx4_priv *priv = mlx4_priv(dev);
1248
1249 if (priv->clock_mapping)
1250 iounmap(priv->clock_mapping);
1251}
1252
225c7b1f
RD		 1253static void mlx4_close_hca(struct mlx4_dev *dev)
1254{
ddd8a6c1 1255 unmap_internal_clock(dev);
c1b43dca 1256 unmap_bf_area(dev);
ab9c17a0
JM		 1257 if (mlx4_is_slave(dev))
1258 mlx4_slave_exit(dev);
1259 else {
1260 mlx4_CLOSE_HCA(dev, 0);
1261 mlx4_free_icms(dev);
1262 mlx4_UNMAP_FA(dev);
1263 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1264 }
1265}
1266
1267static int mlx4_init_slave(struct mlx4_dev *dev)
1268{
1269 struct mlx4_priv *priv = mlx4_priv(dev);
1270 u64 dma = (u64) priv->mfunc.vhcr_dma;
1271 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1272 int ret_from_reset = 0;
1273 u32 slave_read;
1274 u32 cmd_channel_ver;
1275
f3d4c89e 1276 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1277 priv->cmd.max_cmds = 1;
1278 mlx4_warn(dev, "Sending reset\n");
1279 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1280 MLX4_COMM_TIME);
1281 /* if we are in the middle of flr the slave will try
1282 * NUM_OF_RESET_RETRIES times before leaving.*/
1283 if (ret_from_reset) {
1284 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1285 msleep(SLEEP_TIME_IN_RESET);
1286 while (ret_from_reset && num_of_reset_retries) {
1287 mlx4_warn(dev, "slave is currently in the"
1288 "middle of FLR. retrying..."
1289 "(try num:%d)\n",
1290 (NUM_OF_RESET_RETRIES -
1291 num_of_reset_retries + 1));
1292 ret_from_reset =
1293 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1294 0, MLX4_COMM_TIME);
1295 num_of_reset_retries = num_of_reset_retries - 1;
1296 }
1297 } else
1298 goto err;
1299 }
1300
1301 /* check the driver version - the slave I/F revision
1302 * must match the master's */
1303 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1304 cmd_channel_ver = mlx4_comm_get_version();
1305
1306 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1307 MLX4_COMM_GET_IF_REV(slave_read)) {
1308 mlx4_err(dev, "slave driver version is not supported"
1309 " by the master\n");
1310 goto err;
1311 }
1312
1313 mlx4_warn(dev, "Sending vhcr0\n");
1314 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1315 MLX4_COMM_TIME))
1316 goto err;
1317 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1318 MLX4_COMM_TIME))
1319 goto err;
1320 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1321 MLX4_COMM_TIME))
1322 goto err;
1323 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1324 goto err;
f3d4c89e
RD		 1325
1326 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1327 return 0;
1328
1329err:
1330 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1331 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1332 return -EIO;
225c7b1f
RD		 1333}
1334
6634961c
JM		 1335static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1336{
1337 int i;
1338
1339 for (i = 1; i <= dev->caps.num_ports; i++) {
1340 dev->caps.gid_table_len[i] = 1;
1341 dev->caps.pkey_table_len[i] =
1342 dev->phys_caps.pkey_phys_table_len[i] - 1;
1343 }
1344}
1345
3c439b55
JM		 1346static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1347{
1348 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1349
1350 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1351 i++) {
1352 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1353 break;
1354 }
1355
1356 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1357}
1358
7b8157be
JM		 1359static void choose_steering_mode(struct mlx4_dev *dev,
1360 struct mlx4_dev_cap *dev_cap)
1361{
3c439b55
JM		 1362 if (mlx4_log_num_mgm_entry_size == -1 &&
1363 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1364 (!mlx4_is_mfunc(dev) ||
3c439b55
JM		 1365 (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) &&
1366 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1367 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1368 dev->oper_log_mgm_entry_size =
1369 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1370 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1371 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1372 dev->caps.fs_log_max_ucast_qp_range_size =
1373 dev_cap->fs_log_max_ucast_qp_range_size;
1374 } else {
1375 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1376 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1377 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1378 else {
1379 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1380
1381 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1382 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1383 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1384 "set to use B0 steering. Falling back to A0 steering mode.\n");
1385 }
3c439b55
JM		 1386 dev->oper_log_mgm_entry_size =
1387 mlx4_log_num_mgm_entry_size > 0 ?
1388 mlx4_log_num_mgm_entry_size :
1389 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1390 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1391 }
3c439b55
JM		 1392 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1393 "modparam log_num_mgm_entry_size = %d\n",
1394 mlx4_steering_mode_str(dev->caps.steering_mode),
1395 dev->oper_log_mgm_entry_size,
1396 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1397}
1398
3d73c288 1399static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1400{
1401 struct mlx4_priv *priv = mlx4_priv(dev);
1402 struct mlx4_adapter adapter;
1403 struct mlx4_dev_cap dev_cap;
2d928651 1404 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1405 struct mlx4_profile profile;
1406 struct mlx4_init_hca_param init_hca;
1407 u64 icm_size;
1408 int err;
1409
ab9c17a0
JM		 1410 if (!mlx4_is_slave(dev)) {
1411 err = mlx4_QUERY_FW(dev);
1412 if (err) {
1413 if (err == -EACCES)
1414 mlx4_info(dev, "non-primary physical function, skipping.\n");
1415 else
1416 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
bef772eb 1417 return err;
ab9c17a0 1418 }
225c7b1f 1419
ab9c17a0
JM		 1420 err = mlx4_load_fw(dev);
1421 if (err) {
1422 mlx4_err(dev, "Failed to start FW, aborting.\n");
bef772eb 1423 return err;
ab9c17a0 1424 }
225c7b1f 1425
ab9c17a0
JM		 1426 mlx4_cfg.log_pg_sz_m = 1;
1427 mlx4_cfg.log_pg_sz = 0;
1428 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1429 if (err)
1430 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1431
ab9c17a0
JM		 1432 err = mlx4_dev_cap(dev, &dev_cap);
1433 if (err) {
1434 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1435 goto err_stop_fw;
1436 }
225c7b1f 1437
7b8157be
JM		 1438 choose_steering_mode(dev, &dev_cap);
1439
6634961c
JM		 1440 if (mlx4_is_master(dev))
1441 mlx4_parav_master_pf_caps(dev);
1442
ab9c17a0 1443 profile = default_profile;
0ff1fb65
HHZ		 1444 if (dev->caps.steering_mode ==
1445 MLX4_STEERING_MODE_DEVICE_MANAGED)
1446 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1447
ab9c17a0
JM		 1448 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1449 &init_hca);
1450 if ((long long) icm_size < 0) {
1451 err = icm_size;
1452 goto err_stop_fw;
1453 }
225c7b1f 1454
a5bbe892
EC		 1455 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1456
ab9c17a0
JM		 1457 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1458 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1459 init_hca.mw_enabled = 0;
1460 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1461 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1462 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1463
ab9c17a0
JM		 1464 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1465 if (err)
1466 goto err_stop_fw;
225c7b1f 1467
ab9c17a0
JM		 1468 err = mlx4_INIT_HCA(dev, &init_hca);
1469 if (err) {
1470 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1471 goto err_free_icm;
1472 }
ddd8a6c1
EE		 1473 /*
1474 * If TS is supported by FW
1475 * read HCA frequency by QUERY_HCA command
1476 */
1477 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1478 memset(&init_hca, 0, sizeof(init_hca));
1479 err = mlx4_QUERY_HCA(dev, &init_hca);
1480 if (err) {
1481 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1482 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1483 } else {
1484 dev->caps.hca_core_clock =
1485 init_hca.hca_core_clock;
1486 }
1487
1488 /* In case we got HCA frequency 0 - disable timestamping
1489 * to avoid dividing by zero
1490 */
1491 if (!dev->caps.hca_core_clock) {
1492 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1493 mlx4_err(dev,
1494 "HCA frequency is 0. Timestamping is not supported.");
1495 } else if (map_internal_clock(dev)) {
1496 /*
1497 * Map internal clock,
1498 * in case of failure disable timestamping
1499 */
1500 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1501 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1502 }
1503 }
ab9c17a0
JM		 1504 } else {
1505 err = mlx4_init_slave(dev);
1506 if (err) {
1507 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1508 return err;
ab9c17a0 1509 }
225c7b1f 1510
ab9c17a0
JM		 1511 err = mlx4_slave_cap(dev);
1512 if (err) {
1513 mlx4_err(dev, "Failed to obtain slave caps\n");
1514 goto err_close;
1515 }
225c7b1f
RD		 1516 }
1517
ab9c17a0
JM		 1518 if (map_bf_area(dev))
1519 mlx4_dbg(dev, "Failed to map blue flame area\n");
1520
1521 /*Only the master set the ports, all the rest got it from it.*/
1522 if (!mlx4_is_slave(dev))
1523 mlx4_set_port_mask(dev);
1524
225c7b1f
RD		 1525 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1526 if (err) {
1527 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
bef772eb 1528 goto unmap_bf;
225c7b1f
RD		 1529 }
1530
1531 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1532 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1533
1534 return 0;
1535
bef772eb 1536unmap_bf:
ddd8a6c1 1537 unmap_internal_clock(dev);
bef772eb
AY		 1538 unmap_bf_area(dev);
1539
225c7b1f 1540err_close:
41929ed2
DB		 1541 if (mlx4_is_slave(dev))
1542 mlx4_slave_exit(dev);
1543 else
1544 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 1545
1546err_free_icm:
ab9c17a0
JM		 1547 if (!mlx4_is_slave(dev))
1548 mlx4_free_icms(dev);
225c7b1f
RD		 1549
1550err_stop_fw:
ab9c17a0
JM		 1551 if (!mlx4_is_slave(dev)) {
1552 mlx4_UNMAP_FA(dev);
1553 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1554 }
225c7b1f
RD		 1555 return err;
1556}
1557
f2a3f6a3
OG		 1558static int mlx4_init_counters_table(struct mlx4_dev *dev)
1559{
1560 struct mlx4_priv *priv = mlx4_priv(dev);
1561 int nent;
1562
1563 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1564 return -ENOENT;
1565
1566 nent = dev->caps.max_counters;
1567 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1568}
1569
1570static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1571{
1572 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1573}
1574
ba062d52 1575int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1576{
1577 struct mlx4_priv *priv = mlx4_priv(dev);
1578
1579 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1580 return -ENOENT;
1581
1582 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1583 if (*idx == -1)
1584 return -ENOMEM;
1585
1586 return 0;
1587}
ba062d52
JM		 1588
1589int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1590{
1591 u64 out_param;
1592 int err;
1593
1594 if (mlx4_is_mfunc(dev)) {
1595 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1596 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1597 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1598 if (!err)
1599 *idx = get_param_l(&out_param);
1600
1601 return err;
1602 }
1603 return __mlx4_counter_alloc(dev, idx);
1604}
f2a3f6a3
OG		 1605EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1606
ba062d52 1607void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3
OG		 1608{
1609 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1610 return;
1611}
ba062d52
JM		 1612
1613void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1614{
e7dbeba8 1615 u64 in_param = 0;
ba062d52
JM		 1616
1617 if (mlx4_is_mfunc(dev)) {
1618 set_param_l(&in_param, idx);
1619 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1620 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1621 MLX4_CMD_WRAPPED);
1622 return;
1623 }
1624 __mlx4_counter_free(dev, idx);
1625}
f2a3f6a3
OG		 1626EXPORT_SYMBOL_GPL(mlx4_counter_free);
1627
3d73c288 1628static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1629{
1630 struct mlx4_priv *priv = mlx4_priv(dev);
1631 int err;
7ff93f8b 1632 int port;
9a5aa622 1633 __be32 ib_port_default_caps;
225c7b1f 1634
225c7b1f
RD		 1635 err = mlx4_init_uar_table(dev);
1636 if (err) {
1637 mlx4_err(dev, "Failed to initialize "
1638 "user access region table, aborting.\n");
1639 return err;
1640 }
1641
1642 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1643 if (err) {
1644 mlx4_err(dev, "Failed to allocate driver access region, "
1645 "aborting.\n");
1646 goto err_uar_table_free;
1647 }
1648
4979d18f 1649 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f
RD		 1650 if (!priv->kar) {
1651 mlx4_err(dev, "Couldn't map kernel access region, "
1652 "aborting.\n");
1653 err = -ENOMEM;
1654 goto err_uar_free;
1655 }
1656
1657 err = mlx4_init_pd_table(dev);
1658 if (err) {
1659 mlx4_err(dev, "Failed to initialize "
1660 "protection domain table, aborting.\n");
1661 goto err_kar_unmap;
1662 }
1663
012a8ff5
SH		 1664 err = mlx4_init_xrcd_table(dev);
1665 if (err) {
1666 mlx4_err(dev, "Failed to initialize "
1667 "reliable connection domain table, aborting.\n");
1668 goto err_pd_table_free;
1669 }
1670
225c7b1f
RD		 1671 err = mlx4_init_mr_table(dev);
1672 if (err) {
1673 mlx4_err(dev, "Failed to initialize "
1674 "memory region table, aborting.\n");
012a8ff5 1675 goto err_xrcd_table_free;
225c7b1f
RD		 1676 }
1677
225c7b1f
RD		 1678 err = mlx4_init_eq_table(dev);
1679 if (err) {
1680 mlx4_err(dev, "Failed to initialize "
1681 "event queue table, aborting.\n");
ee49bd93 1682 goto err_mr_table_free;
225c7b1f
RD		 1683 }
1684
1685 err = mlx4_cmd_use_events(dev);
1686 if (err) {
1687 mlx4_err(dev, "Failed to switch to event-driven "
1688 "firmware commands, aborting.\n");
1689 goto err_eq_table_free;
1690 }
1691
1692 err = mlx4_NOP(dev);
1693 if (err) {
08fb1055
MT		 1694 if (dev->flags & MLX4_FLAG_MSI_X) {
1695 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1696 "interrupt IRQ %d).\n",
b8dd786f 1697 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 1698 mlx4_warn(dev, "Trying again without MSI-X.\n");
1699 } else {
1700 mlx4_err(dev, "NOP command failed to generate interrupt "
1701 "(IRQ %d), aborting.\n",
b8dd786f 1702 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1703 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1704 }
225c7b1f
RD		 1705
1706 goto err_cmd_poll;
1707 }
1708
1709 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1710
1711 err = mlx4_init_cq_table(dev);
1712 if (err) {
1713 mlx4_err(dev, "Failed to initialize "
1714 "completion queue table, aborting.\n");
1715 goto err_cmd_poll;
1716 }
1717
1718 err = mlx4_init_srq_table(dev);
1719 if (err) {
1720 mlx4_err(dev, "Failed to initialize "
1721 "shared receive queue table, aborting.\n");
1722 goto err_cq_table_free;
1723 }
1724
1725 err = mlx4_init_qp_table(dev);
1726 if (err) {
1727 mlx4_err(dev, "Failed to initialize "
1728 "queue pair table, aborting.\n");
1729 goto err_srq_table_free;
1730 }
1731
ab9c17a0
JM		 1732 if (!mlx4_is_slave(dev)) {
1733 err = mlx4_init_mcg_table(dev);
1734 if (err) {
1735 mlx4_err(dev, "Failed to initialize "
1736 "multicast group table, aborting.\n");
1737 goto err_qp_table_free;
1738 }
225c7b1f
RD		 1739 }
1740
f2a3f6a3
OG		 1741 err = mlx4_init_counters_table(dev);
1742 if (err && err != -ENOENT) {
1743 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
ab9c17a0 1744 goto err_mcg_table_free;
f2a3f6a3
OG		 1745 }
1746
ab9c17a0
JM		 1747 if (!mlx4_is_slave(dev)) {
1748 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1749 ib_port_default_caps = 0;
1750 err = mlx4_get_port_ib_caps(dev, port,
1751 &ib_port_default_caps);
1752 if (err)
1753 mlx4_warn(dev, "failed to get port %d default "
1754 "ib capabilities (%d). Continuing "
1755 "with caps = 0\n", port, err);
1756 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1757
2aca1172
JM		 1758 /* initialize per-slave default ib port capabilities */
1759 if (mlx4_is_master(dev)) {
1760 int i;
1761 for (i = 0; i < dev->num_slaves; i++) {
1762 if (i == mlx4_master_func_num(dev))
1763 continue;
1764 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1765 ib_port_default_caps;
1766 }
1767 }
1768
096335b3
OG		 1769 if (mlx4_is_mfunc(dev))
1770 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1771 else
1772 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 1773
6634961c
JM		 1774 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1775 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 1776 if (err) {
1777 mlx4_err(dev, "Failed to set port %d, aborting\n",
1778 port);
1779 goto err_counters_table_free;
1780 }
7ff93f8b
YP		 1781 }
1782 }
1783
225c7b1f
RD		 1784 return 0;
1785
f2a3f6a3
OG		 1786err_counters_table_free:
1787 mlx4_cleanup_counters_table(dev);
1788
ab9c17a0
JM		 1789err_mcg_table_free:
1790 mlx4_cleanup_mcg_table(dev);
1791
225c7b1f
RD		 1792err_qp_table_free:
1793 mlx4_cleanup_qp_table(dev);
1794
1795err_srq_table_free:
1796 mlx4_cleanup_srq_table(dev);
1797
1798err_cq_table_free:
1799 mlx4_cleanup_cq_table(dev);
1800
1801err_cmd_poll:
1802 mlx4_cmd_use_polling(dev);
1803
1804err_eq_table_free:
1805 mlx4_cleanup_eq_table(dev);
1806
ee49bd93 1807err_mr_table_free:
225c7b1f
RD		 1808 mlx4_cleanup_mr_table(dev);
1809
012a8ff5
SH		 1810err_xrcd_table_free:
1811 mlx4_cleanup_xrcd_table(dev);
1812
225c7b1f
RD		 1813err_pd_table_free:
1814 mlx4_cleanup_pd_table(dev);
1815
1816err_kar_unmap:
1817 iounmap(priv->kar);
1818
1819err_uar_free:
1820 mlx4_uar_free(dev, &priv->driver_uar);
1821
1822err_uar_table_free:
1823 mlx4_cleanup_uar_table(dev);
1824 return err;
1825}
1826
e8f9b2ed 1827static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 1828{
1829 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 1830 struct msix_entry *entries;
0b7ca5a9 1831 int nreq = min_t(int, dev->caps.num_ports *
90b1ebe7
YM		 1832 min_t(int, netif_get_num_default_rss_queues() + 1,
1833 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 1834 int err;
1835 int i;
1836
1837 if (msi_x) {
ca4c7b35
OG		 1838 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1839 nreq);
ab9c17a0 1840
b8dd786f
YP		 1841 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1842 if (!entries)
1843 goto no_msi;
1844
1845 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1846 entries[i].entry = i;
1847
b8dd786f
YP		 1848 retry:
1849 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 1850 if (err) {
b8dd786f
YP		 1851 /* Try again if at least 2 vectors are available */
1852 if (err > 1) {
1853 mlx4_info(dev, "Requested %d vectors, "
1854 "but only %d MSI-X vectors available, "
1855 "trying again\n", nreq, err);
1856 nreq = err;
1857 goto retry;
1858 }
5bf0da7d 1859 kfree(entries);
225c7b1f
RD		 1860 goto no_msi;
1861 }
1862
0b7ca5a9
YP		 1863 if (nreq <
1864 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1865 /*Working in legacy mode , all EQ's shared*/
1866 dev->caps.comp_pool = 0;
1867 dev->caps.num_comp_vectors = nreq - 1;
1868 } else {
1869 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1870 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1871 }
b8dd786f 1872 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1873 priv->eq_table.eq[i].irq = entries[i].vector;
1874
1875 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 1876
1877 kfree(entries);
225c7b1f
RD		 1878 return;
1879 }
1880
1881no_msi:
b8dd786f 1882 dev->caps.num_comp_vectors = 1;
0b7ca5a9 1883 dev->caps.comp_pool = 0;
b8dd786f
YP		 1884
1885 for (i = 0; i < 2; ++i)
225c7b1f
RD		 1886 priv->eq_table.eq[i].irq = dev->pdev->irq;
1887}
1888
7ff93f8b 1889static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 1890{
1891 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 1892 int err = 0;
2a2336f8
YP		 1893
1894 info->dev = dev;
1895 info->port = port;
ab9c17a0 1896 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1897 mlx4_init_mac_table(dev, &info->mac_table);
1898 mlx4_init_vlan_table(dev, &info->vlan_table);
16a10ffd 1899 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 1900 }
7ff93f8b
YP		 1901
1902 sprintf(info->dev_name, "mlx4_port%d", port);
1903 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 1904 if (mlx4_is_mfunc(dev))
1905 info->port_attr.attr.mode = S_IRUGO;
1906 else {
1907 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1908 info->port_attr.store = set_port_type;
1909 }
7ff93f8b 1910 info->port_attr.show = show_port_type;
3691c964 1911 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 1912
1913 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1914 if (err) {
1915 mlx4_err(dev, "Failed to create file for port %d\n", port);
1916 info->port = -1;
1917 }
1918
096335b3
OG		 1919 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1920 info->port_mtu_attr.attr.name = info->dev_mtu_name;
1921 if (mlx4_is_mfunc(dev))
1922 info->port_mtu_attr.attr.mode = S_IRUGO;
1923 else {
1924 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1925 info->port_mtu_attr.store = set_port_ib_mtu;
1926 }
1927 info->port_mtu_attr.show = show_port_ib_mtu;
1928 sysfs_attr_init(&info->port_mtu_attr.attr);
1929
1930 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1931 if (err) {
1932 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1933 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1934 info->port = -1;
1935 }
1936
7ff93f8b
YP		 1937 return err;
1938}
1939
1940static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1941{
1942 if (info->port < 0)
1943 return;
1944
1945 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 1946 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 1947}
1948
b12d93d6
YP		 1949static int mlx4_init_steering(struct mlx4_dev *dev)
1950{
1951 struct mlx4_priv *priv = mlx4_priv(dev);
1952 int num_entries = dev->caps.num_ports;
1953 int i, j;
1954
1955 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1956 if (!priv->steer)
1957 return -ENOMEM;
1958
45b51365 1959 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 1960 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1961 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1962 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1963 }
b12d93d6
YP		 1964 return 0;
1965}
1966
1967static void mlx4_clear_steering(struct mlx4_dev *dev)
1968{
1969 struct mlx4_priv *priv = mlx4_priv(dev);
1970 struct mlx4_steer_index *entry, *tmp_entry;
1971 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1972 int num_entries = dev->caps.num_ports;
1973 int i, j;
1974
1975 for (i = 0; i < num_entries; i++) {
1976 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1977 list_for_each_entry_safe(pqp, tmp_pqp,
1978 &priv->steer[i].promisc_qps[j],
1979 list) {
1980 list_del(&pqp->list);
1981 kfree(pqp);
1982 }
1983 list_for_each_entry_safe(entry, tmp_entry,
1984 &priv->steer[i].steer_entries[j],
1985 list) {
1986 list_del(&entry->list);
1987 list_for_each_entry_safe(pqp, tmp_pqp,
1988 &entry->duplicates,
1989 list) {
1990 list_del(&pqp->list);
1991 kfree(pqp);
1992 }
1993 kfree(entry);
1994 }
1995 }
1996 }
1997 kfree(priv->steer);
1998}
1999
ab9c17a0
JM		 2000static int extended_func_num(struct pci_dev *pdev)
2001{
2002 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2003}
2004
2005#define MLX4_OWNER_BASE 0x8069c
2006#define MLX4_OWNER_SIZE 4
2007
2008static int mlx4_get_ownership(struct mlx4_dev *dev)
2009{
2010 void __iomem *owner;
2011 u32 ret;
2012
57dbf29a
KSS		 2013 if (pci_channel_offline(dev->pdev))
2014 return -EIO;
2015
ab9c17a0
JM		 2016 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2017 MLX4_OWNER_SIZE);
2018 if (!owner) {
2019 mlx4_err(dev, "Failed to obtain ownership bit\n");
2020 return -ENOMEM;
2021 }
2022
2023 ret = readl(owner);
2024 iounmap(owner);
2025 return (int) !!ret;
2026}
2027
2028static void mlx4_free_ownership(struct mlx4_dev *dev)
2029{
2030 void __iomem *owner;
2031
57dbf29a
KSS		 2032 if (pci_channel_offline(dev->pdev))
2033 return;
2034
ab9c17a0
JM		 2035 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2036 MLX4_OWNER_SIZE);
2037 if (!owner) {
2038 mlx4_err(dev, "Failed to obtain ownership bit\n");
2039 return;
2040 }
2041 writel(0, owner);
2042 msleep(1000);
2043 iounmap(owner);
2044}
2045
839f1243 2046static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
225c7b1f 2047{
225c7b1f
RD		 2048 struct mlx4_priv *priv;
2049 struct mlx4_dev *dev;
2050 int err;
2a2336f8 2051 int port;
225c7b1f 2052
0a645e80 2053 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 2054
2055 err = pci_enable_device(pdev);
2056 if (err) {
2057 dev_err(&pdev->dev, "Cannot enable PCI device, "
2058 "aborting.\n");
2059 return err;
2060 }
ab9c17a0
JM		 2061 if (num_vfs > MLX4_MAX_NUM_VF) {
2062 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
2063 num_vfs, MLX4_MAX_NUM_VF);
2064 return -EINVAL;
2065 }
225c7b1f 2066 /*
ab9c17a0 2067 * Check for BARs.
225c7b1f 2068 */
839f1243 2069 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
ab9c17a0
JM		 2070 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2071 dev_err(&pdev->dev, "Missing DCS, aborting."
839f1243
RD		 2072 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2073 pci_dev_data, pci_resource_flags(pdev, 0));
225c7b1f
RD		 2074 err = -ENODEV;
2075 goto err_disable_pdev;
2076 }
2077 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2078 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2079 err = -ENODEV;
2080 goto err_disable_pdev;
2081 }
2082
a01df0fe 2083 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 2084 if (err) {
a01df0fe 2085 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 2086 goto err_disable_pdev;
2087 }
2088
225c7b1f
RD		 2089 pci_set_master(pdev);
2090
6a35528a 2091 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 2092 if (err) {
2093 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 2094 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 2095 if (err) {
2096 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 2097 goto err_release_regions;
225c7b1f
RD		 2098 }
2099 }
6a35528a 2100 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 2101 if (err) {
2102 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2103 "consistent PCI DMA mask.\n");
284901a9 2104 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 2105 if (err) {
2106 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2107 "aborting.\n");
a01df0fe 2108 goto err_release_regions;
225c7b1f
RD		 2109 }
2110 }
2111
7f9e5c48
DD		 2112 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2113 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2114
b2adaca9 2115 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
225c7b1f 2116 if (!priv) {
225c7b1f 2117 err = -ENOMEM;
a01df0fe 2118 goto err_release_regions;
225c7b1f
RD		 2119 }
2120
2121 dev = &priv->dev;
2122 dev->pdev = pdev;
b581401e
RD		 2123 INIT_LIST_HEAD(&priv->ctx_list);
2124 spin_lock_init(&priv->ctx_lock);
225c7b1f 2125
7ff93f8b
YP		 2126 mutex_init(&priv->port_mutex);
2127
6296883c
YP		 2128 INIT_LIST_HEAD(&priv->pgdir_list);
2129 mutex_init(&priv->pgdir_mutex);
2130
c1b43dca
EC		 2131 INIT_LIST_HEAD(&priv->bf_list);
2132 mutex_init(&priv->bf_mutex);
2133
aca7a3ac 2134 dev->rev_id = pdev->revision;
ab9c17a0 2135 /* Detect if this device is a virtual function */
839f1243 2136 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2137 /* When acting as pf, we normally skip vfs unless explicitly
2138 * requested to probe them. */
2139 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2140 mlx4_warn(dev, "Skipping virtual function:%d\n",
2141 extended_func_num(pdev));
2142 err = -ENODEV;
2143 goto err_free_dev;
2144 }
2145 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2146 dev->flags |= MLX4_FLAG_SLAVE;
2147 } else {
2148 /* We reset the device and enable SRIOV only for physical
2149 * devices. Try to claim ownership on the device;
2150 * if already taken, skip -- do not allow multiple PFs */
2151 err = mlx4_get_ownership(dev);
2152 if (err) {
2153 if (err < 0)
2154 goto err_free_dev;
2155 else {
2156 mlx4_warn(dev, "Multiple PFs not yet supported."
2157 " Skipping PF.\n");
2158 err = -EINVAL;
2159 goto err_free_dev;
2160 }
2161 }
aca7a3ac 2162
ab9c17a0 2163 if (num_vfs) {
84b1f153 2164 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
ab9c17a0
JM		 2165 err = pci_enable_sriov(pdev, num_vfs);
2166 if (err) {
84b1f153
RD		 2167 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2168 err);
ab9c17a0
JM		 2169 err = 0;
2170 } else {
2171 mlx4_warn(dev, "Running in master mode\n");
2172 dev->flags |= MLX4_FLAG_SRIOV |
2173 MLX4_FLAG_MASTER;
2174 dev->num_vfs = num_vfs;
2175 }
2176 }
2177
2178 /*
2179 * Now reset the HCA before we touch the PCI capabilities or
2180 * attempt a firmware command, since a boot ROM may have left
2181 * the HCA in an undefined state.
2182 */
2183 err = mlx4_reset(dev);
2184 if (err) {
2185 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2186 goto err_rel_own;
2187 }
225c7b1f
RD		 2188 }
2189
ab9c17a0 2190slave_start:
521130d1
EE		 2191 err = mlx4_cmd_init(dev);
2192 if (err) {
225c7b1f 2193 mlx4_err(dev, "Failed to init command interface, aborting.\n");
ab9c17a0
JM		 2194 goto err_sriov;
2195 }
2196
2197 /* In slave functions, the communication channel must be initialized
2198 * before posting commands. Also, init num_slaves before calling
2199 * mlx4_init_hca */
2200 if (mlx4_is_mfunc(dev)) {
2201 if (mlx4_is_master(dev))
2202 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2203 else {
2204 dev->num_slaves = 0;
f356fcbe
JM		 2205 err = mlx4_multi_func_init(dev);
2206 if (err) {
ab9c17a0
JM		 2207 mlx4_err(dev, "Failed to init slave mfunc"
2208 " interface, aborting.\n");
2209 goto err_cmd;
2210 }
2211 }
225c7b1f
RD		 2212 }
2213
2214 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2215 if (err) {
2216 if (err == -EACCES) {
2217 /* Not primary Physical function
2218 * Running in slave mode */
2219 mlx4_cmd_cleanup(dev);
2220 dev->flags |= MLX4_FLAG_SLAVE;
2221 dev->flags &= ~MLX4_FLAG_MASTER;
2222 goto slave_start;
2223 } else
2224 goto err_mfunc;
2225 }
2226
2227 /* In master functions, the communication channel must be initialized
2228 * after obtaining its address from fw */
2229 if (mlx4_is_master(dev)) {
f356fcbe
JM		 2230 err = mlx4_multi_func_init(dev);
2231 if (err) {
ab9c17a0
JM		 2232 mlx4_err(dev, "Failed to init master mfunc"
2233 "interface, aborting.\n");
2234 goto err_close;
2235 }
2236 }
225c7b1f 2237
b8dd786f
YP		 2238 err = mlx4_alloc_eq_table(dev);
2239 if (err)
ab9c17a0 2240 goto err_master_mfunc;
b8dd786f 2241
0b7ca5a9 2242 priv->msix_ctl.pool_bm = 0;
730c41d5 2243 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2244
08fb1055 2245 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2246 if ((mlx4_is_mfunc(dev)) &&
2247 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2248 err = -ENOSYS;
ab9c17a0
JM		 2249 mlx4_err(dev, "INTx is not supported in multi-function mode."
2250 " aborting.\n");
b12d93d6 2251 goto err_free_eq;
ab9c17a0
JM		 2252 }
2253
2254 if (!mlx4_is_slave(dev)) {
2255 err = mlx4_init_steering(dev);
2256 if (err)
2257 goto err_free_eq;
2258 }
b12d93d6 2259
225c7b1f 2260 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2261 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2262 !mlx4_is_mfunc(dev)) {
08fb1055 2263 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2264 dev->caps.num_comp_vectors = 1;
2265 dev->caps.comp_pool = 0;
08fb1055
MT		 2266 pci_disable_msix(pdev);
2267 err = mlx4_setup_hca(dev);
2268 }
2269
225c7b1f 2270 if (err)
b12d93d6 2271 goto err_steer;
225c7b1f 2272
7ff93f8b
YP		 2273 for (port = 1; port <= dev->caps.num_ports; port++) {
2274 err = mlx4_init_port_info(dev, port);
2275 if (err)
2276 goto err_port;
2277 }
2a2336f8 2278
225c7b1f
RD		 2279 err = mlx4_register_device(dev);
2280 if (err)
7ff93f8b 2281 goto err_port;
225c7b1f 2282
27bf91d6
YP		 2283 mlx4_sense_init(dev);
2284 mlx4_start_sense(dev);
2285
839f1243 2286 priv->pci_dev_data = pci_dev_data;
225c7b1f
RD		 2287 pci_set_drvdata(pdev, dev);
2288
2289 return 0;
2290
7ff93f8b 2291err_port:
b4f77264 2292 for (--port; port >= 1; --port)
7ff93f8b
YP		 2293 mlx4_cleanup_port_info(&priv->port[port]);
2294
f2a3f6a3 2295 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2296 mlx4_cleanup_mcg_table(dev);
2297 mlx4_cleanup_qp_table(dev);
2298 mlx4_cleanup_srq_table(dev);
2299 mlx4_cleanup_cq_table(dev);
2300 mlx4_cmd_use_polling(dev);
2301 mlx4_cleanup_eq_table(dev);
225c7b1f 2302 mlx4_cleanup_mr_table(dev);
012a8ff5 2303 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2304 mlx4_cleanup_pd_table(dev);
2305 mlx4_cleanup_uar_table(dev);
2306
b12d93d6 2307err_steer:
ab9c17a0
JM		 2308 if (!mlx4_is_slave(dev))
2309 mlx4_clear_steering(dev);
b12d93d6 2310
b8dd786f
YP		 2311err_free_eq:
2312 mlx4_free_eq_table(dev);
2313
ab9c17a0
JM		 2314err_master_mfunc:
2315 if (mlx4_is_master(dev))
2316 mlx4_multi_func_cleanup(dev);
2317
225c7b1f 2318err_close:
08fb1055
MT		 2319 if (dev->flags & MLX4_FLAG_MSI_X)
2320 pci_disable_msix(pdev);
2321
225c7b1f
RD		 2322 mlx4_close_hca(dev);
2323
ab9c17a0
JM		 2324err_mfunc:
2325 if (mlx4_is_slave(dev))
2326 mlx4_multi_func_cleanup(dev);
2327
225c7b1f
RD		 2328err_cmd:
2329 mlx4_cmd_cleanup(dev);
2330
ab9c17a0 2331err_sriov:
681372a7 2332 if (dev->flags & MLX4_FLAG_SRIOV)
ab9c17a0
JM		 2333 pci_disable_sriov(pdev);
2334
2335err_rel_own:
2336 if (!mlx4_is_slave(dev))
2337 mlx4_free_ownership(dev);
2338
225c7b1f 2339err_free_dev:
225c7b1f
RD		 2340 kfree(priv);
2341
a01df0fe
RD		 2342err_release_regions:
2343 pci_release_regions(pdev);
225c7b1f
RD		 2344
2345err_disable_pdev:
2346 pci_disable_device(pdev);
2347 pci_set_drvdata(pdev, NULL);
2348 return err;
2349}
2350
1dd06ae8 2351static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 2352{
0a645e80 2353 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2354
839f1243 2355 return __mlx4_init_one(pdev, id->driver_data);
3d73c288
RD		 2356}
2357
2358static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 2359{
2360 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2361 struct mlx4_priv *priv = mlx4_priv(dev);
2362 int p;
2363
2364 if (dev) {
ab9c17a0
JM		 2365 /* in SRIOV it is not allowed to unload the pf's
2366 * driver while there are alive vf's */
2367 if (mlx4_is_master(dev)) {
2368 if (mlx4_how_many_lives_vf(dev))
2369 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2370 }
27bf91d6 2371 mlx4_stop_sense(dev);
225c7b1f
RD		 2372 mlx4_unregister_device(dev);
2373
7ff93f8b
YP		 2374 for (p = 1; p <= dev->caps.num_ports; p++) {
2375 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 2376 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 2377 }
225c7b1f 2378
b8924951
JM		 2379 if (mlx4_is_master(dev))
2380 mlx4_free_resource_tracker(dev,
2381 RES_TR_FREE_SLAVES_ONLY);
2382
f2a3f6a3 2383 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2384 mlx4_cleanup_mcg_table(dev);
2385 mlx4_cleanup_qp_table(dev);
2386 mlx4_cleanup_srq_table(dev);
2387 mlx4_cleanup_cq_table(dev);
2388 mlx4_cmd_use_polling(dev);
2389 mlx4_cleanup_eq_table(dev);
225c7b1f 2390 mlx4_cleanup_mr_table(dev);
012a8ff5 2391 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2392 mlx4_cleanup_pd_table(dev);
2393
ab9c17a0 2394 if (mlx4_is_master(dev))
b8924951
JM		 2395 mlx4_free_resource_tracker(dev,
2396 RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 2397
225c7b1f
RD		 2398 iounmap(priv->kar);
2399 mlx4_uar_free(dev, &priv->driver_uar);
2400 mlx4_cleanup_uar_table(dev);
ab9c17a0
JM		 2401 if (!mlx4_is_slave(dev))
2402 mlx4_clear_steering(dev);
b8dd786f 2403 mlx4_free_eq_table(dev);
ab9c17a0
JM		 2404 if (mlx4_is_master(dev))
2405 mlx4_multi_func_cleanup(dev);
225c7b1f 2406 mlx4_close_hca(dev);
ab9c17a0
JM		 2407 if (mlx4_is_slave(dev))
2408 mlx4_multi_func_cleanup(dev);
225c7b1f
RD		 2409 mlx4_cmd_cleanup(dev);
2410
2411 if (dev->flags & MLX4_FLAG_MSI_X)
2412 pci_disable_msix(pdev);
681372a7 2413 if (dev->flags & MLX4_FLAG_SRIOV) {
84b1f153 2414 mlx4_warn(dev, "Disabling SR-IOV\n");
ab9c17a0
JM		 2415 pci_disable_sriov(pdev);
2416 }
225c7b1f 2417
ab9c17a0
JM		 2418 if (!mlx4_is_slave(dev))
2419 mlx4_free_ownership(dev);
47605df9
JM		 2420
2421 kfree(dev->caps.qp0_tunnel);
2422 kfree(dev->caps.qp0_proxy);
2423 kfree(dev->caps.qp1_tunnel);
2424 kfree(dev->caps.qp1_proxy);
2425
225c7b1f 2426 kfree(priv);
a01df0fe 2427 pci_release_regions(pdev);
225c7b1f
RD		 2428 pci_disable_device(pdev);
2429 pci_set_drvdata(pdev, NULL);
2430 }
2431}
2432
ee49bd93
JM		 2433int mlx4_restart_one(struct pci_dev *pdev)
2434{
839f1243
RD		 2435 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2436 struct mlx4_priv *priv = mlx4_priv(dev);
2437 int pci_dev_data;
2438
2439 pci_dev_data = priv->pci_dev_data;
ee49bd93 2440 mlx4_remove_one(pdev);
839f1243 2441 return __mlx4_init_one(pdev, pci_dev_data);
ee49bd93
JM		 2442}
2443
a3aa1884 2444static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0 2445 /* MT25408 "Hermon" SDR */
ca3e57a5 2446 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2447 /* MT25408 "Hermon" DDR */
ca3e57a5 2448 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2449 /* MT25408 "Hermon" QDR */
ca3e57a5 2450 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2451 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 2452 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2453 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 2454 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2455 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 2456 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2457 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 2458 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2459 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 2460 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2461 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 2462 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2463 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 2464 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2465 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 2466 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2467 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 2468 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2469 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 2470 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2471 /* MT27500 Family [ConnectX-3] */
2472 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2473 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 2474 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2475 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2476 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2477 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2478 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2479 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2480 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2481 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2482 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2483 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2484 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2485 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2486 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2487 { 0, }
2488};
2489
2490MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2491
57dbf29a
KSS		 2492static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2493 pci_channel_state_t state)
2494{
2495 mlx4_remove_one(pdev);
2496
2497 return state == pci_channel_io_perm_failure ?
2498 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2499}
2500
2501static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2502{
839f1243 2503 int ret = __mlx4_init_one(pdev, 0);
57dbf29a
KSS		 2504
2505 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2506}
2507
3646f0e5 2508static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 2509 .error_detected = mlx4_pci_err_detected,
2510 .slot_reset = mlx4_pci_slot_reset,
2511};
2512
225c7b1f
RD		 2513static struct pci_driver mlx4_driver = {
2514 .name = DRV_NAME,
2515 .id_table = mlx4_pci_table,
2516 .probe = mlx4_init_one,
f57e6848 2517 .remove = mlx4_remove_one,
57dbf29a 2518 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 2519};
2520
7ff93f8b
YP		 2521static int __init mlx4_verify_params(void)
2522{
2523 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2524 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2525 return -1;
2526 }
2527
cb29688a
OG		 2528 if (log_num_vlan != 0)
2529 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2530 MLX4_LOG_NUM_VLANS);
7ff93f8b 2531
0498628f 2532 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2533 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2534 return -1;
2535 }
2536
ab9c17a0
JM		 2537 /* Check if module param for ports type has legal combination */
2538 if (port_type_array[0] == false && port_type_array[1] == true) {
2539 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2540 port_type_array[0] = true;
2541 }
2542
3c439b55
JM		 2543 if (mlx4_log_num_mgm_entry_size != -1 &&
2544 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2545 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2546 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2547 "in legal range (-1 or %d..%d)\n",
2548 mlx4_log_num_mgm_entry_size,
2549 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2550 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2551 return -1;
2552 }
2553
7ff93f8b
YP		 2554 return 0;
2555}
2556
225c7b1f
RD		 2557static int __init mlx4_init(void)
2558{
2559 int ret;
2560
7ff93f8b
YP		 2561 if (mlx4_verify_params())
2562 return -EINVAL;
2563
27bf91d6
YP		 2564 mlx4_catas_init();
2565
2566 mlx4_wq = create_singlethread_workqueue("mlx4");
2567 if (!mlx4_wq)
2568 return -ENOMEM;
ee49bd93 2569
225c7b1f
RD		 2570 ret = pci_register_driver(&mlx4_driver);
2571 return ret < 0 ? ret : 0;
2572}
2573
2574static void __exit mlx4_cleanup(void)
2575{
2576 pci_unregister_driver(&mlx4_driver);
27bf91d6 2577 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2578}
2579
2580module_init(mlx4_init);
2581module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)