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net/mlx4_core: Fixed memory leak and incorrect refcount in mlx4_load_one
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
dd41cc3b 80static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 81static int num_vfs_argc;
dd41cc3b
MB		 82module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 87static int probe_vfs_argc;
dd41cc3b
MB		 88module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
ab9c17a0 91
3c439b55 92int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 93module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
3c439b55 97 " 10 gives 248.range: 7 <="
0ff1fb65 98 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 99 " To activate device managed"
100 " flow steering when available, set to -1");
0ec2c0f8 101
be902ab1 102static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 103module_param(enable_64b_cqe_eqe, bool, 0444);
104MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 106
77507aa2 107#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
7d077cd3
MB		 108 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
109 MLX4_FUNC_CAP_DMFS_A0_STATIC)
ab9c17a0 110
f57e6848 111static char mlx4_version[] =
225c7b1f
RD		 112 DRV_NAME ": Mellanox ConnectX core driver v"
113 DRV_VERSION " (" DRV_RELDATE ")\n";
114
115static struct mlx4_profile default_profile = {
ab9c17a0 116 .num_qp = 1 << 18,
225c7b1f 117 .num_srq = 1 << 16,
c9f2ba5e 118 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 119 .num_cq = 1 << 16,
120 .num_mcg = 1 << 13,
ab9c17a0 121 .num_mpt = 1 << 19,
9fd7a1e1 122 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 123};
124
2599d858
AV		 125static struct mlx4_profile low_mem_profile = {
126 .num_qp = 1 << 17,
127 .num_srq = 1 << 6,
128 .rdmarc_per_qp = 1 << 4,
129 .num_cq = 1 << 8,
130 .num_mcg = 1 << 8,
131 .num_mpt = 1 << 9,
132 .num_mtt = 1 << 7,
133};
134
ab9c17a0 135static int log_num_mac = 7;
93fc9e1b
YP		 136module_param_named(log_num_mac, log_num_mac, int, 0444);
137MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
138
139static int log_num_vlan;
140module_param_named(log_num_vlan, log_num_vlan, int, 0444);
141MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 142/* Log2 max number of VLANs per ETH port (0-7) */
143#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 144#define MLX4_MIN_LOG_NUM_VLANS 0
145#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 146
eb939922 147static bool use_prio;
93fc9e1b 148module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 149MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 150
2b8fb286 151int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 152module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 153MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 154
8d0fc7b6 155static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 156static int arr_argc = 2;
157module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 158MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
159 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 160
161struct mlx4_port_config {
162 struct list_head list;
163 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
164 struct pci_dev *pdev;
165};
166
97989356
AV		 167static atomic_t pf_loading = ATOMIC_INIT(0);
168
27bf91d6
YP		 169int mlx4_check_port_params(struct mlx4_dev *dev,
170 enum mlx4_port_type *port_type)
7ff93f8b
YP		 171{
172 int i;
173
174 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 175 if (port_type[i] != port_type[i + 1]) {
176 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
1a91de28 177 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 178 return -EINVAL;
179 }
7ff93f8b
YP		 180 }
181 }
7ff93f8b
YP		 182
183 for (i = 0; i < dev->caps.num_ports; i++) {
184 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 185 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
186 i + 1);
7ff93f8b
YP		 187 return -EINVAL;
188 }
189 }
190 return 0;
191}
192
193static void mlx4_set_port_mask(struct mlx4_dev *dev)
194{
195 int i;
196
7ff93f8b 197 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 198 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 199}
f2a3f6a3 200
7ae0e400
MB		 201enum {
202 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
203};
204
205static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
206{
207 int err = 0;
208 struct mlx4_func func;
209
210 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
211 err = mlx4_QUERY_FUNC(dev, &func, 0);
212 if (err) {
213 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
214 return err;
215 }
216 dev_cap->max_eqs = func.max_eq;
217 dev_cap->reserved_eqs = func.rsvd_eqs;
218 dev_cap->reserved_uars = func.rsvd_uars;
219 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
220 }
221 return err;
222}
223
77507aa2
IS		 224static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
225{
226 struct mlx4_caps *dev_cap = &dev->caps;
227
228 /* FW not supporting or cancelled by user */
229 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
230 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
231 return;
232
233 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
234 * When FW has NCSI it may decide not to report 64B CQE/EQEs
235 */
236 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
237 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
238 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
239 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
240 return;
241 }
242
243 if (cache_line_size() == 128 || cache_line_size() == 256) {
244 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
245 /* Changing the real data inside CQE size to 32B */
246 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
247 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
248
249 if (mlx4_is_master(dev))
250 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
251 } else {
252 mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n");
253 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
254 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
255 }
256}
257
431df8c7
MB		 258static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
259 struct mlx4_port_cap *port_cap)
260{
261 dev->caps.vl_cap[port] = port_cap->max_vl;
262 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
263 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
264 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
265 /* set gid and pkey table operating lengths by default
266 * to non-sriov values
267 */
268 dev->caps.gid_table_len[port] = port_cap->max_gids;
269 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
270 dev->caps.port_width_cap[port] = port_cap->max_port_width;
271 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
272 dev->caps.def_mac[port] = port_cap->def_mac;
273 dev->caps.supported_type[port] = port_cap->supported_port_types;
274 dev->caps.suggested_type[port] = port_cap->suggested_type;
275 dev->caps.default_sense[port] = port_cap->default_sense;
276 dev->caps.trans_type[port] = port_cap->trans_type;
277 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
278 dev->caps.wavelength[port] = port_cap->wavelength;
279 dev->caps.trans_code[port] = port_cap->trans_code;
280
281 return 0;
282}
283
284static int mlx4_dev_port(struct mlx4_dev *dev, int port,
285 struct mlx4_port_cap *port_cap)
286{
287 int err = 0;
288
289 err = mlx4_QUERY_PORT(dev, port, port_cap);
290
291 if (err)
292 mlx4_err(dev, "QUERY_PORT command failed.\n");
293
294 return err;
295}
296
297#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 298static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 299{
300 int err;
5ae2a7a8 301 int i;
225c7b1f
RD		 302
303 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
304 if (err) {
1a91de28 305 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 306 return err;
307 }
308
309 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 310 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 311 dev_cap->min_page_sz, PAGE_SIZE);
312 return -ENODEV;
313 }
314 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 315 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 316 dev_cap->num_ports, MLX4_MAX_PORTS);
317 return -ENODEV;
318 }
319
320 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
1a91de28 321 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f
RD		 322 dev_cap->uar_size,
323 (unsigned long long) pci_resource_len(dev->pdev, 2));
324 return -ENODEV;
325 }
326
327 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 328 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
329 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
330 dev->caps.num_sys_eqs :
331 MLX4_MAX_EQ_NUM;
5ae2a7a8 332 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 333 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
334 if (err) {
335 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
336 return err;
337 }
5ae2a7a8
RD		 338 }
339
ab9c17a0 340 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 341 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 342 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
343 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
344 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
345 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
346 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
347 dev->caps.max_wqes = dev_cap->max_qp_sz;
348 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 349 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
350 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
351 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
352 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
353 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 354 /*
355 * Subtract 1 from the limit because we need to allocate a
356 * spare CQE so the HCA HW can tell the difference between an
357 * empty CQ and a full CQ.
358 */
359 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
360 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
361 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 362 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 363 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 364
365 /* The first 128 UARs are used for EQ doorbells */
366 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 367 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 368 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
369 dev_cap->reserved_xrcds : 0;
370 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
371 dev_cap->max_xrcds : 0;
2b8fb286
MA		 372 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
373
149983af 374 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 375 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
376 dev->caps.flags = dev_cap->flags;
b3416f44 377 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 378 dev->caps.bmme_flags = dev_cap->bmme_flags;
379 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 380 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 381 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 382 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 383
ca3e57a5
RD		 384 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
385 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 386 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 387 /* Don't do sense port on multifunction devices (for now at least) */
388 if (mlx4_is_mfunc(dev))
389 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 390
2599d858
AV		 391 if (mlx4_low_memory_profile()) {
392 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
393 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
394 } else {
395 dev->caps.log_num_macs = log_num_mac;
396 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
397 }
93fc9e1b
YP		 398
399 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 400 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
401 if (dev->caps.supported_type[i]) {
402 /* if only ETH is supported - assign ETH */
403 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
404 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 405 /* if only IB is supported, assign IB */
ab9c17a0 406 else if (dev->caps.supported_type[i] ==
105c320f
JM		 407 MLX4_PORT_TYPE_IB)
408 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 409 else {
105c320f
JM		 410 /* if IB and ETH are supported, we set the port
411 * type according to user selection of port type;
412 * if user selected none, take the FW hint */
413 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 414 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
415 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 416 else
105c320f 417 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 418 }
419 }
8d0fc7b6
YP		 420 /*
421 * Link sensing is allowed on the port if 3 conditions are true:
422 * 1. Both protocols are supported on the port.
423 * 2. Different types are supported on the port
424 * 3. FW declared that it supports link sensing
425 */
27bf91d6 426 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 427 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 428 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 429 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 430
8d0fc7b6
YP		 431 /*
432 * If "default_sense" bit is set, we move the port to "AUTO" mode
433 * and perform sense_port FW command to try and set the correct
434 * port type from beginning
435 */
46c46747 436 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 437 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
438 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
439 mlx4_SENSE_PORT(dev, i, &sensed_port);
440 if (sensed_port != MLX4_PORT_TYPE_NONE)
441 dev->caps.port_type[i] = sensed_port;
442 } else {
443 dev->caps.possible_type[i] = dev->caps.port_type[i];
444 }
445
431df8c7
MB		 446 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
447 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 448 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 449 i, 1 << dev->caps.log_num_macs);
450 }
431df8c7
MB		 451 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
452 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 453 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 454 i, 1 << dev->caps.log_num_vlans);
455 }
456 }
457
f2a3f6a3
OG		 458 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
459
93fc9e1b
YP		 460 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
461 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
462 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
463 (1 << dev->caps.log_num_macs) *
464 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 465 dev->caps.num_ports;
466 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
7d077cd3
MB		 467
468 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
469 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
470 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
471 else
472 dev->caps.dmfs_high_rate_qpn_base =
473 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
474
475 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
476 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
477 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
478 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
479 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
480 } else {
481 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
482 dev->caps.dmfs_high_rate_qpn_base =
483 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
484 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
485 }
486
d57febe1 487 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
7d077cd3 488 dev->caps.dmfs_high_rate_qpn_range;
93fc9e1b
YP		 489
490 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
491 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
492 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
493 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
494
e2c76824 495 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 496
b3051320 497 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 498 if (dev_cap->flags &
499 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
500 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
501 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
502 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
503 }
77507aa2
IS		 504
505 if (dev_cap->flags2 &
506 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
507 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
508 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
509 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
510 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
511 }
08ff3235
OG		 512 }
513
f97b4b5d 514 if ((dev->caps.flags &
08ff3235
OG		 515 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
516 mlx4_is_master(dev))
517 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
518
ddae0349 519 if (!mlx4_is_slave(dev)) {
77507aa2 520 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 521 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 522 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
523 MLX4_RESERVE_A0_QP;
ddae0349
EE		 524 } else {
525 dev->caps.alloc_res_qp_mask = 0;
526 }
77507aa2 527
225c7b1f
RD		 528 return 0;
529}
b912b2f8
EP		 530
531static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
532 enum pci_bus_speed *speed,
533 enum pcie_link_width *width)
534{
535 u32 lnkcap1, lnkcap2;
536 int err1, err2;
537
538#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
539
540 *speed = PCI_SPEED_UNKNOWN;
541 *width = PCIE_LNK_WIDTH_UNKNOWN;
542
543 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
544 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
545 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
546 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
547 *speed = PCIE_SPEED_8_0GT;
548 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
549 *speed = PCIE_SPEED_5_0GT;
550 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
551 *speed = PCIE_SPEED_2_5GT;
552 }
553 if (!err1) {
554 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
555 if (!lnkcap2) { /* pre-r3.0 */
556 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
557 *speed = PCIE_SPEED_5_0GT;
558 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
559 *speed = PCIE_SPEED_2_5GT;
560 }
561 }
562
563 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
564 return err1 ? err1 :
565 err2 ? err2 : -EINVAL;
566 }
567 return 0;
568}
569
570static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
571{
572 enum pcie_link_width width, width_cap;
573 enum pci_bus_speed speed, speed_cap;
574 int err;
575
576#define PCIE_SPEED_STR(speed) \
577 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
578 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
579 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
580 "Unknown")
581
582 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
583 if (err) {
584 mlx4_warn(dev,
585 "Unable to determine PCIe device BW capabilities\n");
586 return;
587 }
588
589 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
590 if (err || speed == PCI_SPEED_UNKNOWN ||
591 width == PCIE_LNK_WIDTH_UNKNOWN) {
592 mlx4_warn(dev,
593 "Unable to determine PCI device chain minimum BW\n");
594 return;
595 }
596
597 if (width != width_cap || speed != speed_cap)
598 mlx4_warn(dev,
599 "PCIe BW is different than device's capability\n");
600
601 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
602 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
603 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
604 width, width_cap);
605 return;
606}
607
ab9c17a0
JM		 608/*The function checks if there are live vf, return the num of them*/
609static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
610{
611 struct mlx4_priv *priv = mlx4_priv(dev);
612 struct mlx4_slave_state *s_state;
613 int i;
614 int ret = 0;
615
616 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
617 s_state = &priv->mfunc.master.slave_state[i];
618 if (s_state->active && s_state->last_cmd !=
619 MLX4_COMM_CMD_RESET) {
620 mlx4_warn(dev, "%s: slave: %d is still active\n",
621 __func__, i);
622 ret++;
623 }
624 }
625 return ret;
626}
627
396f2feb
JM		 628int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
629{
630 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 631
632 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
633 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 634 return -EINVAL;
635
47605df9 636 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 637 /* tunnel qp */
47605df9 638 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 639 else
47605df9 640 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 641 *qkey = qk;
642 return 0;
643}
644EXPORT_SYMBOL(mlx4_get_parav_qkey);
645
54679e14
JM		 646void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
647{
648 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
649
650 if (!mlx4_is_master(dev))
651 return;
652
653 priv->virt2phys_pkey[slave][port - 1][i] = val;
654}
655EXPORT_SYMBOL(mlx4_sync_pkey_table);
656
afa8fd1d
JM		 657void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
658{
659 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
660
661 if (!mlx4_is_master(dev))
662 return;
663
664 priv->slave_node_guids[slave] = guid;
665}
666EXPORT_SYMBOL(mlx4_put_slave_node_guid);
667
668__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
669{
670 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
671
672 if (!mlx4_is_master(dev))
673 return 0;
674
675 return priv->slave_node_guids[slave];
676}
677EXPORT_SYMBOL(mlx4_get_slave_node_guid);
678
e10903b0 679int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 680{
681 struct mlx4_priv *priv = mlx4_priv(dev);
682 struct mlx4_slave_state *s_slave;
683
684 if (!mlx4_is_master(dev))
685 return 0;
686
687 s_slave = &priv->mfunc.master.slave_state[slave];
688 return !!s_slave->active;
689}
690EXPORT_SYMBOL(mlx4_is_slave_active);
691
7b8157be
JM		 692static void slave_adjust_steering_mode(struct mlx4_dev *dev,
693 struct mlx4_dev_cap *dev_cap,
694 struct mlx4_init_hca_param *hca_param)
695{
696 dev->caps.steering_mode = hca_param->steering_mode;
697 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
698 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
699 dev->caps.fs_log_max_ucast_qp_range_size =
700 dev_cap->fs_log_max_ucast_qp_range_size;
701 } else
702 dev->caps.num_qp_per_mgm =
703 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
704
705 mlx4_dbg(dev, "Steering mode is: %s\n",
706 mlx4_steering_mode_str(dev->caps.steering_mode));
707}
708
ab9c17a0
JM		 709static int mlx4_slave_cap(struct mlx4_dev *dev)
710{
711 int err;
712 u32 page_size;
713 struct mlx4_dev_cap dev_cap;
714 struct mlx4_func_cap func_cap;
715 struct mlx4_init_hca_param hca_param;
225c6c8c 716 u8 i;
ab9c17a0
JM		 717
718 memset(&hca_param, 0, sizeof(hca_param));
719 err = mlx4_QUERY_HCA(dev, &hca_param);
720 if (err) {
1a91de28 721 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
ab9c17a0
JM		 722 return err;
723 }
724
483e0132
EP		 725 /* fail if the hca has an unknown global capability
726 * at this time global_caps should be always zeroed
727 */
728 if (hca_param.global_caps) {
ab9c17a0
JM		 729 mlx4_err(dev, "Unknown hca global capabilities\n");
730 return -ENOSYS;
731 }
732
733 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
734
ddd8a6c1
EE		 735 dev->caps.hca_core_clock = hca_param.hca_core_clock;
736
ab9c17a0 737 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 738 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 739 err = mlx4_dev_cap(dev, &dev_cap);
740 if (err) {
1a91de28 741 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 742 return err;
743 }
744
b91cb3eb
JM		 745 err = mlx4_QUERY_FW(dev);
746 if (err)
1a91de28 747 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 748
ab9c17a0
JM		 749 page_size = ~dev->caps.page_size_cap + 1;
750 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
751 if (page_size > PAGE_SIZE) {
1a91de28 752 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0
JM		 753 page_size, PAGE_SIZE);
754 return -ENODEV;
755 }
756
757 /* slave gets uar page size from QUERY_HCA fw command */
758 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
759
760 /* TODO: relax this assumption */
761 if (dev->caps.uar_page_size != PAGE_SIZE) {
762 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
763 dev->caps.uar_page_size, PAGE_SIZE);
764 return -ENODEV;
765 }
766
767 memset(&func_cap, 0, sizeof(func_cap));
47605df9 768 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 769 if (err) {
1a91de28
JP		 770 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
771 err);
ab9c17a0
JM		 772 return err;
773 }
774
775 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
776 PF_CONTEXT_BEHAVIOUR_MASK) {
7d077cd3
MB		 777 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
778 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
ab9c17a0
JM		 779 return -ENOSYS;
780 }
781
ab9c17a0 782 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 783 dev->quotas.qp = func_cap.qp_quota;
784 dev->quotas.srq = func_cap.srq_quota;
785 dev->quotas.cq = func_cap.cq_quota;
786 dev->quotas.mpt = func_cap.mpt_quota;
787 dev->quotas.mtt = func_cap.mtt_quota;
788 dev->caps.num_qps = 1 << hca_param.log_num_qps;
789 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
790 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
791 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
792 dev->caps.num_eqs = func_cap.max_eq;
793 dev->caps.reserved_eqs = func_cap.reserved_eq;
ab9c17a0
JM		 794 dev->caps.num_pds = MLX4_NUM_PDS;
795 dev->caps.num_mgms = 0;
796 dev->caps.num_amgms = 0;
797
ab9c17a0 798 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 799 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
800 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 801 return -ENODEV;
802 }
803
99ec41d0 804 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
47605df9
JM		 805 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
806 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
807 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
808 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
809
810 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
99ec41d0
JM		 811 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
812 !dev->caps.qp0_qkey) {
47605df9
JM		 813 err = -ENOMEM;
814 goto err_mem;
815 }
816
6634961c 817 for (i = 1; i <= dev->caps.num_ports; ++i) {
225c6c8c 818 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
47605df9 819 if (err) {
1a91de28
JP		 820 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
821 i, err);
47605df9
JM		 822 goto err_mem;
823 }
99ec41d0 824 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
47605df9
JM		 825 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
826 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
827 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
828 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 829 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 830 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 831 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
832 &dev->caps.gid_table_len[i],
833 &dev->caps.pkey_table_len[i]))
47605df9 834 goto err_mem;
6634961c 835 }
6230bb23 836
ab9c17a0
JM		 837 if (dev->caps.uar_page_size * (dev->caps.num_uars -
838 dev->caps.reserved_uars) >
839 pci_resource_len(dev->pdev, 2)) {
1a91de28 840 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0
JM		 841 dev->caps.uar_page_size * dev->caps.num_uars,
842 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 843 goto err_mem;
ab9c17a0
JM		 844 }
845
08ff3235
OG		 846 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
847 dev->caps.eqe_size = 64;
848 dev->caps.eqe_factor = 1;
849 } else {
850 dev->caps.eqe_size = 32;
851 dev->caps.eqe_factor = 0;
852 }
853
854 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
855 dev->caps.cqe_size = 64;
77507aa2 856 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 857 } else {
858 dev->caps.cqe_size = 32;
859 }
860
77507aa2
IS		 861 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
862 dev->caps.eqe_size = hca_param.eqe_size;
863 dev->caps.eqe_factor = 0;
864 }
865
866 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
867 dev->caps.cqe_size = hca_param.cqe_size;
868 /* User still need to know when CQE > 32B */
869 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
870 }
871
f9bd2d7f 872 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 873 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 874
7b8157be
JM		 875 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
876
ddae0349
EE		 877 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
878 dev->caps.bf_reg_size)
879 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
880
d57febe1
MB		 881 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
882 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
883
ab9c17a0 884 return 0;
47605df9
JM		 885
886err_mem:
99ec41d0 887 kfree(dev->caps.qp0_qkey);
47605df9
JM		 888 kfree(dev->caps.qp0_tunnel);
889 kfree(dev->caps.qp0_proxy);
890 kfree(dev->caps.qp1_tunnel);
891 kfree(dev->caps.qp1_proxy);
99ec41d0
JM		 892 dev->caps.qp0_qkey = NULL;
893 dev->caps.qp0_tunnel = NULL;
894 dev->caps.qp0_proxy = NULL;
895 dev->caps.qp1_tunnel = NULL;
896 dev->caps.qp1_proxy = NULL;
47605df9
JM		 897
898 return err;
ab9c17a0 899}
225c7b1f 900
b046ffe5
EP		 901static void mlx4_request_modules(struct mlx4_dev *dev)
902{
903 int port;
904 int has_ib_port = false;
905 int has_eth_port = false;
906#define EN_DRV_NAME "mlx4_en"
907#define IB_DRV_NAME "mlx4_ib"
908
909 for (port = 1; port <= dev->caps.num_ports; port++) {
910 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
911 has_ib_port = true;
912 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
913 has_eth_port = true;
914 }
915
b046ffe5
EP		 916 if (has_eth_port)
917 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 918 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
919 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 920}
921
7ff93f8b
YP		 922/*
923 * Change the port configuration of the device.
924 * Every user of this function must hold the port mutex.
925 */
27bf91d6
YP		 926int mlx4_change_port_types(struct mlx4_dev *dev,
927 enum mlx4_port_type *port_types)
7ff93f8b
YP		 928{
929 int err = 0;
930 int change = 0;
931 int port;
932
933 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 934 /* Change the port type only if the new type is different
935 * from the current, and not set to Auto */
3d8f9308 936 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 937 change = 1;
7ff93f8b
YP		 938 }
939 if (change) {
940 mlx4_unregister_device(dev);
941 for (port = 1; port <= dev->caps.num_ports; port++) {
942 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 943 dev->caps.port_type[port] = port_types[port - 1];
6634961c 944 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 945 if (err) {
1a91de28
JP		 946 mlx4_err(dev, "Failed to set port %d, aborting\n",
947 port);
7ff93f8b
YP		 948 goto out;
949 }
950 }
951 mlx4_set_port_mask(dev);
952 err = mlx4_register_device(dev);
b046ffe5
EP		 953 if (err) {
954 mlx4_err(dev, "Failed to register device\n");
955 goto out;
956 }
957 mlx4_request_modules(dev);
7ff93f8b
YP		 958 }
959
960out:
961 return err;
962}
963
964static ssize_t show_port_type(struct device *dev,
965 struct device_attribute *attr,
966 char *buf)
967{
968 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
969 port_attr);
970 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 971 char type[8];
972
973 sprintf(type, "%s",
974 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
975 "ib" : "eth");
976 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
977 sprintf(buf, "auto (%s)\n", type);
978 else
979 sprintf(buf, "%s\n", type);
7ff93f8b 980
27bf91d6 981 return strlen(buf);
7ff93f8b
YP		 982}
983
984static ssize_t set_port_type(struct device *dev,
985 struct device_attribute *attr,
986 const char *buf, size_t count)
987{
988 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
989 port_attr);
990 struct mlx4_dev *mdev = info->dev;
991 struct mlx4_priv *priv = mlx4_priv(mdev);
992 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 993 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
0a984556 994 static DEFINE_MUTEX(set_port_type_mutex);
7ff93f8b
YP		 995 int i;
996 int err = 0;
997
0a984556
AV		 998 mutex_lock(&set_port_type_mutex);
999
7ff93f8b
YP		 1000 if (!strcmp(buf, "ib\n"))
1001 info->tmp_type = MLX4_PORT_TYPE_IB;
1002 else if (!strcmp(buf, "eth\n"))
1003 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 1004 else if (!strcmp(buf, "auto\n"))
1005 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 1006 else {
1007 mlx4_err(mdev, "%s is not supported port type\n", buf);
0a984556
AV		 1008 err = -EINVAL;
1009 goto err_out;
7ff93f8b
YP		 1010 }
1011
27bf91d6 1012 mlx4_stop_sense(mdev);
7ff93f8b 1013 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 1014 /* Possible type is always the one that was delivered */
1015 mdev->caps.possible_type[info->port] = info->tmp_type;
1016
1017 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 1018 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 1019 mdev->caps.possible_type[i+1];
1020 if (types[i] == MLX4_PORT_TYPE_AUTO)
1021 types[i] = mdev->caps.port_type[i+1];
1022 }
7ff93f8b 1023
58a60168
YP		 1024 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1025 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1026 for (i = 1; i <= mdev->caps.num_ports; i++) {
1027 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1028 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1029 err = -EINVAL;
1030 }
1031 }
1032 }
1033 if (err) {
1a91de28 1034 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1035 goto out;
1036 }
1037
1038 mlx4_do_sense_ports(mdev, new_types, types);
1039
1040 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1041 if (err)
1042 goto out;
1043
27bf91d6
YP		 1044 /* We are about to apply the changes after the configuration
1045 * was verified, no need to remember the temporary types
1046 * any more */
1047 for (i = 0; i < mdev->caps.num_ports; i++)
1048 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1049
27bf91d6 1050 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1051
1052out:
27bf91d6 1053 mlx4_start_sense(mdev);
7ff93f8b 1054 mutex_unlock(&priv->port_mutex);
0a984556
AV		 1055err_out:
1056 mutex_unlock(&set_port_type_mutex);
1057
7ff93f8b
YP		 1058 return err ? err : count;
1059}
1060
096335b3
OG		 1061enum ibta_mtu {
1062 IB_MTU_256 = 1,
1063 IB_MTU_512 = 2,
1064 IB_MTU_1024 = 3,
1065 IB_MTU_2048 = 4,
1066 IB_MTU_4096 = 5
1067};
1068
1069static inline int int_to_ibta_mtu(int mtu)
1070{
1071 switch (mtu) {
1072 case 256: return IB_MTU_256;
1073 case 512: return IB_MTU_512;
1074 case 1024: return IB_MTU_1024;
1075 case 2048: return IB_MTU_2048;
1076 case 4096: return IB_MTU_4096;
1077 default: return -1;
1078 }
1079}
1080
1081static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1082{
1083 switch (mtu) {
1084 case IB_MTU_256: return 256;
1085 case IB_MTU_512: return 512;
1086 case IB_MTU_1024: return 1024;
1087 case IB_MTU_2048: return 2048;
1088 case IB_MTU_4096: return 4096;
1089 default: return -1;
1090 }
1091}
1092
1093static ssize_t show_port_ib_mtu(struct device *dev,
1094 struct device_attribute *attr,
1095 char *buf)
1096{
1097 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1098 port_mtu_attr);
1099 struct mlx4_dev *mdev = info->dev;
1100
1101 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1102 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1103
1104 sprintf(buf, "%d\n",
1105 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1106 return strlen(buf);
1107}
1108
1109static ssize_t set_port_ib_mtu(struct device *dev,
1110 struct device_attribute *attr,
1111 const char *buf, size_t count)
1112{
1113 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1114 port_mtu_attr);
1115 struct mlx4_dev *mdev = info->dev;
1116 struct mlx4_priv *priv = mlx4_priv(mdev);
1117 int err, port, mtu, ibta_mtu = -1;
1118
1119 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1120 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1121 return -EINVAL;
1122 }
1123
618fad95
DB		 1124 err = kstrtoint(buf, 0, &mtu);
1125 if (!err)
096335b3
OG		 1126 ibta_mtu = int_to_ibta_mtu(mtu);
1127
618fad95 1128 if (err || ibta_mtu < 0) {
096335b3
OG		 1129 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1130 return -EINVAL;
1131 }
1132
1133 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1134
1135 mlx4_stop_sense(mdev);
1136 mutex_lock(&priv->port_mutex);
1137 mlx4_unregister_device(mdev);
1138 for (port = 1; port <= mdev->caps.num_ports; port++) {
1139 mlx4_CLOSE_PORT(mdev, port);
6634961c 1140 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1141 if (err) {
1a91de28
JP		 1142 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1143 port);
096335b3
OG		 1144 goto err_set_port;
1145 }
1146 }
1147 err = mlx4_register_device(mdev);
1148err_set_port:
1149 mutex_unlock(&priv->port_mutex);
1150 mlx4_start_sense(mdev);
1151 return err ? err : count;
1152}
1153
e8f9b2ed 1154static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1155{
1156 struct mlx4_priv *priv = mlx4_priv(dev);
1157 int err;
1158
1159 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1160 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1161 if (!priv->fw.fw_icm) {
1a91de28 1162 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1163 return -ENOMEM;
1164 }
1165
1166 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1167 if (err) {
1a91de28 1168 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1169 goto err_free;
1170 }
1171
1172 err = mlx4_RUN_FW(dev);
1173 if (err) {
1a91de28 1174 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1175 goto err_unmap_fa;
1176 }
1177
1178 return 0;
1179
1180err_unmap_fa:
1181 mlx4_UNMAP_FA(dev);
1182
1183err_free:
5b0bf5e2 1184 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1185 return err;
1186}
1187
e8f9b2ed
RD		 1188static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1189 int cmpt_entry_sz)
225c7b1f
RD		 1190{
1191 struct mlx4_priv *priv = mlx4_priv(dev);
1192 int err;
ab9c17a0 1193 int num_eqs;
225c7b1f
RD		 1194
1195 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1196 cmpt_base +
1197 ((u64) (MLX4_CMPT_TYPE_QP *
1198 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1199 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1200 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1201 0, 0);
225c7b1f
RD		 1202 if (err)
1203 goto err;
1204
1205 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1206 cmpt_base +
1207 ((u64) (MLX4_CMPT_TYPE_SRQ *
1208 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1209 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1210 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1211 if (err)
1212 goto err_qp;
1213
1214 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1215 cmpt_base +
1216 ((u64) (MLX4_CMPT_TYPE_CQ *
1217 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1218 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1219 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1220 if (err)
1221 goto err_srq;
1222
7ae0e400 1223 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1224 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1225 cmpt_base +
1226 ((u64) (MLX4_CMPT_TYPE_EQ *
1227 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1228 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1229 if (err)
1230 goto err_cq;
1231
1232 return 0;
1233
1234err_cq:
1235 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1236
1237err_srq:
1238 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1239
1240err_qp:
1241 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1242
1243err:
1244 return err;
1245}
1246
3d73c288
RD		 1247static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1248 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1249{
1250 struct mlx4_priv *priv = mlx4_priv(dev);
1251 u64 aux_pages;
ab9c17a0 1252 int num_eqs;
225c7b1f
RD		 1253 int err;
1254
1255 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1256 if (err) {
1a91de28 1257 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1258 return err;
1259 }
1260
1a91de28 1261 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1262 (unsigned long long) icm_size >> 10,
1263 (unsigned long long) aux_pages << 2);
1264
1265 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1266 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1267 if (!priv->fw.aux_icm) {
1a91de28 1268 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1269 return -ENOMEM;
1270 }
1271
1272 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1273 if (err) {
1a91de28 1274 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1275 goto err_free_aux;
1276 }
1277
1278 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1279 if (err) {
1a91de28 1280 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1281 goto err_unmap_aux;
1282 }
1283
ab9c17a0 1284
7ae0e400 1285 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1286 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1287 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1288 num_eqs, num_eqs, 0, 0);
225c7b1f 1289 if (err) {
1a91de28 1290 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1291 goto err_unmap_cmpt;
1292 }
1293
d7bb58fb
JM		 1294 /*
1295 * Reserved MTT entries must be aligned up to a cacheline
1296 * boundary, since the FW will write to them, while the driver
1297 * writes to all other MTT entries. (The variable
1298 * dev->caps.mtt_entry_sz below is really the MTT segment
1299 * size, not the raw entry size)
1300 */
1301 dev->caps.reserved_mtts =
1302 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1303 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1304
225c7b1f
RD		 1305 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1306 init_hca->mtt_base,
1307 dev->caps.mtt_entry_sz,
2b8fb286 1308 dev->caps.num_mtts,
5b0bf5e2 1309 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1310 if (err) {
1a91de28 1311 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1312 goto err_unmap_eq;
1313 }
1314
1315 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1316 init_hca->dmpt_base,
1317 dev_cap->dmpt_entry_sz,
1318 dev->caps.num_mpts,
5b0bf5e2 1319 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1320 if (err) {
1a91de28 1321 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1322 goto err_unmap_mtt;
1323 }
1324
1325 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1326 init_hca->qpc_base,
1327 dev_cap->qpc_entry_sz,
1328 dev->caps.num_qps,
93fc9e1b
YP		 1329 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1330 0, 0);
225c7b1f 1331 if (err) {
1a91de28 1332 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1333 goto err_unmap_dmpt;
1334 }
1335
1336 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1337 init_hca->auxc_base,
1338 dev_cap->aux_entry_sz,
1339 dev->caps.num_qps,
93fc9e1b
YP		 1340 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1341 0, 0);
225c7b1f 1342 if (err) {
1a91de28 1343 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1344 goto err_unmap_qp;
1345 }
1346
1347 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1348 init_hca->altc_base,
1349 dev_cap->altc_entry_sz,
1350 dev->caps.num_qps,
93fc9e1b
YP		 1351 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1352 0, 0);
225c7b1f 1353 if (err) {
1a91de28 1354 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1355 goto err_unmap_auxc;
1356 }
1357
1358 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1359 init_hca->rdmarc_base,
1360 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1361 dev->caps.num_qps,
93fc9e1b
YP		 1362 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1363 0, 0);
225c7b1f
RD		 1364 if (err) {
1365 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1366 goto err_unmap_altc;
1367 }
1368
1369 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1370 init_hca->cqc_base,
1371 dev_cap->cqc_entry_sz,
1372 dev->caps.num_cqs,
5b0bf5e2 1373 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1374 if (err) {
1a91de28 1375 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1376 goto err_unmap_rdmarc;
1377 }
1378
1379 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1380 init_hca->srqc_base,
1381 dev_cap->srq_entry_sz,
1382 dev->caps.num_srqs,
5b0bf5e2 1383 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1384 if (err) {
1a91de28 1385 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1386 goto err_unmap_cq;
1387 }
1388
1389 /*
0ff1fb65
HHZ		 1390 * For flow steering device managed mode it is required to use
1391 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1392 * required, but for simplicity just map the whole multicast
1393 * group table now. The table isn't very big and it's a lot
1394 * easier than trying to track ref counts.
225c7b1f
RD		 1395 */
1396 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1397 init_hca->mc_base,
1398 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1399 dev->caps.num_mgms + dev->caps.num_amgms,
1400 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1401 0, 0);
225c7b1f 1402 if (err) {
1a91de28 1403 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1404 goto err_unmap_srq;
1405 }
1406
1407 return 0;
1408
1409err_unmap_srq:
1410 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1411
1412err_unmap_cq:
1413 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1414
1415err_unmap_rdmarc:
1416 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1417
1418err_unmap_altc:
1419 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1420
1421err_unmap_auxc:
1422 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1423
1424err_unmap_qp:
1425 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1426
1427err_unmap_dmpt:
1428 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1429
1430err_unmap_mtt:
1431 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1432
1433err_unmap_eq:
fa0681d2 1434 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1435
1436err_unmap_cmpt:
1437 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1438 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1439 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1440 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1441
1442err_unmap_aux:
1443 mlx4_UNMAP_ICM_AUX(dev);
1444
1445err_free_aux:
5b0bf5e2 1446 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1447
1448 return err;
1449}
1450
1451static void mlx4_free_icms(struct mlx4_dev *dev)
1452{
1453 struct mlx4_priv *priv = mlx4_priv(dev);
1454
1455 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1456 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1457 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1458 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1459 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1460 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1461 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1462 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1463 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1464 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1465 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1466 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1467 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1468 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1469
1470 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1471 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1472}
1473
ab9c17a0
JM		 1474static void mlx4_slave_exit(struct mlx4_dev *dev)
1475{
1476 struct mlx4_priv *priv = mlx4_priv(dev);
1477
f3d4c89e 1478 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1479 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1a91de28 1480 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1481 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1482}
1483
c1b43dca
EC		 1484static int map_bf_area(struct mlx4_dev *dev)
1485{
1486 struct mlx4_priv *priv = mlx4_priv(dev);
1487 resource_size_t bf_start;
1488 resource_size_t bf_len;
1489 int err = 0;
1490
3d747473
JM		 1491 if (!dev->caps.bf_reg_size)
1492 return -ENXIO;
1493
ab9c17a0
JM		 1494 bf_start = pci_resource_start(dev->pdev, 2) +
1495 (dev->caps.num_uars << PAGE_SHIFT);
1496 bf_len = pci_resource_len(dev->pdev, 2) -
1497 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1498 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1499 if (!priv->bf_mapping)
1500 err = -ENOMEM;
1501
1502 return err;
1503}
1504
1505static void unmap_bf_area(struct mlx4_dev *dev)
1506{
1507 if (mlx4_priv(dev)->bf_mapping)
1508 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1509}
1510
ec693d47
AV		 1511cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1512{
1513 u32 clockhi, clocklo, clockhi1;
1514 cycle_t cycles;
1515 int i;
1516 struct mlx4_priv *priv = mlx4_priv(dev);
1517
1518 for (i = 0; i < 10; i++) {
1519 clockhi = swab32(readl(priv->clock_mapping));
1520 clocklo = swab32(readl(priv->clock_mapping + 4));
1521 clockhi1 = swab32(readl(priv->clock_mapping));
1522 if (clockhi == clockhi1)
1523 break;
1524 }
1525
1526 cycles = (u64) clockhi << 32 | (u64) clocklo;
1527
1528 return cycles;
1529}
1530EXPORT_SYMBOL_GPL(mlx4_read_clock);
1531
1532
ddd8a6c1
EE		 1533static int map_internal_clock(struct mlx4_dev *dev)
1534{
1535 struct mlx4_priv *priv = mlx4_priv(dev);
1536
1537 priv->clock_mapping =
1538 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1539 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1540
1541 if (!priv->clock_mapping)
1542 return -ENOMEM;
1543
1544 return 0;
1545}
1546
1547static void unmap_internal_clock(struct mlx4_dev *dev)
1548{
1549 struct mlx4_priv *priv = mlx4_priv(dev);
1550
1551 if (priv->clock_mapping)
1552 iounmap(priv->clock_mapping);
1553}
1554
225c7b1f
RD		 1555static void mlx4_close_hca(struct mlx4_dev *dev)
1556{
ddd8a6c1 1557 unmap_internal_clock(dev);
c1b43dca 1558 unmap_bf_area(dev);
ab9c17a0
JM		 1559 if (mlx4_is_slave(dev))
1560 mlx4_slave_exit(dev);
1561 else {
1562 mlx4_CLOSE_HCA(dev, 0);
1563 mlx4_free_icms(dev);
a0eacca9
MB		 1564 }
1565}
1566
1567static void mlx4_close_fw(struct mlx4_dev *dev)
1568{
1569 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1570 mlx4_UNMAP_FA(dev);
1571 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1572 }
1573}
1574
1575static int mlx4_init_slave(struct mlx4_dev *dev)
1576{
1577 struct mlx4_priv *priv = mlx4_priv(dev);
1578 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1579 int ret_from_reset = 0;
1580 u32 slave_read;
1581 u32 cmd_channel_ver;
1582
97989356 1583 if (atomic_read(&pf_loading)) {
1a91de28 1584 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 1585 return -EPROBE_DEFER;
1586 }
1587
f3d4c89e 1588 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1589 priv->cmd.max_cmds = 1;
1590 mlx4_warn(dev, "Sending reset\n");
1591 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1592 MLX4_COMM_TIME);
1593 /* if we are in the middle of flr the slave will try
1594 * NUM_OF_RESET_RETRIES times before leaving.*/
1595 if (ret_from_reset) {
1596 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 1597 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 1598 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1599 return -EPROBE_DEFER;
ab9c17a0
JM		 1600 } else
1601 goto err;
1602 }
1603
1604 /* check the driver version - the slave I/F revision
1605 * must match the master's */
1606 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1607 cmd_channel_ver = mlx4_comm_get_version();
1608
1609 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1610 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 1611 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 1612 goto err;
1613 }
1614
1615 mlx4_warn(dev, "Sending vhcr0\n");
1616 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1617 MLX4_COMM_TIME))
1618 goto err;
1619 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1620 MLX4_COMM_TIME))
1621 goto err;
1622 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1623 MLX4_COMM_TIME))
1624 goto err;
1625 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1626 goto err;
f3d4c89e
RD		 1627
1628 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1629 return 0;
1630
1631err:
1632 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1633 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1634 return -EIO;
225c7b1f
RD		 1635}
1636
6634961c
JM		 1637static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1638{
1639 int i;
1640
1641 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1642 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1643 dev->caps.gid_table_len[i] =
449fc488 1644 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1645 else
1646 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1647 dev->caps.pkey_table_len[i] =
1648 dev->phys_caps.pkey_phys_table_len[i] - 1;
1649 }
1650}
1651
3c439b55
JM		 1652static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1653{
1654 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1655
1656 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1657 i++) {
1658 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1659 break;
1660 }
1661
1662 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1663}
1664
7d077cd3
MB		 1665static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
1666{
1667 switch (dmfs_high_steer_mode) {
1668 case MLX4_STEERING_DMFS_A0_DEFAULT:
1669 return "default performance";
1670
1671 case MLX4_STEERING_DMFS_A0_DYNAMIC:
1672 return "dynamic hybrid mode";
1673
1674 case MLX4_STEERING_DMFS_A0_STATIC:
1675 return "performance optimized for limited rule configuration (static)";
1676
1677 case MLX4_STEERING_DMFS_A0_DISABLE:
1678 return "disabled performance optimized steering";
1679
1680 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
1681 return "performance optimized steering not supported";
1682
1683 default:
1684 return "Unrecognized mode";
1685 }
1686}
1687
1688#define MLX4_DMFS_A0_STEERING (1UL << 2)
1689
7b8157be
JM		 1690static void choose_steering_mode(struct mlx4_dev *dev,
1691 struct mlx4_dev_cap *dev_cap)
1692{
7d077cd3
MB		 1693 if (mlx4_log_num_mgm_entry_size <= 0) {
1694 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
1695 if (dev->caps.dmfs_high_steer_mode ==
1696 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1697 mlx4_err(dev, "DMFS high rate mode not supported\n");
1698 else
1699 dev->caps.dmfs_high_steer_mode =
1700 MLX4_STEERING_DMFS_A0_STATIC;
1701 }
1702 }
1703
1704 if (mlx4_log_num_mgm_entry_size <= 0 &&
3c439b55 1705 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1706 (!mlx4_is_mfunc(dev) ||
449fc488 1707 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) &&
3c439b55
JM		 1708 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1709 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1710 dev->oper_log_mgm_entry_size =
1711 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1712 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1713 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1714 dev->caps.fs_log_max_ucast_qp_range_size =
1715 dev_cap->fs_log_max_ucast_qp_range_size;
1716 } else {
7d077cd3
MB		 1717 if (dev->caps.dmfs_high_steer_mode !=
1718 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1719 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
7b8157be
JM		 1720 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1721 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1722 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1723 else {
1724 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1725
1726 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1727 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 1728 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 1729 }
3c439b55
JM		 1730 dev->oper_log_mgm_entry_size =
1731 mlx4_log_num_mgm_entry_size > 0 ?
1732 mlx4_log_num_mgm_entry_size :
1733 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1734 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1735 }
1a91de28 1736 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 1737 mlx4_steering_mode_str(dev->caps.steering_mode),
1738 dev->oper_log_mgm_entry_size,
1739 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1740}
1741
7ffdf726
OG		 1742static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1743 struct mlx4_dev_cap *dev_cap)
1744{
1745 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
7d077cd3
MB		 1746 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS &&
1747 dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
7ffdf726
OG		 1748 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1749 else
1750 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1751
1752 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1753 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1754}
1755
7d077cd3
MB		 1756static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
1757{
1758 int i;
1759 struct mlx4_port_cap port_cap;
1760
1761 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1762 return -EINVAL;
1763
1764 for (i = 1; i <= dev->caps.num_ports; i++) {
1765 if (mlx4_dev_port(dev, i, &port_cap)) {
1766 mlx4_err(dev,
1767 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
1768 } else if ((dev->caps.dmfs_high_steer_mode !=
1769 MLX4_STEERING_DMFS_A0_DEFAULT) &&
1770 (port_cap.dmfs_optimized_state ==
1771 !!(dev->caps.dmfs_high_steer_mode ==
1772 MLX4_STEERING_DMFS_A0_DISABLE))) {
1773 mlx4_err(dev,
1774 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
1775 dmfs_high_rate_steering_mode_str(
1776 dev->caps.dmfs_high_steer_mode),
1777 (port_cap.dmfs_optimized_state ?
1778 "enabled" : "disabled"));
1779 }
1780 }
1781
1782 return 0;
1783}
1784
a0eacca9 1785static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 1786{
2d928651 1787 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 1788 int err = 0;
225c7b1f 1789
ab9c17a0
JM		 1790 if (!mlx4_is_slave(dev)) {
1791 err = mlx4_QUERY_FW(dev);
1792 if (err) {
1793 if (err == -EACCES)
1a91de28 1794 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 1795 else
1a91de28 1796 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 1797 return err;
ab9c17a0 1798 }
225c7b1f 1799
ab9c17a0
JM		 1800 err = mlx4_load_fw(dev);
1801 if (err) {
1a91de28 1802 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 1803 return err;
ab9c17a0 1804 }
225c7b1f 1805
ab9c17a0
JM		 1806 mlx4_cfg.log_pg_sz_m = 1;
1807 mlx4_cfg.log_pg_sz = 0;
1808 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1809 if (err)
1810 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 1811 }
2d928651 1812
a0eacca9
MB		 1813 return err;
1814}
1815
1816static int mlx4_init_hca(struct mlx4_dev *dev)
1817{
1818 struct mlx4_priv *priv = mlx4_priv(dev);
1819 struct mlx4_adapter adapter;
1820 struct mlx4_dev_cap dev_cap;
1821 struct mlx4_profile profile;
1822 struct mlx4_init_hca_param init_hca;
1823 u64 icm_size;
1824 struct mlx4_config_dev_params params;
1825 int err;
1826
1827 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1828 err = mlx4_dev_cap(dev, &dev_cap);
1829 if (err) {
1a91de28 1830 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 1831 goto err_stop_fw;
1832 }
225c7b1f 1833
7b8157be 1834 choose_steering_mode(dev, &dev_cap);
7ffdf726 1835 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1836
7d077cd3
MB		 1837 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
1838 mlx4_is_master(dev))
1839 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
1840
8e1a28e8
HHZ		 1841 err = mlx4_get_phys_port_id(dev);
1842 if (err)
1843 mlx4_err(dev, "Fail to get physical port id\n");
1844
6634961c
JM		 1845 if (mlx4_is_master(dev))
1846 mlx4_parav_master_pf_caps(dev);
1847
2599d858
AV		 1848 if (mlx4_low_memory_profile()) {
1849 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
1850 profile = low_mem_profile;
1851 } else {
1852 profile = default_profile;
1853 }
0ff1fb65
HHZ		 1854 if (dev->caps.steering_mode ==
1855 MLX4_STEERING_MODE_DEVICE_MANAGED)
1856 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1857
ab9c17a0
JM		 1858 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1859 &init_hca);
1860 if ((long long) icm_size < 0) {
1861 err = icm_size;
1862 goto err_stop_fw;
1863 }
225c7b1f 1864
a5bbe892
EC		 1865 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1866
ab9c17a0
JM		 1867 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1868 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1869 init_hca.mw_enabled = 0;
1870 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1871 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1872 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1873
ab9c17a0
JM		 1874 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1875 if (err)
1876 goto err_stop_fw;
225c7b1f 1877
ab9c17a0
JM		 1878 err = mlx4_INIT_HCA(dev, &init_hca);
1879 if (err) {
1a91de28 1880 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 1881 goto err_free_icm;
1882 }
7ae0e400
MB		 1883
1884 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
1885 err = mlx4_query_func(dev, &dev_cap);
1886 if (err < 0) {
1887 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
1888 goto err_stop_fw;
1889 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
1890 dev->caps.num_eqs = dev_cap.max_eqs;
1891 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
1892 dev->caps.reserved_uars = dev_cap.reserved_uars;
1893 }
1894 }
1895
ddd8a6c1
EE		 1896 /*
1897 * If TS is supported by FW
1898 * read HCA frequency by QUERY_HCA command
1899 */
1900 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1901 memset(&init_hca, 0, sizeof(init_hca));
1902 err = mlx4_QUERY_HCA(dev, &init_hca);
1903 if (err) {
1a91de28 1904 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 1905 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1906 } else {
1907 dev->caps.hca_core_clock =
1908 init_hca.hca_core_clock;
1909 }
1910
1911 /* In case we got HCA frequency 0 - disable timestamping
1912 * to avoid dividing by zero
1913 */
1914 if (!dev->caps.hca_core_clock) {
1915 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1916 mlx4_err(dev,
1a91de28 1917 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 1918 } else if (map_internal_clock(dev)) {
1919 /*
1920 * Map internal clock,
1921 * in case of failure disable timestamping
1922 */
1923 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1924 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 1925 }
1926 }
7d077cd3
MB		 1927
1928 if (dev->caps.dmfs_high_steer_mode !=
1929 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
1930 if (mlx4_validate_optimized_steering(dev))
1931 mlx4_warn(dev, "Optimized steering validation failed\n");
1932
1933 if (dev->caps.dmfs_high_steer_mode ==
1934 MLX4_STEERING_DMFS_A0_DISABLE) {
1935 dev->caps.dmfs_high_rate_qpn_base =
1936 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1937 dev->caps.dmfs_high_rate_qpn_range =
1938 MLX4_A0_STEERING_TABLE_SIZE;
1939 }
1940
1941 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
1942 dmfs_high_rate_steering_mode_str(
1943 dev->caps.dmfs_high_steer_mode));
1944 }
ab9c17a0
JM		 1945 } else {
1946 err = mlx4_init_slave(dev);
1947 if (err) {
5efe5355
JM		 1948 if (err != -EPROBE_DEFER)
1949 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1950 return err;
ab9c17a0 1951 }
225c7b1f 1952
ab9c17a0
JM		 1953 err = mlx4_slave_cap(dev);
1954 if (err) {
1955 mlx4_err(dev, "Failed to obtain slave caps\n");
1956 goto err_close;
1957 }
225c7b1f
RD		 1958 }
1959
ab9c17a0
JM		 1960 if (map_bf_area(dev))
1961 mlx4_dbg(dev, "Failed to map blue flame area\n");
1962
1963 /*Only the master set the ports, all the rest got it from it.*/
1964 if (!mlx4_is_slave(dev))
1965 mlx4_set_port_mask(dev);
1966
225c7b1f
RD		 1967 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1968 if (err) {
1a91de28 1969 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 1970 goto unmap_bf;
225c7b1f
RD		 1971 }
1972
f8c6455b
SM		 1973 /* Query CONFIG_DEV parameters */
1974 err = mlx4_config_dev_retrieval(dev, &params);
1975 if (err && err != -ENOTSUPP) {
1976 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
1977 } else if (!err) {
1978 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
1979 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
1980 }
225c7b1f 1981 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1982 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1983
1984 return 0;
1985
bef772eb 1986unmap_bf:
ddd8a6c1 1987 unmap_internal_clock(dev);
bef772eb
AY		 1988 unmap_bf_area(dev);
1989
b38f2879 1990 if (mlx4_is_slave(dev)) {
99ec41d0 1991 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 1992 kfree(dev->caps.qp0_tunnel);
1993 kfree(dev->caps.qp0_proxy);
1994 kfree(dev->caps.qp1_tunnel);
1995 kfree(dev->caps.qp1_proxy);
1996 }
1997
225c7b1f 1998err_close:
41929ed2
DB		 1999 if (mlx4_is_slave(dev))
2000 mlx4_slave_exit(dev);
2001 else
2002 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 2003
2004err_free_icm:
ab9c17a0
JM		 2005 if (!mlx4_is_slave(dev))
2006 mlx4_free_icms(dev);
225c7b1f
RD		 2007
2008err_stop_fw:
ab9c17a0
JM		 2009 if (!mlx4_is_slave(dev)) {
2010 mlx4_UNMAP_FA(dev);
2011 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
2012 }
225c7b1f
RD		 2013 return err;
2014}
2015
f2a3f6a3
OG		 2016static int mlx4_init_counters_table(struct mlx4_dev *dev)
2017{
2018 struct mlx4_priv *priv = mlx4_priv(dev);
2019 int nent;
2020
2021 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2022 return -ENOENT;
2023
2024 nent = dev->caps.max_counters;
2025 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
2026}
2027
2028static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2029{
2030 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2031}
2032
ba062d52 2033int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 2034{
2035 struct mlx4_priv *priv = mlx4_priv(dev);
2036
2037 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2038 return -ENOENT;
2039
2040 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2041 if (*idx == -1)
2042 return -ENOMEM;
2043
2044 return 0;
2045}
ba062d52
JM		 2046
2047int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2048{
2049 u64 out_param;
2050 int err;
2051
2052 if (mlx4_is_mfunc(dev)) {
2053 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2054 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2055 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2056 if (!err)
2057 *idx = get_param_l(&out_param);
2058
2059 return err;
2060 }
2061 return __mlx4_counter_alloc(dev, idx);
2062}
f2a3f6a3
OG		 2063EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2064
ba062d52 2065void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 2066{
7c6d74d2 2067 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 2068 return;
2069}
ba062d52
JM		 2070
2071void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2072{
e7dbeba8 2073 u64 in_param = 0;
ba062d52
JM		 2074
2075 if (mlx4_is_mfunc(dev)) {
2076 set_param_l(&in_param, idx);
2077 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2078 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2079 MLX4_CMD_WRAPPED);
2080 return;
2081 }
2082 __mlx4_counter_free(dev, idx);
2083}
f2a3f6a3
OG		 2084EXPORT_SYMBOL_GPL(mlx4_counter_free);
2085
3d73c288 2086static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 2087{
2088 struct mlx4_priv *priv = mlx4_priv(dev);
2089 int err;
7ff93f8b 2090 int port;
9a5aa622 2091 __be32 ib_port_default_caps;
225c7b1f 2092
225c7b1f
RD		 2093 err = mlx4_init_uar_table(dev);
2094 if (err) {
1a91de28
JP		 2095 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2096 return err;
225c7b1f
RD		 2097 }
2098
2099 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2100 if (err) {
1a91de28 2101 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 2102 goto err_uar_table_free;
2103 }
2104
4979d18f 2105 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 2106 if (!priv->kar) {
1a91de28 2107 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 2108 err = -ENOMEM;
2109 goto err_uar_free;
2110 }
2111
2112 err = mlx4_init_pd_table(dev);
2113 if (err) {
1a91de28 2114 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2115 goto err_kar_unmap;
2116 }
2117
012a8ff5
SH		 2118 err = mlx4_init_xrcd_table(dev);
2119 if (err) {
1a91de28 2120 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2121 goto err_pd_table_free;
2122 }
2123
225c7b1f
RD		 2124 err = mlx4_init_mr_table(dev);
2125 if (err) {
1a91de28 2126 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2127 goto err_xrcd_table_free;
225c7b1f
RD		 2128 }
2129
fe6f700d
YP		 2130 if (!mlx4_is_slave(dev)) {
2131 err = mlx4_init_mcg_table(dev);
2132 if (err) {
1a91de28 2133 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2134 goto err_mr_table_free;
2135 }
114840c3
JM		 2136 err = mlx4_config_mad_demux(dev);
2137 if (err) {
2138 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2139 goto err_mcg_table_free;
2140 }
fe6f700d
YP		 2141 }
2142
225c7b1f
RD		 2143 err = mlx4_init_eq_table(dev);
2144 if (err) {
1a91de28 2145 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2146 goto err_mcg_table_free;
225c7b1f
RD		 2147 }
2148
2149 err = mlx4_cmd_use_events(dev);
2150 if (err) {
1a91de28 2151 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2152 goto err_eq_table_free;
2153 }
2154
2155 err = mlx4_NOP(dev);
2156 if (err) {
08fb1055 2157 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2158 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
b8dd786f 2159 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1a91de28 2160 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2161 } else {
1a91de28 2162 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
b8dd786f 2163 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 2164 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2165 }
225c7b1f
RD		 2166
2167 goto err_cmd_poll;
2168 }
2169
2170 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2171
2172 err = mlx4_init_cq_table(dev);
2173 if (err) {
1a91de28 2174 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2175 goto err_cmd_poll;
2176 }
2177
2178 err = mlx4_init_srq_table(dev);
2179 if (err) {
1a91de28 2180 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2181 goto err_cq_table_free;
2182 }
2183
2184 err = mlx4_init_qp_table(dev);
2185 if (err) {
1a91de28 2186 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2187 goto err_srq_table_free;
2188 }
2189
f2a3f6a3
OG		 2190 err = mlx4_init_counters_table(dev);
2191 if (err && err != -ENOENT) {
1a91de28 2192 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
fe6f700d 2193 goto err_qp_table_free;
f2a3f6a3
OG		 2194 }
2195
ab9c17a0
JM		 2196 if (!mlx4_is_slave(dev)) {
2197 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2198 ib_port_default_caps = 0;
2199 err = mlx4_get_port_ib_caps(dev, port,
2200 &ib_port_default_caps);
2201 if (err)
1a91de28
JP		 2202 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2203 port, err);
ab9c17a0
JM		 2204 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2205
2aca1172
JM		 2206 /* initialize per-slave default ib port capabilities */
2207 if (mlx4_is_master(dev)) {
2208 int i;
2209 for (i = 0; i < dev->num_slaves; i++) {
2210 if (i == mlx4_master_func_num(dev))
2211 continue;
2212 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2213 ib_port_default_caps;
2aca1172
JM		 2214 }
2215 }
2216
096335b3
OG		 2217 if (mlx4_is_mfunc(dev))
2218 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2219 else
2220 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2221
6634961c
JM		 2222 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2223 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2224 if (err) {
2225 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2226 port);
ab9c17a0
JM		 2227 goto err_counters_table_free;
2228 }
7ff93f8b
YP		 2229 }
2230 }
2231
225c7b1f
RD		 2232 return 0;
2233
f2a3f6a3
OG		 2234err_counters_table_free:
2235 mlx4_cleanup_counters_table(dev);
2236
225c7b1f
RD		 2237err_qp_table_free:
2238 mlx4_cleanup_qp_table(dev);
2239
2240err_srq_table_free:
2241 mlx4_cleanup_srq_table(dev);
2242
2243err_cq_table_free:
2244 mlx4_cleanup_cq_table(dev);
2245
2246err_cmd_poll:
2247 mlx4_cmd_use_polling(dev);
2248
2249err_eq_table_free:
2250 mlx4_cleanup_eq_table(dev);
2251
fe6f700d
YP		 2252err_mcg_table_free:
2253 if (!mlx4_is_slave(dev))
2254 mlx4_cleanup_mcg_table(dev);
2255
ee49bd93 2256err_mr_table_free:
225c7b1f
RD		 2257 mlx4_cleanup_mr_table(dev);
2258
012a8ff5
SH		 2259err_xrcd_table_free:
2260 mlx4_cleanup_xrcd_table(dev);
2261
225c7b1f
RD		 2262err_pd_table_free:
2263 mlx4_cleanup_pd_table(dev);
2264
2265err_kar_unmap:
2266 iounmap(priv->kar);
2267
2268err_uar_free:
2269 mlx4_uar_free(dev, &priv->driver_uar);
2270
2271err_uar_table_free:
2272 mlx4_cleanup_uar_table(dev);
2273 return err;
2274}
2275
e8f9b2ed 2276static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2277{
2278 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2279 struct msix_entry *entries;
225c7b1f
RD		 2280 int i;
2281
2282 if (msi_x) {
7ae0e400
MB		 2283 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ;
2284
ca4c7b35
OG		 2285 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2286 nreq);
ab9c17a0 2287
b8dd786f
YP		 2288 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2289 if (!entries)
2290 goto no_msi;
2291
2292 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2293 entries[i].entry = i;
2294
66e2f9c1
AG		 2295 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
2296
2297 if (nreq < 0) {
5bf0da7d 2298 kfree(entries);
225c7b1f 2299 goto no_msi;
66e2f9c1 2300 } else if (nreq < MSIX_LEGACY_SZ +
1a91de28 2301 dev->caps.num_ports * MIN_MSIX_P_PORT) {
0b7ca5a9
YP		 2302 /*Working in legacy mode , all EQ's shared*/
2303 dev->caps.comp_pool = 0;
2304 dev->caps.num_comp_vectors = nreq - 1;
2305 } else {
2306 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2307 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2308 }
b8dd786f 2309 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2310 priv->eq_table.eq[i].irq = entries[i].vector;
2311
2312 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2313
2314 kfree(entries);
225c7b1f
RD		 2315 return;
2316 }
2317
2318no_msi:
b8dd786f 2319 dev->caps.num_comp_vectors = 1;
0b7ca5a9 2320 dev->caps.comp_pool = 0;
b8dd786f
YP		 2321
2322 for (i = 0; i < 2; ++i)
225c7b1f
RD		 2323 priv->eq_table.eq[i].irq = dev->pdev->irq;
2324}
2325
7ff93f8b 2326static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2327{
2328 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2329 int err = 0;
2a2336f8
YP		 2330
2331 info->dev = dev;
2332 info->port = port;
ab9c17a0 2333 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2334 mlx4_init_mac_table(dev, &info->mac_table);
2335 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2336 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2337 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2338 }
7ff93f8b
YP		 2339
2340 sprintf(info->dev_name, "mlx4_port%d", port);
2341 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2342 if (mlx4_is_mfunc(dev))
2343 info->port_attr.attr.mode = S_IRUGO;
2344 else {
2345 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2346 info->port_attr.store = set_port_type;
2347 }
7ff93f8b 2348 info->port_attr.show = show_port_type;
3691c964 2349 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 2350
2351 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2352 if (err) {
2353 mlx4_err(dev, "Failed to create file for port %d\n", port);
2354 info->port = -1;
2355 }
2356
096335b3
OG		 2357 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2358 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2359 if (mlx4_is_mfunc(dev))
2360 info->port_mtu_attr.attr.mode = S_IRUGO;
2361 else {
2362 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2363 info->port_mtu_attr.store = set_port_ib_mtu;
2364 }
2365 info->port_mtu_attr.show = show_port_ib_mtu;
2366 sysfs_attr_init(&info->port_mtu_attr.attr);
2367
2368 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2369 if (err) {
2370 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2371 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2372 info->port = -1;
2373 }
2374
7ff93f8b
YP		 2375 return err;
2376}
2377
2378static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2379{
2380 if (info->port < 0)
2381 return;
2382
2383 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 2384 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 2385}
2386
b12d93d6
YP		 2387static int mlx4_init_steering(struct mlx4_dev *dev)
2388{
2389 struct mlx4_priv *priv = mlx4_priv(dev);
2390 int num_entries = dev->caps.num_ports;
2391 int i, j;
2392
2393 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2394 if (!priv->steer)
2395 return -ENOMEM;
2396
45b51365 2397 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2398 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2399 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2400 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2401 }
b12d93d6
YP		 2402 return 0;
2403}
2404
2405static void mlx4_clear_steering(struct mlx4_dev *dev)
2406{
2407 struct mlx4_priv *priv = mlx4_priv(dev);
2408 struct mlx4_steer_index *entry, *tmp_entry;
2409 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2410 int num_entries = dev->caps.num_ports;
2411 int i, j;
2412
2413 for (i = 0; i < num_entries; i++) {
2414 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2415 list_for_each_entry_safe(pqp, tmp_pqp,
2416 &priv->steer[i].promisc_qps[j],
2417 list) {
2418 list_del(&pqp->list);
2419 kfree(pqp);
2420 }
2421 list_for_each_entry_safe(entry, tmp_entry,
2422 &priv->steer[i].steer_entries[j],
2423 list) {
2424 list_del(&entry->list);
2425 list_for_each_entry_safe(pqp, tmp_pqp,
2426 &entry->duplicates,
2427 list) {
2428 list_del(&pqp->list);
2429 kfree(pqp);
2430 }
2431 kfree(entry);
2432 }
2433 }
2434 }
2435 kfree(priv->steer);
2436}
2437
ab9c17a0
JM		 2438static int extended_func_num(struct pci_dev *pdev)
2439{
2440 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2441}
2442
2443#define MLX4_OWNER_BASE 0x8069c
2444#define MLX4_OWNER_SIZE 4
2445
2446static int mlx4_get_ownership(struct mlx4_dev *dev)
2447{
2448 void __iomem *owner;
2449 u32 ret;
2450
57dbf29a
KSS		 2451 if (pci_channel_offline(dev->pdev))
2452 return -EIO;
2453
ab9c17a0
JM		 2454 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2455 MLX4_OWNER_SIZE);
2456 if (!owner) {
2457 mlx4_err(dev, "Failed to obtain ownership bit\n");
2458 return -ENOMEM;
2459 }
2460
2461 ret = readl(owner);
2462 iounmap(owner);
2463 return (int) !!ret;
2464}
2465
2466static void mlx4_free_ownership(struct mlx4_dev *dev)
2467{
2468 void __iomem *owner;
2469
57dbf29a
KSS		 2470 if (pci_channel_offline(dev->pdev))
2471 return;
2472
ab9c17a0
JM		 2473 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2474 MLX4_OWNER_SIZE);
2475 if (!owner) {
2476 mlx4_err(dev, "Failed to obtain ownership bit\n");
2477 return;
2478 }
2479 writel(0, owner);
2480 msleep(1000);
2481 iounmap(owner);
2482}
2483
a0eacca9
MB		 2484#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2485 !!((flags) & MLX4_FLAG_MASTER))
2486
2487static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
2488 u8 total_vfs, int existing_vfs)
2489{
2490 u64 dev_flags = dev->flags;
da315679 2491 int err = 0;
a0eacca9 2492
da315679
MB		 2493 atomic_inc(&pf_loading);
2494 if (dev->flags & MLX4_FLAG_SRIOV) {
2495 if (existing_vfs != total_vfs) {
2496 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2497 existing_vfs, total_vfs);
2498 total_vfs = existing_vfs;
2499 }
2500 }
2501
2502 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
a0eacca9
MB		 2503 if (NULL == dev->dev_vfs) {
2504 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2505 goto disable_sriov;
da315679
MB		 2506 }
2507
2508 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
2509 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2510 err = pci_enable_sriov(pdev, total_vfs);
2511 }
2512 if (err) {
2513 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2514 err);
2515 goto disable_sriov;
2516 } else {
2517 mlx4_warn(dev, "Running in master mode\n");
2518 dev_flags |= MLX4_FLAG_SRIOV |
2519 MLX4_FLAG_MASTER;
2520 dev_flags &= ~MLX4_FLAG_SLAVE;
2521 dev->num_vfs = total_vfs;
a0eacca9
MB		 2522 }
2523 return dev_flags;
2524
2525disable_sriov:
da315679 2526 atomic_dec(&pf_loading);
a0eacca9
MB		 2527 dev->num_vfs = 0;
2528 kfree(dev->dev_vfs);
2529 return dev_flags & ~MLX4_FLAG_MASTER;
2530}
2531
de966c59
MB		 2532enum {
2533 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2534};
2535
2536static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
2537 int *nvfs)
2538{
2539 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
2540 /* Checking for 64 VFs as a limitation of CX2 */
2541 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
2542 requested_vfs >= 64) {
2543 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
2544 requested_vfs);
2545 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
2546 }
2547 return 0;
2548}
2549
e1c00e10
MD		 2550static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
2551 int total_vfs, int *nvfs, struct mlx4_priv *priv)
225c7b1f 2552{
225c7b1f 2553 struct mlx4_dev *dev;
e1c00e10 2554 unsigned sum = 0;
225c7b1f 2555 int err;
2a2336f8 2556 int port;
e1c00e10 2557 int i;
7ae0e400 2558 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 2559 int existing_vfs = 0;
225c7b1f 2560
e1c00e10 2561 dev = &priv->dev;
225c7b1f 2562
b581401e
RD		 2563 INIT_LIST_HEAD(&priv->ctx_list);
2564 spin_lock_init(&priv->ctx_lock);
225c7b1f 2565
7ff93f8b
YP		 2566 mutex_init(&priv->port_mutex);
2567
6296883c
YP		 2568 INIT_LIST_HEAD(&priv->pgdir_list);
2569 mutex_init(&priv->pgdir_mutex);
2570
c1b43dca
EC		 2571 INIT_LIST_HEAD(&priv->bf_list);
2572 mutex_init(&priv->bf_mutex);
2573
aca7a3ac 2574 dev->rev_id = pdev->revision;
6e7136ed 2575 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 2576
ab9c17a0 2577 /* Detect if this device is a virtual function */
839f1243 2578 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2579 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2580 dev->flags |= MLX4_FLAG_SLAVE;
2581 } else {
2582 /* We reset the device and enable SRIOV only for physical
2583 * devices. Try to claim ownership on the device;
2584 * if already taken, skip -- do not allow multiple PFs */
2585 err = mlx4_get_ownership(dev);
2586 if (err) {
2587 if (err < 0)
e1c00e10 2588 return err;
ab9c17a0 2589 else {
1a91de28 2590 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 2591 return -EINVAL;
ab9c17a0
JM		 2592 }
2593 }
aca7a3ac 2594
fe6f700d
YP		 2595 atomic_set(&priv->opreq_count, 0);
2596 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2597
ab9c17a0
JM		 2598 /*
2599 * Now reset the HCA before we touch the PCI capabilities or
2600 * attempt a firmware command, since a boot ROM may have left
2601 * the HCA in an undefined state.
2602 */
2603 err = mlx4_reset(dev);
2604 if (err) {
1a91de28 2605 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 2606 goto err_sriov;
ab9c17a0 2607 }
7ae0e400
MB		 2608
2609 if (total_vfs) {
7ae0e400 2610 dev->flags = MLX4_FLAG_MASTER;
da315679
MB		 2611 existing_vfs = pci_num_vf(pdev);
2612 if (existing_vfs)
2613 dev->flags |= MLX4_FLAG_SRIOV;
7ae0e400
MB		 2614 dev->num_vfs = total_vfs;
2615 }
225c7b1f
RD		 2616 }
2617
ab9c17a0 2618slave_start:
521130d1
EE		 2619 err = mlx4_cmd_init(dev);
2620 if (err) {
1a91de28 2621 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 2622 goto err_sriov;
2623 }
2624
2625 /* In slave functions, the communication channel must be initialized
2626 * before posting commands. Also, init num_slaves before calling
2627 * mlx4_init_hca */
2628 if (mlx4_is_mfunc(dev)) {
7ae0e400 2629 if (mlx4_is_master(dev)) {
ab9c17a0 2630 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 2631
2632 } else {
ab9c17a0 2633 dev->num_slaves = 0;
f356fcbe
JM		 2634 err = mlx4_multi_func_init(dev);
2635 if (err) {
1a91de28 2636 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 2637 goto err_cmd;
2638 }
2639 }
225c7b1f
RD		 2640 }
2641
a0eacca9
MB		 2642 err = mlx4_init_fw(dev);
2643 if (err) {
2644 mlx4_err(dev, "Failed to init fw, aborting.\n");
2645 goto err_mfunc;
2646 }
2647
7ae0e400 2648 if (mlx4_is_master(dev)) {
da315679 2649 /* when we hit the goto slave_start below, dev_cap already initialized */
7ae0e400
MB		 2650 if (!dev_cap) {
2651 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
2652
2653 if (!dev_cap) {
2654 err = -ENOMEM;
2655 goto err_fw;
2656 }
2657
2658 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2659 if (err) {
2660 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2661 goto err_fw;
2662 }
2663
de966c59
MB		 2664 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2665 goto err_fw;
2666
7ae0e400
MB		 2667 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2668 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
2669 existing_vfs);
2670
2671 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2672 dev->flags = dev_flags;
2673 if (!SRIOV_VALID_STATE(dev->flags)) {
2674 mlx4_err(dev, "Invalid SRIOV state\n");
2675 goto err_sriov;
2676 }
2677 err = mlx4_reset(dev);
2678 if (err) {
2679 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2680 goto err_sriov;
2681 }
2682 goto slave_start;
2683 }
2684 } else {
2685 /* Legacy mode FW requires SRIOV to be enabled before
2686 * doing QUERY_DEV_CAP, since max_eq's value is different if
2687 * SRIOV is enabled.
2688 */
2689 memset(dev_cap, 0, sizeof(*dev_cap));
2690 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2691 if (err) {
2692 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2693 goto err_fw;
2694 }
de966c59
MB		 2695
2696 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2697 goto err_fw;
7ae0e400
MB		 2698 }
2699 }
2700
225c7b1f 2701 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2702 if (err) {
2703 if (err == -EACCES) {
2704 /* Not primary Physical function
2705 * Running in slave mode */
ffc39f6d 2706 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 2707 /* We're not a PF */
2708 if (dev->flags & MLX4_FLAG_SRIOV) {
2709 if (!existing_vfs)
2710 pci_disable_sriov(pdev);
2711 if (mlx4_is_master(dev))
2712 atomic_dec(&pf_loading);
2713 dev->flags &= ~MLX4_FLAG_SRIOV;
2714 }
2715 if (!mlx4_is_slave(dev))
2716 mlx4_free_ownership(dev);
ab9c17a0
JM		 2717 dev->flags |= MLX4_FLAG_SLAVE;
2718 dev->flags &= ~MLX4_FLAG_MASTER;
2719 goto slave_start;
2720 } else
a0eacca9 2721 goto err_fw;
ab9c17a0
JM		 2722 }
2723
7ae0e400
MB		 2724 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2725 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, existing_vfs);
2726
2727 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
2728 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
2729 dev->flags = dev_flags;
2730 err = mlx4_cmd_init(dev);
2731 if (err) {
2732 /* Only VHCR is cleaned up, so could still
2733 * send FW commands
2734 */
2735 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
2736 goto err_close;
2737 }
2738 } else {
2739 dev->flags = dev_flags;
2740 }
2741
2742 if (!SRIOV_VALID_STATE(dev->flags)) {
2743 mlx4_err(dev, "Invalid SRIOV state\n");
2744 goto err_close;
2745 }
2746 }
2747
b912b2f8
EP		 2748 /* check if the device is functioning at its maximum possible speed.
2749 * No return code for this call, just warn the user in case of PCI
2750 * express device capabilities are under-satisfied by the bus.
2751 */
83d3459a
EP		 2752 if (!mlx4_is_slave(dev))
2753 mlx4_check_pcie_caps(dev);
b912b2f8 2754
ab9c17a0
JM		 2755 /* In master functions, the communication channel must be initialized
2756 * after obtaining its address from fw */
2757 if (mlx4_is_master(dev)) {
e1c00e10
MD		 2758 int ib_ports = 0;
2759
2760 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2761 ib_ports++;
2762
2763 if (ib_ports &&
2764 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2765 mlx4_err(dev,
2766 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2767 err = -EINVAL;
2768 goto err_close;
2769 }
2770 if (dev->caps.num_ports < 2 &&
2771 num_vfs_argc > 1) {
2772 err = -EINVAL;
2773 mlx4_err(dev,
2774 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2775 dev->caps.num_ports);
ab9c17a0
JM		 2776 goto err_close;
2777 }
e1c00e10 2778 memcpy(dev->nvfs, nvfs, sizeof(dev->nvfs));
dd41cc3b 2779
e1c00e10
MD		 2780 for (i = 0; i < sizeof(dev->nvfs)/sizeof(dev->nvfs[0]); i++) {
2781 unsigned j;
2782
2783 for (j = 0; j < dev->nvfs[i]; ++sum, ++j) {
2784 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
2785 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2786 dev->caps.num_ports;
1ab95d37
MB		 2787 }
2788 }
e1c00e10
MD		 2789
2790 /* In master functions, the communication channel
2791 * must be initialized after obtaining its address from fw
2792 */
2793 err = mlx4_multi_func_init(dev);
2794 if (err) {
2795 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
2796 goto err_close;
2797 }
ab9c17a0 2798 }
225c7b1f 2799
b8dd786f
YP		 2800 err = mlx4_alloc_eq_table(dev);
2801 if (err)
ab9c17a0 2802 goto err_master_mfunc;
b8dd786f 2803
0b7ca5a9 2804 priv->msix_ctl.pool_bm = 0;
730c41d5 2805 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2806
08fb1055 2807 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2808 if ((mlx4_is_mfunc(dev)) &&
2809 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2810 err = -ENOSYS;
1a91de28 2811 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 2812 goto err_free_eq;
ab9c17a0
JM		 2813 }
2814
2815 if (!mlx4_is_slave(dev)) {
2816 err = mlx4_init_steering(dev);
2817 if (err)
e1c00e10 2818 goto err_disable_msix;
ab9c17a0 2819 }
b12d93d6 2820
225c7b1f 2821 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2822 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2823 !mlx4_is_mfunc(dev)) {
08fb1055 2824 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2825 dev->caps.num_comp_vectors = 1;
2826 dev->caps.comp_pool = 0;
08fb1055
MT		 2827 pci_disable_msix(pdev);
2828 err = mlx4_setup_hca(dev);
2829 }
2830
225c7b1f 2831 if (err)
b12d93d6 2832 goto err_steer;
225c7b1f 2833
5a0d0a61
JM		 2834 mlx4_init_quotas(dev);
2835
7ff93f8b
YP		 2836 for (port = 1; port <= dev->caps.num_ports; port++) {
2837 err = mlx4_init_port_info(dev, port);
2838 if (err)
2839 goto err_port;
2840 }
2a2336f8 2841
225c7b1f
RD		 2842 err = mlx4_register_device(dev);
2843 if (err)
7ff93f8b 2844 goto err_port;
225c7b1f 2845
b046ffe5
EP		 2846 mlx4_request_modules(dev);
2847
27bf91d6
YP		 2848 mlx4_sense_init(dev);
2849 mlx4_start_sense(dev);
2850
befdf897 2851 priv->removed = 0;
225c7b1f 2852
e1a5ddc5
AV		 2853 if (mlx4_is_master(dev) && dev->num_vfs)
2854 atomic_dec(&pf_loading);
2855
da315679 2856 kfree(dev_cap);
225c7b1f
RD		 2857 return 0;
2858
7ff93f8b 2859err_port:
b4f77264 2860 for (--port; port >= 1; --port)
7ff93f8b
YP		 2861 mlx4_cleanup_port_info(&priv->port[port]);
2862
f2a3f6a3 2863 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2864 mlx4_cleanup_qp_table(dev);
2865 mlx4_cleanup_srq_table(dev);
2866 mlx4_cleanup_cq_table(dev);
2867 mlx4_cmd_use_polling(dev);
2868 mlx4_cleanup_eq_table(dev);
fe6f700d 2869 mlx4_cleanup_mcg_table(dev);
225c7b1f 2870 mlx4_cleanup_mr_table(dev);
012a8ff5 2871 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2872 mlx4_cleanup_pd_table(dev);
2873 mlx4_cleanup_uar_table(dev);
2874
b12d93d6 2875err_steer:
ab9c17a0
JM		 2876 if (!mlx4_is_slave(dev))
2877 mlx4_clear_steering(dev);
b12d93d6 2878
e1c00e10
MD		 2879err_disable_msix:
2880 if (dev->flags & MLX4_FLAG_MSI_X)
2881 pci_disable_msix(pdev);
2882
b8dd786f
YP		 2883err_free_eq:
2884 mlx4_free_eq_table(dev);
2885
ab9c17a0
JM		 2886err_master_mfunc:
2887 if (mlx4_is_master(dev))
2888 mlx4_multi_func_cleanup(dev);
2889
b38f2879 2890 if (mlx4_is_slave(dev)) {
99ec41d0 2891 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2892 kfree(dev->caps.qp0_tunnel);
2893 kfree(dev->caps.qp0_proxy);
2894 kfree(dev->caps.qp1_tunnel);
2895 kfree(dev->caps.qp1_proxy);
2896 }
2897
225c7b1f
RD		 2898err_close:
2899 mlx4_close_hca(dev);
2900
a0eacca9
MB		 2901err_fw:
2902 mlx4_close_fw(dev);
2903
ab9c17a0
JM		 2904err_mfunc:
2905 if (mlx4_is_slave(dev))
2906 mlx4_multi_func_cleanup(dev);
2907
225c7b1f 2908err_cmd:
ffc39f6d 2909 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 2910
ab9c17a0 2911err_sriov:
bbb07af4 2912 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs)
ab9c17a0
JM		 2913 pci_disable_sriov(pdev);
2914
e1a5ddc5
AV		 2915 if (mlx4_is_master(dev) && dev->num_vfs)
2916 atomic_dec(&pf_loading);
2917
1ab95d37
MB		 2918 kfree(priv->dev.dev_vfs);
2919
e1c00e10
MD		 2920 if (!mlx4_is_slave(dev))
2921 mlx4_free_ownership(dev);
2922
7ae0e400 2923 kfree(dev_cap);
e1c00e10
MD		 2924 return err;
2925}
2926
2927static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
2928 struct mlx4_priv *priv)
2929{
2930 int err;
2931 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2932 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2933 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2934 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2935 unsigned total_vfs = 0;
2936 unsigned int i;
2937
2938 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2939
2940 err = pci_enable_device(pdev);
2941 if (err) {
2942 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
2943 return err;
2944 }
2945
2946 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2947 * per port, we must limit the number of VFs to 63 (since their are
2948 * 128 MACs)
2949 */
2950 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2951 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2952 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
2953 if (nvfs[i] < 0) {
2954 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2955 err = -EINVAL;
2956 goto err_disable_pdev;
2957 }
2958 }
2959 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2960 i++) {
2961 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
2962 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2963 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2964 err = -EINVAL;
2965 goto err_disable_pdev;
2966 }
2967 }
2968 if (total_vfs >= MLX4_MAX_NUM_VF) {
2969 dev_err(&pdev->dev,
2970 "Requested more VF's (%d) than allowed (%d)\n",
2971 total_vfs, MLX4_MAX_NUM_VF - 1);
2972 err = -EINVAL;
2973 goto err_disable_pdev;
2974 }
2975
2976 for (i = 0; i < MLX4_MAX_PORTS; i++) {
2977 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2978 dev_err(&pdev->dev,
2979 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2980 nvfs[i] + nvfs[2], i + 1,
2981 MLX4_MAX_NUM_VF_P_PORT - 1);
2982 err = -EINVAL;
2983 goto err_disable_pdev;
2984 }
2985 }
2986
2987 /* Check for BARs. */
2988 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2989 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2990 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2991 pci_dev_data, pci_resource_flags(pdev, 0));
2992 err = -ENODEV;
2993 goto err_disable_pdev;
2994 }
2995 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2996 dev_err(&pdev->dev, "Missing UAR, aborting\n");
2997 err = -ENODEV;
2998 goto err_disable_pdev;
2999 }
3000
3001 err = pci_request_regions(pdev, DRV_NAME);
3002 if (err) {
3003 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3004 goto err_disable_pdev;
3005 }
3006
3007 pci_set_master(pdev);
3008
3009 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3010 if (err) {
3011 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3012 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3013 if (err) {
3014 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3015 goto err_release_regions;
3016 }
3017 }
3018 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3019 if (err) {
3020 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3021 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3022 if (err) {
3023 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3024 goto err_release_regions;
3025 }
3026 }
3027
3028 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3029 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3030 /* Detect if this device is a virtual function */
3031 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3032 /* When acting as pf, we normally skip vfs unless explicitly
3033 * requested to probe them.
3034 */
3035 if (total_vfs) {
3036 unsigned vfs_offset = 0;
3037
3038 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3039 vfs_offset + nvfs[i] < extended_func_num(pdev);
3040 vfs_offset += nvfs[i], i++)
3041 ;
3042 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3043 err = -ENODEV;
3044 goto err_release_regions;
3045 }
3046 if ((extended_func_num(pdev) - vfs_offset)
3047 > prb_vf[i]) {
3048 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3049 extended_func_num(pdev));
3050 err = -ENODEV;
3051 goto err_release_regions;
3052 }
3053 }
3054 }
3055
3056 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
3057 if (err)
3058 goto err_release_regions;
3059 return 0;
225c7b1f 3060
a01df0fe
RD		 3061err_release_regions:
3062 pci_release_regions(pdev);
225c7b1f
RD		 3063
3064err_disable_pdev:
3065 pci_disable_device(pdev);
3066 pci_set_drvdata(pdev, NULL);
3067 return err;
3068}
3069
1dd06ae8 3070static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 3071{
befdf897
WY		 3072 struct mlx4_priv *priv;
3073 struct mlx4_dev *dev;
e1c00e10 3074 int ret;
befdf897 3075
0a645e80 3076 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 3077
befdf897
WY		 3078 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
3079 if (!priv)
3080 return -ENOMEM;
3081
3082 dev = &priv->dev;
e1c00e10 3083 dev->pdev = pdev;
befdf897
WY		 3084 pci_set_drvdata(pdev, dev);
3085 priv->pci_dev_data = id->driver_data;
3086
e1c00e10
MD		 3087 ret = __mlx4_init_one(pdev, id->driver_data, priv);
3088 if (ret)
3089 kfree(priv);
3090
3091 return ret;
3d73c288
RD		 3092}
3093
e1c00e10 3094static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f
RD		 3095{
3096 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3097 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 3098 int pci_dev_data;
225c7b1f 3099 int p;
bbb07af4 3100 int active_vfs = 0;
225c7b1f 3101
befdf897
WY		 3102 if (priv->removed)
3103 return;
225c7b1f 3104
befdf897 3105 pci_dev_data = priv->pci_dev_data;
225c7b1f 3106
bbb07af4
JM		 3107 /* Disabling SR-IOV is not allowed while there are active vf's */
3108 if (mlx4_is_master(dev)) {
3109 active_vfs = mlx4_how_many_lives_vf(dev);
3110 if (active_vfs) {
3111 pr_warn("Removing PF when there are active VF's !!\n");
3112 pr_warn("Will not disable SR-IOV.\n");
3113 }
3114 }
befdf897
WY		 3115 mlx4_stop_sense(dev);
3116 mlx4_unregister_device(dev);
225c7b1f 3117
befdf897
WY		 3118 for (p = 1; p <= dev->caps.num_ports; p++) {
3119 mlx4_cleanup_port_info(&priv->port[p]);
3120 mlx4_CLOSE_PORT(dev, p);
3121 }
3122
3123 if (mlx4_is_master(dev))
3124 mlx4_free_resource_tracker(dev,
3125 RES_TR_FREE_SLAVES_ONLY);
3126
3127 mlx4_cleanup_counters_table(dev);
3128 mlx4_cleanup_qp_table(dev);
3129 mlx4_cleanup_srq_table(dev);
3130 mlx4_cleanup_cq_table(dev);
3131 mlx4_cmd_use_polling(dev);
3132 mlx4_cleanup_eq_table(dev);
3133 mlx4_cleanup_mcg_table(dev);
3134 mlx4_cleanup_mr_table(dev);
3135 mlx4_cleanup_xrcd_table(dev);
3136 mlx4_cleanup_pd_table(dev);
225c7b1f 3137
befdf897
WY		 3138 if (mlx4_is_master(dev))
3139 mlx4_free_resource_tracker(dev,
3140 RES_TR_FREE_STRUCTS_ONLY);
47605df9 3141
befdf897
WY		 3142 iounmap(priv->kar);
3143 mlx4_uar_free(dev, &priv->driver_uar);
3144 mlx4_cleanup_uar_table(dev);
3145 if (!mlx4_is_slave(dev))
3146 mlx4_clear_steering(dev);
3147 mlx4_free_eq_table(dev);
3148 if (mlx4_is_master(dev))
3149 mlx4_multi_func_cleanup(dev);
3150 mlx4_close_hca(dev);
a0eacca9 3151 mlx4_close_fw(dev);
befdf897
WY		 3152 if (mlx4_is_slave(dev))
3153 mlx4_multi_func_cleanup(dev);
ffc39f6d 3154 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 3155
befdf897
WY		 3156 if (dev->flags & MLX4_FLAG_MSI_X)
3157 pci_disable_msix(pdev);
bbb07af4 3158 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
befdf897
WY		 3159 mlx4_warn(dev, "Disabling SR-IOV\n");
3160 pci_disable_sriov(pdev);
a0eacca9 3161 dev->flags &= ~MLX4_FLAG_SRIOV;
e1a5ddc5 3162 dev->num_vfs = 0;
225c7b1f 3163 }
befdf897
WY		 3164
3165 if (!mlx4_is_slave(dev))
3166 mlx4_free_ownership(dev);
3167
99ec41d0 3168 kfree(dev->caps.qp0_qkey);
befdf897
WY		 3169 kfree(dev->caps.qp0_tunnel);
3170 kfree(dev->caps.qp0_proxy);
3171 kfree(dev->caps.qp1_tunnel);
3172 kfree(dev->caps.qp1_proxy);
3173 kfree(dev->dev_vfs);
3174
befdf897
WY		 3175 memset(priv, 0, sizeof(*priv));
3176 priv->pci_dev_data = pci_dev_data;
3177 priv->removed = 1;
3178}
3179
3180static void mlx4_remove_one(struct pci_dev *pdev)
3181{
3182 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3183 struct mlx4_priv *priv = mlx4_priv(dev);
3184
e1c00e10
MD		 3185 mlx4_unload_one(pdev);
3186 pci_release_regions(pdev);
3187 pci_disable_device(pdev);
befdf897
WY		 3188 kfree(priv);
3189 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 3190}
3191
ee49bd93
JM		 3192int mlx4_restart_one(struct pci_dev *pdev)
3193{
839f1243
RD		 3194 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3195 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 3196 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3197 int pci_dev_data, err, total_vfs;
839f1243
RD		 3198
3199 pci_dev_data = priv->pci_dev_data;
e1c00e10
MD		 3200 total_vfs = dev->num_vfs;
3201 memcpy(nvfs, dev->nvfs, sizeof(dev->nvfs));
3202
3203 mlx4_unload_one(pdev);
3204 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
3205 if (err) {
3206 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3207 __func__, pci_name(pdev), err);
3208 return err;
3209 }
3210
3211 return err;
ee49bd93
JM		 3212}
3213
9baa3c34 3214static const struct pci_device_id mlx4_pci_table[] = {
ab9c17a0 3215 /* MT25408 "Hermon" SDR */
ca3e57a5 3216 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3217 /* MT25408 "Hermon" DDR */
ca3e57a5 3218 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3219 /* MT25408 "Hermon" QDR */
ca3e57a5 3220 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3221 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 3222 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3223 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 3224 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3225 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 3226 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3227 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 3228 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3229 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 3230 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3231 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 3232 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3233 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 3234 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3235 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 3236 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3237 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 3238 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3239 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 3240 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3241 /* MT27500 Family [ConnectX-3] */
3242 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3243 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 3244 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3245 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3246 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3247 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3248 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3249 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3250 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3251 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3252 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3253 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3254 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3255 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3256 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 3257 { 0, }
3258};
3259
3260MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3261
57dbf29a
KSS		 3262static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3263 pci_channel_state_t state)
3264{
e1c00e10 3265 mlx4_unload_one(pdev);
57dbf29a
KSS		 3266
3267 return state == pci_channel_io_perm_failure ?
3268 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
3269}
3270
3271static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3272{
befdf897
WY		 3273 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3274 struct mlx4_priv *priv = mlx4_priv(dev);
3275 int ret;
97a5221f 3276
e1c00e10 3277 ret = __mlx4_init_one(pdev, priv->pci_dev_data, priv);
57dbf29a
KSS		 3278
3279 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3280}
3281
3646f0e5 3282static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 3283 .error_detected = mlx4_pci_err_detected,
3284 .slot_reset = mlx4_pci_slot_reset,
3285};
3286
225c7b1f
RD		 3287static struct pci_driver mlx4_driver = {
3288 .name = DRV_NAME,
3289 .id_table = mlx4_pci_table,
3290 .probe = mlx4_init_one,
e1c00e10 3291 .shutdown = mlx4_unload_one,
f57e6848 3292 .remove = mlx4_remove_one,
57dbf29a 3293 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 3294};
3295
7ff93f8b
YP		 3296static int __init mlx4_verify_params(void)
3297{
3298 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 3299 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 3300 return -1;
3301 }
3302
cb29688a 3303 if (log_num_vlan != 0)
c20862c8
AV		 3304 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3305 MLX4_LOG_NUM_VLANS);
7ff93f8b 3306
ecc8fb11
AV		 3307 if (use_prio != 0)
3308 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 3309
0498628f 3310 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 3311 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3312 log_mtts_per_seg);
ab6bf42e
EC		 3313 return -1;
3314 }
3315
ab9c17a0
JM		 3316 /* Check if module param for ports type has legal combination */
3317 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 3318 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 3319 port_type_array[0] = true;
3320 }
3321
7d077cd3
MB		 3322 if (mlx4_log_num_mgm_entry_size < -7 ||
3323 (mlx4_log_num_mgm_entry_size > 0 &&
3324 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3325 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
3326 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
1a91de28
JP		 3327 mlx4_log_num_mgm_entry_size,
3328 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3329 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 3330 return -1;
3331 }
3332
7ff93f8b
YP		 3333 return 0;
3334}
3335
225c7b1f
RD		 3336static int __init mlx4_init(void)
3337{
3338 int ret;
3339
7ff93f8b
YP		 3340 if (mlx4_verify_params())
3341 return -EINVAL;
3342
27bf91d6
YP		 3343 mlx4_catas_init();
3344
3345 mlx4_wq = create_singlethread_workqueue("mlx4");
3346 if (!mlx4_wq)
3347 return -ENOMEM;
ee49bd93 3348
225c7b1f 3349 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 3350 if (ret < 0)
3351 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3352 return ret < 0 ? ret : 0;
3353}
3354
3355static void __exit mlx4_cleanup(void)
3356{
3357 pci_unregister_driver(&mlx4_driver);
27bf91d6 3358 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3359}
3360
3361module_init(mlx4_init);
3362module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)