projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'mac80211-for-davem-2015-01-15' of git://git.kernel.org/pub/scm/linux/kerne...
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
dd41cc3b 80static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 81static int num_vfs_argc;
dd41cc3b
MB		 82module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 87static int probe_vfs_argc;
dd41cc3b
MB		 88module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
ab9c17a0 91
3c439b55 92int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 93module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
3c439b55 97 " 10 gives 248.range: 7 <="
0ff1fb65 98 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 99 " To activate device managed"
100 " flow steering when available, set to -1");
0ec2c0f8 101
be902ab1 102static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 103module_param(enable_64b_cqe_eqe, bool, 0444);
104MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 106
77507aa2 107#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
7d077cd3
MB		 108 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
109 MLX4_FUNC_CAP_DMFS_A0_STATIC)
ab9c17a0 110
f57e6848 111static char mlx4_version[] =
225c7b1f
RD		 112 DRV_NAME ": Mellanox ConnectX core driver v"
113 DRV_VERSION " (" DRV_RELDATE ")\n";
114
115static struct mlx4_profile default_profile = {
ab9c17a0 116 .num_qp = 1 << 18,
225c7b1f 117 .num_srq = 1 << 16,
c9f2ba5e 118 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 119 .num_cq = 1 << 16,
120 .num_mcg = 1 << 13,
ab9c17a0 121 .num_mpt = 1 << 19,
9fd7a1e1 122 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 123};
124
2599d858
AV		 125static struct mlx4_profile low_mem_profile = {
126 .num_qp = 1 << 17,
127 .num_srq = 1 << 6,
128 .rdmarc_per_qp = 1 << 4,
129 .num_cq = 1 << 8,
130 .num_mcg = 1 << 8,
131 .num_mpt = 1 << 9,
132 .num_mtt = 1 << 7,
133};
134
ab9c17a0 135static int log_num_mac = 7;
93fc9e1b
YP		 136module_param_named(log_num_mac, log_num_mac, int, 0444);
137MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
138
139static int log_num_vlan;
140module_param_named(log_num_vlan, log_num_vlan, int, 0444);
141MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 142/* Log2 max number of VLANs per ETH port (0-7) */
143#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 144#define MLX4_MIN_LOG_NUM_VLANS 0
145#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 146
eb939922 147static bool use_prio;
93fc9e1b 148module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 149MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 150
2b8fb286 151int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 152module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 153MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 154
8d0fc7b6 155static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 156static int arr_argc = 2;
157module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 158MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
159 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 160
161struct mlx4_port_config {
162 struct list_head list;
163 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
164 struct pci_dev *pdev;
165};
166
97989356
AV		 167static atomic_t pf_loading = ATOMIC_INIT(0);
168
27bf91d6
YP		 169int mlx4_check_port_params(struct mlx4_dev *dev,
170 enum mlx4_port_type *port_type)
7ff93f8b
YP		 171{
172 int i;
173
0b997657
YS		 174 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
175 for (i = 0; i < dev->caps.num_ports - 1; i++) {
176 if (port_type[i] != port_type[i + 1]) {
1a91de28 177 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 178 return -EINVAL;
179 }
7ff93f8b
YP		 180 }
181 }
7ff93f8b
YP		 182
183 for (i = 0; i < dev->caps.num_ports; i++) {
184 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 185 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
186 i + 1);
7ff93f8b
YP		 187 return -EINVAL;
188 }
189 }
190 return 0;
191}
192
193static void mlx4_set_port_mask(struct mlx4_dev *dev)
194{
195 int i;
196
7ff93f8b 197 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 198 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 199}
f2a3f6a3 200
7ae0e400
MB		 201enum {
202 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
203};
204
205static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
206{
207 int err = 0;
208 struct mlx4_func func;
209
210 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
211 err = mlx4_QUERY_FUNC(dev, &func, 0);
212 if (err) {
213 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
214 return err;
215 }
216 dev_cap->max_eqs = func.max_eq;
217 dev_cap->reserved_eqs = func.rsvd_eqs;
218 dev_cap->reserved_uars = func.rsvd_uars;
219 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
220 }
221 return err;
222}
223
77507aa2
IS		 224static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
225{
226 struct mlx4_caps *dev_cap = &dev->caps;
227
228 /* FW not supporting or cancelled by user */
229 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
230 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
231 return;
232
233 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
234 * When FW has NCSI it may decide not to report 64B CQE/EQEs
235 */
236 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
237 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
238 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
239 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
240 return;
241 }
242
243 if (cache_line_size() == 128 || cache_line_size() == 256) {
244 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
245 /* Changing the real data inside CQE size to 32B */
246 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
247 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
248
249 if (mlx4_is_master(dev))
250 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
251 } else {
252 mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n");
253 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
254 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
255 }
256}
257
431df8c7
MB		 258static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
259 struct mlx4_port_cap *port_cap)
260{
261 dev->caps.vl_cap[port] = port_cap->max_vl;
262 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
263 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
264 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
265 /* set gid and pkey table operating lengths by default
266 * to non-sriov values
267 */
268 dev->caps.gid_table_len[port] = port_cap->max_gids;
269 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
270 dev->caps.port_width_cap[port] = port_cap->max_port_width;
271 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
272 dev->caps.def_mac[port] = port_cap->def_mac;
273 dev->caps.supported_type[port] = port_cap->supported_port_types;
274 dev->caps.suggested_type[port] = port_cap->suggested_type;
275 dev->caps.default_sense[port] = port_cap->default_sense;
276 dev->caps.trans_type[port] = port_cap->trans_type;
277 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
278 dev->caps.wavelength[port] = port_cap->wavelength;
279 dev->caps.trans_code[port] = port_cap->trans_code;
280
281 return 0;
282}
283
284static int mlx4_dev_port(struct mlx4_dev *dev, int port,
285 struct mlx4_port_cap *port_cap)
286{
287 int err = 0;
288
289 err = mlx4_QUERY_PORT(dev, port, port_cap);
290
291 if (err)
292 mlx4_err(dev, "QUERY_PORT command failed.\n");
293
294 return err;
295}
296
297#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 298static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 299{
300 int err;
5ae2a7a8 301 int i;
225c7b1f
RD		 302
303 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
304 if (err) {
1a91de28 305 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 306 return err;
307 }
c78e25ed 308 mlx4_dev_cap_dump(dev, dev_cap);
225c7b1f
RD		 309
310 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 311 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 312 dev_cap->min_page_sz, PAGE_SIZE);
313 return -ENODEV;
314 }
315 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 316 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 317 dev_cap->num_ports, MLX4_MAX_PORTS);
318 return -ENODEV;
319 }
320
321 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
1a91de28 322 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f
RD		 323 dev_cap->uar_size,
324 (unsigned long long) pci_resource_len(dev->pdev, 2));
325 return -ENODEV;
326 }
327
328 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 329 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
330 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
331 dev->caps.num_sys_eqs :
332 MLX4_MAX_EQ_NUM;
5ae2a7a8 333 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 334 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
335 if (err) {
336 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
337 return err;
338 }
5ae2a7a8
RD		 339 }
340
ab9c17a0 341 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 342 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 343 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
344 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
345 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
346 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
347 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
348 dev->caps.max_wqes = dev_cap->max_qp_sz;
349 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 350 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
351 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
352 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
353 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
354 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 355 /*
356 * Subtract 1 from the limit because we need to allocate a
357 * spare CQE so the HCA HW can tell the difference between an
358 * empty CQ and a full CQ.
359 */
360 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
361 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
362 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 363 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 364 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 365
366 /* The first 128 UARs are used for EQ doorbells */
367 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 368 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 369 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
370 dev_cap->reserved_xrcds : 0;
371 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
372 dev_cap->max_xrcds : 0;
2b8fb286
MA		 373 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
374
149983af 375 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 376 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
377 dev->caps.flags = dev_cap->flags;
b3416f44 378 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 379 dev->caps.bmme_flags = dev_cap->bmme_flags;
380 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 381 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 382 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 383 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 384
ca3e57a5
RD		 385 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
386 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 387 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 388 /* Don't do sense port on multifunction devices (for now at least) */
389 if (mlx4_is_mfunc(dev))
390 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 391
2599d858
AV		 392 if (mlx4_low_memory_profile()) {
393 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
394 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
395 } else {
396 dev->caps.log_num_macs = log_num_mac;
397 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
398 }
93fc9e1b
YP		 399
400 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 401 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
402 if (dev->caps.supported_type[i]) {
403 /* if only ETH is supported - assign ETH */
404 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
405 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 406 /* if only IB is supported, assign IB */
ab9c17a0 407 else if (dev->caps.supported_type[i] ==
105c320f
JM		 408 MLX4_PORT_TYPE_IB)
409 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 410 else {
105c320f
JM		 411 /* if IB and ETH are supported, we set the port
412 * type according to user selection of port type;
413 * if user selected none, take the FW hint */
414 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 415 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
416 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 417 else
105c320f 418 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 419 }
420 }
8d0fc7b6
YP		 421 /*
422 * Link sensing is allowed on the port if 3 conditions are true:
423 * 1. Both protocols are supported on the port.
424 * 2. Different types are supported on the port
425 * 3. FW declared that it supports link sensing
426 */
27bf91d6 427 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 428 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 429 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 430 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 431
8d0fc7b6
YP		 432 /*
433 * If "default_sense" bit is set, we move the port to "AUTO" mode
434 * and perform sense_port FW command to try and set the correct
435 * port type from beginning
436 */
46c46747 437 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 438 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
439 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
440 mlx4_SENSE_PORT(dev, i, &sensed_port);
441 if (sensed_port != MLX4_PORT_TYPE_NONE)
442 dev->caps.port_type[i] = sensed_port;
443 } else {
444 dev->caps.possible_type[i] = dev->caps.port_type[i];
445 }
446
431df8c7
MB		 447 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
448 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 449 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 450 i, 1 << dev->caps.log_num_macs);
451 }
431df8c7
MB		 452 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
453 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 454 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 455 i, 1 << dev->caps.log_num_vlans);
456 }
457 }
458
f2a3f6a3
OG		 459 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
460
93fc9e1b
YP		 461 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
462 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
463 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
464 (1 << dev->caps.log_num_macs) *
465 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 466 dev->caps.num_ports;
467 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
7d077cd3
MB		 468
469 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
470 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
471 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
472 else
473 dev->caps.dmfs_high_rate_qpn_base =
474 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
475
476 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
477 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
478 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
479 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
480 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
481 } else {
482 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
483 dev->caps.dmfs_high_rate_qpn_base =
484 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
485 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
486 }
487
d57febe1 488 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
7d077cd3 489 dev->caps.dmfs_high_rate_qpn_range;
93fc9e1b
YP		 490
491 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
492 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
493 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
494 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
495
e2c76824 496 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 497
b3051320 498 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 499 if (dev_cap->flags &
500 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
501 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
502 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
503 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
504 }
77507aa2
IS		 505
506 if (dev_cap->flags2 &
507 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
508 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
509 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
510 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
511 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
512 }
08ff3235
OG		 513 }
514
f97b4b5d 515 if ((dev->caps.flags &
08ff3235
OG		 516 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
517 mlx4_is_master(dev))
518 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
519
ddae0349 520 if (!mlx4_is_slave(dev)) {
77507aa2 521 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 522 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 523 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
524 MLX4_RESERVE_A0_QP;
ddae0349
EE		 525 } else {
526 dev->caps.alloc_res_qp_mask = 0;
527 }
77507aa2 528
225c7b1f
RD		 529 return 0;
530}
b912b2f8
EP		 531
532static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
533 enum pci_bus_speed *speed,
534 enum pcie_link_width *width)
535{
536 u32 lnkcap1, lnkcap2;
537 int err1, err2;
538
539#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
540
541 *speed = PCI_SPEED_UNKNOWN;
542 *width = PCIE_LNK_WIDTH_UNKNOWN;
543
544 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
545 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
546 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
547 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
548 *speed = PCIE_SPEED_8_0GT;
549 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
550 *speed = PCIE_SPEED_5_0GT;
551 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
552 *speed = PCIE_SPEED_2_5GT;
553 }
554 if (!err1) {
555 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
556 if (!lnkcap2) { /* pre-r3.0 */
557 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
558 *speed = PCIE_SPEED_5_0GT;
559 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
560 *speed = PCIE_SPEED_2_5GT;
561 }
562 }
563
564 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
565 return err1 ? err1 :
566 err2 ? err2 : -EINVAL;
567 }
568 return 0;
569}
570
571static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
572{
573 enum pcie_link_width width, width_cap;
574 enum pci_bus_speed speed, speed_cap;
575 int err;
576
577#define PCIE_SPEED_STR(speed) \
578 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
579 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
580 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
581 "Unknown")
582
583 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
584 if (err) {
585 mlx4_warn(dev,
586 "Unable to determine PCIe device BW capabilities\n");
587 return;
588 }
589
590 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
591 if (err || speed == PCI_SPEED_UNKNOWN ||
592 width == PCIE_LNK_WIDTH_UNKNOWN) {
593 mlx4_warn(dev,
594 "Unable to determine PCI device chain minimum BW\n");
595 return;
596 }
597
598 if (width != width_cap || speed != speed_cap)
599 mlx4_warn(dev,
600 "PCIe BW is different than device's capability\n");
601
602 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
603 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
604 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
605 width, width_cap);
606 return;
607}
608
ab9c17a0
JM		 609/*The function checks if there are live vf, return the num of them*/
610static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
611{
612 struct mlx4_priv *priv = mlx4_priv(dev);
613 struct mlx4_slave_state *s_state;
614 int i;
615 int ret = 0;
616
617 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
618 s_state = &priv->mfunc.master.slave_state[i];
619 if (s_state->active && s_state->last_cmd !=
620 MLX4_COMM_CMD_RESET) {
621 mlx4_warn(dev, "%s: slave: %d is still active\n",
622 __func__, i);
623 ret++;
624 }
625 }
626 return ret;
627}
628
396f2feb
JM		 629int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
630{
631 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 632
633 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
634 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 635 return -EINVAL;
636
47605df9 637 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 638 /* tunnel qp */
47605df9 639 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 640 else
47605df9 641 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 642 *qkey = qk;
643 return 0;
644}
645EXPORT_SYMBOL(mlx4_get_parav_qkey);
646
54679e14
JM		 647void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
648{
649 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
650
651 if (!mlx4_is_master(dev))
652 return;
653
654 priv->virt2phys_pkey[slave][port - 1][i] = val;
655}
656EXPORT_SYMBOL(mlx4_sync_pkey_table);
657
afa8fd1d
JM		 658void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
659{
660 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
661
662 if (!mlx4_is_master(dev))
663 return;
664
665 priv->slave_node_guids[slave] = guid;
666}
667EXPORT_SYMBOL(mlx4_put_slave_node_guid);
668
669__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
670{
671 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
672
673 if (!mlx4_is_master(dev))
674 return 0;
675
676 return priv->slave_node_guids[slave];
677}
678EXPORT_SYMBOL(mlx4_get_slave_node_guid);
679
e10903b0 680int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 681{
682 struct mlx4_priv *priv = mlx4_priv(dev);
683 struct mlx4_slave_state *s_slave;
684
685 if (!mlx4_is_master(dev))
686 return 0;
687
688 s_slave = &priv->mfunc.master.slave_state[slave];
689 return !!s_slave->active;
690}
691EXPORT_SYMBOL(mlx4_is_slave_active);
692
7b8157be
JM		 693static void slave_adjust_steering_mode(struct mlx4_dev *dev,
694 struct mlx4_dev_cap *dev_cap,
695 struct mlx4_init_hca_param *hca_param)
696{
697 dev->caps.steering_mode = hca_param->steering_mode;
698 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
699 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
700 dev->caps.fs_log_max_ucast_qp_range_size =
701 dev_cap->fs_log_max_ucast_qp_range_size;
702 } else
703 dev->caps.num_qp_per_mgm =
704 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
705
706 mlx4_dbg(dev, "Steering mode is: %s\n",
707 mlx4_steering_mode_str(dev->caps.steering_mode));
708}
709
ab9c17a0
JM		 710static int mlx4_slave_cap(struct mlx4_dev *dev)
711{
712 int err;
713 u32 page_size;
714 struct mlx4_dev_cap dev_cap;
715 struct mlx4_func_cap func_cap;
716 struct mlx4_init_hca_param hca_param;
225c6c8c 717 u8 i;
ab9c17a0
JM		 718
719 memset(&hca_param, 0, sizeof(hca_param));
720 err = mlx4_QUERY_HCA(dev, &hca_param);
721 if (err) {
1a91de28 722 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
ab9c17a0
JM		 723 return err;
724 }
725
483e0132
EP		 726 /* fail if the hca has an unknown global capability
727 * at this time global_caps should be always zeroed
728 */
729 if (hca_param.global_caps) {
ab9c17a0
JM		 730 mlx4_err(dev, "Unknown hca global capabilities\n");
731 return -ENOSYS;
732 }
733
734 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
735
ddd8a6c1
EE		 736 dev->caps.hca_core_clock = hca_param.hca_core_clock;
737
ab9c17a0 738 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 739 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 740 err = mlx4_dev_cap(dev, &dev_cap);
741 if (err) {
1a91de28 742 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 743 return err;
744 }
745
b91cb3eb
JM		 746 err = mlx4_QUERY_FW(dev);
747 if (err)
1a91de28 748 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 749
ab9c17a0
JM		 750 page_size = ~dev->caps.page_size_cap + 1;
751 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
752 if (page_size > PAGE_SIZE) {
1a91de28 753 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0
JM		 754 page_size, PAGE_SIZE);
755 return -ENODEV;
756 }
757
758 /* slave gets uar page size from QUERY_HCA fw command */
759 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
760
761 /* TODO: relax this assumption */
762 if (dev->caps.uar_page_size != PAGE_SIZE) {
763 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
764 dev->caps.uar_page_size, PAGE_SIZE);
765 return -ENODEV;
766 }
767
768 memset(&func_cap, 0, sizeof(func_cap));
47605df9 769 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 770 if (err) {
1a91de28
JP		 771 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
772 err);
ab9c17a0
JM		 773 return err;
774 }
775
776 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
777 PF_CONTEXT_BEHAVIOUR_MASK) {
7d077cd3
MB		 778 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
779 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
ab9c17a0
JM		 780 return -ENOSYS;
781 }
782
ab9c17a0 783 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 784 dev->quotas.qp = func_cap.qp_quota;
785 dev->quotas.srq = func_cap.srq_quota;
786 dev->quotas.cq = func_cap.cq_quota;
787 dev->quotas.mpt = func_cap.mpt_quota;
788 dev->quotas.mtt = func_cap.mtt_quota;
789 dev->caps.num_qps = 1 << hca_param.log_num_qps;
790 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
791 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
792 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
793 dev->caps.num_eqs = func_cap.max_eq;
794 dev->caps.reserved_eqs = func_cap.reserved_eq;
ab9c17a0
JM		 795 dev->caps.num_pds = MLX4_NUM_PDS;
796 dev->caps.num_mgms = 0;
797 dev->caps.num_amgms = 0;
798
ab9c17a0 799 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 800 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
801 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 802 return -ENODEV;
803 }
804
99ec41d0 805 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
47605df9
JM		 806 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
807 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
808 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
809 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
810
811 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
99ec41d0
JM		 812 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
813 !dev->caps.qp0_qkey) {
47605df9
JM		 814 err = -ENOMEM;
815 goto err_mem;
816 }
817
6634961c 818 for (i = 1; i <= dev->caps.num_ports; ++i) {
225c6c8c 819 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
47605df9 820 if (err) {
1a91de28
JP		 821 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
822 i, err);
47605df9
JM		 823 goto err_mem;
824 }
99ec41d0 825 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
47605df9
JM		 826 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
827 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
828 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
829 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 830 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 831 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 832 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
833 &dev->caps.gid_table_len[i],
834 &dev->caps.pkey_table_len[i]))
47605df9 835 goto err_mem;
6634961c 836 }
6230bb23 837
ab9c17a0
JM		 838 if (dev->caps.uar_page_size * (dev->caps.num_uars -
839 dev->caps.reserved_uars) >
840 pci_resource_len(dev->pdev, 2)) {
1a91de28 841 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0
JM		 842 dev->caps.uar_page_size * dev->caps.num_uars,
843 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 844 goto err_mem;
ab9c17a0
JM		 845 }
846
08ff3235
OG		 847 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
848 dev->caps.eqe_size = 64;
849 dev->caps.eqe_factor = 1;
850 } else {
851 dev->caps.eqe_size = 32;
852 dev->caps.eqe_factor = 0;
853 }
854
855 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
856 dev->caps.cqe_size = 64;
77507aa2 857 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 858 } else {
859 dev->caps.cqe_size = 32;
860 }
861
77507aa2
IS		 862 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
863 dev->caps.eqe_size = hca_param.eqe_size;
864 dev->caps.eqe_factor = 0;
865 }
866
867 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
868 dev->caps.cqe_size = hca_param.cqe_size;
869 /* User still need to know when CQE > 32B */
870 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
871 }
872
f9bd2d7f 873 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 874 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 875
7b8157be
JM		 876 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
877
ddae0349
EE		 878 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
879 dev->caps.bf_reg_size)
880 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
881
d57febe1
MB		 882 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
883 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
884
ab9c17a0 885 return 0;
47605df9
JM		 886
887err_mem:
99ec41d0 888 kfree(dev->caps.qp0_qkey);
47605df9
JM		 889 kfree(dev->caps.qp0_tunnel);
890 kfree(dev->caps.qp0_proxy);
891 kfree(dev->caps.qp1_tunnel);
892 kfree(dev->caps.qp1_proxy);
99ec41d0
JM		 893 dev->caps.qp0_qkey = NULL;
894 dev->caps.qp0_tunnel = NULL;
895 dev->caps.qp0_proxy = NULL;
896 dev->caps.qp1_tunnel = NULL;
897 dev->caps.qp1_proxy = NULL;
47605df9
JM		 898
899 return err;
ab9c17a0 900}
225c7b1f 901
b046ffe5
EP		 902static void mlx4_request_modules(struct mlx4_dev *dev)
903{
904 int port;
905 int has_ib_port = false;
906 int has_eth_port = false;
907#define EN_DRV_NAME "mlx4_en"
908#define IB_DRV_NAME "mlx4_ib"
909
910 for (port = 1; port <= dev->caps.num_ports; port++) {
911 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
912 has_ib_port = true;
913 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
914 has_eth_port = true;
915 }
916
b046ffe5
EP		 917 if (has_eth_port)
918 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 919 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
920 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 921}
922
7ff93f8b
YP		 923/*
924 * Change the port configuration of the device.
925 * Every user of this function must hold the port mutex.
926 */
27bf91d6
YP		 927int mlx4_change_port_types(struct mlx4_dev *dev,
928 enum mlx4_port_type *port_types)
7ff93f8b
YP		 929{
930 int err = 0;
931 int change = 0;
932 int port;
933
934 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 935 /* Change the port type only if the new type is different
936 * from the current, and not set to Auto */
3d8f9308 937 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 938 change = 1;
7ff93f8b
YP		 939 }
940 if (change) {
941 mlx4_unregister_device(dev);
942 for (port = 1; port <= dev->caps.num_ports; port++) {
943 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 944 dev->caps.port_type[port] = port_types[port - 1];
6634961c 945 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 946 if (err) {
1a91de28
JP		 947 mlx4_err(dev, "Failed to set port %d, aborting\n",
948 port);
7ff93f8b
YP		 949 goto out;
950 }
951 }
952 mlx4_set_port_mask(dev);
953 err = mlx4_register_device(dev);
b046ffe5
EP		 954 if (err) {
955 mlx4_err(dev, "Failed to register device\n");
956 goto out;
957 }
958 mlx4_request_modules(dev);
7ff93f8b
YP		 959 }
960
961out:
962 return err;
963}
964
965static ssize_t show_port_type(struct device *dev,
966 struct device_attribute *attr,
967 char *buf)
968{
969 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
970 port_attr);
971 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 972 char type[8];
973
974 sprintf(type, "%s",
975 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
976 "ib" : "eth");
977 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
978 sprintf(buf, "auto (%s)\n", type);
979 else
980 sprintf(buf, "%s\n", type);
7ff93f8b 981
27bf91d6 982 return strlen(buf);
7ff93f8b
YP		 983}
984
985static ssize_t set_port_type(struct device *dev,
986 struct device_attribute *attr,
987 const char *buf, size_t count)
988{
989 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
990 port_attr);
991 struct mlx4_dev *mdev = info->dev;
992 struct mlx4_priv *priv = mlx4_priv(mdev);
993 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 994 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
0a984556 995 static DEFINE_MUTEX(set_port_type_mutex);
7ff93f8b
YP		 996 int i;
997 int err = 0;
998
0a984556
AV		 999 mutex_lock(&set_port_type_mutex);
1000
7ff93f8b
YP		 1001 if (!strcmp(buf, "ib\n"))
1002 info->tmp_type = MLX4_PORT_TYPE_IB;
1003 else if (!strcmp(buf, "eth\n"))
1004 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 1005 else if (!strcmp(buf, "auto\n"))
1006 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 1007 else {
1008 mlx4_err(mdev, "%s is not supported port type\n", buf);
0a984556
AV		 1009 err = -EINVAL;
1010 goto err_out;
7ff93f8b
YP		 1011 }
1012
27bf91d6 1013 mlx4_stop_sense(mdev);
7ff93f8b 1014 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 1015 /* Possible type is always the one that was delivered */
1016 mdev->caps.possible_type[info->port] = info->tmp_type;
1017
1018 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 1019 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 1020 mdev->caps.possible_type[i+1];
1021 if (types[i] == MLX4_PORT_TYPE_AUTO)
1022 types[i] = mdev->caps.port_type[i+1];
1023 }
7ff93f8b 1024
58a60168
YP		 1025 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1026 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1027 for (i = 1; i <= mdev->caps.num_ports; i++) {
1028 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1029 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1030 err = -EINVAL;
1031 }
1032 }
1033 }
1034 if (err) {
1a91de28 1035 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1036 goto out;
1037 }
1038
1039 mlx4_do_sense_ports(mdev, new_types, types);
1040
1041 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1042 if (err)
1043 goto out;
1044
27bf91d6
YP		 1045 /* We are about to apply the changes after the configuration
1046 * was verified, no need to remember the temporary types
1047 * any more */
1048 for (i = 0; i < mdev->caps.num_ports; i++)
1049 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1050
27bf91d6 1051 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1052
1053out:
27bf91d6 1054 mlx4_start_sense(mdev);
7ff93f8b 1055 mutex_unlock(&priv->port_mutex);
0a984556
AV		 1056err_out:
1057 mutex_unlock(&set_port_type_mutex);
1058
7ff93f8b
YP		 1059 return err ? err : count;
1060}
1061
096335b3
OG		 1062enum ibta_mtu {
1063 IB_MTU_256 = 1,
1064 IB_MTU_512 = 2,
1065 IB_MTU_1024 = 3,
1066 IB_MTU_2048 = 4,
1067 IB_MTU_4096 = 5
1068};
1069
1070static inline int int_to_ibta_mtu(int mtu)
1071{
1072 switch (mtu) {
1073 case 256: return IB_MTU_256;
1074 case 512: return IB_MTU_512;
1075 case 1024: return IB_MTU_1024;
1076 case 2048: return IB_MTU_2048;
1077 case 4096: return IB_MTU_4096;
1078 default: return -1;
1079 }
1080}
1081
1082static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1083{
1084 switch (mtu) {
1085 case IB_MTU_256: return 256;
1086 case IB_MTU_512: return 512;
1087 case IB_MTU_1024: return 1024;
1088 case IB_MTU_2048: return 2048;
1089 case IB_MTU_4096: return 4096;
1090 default: return -1;
1091 }
1092}
1093
1094static ssize_t show_port_ib_mtu(struct device *dev,
1095 struct device_attribute *attr,
1096 char *buf)
1097{
1098 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1099 port_mtu_attr);
1100 struct mlx4_dev *mdev = info->dev;
1101
1102 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1103 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1104
1105 sprintf(buf, "%d\n",
1106 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1107 return strlen(buf);
1108}
1109
1110static ssize_t set_port_ib_mtu(struct device *dev,
1111 struct device_attribute *attr,
1112 const char *buf, size_t count)
1113{
1114 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1115 port_mtu_attr);
1116 struct mlx4_dev *mdev = info->dev;
1117 struct mlx4_priv *priv = mlx4_priv(mdev);
1118 int err, port, mtu, ibta_mtu = -1;
1119
1120 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1121 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1122 return -EINVAL;
1123 }
1124
618fad95
DB		 1125 err = kstrtoint(buf, 0, &mtu);
1126 if (!err)
096335b3
OG		 1127 ibta_mtu = int_to_ibta_mtu(mtu);
1128
618fad95 1129 if (err || ibta_mtu < 0) {
096335b3
OG		 1130 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1131 return -EINVAL;
1132 }
1133
1134 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1135
1136 mlx4_stop_sense(mdev);
1137 mutex_lock(&priv->port_mutex);
1138 mlx4_unregister_device(mdev);
1139 for (port = 1; port <= mdev->caps.num_ports; port++) {
1140 mlx4_CLOSE_PORT(mdev, port);
6634961c 1141 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1142 if (err) {
1a91de28
JP		 1143 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1144 port);
096335b3
OG		 1145 goto err_set_port;
1146 }
1147 }
1148 err = mlx4_register_device(mdev);
1149err_set_port:
1150 mutex_unlock(&priv->port_mutex);
1151 mlx4_start_sense(mdev);
1152 return err ? err : count;
1153}
1154
e8f9b2ed 1155static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1156{
1157 struct mlx4_priv *priv = mlx4_priv(dev);
1158 int err;
1159
1160 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1161 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1162 if (!priv->fw.fw_icm) {
1a91de28 1163 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1164 return -ENOMEM;
1165 }
1166
1167 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1168 if (err) {
1a91de28 1169 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1170 goto err_free;
1171 }
1172
1173 err = mlx4_RUN_FW(dev);
1174 if (err) {
1a91de28 1175 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1176 goto err_unmap_fa;
1177 }
1178
1179 return 0;
1180
1181err_unmap_fa:
1182 mlx4_UNMAP_FA(dev);
1183
1184err_free:
5b0bf5e2 1185 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1186 return err;
1187}
1188
e8f9b2ed
RD		 1189static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1190 int cmpt_entry_sz)
225c7b1f
RD		 1191{
1192 struct mlx4_priv *priv = mlx4_priv(dev);
1193 int err;
ab9c17a0 1194 int num_eqs;
225c7b1f
RD		 1195
1196 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1197 cmpt_base +
1198 ((u64) (MLX4_CMPT_TYPE_QP *
1199 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1200 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1201 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1202 0, 0);
225c7b1f
RD		 1203 if (err)
1204 goto err;
1205
1206 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1207 cmpt_base +
1208 ((u64) (MLX4_CMPT_TYPE_SRQ *
1209 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1210 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1211 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1212 if (err)
1213 goto err_qp;
1214
1215 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1216 cmpt_base +
1217 ((u64) (MLX4_CMPT_TYPE_CQ *
1218 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1219 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1220 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1221 if (err)
1222 goto err_srq;
1223
7ae0e400 1224 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1225 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1226 cmpt_base +
1227 ((u64) (MLX4_CMPT_TYPE_EQ *
1228 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1229 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1230 if (err)
1231 goto err_cq;
1232
1233 return 0;
1234
1235err_cq:
1236 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1237
1238err_srq:
1239 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1240
1241err_qp:
1242 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1243
1244err:
1245 return err;
1246}
1247
3d73c288
RD		 1248static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1249 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1250{
1251 struct mlx4_priv *priv = mlx4_priv(dev);
1252 u64 aux_pages;
ab9c17a0 1253 int num_eqs;
225c7b1f
RD		 1254 int err;
1255
1256 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1257 if (err) {
1a91de28 1258 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1259 return err;
1260 }
1261
1a91de28 1262 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1263 (unsigned long long) icm_size >> 10,
1264 (unsigned long long) aux_pages << 2);
1265
1266 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1267 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1268 if (!priv->fw.aux_icm) {
1a91de28 1269 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1270 return -ENOMEM;
1271 }
1272
1273 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1274 if (err) {
1a91de28 1275 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1276 goto err_free_aux;
1277 }
1278
1279 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1280 if (err) {
1a91de28 1281 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1282 goto err_unmap_aux;
1283 }
1284
ab9c17a0 1285
7ae0e400 1286 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1287 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1288 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1289 num_eqs, num_eqs, 0, 0);
225c7b1f 1290 if (err) {
1a91de28 1291 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1292 goto err_unmap_cmpt;
1293 }
1294
d7bb58fb
JM		 1295 /*
1296 * Reserved MTT entries must be aligned up to a cacheline
1297 * boundary, since the FW will write to them, while the driver
1298 * writes to all other MTT entries. (The variable
1299 * dev->caps.mtt_entry_sz below is really the MTT segment
1300 * size, not the raw entry size)
1301 */
1302 dev->caps.reserved_mtts =
1303 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1304 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1305
225c7b1f
RD		 1306 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1307 init_hca->mtt_base,
1308 dev->caps.mtt_entry_sz,
2b8fb286 1309 dev->caps.num_mtts,
5b0bf5e2 1310 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1311 if (err) {
1a91de28 1312 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1313 goto err_unmap_eq;
1314 }
1315
1316 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1317 init_hca->dmpt_base,
1318 dev_cap->dmpt_entry_sz,
1319 dev->caps.num_mpts,
5b0bf5e2 1320 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1321 if (err) {
1a91de28 1322 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1323 goto err_unmap_mtt;
1324 }
1325
1326 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1327 init_hca->qpc_base,
1328 dev_cap->qpc_entry_sz,
1329 dev->caps.num_qps,
93fc9e1b
YP		 1330 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1331 0, 0);
225c7b1f 1332 if (err) {
1a91de28 1333 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1334 goto err_unmap_dmpt;
1335 }
1336
1337 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1338 init_hca->auxc_base,
1339 dev_cap->aux_entry_sz,
1340 dev->caps.num_qps,
93fc9e1b
YP		 1341 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1342 0, 0);
225c7b1f 1343 if (err) {
1a91de28 1344 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1345 goto err_unmap_qp;
1346 }
1347
1348 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1349 init_hca->altc_base,
1350 dev_cap->altc_entry_sz,
1351 dev->caps.num_qps,
93fc9e1b
YP		 1352 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1353 0, 0);
225c7b1f 1354 if (err) {
1a91de28 1355 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1356 goto err_unmap_auxc;
1357 }
1358
1359 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1360 init_hca->rdmarc_base,
1361 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1362 dev->caps.num_qps,
93fc9e1b
YP		 1363 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1364 0, 0);
225c7b1f
RD		 1365 if (err) {
1366 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1367 goto err_unmap_altc;
1368 }
1369
1370 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1371 init_hca->cqc_base,
1372 dev_cap->cqc_entry_sz,
1373 dev->caps.num_cqs,
5b0bf5e2 1374 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1375 if (err) {
1a91de28 1376 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1377 goto err_unmap_rdmarc;
1378 }
1379
1380 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1381 init_hca->srqc_base,
1382 dev_cap->srq_entry_sz,
1383 dev->caps.num_srqs,
5b0bf5e2 1384 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1385 if (err) {
1a91de28 1386 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1387 goto err_unmap_cq;
1388 }
1389
1390 /*
0ff1fb65
HHZ		 1391 * For flow steering device managed mode it is required to use
1392 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1393 * required, but for simplicity just map the whole multicast
1394 * group table now. The table isn't very big and it's a lot
1395 * easier than trying to track ref counts.
225c7b1f
RD		 1396 */
1397 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1398 init_hca->mc_base,
1399 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1400 dev->caps.num_mgms + dev->caps.num_amgms,
1401 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1402 0, 0);
225c7b1f 1403 if (err) {
1a91de28 1404 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1405 goto err_unmap_srq;
1406 }
1407
1408 return 0;
1409
1410err_unmap_srq:
1411 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1412
1413err_unmap_cq:
1414 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1415
1416err_unmap_rdmarc:
1417 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1418
1419err_unmap_altc:
1420 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1421
1422err_unmap_auxc:
1423 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1424
1425err_unmap_qp:
1426 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1427
1428err_unmap_dmpt:
1429 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1430
1431err_unmap_mtt:
1432 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1433
1434err_unmap_eq:
fa0681d2 1435 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1436
1437err_unmap_cmpt:
1438 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1439 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1440 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1441 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1442
1443err_unmap_aux:
1444 mlx4_UNMAP_ICM_AUX(dev);
1445
1446err_free_aux:
5b0bf5e2 1447 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1448
1449 return err;
1450}
1451
1452static void mlx4_free_icms(struct mlx4_dev *dev)
1453{
1454 struct mlx4_priv *priv = mlx4_priv(dev);
1455
1456 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1457 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1458 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1459 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1460 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1461 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1462 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1463 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1464 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1465 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1466 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1467 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1468 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1469 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1470
1471 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1472 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1473}
1474
ab9c17a0
JM		 1475static void mlx4_slave_exit(struct mlx4_dev *dev)
1476{
1477 struct mlx4_priv *priv = mlx4_priv(dev);
1478
f3d4c89e 1479 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1480 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1a91de28 1481 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1482 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1483}
1484
c1b43dca
EC		 1485static int map_bf_area(struct mlx4_dev *dev)
1486{
1487 struct mlx4_priv *priv = mlx4_priv(dev);
1488 resource_size_t bf_start;
1489 resource_size_t bf_len;
1490 int err = 0;
1491
3d747473
JM		 1492 if (!dev->caps.bf_reg_size)
1493 return -ENXIO;
1494
ab9c17a0
JM		 1495 bf_start = pci_resource_start(dev->pdev, 2) +
1496 (dev->caps.num_uars << PAGE_SHIFT);
1497 bf_len = pci_resource_len(dev->pdev, 2) -
1498 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1499 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1500 if (!priv->bf_mapping)
1501 err = -ENOMEM;
1502
1503 return err;
1504}
1505
1506static void unmap_bf_area(struct mlx4_dev *dev)
1507{
1508 if (mlx4_priv(dev)->bf_mapping)
1509 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1510}
1511
ec693d47
AV		 1512cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1513{
1514 u32 clockhi, clocklo, clockhi1;
1515 cycle_t cycles;
1516 int i;
1517 struct mlx4_priv *priv = mlx4_priv(dev);
1518
1519 for (i = 0; i < 10; i++) {
1520 clockhi = swab32(readl(priv->clock_mapping));
1521 clocklo = swab32(readl(priv->clock_mapping + 4));
1522 clockhi1 = swab32(readl(priv->clock_mapping));
1523 if (clockhi == clockhi1)
1524 break;
1525 }
1526
1527 cycles = (u64) clockhi << 32 | (u64) clocklo;
1528
1529 return cycles;
1530}
1531EXPORT_SYMBOL_GPL(mlx4_read_clock);
1532
1533
ddd8a6c1
EE		 1534static int map_internal_clock(struct mlx4_dev *dev)
1535{
1536 struct mlx4_priv *priv = mlx4_priv(dev);
1537
1538 priv->clock_mapping =
1539 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1540 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1541
1542 if (!priv->clock_mapping)
1543 return -ENOMEM;
1544
1545 return 0;
1546}
1547
1548static void unmap_internal_clock(struct mlx4_dev *dev)
1549{
1550 struct mlx4_priv *priv = mlx4_priv(dev);
1551
1552 if (priv->clock_mapping)
1553 iounmap(priv->clock_mapping);
1554}
1555
225c7b1f
RD		 1556static void mlx4_close_hca(struct mlx4_dev *dev)
1557{
ddd8a6c1 1558 unmap_internal_clock(dev);
c1b43dca 1559 unmap_bf_area(dev);
ab9c17a0
JM		 1560 if (mlx4_is_slave(dev))
1561 mlx4_slave_exit(dev);
1562 else {
1563 mlx4_CLOSE_HCA(dev, 0);
1564 mlx4_free_icms(dev);
a0eacca9
MB		 1565 }
1566}
1567
1568static void mlx4_close_fw(struct mlx4_dev *dev)
1569{
1570 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1571 mlx4_UNMAP_FA(dev);
1572 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1573 }
1574}
1575
1576static int mlx4_init_slave(struct mlx4_dev *dev)
1577{
1578 struct mlx4_priv *priv = mlx4_priv(dev);
1579 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1580 int ret_from_reset = 0;
1581 u32 slave_read;
1582 u32 cmd_channel_ver;
1583
97989356 1584 if (atomic_read(&pf_loading)) {
1a91de28 1585 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 1586 return -EPROBE_DEFER;
1587 }
1588
f3d4c89e 1589 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1590 priv->cmd.max_cmds = 1;
1591 mlx4_warn(dev, "Sending reset\n");
1592 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1593 MLX4_COMM_TIME);
1594 /* if we are in the middle of flr the slave will try
1595 * NUM_OF_RESET_RETRIES times before leaving.*/
1596 if (ret_from_reset) {
1597 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 1598 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 1599 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1600 return -EPROBE_DEFER;
ab9c17a0
JM		 1601 } else
1602 goto err;
1603 }
1604
1605 /* check the driver version - the slave I/F revision
1606 * must match the master's */
1607 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1608 cmd_channel_ver = mlx4_comm_get_version();
1609
1610 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1611 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 1612 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 1613 goto err;
1614 }
1615
1616 mlx4_warn(dev, "Sending vhcr0\n");
1617 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1618 MLX4_COMM_TIME))
1619 goto err;
1620 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1621 MLX4_COMM_TIME))
1622 goto err;
1623 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1624 MLX4_COMM_TIME))
1625 goto err;
1626 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1627 goto err;
f3d4c89e
RD		 1628
1629 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1630 return 0;
1631
1632err:
1633 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1634 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1635 return -EIO;
225c7b1f
RD		 1636}
1637
6634961c
JM		 1638static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1639{
1640 int i;
1641
1642 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1643 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1644 dev->caps.gid_table_len[i] =
449fc488 1645 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1646 else
1647 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1648 dev->caps.pkey_table_len[i] =
1649 dev->phys_caps.pkey_phys_table_len[i] - 1;
1650 }
1651}
1652
3c439b55
JM		 1653static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1654{
1655 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1656
1657 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1658 i++) {
1659 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1660 break;
1661 }
1662
1663 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1664}
1665
7d077cd3
MB		 1666static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
1667{
1668 switch (dmfs_high_steer_mode) {
1669 case MLX4_STEERING_DMFS_A0_DEFAULT:
1670 return "default performance";
1671
1672 case MLX4_STEERING_DMFS_A0_DYNAMIC:
1673 return "dynamic hybrid mode";
1674
1675 case MLX4_STEERING_DMFS_A0_STATIC:
1676 return "performance optimized for limited rule configuration (static)";
1677
1678 case MLX4_STEERING_DMFS_A0_DISABLE:
1679 return "disabled performance optimized steering";
1680
1681 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
1682 return "performance optimized steering not supported";
1683
1684 default:
1685 return "Unrecognized mode";
1686 }
1687}
1688
1689#define MLX4_DMFS_A0_STEERING (1UL << 2)
1690
7b8157be
JM		 1691static void choose_steering_mode(struct mlx4_dev *dev,
1692 struct mlx4_dev_cap *dev_cap)
1693{
7d077cd3
MB		 1694 if (mlx4_log_num_mgm_entry_size <= 0) {
1695 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
1696 if (dev->caps.dmfs_high_steer_mode ==
1697 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1698 mlx4_err(dev, "DMFS high rate mode not supported\n");
1699 else
1700 dev->caps.dmfs_high_steer_mode =
1701 MLX4_STEERING_DMFS_A0_STATIC;
1702 }
1703 }
1704
1705 if (mlx4_log_num_mgm_entry_size <= 0 &&
3c439b55 1706 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1707 (!mlx4_is_mfunc(dev) ||
449fc488 1708 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) &&
3c439b55
JM		 1709 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1710 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1711 dev->oper_log_mgm_entry_size =
1712 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1713 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1714 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1715 dev->caps.fs_log_max_ucast_qp_range_size =
1716 dev_cap->fs_log_max_ucast_qp_range_size;
1717 } else {
7d077cd3
MB		 1718 if (dev->caps.dmfs_high_steer_mode !=
1719 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1720 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
7b8157be
JM		 1721 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1722 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1723 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1724 else {
1725 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1726
1727 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1728 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 1729 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 1730 }
3c439b55
JM		 1731 dev->oper_log_mgm_entry_size =
1732 mlx4_log_num_mgm_entry_size > 0 ?
1733 mlx4_log_num_mgm_entry_size :
1734 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1735 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1736 }
1a91de28 1737 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 1738 mlx4_steering_mode_str(dev->caps.steering_mode),
1739 dev->oper_log_mgm_entry_size,
1740 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1741}
1742
7ffdf726
OG		 1743static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1744 struct mlx4_dev_cap *dev_cap)
1745{
1746 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
7d077cd3
MB		 1747 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS &&
1748 dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
7ffdf726
OG		 1749 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1750 else
1751 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1752
1753 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1754 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1755}
1756
7d077cd3
MB		 1757static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
1758{
1759 int i;
1760 struct mlx4_port_cap port_cap;
1761
1762 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1763 return -EINVAL;
1764
1765 for (i = 1; i <= dev->caps.num_ports; i++) {
1766 if (mlx4_dev_port(dev, i, &port_cap)) {
1767 mlx4_err(dev,
1768 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
1769 } else if ((dev->caps.dmfs_high_steer_mode !=
1770 MLX4_STEERING_DMFS_A0_DEFAULT) &&
1771 (port_cap.dmfs_optimized_state ==
1772 !!(dev->caps.dmfs_high_steer_mode ==
1773 MLX4_STEERING_DMFS_A0_DISABLE))) {
1774 mlx4_err(dev,
1775 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
1776 dmfs_high_rate_steering_mode_str(
1777 dev->caps.dmfs_high_steer_mode),
1778 (port_cap.dmfs_optimized_state ?
1779 "enabled" : "disabled"));
1780 }
1781 }
1782
1783 return 0;
1784}
1785
a0eacca9 1786static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 1787{
2d928651 1788 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 1789 int err = 0;
225c7b1f 1790
ab9c17a0
JM		 1791 if (!mlx4_is_slave(dev)) {
1792 err = mlx4_QUERY_FW(dev);
1793 if (err) {
1794 if (err == -EACCES)
1a91de28 1795 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 1796 else
1a91de28 1797 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 1798 return err;
ab9c17a0 1799 }
225c7b1f 1800
ab9c17a0
JM		 1801 err = mlx4_load_fw(dev);
1802 if (err) {
1a91de28 1803 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 1804 return err;
ab9c17a0 1805 }
225c7b1f 1806
ab9c17a0
JM		 1807 mlx4_cfg.log_pg_sz_m = 1;
1808 mlx4_cfg.log_pg_sz = 0;
1809 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1810 if (err)
1811 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 1812 }
2d928651 1813
a0eacca9
MB		 1814 return err;
1815}
1816
1817static int mlx4_init_hca(struct mlx4_dev *dev)
1818{
1819 struct mlx4_priv *priv = mlx4_priv(dev);
1820 struct mlx4_adapter adapter;
1821 struct mlx4_dev_cap dev_cap;
1822 struct mlx4_profile profile;
1823 struct mlx4_init_hca_param init_hca;
1824 u64 icm_size;
1825 struct mlx4_config_dev_params params;
1826 int err;
1827
1828 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1829 err = mlx4_dev_cap(dev, &dev_cap);
1830 if (err) {
1a91de28 1831 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
d0d01250 1832 return err;
ab9c17a0 1833 }
225c7b1f 1834
7b8157be 1835 choose_steering_mode(dev, &dev_cap);
7ffdf726 1836 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1837
7d077cd3
MB		 1838 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
1839 mlx4_is_master(dev))
1840 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
1841
8e1a28e8
HHZ		 1842 err = mlx4_get_phys_port_id(dev);
1843 if (err)
1844 mlx4_err(dev, "Fail to get physical port id\n");
1845
6634961c
JM		 1846 if (mlx4_is_master(dev))
1847 mlx4_parav_master_pf_caps(dev);
1848
2599d858
AV		 1849 if (mlx4_low_memory_profile()) {
1850 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
1851 profile = low_mem_profile;
1852 } else {
1853 profile = default_profile;
1854 }
0ff1fb65
HHZ		 1855 if (dev->caps.steering_mode ==
1856 MLX4_STEERING_MODE_DEVICE_MANAGED)
1857 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1858
ab9c17a0
JM		 1859 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1860 &init_hca);
1861 if ((long long) icm_size < 0) {
1862 err = icm_size;
d0d01250 1863 return err;
ab9c17a0 1864 }
225c7b1f 1865
a5bbe892
EC		 1866 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1867
ab9c17a0
JM		 1868 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1869 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1870 init_hca.mw_enabled = 0;
1871 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1872 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1873 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1874
ab9c17a0
JM		 1875 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1876 if (err)
d0d01250 1877 return err;
225c7b1f 1878
ab9c17a0
JM		 1879 err = mlx4_INIT_HCA(dev, &init_hca);
1880 if (err) {
1a91de28 1881 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 1882 goto err_free_icm;
1883 }
7ae0e400
MB		 1884
1885 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
1886 err = mlx4_query_func(dev, &dev_cap);
1887 if (err < 0) {
1888 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
d0d01250 1889 goto err_close;
7ae0e400
MB		 1890 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
1891 dev->caps.num_eqs = dev_cap.max_eqs;
1892 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
1893 dev->caps.reserved_uars = dev_cap.reserved_uars;
1894 }
1895 }
1896
ddd8a6c1
EE		 1897 /*
1898 * If TS is supported by FW
1899 * read HCA frequency by QUERY_HCA command
1900 */
1901 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1902 memset(&init_hca, 0, sizeof(init_hca));
1903 err = mlx4_QUERY_HCA(dev, &init_hca);
1904 if (err) {
1a91de28 1905 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 1906 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1907 } else {
1908 dev->caps.hca_core_clock =
1909 init_hca.hca_core_clock;
1910 }
1911
1912 /* In case we got HCA frequency 0 - disable timestamping
1913 * to avoid dividing by zero
1914 */
1915 if (!dev->caps.hca_core_clock) {
1916 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1917 mlx4_err(dev,
1a91de28 1918 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 1919 } else if (map_internal_clock(dev)) {
1920 /*
1921 * Map internal clock,
1922 * in case of failure disable timestamping
1923 */
1924 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1925 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 1926 }
1927 }
7d077cd3
MB		 1928
1929 if (dev->caps.dmfs_high_steer_mode !=
1930 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
1931 if (mlx4_validate_optimized_steering(dev))
1932 mlx4_warn(dev, "Optimized steering validation failed\n");
1933
1934 if (dev->caps.dmfs_high_steer_mode ==
1935 MLX4_STEERING_DMFS_A0_DISABLE) {
1936 dev->caps.dmfs_high_rate_qpn_base =
1937 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1938 dev->caps.dmfs_high_rate_qpn_range =
1939 MLX4_A0_STEERING_TABLE_SIZE;
1940 }
1941
1942 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
1943 dmfs_high_rate_steering_mode_str(
1944 dev->caps.dmfs_high_steer_mode));
1945 }
ab9c17a0
JM		 1946 } else {
1947 err = mlx4_init_slave(dev);
1948 if (err) {
5efe5355
JM		 1949 if (err != -EPROBE_DEFER)
1950 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1951 return err;
ab9c17a0 1952 }
225c7b1f 1953
ab9c17a0
JM		 1954 err = mlx4_slave_cap(dev);
1955 if (err) {
1956 mlx4_err(dev, "Failed to obtain slave caps\n");
1957 goto err_close;
1958 }
225c7b1f
RD		 1959 }
1960
ab9c17a0
JM		 1961 if (map_bf_area(dev))
1962 mlx4_dbg(dev, "Failed to map blue flame area\n");
1963
1964 /*Only the master set the ports, all the rest got it from it.*/
1965 if (!mlx4_is_slave(dev))
1966 mlx4_set_port_mask(dev);
1967
225c7b1f
RD		 1968 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1969 if (err) {
1a91de28 1970 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 1971 goto unmap_bf;
225c7b1f
RD		 1972 }
1973
f8c6455b
SM		 1974 /* Query CONFIG_DEV parameters */
1975 err = mlx4_config_dev_retrieval(dev, &params);
1976 if (err && err != -ENOTSUPP) {
1977 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
1978 } else if (!err) {
1979 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
1980 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
1981 }
225c7b1f 1982 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1983 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1984
1985 return 0;
1986
bef772eb 1987unmap_bf:
ddd8a6c1 1988 unmap_internal_clock(dev);
bef772eb
AY		 1989 unmap_bf_area(dev);
1990
b38f2879 1991 if (mlx4_is_slave(dev)) {
99ec41d0 1992 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 1993 kfree(dev->caps.qp0_tunnel);
1994 kfree(dev->caps.qp0_proxy);
1995 kfree(dev->caps.qp1_tunnel);
1996 kfree(dev->caps.qp1_proxy);
1997 }
1998
225c7b1f 1999err_close:
41929ed2
DB		 2000 if (mlx4_is_slave(dev))
2001 mlx4_slave_exit(dev);
2002 else
2003 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 2004
2005err_free_icm:
ab9c17a0
JM		 2006 if (!mlx4_is_slave(dev))
2007 mlx4_free_icms(dev);
225c7b1f 2008
225c7b1f
RD		 2009 return err;
2010}
2011
f2a3f6a3
OG		 2012static int mlx4_init_counters_table(struct mlx4_dev *dev)
2013{
2014 struct mlx4_priv *priv = mlx4_priv(dev);
2015 int nent;
2016
2017 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2018 return -ENOENT;
2019
2020 nent = dev->caps.max_counters;
2021 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
2022}
2023
2024static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2025{
2026 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2027}
2028
ba062d52 2029int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 2030{
2031 struct mlx4_priv *priv = mlx4_priv(dev);
2032
2033 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2034 return -ENOENT;
2035
2036 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2037 if (*idx == -1)
2038 return -ENOMEM;
2039
2040 return 0;
2041}
ba062d52
JM		 2042
2043int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2044{
2045 u64 out_param;
2046 int err;
2047
2048 if (mlx4_is_mfunc(dev)) {
2049 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2050 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2051 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2052 if (!err)
2053 *idx = get_param_l(&out_param);
2054
2055 return err;
2056 }
2057 return __mlx4_counter_alloc(dev, idx);
2058}
f2a3f6a3
OG		 2059EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2060
ba062d52 2061void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 2062{
7c6d74d2 2063 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 2064 return;
2065}
ba062d52
JM		 2066
2067void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2068{
e7dbeba8 2069 u64 in_param = 0;
ba062d52
JM		 2070
2071 if (mlx4_is_mfunc(dev)) {
2072 set_param_l(&in_param, idx);
2073 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2074 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2075 MLX4_CMD_WRAPPED);
2076 return;
2077 }
2078 __mlx4_counter_free(dev, idx);
2079}
f2a3f6a3
OG		 2080EXPORT_SYMBOL_GPL(mlx4_counter_free);
2081
3d73c288 2082static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 2083{
2084 struct mlx4_priv *priv = mlx4_priv(dev);
2085 int err;
7ff93f8b 2086 int port;
9a5aa622 2087 __be32 ib_port_default_caps;
225c7b1f 2088
225c7b1f
RD		 2089 err = mlx4_init_uar_table(dev);
2090 if (err) {
1a91de28
JP		 2091 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2092 return err;
225c7b1f
RD		 2093 }
2094
2095 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2096 if (err) {
1a91de28 2097 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 2098 goto err_uar_table_free;
2099 }
2100
4979d18f 2101 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 2102 if (!priv->kar) {
1a91de28 2103 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 2104 err = -ENOMEM;
2105 goto err_uar_free;
2106 }
2107
2108 err = mlx4_init_pd_table(dev);
2109 if (err) {
1a91de28 2110 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2111 goto err_kar_unmap;
2112 }
2113
012a8ff5
SH		 2114 err = mlx4_init_xrcd_table(dev);
2115 if (err) {
1a91de28 2116 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2117 goto err_pd_table_free;
2118 }
2119
225c7b1f
RD		 2120 err = mlx4_init_mr_table(dev);
2121 if (err) {
1a91de28 2122 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2123 goto err_xrcd_table_free;
225c7b1f
RD		 2124 }
2125
fe6f700d
YP		 2126 if (!mlx4_is_slave(dev)) {
2127 err = mlx4_init_mcg_table(dev);
2128 if (err) {
1a91de28 2129 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2130 goto err_mr_table_free;
2131 }
114840c3
JM		 2132 err = mlx4_config_mad_demux(dev);
2133 if (err) {
2134 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2135 goto err_mcg_table_free;
2136 }
fe6f700d
YP		 2137 }
2138
225c7b1f
RD		 2139 err = mlx4_init_eq_table(dev);
2140 if (err) {
1a91de28 2141 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2142 goto err_mcg_table_free;
225c7b1f
RD		 2143 }
2144
2145 err = mlx4_cmd_use_events(dev);
2146 if (err) {
1a91de28 2147 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2148 goto err_eq_table_free;
2149 }
2150
2151 err = mlx4_NOP(dev);
2152 if (err) {
08fb1055 2153 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2154 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
b8dd786f 2155 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1a91de28 2156 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2157 } else {
1a91de28 2158 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
b8dd786f 2159 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 2160 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2161 }
225c7b1f
RD		 2162
2163 goto err_cmd_poll;
2164 }
2165
2166 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2167
2168 err = mlx4_init_cq_table(dev);
2169 if (err) {
1a91de28 2170 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2171 goto err_cmd_poll;
2172 }
2173
2174 err = mlx4_init_srq_table(dev);
2175 if (err) {
1a91de28 2176 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2177 goto err_cq_table_free;
2178 }
2179
2180 err = mlx4_init_qp_table(dev);
2181 if (err) {
1a91de28 2182 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2183 goto err_srq_table_free;
2184 }
2185
f2a3f6a3
OG		 2186 err = mlx4_init_counters_table(dev);
2187 if (err && err != -ENOENT) {
1a91de28 2188 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
fe6f700d 2189 goto err_qp_table_free;
f2a3f6a3
OG		 2190 }
2191
ab9c17a0
JM		 2192 if (!mlx4_is_slave(dev)) {
2193 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2194 ib_port_default_caps = 0;
2195 err = mlx4_get_port_ib_caps(dev, port,
2196 &ib_port_default_caps);
2197 if (err)
1a91de28
JP		 2198 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2199 port, err);
ab9c17a0
JM		 2200 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2201
2aca1172
JM		 2202 /* initialize per-slave default ib port capabilities */
2203 if (mlx4_is_master(dev)) {
2204 int i;
2205 for (i = 0; i < dev->num_slaves; i++) {
2206 if (i == mlx4_master_func_num(dev))
2207 continue;
2208 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2209 ib_port_default_caps;
2aca1172
JM		 2210 }
2211 }
2212
096335b3
OG		 2213 if (mlx4_is_mfunc(dev))
2214 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2215 else
2216 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2217
6634961c
JM		 2218 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2219 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2220 if (err) {
2221 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2222 port);
ab9c17a0
JM		 2223 goto err_counters_table_free;
2224 }
7ff93f8b
YP		 2225 }
2226 }
2227
225c7b1f
RD		 2228 return 0;
2229
f2a3f6a3
OG		 2230err_counters_table_free:
2231 mlx4_cleanup_counters_table(dev);
2232
225c7b1f
RD		 2233err_qp_table_free:
2234 mlx4_cleanup_qp_table(dev);
2235
2236err_srq_table_free:
2237 mlx4_cleanup_srq_table(dev);
2238
2239err_cq_table_free:
2240 mlx4_cleanup_cq_table(dev);
2241
2242err_cmd_poll:
2243 mlx4_cmd_use_polling(dev);
2244
2245err_eq_table_free:
2246 mlx4_cleanup_eq_table(dev);
2247
fe6f700d
YP		 2248err_mcg_table_free:
2249 if (!mlx4_is_slave(dev))
2250 mlx4_cleanup_mcg_table(dev);
2251
ee49bd93 2252err_mr_table_free:
225c7b1f
RD		 2253 mlx4_cleanup_mr_table(dev);
2254
012a8ff5
SH		 2255err_xrcd_table_free:
2256 mlx4_cleanup_xrcd_table(dev);
2257
225c7b1f
RD		 2258err_pd_table_free:
2259 mlx4_cleanup_pd_table(dev);
2260
2261err_kar_unmap:
2262 iounmap(priv->kar);
2263
2264err_uar_free:
2265 mlx4_uar_free(dev, &priv->driver_uar);
2266
2267err_uar_table_free:
2268 mlx4_cleanup_uar_table(dev);
2269 return err;
2270}
2271
e8f9b2ed 2272static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2273{
2274 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2275 struct msix_entry *entries;
225c7b1f
RD		 2276 int i;
2277
2278 if (msi_x) {
7ae0e400
MB		 2279 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ;
2280
ca4c7b35
OG		 2281 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2282 nreq);
ab9c17a0 2283
b8dd786f
YP		 2284 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2285 if (!entries)
2286 goto no_msi;
2287
2288 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2289 entries[i].entry = i;
2290
66e2f9c1
AG		 2291 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
2292
2293 if (nreq < 0) {
5bf0da7d 2294 kfree(entries);
225c7b1f 2295 goto no_msi;
66e2f9c1 2296 } else if (nreq < MSIX_LEGACY_SZ +
1a91de28 2297 dev->caps.num_ports * MIN_MSIX_P_PORT) {
0b7ca5a9
YP		 2298 /*Working in legacy mode , all EQ's shared*/
2299 dev->caps.comp_pool = 0;
2300 dev->caps.num_comp_vectors = nreq - 1;
2301 } else {
2302 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2303 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2304 }
b8dd786f 2305 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2306 priv->eq_table.eq[i].irq = entries[i].vector;
2307
2308 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2309
2310 kfree(entries);
225c7b1f
RD		 2311 return;
2312 }
2313
2314no_msi:
b8dd786f 2315 dev->caps.num_comp_vectors = 1;
0b7ca5a9 2316 dev->caps.comp_pool = 0;
b8dd786f
YP		 2317
2318 for (i = 0; i < 2; ++i)
225c7b1f
RD		 2319 priv->eq_table.eq[i].irq = dev->pdev->irq;
2320}
2321
7ff93f8b 2322static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2323{
2324 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2325 int err = 0;
2a2336f8
YP		 2326
2327 info->dev = dev;
2328 info->port = port;
ab9c17a0 2329 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2330 mlx4_init_mac_table(dev, &info->mac_table);
2331 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2332 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2333 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2334 }
7ff93f8b
YP		 2335
2336 sprintf(info->dev_name, "mlx4_port%d", port);
2337 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2338 if (mlx4_is_mfunc(dev))
2339 info->port_attr.attr.mode = S_IRUGO;
2340 else {
2341 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2342 info->port_attr.store = set_port_type;
2343 }
7ff93f8b 2344 info->port_attr.show = show_port_type;
3691c964 2345 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 2346
2347 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2348 if (err) {
2349 mlx4_err(dev, "Failed to create file for port %d\n", port);
2350 info->port = -1;
2351 }
2352
096335b3
OG		 2353 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2354 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2355 if (mlx4_is_mfunc(dev))
2356 info->port_mtu_attr.attr.mode = S_IRUGO;
2357 else {
2358 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2359 info->port_mtu_attr.store = set_port_ib_mtu;
2360 }
2361 info->port_mtu_attr.show = show_port_ib_mtu;
2362 sysfs_attr_init(&info->port_mtu_attr.attr);
2363
2364 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2365 if (err) {
2366 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2367 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2368 info->port = -1;
2369 }
2370
7ff93f8b
YP		 2371 return err;
2372}
2373
2374static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2375{
2376 if (info->port < 0)
2377 return;
2378
2379 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 2380 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 2381}
2382
b12d93d6
YP		 2383static int mlx4_init_steering(struct mlx4_dev *dev)
2384{
2385 struct mlx4_priv *priv = mlx4_priv(dev);
2386 int num_entries = dev->caps.num_ports;
2387 int i, j;
2388
2389 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2390 if (!priv->steer)
2391 return -ENOMEM;
2392
45b51365 2393 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2394 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2395 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2396 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2397 }
b12d93d6
YP		 2398 return 0;
2399}
2400
2401static void mlx4_clear_steering(struct mlx4_dev *dev)
2402{
2403 struct mlx4_priv *priv = mlx4_priv(dev);
2404 struct mlx4_steer_index *entry, *tmp_entry;
2405 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2406 int num_entries = dev->caps.num_ports;
2407 int i, j;
2408
2409 for (i = 0; i < num_entries; i++) {
2410 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2411 list_for_each_entry_safe(pqp, tmp_pqp,
2412 &priv->steer[i].promisc_qps[j],
2413 list) {
2414 list_del(&pqp->list);
2415 kfree(pqp);
2416 }
2417 list_for_each_entry_safe(entry, tmp_entry,
2418 &priv->steer[i].steer_entries[j],
2419 list) {
2420 list_del(&entry->list);
2421 list_for_each_entry_safe(pqp, tmp_pqp,
2422 &entry->duplicates,
2423 list) {
2424 list_del(&pqp->list);
2425 kfree(pqp);
2426 }
2427 kfree(entry);
2428 }
2429 }
2430 }
2431 kfree(priv->steer);
2432}
2433
ab9c17a0
JM		 2434static int extended_func_num(struct pci_dev *pdev)
2435{
2436 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2437}
2438
2439#define MLX4_OWNER_BASE 0x8069c
2440#define MLX4_OWNER_SIZE 4
2441
2442static int mlx4_get_ownership(struct mlx4_dev *dev)
2443{
2444 void __iomem *owner;
2445 u32 ret;
2446
57dbf29a
KSS		 2447 if (pci_channel_offline(dev->pdev))
2448 return -EIO;
2449
ab9c17a0
JM		 2450 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2451 MLX4_OWNER_SIZE);
2452 if (!owner) {
2453 mlx4_err(dev, "Failed to obtain ownership bit\n");
2454 return -ENOMEM;
2455 }
2456
2457 ret = readl(owner);
2458 iounmap(owner);
2459 return (int) !!ret;
2460}
2461
2462static void mlx4_free_ownership(struct mlx4_dev *dev)
2463{
2464 void __iomem *owner;
2465
57dbf29a
KSS		 2466 if (pci_channel_offline(dev->pdev))
2467 return;
2468
ab9c17a0
JM		 2469 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2470 MLX4_OWNER_SIZE);
2471 if (!owner) {
2472 mlx4_err(dev, "Failed to obtain ownership bit\n");
2473 return;
2474 }
2475 writel(0, owner);
2476 msleep(1000);
2477 iounmap(owner);
2478}
2479
a0eacca9
MB		 2480#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2481 !!((flags) & MLX4_FLAG_MASTER))
2482
2483static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
2484 u8 total_vfs, int existing_vfs)
2485{
2486 u64 dev_flags = dev->flags;
da315679 2487 int err = 0;
a0eacca9 2488
da315679
MB		 2489 atomic_inc(&pf_loading);
2490 if (dev->flags & MLX4_FLAG_SRIOV) {
2491 if (existing_vfs != total_vfs) {
2492 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2493 existing_vfs, total_vfs);
2494 total_vfs = existing_vfs;
2495 }
2496 }
2497
2498 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
a0eacca9
MB		 2499 if (NULL == dev->dev_vfs) {
2500 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2501 goto disable_sriov;
da315679
MB		 2502 }
2503
2504 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
2505 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2506 err = pci_enable_sriov(pdev, total_vfs);
2507 }
2508 if (err) {
2509 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2510 err);
2511 goto disable_sriov;
2512 } else {
2513 mlx4_warn(dev, "Running in master mode\n");
2514 dev_flags |= MLX4_FLAG_SRIOV |
2515 MLX4_FLAG_MASTER;
2516 dev_flags &= ~MLX4_FLAG_SLAVE;
2517 dev->num_vfs = total_vfs;
a0eacca9
MB		 2518 }
2519 return dev_flags;
2520
2521disable_sriov:
da315679 2522 atomic_dec(&pf_loading);
a0eacca9
MB		 2523 dev->num_vfs = 0;
2524 kfree(dev->dev_vfs);
2525 return dev_flags & ~MLX4_FLAG_MASTER;
2526}
2527
de966c59
MB		 2528enum {
2529 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2530};
2531
2532static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
2533 int *nvfs)
2534{
2535 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
2536 /* Checking for 64 VFs as a limitation of CX2 */
2537 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
2538 requested_vfs >= 64) {
2539 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
2540 requested_vfs);
2541 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
2542 }
2543 return 0;
2544}
2545
e1c00e10
MD		 2546static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
2547 int total_vfs, int *nvfs, struct mlx4_priv *priv)
225c7b1f 2548{
225c7b1f 2549 struct mlx4_dev *dev;
e1c00e10 2550 unsigned sum = 0;
225c7b1f 2551 int err;
2a2336f8 2552 int port;
e1c00e10 2553 int i;
7ae0e400 2554 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 2555 int existing_vfs = 0;
225c7b1f 2556
e1c00e10 2557 dev = &priv->dev;
225c7b1f 2558
b581401e
RD		 2559 INIT_LIST_HEAD(&priv->ctx_list);
2560 spin_lock_init(&priv->ctx_lock);
225c7b1f 2561
7ff93f8b
YP		 2562 mutex_init(&priv->port_mutex);
2563
6296883c
YP		 2564 INIT_LIST_HEAD(&priv->pgdir_list);
2565 mutex_init(&priv->pgdir_mutex);
2566
c1b43dca
EC		 2567 INIT_LIST_HEAD(&priv->bf_list);
2568 mutex_init(&priv->bf_mutex);
2569
aca7a3ac 2570 dev->rev_id = pdev->revision;
6e7136ed 2571 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 2572
ab9c17a0 2573 /* Detect if this device is a virtual function */
839f1243 2574 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2575 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2576 dev->flags |= MLX4_FLAG_SLAVE;
2577 } else {
2578 /* We reset the device and enable SRIOV only for physical
2579 * devices. Try to claim ownership on the device;
2580 * if already taken, skip -- do not allow multiple PFs */
2581 err = mlx4_get_ownership(dev);
2582 if (err) {
2583 if (err < 0)
e1c00e10 2584 return err;
ab9c17a0 2585 else {
1a91de28 2586 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 2587 return -EINVAL;
ab9c17a0
JM		 2588 }
2589 }
aca7a3ac 2590
fe6f700d
YP		 2591 atomic_set(&priv->opreq_count, 0);
2592 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2593
ab9c17a0
JM		 2594 /*
2595 * Now reset the HCA before we touch the PCI capabilities or
2596 * attempt a firmware command, since a boot ROM may have left
2597 * the HCA in an undefined state.
2598 */
2599 err = mlx4_reset(dev);
2600 if (err) {
1a91de28 2601 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 2602 goto err_sriov;
ab9c17a0 2603 }
7ae0e400
MB		 2604
2605 if (total_vfs) {
7ae0e400 2606 dev->flags = MLX4_FLAG_MASTER;
da315679
MB		 2607 existing_vfs = pci_num_vf(pdev);
2608 if (existing_vfs)
2609 dev->flags |= MLX4_FLAG_SRIOV;
7ae0e400
MB		 2610 dev->num_vfs = total_vfs;
2611 }
225c7b1f
RD		 2612 }
2613
ab9c17a0 2614slave_start:
521130d1
EE		 2615 err = mlx4_cmd_init(dev);
2616 if (err) {
1a91de28 2617 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 2618 goto err_sriov;
2619 }
2620
2621 /* In slave functions, the communication channel must be initialized
2622 * before posting commands. Also, init num_slaves before calling
2623 * mlx4_init_hca */
2624 if (mlx4_is_mfunc(dev)) {
7ae0e400 2625 if (mlx4_is_master(dev)) {
ab9c17a0 2626 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 2627
2628 } else {
ab9c17a0 2629 dev->num_slaves = 0;
f356fcbe
JM		 2630 err = mlx4_multi_func_init(dev);
2631 if (err) {
1a91de28 2632 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 2633 goto err_cmd;
2634 }
2635 }
225c7b1f
RD		 2636 }
2637
a0eacca9
MB		 2638 err = mlx4_init_fw(dev);
2639 if (err) {
2640 mlx4_err(dev, "Failed to init fw, aborting.\n");
2641 goto err_mfunc;
2642 }
2643
7ae0e400 2644 if (mlx4_is_master(dev)) {
da315679 2645 /* when we hit the goto slave_start below, dev_cap already initialized */
7ae0e400
MB		 2646 if (!dev_cap) {
2647 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
2648
2649 if (!dev_cap) {
2650 err = -ENOMEM;
2651 goto err_fw;
2652 }
2653
2654 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2655 if (err) {
2656 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2657 goto err_fw;
2658 }
2659
de966c59
MB		 2660 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2661 goto err_fw;
2662
7ae0e400
MB		 2663 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2664 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
2665 existing_vfs);
2666
2667 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2668 dev->flags = dev_flags;
2669 if (!SRIOV_VALID_STATE(dev->flags)) {
2670 mlx4_err(dev, "Invalid SRIOV state\n");
2671 goto err_sriov;
2672 }
2673 err = mlx4_reset(dev);
2674 if (err) {
2675 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2676 goto err_sriov;
2677 }
2678 goto slave_start;
2679 }
2680 } else {
2681 /* Legacy mode FW requires SRIOV to be enabled before
2682 * doing QUERY_DEV_CAP, since max_eq's value is different if
2683 * SRIOV is enabled.
2684 */
2685 memset(dev_cap, 0, sizeof(*dev_cap));
2686 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2687 if (err) {
2688 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2689 goto err_fw;
2690 }
de966c59
MB		 2691
2692 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2693 goto err_fw;
7ae0e400
MB		 2694 }
2695 }
2696
225c7b1f 2697 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2698 if (err) {
2699 if (err == -EACCES) {
2700 /* Not primary Physical function
2701 * Running in slave mode */
ffc39f6d 2702 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 2703 /* We're not a PF */
2704 if (dev->flags & MLX4_FLAG_SRIOV) {
2705 if (!existing_vfs)
2706 pci_disable_sriov(pdev);
2707 if (mlx4_is_master(dev))
2708 atomic_dec(&pf_loading);
2709 dev->flags &= ~MLX4_FLAG_SRIOV;
2710 }
2711 if (!mlx4_is_slave(dev))
2712 mlx4_free_ownership(dev);
ab9c17a0
JM		 2713 dev->flags |= MLX4_FLAG_SLAVE;
2714 dev->flags &= ~MLX4_FLAG_MASTER;
2715 goto slave_start;
2716 } else
a0eacca9 2717 goto err_fw;
ab9c17a0
JM		 2718 }
2719
7ae0e400
MB		 2720 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2721 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, existing_vfs);
2722
2723 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
2724 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
2725 dev->flags = dev_flags;
2726 err = mlx4_cmd_init(dev);
2727 if (err) {
2728 /* Only VHCR is cleaned up, so could still
2729 * send FW commands
2730 */
2731 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
2732 goto err_close;
2733 }
2734 } else {
2735 dev->flags = dev_flags;
2736 }
2737
2738 if (!SRIOV_VALID_STATE(dev->flags)) {
2739 mlx4_err(dev, "Invalid SRIOV state\n");
2740 goto err_close;
2741 }
2742 }
2743
b912b2f8
EP		 2744 /* check if the device is functioning at its maximum possible speed.
2745 * No return code for this call, just warn the user in case of PCI
2746 * express device capabilities are under-satisfied by the bus.
2747 */
83d3459a
EP		 2748 if (!mlx4_is_slave(dev))
2749 mlx4_check_pcie_caps(dev);
b912b2f8 2750
ab9c17a0
JM		 2751 /* In master functions, the communication channel must be initialized
2752 * after obtaining its address from fw */
2753 if (mlx4_is_master(dev)) {
e1c00e10
MD		 2754 int ib_ports = 0;
2755
2756 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2757 ib_ports++;
2758
2759 if (ib_ports &&
2760 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2761 mlx4_err(dev,
2762 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2763 err = -EINVAL;
2764 goto err_close;
2765 }
2766 if (dev->caps.num_ports < 2 &&
2767 num_vfs_argc > 1) {
2768 err = -EINVAL;
2769 mlx4_err(dev,
2770 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2771 dev->caps.num_ports);
ab9c17a0
JM		 2772 goto err_close;
2773 }
e1c00e10 2774 memcpy(dev->nvfs, nvfs, sizeof(dev->nvfs));
dd41cc3b 2775
e1c00e10
MD		 2776 for (i = 0; i < sizeof(dev->nvfs)/sizeof(dev->nvfs[0]); i++) {
2777 unsigned j;
2778
2779 for (j = 0; j < dev->nvfs[i]; ++sum, ++j) {
2780 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
2781 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2782 dev->caps.num_ports;
1ab95d37
MB		 2783 }
2784 }
e1c00e10
MD		 2785
2786 /* In master functions, the communication channel
2787 * must be initialized after obtaining its address from fw
2788 */
2789 err = mlx4_multi_func_init(dev);
2790 if (err) {
2791 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
2792 goto err_close;
2793 }
ab9c17a0 2794 }
225c7b1f 2795
b8dd786f
YP		 2796 err = mlx4_alloc_eq_table(dev);
2797 if (err)
ab9c17a0 2798 goto err_master_mfunc;
b8dd786f 2799
0b7ca5a9 2800 priv->msix_ctl.pool_bm = 0;
730c41d5 2801 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2802
08fb1055 2803 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2804 if ((mlx4_is_mfunc(dev)) &&
2805 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2806 err = -ENOSYS;
1a91de28 2807 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 2808 goto err_free_eq;
ab9c17a0
JM		 2809 }
2810
2811 if (!mlx4_is_slave(dev)) {
2812 err = mlx4_init_steering(dev);
2813 if (err)
e1c00e10 2814 goto err_disable_msix;
ab9c17a0 2815 }
b12d93d6 2816
225c7b1f 2817 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2818 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2819 !mlx4_is_mfunc(dev)) {
08fb1055 2820 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2821 dev->caps.num_comp_vectors = 1;
2822 dev->caps.comp_pool = 0;
08fb1055
MT		 2823 pci_disable_msix(pdev);
2824 err = mlx4_setup_hca(dev);
2825 }
2826
225c7b1f 2827 if (err)
b12d93d6 2828 goto err_steer;
225c7b1f 2829
5a0d0a61
JM		 2830 mlx4_init_quotas(dev);
2831
7ff93f8b
YP		 2832 for (port = 1; port <= dev->caps.num_ports; port++) {
2833 err = mlx4_init_port_info(dev, port);
2834 if (err)
2835 goto err_port;
2836 }
2a2336f8 2837
225c7b1f
RD		 2838 err = mlx4_register_device(dev);
2839 if (err)
7ff93f8b 2840 goto err_port;
225c7b1f 2841
b046ffe5
EP		 2842 mlx4_request_modules(dev);
2843
27bf91d6
YP		 2844 mlx4_sense_init(dev);
2845 mlx4_start_sense(dev);
2846
befdf897 2847 priv->removed = 0;
225c7b1f 2848
e1a5ddc5
AV		 2849 if (mlx4_is_master(dev) && dev->num_vfs)
2850 atomic_dec(&pf_loading);
2851
da315679 2852 kfree(dev_cap);
225c7b1f
RD		 2853 return 0;
2854
7ff93f8b 2855err_port:
b4f77264 2856 for (--port; port >= 1; --port)
7ff93f8b
YP		 2857 mlx4_cleanup_port_info(&priv->port[port]);
2858
f2a3f6a3 2859 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2860 mlx4_cleanup_qp_table(dev);
2861 mlx4_cleanup_srq_table(dev);
2862 mlx4_cleanup_cq_table(dev);
2863 mlx4_cmd_use_polling(dev);
2864 mlx4_cleanup_eq_table(dev);
fe6f700d 2865 mlx4_cleanup_mcg_table(dev);
225c7b1f 2866 mlx4_cleanup_mr_table(dev);
012a8ff5 2867 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2868 mlx4_cleanup_pd_table(dev);
2869 mlx4_cleanup_uar_table(dev);
2870
b12d93d6 2871err_steer:
ab9c17a0
JM		 2872 if (!mlx4_is_slave(dev))
2873 mlx4_clear_steering(dev);
b12d93d6 2874
e1c00e10
MD		 2875err_disable_msix:
2876 if (dev->flags & MLX4_FLAG_MSI_X)
2877 pci_disable_msix(pdev);
2878
b8dd786f
YP		 2879err_free_eq:
2880 mlx4_free_eq_table(dev);
2881
ab9c17a0
JM		 2882err_master_mfunc:
2883 if (mlx4_is_master(dev))
2884 mlx4_multi_func_cleanup(dev);
2885
b38f2879 2886 if (mlx4_is_slave(dev)) {
99ec41d0 2887 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2888 kfree(dev->caps.qp0_tunnel);
2889 kfree(dev->caps.qp0_proxy);
2890 kfree(dev->caps.qp1_tunnel);
2891 kfree(dev->caps.qp1_proxy);
2892 }
2893
225c7b1f
RD		 2894err_close:
2895 mlx4_close_hca(dev);
2896
a0eacca9
MB		 2897err_fw:
2898 mlx4_close_fw(dev);
2899
ab9c17a0
JM		 2900err_mfunc:
2901 if (mlx4_is_slave(dev))
2902 mlx4_multi_func_cleanup(dev);
2903
225c7b1f 2904err_cmd:
ffc39f6d 2905 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 2906
ab9c17a0 2907err_sriov:
bbb07af4 2908 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs)
ab9c17a0
JM		 2909 pci_disable_sriov(pdev);
2910
e1a5ddc5
AV		 2911 if (mlx4_is_master(dev) && dev->num_vfs)
2912 atomic_dec(&pf_loading);
2913
1ab95d37
MB		 2914 kfree(priv->dev.dev_vfs);
2915
e1c00e10
MD		 2916 if (!mlx4_is_slave(dev))
2917 mlx4_free_ownership(dev);
2918
7ae0e400 2919 kfree(dev_cap);
e1c00e10
MD		 2920 return err;
2921}
2922
2923static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
2924 struct mlx4_priv *priv)
2925{
2926 int err;
2927 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2928 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2929 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2930 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2931 unsigned total_vfs = 0;
2932 unsigned int i;
2933
2934 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2935
2936 err = pci_enable_device(pdev);
2937 if (err) {
2938 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
2939 return err;
2940 }
2941
2942 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2943 * per port, we must limit the number of VFs to 63 (since their are
2944 * 128 MACs)
2945 */
2946 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2947 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2948 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
2949 if (nvfs[i] < 0) {
2950 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2951 err = -EINVAL;
2952 goto err_disable_pdev;
2953 }
2954 }
2955 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2956 i++) {
2957 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
2958 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2959 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2960 err = -EINVAL;
2961 goto err_disable_pdev;
2962 }
2963 }
2964 if (total_vfs >= MLX4_MAX_NUM_VF) {
2965 dev_err(&pdev->dev,
2966 "Requested more VF's (%d) than allowed (%d)\n",
2967 total_vfs, MLX4_MAX_NUM_VF - 1);
2968 err = -EINVAL;
2969 goto err_disable_pdev;
2970 }
2971
2972 for (i = 0; i < MLX4_MAX_PORTS; i++) {
2973 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2974 dev_err(&pdev->dev,
2975 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2976 nvfs[i] + nvfs[2], i + 1,
2977 MLX4_MAX_NUM_VF_P_PORT - 1);
2978 err = -EINVAL;
2979 goto err_disable_pdev;
2980 }
2981 }
2982
2983 /* Check for BARs. */
2984 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2985 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2986 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2987 pci_dev_data, pci_resource_flags(pdev, 0));
2988 err = -ENODEV;
2989 goto err_disable_pdev;
2990 }
2991 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2992 dev_err(&pdev->dev, "Missing UAR, aborting\n");
2993 err = -ENODEV;
2994 goto err_disable_pdev;
2995 }
2996
2997 err = pci_request_regions(pdev, DRV_NAME);
2998 if (err) {
2999 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3000 goto err_disable_pdev;
3001 }
3002
3003 pci_set_master(pdev);
3004
3005 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3006 if (err) {
3007 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3008 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3009 if (err) {
3010 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3011 goto err_release_regions;
3012 }
3013 }
3014 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3015 if (err) {
3016 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3017 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3018 if (err) {
3019 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3020 goto err_release_regions;
3021 }
3022 }
3023
3024 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3025 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3026 /* Detect if this device is a virtual function */
3027 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3028 /* When acting as pf, we normally skip vfs unless explicitly
3029 * requested to probe them.
3030 */
3031 if (total_vfs) {
3032 unsigned vfs_offset = 0;
3033
3034 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3035 vfs_offset + nvfs[i] < extended_func_num(pdev);
3036 vfs_offset += nvfs[i], i++)
3037 ;
3038 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3039 err = -ENODEV;
3040 goto err_release_regions;
3041 }
3042 if ((extended_func_num(pdev) - vfs_offset)
3043 > prb_vf[i]) {
3044 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3045 extended_func_num(pdev));
3046 err = -ENODEV;
3047 goto err_release_regions;
3048 }
3049 }
3050 }
3051
3052 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
3053 if (err)
3054 goto err_release_regions;
3055 return 0;
225c7b1f 3056
a01df0fe
RD		 3057err_release_regions:
3058 pci_release_regions(pdev);
225c7b1f
RD		 3059
3060err_disable_pdev:
3061 pci_disable_device(pdev);
3062 pci_set_drvdata(pdev, NULL);
3063 return err;
3064}
3065
1dd06ae8 3066static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 3067{
befdf897
WY		 3068 struct mlx4_priv *priv;
3069 struct mlx4_dev *dev;
e1c00e10 3070 int ret;
befdf897 3071
0a645e80 3072 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 3073
befdf897
WY		 3074 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
3075 if (!priv)
3076 return -ENOMEM;
3077
3078 dev = &priv->dev;
e1c00e10 3079 dev->pdev = pdev;
befdf897
WY		 3080 pci_set_drvdata(pdev, dev);
3081 priv->pci_dev_data = id->driver_data;
3082
e1c00e10
MD		 3083 ret = __mlx4_init_one(pdev, id->driver_data, priv);
3084 if (ret)
3085 kfree(priv);
3086
3087 return ret;
3d73c288
RD		 3088}
3089
e1c00e10 3090static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f
RD		 3091{
3092 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3093 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 3094 int pci_dev_data;
225c7b1f 3095 int p;
bbb07af4 3096 int active_vfs = 0;
225c7b1f 3097
befdf897
WY		 3098 if (priv->removed)
3099 return;
225c7b1f 3100
befdf897 3101 pci_dev_data = priv->pci_dev_data;
225c7b1f 3102
bbb07af4
JM		 3103 /* Disabling SR-IOV is not allowed while there are active vf's */
3104 if (mlx4_is_master(dev)) {
3105 active_vfs = mlx4_how_many_lives_vf(dev);
3106 if (active_vfs) {
3107 pr_warn("Removing PF when there are active VF's !!\n");
3108 pr_warn("Will not disable SR-IOV.\n");
3109 }
3110 }
befdf897
WY		 3111 mlx4_stop_sense(dev);
3112 mlx4_unregister_device(dev);
225c7b1f 3113
befdf897
WY		 3114 for (p = 1; p <= dev->caps.num_ports; p++) {
3115 mlx4_cleanup_port_info(&priv->port[p]);
3116 mlx4_CLOSE_PORT(dev, p);
3117 }
3118
3119 if (mlx4_is_master(dev))
3120 mlx4_free_resource_tracker(dev,
3121 RES_TR_FREE_SLAVES_ONLY);
3122
3123 mlx4_cleanup_counters_table(dev);
3124 mlx4_cleanup_qp_table(dev);
3125 mlx4_cleanup_srq_table(dev);
3126 mlx4_cleanup_cq_table(dev);
3127 mlx4_cmd_use_polling(dev);
3128 mlx4_cleanup_eq_table(dev);
3129 mlx4_cleanup_mcg_table(dev);
3130 mlx4_cleanup_mr_table(dev);
3131 mlx4_cleanup_xrcd_table(dev);
3132 mlx4_cleanup_pd_table(dev);
225c7b1f 3133
befdf897
WY		 3134 if (mlx4_is_master(dev))
3135 mlx4_free_resource_tracker(dev,
3136 RES_TR_FREE_STRUCTS_ONLY);
47605df9 3137
befdf897
WY		 3138 iounmap(priv->kar);
3139 mlx4_uar_free(dev, &priv->driver_uar);
3140 mlx4_cleanup_uar_table(dev);
3141 if (!mlx4_is_slave(dev))
3142 mlx4_clear_steering(dev);
3143 mlx4_free_eq_table(dev);
3144 if (mlx4_is_master(dev))
3145 mlx4_multi_func_cleanup(dev);
3146 mlx4_close_hca(dev);
a0eacca9 3147 mlx4_close_fw(dev);
befdf897
WY		 3148 if (mlx4_is_slave(dev))
3149 mlx4_multi_func_cleanup(dev);
ffc39f6d 3150 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 3151
befdf897
WY		 3152 if (dev->flags & MLX4_FLAG_MSI_X)
3153 pci_disable_msix(pdev);
bbb07af4 3154 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
befdf897
WY		 3155 mlx4_warn(dev, "Disabling SR-IOV\n");
3156 pci_disable_sriov(pdev);
a0eacca9 3157 dev->flags &= ~MLX4_FLAG_SRIOV;
e1a5ddc5 3158 dev->num_vfs = 0;
225c7b1f 3159 }
befdf897
WY		 3160
3161 if (!mlx4_is_slave(dev))
3162 mlx4_free_ownership(dev);
3163
99ec41d0 3164 kfree(dev->caps.qp0_qkey);
befdf897
WY		 3165 kfree(dev->caps.qp0_tunnel);
3166 kfree(dev->caps.qp0_proxy);
3167 kfree(dev->caps.qp1_tunnel);
3168 kfree(dev->caps.qp1_proxy);
3169 kfree(dev->dev_vfs);
3170
befdf897
WY		 3171 memset(priv, 0, sizeof(*priv));
3172 priv->pci_dev_data = pci_dev_data;
3173 priv->removed = 1;
3174}
3175
3176static void mlx4_remove_one(struct pci_dev *pdev)
3177{
3178 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3179 struct mlx4_priv *priv = mlx4_priv(dev);
3180
e1c00e10
MD		 3181 mlx4_unload_one(pdev);
3182 pci_release_regions(pdev);
3183 pci_disable_device(pdev);
befdf897
WY		 3184 kfree(priv);
3185 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 3186}
3187
ee49bd93
JM		 3188int mlx4_restart_one(struct pci_dev *pdev)
3189{
839f1243
RD		 3190 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3191 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 3192 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3193 int pci_dev_data, err, total_vfs;
839f1243
RD		 3194
3195 pci_dev_data = priv->pci_dev_data;
e1c00e10
MD		 3196 total_vfs = dev->num_vfs;
3197 memcpy(nvfs, dev->nvfs, sizeof(dev->nvfs));
3198
3199 mlx4_unload_one(pdev);
3200 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
3201 if (err) {
3202 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3203 __func__, pci_name(pdev), err);
3204 return err;
3205 }
3206
3207 return err;
ee49bd93
JM		 3208}
3209
9baa3c34 3210static const struct pci_device_id mlx4_pci_table[] = {
ab9c17a0 3211 /* MT25408 "Hermon" SDR */
ca3e57a5 3212 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3213 /* MT25408 "Hermon" DDR */
ca3e57a5 3214 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3215 /* MT25408 "Hermon" QDR */
ca3e57a5 3216 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3217 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 3218 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3219 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 3220 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3221 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 3222 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3223 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 3224 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3225 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 3226 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3227 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 3228 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3229 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 3230 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3231 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 3232 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3233 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 3234 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3235 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 3236 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3237 /* MT27500 Family [ConnectX-3] */
3238 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3239 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 3240 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3241 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3242 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3243 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3244 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3245 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3246 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3247 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3248 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3249 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3250 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3251 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3252 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 3253 { 0, }
3254};
3255
3256MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3257
57dbf29a
KSS		 3258static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3259 pci_channel_state_t state)
3260{
e1c00e10 3261 mlx4_unload_one(pdev);
57dbf29a
KSS		 3262
3263 return state == pci_channel_io_perm_failure ?
3264 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
3265}
3266
3267static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3268{
befdf897
WY		 3269 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3270 struct mlx4_priv *priv = mlx4_priv(dev);
3271 int ret;
97a5221f 3272
e1c00e10 3273 ret = __mlx4_init_one(pdev, priv->pci_dev_data, priv);
57dbf29a
KSS		 3274
3275 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3276}
3277
3646f0e5 3278static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 3279 .error_detected = mlx4_pci_err_detected,
3280 .slot_reset = mlx4_pci_slot_reset,
3281};
3282
225c7b1f
RD		 3283static struct pci_driver mlx4_driver = {
3284 .name = DRV_NAME,
3285 .id_table = mlx4_pci_table,
3286 .probe = mlx4_init_one,
e1c00e10 3287 .shutdown = mlx4_unload_one,
f57e6848 3288 .remove = mlx4_remove_one,
57dbf29a 3289 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 3290};
3291
7ff93f8b
YP		 3292static int __init mlx4_verify_params(void)
3293{
3294 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 3295 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 3296 return -1;
3297 }
3298
cb29688a 3299 if (log_num_vlan != 0)
c20862c8
AV		 3300 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3301 MLX4_LOG_NUM_VLANS);
7ff93f8b 3302
ecc8fb11
AV		 3303 if (use_prio != 0)
3304 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 3305
0498628f 3306 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 3307 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3308 log_mtts_per_seg);
ab6bf42e
EC		 3309 return -1;
3310 }
3311
ab9c17a0
JM		 3312 /* Check if module param for ports type has legal combination */
3313 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 3314 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 3315 port_type_array[0] = true;
3316 }
3317
7d077cd3
MB		 3318 if (mlx4_log_num_mgm_entry_size < -7 ||
3319 (mlx4_log_num_mgm_entry_size > 0 &&
3320 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3321 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
3322 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
1a91de28
JP		 3323 mlx4_log_num_mgm_entry_size,
3324 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3325 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 3326 return -1;
3327 }
3328
7ff93f8b
YP		 3329 return 0;
3330}
3331
225c7b1f
RD		 3332static int __init mlx4_init(void)
3333{
3334 int ret;
3335
7ff93f8b
YP		 3336 if (mlx4_verify_params())
3337 return -EINVAL;
3338
27bf91d6
YP		 3339 mlx4_catas_init();
3340
3341 mlx4_wq = create_singlethread_workqueue("mlx4");
3342 if (!mlx4_wq)
3343 return -ENOMEM;
ee49bd93 3344
225c7b1f 3345 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 3346 if (ret < 0)
3347 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3348 return ret < 0 ? ret : 0;
3349}
3350
3351static void __exit mlx4_cleanup(void)
3352{
3353 pci_unregister_driver(&mlx4_driver);
27bf91d6 3354 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3355}
3356
3357module_init(mlx4_init);
3358module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)