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net: vlan: fix comment for vlan_ethhdr->h_vlan_proto
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
90b1ebe7 44#include <linux/netdevice.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
ab9c17a0
JM		 80static int num_vfs;
81module_param(num_vfs, int, 0444);
82MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
83
84static int probe_vf;
85module_param(probe_vf, int, 0644);
86MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
87
3c439b55 88int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 89module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
3c439b55 93 " 10 gives 248.range: 7 <="
0ff1fb65 94 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 95 " To activate device managed"
96 " flow steering when available, set to -1");
0ec2c0f8 97
08ff3235
OG		 98static bool enable_64b_cqe_eqe;
99module_param(enable_64b_cqe_eqe, bool, 0444);
100MODULE_PARM_DESC(enable_64b_cqe_eqe,
101 "Enable 64 byte CQEs/EQEs when the the FW supports this");
102
ab9c17a0 103#define HCA_GLOBAL_CAP_MASK 0
08ff3235
OG		 104
105#define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
ab9c17a0 106
f57e6848 107static char mlx4_version[] =
225c7b1f
RD		 108 DRV_NAME ": Mellanox ConnectX core driver v"
109 DRV_VERSION " (" DRV_RELDATE ")\n";
110
111static struct mlx4_profile default_profile = {
ab9c17a0 112 .num_qp = 1 << 18,
225c7b1f 113 .num_srq = 1 << 16,
c9f2ba5e 114 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 115 .num_cq = 1 << 16,
116 .num_mcg = 1 << 13,
ab9c17a0 117 .num_mpt = 1 << 19,
9fd7a1e1 118 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 119};
120
ab9c17a0 121static int log_num_mac = 7;
93fc9e1b
YP		 122module_param_named(log_num_mac, log_num_mac, int, 0444);
123MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
124
125static int log_num_vlan;
126module_param_named(log_num_vlan, log_num_vlan, int, 0444);
127MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 128/* Log2 max number of VLANs per ETH port (0-7) */
129#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 130
eb939922 131static bool use_prio;
93fc9e1b
YP		 132module_param_named(use_prio, use_prio, bool, 0444);
133MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
134 "(0/1, default 0)");
135
2b8fb286 136int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 137module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 138MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 139
8d0fc7b6 140static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 141static int arr_argc = 2;
142module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 143MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
144 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 145
146struct mlx4_port_config {
147 struct list_head list;
148 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
149 struct pci_dev *pdev;
150};
151
27bf91d6
YP		 152int mlx4_check_port_params(struct mlx4_dev *dev,
153 enum mlx4_port_type *port_type)
7ff93f8b
YP		 154{
155 int i;
156
157 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 158 if (port_type[i] != port_type[i + 1]) {
159 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
160 mlx4_err(dev, "Only same port types supported "
161 "on this HCA, aborting.\n");
162 return -EINVAL;
163 }
7ff93f8b
YP		 164 }
165 }
7ff93f8b
YP		 166
167 for (i = 0; i < dev->caps.num_ports; i++) {
168 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
169 mlx4_err(dev, "Requested port type for port %d is not "
170 "supported on this HCA\n", i + 1);
171 return -EINVAL;
172 }
173 }
174 return 0;
175}
176
177static void mlx4_set_port_mask(struct mlx4_dev *dev)
178{
179 int i;
180
7ff93f8b 181 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 182 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 183}
f2a3f6a3 184
3d73c288 185static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 186{
187 int err;
5ae2a7a8 188 int i;
225c7b1f
RD		 189
190 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
191 if (err) {
192 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
193 return err;
194 }
195
196 if (dev_cap->min_page_sz > PAGE_SIZE) {
197 mlx4_err(dev, "HCA minimum page size of %d bigger than "
198 "kernel PAGE_SIZE of %ld, aborting.\n",
199 dev_cap->min_page_sz, PAGE_SIZE);
200 return -ENODEV;
201 }
202 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
203 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
204 "aborting.\n",
205 dev_cap->num_ports, MLX4_MAX_PORTS);
206 return -ENODEV;
207 }
208
209 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
210 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
211 "PCI resource 2 size of 0x%llx, aborting.\n",
212 dev_cap->uar_size,
213 (unsigned long long) pci_resource_len(dev->pdev, 2));
214 return -ENODEV;
215 }
216
217 dev->caps.num_ports = dev_cap->num_ports;
3fc929e2 218 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
5ae2a7a8
RD		 219 for (i = 1; i <= dev->caps.num_ports; ++i) {
220 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 221 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
6634961c
JM		 222 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
223 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
224 /* set gid and pkey table operating lengths by default
225 * to non-sriov values */
5ae2a7a8
RD		 226 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
227 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
228 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 229 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
230 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 231 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 232 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
233 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 234 dev->caps.trans_type[i] = dev_cap->trans_type[i];
235 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
236 dev->caps.wavelength[i] = dev_cap->wavelength[i];
237 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 238 }
239
ab9c17a0 240 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 241 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 242 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
243 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
244 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
245 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
246 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
247 dev->caps.max_wqes = dev_cap->max_qp_sz;
248 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 249 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
250 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
251 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
252 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
253 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 254 /*
255 * Subtract 1 from the limit because we need to allocate a
256 * spare CQE so the HCA HW can tell the difference between an
257 * empty CQ and a full CQ.
258 */
259 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
260 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
261 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 262 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 263 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 264
265 /* The first 128 UARs are used for EQ doorbells */
266 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 267 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 268 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
269 dev_cap->reserved_xrcds : 0;
270 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
271 dev_cap->max_xrcds : 0;
2b8fb286
MA		 272 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
273
149983af 274 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 275 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
276 dev->caps.flags = dev_cap->flags;
b3416f44 277 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 278 dev->caps.bmme_flags = dev_cap->bmme_flags;
279 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 280 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 281 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 282 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 283
ca3e57a5
RD		 284 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
285 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 286 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 287 /* Don't do sense port on multifunction devices (for now at least) */
288 if (mlx4_is_mfunc(dev))
289 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 290
93fc9e1b 291 dev->caps.log_num_macs = log_num_mac;
cb29688a 292 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 293 dev->caps.log_num_prios = use_prio ? 3 : 0;
294
295 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 296 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
297 if (dev->caps.supported_type[i]) {
298 /* if only ETH is supported - assign ETH */
299 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
300 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 301 /* if only IB is supported, assign IB */
ab9c17a0 302 else if (dev->caps.supported_type[i] ==
105c320f
JM		 303 MLX4_PORT_TYPE_IB)
304 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 305 else {
105c320f
JM		 306 /* if IB and ETH are supported, we set the port
307 * type according to user selection of port type;
308 * if user selected none, take the FW hint */
309 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 310 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
311 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 312 else
105c320f 313 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 314 }
315 }
8d0fc7b6
YP		 316 /*
317 * Link sensing is allowed on the port if 3 conditions are true:
318 * 1. Both protocols are supported on the port.
319 * 2. Different types are supported on the port
320 * 3. FW declared that it supports link sensing
321 */
27bf91d6 322 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 323 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 324 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 325 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 326
8d0fc7b6
YP		 327 /*
328 * If "default_sense" bit is set, we move the port to "AUTO" mode
329 * and perform sense_port FW command to try and set the correct
330 * port type from beginning
331 */
46c46747 332 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 333 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
334 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
335 mlx4_SENSE_PORT(dev, i, &sensed_port);
336 if (sensed_port != MLX4_PORT_TYPE_NONE)
337 dev->caps.port_type[i] = sensed_port;
338 } else {
339 dev->caps.possible_type[i] = dev->caps.port_type[i];
340 }
341
93fc9e1b
YP		 342 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
343 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
344 mlx4_warn(dev, "Requested number of MACs is too much "
345 "for port %d, reducing to %d.\n",
346 i, 1 << dev->caps.log_num_macs);
347 }
348 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
349 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
350 mlx4_warn(dev, "Requested number of VLANs is too much "
351 "for port %d, reducing to %d.\n",
352 i, 1 << dev->caps.log_num_vlans);
353 }
354 }
355
f2a3f6a3
OG		 356 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
357
93fc9e1b
YP		 358 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
359 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
360 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
361 (1 << dev->caps.log_num_macs) *
362 (1 << dev->caps.log_num_vlans) *
363 (1 << dev->caps.log_num_prios) *
364 dev->caps.num_ports;
365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
366
367 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
369 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
370 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
371
e2c76824 372 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235
OG		 373
374 if (!enable_64b_cqe_eqe) {
375 if (dev_cap->flags &
376 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
377 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
378 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
379 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
380 }
381 }
382
f97b4b5d 383 if ((dev->caps.flags &
08ff3235
OG		 384 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
385 mlx4_is_master(dev))
386 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
387
225c7b1f
RD		 388 return 0;
389}
ab9c17a0
JM		 390/*The function checks if there are live vf, return the num of them*/
391static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
392{
393 struct mlx4_priv *priv = mlx4_priv(dev);
394 struct mlx4_slave_state *s_state;
395 int i;
396 int ret = 0;
397
398 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
399 s_state = &priv->mfunc.master.slave_state[i];
400 if (s_state->active && s_state->last_cmd !=
401 MLX4_COMM_CMD_RESET) {
402 mlx4_warn(dev, "%s: slave: %d is still active\n",
403 __func__, i);
404 ret++;
405 }
406 }
407 return ret;
408}
409
396f2feb
JM		 410int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
411{
412 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 413
414 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
415 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 416 return -EINVAL;
417
47605df9 418 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 419 /* tunnel qp */
47605df9 420 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 421 else
47605df9 422 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 423 *qkey = qk;
424 return 0;
425}
426EXPORT_SYMBOL(mlx4_get_parav_qkey);
427
54679e14
JM		 428void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
429{
430 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
431
432 if (!mlx4_is_master(dev))
433 return;
434
435 priv->virt2phys_pkey[slave][port - 1][i] = val;
436}
437EXPORT_SYMBOL(mlx4_sync_pkey_table);
438
afa8fd1d
JM		 439void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
440{
441 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
442
443 if (!mlx4_is_master(dev))
444 return;
445
446 priv->slave_node_guids[slave] = guid;
447}
448EXPORT_SYMBOL(mlx4_put_slave_node_guid);
449
450__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
451{
452 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
453
454 if (!mlx4_is_master(dev))
455 return 0;
456
457 return priv->slave_node_guids[slave];
458}
459EXPORT_SYMBOL(mlx4_get_slave_node_guid);
460
e10903b0 461int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 462{
463 struct mlx4_priv *priv = mlx4_priv(dev);
464 struct mlx4_slave_state *s_slave;
465
466 if (!mlx4_is_master(dev))
467 return 0;
468
469 s_slave = &priv->mfunc.master.slave_state[slave];
470 return !!s_slave->active;
471}
472EXPORT_SYMBOL(mlx4_is_slave_active);
473
7b8157be
JM		 474static void slave_adjust_steering_mode(struct mlx4_dev *dev,
475 struct mlx4_dev_cap *dev_cap,
476 struct mlx4_init_hca_param *hca_param)
477{
478 dev->caps.steering_mode = hca_param->steering_mode;
479 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
480 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
481 dev->caps.fs_log_max_ucast_qp_range_size =
482 dev_cap->fs_log_max_ucast_qp_range_size;
483 } else
484 dev->caps.num_qp_per_mgm =
485 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
486
487 mlx4_dbg(dev, "Steering mode is: %s\n",
488 mlx4_steering_mode_str(dev->caps.steering_mode));
489}
490
ab9c17a0
JM		 491static int mlx4_slave_cap(struct mlx4_dev *dev)
492{
493 int err;
494 u32 page_size;
495 struct mlx4_dev_cap dev_cap;
496 struct mlx4_func_cap func_cap;
497 struct mlx4_init_hca_param hca_param;
498 int i;
499
500 memset(&hca_param, 0, sizeof(hca_param));
501 err = mlx4_QUERY_HCA(dev, &hca_param);
502 if (err) {
503 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
504 return err;
505 }
506
507 /*fail if the hca has an unknown capability */
508 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
509 HCA_GLOBAL_CAP_MASK) {
510 mlx4_err(dev, "Unknown hca global capabilities\n");
511 return -ENOSYS;
512 }
513
514 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
515
ddd8a6c1
EE		 516 dev->caps.hca_core_clock = hca_param.hca_core_clock;
517
ab9c17a0 518 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 519 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 520 err = mlx4_dev_cap(dev, &dev_cap);
521 if (err) {
522 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
523 return err;
524 }
525
b91cb3eb
JM		 526 err = mlx4_QUERY_FW(dev);
527 if (err)
528 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
529
ab9c17a0
JM		 530 page_size = ~dev->caps.page_size_cap + 1;
531 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
532 if (page_size > PAGE_SIZE) {
533 mlx4_err(dev, "HCA minimum page size of %d bigger than "
534 "kernel PAGE_SIZE of %ld, aborting.\n",
535 page_size, PAGE_SIZE);
536 return -ENODEV;
537 }
538
539 /* slave gets uar page size from QUERY_HCA fw command */
540 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
541
542 /* TODO: relax this assumption */
543 if (dev->caps.uar_page_size != PAGE_SIZE) {
544 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
545 dev->caps.uar_page_size, PAGE_SIZE);
546 return -ENODEV;
547 }
548
549 memset(&func_cap, 0, sizeof(func_cap));
47605df9 550 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 551 if (err) {
47605df9
JM		 552 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
553 err);
ab9c17a0
JM		 554 return err;
555 }
556
557 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
558 PF_CONTEXT_BEHAVIOUR_MASK) {
559 mlx4_err(dev, "Unknown pf context behaviour\n");
560 return -ENOSYS;
561 }
562
ab9c17a0
JM		 563 dev->caps.num_ports = func_cap.num_ports;
564 dev->caps.num_qps = func_cap.qp_quota;
565 dev->caps.num_srqs = func_cap.srq_quota;
566 dev->caps.num_cqs = func_cap.cq_quota;
567 dev->caps.num_eqs = func_cap.max_eq;
568 dev->caps.reserved_eqs = func_cap.reserved_eq;
569 dev->caps.num_mpts = func_cap.mpt_quota;
570 dev->caps.num_mtts = func_cap.mtt_quota;
571 dev->caps.num_pds = MLX4_NUM_PDS;
572 dev->caps.num_mgms = 0;
573 dev->caps.num_amgms = 0;
574
ab9c17a0
JM		 575 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
576 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
577 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
578 return -ENODEV;
579 }
580
47605df9
JM		 581 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
582 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
583 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
584 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
585
586 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
587 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
588 err = -ENOMEM;
589 goto err_mem;
590 }
591
6634961c 592 for (i = 1; i <= dev->caps.num_ports; ++i) {
47605df9
JM		 593 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
594 if (err) {
595 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
596 " port %d, aborting (%d).\n", i, err);
597 goto err_mem;
598 }
599 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
600 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
601 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
602 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 603 dev->caps.port_mask[i] = dev->caps.port_type[i];
6634961c
JM		 604 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
605 &dev->caps.gid_table_len[i],
606 &dev->caps.pkey_table_len[i]))
47605df9 607 goto err_mem;
6634961c 608 }
6230bb23 609
ab9c17a0
JM		 610 if (dev->caps.uar_page_size * (dev->caps.num_uars -
611 dev->caps.reserved_uars) >
612 pci_resource_len(dev->pdev, 2)) {
613 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
614 "PCI resource 2 size of 0x%llx, aborting.\n",
615 dev->caps.uar_page_size * dev->caps.num_uars,
616 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 617 goto err_mem;
ab9c17a0
JM		 618 }
619
08ff3235
OG		 620 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
621 dev->caps.eqe_size = 64;
622 dev->caps.eqe_factor = 1;
623 } else {
624 dev->caps.eqe_size = 32;
625 dev->caps.eqe_factor = 0;
626 }
627
628 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
629 dev->caps.cqe_size = 64;
630 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
631 } else {
632 dev->caps.cqe_size = 32;
633 }
634
7b8157be
JM		 635 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
636
ab9c17a0 637 return 0;
47605df9
JM		 638
639err_mem:
640 kfree(dev->caps.qp0_tunnel);
641 kfree(dev->caps.qp0_proxy);
642 kfree(dev->caps.qp1_tunnel);
643 kfree(dev->caps.qp1_proxy);
644 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
645 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
646
647 return err;
ab9c17a0 648}
225c7b1f 649
7ff93f8b
YP		 650/*
651 * Change the port configuration of the device.
652 * Every user of this function must hold the port mutex.
653 */
27bf91d6
YP		 654int mlx4_change_port_types(struct mlx4_dev *dev,
655 enum mlx4_port_type *port_types)
7ff93f8b
YP		 656{
657 int err = 0;
658 int change = 0;
659 int port;
660
661 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 662 /* Change the port type only if the new type is different
663 * from the current, and not set to Auto */
3d8f9308 664 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 665 change = 1;
7ff93f8b
YP		 666 }
667 if (change) {
668 mlx4_unregister_device(dev);
669 for (port = 1; port <= dev->caps.num_ports; port++) {
670 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 671 dev->caps.port_type[port] = port_types[port - 1];
6634961c 672 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b
YP		 673 if (err) {
674 mlx4_err(dev, "Failed to set port %d, "
675 "aborting\n", port);
676 goto out;
677 }
678 }
679 mlx4_set_port_mask(dev);
680 err = mlx4_register_device(dev);
681 }
682
683out:
684 return err;
685}
686
687static ssize_t show_port_type(struct device *dev,
688 struct device_attribute *attr,
689 char *buf)
690{
691 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
692 port_attr);
693 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 694 char type[8];
695
696 sprintf(type, "%s",
697 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
698 "ib" : "eth");
699 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
700 sprintf(buf, "auto (%s)\n", type);
701 else
702 sprintf(buf, "%s\n", type);
7ff93f8b 703
27bf91d6 704 return strlen(buf);
7ff93f8b
YP		 705}
706
707static ssize_t set_port_type(struct device *dev,
708 struct device_attribute *attr,
709 const char *buf, size_t count)
710{
711 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
712 port_attr);
713 struct mlx4_dev *mdev = info->dev;
714 struct mlx4_priv *priv = mlx4_priv(mdev);
715 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 716 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 717 int i;
718 int err = 0;
719
720 if (!strcmp(buf, "ib\n"))
721 info->tmp_type = MLX4_PORT_TYPE_IB;
722 else if (!strcmp(buf, "eth\n"))
723 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 724 else if (!strcmp(buf, "auto\n"))
725 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 726 else {
727 mlx4_err(mdev, "%s is not supported port type\n", buf);
728 return -EINVAL;
729 }
730
27bf91d6 731 mlx4_stop_sense(mdev);
7ff93f8b 732 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 733 /* Possible type is always the one that was delivered */
734 mdev->caps.possible_type[info->port] = info->tmp_type;
735
736 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 737 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 738 mdev->caps.possible_type[i+1];
739 if (types[i] == MLX4_PORT_TYPE_AUTO)
740 types[i] = mdev->caps.port_type[i+1];
741 }
7ff93f8b 742
58a60168
YP		 743 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
744 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 745 for (i = 1; i <= mdev->caps.num_ports; i++) {
746 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
747 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
748 err = -EINVAL;
749 }
750 }
751 }
752 if (err) {
753 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
754 "Set only 'eth' or 'ib' for both ports "
755 "(should be the same)\n");
756 goto out;
757 }
758
759 mlx4_do_sense_ports(mdev, new_types, types);
760
761 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 762 if (err)
763 goto out;
764
27bf91d6
YP		 765 /* We are about to apply the changes after the configuration
766 * was verified, no need to remember the temporary types
767 * any more */
768 for (i = 0; i < mdev->caps.num_ports; i++)
769 priv->port[i + 1].tmp_type = 0;
7ff93f8b 770
27bf91d6 771 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 772
773out:
27bf91d6 774 mlx4_start_sense(mdev);
7ff93f8b
YP		 775 mutex_unlock(&priv->port_mutex);
776 return err ? err : count;
777}
778
096335b3
OG		 779enum ibta_mtu {
780 IB_MTU_256 = 1,
781 IB_MTU_512 = 2,
782 IB_MTU_1024 = 3,
783 IB_MTU_2048 = 4,
784 IB_MTU_4096 = 5
785};
786
787static inline int int_to_ibta_mtu(int mtu)
788{
789 switch (mtu) {
790 case 256: return IB_MTU_256;
791 case 512: return IB_MTU_512;
792 case 1024: return IB_MTU_1024;
793 case 2048: return IB_MTU_2048;
794 case 4096: return IB_MTU_4096;
795 default: return -1;
796 }
797}
798
799static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
800{
801 switch (mtu) {
802 case IB_MTU_256: return 256;
803 case IB_MTU_512: return 512;
804 case IB_MTU_1024: return 1024;
805 case IB_MTU_2048: return 2048;
806 case IB_MTU_4096: return 4096;
807 default: return -1;
808 }
809}
810
811static ssize_t show_port_ib_mtu(struct device *dev,
812 struct device_attribute *attr,
813 char *buf)
814{
815 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
816 port_mtu_attr);
817 struct mlx4_dev *mdev = info->dev;
818
819 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
820 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
821
822 sprintf(buf, "%d\n",
823 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
824 return strlen(buf);
825}
826
827static ssize_t set_port_ib_mtu(struct device *dev,
828 struct device_attribute *attr,
829 const char *buf, size_t count)
830{
831 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
832 port_mtu_attr);
833 struct mlx4_dev *mdev = info->dev;
834 struct mlx4_priv *priv = mlx4_priv(mdev);
835 int err, port, mtu, ibta_mtu = -1;
836
837 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
838 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
839 return -EINVAL;
840 }
841
842 err = sscanf(buf, "%d", &mtu);
843 if (err > 0)
844 ibta_mtu = int_to_ibta_mtu(mtu);
845
846 if (err <= 0 || ibta_mtu < 0) {
847 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
848 return -EINVAL;
849 }
850
851 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
852
853 mlx4_stop_sense(mdev);
854 mutex_lock(&priv->port_mutex);
855 mlx4_unregister_device(mdev);
856 for (port = 1; port <= mdev->caps.num_ports; port++) {
857 mlx4_CLOSE_PORT(mdev, port);
6634961c 858 err = mlx4_SET_PORT(mdev, port, -1);
096335b3
OG		 859 if (err) {
860 mlx4_err(mdev, "Failed to set port %d, "
861 "aborting\n", port);
862 goto err_set_port;
863 }
864 }
865 err = mlx4_register_device(mdev);
866err_set_port:
867 mutex_unlock(&priv->port_mutex);
868 mlx4_start_sense(mdev);
869 return err ? err : count;
870}
871
e8f9b2ed 872static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 873{
874 struct mlx4_priv *priv = mlx4_priv(dev);
875 int err;
876
877 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 878 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 879 if (!priv->fw.fw_icm) {
880 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
881 return -ENOMEM;
882 }
883
884 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
885 if (err) {
886 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
887 goto err_free;
888 }
889
890 err = mlx4_RUN_FW(dev);
891 if (err) {
892 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
893 goto err_unmap_fa;
894 }
895
896 return 0;
897
898err_unmap_fa:
899 mlx4_UNMAP_FA(dev);
900
901err_free:
5b0bf5e2 902 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 903 return err;
904}
905
e8f9b2ed
RD		 906static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
907 int cmpt_entry_sz)
225c7b1f
RD		 908{
909 struct mlx4_priv *priv = mlx4_priv(dev);
910 int err;
ab9c17a0 911 int num_eqs;
225c7b1f
RD		 912
913 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
914 cmpt_base +
915 ((u64) (MLX4_CMPT_TYPE_QP *
916 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
917 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 918 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
919 0, 0);
225c7b1f
RD		 920 if (err)
921 goto err;
922
923 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
924 cmpt_base +
925 ((u64) (MLX4_CMPT_TYPE_SRQ *
926 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
927 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 928 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 929 if (err)
930 goto err_qp;
931
932 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
933 cmpt_base +
934 ((u64) (MLX4_CMPT_TYPE_CQ *
935 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
936 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 937 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 938 if (err)
939 goto err_srq;
940
3fc929e2
MA		 941 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
942 dev->caps.num_eqs;
225c7b1f
RD		 943 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
944 cmpt_base +
945 ((u64) (MLX4_CMPT_TYPE_EQ *
946 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 947 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 948 if (err)
949 goto err_cq;
950
951 return 0;
952
953err_cq:
954 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
955
956err_srq:
957 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
958
959err_qp:
960 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
961
962err:
963 return err;
964}
965
3d73c288
RD		 966static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
967 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 968{
969 struct mlx4_priv *priv = mlx4_priv(dev);
970 u64 aux_pages;
ab9c17a0 971 int num_eqs;
225c7b1f
RD		 972 int err;
973
974 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
975 if (err) {
976 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
977 return err;
978 }
979
980 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
981 (unsigned long long) icm_size >> 10,
982 (unsigned long long) aux_pages << 2);
983
984 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 985 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 986 if (!priv->fw.aux_icm) {
987 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
988 return -ENOMEM;
989 }
990
991 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
992 if (err) {
993 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
994 goto err_free_aux;
995 }
996
997 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
998 if (err) {
999 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1000 goto err_unmap_aux;
1001 }
1002
ab9c17a0 1003
3fc929e2
MA		 1004 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1005 dev->caps.num_eqs;
fa0681d2
RD		 1006 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1007 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1008 num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1009 if (err) {
1010 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1011 goto err_unmap_cmpt;
1012 }
1013
d7bb58fb
JM		 1014 /*
1015 * Reserved MTT entries must be aligned up to a cacheline
1016 * boundary, since the FW will write to them, while the driver
1017 * writes to all other MTT entries. (The variable
1018 * dev->caps.mtt_entry_sz below is really the MTT segment
1019 * size, not the raw entry size)
1020 */
1021 dev->caps.reserved_mtts =
1022 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1023 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1024
225c7b1f
RD		 1025 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1026 init_hca->mtt_base,
1027 dev->caps.mtt_entry_sz,
2b8fb286 1028 dev->caps.num_mtts,
5b0bf5e2 1029 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 1030 if (err) {
1031 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1032 goto err_unmap_eq;
1033 }
1034
1035 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1036 init_hca->dmpt_base,
1037 dev_cap->dmpt_entry_sz,
1038 dev->caps.num_mpts,
5b0bf5e2 1039 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 1040 if (err) {
1041 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1042 goto err_unmap_mtt;
1043 }
1044
1045 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1046 init_hca->qpc_base,
1047 dev_cap->qpc_entry_sz,
1048 dev->caps.num_qps,
93fc9e1b
YP		 1049 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1050 0, 0);
225c7b1f
RD		 1051 if (err) {
1052 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1053 goto err_unmap_dmpt;
1054 }
1055
1056 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1057 init_hca->auxc_base,
1058 dev_cap->aux_entry_sz,
1059 dev->caps.num_qps,
93fc9e1b
YP		 1060 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1061 0, 0);
225c7b1f
RD		 1062 if (err) {
1063 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1064 goto err_unmap_qp;
1065 }
1066
1067 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1068 init_hca->altc_base,
1069 dev_cap->altc_entry_sz,
1070 dev->caps.num_qps,
93fc9e1b
YP		 1071 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1072 0, 0);
225c7b1f
RD		 1073 if (err) {
1074 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1075 goto err_unmap_auxc;
1076 }
1077
1078 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1079 init_hca->rdmarc_base,
1080 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1081 dev->caps.num_qps,
93fc9e1b
YP		 1082 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1083 0, 0);
225c7b1f
RD		 1084 if (err) {
1085 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1086 goto err_unmap_altc;
1087 }
1088
1089 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1090 init_hca->cqc_base,
1091 dev_cap->cqc_entry_sz,
1092 dev->caps.num_cqs,
5b0bf5e2 1093 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1094 if (err) {
1095 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1096 goto err_unmap_rdmarc;
1097 }
1098
1099 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1100 init_hca->srqc_base,
1101 dev_cap->srq_entry_sz,
1102 dev->caps.num_srqs,
5b0bf5e2 1103 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1104 if (err) {
1105 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1106 goto err_unmap_cq;
1107 }
1108
1109 /*
0ff1fb65
HHZ		 1110 * For flow steering device managed mode it is required to use
1111 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1112 * required, but for simplicity just map the whole multicast
1113 * group table now. The table isn't very big and it's a lot
1114 * easier than trying to track ref counts.
225c7b1f
RD		 1115 */
1116 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1117 init_hca->mc_base,
1118 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1119 dev->caps.num_mgms + dev->caps.num_amgms,
1120 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1121 0, 0);
225c7b1f
RD		 1122 if (err) {
1123 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1124 goto err_unmap_srq;
1125 }
1126
1127 return 0;
1128
1129err_unmap_srq:
1130 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1131
1132err_unmap_cq:
1133 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1134
1135err_unmap_rdmarc:
1136 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1137
1138err_unmap_altc:
1139 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1140
1141err_unmap_auxc:
1142 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1143
1144err_unmap_qp:
1145 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1146
1147err_unmap_dmpt:
1148 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1149
1150err_unmap_mtt:
1151 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1152
1153err_unmap_eq:
fa0681d2 1154 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1155
1156err_unmap_cmpt:
1157 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1158 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1159 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1160 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1161
1162err_unmap_aux:
1163 mlx4_UNMAP_ICM_AUX(dev);
1164
1165err_free_aux:
5b0bf5e2 1166 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1167
1168 return err;
1169}
1170
1171static void mlx4_free_icms(struct mlx4_dev *dev)
1172{
1173 struct mlx4_priv *priv = mlx4_priv(dev);
1174
1175 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1176 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1177 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1178 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1179 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1180 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1181 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1182 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1183 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1184 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1185 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1186 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1187 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1188 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1189
1190 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1191 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1192}
1193
ab9c17a0
JM		 1194static void mlx4_slave_exit(struct mlx4_dev *dev)
1195{
1196 struct mlx4_priv *priv = mlx4_priv(dev);
1197
f3d4c89e 1198 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1199 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1200 mlx4_warn(dev, "Failed to close slave function.\n");
f3d4c89e 1201 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1202}
1203
c1b43dca
EC		 1204static int map_bf_area(struct mlx4_dev *dev)
1205{
1206 struct mlx4_priv *priv = mlx4_priv(dev);
1207 resource_size_t bf_start;
1208 resource_size_t bf_len;
1209 int err = 0;
1210
3d747473
JM		 1211 if (!dev->caps.bf_reg_size)
1212 return -ENXIO;
1213
ab9c17a0
JM		 1214 bf_start = pci_resource_start(dev->pdev, 2) +
1215 (dev->caps.num_uars << PAGE_SHIFT);
1216 bf_len = pci_resource_len(dev->pdev, 2) -
1217 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1218 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1219 if (!priv->bf_mapping)
1220 err = -ENOMEM;
1221
1222 return err;
1223}
1224
1225static void unmap_bf_area(struct mlx4_dev *dev)
1226{
1227 if (mlx4_priv(dev)->bf_mapping)
1228 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1229}
1230
ec693d47
AV		 1231cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1232{
1233 u32 clockhi, clocklo, clockhi1;
1234 cycle_t cycles;
1235 int i;
1236 struct mlx4_priv *priv = mlx4_priv(dev);
1237
1238 for (i = 0; i < 10; i++) {
1239 clockhi = swab32(readl(priv->clock_mapping));
1240 clocklo = swab32(readl(priv->clock_mapping + 4));
1241 clockhi1 = swab32(readl(priv->clock_mapping));
1242 if (clockhi == clockhi1)
1243 break;
1244 }
1245
1246 cycles = (u64) clockhi << 32 | (u64) clocklo;
1247
1248 return cycles;
1249}
1250EXPORT_SYMBOL_GPL(mlx4_read_clock);
1251
1252
ddd8a6c1
EE		 1253static int map_internal_clock(struct mlx4_dev *dev)
1254{
1255 struct mlx4_priv *priv = mlx4_priv(dev);
1256
1257 priv->clock_mapping =
1258 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1259 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1260
1261 if (!priv->clock_mapping)
1262 return -ENOMEM;
1263
1264 return 0;
1265}
1266
1267static void unmap_internal_clock(struct mlx4_dev *dev)
1268{
1269 struct mlx4_priv *priv = mlx4_priv(dev);
1270
1271 if (priv->clock_mapping)
1272 iounmap(priv->clock_mapping);
1273}
1274
225c7b1f
RD		 1275static void mlx4_close_hca(struct mlx4_dev *dev)
1276{
ddd8a6c1 1277 unmap_internal_clock(dev);
c1b43dca 1278 unmap_bf_area(dev);
ab9c17a0
JM		 1279 if (mlx4_is_slave(dev))
1280 mlx4_slave_exit(dev);
1281 else {
1282 mlx4_CLOSE_HCA(dev, 0);
1283 mlx4_free_icms(dev);
1284 mlx4_UNMAP_FA(dev);
1285 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1286 }
1287}
1288
1289static int mlx4_init_slave(struct mlx4_dev *dev)
1290{
1291 struct mlx4_priv *priv = mlx4_priv(dev);
1292 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1293 int ret_from_reset = 0;
1294 u32 slave_read;
1295 u32 cmd_channel_ver;
1296
f3d4c89e 1297 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1298 priv->cmd.max_cmds = 1;
1299 mlx4_warn(dev, "Sending reset\n");
1300 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1301 MLX4_COMM_TIME);
1302 /* if we are in the middle of flr the slave will try
1303 * NUM_OF_RESET_RETRIES times before leaving.*/
1304 if (ret_from_reset) {
1305 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
5efe5355
JM		 1306 mlx4_warn(dev, "slave is currently in the "
1307 "middle of FLR. Deferring probe.\n");
1308 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1309 return -EPROBE_DEFER;
ab9c17a0
JM		 1310 } else
1311 goto err;
1312 }
1313
1314 /* check the driver version - the slave I/F revision
1315 * must match the master's */
1316 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1317 cmd_channel_ver = mlx4_comm_get_version();
1318
1319 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1320 MLX4_COMM_GET_IF_REV(slave_read)) {
1321 mlx4_err(dev, "slave driver version is not supported"
1322 " by the master\n");
1323 goto err;
1324 }
1325
1326 mlx4_warn(dev, "Sending vhcr0\n");
1327 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1328 MLX4_COMM_TIME))
1329 goto err;
1330 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1331 MLX4_COMM_TIME))
1332 goto err;
1333 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1334 MLX4_COMM_TIME))
1335 goto err;
1336 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1337 goto err;
f3d4c89e
RD		 1338
1339 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1340 return 0;
1341
1342err:
1343 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1344 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1345 return -EIO;
225c7b1f
RD		 1346}
1347
6634961c
JM		 1348static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1349{
1350 int i;
1351
1352 for (i = 1; i <= dev->caps.num_ports; i++) {
1353 dev->caps.gid_table_len[i] = 1;
1354 dev->caps.pkey_table_len[i] =
1355 dev->phys_caps.pkey_phys_table_len[i] - 1;
1356 }
1357}
1358
3c439b55
JM		 1359static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1360{
1361 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1362
1363 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1364 i++) {
1365 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1366 break;
1367 }
1368
1369 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1370}
1371
7b8157be
JM		 1372static void choose_steering_mode(struct mlx4_dev *dev,
1373 struct mlx4_dev_cap *dev_cap)
1374{
3c439b55
JM		 1375 if (mlx4_log_num_mgm_entry_size == -1 &&
1376 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1377 (!mlx4_is_mfunc(dev) ||
3c439b55
JM		 1378 (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) &&
1379 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1380 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1381 dev->oper_log_mgm_entry_size =
1382 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1383 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1384 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1385 dev->caps.fs_log_max_ucast_qp_range_size =
1386 dev_cap->fs_log_max_ucast_qp_range_size;
1387 } else {
1388 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1389 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1390 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1391 else {
1392 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1393
1394 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1395 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1396 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1397 "set to use B0 steering. Falling back to A0 steering mode.\n");
1398 }
3c439b55
JM		 1399 dev->oper_log_mgm_entry_size =
1400 mlx4_log_num_mgm_entry_size > 0 ?
1401 mlx4_log_num_mgm_entry_size :
1402 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1403 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1404 }
3c439b55
JM		 1405 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1406 "modparam log_num_mgm_entry_size = %d\n",
1407 mlx4_steering_mode_str(dev->caps.steering_mode),
1408 dev->oper_log_mgm_entry_size,
1409 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1410}
1411
3d73c288 1412static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1413{
1414 struct mlx4_priv *priv = mlx4_priv(dev);
1415 struct mlx4_adapter adapter;
1416 struct mlx4_dev_cap dev_cap;
2d928651 1417 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1418 struct mlx4_profile profile;
1419 struct mlx4_init_hca_param init_hca;
1420 u64 icm_size;
1421 int err;
1422
ab9c17a0
JM		 1423 if (!mlx4_is_slave(dev)) {
1424 err = mlx4_QUERY_FW(dev);
1425 if (err) {
1426 if (err == -EACCES)
1427 mlx4_info(dev, "non-primary physical function, skipping.\n");
1428 else
1429 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
bef772eb 1430 return err;
ab9c17a0 1431 }
225c7b1f 1432
ab9c17a0
JM		 1433 err = mlx4_load_fw(dev);
1434 if (err) {
1435 mlx4_err(dev, "Failed to start FW, aborting.\n");
bef772eb 1436 return err;
ab9c17a0 1437 }
225c7b1f 1438
ab9c17a0
JM		 1439 mlx4_cfg.log_pg_sz_m = 1;
1440 mlx4_cfg.log_pg_sz = 0;
1441 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1442 if (err)
1443 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1444
ab9c17a0
JM		 1445 err = mlx4_dev_cap(dev, &dev_cap);
1446 if (err) {
1447 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1448 goto err_stop_fw;
1449 }
225c7b1f 1450
7b8157be
JM		 1451 choose_steering_mode(dev, &dev_cap);
1452
6634961c
JM		 1453 if (mlx4_is_master(dev))
1454 mlx4_parav_master_pf_caps(dev);
1455
ab9c17a0 1456 profile = default_profile;
0ff1fb65
HHZ		 1457 if (dev->caps.steering_mode ==
1458 MLX4_STEERING_MODE_DEVICE_MANAGED)
1459 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1460
ab9c17a0
JM		 1461 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1462 &init_hca);
1463 if ((long long) icm_size < 0) {
1464 err = icm_size;
1465 goto err_stop_fw;
1466 }
225c7b1f 1467
a5bbe892
EC		 1468 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1469
ab9c17a0
JM		 1470 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1471 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1472 init_hca.mw_enabled = 0;
1473 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1474 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1475 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1476
ab9c17a0
JM		 1477 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1478 if (err)
1479 goto err_stop_fw;
225c7b1f 1480
ab9c17a0
JM		 1481 err = mlx4_INIT_HCA(dev, &init_hca);
1482 if (err) {
1483 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1484 goto err_free_icm;
1485 }
ddd8a6c1
EE		 1486 /*
1487 * If TS is supported by FW
1488 * read HCA frequency by QUERY_HCA command
1489 */
1490 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1491 memset(&init_hca, 0, sizeof(init_hca));
1492 err = mlx4_QUERY_HCA(dev, &init_hca);
1493 if (err) {
1494 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1495 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1496 } else {
1497 dev->caps.hca_core_clock =
1498 init_hca.hca_core_clock;
1499 }
1500
1501 /* In case we got HCA frequency 0 - disable timestamping
1502 * to avoid dividing by zero
1503 */
1504 if (!dev->caps.hca_core_clock) {
1505 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1506 mlx4_err(dev,
1507 "HCA frequency is 0. Timestamping is not supported.");
1508 } else if (map_internal_clock(dev)) {
1509 /*
1510 * Map internal clock,
1511 * in case of failure disable timestamping
1512 */
1513 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1514 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1515 }
1516 }
ab9c17a0
JM		 1517 } else {
1518 err = mlx4_init_slave(dev);
1519 if (err) {
5efe5355
JM		 1520 if (err != -EPROBE_DEFER)
1521 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1522 return err;
ab9c17a0 1523 }
225c7b1f 1524
ab9c17a0
JM		 1525 err = mlx4_slave_cap(dev);
1526 if (err) {
1527 mlx4_err(dev, "Failed to obtain slave caps\n");
1528 goto err_close;
1529 }
225c7b1f
RD		 1530 }
1531
ab9c17a0
JM		 1532 if (map_bf_area(dev))
1533 mlx4_dbg(dev, "Failed to map blue flame area\n");
1534
1535 /*Only the master set the ports, all the rest got it from it.*/
1536 if (!mlx4_is_slave(dev))
1537 mlx4_set_port_mask(dev);
1538
225c7b1f
RD		 1539 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1540 if (err) {
1541 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
bef772eb 1542 goto unmap_bf;
225c7b1f
RD		 1543 }
1544
1545 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1546 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1547
1548 return 0;
1549
bef772eb 1550unmap_bf:
ddd8a6c1 1551 unmap_internal_clock(dev);
bef772eb
AY		 1552 unmap_bf_area(dev);
1553
225c7b1f 1554err_close:
41929ed2
DB		 1555 if (mlx4_is_slave(dev))
1556 mlx4_slave_exit(dev);
1557 else
1558 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 1559
1560err_free_icm:
ab9c17a0
JM		 1561 if (!mlx4_is_slave(dev))
1562 mlx4_free_icms(dev);
225c7b1f
RD		 1563
1564err_stop_fw:
ab9c17a0
JM		 1565 if (!mlx4_is_slave(dev)) {
1566 mlx4_UNMAP_FA(dev);
1567 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1568 }
225c7b1f
RD		 1569 return err;
1570}
1571
f2a3f6a3
OG		 1572static int mlx4_init_counters_table(struct mlx4_dev *dev)
1573{
1574 struct mlx4_priv *priv = mlx4_priv(dev);
1575 int nent;
1576
1577 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1578 return -ENOENT;
1579
1580 nent = dev->caps.max_counters;
1581 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1582}
1583
1584static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1585{
1586 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1587}
1588
ba062d52 1589int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1590{
1591 struct mlx4_priv *priv = mlx4_priv(dev);
1592
1593 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1594 return -ENOENT;
1595
1596 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1597 if (*idx == -1)
1598 return -ENOMEM;
1599
1600 return 0;
1601}
ba062d52
JM		 1602
1603int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1604{
1605 u64 out_param;
1606 int err;
1607
1608 if (mlx4_is_mfunc(dev)) {
1609 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1610 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1611 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1612 if (!err)
1613 *idx = get_param_l(&out_param);
1614
1615 return err;
1616 }
1617 return __mlx4_counter_alloc(dev, idx);
1618}
f2a3f6a3
OG		 1619EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1620
ba062d52 1621void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3
OG		 1622{
1623 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1624 return;
1625}
ba062d52
JM		 1626
1627void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1628{
e7dbeba8 1629 u64 in_param = 0;
ba062d52
JM		 1630
1631 if (mlx4_is_mfunc(dev)) {
1632 set_param_l(&in_param, idx);
1633 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1634 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1635 MLX4_CMD_WRAPPED);
1636 return;
1637 }
1638 __mlx4_counter_free(dev, idx);
1639}
f2a3f6a3
OG		 1640EXPORT_SYMBOL_GPL(mlx4_counter_free);
1641
3d73c288 1642static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1643{
1644 struct mlx4_priv *priv = mlx4_priv(dev);
1645 int err;
7ff93f8b 1646 int port;
9a5aa622 1647 __be32 ib_port_default_caps;
225c7b1f 1648
225c7b1f
RD		 1649 err = mlx4_init_uar_table(dev);
1650 if (err) {
1651 mlx4_err(dev, "Failed to initialize "
1652 "user access region table, aborting.\n");
1653 return err;
1654 }
1655
1656 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1657 if (err) {
1658 mlx4_err(dev, "Failed to allocate driver access region, "
1659 "aborting.\n");
1660 goto err_uar_table_free;
1661 }
1662
4979d18f 1663 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f
RD		 1664 if (!priv->kar) {
1665 mlx4_err(dev, "Couldn't map kernel access region, "
1666 "aborting.\n");
1667 err = -ENOMEM;
1668 goto err_uar_free;
1669 }
1670
1671 err = mlx4_init_pd_table(dev);
1672 if (err) {
1673 mlx4_err(dev, "Failed to initialize "
1674 "protection domain table, aborting.\n");
1675 goto err_kar_unmap;
1676 }
1677
012a8ff5
SH		 1678 err = mlx4_init_xrcd_table(dev);
1679 if (err) {
1680 mlx4_err(dev, "Failed to initialize "
1681 "reliable connection domain table, aborting.\n");
1682 goto err_pd_table_free;
1683 }
1684
225c7b1f
RD		 1685 err = mlx4_init_mr_table(dev);
1686 if (err) {
1687 mlx4_err(dev, "Failed to initialize "
1688 "memory region table, aborting.\n");
012a8ff5 1689 goto err_xrcd_table_free;
225c7b1f
RD		 1690 }
1691
225c7b1f
RD		 1692 err = mlx4_init_eq_table(dev);
1693 if (err) {
1694 mlx4_err(dev, "Failed to initialize "
1695 "event queue table, aborting.\n");
ee49bd93 1696 goto err_mr_table_free;
225c7b1f
RD		 1697 }
1698
1699 err = mlx4_cmd_use_events(dev);
1700 if (err) {
1701 mlx4_err(dev, "Failed to switch to event-driven "
1702 "firmware commands, aborting.\n");
1703 goto err_eq_table_free;
1704 }
1705
1706 err = mlx4_NOP(dev);
1707 if (err) {
08fb1055
MT		 1708 if (dev->flags & MLX4_FLAG_MSI_X) {
1709 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1710 "interrupt IRQ %d).\n",
b8dd786f 1711 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 1712 mlx4_warn(dev, "Trying again without MSI-X.\n");
1713 } else {
1714 mlx4_err(dev, "NOP command failed to generate interrupt "
1715 "(IRQ %d), aborting.\n",
b8dd786f 1716 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1717 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1718 }
225c7b1f
RD		 1719
1720 goto err_cmd_poll;
1721 }
1722
1723 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1724
1725 err = mlx4_init_cq_table(dev);
1726 if (err) {
1727 mlx4_err(dev, "Failed to initialize "
1728 "completion queue table, aborting.\n");
1729 goto err_cmd_poll;
1730 }
1731
1732 err = mlx4_init_srq_table(dev);
1733 if (err) {
1734 mlx4_err(dev, "Failed to initialize "
1735 "shared receive queue table, aborting.\n");
1736 goto err_cq_table_free;
1737 }
1738
1739 err = mlx4_init_qp_table(dev);
1740 if (err) {
1741 mlx4_err(dev, "Failed to initialize "
1742 "queue pair table, aborting.\n");
1743 goto err_srq_table_free;
1744 }
1745
ab9c17a0
JM		 1746 if (!mlx4_is_slave(dev)) {
1747 err = mlx4_init_mcg_table(dev);
1748 if (err) {
1749 mlx4_err(dev, "Failed to initialize "
1750 "multicast group table, aborting.\n");
1751 goto err_qp_table_free;
1752 }
225c7b1f
RD		 1753 }
1754
f2a3f6a3
OG		 1755 err = mlx4_init_counters_table(dev);
1756 if (err && err != -ENOENT) {
1757 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
ab9c17a0 1758 goto err_mcg_table_free;
f2a3f6a3
OG		 1759 }
1760
ab9c17a0
JM		 1761 if (!mlx4_is_slave(dev)) {
1762 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1763 ib_port_default_caps = 0;
1764 err = mlx4_get_port_ib_caps(dev, port,
1765 &ib_port_default_caps);
1766 if (err)
1767 mlx4_warn(dev, "failed to get port %d default "
1768 "ib capabilities (%d). Continuing "
1769 "with caps = 0\n", port, err);
1770 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1771
2aca1172
JM		 1772 /* initialize per-slave default ib port capabilities */
1773 if (mlx4_is_master(dev)) {
1774 int i;
1775 for (i = 0; i < dev->num_slaves; i++) {
1776 if (i == mlx4_master_func_num(dev))
1777 continue;
1778 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1779 ib_port_default_caps;
1780 }
1781 }
1782
096335b3
OG		 1783 if (mlx4_is_mfunc(dev))
1784 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1785 else
1786 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 1787
6634961c
JM		 1788 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1789 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 1790 if (err) {
1791 mlx4_err(dev, "Failed to set port %d, aborting\n",
1792 port);
1793 goto err_counters_table_free;
1794 }
7ff93f8b
YP		 1795 }
1796 }
1797
225c7b1f
RD		 1798 return 0;
1799
f2a3f6a3
OG		 1800err_counters_table_free:
1801 mlx4_cleanup_counters_table(dev);
1802
ab9c17a0
JM		 1803err_mcg_table_free:
1804 mlx4_cleanup_mcg_table(dev);
1805
225c7b1f
RD		 1806err_qp_table_free:
1807 mlx4_cleanup_qp_table(dev);
1808
1809err_srq_table_free:
1810 mlx4_cleanup_srq_table(dev);
1811
1812err_cq_table_free:
1813 mlx4_cleanup_cq_table(dev);
1814
1815err_cmd_poll:
1816 mlx4_cmd_use_polling(dev);
1817
1818err_eq_table_free:
1819 mlx4_cleanup_eq_table(dev);
1820
ee49bd93 1821err_mr_table_free:
225c7b1f
RD		 1822 mlx4_cleanup_mr_table(dev);
1823
012a8ff5
SH		 1824err_xrcd_table_free:
1825 mlx4_cleanup_xrcd_table(dev);
1826
225c7b1f
RD		 1827err_pd_table_free:
1828 mlx4_cleanup_pd_table(dev);
1829
1830err_kar_unmap:
1831 iounmap(priv->kar);
1832
1833err_uar_free:
1834 mlx4_uar_free(dev, &priv->driver_uar);
1835
1836err_uar_table_free:
1837 mlx4_cleanup_uar_table(dev);
1838 return err;
1839}
1840
e8f9b2ed 1841static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 1842{
1843 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 1844 struct msix_entry *entries;
0b7ca5a9 1845 int nreq = min_t(int, dev->caps.num_ports *
90b1ebe7
YM		 1846 min_t(int, netif_get_num_default_rss_queues() + 1,
1847 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 1848 int err;
1849 int i;
1850
1851 if (msi_x) {
ca4c7b35
OG		 1852 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1853 nreq);
ab9c17a0 1854
b8dd786f
YP		 1855 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1856 if (!entries)
1857 goto no_msi;
1858
1859 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1860 entries[i].entry = i;
1861
b8dd786f
YP		 1862 retry:
1863 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 1864 if (err) {
b8dd786f
YP		 1865 /* Try again if at least 2 vectors are available */
1866 if (err > 1) {
1867 mlx4_info(dev, "Requested %d vectors, "
1868 "but only %d MSI-X vectors available, "
1869 "trying again\n", nreq, err);
1870 nreq = err;
1871 goto retry;
1872 }
5bf0da7d 1873 kfree(entries);
225c7b1f
RD		 1874 goto no_msi;
1875 }
1876
0b7ca5a9
YP		 1877 if (nreq <
1878 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1879 /*Working in legacy mode , all EQ's shared*/
1880 dev->caps.comp_pool = 0;
1881 dev->caps.num_comp_vectors = nreq - 1;
1882 } else {
1883 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1884 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1885 }
b8dd786f 1886 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1887 priv->eq_table.eq[i].irq = entries[i].vector;
1888
1889 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 1890
1891 kfree(entries);
225c7b1f
RD		 1892 return;
1893 }
1894
1895no_msi:
b8dd786f 1896 dev->caps.num_comp_vectors = 1;
0b7ca5a9 1897 dev->caps.comp_pool = 0;
b8dd786f
YP		 1898
1899 for (i = 0; i < 2; ++i)
225c7b1f
RD		 1900 priv->eq_table.eq[i].irq = dev->pdev->irq;
1901}
1902
7ff93f8b 1903static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 1904{
1905 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 1906 int err = 0;
2a2336f8
YP		 1907
1908 info->dev = dev;
1909 info->port = port;
ab9c17a0 1910 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1911 mlx4_init_mac_table(dev, &info->mac_table);
1912 mlx4_init_vlan_table(dev, &info->vlan_table);
16a10ffd 1913 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 1914 }
7ff93f8b
YP		 1915
1916 sprintf(info->dev_name, "mlx4_port%d", port);
1917 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 1918 if (mlx4_is_mfunc(dev))
1919 info->port_attr.attr.mode = S_IRUGO;
1920 else {
1921 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1922 info->port_attr.store = set_port_type;
1923 }
7ff93f8b 1924 info->port_attr.show = show_port_type;
3691c964 1925 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 1926
1927 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1928 if (err) {
1929 mlx4_err(dev, "Failed to create file for port %d\n", port);
1930 info->port = -1;
1931 }
1932
096335b3
OG		 1933 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1934 info->port_mtu_attr.attr.name = info->dev_mtu_name;
1935 if (mlx4_is_mfunc(dev))
1936 info->port_mtu_attr.attr.mode = S_IRUGO;
1937 else {
1938 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1939 info->port_mtu_attr.store = set_port_ib_mtu;
1940 }
1941 info->port_mtu_attr.show = show_port_ib_mtu;
1942 sysfs_attr_init(&info->port_mtu_attr.attr);
1943
1944 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1945 if (err) {
1946 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1947 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1948 info->port = -1;
1949 }
1950
7ff93f8b
YP		 1951 return err;
1952}
1953
1954static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1955{
1956 if (info->port < 0)
1957 return;
1958
1959 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 1960 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 1961}
1962
b12d93d6
YP		 1963static int mlx4_init_steering(struct mlx4_dev *dev)
1964{
1965 struct mlx4_priv *priv = mlx4_priv(dev);
1966 int num_entries = dev->caps.num_ports;
1967 int i, j;
1968
1969 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1970 if (!priv->steer)
1971 return -ENOMEM;
1972
45b51365 1973 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 1974 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1975 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1976 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1977 }
b12d93d6
YP		 1978 return 0;
1979}
1980
1981static void mlx4_clear_steering(struct mlx4_dev *dev)
1982{
1983 struct mlx4_priv *priv = mlx4_priv(dev);
1984 struct mlx4_steer_index *entry, *tmp_entry;
1985 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1986 int num_entries = dev->caps.num_ports;
1987 int i, j;
1988
1989 for (i = 0; i < num_entries; i++) {
1990 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1991 list_for_each_entry_safe(pqp, tmp_pqp,
1992 &priv->steer[i].promisc_qps[j],
1993 list) {
1994 list_del(&pqp->list);
1995 kfree(pqp);
1996 }
1997 list_for_each_entry_safe(entry, tmp_entry,
1998 &priv->steer[i].steer_entries[j],
1999 list) {
2000 list_del(&entry->list);
2001 list_for_each_entry_safe(pqp, tmp_pqp,
2002 &entry->duplicates,
2003 list) {
2004 list_del(&pqp->list);
2005 kfree(pqp);
2006 }
2007 kfree(entry);
2008 }
2009 }
2010 }
2011 kfree(priv->steer);
2012}
2013
ab9c17a0
JM		 2014static int extended_func_num(struct pci_dev *pdev)
2015{
2016 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2017}
2018
2019#define MLX4_OWNER_BASE 0x8069c
2020#define MLX4_OWNER_SIZE 4
2021
2022static int mlx4_get_ownership(struct mlx4_dev *dev)
2023{
2024 void __iomem *owner;
2025 u32 ret;
2026
57dbf29a
KSS		 2027 if (pci_channel_offline(dev->pdev))
2028 return -EIO;
2029
ab9c17a0
JM		 2030 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2031 MLX4_OWNER_SIZE);
2032 if (!owner) {
2033 mlx4_err(dev, "Failed to obtain ownership bit\n");
2034 return -ENOMEM;
2035 }
2036
2037 ret = readl(owner);
2038 iounmap(owner);
2039 return (int) !!ret;
2040}
2041
2042static void mlx4_free_ownership(struct mlx4_dev *dev)
2043{
2044 void __iomem *owner;
2045
57dbf29a
KSS		 2046 if (pci_channel_offline(dev->pdev))
2047 return;
2048
ab9c17a0
JM		 2049 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2050 MLX4_OWNER_SIZE);
2051 if (!owner) {
2052 mlx4_err(dev, "Failed to obtain ownership bit\n");
2053 return;
2054 }
2055 writel(0, owner);
2056 msleep(1000);
2057 iounmap(owner);
2058}
2059
839f1243 2060static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
225c7b1f 2061{
225c7b1f
RD		 2062 struct mlx4_priv *priv;
2063 struct mlx4_dev *dev;
2064 int err;
2a2336f8 2065 int port;
225c7b1f 2066
0a645e80 2067 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 2068
2069 err = pci_enable_device(pdev);
2070 if (err) {
2071 dev_err(&pdev->dev, "Cannot enable PCI device, "
2072 "aborting.\n");
2073 return err;
2074 }
ab9c17a0
JM		 2075 if (num_vfs > MLX4_MAX_NUM_VF) {
2076 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
2077 num_vfs, MLX4_MAX_NUM_VF);
2078 return -EINVAL;
2079 }
225c7b1f 2080 /*
ab9c17a0 2081 * Check for BARs.
225c7b1f 2082 */
839f1243 2083 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
ab9c17a0
JM		 2084 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2085 dev_err(&pdev->dev, "Missing DCS, aborting."
839f1243
RD		 2086 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2087 pci_dev_data, pci_resource_flags(pdev, 0));
225c7b1f
RD		 2088 err = -ENODEV;
2089 goto err_disable_pdev;
2090 }
2091 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2092 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2093 err = -ENODEV;
2094 goto err_disable_pdev;
2095 }
2096
a01df0fe 2097 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 2098 if (err) {
a01df0fe 2099 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 2100 goto err_disable_pdev;
2101 }
2102
225c7b1f
RD		 2103 pci_set_master(pdev);
2104
6a35528a 2105 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 2106 if (err) {
2107 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 2108 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 2109 if (err) {
2110 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 2111 goto err_release_regions;
225c7b1f
RD		 2112 }
2113 }
6a35528a 2114 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 2115 if (err) {
2116 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2117 "consistent PCI DMA mask.\n");
284901a9 2118 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 2119 if (err) {
2120 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2121 "aborting.\n");
a01df0fe 2122 goto err_release_regions;
225c7b1f
RD		 2123 }
2124 }
2125
7f9e5c48
DD		 2126 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2127 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2128
b2adaca9 2129 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
225c7b1f 2130 if (!priv) {
225c7b1f 2131 err = -ENOMEM;
a01df0fe 2132 goto err_release_regions;
225c7b1f
RD		 2133 }
2134
2135 dev = &priv->dev;
2136 dev->pdev = pdev;
b581401e
RD		 2137 INIT_LIST_HEAD(&priv->ctx_list);
2138 spin_lock_init(&priv->ctx_lock);
225c7b1f 2139
7ff93f8b
YP		 2140 mutex_init(&priv->port_mutex);
2141
6296883c
YP		 2142 INIT_LIST_HEAD(&priv->pgdir_list);
2143 mutex_init(&priv->pgdir_mutex);
2144
c1b43dca
EC		 2145 INIT_LIST_HEAD(&priv->bf_list);
2146 mutex_init(&priv->bf_mutex);
2147
aca7a3ac 2148 dev->rev_id = pdev->revision;
ab9c17a0 2149 /* Detect if this device is a virtual function */
839f1243 2150 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2151 /* When acting as pf, we normally skip vfs unless explicitly
2152 * requested to probe them. */
2153 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2154 mlx4_warn(dev, "Skipping virtual function:%d\n",
2155 extended_func_num(pdev));
2156 err = -ENODEV;
2157 goto err_free_dev;
2158 }
2159 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2160 dev->flags |= MLX4_FLAG_SLAVE;
2161 } else {
2162 /* We reset the device and enable SRIOV only for physical
2163 * devices. Try to claim ownership on the device;
2164 * if already taken, skip -- do not allow multiple PFs */
2165 err = mlx4_get_ownership(dev);
2166 if (err) {
2167 if (err < 0)
2168 goto err_free_dev;
2169 else {
2170 mlx4_warn(dev, "Multiple PFs not yet supported."
2171 " Skipping PF.\n");
2172 err = -EINVAL;
2173 goto err_free_dev;
2174 }
2175 }
aca7a3ac 2176
ab9c17a0 2177 if (num_vfs) {
84b1f153 2178 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
ab9c17a0
JM		 2179 err = pci_enable_sriov(pdev, num_vfs);
2180 if (err) {
84b1f153
RD		 2181 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2182 err);
ab9c17a0
JM		 2183 err = 0;
2184 } else {
2185 mlx4_warn(dev, "Running in master mode\n");
2186 dev->flags |= MLX4_FLAG_SRIOV |
2187 MLX4_FLAG_MASTER;
2188 dev->num_vfs = num_vfs;
2189 }
2190 }
2191
2192 /*
2193 * Now reset the HCA before we touch the PCI capabilities or
2194 * attempt a firmware command, since a boot ROM may have left
2195 * the HCA in an undefined state.
2196 */
2197 err = mlx4_reset(dev);
2198 if (err) {
2199 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2200 goto err_rel_own;
2201 }
225c7b1f
RD		 2202 }
2203
ab9c17a0 2204slave_start:
521130d1
EE		 2205 err = mlx4_cmd_init(dev);
2206 if (err) {
225c7b1f 2207 mlx4_err(dev, "Failed to init command interface, aborting.\n");
ab9c17a0
JM		 2208 goto err_sriov;
2209 }
2210
2211 /* In slave functions, the communication channel must be initialized
2212 * before posting commands. Also, init num_slaves before calling
2213 * mlx4_init_hca */
2214 if (mlx4_is_mfunc(dev)) {
2215 if (mlx4_is_master(dev))
2216 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2217 else {
2218 dev->num_slaves = 0;
f356fcbe
JM		 2219 err = mlx4_multi_func_init(dev);
2220 if (err) {
ab9c17a0
JM		 2221 mlx4_err(dev, "Failed to init slave mfunc"
2222 " interface, aborting.\n");
2223 goto err_cmd;
2224 }
2225 }
225c7b1f
RD		 2226 }
2227
2228 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2229 if (err) {
2230 if (err == -EACCES) {
2231 /* Not primary Physical function
2232 * Running in slave mode */
2233 mlx4_cmd_cleanup(dev);
2234 dev->flags |= MLX4_FLAG_SLAVE;
2235 dev->flags &= ~MLX4_FLAG_MASTER;
2236 goto slave_start;
2237 } else
2238 goto err_mfunc;
2239 }
2240
2241 /* In master functions, the communication channel must be initialized
2242 * after obtaining its address from fw */
2243 if (mlx4_is_master(dev)) {
f356fcbe
JM		 2244 err = mlx4_multi_func_init(dev);
2245 if (err) {
ab9c17a0
JM		 2246 mlx4_err(dev, "Failed to init master mfunc"
2247 "interface, aborting.\n");
2248 goto err_close;
2249 }
2250 }
225c7b1f 2251
b8dd786f
YP		 2252 err = mlx4_alloc_eq_table(dev);
2253 if (err)
ab9c17a0 2254 goto err_master_mfunc;
b8dd786f 2255
0b7ca5a9 2256 priv->msix_ctl.pool_bm = 0;
730c41d5 2257 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2258
08fb1055 2259 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2260 if ((mlx4_is_mfunc(dev)) &&
2261 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2262 err = -ENOSYS;
ab9c17a0
JM		 2263 mlx4_err(dev, "INTx is not supported in multi-function mode."
2264 " aborting.\n");
b12d93d6 2265 goto err_free_eq;
ab9c17a0
JM		 2266 }
2267
2268 if (!mlx4_is_slave(dev)) {
2269 err = mlx4_init_steering(dev);
2270 if (err)
2271 goto err_free_eq;
2272 }
b12d93d6 2273
225c7b1f 2274 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2275 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2276 !mlx4_is_mfunc(dev)) {
08fb1055 2277 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2278 dev->caps.num_comp_vectors = 1;
2279 dev->caps.comp_pool = 0;
08fb1055
MT		 2280 pci_disable_msix(pdev);
2281 err = mlx4_setup_hca(dev);
2282 }
2283
225c7b1f 2284 if (err)
b12d93d6 2285 goto err_steer;
225c7b1f 2286
7ff93f8b
YP		 2287 for (port = 1; port <= dev->caps.num_ports; port++) {
2288 err = mlx4_init_port_info(dev, port);
2289 if (err)
2290 goto err_port;
2291 }
2a2336f8 2292
225c7b1f
RD		 2293 err = mlx4_register_device(dev);
2294 if (err)
7ff93f8b 2295 goto err_port;
225c7b1f 2296
27bf91d6
YP		 2297 mlx4_sense_init(dev);
2298 mlx4_start_sense(dev);
2299
839f1243 2300 priv->pci_dev_data = pci_dev_data;
225c7b1f
RD		 2301 pci_set_drvdata(pdev, dev);
2302
2303 return 0;
2304
7ff93f8b 2305err_port:
b4f77264 2306 for (--port; port >= 1; --port)
7ff93f8b
YP		 2307 mlx4_cleanup_port_info(&priv->port[port]);
2308
f2a3f6a3 2309 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2310 mlx4_cleanup_mcg_table(dev);
2311 mlx4_cleanup_qp_table(dev);
2312 mlx4_cleanup_srq_table(dev);
2313 mlx4_cleanup_cq_table(dev);
2314 mlx4_cmd_use_polling(dev);
2315 mlx4_cleanup_eq_table(dev);
225c7b1f 2316 mlx4_cleanup_mr_table(dev);
012a8ff5 2317 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2318 mlx4_cleanup_pd_table(dev);
2319 mlx4_cleanup_uar_table(dev);
2320
b12d93d6 2321err_steer:
ab9c17a0
JM		 2322 if (!mlx4_is_slave(dev))
2323 mlx4_clear_steering(dev);
b12d93d6 2324
b8dd786f
YP		 2325err_free_eq:
2326 mlx4_free_eq_table(dev);
2327
ab9c17a0
JM		 2328err_master_mfunc:
2329 if (mlx4_is_master(dev))
2330 mlx4_multi_func_cleanup(dev);
2331
225c7b1f 2332err_close:
08fb1055
MT		 2333 if (dev->flags & MLX4_FLAG_MSI_X)
2334 pci_disable_msix(pdev);
2335
225c7b1f
RD		 2336 mlx4_close_hca(dev);
2337
ab9c17a0
JM		 2338err_mfunc:
2339 if (mlx4_is_slave(dev))
2340 mlx4_multi_func_cleanup(dev);
2341
225c7b1f
RD		 2342err_cmd:
2343 mlx4_cmd_cleanup(dev);
2344
ab9c17a0 2345err_sriov:
681372a7 2346 if (dev->flags & MLX4_FLAG_SRIOV)
ab9c17a0
JM		 2347 pci_disable_sriov(pdev);
2348
2349err_rel_own:
2350 if (!mlx4_is_slave(dev))
2351 mlx4_free_ownership(dev);
2352
225c7b1f 2353err_free_dev:
225c7b1f
RD		 2354 kfree(priv);
2355
a01df0fe
RD		 2356err_release_regions:
2357 pci_release_regions(pdev);
225c7b1f
RD		 2358
2359err_disable_pdev:
2360 pci_disable_device(pdev);
2361 pci_set_drvdata(pdev, NULL);
2362 return err;
2363}
2364
1dd06ae8 2365static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 2366{
0a645e80 2367 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2368
839f1243 2369 return __mlx4_init_one(pdev, id->driver_data);
3d73c288
RD		 2370}
2371
2372static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 2373{
2374 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2375 struct mlx4_priv *priv = mlx4_priv(dev);
2376 int p;
2377
2378 if (dev) {
ab9c17a0
JM		 2379 /* in SRIOV it is not allowed to unload the pf's
2380 * driver while there are alive vf's */
2381 if (mlx4_is_master(dev)) {
2382 if (mlx4_how_many_lives_vf(dev))
2383 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2384 }
27bf91d6 2385 mlx4_stop_sense(dev);
225c7b1f
RD		 2386 mlx4_unregister_device(dev);
2387
7ff93f8b
YP		 2388 for (p = 1; p <= dev->caps.num_ports; p++) {
2389 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 2390 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 2391 }
225c7b1f 2392
b8924951
JM		 2393 if (mlx4_is_master(dev))
2394 mlx4_free_resource_tracker(dev,
2395 RES_TR_FREE_SLAVES_ONLY);
2396
f2a3f6a3 2397 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2398 mlx4_cleanup_mcg_table(dev);
2399 mlx4_cleanup_qp_table(dev);
2400 mlx4_cleanup_srq_table(dev);
2401 mlx4_cleanup_cq_table(dev);
2402 mlx4_cmd_use_polling(dev);
2403 mlx4_cleanup_eq_table(dev);
225c7b1f 2404 mlx4_cleanup_mr_table(dev);
012a8ff5 2405 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2406 mlx4_cleanup_pd_table(dev);
2407
ab9c17a0 2408 if (mlx4_is_master(dev))
b8924951
JM		 2409 mlx4_free_resource_tracker(dev,
2410 RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 2411
225c7b1f
RD		 2412 iounmap(priv->kar);
2413 mlx4_uar_free(dev, &priv->driver_uar);
2414 mlx4_cleanup_uar_table(dev);
ab9c17a0
JM		 2415 if (!mlx4_is_slave(dev))
2416 mlx4_clear_steering(dev);
b8dd786f 2417 mlx4_free_eq_table(dev);
ab9c17a0
JM		 2418 if (mlx4_is_master(dev))
2419 mlx4_multi_func_cleanup(dev);
225c7b1f 2420 mlx4_close_hca(dev);
ab9c17a0
JM		 2421 if (mlx4_is_slave(dev))
2422 mlx4_multi_func_cleanup(dev);
225c7b1f
RD		 2423 mlx4_cmd_cleanup(dev);
2424
2425 if (dev->flags & MLX4_FLAG_MSI_X)
2426 pci_disable_msix(pdev);
681372a7 2427 if (dev->flags & MLX4_FLAG_SRIOV) {
84b1f153 2428 mlx4_warn(dev, "Disabling SR-IOV\n");
ab9c17a0
JM		 2429 pci_disable_sriov(pdev);
2430 }
225c7b1f 2431
ab9c17a0
JM		 2432 if (!mlx4_is_slave(dev))
2433 mlx4_free_ownership(dev);
47605df9
JM		 2434
2435 kfree(dev->caps.qp0_tunnel);
2436 kfree(dev->caps.qp0_proxy);
2437 kfree(dev->caps.qp1_tunnel);
2438 kfree(dev->caps.qp1_proxy);
2439
225c7b1f 2440 kfree(priv);
a01df0fe 2441 pci_release_regions(pdev);
225c7b1f
RD		 2442 pci_disable_device(pdev);
2443 pci_set_drvdata(pdev, NULL);
2444 }
2445}
2446
ee49bd93
JM		 2447int mlx4_restart_one(struct pci_dev *pdev)
2448{
839f1243
RD		 2449 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2450 struct mlx4_priv *priv = mlx4_priv(dev);
2451 int pci_dev_data;
2452
2453 pci_dev_data = priv->pci_dev_data;
ee49bd93 2454 mlx4_remove_one(pdev);
839f1243 2455 return __mlx4_init_one(pdev, pci_dev_data);
ee49bd93
JM		 2456}
2457
a3aa1884 2458static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0 2459 /* MT25408 "Hermon" SDR */
ca3e57a5 2460 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2461 /* MT25408 "Hermon" DDR */
ca3e57a5 2462 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2463 /* MT25408 "Hermon" QDR */
ca3e57a5 2464 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2465 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 2466 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2467 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 2468 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2469 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 2470 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2471 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 2472 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2473 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 2474 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2475 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 2476 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2477 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 2478 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2479 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 2480 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2481 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 2482 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2483 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 2484 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2485 /* MT27500 Family [ConnectX-3] */
2486 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2487 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 2488 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2489 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2490 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2491 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2492 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2493 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2494 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2495 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2496 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2497 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2498 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2499 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2500 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2501 { 0, }
2502};
2503
2504MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2505
57dbf29a
KSS		 2506static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2507 pci_channel_state_t state)
2508{
2509 mlx4_remove_one(pdev);
2510
2511 return state == pci_channel_io_perm_failure ?
2512 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2513}
2514
2515static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2516{
839f1243 2517 int ret = __mlx4_init_one(pdev, 0);
57dbf29a
KSS		 2518
2519 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2520}
2521
3646f0e5 2522static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 2523 .error_detected = mlx4_pci_err_detected,
2524 .slot_reset = mlx4_pci_slot_reset,
2525};
2526
225c7b1f
RD		 2527static struct pci_driver mlx4_driver = {
2528 .name = DRV_NAME,
2529 .id_table = mlx4_pci_table,
2530 .probe = mlx4_init_one,
f57e6848 2531 .remove = mlx4_remove_one,
57dbf29a 2532 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 2533};
2534
7ff93f8b
YP		 2535static int __init mlx4_verify_params(void)
2536{
2537 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2538 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2539 return -1;
2540 }
2541
cb29688a
OG		 2542 if (log_num_vlan != 0)
2543 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2544 MLX4_LOG_NUM_VLANS);
7ff93f8b 2545
0498628f 2546 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2547 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2548 return -1;
2549 }
2550
ab9c17a0
JM		 2551 /* Check if module param for ports type has legal combination */
2552 if (port_type_array[0] == false && port_type_array[1] == true) {
2553 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2554 port_type_array[0] = true;
2555 }
2556
3c439b55
JM		 2557 if (mlx4_log_num_mgm_entry_size != -1 &&
2558 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2559 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2560 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2561 "in legal range (-1 or %d..%d)\n",
2562 mlx4_log_num_mgm_entry_size,
2563 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2564 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2565 return -1;
2566 }
2567
7ff93f8b
YP		 2568 return 0;
2569}
2570
225c7b1f
RD		 2571static int __init mlx4_init(void)
2572{
2573 int ret;
2574
7ff93f8b
YP		 2575 if (mlx4_verify_params())
2576 return -EINVAL;
2577
27bf91d6
YP		 2578 mlx4_catas_init();
2579
2580 mlx4_wq = create_singlethread_workqueue("mlx4");
2581 if (!mlx4_wq)
2582 return -ENOMEM;
ee49bd93 2583
225c7b1f
RD		 2584 ret = pci_register_driver(&mlx4_driver);
2585 return ret < 0 ? ret : 0;
2586}
2587
2588static void __exit mlx4_cleanup(void)
2589{
2590 pci_unregister_driver(&mlx4_driver);
27bf91d6 2591 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2592}
2593
2594module_init(mlx4_init);
2595module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)