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net/mlx4: Add mlx4_bitmap zone allocator
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
dd41cc3b 80static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 81static int num_vfs_argc;
dd41cc3b
MB		 82module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 87static int probe_vfs_argc;
dd41cc3b
MB		 88module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
ab9c17a0 91
3c439b55 92int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 93module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
3c439b55 97 " 10 gives 248.range: 7 <="
0ff1fb65 98 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 99 " To activate device managed"
100 " flow steering when available, set to -1");
0ec2c0f8 101
be902ab1 102static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 103module_param(enable_64b_cqe_eqe, bool, 0444);
104MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 106
77507aa2
IS		 107#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
108 MLX4_FUNC_CAP_EQE_CQE_STRIDE)
ab9c17a0 109
f57e6848 110static char mlx4_version[] =
225c7b1f
RD		 111 DRV_NAME ": Mellanox ConnectX core driver v"
112 DRV_VERSION " (" DRV_RELDATE ")\n";
113
114static struct mlx4_profile default_profile = {
ab9c17a0 115 .num_qp = 1 << 18,
225c7b1f 116 .num_srq = 1 << 16,
c9f2ba5e 117 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 118 .num_cq = 1 << 16,
119 .num_mcg = 1 << 13,
ab9c17a0 120 .num_mpt = 1 << 19,
9fd7a1e1 121 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 122};
123
2599d858
AV		 124static struct mlx4_profile low_mem_profile = {
125 .num_qp = 1 << 17,
126 .num_srq = 1 << 6,
127 .rdmarc_per_qp = 1 << 4,
128 .num_cq = 1 << 8,
129 .num_mcg = 1 << 8,
130 .num_mpt = 1 << 9,
131 .num_mtt = 1 << 7,
132};
133
ab9c17a0 134static int log_num_mac = 7;
93fc9e1b
YP		 135module_param_named(log_num_mac, log_num_mac, int, 0444);
136MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
137
138static int log_num_vlan;
139module_param_named(log_num_vlan, log_num_vlan, int, 0444);
140MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 141/* Log2 max number of VLANs per ETH port (0-7) */
142#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 143#define MLX4_MIN_LOG_NUM_VLANS 0
144#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 145
eb939922 146static bool use_prio;
93fc9e1b 147module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 148MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 149
2b8fb286 150int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 151module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 152MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 153
8d0fc7b6 154static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 155static int arr_argc = 2;
156module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 157MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
158 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 159
160struct mlx4_port_config {
161 struct list_head list;
162 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
163 struct pci_dev *pdev;
164};
165
97989356
AV		 166static atomic_t pf_loading = ATOMIC_INIT(0);
167
27bf91d6
YP		 168int mlx4_check_port_params(struct mlx4_dev *dev,
169 enum mlx4_port_type *port_type)
7ff93f8b
YP		 170{
171 int i;
172
173 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 174 if (port_type[i] != port_type[i + 1]) {
175 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
1a91de28 176 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 177 return -EINVAL;
178 }
7ff93f8b
YP		 179 }
180 }
7ff93f8b
YP		 181
182 for (i = 0; i < dev->caps.num_ports; i++) {
183 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 184 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
185 i + 1);
7ff93f8b
YP		 186 return -EINVAL;
187 }
188 }
189 return 0;
190}
191
192static void mlx4_set_port_mask(struct mlx4_dev *dev)
193{
194 int i;
195
7ff93f8b 196 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 197 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 198}
f2a3f6a3 199
7ae0e400
MB		 200enum {
201 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
202};
203
204static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
205{
206 int err = 0;
207 struct mlx4_func func;
208
209 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
210 err = mlx4_QUERY_FUNC(dev, &func, 0);
211 if (err) {
212 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
213 return err;
214 }
215 dev_cap->max_eqs = func.max_eq;
216 dev_cap->reserved_eqs = func.rsvd_eqs;
217 dev_cap->reserved_uars = func.rsvd_uars;
218 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
219 }
220 return err;
221}
222
77507aa2
IS		 223static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
224{
225 struct mlx4_caps *dev_cap = &dev->caps;
226
227 /* FW not supporting or cancelled by user */
228 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
229 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
230 return;
231
232 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
233 * When FW has NCSI it may decide not to report 64B CQE/EQEs
234 */
235 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
236 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
237 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
238 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
239 return;
240 }
241
242 if (cache_line_size() == 128 || cache_line_size() == 256) {
243 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
244 /* Changing the real data inside CQE size to 32B */
245 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
246 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
247
248 if (mlx4_is_master(dev))
249 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
250 } else {
251 mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n");
252 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
253 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
254 }
255}
256
3d73c288 257static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 258{
259 int err;
5ae2a7a8 260 int i;
225c7b1f
RD		 261
262 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
263 if (err) {
1a91de28 264 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 265 return err;
266 }
267
268 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 269 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 270 dev_cap->min_page_sz, PAGE_SIZE);
271 return -ENODEV;
272 }
273 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 274 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 275 dev_cap->num_ports, MLX4_MAX_PORTS);
276 return -ENODEV;
277 }
278
279 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
1a91de28 280 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f
RD		 281 dev_cap->uar_size,
282 (unsigned long long) pci_resource_len(dev->pdev, 2));
283 return -ENODEV;
284 }
285
286 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 287 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
288 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
289 dev->caps.num_sys_eqs :
290 MLX4_MAX_EQ_NUM;
5ae2a7a8
RD		 291 for (i = 1; i <= dev->caps.num_ports; ++i) {
292 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 293 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
6634961c
JM		 294 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
295 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
296 /* set gid and pkey table operating lengths by default
297 * to non-sriov values */
5ae2a7a8
RD		 298 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
299 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
300 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 301 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
302 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 303 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 304 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
305 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 306 dev->caps.trans_type[i] = dev_cap->trans_type[i];
307 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
308 dev->caps.wavelength[i] = dev_cap->wavelength[i];
309 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 310 }
311
ab9c17a0 312 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 313 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 314 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
315 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
316 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
317 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
318 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
319 dev->caps.max_wqes = dev_cap->max_qp_sz;
320 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 321 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
322 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
323 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
324 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
325 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 326 /*
327 * Subtract 1 from the limit because we need to allocate a
328 * spare CQE so the HCA HW can tell the difference between an
329 * empty CQ and a full CQ.
330 */
331 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
332 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
333 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 334 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 335 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 336
337 /* The first 128 UARs are used for EQ doorbells */
338 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 339 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 340 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
341 dev_cap->reserved_xrcds : 0;
342 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
343 dev_cap->max_xrcds : 0;
2b8fb286
MA		 344 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
345
149983af 346 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 347 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
348 dev->caps.flags = dev_cap->flags;
b3416f44 349 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 350 dev->caps.bmme_flags = dev_cap->bmme_flags;
351 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 352 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 353 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 354 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 355
ca3e57a5
RD		 356 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
357 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 358 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 359 /* Don't do sense port on multifunction devices (for now at least) */
360 if (mlx4_is_mfunc(dev))
361 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 362
2599d858
AV		 363 if (mlx4_low_memory_profile()) {
364 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
365 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
366 } else {
367 dev->caps.log_num_macs = log_num_mac;
368 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
369 }
93fc9e1b
YP		 370
371 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 372 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
373 if (dev->caps.supported_type[i]) {
374 /* if only ETH is supported - assign ETH */
375 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
376 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 377 /* if only IB is supported, assign IB */
ab9c17a0 378 else if (dev->caps.supported_type[i] ==
105c320f
JM		 379 MLX4_PORT_TYPE_IB)
380 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 381 else {
105c320f
JM		 382 /* if IB and ETH are supported, we set the port
383 * type according to user selection of port type;
384 * if user selected none, take the FW hint */
385 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 386 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
387 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 388 else
105c320f 389 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 390 }
391 }
8d0fc7b6
YP		 392 /*
393 * Link sensing is allowed on the port if 3 conditions are true:
394 * 1. Both protocols are supported on the port.
395 * 2. Different types are supported on the port
396 * 3. FW declared that it supports link sensing
397 */
27bf91d6 398 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 399 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 400 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 401 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 402
8d0fc7b6
YP		 403 /*
404 * If "default_sense" bit is set, we move the port to "AUTO" mode
405 * and perform sense_port FW command to try and set the correct
406 * port type from beginning
407 */
46c46747 408 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 409 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
410 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
411 mlx4_SENSE_PORT(dev, i, &sensed_port);
412 if (sensed_port != MLX4_PORT_TYPE_NONE)
413 dev->caps.port_type[i] = sensed_port;
414 } else {
415 dev->caps.possible_type[i] = dev->caps.port_type[i];
416 }
417
93fc9e1b
YP		 418 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
419 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
1a91de28 420 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 421 i, 1 << dev->caps.log_num_macs);
422 }
423 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
424 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
1a91de28 425 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 426 i, 1 << dev->caps.log_num_vlans);
427 }
428 }
429
f2a3f6a3
OG		 430 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
431
93fc9e1b
YP		 432 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
433 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
434 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
435 (1 << dev->caps.log_num_macs) *
436 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 437 dev->caps.num_ports;
438 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
439
440 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
441 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
442 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
443 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
444
e2c76824 445 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 446
b3051320 447 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 448 if (dev_cap->flags &
449 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
450 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
451 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
452 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
453 }
77507aa2
IS		 454
455 if (dev_cap->flags2 &
456 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
457 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
458 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
459 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
460 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
461 }
08ff3235
OG		 462 }
463
f97b4b5d 464 if ((dev->caps.flags &
08ff3235
OG		 465 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
466 mlx4_is_master(dev))
467 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
468
ddae0349 469 if (!mlx4_is_slave(dev)) {
77507aa2 470 mlx4_enable_cqe_eqe_stride(dev);
ddae0349
EE		 471 dev->caps.alloc_res_qp_mask =
472 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0);
473 } else {
474 dev->caps.alloc_res_qp_mask = 0;
475 }
77507aa2 476
225c7b1f
RD		 477 return 0;
478}
b912b2f8
EP		 479
480static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
481 enum pci_bus_speed *speed,
482 enum pcie_link_width *width)
483{
484 u32 lnkcap1, lnkcap2;
485 int err1, err2;
486
487#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
488
489 *speed = PCI_SPEED_UNKNOWN;
490 *width = PCIE_LNK_WIDTH_UNKNOWN;
491
492 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
493 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
494 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
495 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
496 *speed = PCIE_SPEED_8_0GT;
497 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
498 *speed = PCIE_SPEED_5_0GT;
499 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
500 *speed = PCIE_SPEED_2_5GT;
501 }
502 if (!err1) {
503 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
504 if (!lnkcap2) { /* pre-r3.0 */
505 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
506 *speed = PCIE_SPEED_5_0GT;
507 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
508 *speed = PCIE_SPEED_2_5GT;
509 }
510 }
511
512 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
513 return err1 ? err1 :
514 err2 ? err2 : -EINVAL;
515 }
516 return 0;
517}
518
519static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
520{
521 enum pcie_link_width width, width_cap;
522 enum pci_bus_speed speed, speed_cap;
523 int err;
524
525#define PCIE_SPEED_STR(speed) \
526 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
527 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
528 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
529 "Unknown")
530
531 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
532 if (err) {
533 mlx4_warn(dev,
534 "Unable to determine PCIe device BW capabilities\n");
535 return;
536 }
537
538 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
539 if (err || speed == PCI_SPEED_UNKNOWN ||
540 width == PCIE_LNK_WIDTH_UNKNOWN) {
541 mlx4_warn(dev,
542 "Unable to determine PCI device chain minimum BW\n");
543 return;
544 }
545
546 if (width != width_cap || speed != speed_cap)
547 mlx4_warn(dev,
548 "PCIe BW is different than device's capability\n");
549
550 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
551 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
552 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
553 width, width_cap);
554 return;
555}
556
ab9c17a0
JM		 557/*The function checks if there are live vf, return the num of them*/
558static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
559{
560 struct mlx4_priv *priv = mlx4_priv(dev);
561 struct mlx4_slave_state *s_state;
562 int i;
563 int ret = 0;
564
565 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
566 s_state = &priv->mfunc.master.slave_state[i];
567 if (s_state->active && s_state->last_cmd !=
568 MLX4_COMM_CMD_RESET) {
569 mlx4_warn(dev, "%s: slave: %d is still active\n",
570 __func__, i);
571 ret++;
572 }
573 }
574 return ret;
575}
576
396f2feb
JM		 577int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
578{
579 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 580
581 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
582 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 583 return -EINVAL;
584
47605df9 585 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 586 /* tunnel qp */
47605df9 587 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 588 else
47605df9 589 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 590 *qkey = qk;
591 return 0;
592}
593EXPORT_SYMBOL(mlx4_get_parav_qkey);
594
54679e14
JM		 595void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
596{
597 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
598
599 if (!mlx4_is_master(dev))
600 return;
601
602 priv->virt2phys_pkey[slave][port - 1][i] = val;
603}
604EXPORT_SYMBOL(mlx4_sync_pkey_table);
605
afa8fd1d
JM		 606void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
607{
608 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
609
610 if (!mlx4_is_master(dev))
611 return;
612
613 priv->slave_node_guids[slave] = guid;
614}
615EXPORT_SYMBOL(mlx4_put_slave_node_guid);
616
617__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
618{
619 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
620
621 if (!mlx4_is_master(dev))
622 return 0;
623
624 return priv->slave_node_guids[slave];
625}
626EXPORT_SYMBOL(mlx4_get_slave_node_guid);
627
e10903b0 628int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 629{
630 struct mlx4_priv *priv = mlx4_priv(dev);
631 struct mlx4_slave_state *s_slave;
632
633 if (!mlx4_is_master(dev))
634 return 0;
635
636 s_slave = &priv->mfunc.master.slave_state[slave];
637 return !!s_slave->active;
638}
639EXPORT_SYMBOL(mlx4_is_slave_active);
640
7b8157be
JM		 641static void slave_adjust_steering_mode(struct mlx4_dev *dev,
642 struct mlx4_dev_cap *dev_cap,
643 struct mlx4_init_hca_param *hca_param)
644{
645 dev->caps.steering_mode = hca_param->steering_mode;
646 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
647 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
648 dev->caps.fs_log_max_ucast_qp_range_size =
649 dev_cap->fs_log_max_ucast_qp_range_size;
650 } else
651 dev->caps.num_qp_per_mgm =
652 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
653
654 mlx4_dbg(dev, "Steering mode is: %s\n",
655 mlx4_steering_mode_str(dev->caps.steering_mode));
656}
657
ab9c17a0
JM		 658static int mlx4_slave_cap(struct mlx4_dev *dev)
659{
660 int err;
661 u32 page_size;
662 struct mlx4_dev_cap dev_cap;
663 struct mlx4_func_cap func_cap;
664 struct mlx4_init_hca_param hca_param;
225c6c8c 665 u8 i;
ab9c17a0
JM		 666
667 memset(&hca_param, 0, sizeof(hca_param));
668 err = mlx4_QUERY_HCA(dev, &hca_param);
669 if (err) {
1a91de28 670 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
ab9c17a0
JM		 671 return err;
672 }
673
483e0132
EP		 674 /* fail if the hca has an unknown global capability
675 * at this time global_caps should be always zeroed
676 */
677 if (hca_param.global_caps) {
ab9c17a0
JM		 678 mlx4_err(dev, "Unknown hca global capabilities\n");
679 return -ENOSYS;
680 }
681
682 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
683
ddd8a6c1
EE		 684 dev->caps.hca_core_clock = hca_param.hca_core_clock;
685
ab9c17a0 686 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 687 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 688 err = mlx4_dev_cap(dev, &dev_cap);
689 if (err) {
1a91de28 690 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 691 return err;
692 }
693
b91cb3eb
JM		 694 err = mlx4_QUERY_FW(dev);
695 if (err)
1a91de28 696 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 697
ab9c17a0
JM		 698 page_size = ~dev->caps.page_size_cap + 1;
699 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
700 if (page_size > PAGE_SIZE) {
1a91de28 701 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0
JM		 702 page_size, PAGE_SIZE);
703 return -ENODEV;
704 }
705
706 /* slave gets uar page size from QUERY_HCA fw command */
707 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
708
709 /* TODO: relax this assumption */
710 if (dev->caps.uar_page_size != PAGE_SIZE) {
711 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
712 dev->caps.uar_page_size, PAGE_SIZE);
713 return -ENODEV;
714 }
715
716 memset(&func_cap, 0, sizeof(func_cap));
47605df9 717 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 718 if (err) {
1a91de28
JP		 719 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
720 err);
ab9c17a0
JM		 721 return err;
722 }
723
724 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
725 PF_CONTEXT_BEHAVIOUR_MASK) {
726 mlx4_err(dev, "Unknown pf context behaviour\n");
727 return -ENOSYS;
728 }
729
ab9c17a0 730 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 731 dev->quotas.qp = func_cap.qp_quota;
732 dev->quotas.srq = func_cap.srq_quota;
733 dev->quotas.cq = func_cap.cq_quota;
734 dev->quotas.mpt = func_cap.mpt_quota;
735 dev->quotas.mtt = func_cap.mtt_quota;
736 dev->caps.num_qps = 1 << hca_param.log_num_qps;
737 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
738 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
739 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
740 dev->caps.num_eqs = func_cap.max_eq;
741 dev->caps.reserved_eqs = func_cap.reserved_eq;
ab9c17a0
JM		 742 dev->caps.num_pds = MLX4_NUM_PDS;
743 dev->caps.num_mgms = 0;
744 dev->caps.num_amgms = 0;
745
ab9c17a0 746 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 747 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
748 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 749 return -ENODEV;
750 }
751
99ec41d0 752 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
47605df9
JM		 753 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
754 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
755 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
756 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
757
758 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
99ec41d0
JM		 759 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
760 !dev->caps.qp0_qkey) {
47605df9
JM		 761 err = -ENOMEM;
762 goto err_mem;
763 }
764
6634961c 765 for (i = 1; i <= dev->caps.num_ports; ++i) {
225c6c8c 766 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
47605df9 767 if (err) {
1a91de28
JP		 768 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
769 i, err);
47605df9
JM		 770 goto err_mem;
771 }
99ec41d0 772 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
47605df9
JM		 773 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
774 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
775 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
776 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 777 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 778 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 779 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
780 &dev->caps.gid_table_len[i],
781 &dev->caps.pkey_table_len[i]))
47605df9 782 goto err_mem;
6634961c 783 }
6230bb23 784
ab9c17a0
JM		 785 if (dev->caps.uar_page_size * (dev->caps.num_uars -
786 dev->caps.reserved_uars) >
787 pci_resource_len(dev->pdev, 2)) {
1a91de28 788 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0
JM		 789 dev->caps.uar_page_size * dev->caps.num_uars,
790 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 791 goto err_mem;
ab9c17a0
JM		 792 }
793
08ff3235
OG		 794 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
795 dev->caps.eqe_size = 64;
796 dev->caps.eqe_factor = 1;
797 } else {
798 dev->caps.eqe_size = 32;
799 dev->caps.eqe_factor = 0;
800 }
801
802 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
803 dev->caps.cqe_size = 64;
77507aa2 804 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 805 } else {
806 dev->caps.cqe_size = 32;
807 }
808
77507aa2
IS		 809 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
810 dev->caps.eqe_size = hca_param.eqe_size;
811 dev->caps.eqe_factor = 0;
812 }
813
814 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
815 dev->caps.cqe_size = hca_param.cqe_size;
816 /* User still need to know when CQE > 32B */
817 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
818 }
819
f9bd2d7f 820 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 821 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 822
7b8157be
JM		 823 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
824
ddae0349
EE		 825 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
826 dev->caps.bf_reg_size)
827 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
828
ab9c17a0 829 return 0;
47605df9
JM		 830
831err_mem:
99ec41d0 832 kfree(dev->caps.qp0_qkey);
47605df9
JM		 833 kfree(dev->caps.qp0_tunnel);
834 kfree(dev->caps.qp0_proxy);
835 kfree(dev->caps.qp1_tunnel);
836 kfree(dev->caps.qp1_proxy);
99ec41d0
JM		 837 dev->caps.qp0_qkey = NULL;
838 dev->caps.qp0_tunnel = NULL;
839 dev->caps.qp0_proxy = NULL;
840 dev->caps.qp1_tunnel = NULL;
841 dev->caps.qp1_proxy = NULL;
47605df9
JM		 842
843 return err;
ab9c17a0 844}
225c7b1f 845
b046ffe5
EP		 846static void mlx4_request_modules(struct mlx4_dev *dev)
847{
848 int port;
849 int has_ib_port = false;
850 int has_eth_port = false;
851#define EN_DRV_NAME "mlx4_en"
852#define IB_DRV_NAME "mlx4_ib"
853
854 for (port = 1; port <= dev->caps.num_ports; port++) {
855 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
856 has_ib_port = true;
857 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
858 has_eth_port = true;
859 }
860
b046ffe5
EP		 861 if (has_eth_port)
862 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 863 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
864 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 865}
866
7ff93f8b
YP		 867/*
868 * Change the port configuration of the device.
869 * Every user of this function must hold the port mutex.
870 */
27bf91d6
YP		 871int mlx4_change_port_types(struct mlx4_dev *dev,
872 enum mlx4_port_type *port_types)
7ff93f8b
YP		 873{
874 int err = 0;
875 int change = 0;
876 int port;
877
878 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 879 /* Change the port type only if the new type is different
880 * from the current, and not set to Auto */
3d8f9308 881 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 882 change = 1;
7ff93f8b
YP		 883 }
884 if (change) {
885 mlx4_unregister_device(dev);
886 for (port = 1; port <= dev->caps.num_ports; port++) {
887 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 888 dev->caps.port_type[port] = port_types[port - 1];
6634961c 889 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 890 if (err) {
1a91de28
JP		 891 mlx4_err(dev, "Failed to set port %d, aborting\n",
892 port);
7ff93f8b
YP		 893 goto out;
894 }
895 }
896 mlx4_set_port_mask(dev);
897 err = mlx4_register_device(dev);
b046ffe5
EP		 898 if (err) {
899 mlx4_err(dev, "Failed to register device\n");
900 goto out;
901 }
902 mlx4_request_modules(dev);
7ff93f8b
YP		 903 }
904
905out:
906 return err;
907}
908
909static ssize_t show_port_type(struct device *dev,
910 struct device_attribute *attr,
911 char *buf)
912{
913 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
914 port_attr);
915 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 916 char type[8];
917
918 sprintf(type, "%s",
919 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
920 "ib" : "eth");
921 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
922 sprintf(buf, "auto (%s)\n", type);
923 else
924 sprintf(buf, "%s\n", type);
7ff93f8b 925
27bf91d6 926 return strlen(buf);
7ff93f8b
YP		 927}
928
929static ssize_t set_port_type(struct device *dev,
930 struct device_attribute *attr,
931 const char *buf, size_t count)
932{
933 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
934 port_attr);
935 struct mlx4_dev *mdev = info->dev;
936 struct mlx4_priv *priv = mlx4_priv(mdev);
937 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 938 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
0a984556 939 static DEFINE_MUTEX(set_port_type_mutex);
7ff93f8b
YP		 940 int i;
941 int err = 0;
942
0a984556
AV		 943 mutex_lock(&set_port_type_mutex);
944
7ff93f8b
YP		 945 if (!strcmp(buf, "ib\n"))
946 info->tmp_type = MLX4_PORT_TYPE_IB;
947 else if (!strcmp(buf, "eth\n"))
948 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 949 else if (!strcmp(buf, "auto\n"))
950 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 951 else {
952 mlx4_err(mdev, "%s is not supported port type\n", buf);
0a984556
AV		 953 err = -EINVAL;
954 goto err_out;
7ff93f8b
YP		 955 }
956
27bf91d6 957 mlx4_stop_sense(mdev);
7ff93f8b 958 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 959 /* Possible type is always the one that was delivered */
960 mdev->caps.possible_type[info->port] = info->tmp_type;
961
962 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 963 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 964 mdev->caps.possible_type[i+1];
965 if (types[i] == MLX4_PORT_TYPE_AUTO)
966 types[i] = mdev->caps.port_type[i+1];
967 }
7ff93f8b 968
58a60168
YP		 969 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
970 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 971 for (i = 1; i <= mdev->caps.num_ports; i++) {
972 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
973 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
974 err = -EINVAL;
975 }
976 }
977 }
978 if (err) {
1a91de28 979 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 980 goto out;
981 }
982
983 mlx4_do_sense_ports(mdev, new_types, types);
984
985 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 986 if (err)
987 goto out;
988
27bf91d6
YP		 989 /* We are about to apply the changes after the configuration
990 * was verified, no need to remember the temporary types
991 * any more */
992 for (i = 0; i < mdev->caps.num_ports; i++)
993 priv->port[i + 1].tmp_type = 0;
7ff93f8b 994
27bf91d6 995 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 996
997out:
27bf91d6 998 mlx4_start_sense(mdev);
7ff93f8b 999 mutex_unlock(&priv->port_mutex);
0a984556
AV		 1000err_out:
1001 mutex_unlock(&set_port_type_mutex);
1002
7ff93f8b
YP		 1003 return err ? err : count;
1004}
1005
096335b3
OG		 1006enum ibta_mtu {
1007 IB_MTU_256 = 1,
1008 IB_MTU_512 = 2,
1009 IB_MTU_1024 = 3,
1010 IB_MTU_2048 = 4,
1011 IB_MTU_4096 = 5
1012};
1013
1014static inline int int_to_ibta_mtu(int mtu)
1015{
1016 switch (mtu) {
1017 case 256: return IB_MTU_256;
1018 case 512: return IB_MTU_512;
1019 case 1024: return IB_MTU_1024;
1020 case 2048: return IB_MTU_2048;
1021 case 4096: return IB_MTU_4096;
1022 default: return -1;
1023 }
1024}
1025
1026static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1027{
1028 switch (mtu) {
1029 case IB_MTU_256: return 256;
1030 case IB_MTU_512: return 512;
1031 case IB_MTU_1024: return 1024;
1032 case IB_MTU_2048: return 2048;
1033 case IB_MTU_4096: return 4096;
1034 default: return -1;
1035 }
1036}
1037
1038static ssize_t show_port_ib_mtu(struct device *dev,
1039 struct device_attribute *attr,
1040 char *buf)
1041{
1042 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1043 port_mtu_attr);
1044 struct mlx4_dev *mdev = info->dev;
1045
1046 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1047 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1048
1049 sprintf(buf, "%d\n",
1050 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1051 return strlen(buf);
1052}
1053
1054static ssize_t set_port_ib_mtu(struct device *dev,
1055 struct device_attribute *attr,
1056 const char *buf, size_t count)
1057{
1058 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1059 port_mtu_attr);
1060 struct mlx4_dev *mdev = info->dev;
1061 struct mlx4_priv *priv = mlx4_priv(mdev);
1062 int err, port, mtu, ibta_mtu = -1;
1063
1064 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1065 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1066 return -EINVAL;
1067 }
1068
618fad95
DB		 1069 err = kstrtoint(buf, 0, &mtu);
1070 if (!err)
096335b3
OG		 1071 ibta_mtu = int_to_ibta_mtu(mtu);
1072
618fad95 1073 if (err || ibta_mtu < 0) {
096335b3
OG		 1074 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1075 return -EINVAL;
1076 }
1077
1078 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1079
1080 mlx4_stop_sense(mdev);
1081 mutex_lock(&priv->port_mutex);
1082 mlx4_unregister_device(mdev);
1083 for (port = 1; port <= mdev->caps.num_ports; port++) {
1084 mlx4_CLOSE_PORT(mdev, port);
6634961c 1085 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1086 if (err) {
1a91de28
JP		 1087 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1088 port);
096335b3
OG		 1089 goto err_set_port;
1090 }
1091 }
1092 err = mlx4_register_device(mdev);
1093err_set_port:
1094 mutex_unlock(&priv->port_mutex);
1095 mlx4_start_sense(mdev);
1096 return err ? err : count;
1097}
1098
e8f9b2ed 1099static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1100{
1101 struct mlx4_priv *priv = mlx4_priv(dev);
1102 int err;
1103
1104 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1105 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1106 if (!priv->fw.fw_icm) {
1a91de28 1107 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1108 return -ENOMEM;
1109 }
1110
1111 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1112 if (err) {
1a91de28 1113 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1114 goto err_free;
1115 }
1116
1117 err = mlx4_RUN_FW(dev);
1118 if (err) {
1a91de28 1119 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1120 goto err_unmap_fa;
1121 }
1122
1123 return 0;
1124
1125err_unmap_fa:
1126 mlx4_UNMAP_FA(dev);
1127
1128err_free:
5b0bf5e2 1129 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1130 return err;
1131}
1132
e8f9b2ed
RD		 1133static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1134 int cmpt_entry_sz)
225c7b1f
RD		 1135{
1136 struct mlx4_priv *priv = mlx4_priv(dev);
1137 int err;
ab9c17a0 1138 int num_eqs;
225c7b1f
RD		 1139
1140 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1141 cmpt_base +
1142 ((u64) (MLX4_CMPT_TYPE_QP *
1143 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1144 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1145 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1146 0, 0);
225c7b1f
RD		 1147 if (err)
1148 goto err;
1149
1150 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1151 cmpt_base +
1152 ((u64) (MLX4_CMPT_TYPE_SRQ *
1153 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1154 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1155 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1156 if (err)
1157 goto err_qp;
1158
1159 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1160 cmpt_base +
1161 ((u64) (MLX4_CMPT_TYPE_CQ *
1162 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1163 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1164 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1165 if (err)
1166 goto err_srq;
1167
7ae0e400 1168 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1169 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1170 cmpt_base +
1171 ((u64) (MLX4_CMPT_TYPE_EQ *
1172 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1173 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1174 if (err)
1175 goto err_cq;
1176
1177 return 0;
1178
1179err_cq:
1180 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1181
1182err_srq:
1183 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1184
1185err_qp:
1186 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1187
1188err:
1189 return err;
1190}
1191
3d73c288
RD		 1192static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1193 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1194{
1195 struct mlx4_priv *priv = mlx4_priv(dev);
1196 u64 aux_pages;
ab9c17a0 1197 int num_eqs;
225c7b1f
RD		 1198 int err;
1199
1200 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1201 if (err) {
1a91de28 1202 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1203 return err;
1204 }
1205
1a91de28 1206 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1207 (unsigned long long) icm_size >> 10,
1208 (unsigned long long) aux_pages << 2);
1209
1210 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1211 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1212 if (!priv->fw.aux_icm) {
1a91de28 1213 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1214 return -ENOMEM;
1215 }
1216
1217 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1218 if (err) {
1a91de28 1219 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1220 goto err_free_aux;
1221 }
1222
1223 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1224 if (err) {
1a91de28 1225 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1226 goto err_unmap_aux;
1227 }
1228
ab9c17a0 1229
7ae0e400 1230 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1231 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1232 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1233 num_eqs, num_eqs, 0, 0);
225c7b1f 1234 if (err) {
1a91de28 1235 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1236 goto err_unmap_cmpt;
1237 }
1238
d7bb58fb
JM		 1239 /*
1240 * Reserved MTT entries must be aligned up to a cacheline
1241 * boundary, since the FW will write to them, while the driver
1242 * writes to all other MTT entries. (The variable
1243 * dev->caps.mtt_entry_sz below is really the MTT segment
1244 * size, not the raw entry size)
1245 */
1246 dev->caps.reserved_mtts =
1247 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1248 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1249
225c7b1f
RD		 1250 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1251 init_hca->mtt_base,
1252 dev->caps.mtt_entry_sz,
2b8fb286 1253 dev->caps.num_mtts,
5b0bf5e2 1254 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1255 if (err) {
1a91de28 1256 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1257 goto err_unmap_eq;
1258 }
1259
1260 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1261 init_hca->dmpt_base,
1262 dev_cap->dmpt_entry_sz,
1263 dev->caps.num_mpts,
5b0bf5e2 1264 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1265 if (err) {
1a91de28 1266 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1267 goto err_unmap_mtt;
1268 }
1269
1270 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1271 init_hca->qpc_base,
1272 dev_cap->qpc_entry_sz,
1273 dev->caps.num_qps,
93fc9e1b
YP		 1274 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1275 0, 0);
225c7b1f 1276 if (err) {
1a91de28 1277 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1278 goto err_unmap_dmpt;
1279 }
1280
1281 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1282 init_hca->auxc_base,
1283 dev_cap->aux_entry_sz,
1284 dev->caps.num_qps,
93fc9e1b
YP		 1285 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1286 0, 0);
225c7b1f 1287 if (err) {
1a91de28 1288 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1289 goto err_unmap_qp;
1290 }
1291
1292 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1293 init_hca->altc_base,
1294 dev_cap->altc_entry_sz,
1295 dev->caps.num_qps,
93fc9e1b
YP		 1296 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1297 0, 0);
225c7b1f 1298 if (err) {
1a91de28 1299 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1300 goto err_unmap_auxc;
1301 }
1302
1303 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1304 init_hca->rdmarc_base,
1305 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1306 dev->caps.num_qps,
93fc9e1b
YP		 1307 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1308 0, 0);
225c7b1f
RD		 1309 if (err) {
1310 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1311 goto err_unmap_altc;
1312 }
1313
1314 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1315 init_hca->cqc_base,
1316 dev_cap->cqc_entry_sz,
1317 dev->caps.num_cqs,
5b0bf5e2 1318 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1319 if (err) {
1a91de28 1320 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1321 goto err_unmap_rdmarc;
1322 }
1323
1324 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1325 init_hca->srqc_base,
1326 dev_cap->srq_entry_sz,
1327 dev->caps.num_srqs,
5b0bf5e2 1328 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1329 if (err) {
1a91de28 1330 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1331 goto err_unmap_cq;
1332 }
1333
1334 /*
0ff1fb65
HHZ		 1335 * For flow steering device managed mode it is required to use
1336 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1337 * required, but for simplicity just map the whole multicast
1338 * group table now. The table isn't very big and it's a lot
1339 * easier than trying to track ref counts.
225c7b1f
RD		 1340 */
1341 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1342 init_hca->mc_base,
1343 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1344 dev->caps.num_mgms + dev->caps.num_amgms,
1345 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1346 0, 0);
225c7b1f 1347 if (err) {
1a91de28 1348 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1349 goto err_unmap_srq;
1350 }
1351
1352 return 0;
1353
1354err_unmap_srq:
1355 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1356
1357err_unmap_cq:
1358 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1359
1360err_unmap_rdmarc:
1361 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1362
1363err_unmap_altc:
1364 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1365
1366err_unmap_auxc:
1367 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1368
1369err_unmap_qp:
1370 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1371
1372err_unmap_dmpt:
1373 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1374
1375err_unmap_mtt:
1376 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1377
1378err_unmap_eq:
fa0681d2 1379 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1380
1381err_unmap_cmpt:
1382 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1383 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1384 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1385 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1386
1387err_unmap_aux:
1388 mlx4_UNMAP_ICM_AUX(dev);
1389
1390err_free_aux:
5b0bf5e2 1391 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1392
1393 return err;
1394}
1395
1396static void mlx4_free_icms(struct mlx4_dev *dev)
1397{
1398 struct mlx4_priv *priv = mlx4_priv(dev);
1399
1400 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1401 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1402 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1403 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1404 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1405 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1406 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1407 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1408 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1409 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1410 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1411 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1412 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1413 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1414
1415 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1416 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1417}
1418
ab9c17a0
JM		 1419static void mlx4_slave_exit(struct mlx4_dev *dev)
1420{
1421 struct mlx4_priv *priv = mlx4_priv(dev);
1422
f3d4c89e 1423 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1424 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1a91de28 1425 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1426 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1427}
1428
c1b43dca
EC		 1429static int map_bf_area(struct mlx4_dev *dev)
1430{
1431 struct mlx4_priv *priv = mlx4_priv(dev);
1432 resource_size_t bf_start;
1433 resource_size_t bf_len;
1434 int err = 0;
1435
3d747473
JM		 1436 if (!dev->caps.bf_reg_size)
1437 return -ENXIO;
1438
ab9c17a0
JM		 1439 bf_start = pci_resource_start(dev->pdev, 2) +
1440 (dev->caps.num_uars << PAGE_SHIFT);
1441 bf_len = pci_resource_len(dev->pdev, 2) -
1442 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1443 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1444 if (!priv->bf_mapping)
1445 err = -ENOMEM;
1446
1447 return err;
1448}
1449
1450static void unmap_bf_area(struct mlx4_dev *dev)
1451{
1452 if (mlx4_priv(dev)->bf_mapping)
1453 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1454}
1455
ec693d47
AV		 1456cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1457{
1458 u32 clockhi, clocklo, clockhi1;
1459 cycle_t cycles;
1460 int i;
1461 struct mlx4_priv *priv = mlx4_priv(dev);
1462
1463 for (i = 0; i < 10; i++) {
1464 clockhi = swab32(readl(priv->clock_mapping));
1465 clocklo = swab32(readl(priv->clock_mapping + 4));
1466 clockhi1 = swab32(readl(priv->clock_mapping));
1467 if (clockhi == clockhi1)
1468 break;
1469 }
1470
1471 cycles = (u64) clockhi << 32 | (u64) clocklo;
1472
1473 return cycles;
1474}
1475EXPORT_SYMBOL_GPL(mlx4_read_clock);
1476
1477
ddd8a6c1
EE		 1478static int map_internal_clock(struct mlx4_dev *dev)
1479{
1480 struct mlx4_priv *priv = mlx4_priv(dev);
1481
1482 priv->clock_mapping =
1483 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1484 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1485
1486 if (!priv->clock_mapping)
1487 return -ENOMEM;
1488
1489 return 0;
1490}
1491
1492static void unmap_internal_clock(struct mlx4_dev *dev)
1493{
1494 struct mlx4_priv *priv = mlx4_priv(dev);
1495
1496 if (priv->clock_mapping)
1497 iounmap(priv->clock_mapping);
1498}
1499
225c7b1f
RD		 1500static void mlx4_close_hca(struct mlx4_dev *dev)
1501{
ddd8a6c1 1502 unmap_internal_clock(dev);
c1b43dca 1503 unmap_bf_area(dev);
ab9c17a0
JM		 1504 if (mlx4_is_slave(dev))
1505 mlx4_slave_exit(dev);
1506 else {
1507 mlx4_CLOSE_HCA(dev, 0);
1508 mlx4_free_icms(dev);
a0eacca9
MB		 1509 }
1510}
1511
1512static void mlx4_close_fw(struct mlx4_dev *dev)
1513{
1514 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1515 mlx4_UNMAP_FA(dev);
1516 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1517 }
1518}
1519
1520static int mlx4_init_slave(struct mlx4_dev *dev)
1521{
1522 struct mlx4_priv *priv = mlx4_priv(dev);
1523 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1524 int ret_from_reset = 0;
1525 u32 slave_read;
1526 u32 cmd_channel_ver;
1527
97989356 1528 if (atomic_read(&pf_loading)) {
1a91de28 1529 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 1530 return -EPROBE_DEFER;
1531 }
1532
f3d4c89e 1533 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1534 priv->cmd.max_cmds = 1;
1535 mlx4_warn(dev, "Sending reset\n");
1536 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1537 MLX4_COMM_TIME);
1538 /* if we are in the middle of flr the slave will try
1539 * NUM_OF_RESET_RETRIES times before leaving.*/
1540 if (ret_from_reset) {
1541 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 1542 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 1543 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1544 return -EPROBE_DEFER;
ab9c17a0
JM		 1545 } else
1546 goto err;
1547 }
1548
1549 /* check the driver version - the slave I/F revision
1550 * must match the master's */
1551 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1552 cmd_channel_ver = mlx4_comm_get_version();
1553
1554 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1555 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 1556 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 1557 goto err;
1558 }
1559
1560 mlx4_warn(dev, "Sending vhcr0\n");
1561 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1562 MLX4_COMM_TIME))
1563 goto err;
1564 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1565 MLX4_COMM_TIME))
1566 goto err;
1567 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1568 MLX4_COMM_TIME))
1569 goto err;
1570 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1571 goto err;
f3d4c89e
RD		 1572
1573 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1574 return 0;
1575
1576err:
1577 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1578 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1579 return -EIO;
225c7b1f
RD		 1580}
1581
6634961c
JM		 1582static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1583{
1584 int i;
1585
1586 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1587 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1588 dev->caps.gid_table_len[i] =
449fc488 1589 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1590 else
1591 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1592 dev->caps.pkey_table_len[i] =
1593 dev->phys_caps.pkey_phys_table_len[i] - 1;
1594 }
1595}
1596
3c439b55
JM		 1597static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1598{
1599 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1600
1601 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1602 i++) {
1603 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1604 break;
1605 }
1606
1607 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1608}
1609
7b8157be
JM		 1610static void choose_steering_mode(struct mlx4_dev *dev,
1611 struct mlx4_dev_cap *dev_cap)
1612{
3c439b55
JM		 1613 if (mlx4_log_num_mgm_entry_size == -1 &&
1614 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1615 (!mlx4_is_mfunc(dev) ||
449fc488 1616 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) &&
3c439b55
JM		 1617 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1618 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1619 dev->oper_log_mgm_entry_size =
1620 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1621 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1622 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1623 dev->caps.fs_log_max_ucast_qp_range_size =
1624 dev_cap->fs_log_max_ucast_qp_range_size;
1625 } else {
1626 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1627 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1628 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1629 else {
1630 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1631
1632 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1633 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 1634 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 1635 }
3c439b55
JM		 1636 dev->oper_log_mgm_entry_size =
1637 mlx4_log_num_mgm_entry_size > 0 ?
1638 mlx4_log_num_mgm_entry_size :
1639 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1640 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1641 }
1a91de28 1642 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 1643 mlx4_steering_mode_str(dev->caps.steering_mode),
1644 dev->oper_log_mgm_entry_size,
1645 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1646}
1647
7ffdf726
OG		 1648static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1649 struct mlx4_dev_cap *dev_cap)
1650{
1651 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1652 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1653 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1654 else
1655 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1656
1657 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1658 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1659}
1660
a0eacca9 1661static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 1662{
2d928651 1663 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 1664 int err = 0;
225c7b1f 1665
ab9c17a0
JM		 1666 if (!mlx4_is_slave(dev)) {
1667 err = mlx4_QUERY_FW(dev);
1668 if (err) {
1669 if (err == -EACCES)
1a91de28 1670 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 1671 else
1a91de28 1672 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 1673 return err;
ab9c17a0 1674 }
225c7b1f 1675
ab9c17a0
JM		 1676 err = mlx4_load_fw(dev);
1677 if (err) {
1a91de28 1678 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 1679 return err;
ab9c17a0 1680 }
225c7b1f 1681
ab9c17a0
JM		 1682 mlx4_cfg.log_pg_sz_m = 1;
1683 mlx4_cfg.log_pg_sz = 0;
1684 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1685 if (err)
1686 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 1687 }
2d928651 1688
a0eacca9
MB		 1689 return err;
1690}
1691
1692static int mlx4_init_hca(struct mlx4_dev *dev)
1693{
1694 struct mlx4_priv *priv = mlx4_priv(dev);
1695 struct mlx4_adapter adapter;
1696 struct mlx4_dev_cap dev_cap;
1697 struct mlx4_profile profile;
1698 struct mlx4_init_hca_param init_hca;
1699 u64 icm_size;
1700 struct mlx4_config_dev_params params;
1701 int err;
1702
1703 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1704 err = mlx4_dev_cap(dev, &dev_cap);
1705 if (err) {
1a91de28 1706 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 1707 goto err_stop_fw;
1708 }
225c7b1f 1709
7b8157be 1710 choose_steering_mode(dev, &dev_cap);
7ffdf726 1711 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1712
8e1a28e8
HHZ		 1713 err = mlx4_get_phys_port_id(dev);
1714 if (err)
1715 mlx4_err(dev, "Fail to get physical port id\n");
1716
6634961c
JM		 1717 if (mlx4_is_master(dev))
1718 mlx4_parav_master_pf_caps(dev);
1719
2599d858
AV		 1720 if (mlx4_low_memory_profile()) {
1721 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
1722 profile = low_mem_profile;
1723 } else {
1724 profile = default_profile;
1725 }
0ff1fb65
HHZ		 1726 if (dev->caps.steering_mode ==
1727 MLX4_STEERING_MODE_DEVICE_MANAGED)
1728 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1729
ab9c17a0
JM		 1730 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1731 &init_hca);
1732 if ((long long) icm_size < 0) {
1733 err = icm_size;
1734 goto err_stop_fw;
1735 }
225c7b1f 1736
a5bbe892
EC		 1737 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1738
ab9c17a0
JM		 1739 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1740 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1741 init_hca.mw_enabled = 0;
1742 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1743 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1744 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1745
ab9c17a0
JM		 1746 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1747 if (err)
1748 goto err_stop_fw;
225c7b1f 1749
ab9c17a0
JM		 1750 err = mlx4_INIT_HCA(dev, &init_hca);
1751 if (err) {
1a91de28 1752 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 1753 goto err_free_icm;
1754 }
7ae0e400
MB		 1755
1756 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
1757 err = mlx4_query_func(dev, &dev_cap);
1758 if (err < 0) {
1759 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
1760 goto err_stop_fw;
1761 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
1762 dev->caps.num_eqs = dev_cap.max_eqs;
1763 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
1764 dev->caps.reserved_uars = dev_cap.reserved_uars;
1765 }
1766 }
1767
ddd8a6c1
EE		 1768 /*
1769 * If TS is supported by FW
1770 * read HCA frequency by QUERY_HCA command
1771 */
1772 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1773 memset(&init_hca, 0, sizeof(init_hca));
1774 err = mlx4_QUERY_HCA(dev, &init_hca);
1775 if (err) {
1a91de28 1776 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 1777 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1778 } else {
1779 dev->caps.hca_core_clock =
1780 init_hca.hca_core_clock;
1781 }
1782
1783 /* In case we got HCA frequency 0 - disable timestamping
1784 * to avoid dividing by zero
1785 */
1786 if (!dev->caps.hca_core_clock) {
1787 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1788 mlx4_err(dev,
1a91de28 1789 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 1790 } else if (map_internal_clock(dev)) {
1791 /*
1792 * Map internal clock,
1793 * in case of failure disable timestamping
1794 */
1795 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1796 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 1797 }
1798 }
ab9c17a0
JM		 1799 } else {
1800 err = mlx4_init_slave(dev);
1801 if (err) {
5efe5355
JM		 1802 if (err != -EPROBE_DEFER)
1803 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1804 return err;
ab9c17a0 1805 }
225c7b1f 1806
ab9c17a0
JM		 1807 err = mlx4_slave_cap(dev);
1808 if (err) {
1809 mlx4_err(dev, "Failed to obtain slave caps\n");
1810 goto err_close;
1811 }
225c7b1f
RD		 1812 }
1813
ab9c17a0
JM		 1814 if (map_bf_area(dev))
1815 mlx4_dbg(dev, "Failed to map blue flame area\n");
1816
1817 /*Only the master set the ports, all the rest got it from it.*/
1818 if (!mlx4_is_slave(dev))
1819 mlx4_set_port_mask(dev);
1820
225c7b1f
RD		 1821 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1822 if (err) {
1a91de28 1823 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 1824 goto unmap_bf;
225c7b1f
RD		 1825 }
1826
f8c6455b
SM		 1827 /* Query CONFIG_DEV parameters */
1828 err = mlx4_config_dev_retrieval(dev, &params);
1829 if (err && err != -ENOTSUPP) {
1830 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
1831 } else if (!err) {
1832 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
1833 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
1834 }
225c7b1f 1835 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1836 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1837
1838 return 0;
1839
bef772eb 1840unmap_bf:
ddd8a6c1 1841 unmap_internal_clock(dev);
bef772eb
AY		 1842 unmap_bf_area(dev);
1843
b38f2879 1844 if (mlx4_is_slave(dev)) {
99ec41d0 1845 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 1846 kfree(dev->caps.qp0_tunnel);
1847 kfree(dev->caps.qp0_proxy);
1848 kfree(dev->caps.qp1_tunnel);
1849 kfree(dev->caps.qp1_proxy);
1850 }
1851
225c7b1f 1852err_close:
41929ed2
DB		 1853 if (mlx4_is_slave(dev))
1854 mlx4_slave_exit(dev);
1855 else
1856 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 1857
1858err_free_icm:
ab9c17a0
JM		 1859 if (!mlx4_is_slave(dev))
1860 mlx4_free_icms(dev);
225c7b1f
RD		 1861
1862err_stop_fw:
ab9c17a0
JM		 1863 if (!mlx4_is_slave(dev)) {
1864 mlx4_UNMAP_FA(dev);
1865 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1866 }
225c7b1f
RD		 1867 return err;
1868}
1869
f2a3f6a3
OG		 1870static int mlx4_init_counters_table(struct mlx4_dev *dev)
1871{
1872 struct mlx4_priv *priv = mlx4_priv(dev);
1873 int nent;
1874
1875 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1876 return -ENOENT;
1877
1878 nent = dev->caps.max_counters;
1879 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1880}
1881
1882static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1883{
1884 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1885}
1886
ba062d52 1887int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1888{
1889 struct mlx4_priv *priv = mlx4_priv(dev);
1890
1891 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1892 return -ENOENT;
1893
1894 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1895 if (*idx == -1)
1896 return -ENOMEM;
1897
1898 return 0;
1899}
ba062d52
JM		 1900
1901int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1902{
1903 u64 out_param;
1904 int err;
1905
1906 if (mlx4_is_mfunc(dev)) {
1907 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1908 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1909 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1910 if (!err)
1911 *idx = get_param_l(&out_param);
1912
1913 return err;
1914 }
1915 return __mlx4_counter_alloc(dev, idx);
1916}
f2a3f6a3
OG		 1917EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1918
ba062d52 1919void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 1920{
7c6d74d2 1921 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 1922 return;
1923}
ba062d52
JM		 1924
1925void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1926{
e7dbeba8 1927 u64 in_param = 0;
ba062d52
JM		 1928
1929 if (mlx4_is_mfunc(dev)) {
1930 set_param_l(&in_param, idx);
1931 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1932 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1933 MLX4_CMD_WRAPPED);
1934 return;
1935 }
1936 __mlx4_counter_free(dev, idx);
1937}
f2a3f6a3
OG		 1938EXPORT_SYMBOL_GPL(mlx4_counter_free);
1939
3d73c288 1940static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1941{
1942 struct mlx4_priv *priv = mlx4_priv(dev);
1943 int err;
7ff93f8b 1944 int port;
9a5aa622 1945 __be32 ib_port_default_caps;
225c7b1f 1946
225c7b1f
RD		 1947 err = mlx4_init_uar_table(dev);
1948 if (err) {
1a91de28
JP		 1949 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
1950 return err;
225c7b1f
RD		 1951 }
1952
1953 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1954 if (err) {
1a91de28 1955 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 1956 goto err_uar_table_free;
1957 }
1958
4979d18f 1959 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 1960 if (!priv->kar) {
1a91de28 1961 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 1962 err = -ENOMEM;
1963 goto err_uar_free;
1964 }
1965
1966 err = mlx4_init_pd_table(dev);
1967 if (err) {
1a91de28 1968 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 1969 goto err_kar_unmap;
1970 }
1971
012a8ff5
SH		 1972 err = mlx4_init_xrcd_table(dev);
1973 if (err) {
1a91de28 1974 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 1975 goto err_pd_table_free;
1976 }
1977
225c7b1f
RD		 1978 err = mlx4_init_mr_table(dev);
1979 if (err) {
1a91de28 1980 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 1981 goto err_xrcd_table_free;
225c7b1f
RD		 1982 }
1983
fe6f700d
YP		 1984 if (!mlx4_is_slave(dev)) {
1985 err = mlx4_init_mcg_table(dev);
1986 if (err) {
1a91de28 1987 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 1988 goto err_mr_table_free;
1989 }
114840c3
JM		 1990 err = mlx4_config_mad_demux(dev);
1991 if (err) {
1992 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
1993 goto err_mcg_table_free;
1994 }
fe6f700d
YP		 1995 }
1996
225c7b1f
RD		 1997 err = mlx4_init_eq_table(dev);
1998 if (err) {
1a91de28 1999 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2000 goto err_mcg_table_free;
225c7b1f
RD		 2001 }
2002
2003 err = mlx4_cmd_use_events(dev);
2004 if (err) {
1a91de28 2005 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2006 goto err_eq_table_free;
2007 }
2008
2009 err = mlx4_NOP(dev);
2010 if (err) {
08fb1055 2011 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2012 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
b8dd786f 2013 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1a91de28 2014 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2015 } else {
1a91de28 2016 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
b8dd786f 2017 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 2018 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2019 }
225c7b1f
RD		 2020
2021 goto err_cmd_poll;
2022 }
2023
2024 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2025
2026 err = mlx4_init_cq_table(dev);
2027 if (err) {
1a91de28 2028 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2029 goto err_cmd_poll;
2030 }
2031
2032 err = mlx4_init_srq_table(dev);
2033 if (err) {
1a91de28 2034 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2035 goto err_cq_table_free;
2036 }
2037
2038 err = mlx4_init_qp_table(dev);
2039 if (err) {
1a91de28 2040 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2041 goto err_srq_table_free;
2042 }
2043
f2a3f6a3
OG		 2044 err = mlx4_init_counters_table(dev);
2045 if (err && err != -ENOENT) {
1a91de28 2046 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
fe6f700d 2047 goto err_qp_table_free;
f2a3f6a3
OG		 2048 }
2049
ab9c17a0
JM		 2050 if (!mlx4_is_slave(dev)) {
2051 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2052 ib_port_default_caps = 0;
2053 err = mlx4_get_port_ib_caps(dev, port,
2054 &ib_port_default_caps);
2055 if (err)
1a91de28
JP		 2056 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2057 port, err);
ab9c17a0
JM		 2058 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2059
2aca1172
JM		 2060 /* initialize per-slave default ib port capabilities */
2061 if (mlx4_is_master(dev)) {
2062 int i;
2063 for (i = 0; i < dev->num_slaves; i++) {
2064 if (i == mlx4_master_func_num(dev))
2065 continue;
2066 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2067 ib_port_default_caps;
2aca1172
JM		 2068 }
2069 }
2070
096335b3
OG		 2071 if (mlx4_is_mfunc(dev))
2072 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2073 else
2074 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2075
6634961c
JM		 2076 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2077 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2078 if (err) {
2079 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2080 port);
ab9c17a0
JM		 2081 goto err_counters_table_free;
2082 }
7ff93f8b
YP		 2083 }
2084 }
2085
225c7b1f
RD		 2086 return 0;
2087
f2a3f6a3
OG		 2088err_counters_table_free:
2089 mlx4_cleanup_counters_table(dev);
2090
225c7b1f
RD		 2091err_qp_table_free:
2092 mlx4_cleanup_qp_table(dev);
2093
2094err_srq_table_free:
2095 mlx4_cleanup_srq_table(dev);
2096
2097err_cq_table_free:
2098 mlx4_cleanup_cq_table(dev);
2099
2100err_cmd_poll:
2101 mlx4_cmd_use_polling(dev);
2102
2103err_eq_table_free:
2104 mlx4_cleanup_eq_table(dev);
2105
fe6f700d
YP		 2106err_mcg_table_free:
2107 if (!mlx4_is_slave(dev))
2108 mlx4_cleanup_mcg_table(dev);
2109
ee49bd93 2110err_mr_table_free:
225c7b1f
RD		 2111 mlx4_cleanup_mr_table(dev);
2112
012a8ff5
SH		 2113err_xrcd_table_free:
2114 mlx4_cleanup_xrcd_table(dev);
2115
225c7b1f
RD		 2116err_pd_table_free:
2117 mlx4_cleanup_pd_table(dev);
2118
2119err_kar_unmap:
2120 iounmap(priv->kar);
2121
2122err_uar_free:
2123 mlx4_uar_free(dev, &priv->driver_uar);
2124
2125err_uar_table_free:
2126 mlx4_cleanup_uar_table(dev);
2127 return err;
2128}
2129
e8f9b2ed 2130static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2131{
2132 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2133 struct msix_entry *entries;
225c7b1f
RD		 2134 int i;
2135
2136 if (msi_x) {
7ae0e400
MB		 2137 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ;
2138
ca4c7b35
OG		 2139 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2140 nreq);
ab9c17a0 2141
b8dd786f
YP		 2142 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2143 if (!entries)
2144 goto no_msi;
2145
2146 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2147 entries[i].entry = i;
2148
66e2f9c1
AG		 2149 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
2150
2151 if (nreq < 0) {
5bf0da7d 2152 kfree(entries);
225c7b1f 2153 goto no_msi;
66e2f9c1 2154 } else if (nreq < MSIX_LEGACY_SZ +
1a91de28 2155 dev->caps.num_ports * MIN_MSIX_P_PORT) {
0b7ca5a9
YP		 2156 /*Working in legacy mode , all EQ's shared*/
2157 dev->caps.comp_pool = 0;
2158 dev->caps.num_comp_vectors = nreq - 1;
2159 } else {
2160 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2161 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2162 }
b8dd786f 2163 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2164 priv->eq_table.eq[i].irq = entries[i].vector;
2165
2166 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2167
2168 kfree(entries);
225c7b1f
RD		 2169 return;
2170 }
2171
2172no_msi:
b8dd786f 2173 dev->caps.num_comp_vectors = 1;
0b7ca5a9 2174 dev->caps.comp_pool = 0;
b8dd786f
YP		 2175
2176 for (i = 0; i < 2; ++i)
225c7b1f
RD		 2177 priv->eq_table.eq[i].irq = dev->pdev->irq;
2178}
2179
7ff93f8b 2180static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2181{
2182 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2183 int err = 0;
2a2336f8
YP		 2184
2185 info->dev = dev;
2186 info->port = port;
ab9c17a0 2187 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2188 mlx4_init_mac_table(dev, &info->mac_table);
2189 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2190 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2191 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2192 }
7ff93f8b
YP		 2193
2194 sprintf(info->dev_name, "mlx4_port%d", port);
2195 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2196 if (mlx4_is_mfunc(dev))
2197 info->port_attr.attr.mode = S_IRUGO;
2198 else {
2199 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2200 info->port_attr.store = set_port_type;
2201 }
7ff93f8b 2202 info->port_attr.show = show_port_type;
3691c964 2203 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 2204
2205 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2206 if (err) {
2207 mlx4_err(dev, "Failed to create file for port %d\n", port);
2208 info->port = -1;
2209 }
2210
096335b3
OG		 2211 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2212 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2213 if (mlx4_is_mfunc(dev))
2214 info->port_mtu_attr.attr.mode = S_IRUGO;
2215 else {
2216 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2217 info->port_mtu_attr.store = set_port_ib_mtu;
2218 }
2219 info->port_mtu_attr.show = show_port_ib_mtu;
2220 sysfs_attr_init(&info->port_mtu_attr.attr);
2221
2222 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2223 if (err) {
2224 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2225 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2226 info->port = -1;
2227 }
2228
7ff93f8b
YP		 2229 return err;
2230}
2231
2232static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2233{
2234 if (info->port < 0)
2235 return;
2236
2237 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 2238 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 2239}
2240
b12d93d6
YP		 2241static int mlx4_init_steering(struct mlx4_dev *dev)
2242{
2243 struct mlx4_priv *priv = mlx4_priv(dev);
2244 int num_entries = dev->caps.num_ports;
2245 int i, j;
2246
2247 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2248 if (!priv->steer)
2249 return -ENOMEM;
2250
45b51365 2251 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2252 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2253 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2254 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2255 }
b12d93d6
YP		 2256 return 0;
2257}
2258
2259static void mlx4_clear_steering(struct mlx4_dev *dev)
2260{
2261 struct mlx4_priv *priv = mlx4_priv(dev);
2262 struct mlx4_steer_index *entry, *tmp_entry;
2263 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2264 int num_entries = dev->caps.num_ports;
2265 int i, j;
2266
2267 for (i = 0; i < num_entries; i++) {
2268 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2269 list_for_each_entry_safe(pqp, tmp_pqp,
2270 &priv->steer[i].promisc_qps[j],
2271 list) {
2272 list_del(&pqp->list);
2273 kfree(pqp);
2274 }
2275 list_for_each_entry_safe(entry, tmp_entry,
2276 &priv->steer[i].steer_entries[j],
2277 list) {
2278 list_del(&entry->list);
2279 list_for_each_entry_safe(pqp, tmp_pqp,
2280 &entry->duplicates,
2281 list) {
2282 list_del(&pqp->list);
2283 kfree(pqp);
2284 }
2285 kfree(entry);
2286 }
2287 }
2288 }
2289 kfree(priv->steer);
2290}
2291
ab9c17a0
JM		 2292static int extended_func_num(struct pci_dev *pdev)
2293{
2294 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2295}
2296
2297#define MLX4_OWNER_BASE 0x8069c
2298#define MLX4_OWNER_SIZE 4
2299
2300static int mlx4_get_ownership(struct mlx4_dev *dev)
2301{
2302 void __iomem *owner;
2303 u32 ret;
2304
57dbf29a
KSS		 2305 if (pci_channel_offline(dev->pdev))
2306 return -EIO;
2307
ab9c17a0
JM		 2308 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2309 MLX4_OWNER_SIZE);
2310 if (!owner) {
2311 mlx4_err(dev, "Failed to obtain ownership bit\n");
2312 return -ENOMEM;
2313 }
2314
2315 ret = readl(owner);
2316 iounmap(owner);
2317 return (int) !!ret;
2318}
2319
2320static void mlx4_free_ownership(struct mlx4_dev *dev)
2321{
2322 void __iomem *owner;
2323
57dbf29a
KSS		 2324 if (pci_channel_offline(dev->pdev))
2325 return;
2326
ab9c17a0
JM		 2327 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2328 MLX4_OWNER_SIZE);
2329 if (!owner) {
2330 mlx4_err(dev, "Failed to obtain ownership bit\n");
2331 return;
2332 }
2333 writel(0, owner);
2334 msleep(1000);
2335 iounmap(owner);
2336}
2337
a0eacca9
MB		 2338#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2339 !!((flags) & MLX4_FLAG_MASTER))
2340
2341static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
2342 u8 total_vfs, int existing_vfs)
2343{
2344 u64 dev_flags = dev->flags;
2345
2346 dev->dev_vfs = kzalloc(
2347 total_vfs * sizeof(*dev->dev_vfs),
2348 GFP_KERNEL);
2349 if (NULL == dev->dev_vfs) {
2350 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2351 goto disable_sriov;
2352 } else if (!(dev->flags & MLX4_FLAG_SRIOV)) {
2353 int err = 0;
2354
2355 atomic_inc(&pf_loading);
2356 if (existing_vfs) {
2357 if (existing_vfs != total_vfs)
2358 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2359 existing_vfs, total_vfs);
2360 } else {
2361 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2362 err = pci_enable_sriov(pdev, total_vfs);
2363 }
2364 if (err) {
2365 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2366 err);
2367 atomic_dec(&pf_loading);
2368 goto disable_sriov;
2369 } else {
2370 mlx4_warn(dev, "Running in master mode\n");
2371 dev_flags |= MLX4_FLAG_SRIOV |
2372 MLX4_FLAG_MASTER;
2373 dev_flags &= ~MLX4_FLAG_SLAVE;
2374 dev->num_vfs = total_vfs;
2375 }
2376 }
2377 return dev_flags;
2378
2379disable_sriov:
2380 dev->num_vfs = 0;
2381 kfree(dev->dev_vfs);
2382 return dev_flags & ~MLX4_FLAG_MASTER;
2383}
2384
de966c59
MB		 2385enum {
2386 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2387};
2388
2389static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
2390 int *nvfs)
2391{
2392 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
2393 /* Checking for 64 VFs as a limitation of CX2 */
2394 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
2395 requested_vfs >= 64) {
2396 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
2397 requested_vfs);
2398 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
2399 }
2400 return 0;
2401}
2402
e1c00e10
MD		 2403static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
2404 int total_vfs, int *nvfs, struct mlx4_priv *priv)
225c7b1f 2405{
225c7b1f 2406 struct mlx4_dev *dev;
e1c00e10 2407 unsigned sum = 0;
225c7b1f 2408 int err;
2a2336f8 2409 int port;
e1c00e10 2410 int i;
7ae0e400 2411 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 2412 int existing_vfs = 0;
225c7b1f 2413
e1c00e10 2414 dev = &priv->dev;
225c7b1f 2415
b581401e
RD		 2416 INIT_LIST_HEAD(&priv->ctx_list);
2417 spin_lock_init(&priv->ctx_lock);
225c7b1f 2418
7ff93f8b
YP		 2419 mutex_init(&priv->port_mutex);
2420
6296883c
YP		 2421 INIT_LIST_HEAD(&priv->pgdir_list);
2422 mutex_init(&priv->pgdir_mutex);
2423
c1b43dca
EC		 2424 INIT_LIST_HEAD(&priv->bf_list);
2425 mutex_init(&priv->bf_mutex);
2426
aca7a3ac 2427 dev->rev_id = pdev->revision;
6e7136ed 2428 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 2429
ab9c17a0 2430 /* Detect if this device is a virtual function */
839f1243 2431 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2432 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2433 dev->flags |= MLX4_FLAG_SLAVE;
2434 } else {
2435 /* We reset the device and enable SRIOV only for physical
2436 * devices. Try to claim ownership on the device;
2437 * if already taken, skip -- do not allow multiple PFs */
2438 err = mlx4_get_ownership(dev);
2439 if (err) {
2440 if (err < 0)
e1c00e10 2441 return err;
ab9c17a0 2442 else {
1a91de28 2443 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 2444 return -EINVAL;
ab9c17a0
JM		 2445 }
2446 }
aca7a3ac 2447
fe6f700d
YP		 2448 atomic_set(&priv->opreq_count, 0);
2449 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2450
ab9c17a0
JM		 2451 /*
2452 * Now reset the HCA before we touch the PCI capabilities or
2453 * attempt a firmware command, since a boot ROM may have left
2454 * the HCA in an undefined state.
2455 */
2456 err = mlx4_reset(dev);
2457 if (err) {
1a91de28 2458 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 2459 goto err_sriov;
ab9c17a0 2460 }
7ae0e400
MB		 2461
2462 if (total_vfs) {
2463 existing_vfs = pci_num_vf(pdev);
2464 dev->flags = MLX4_FLAG_MASTER;
2465 dev->num_vfs = total_vfs;
2466 }
225c7b1f
RD		 2467 }
2468
ab9c17a0 2469slave_start:
521130d1
EE		 2470 err = mlx4_cmd_init(dev);
2471 if (err) {
1a91de28 2472 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 2473 goto err_sriov;
2474 }
2475
2476 /* In slave functions, the communication channel must be initialized
2477 * before posting commands. Also, init num_slaves before calling
2478 * mlx4_init_hca */
2479 if (mlx4_is_mfunc(dev)) {
7ae0e400 2480 if (mlx4_is_master(dev)) {
ab9c17a0 2481 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 2482
2483 } else {
ab9c17a0 2484 dev->num_slaves = 0;
f356fcbe
JM		 2485 err = mlx4_multi_func_init(dev);
2486 if (err) {
1a91de28 2487 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 2488 goto err_cmd;
2489 }
2490 }
225c7b1f
RD		 2491 }
2492
a0eacca9
MB		 2493 err = mlx4_init_fw(dev);
2494 if (err) {
2495 mlx4_err(dev, "Failed to init fw, aborting.\n");
2496 goto err_mfunc;
2497 }
2498
7ae0e400
MB		 2499 if (mlx4_is_master(dev)) {
2500 if (!dev_cap) {
2501 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
2502
2503 if (!dev_cap) {
2504 err = -ENOMEM;
2505 goto err_fw;
2506 }
2507
2508 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2509 if (err) {
2510 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2511 goto err_fw;
2512 }
2513
de966c59
MB		 2514 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2515 goto err_fw;
2516
7ae0e400
MB		 2517 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2518 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
2519 existing_vfs);
2520
2521 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2522 dev->flags = dev_flags;
2523 if (!SRIOV_VALID_STATE(dev->flags)) {
2524 mlx4_err(dev, "Invalid SRIOV state\n");
2525 goto err_sriov;
2526 }
2527 err = mlx4_reset(dev);
2528 if (err) {
2529 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2530 goto err_sriov;
2531 }
2532 goto slave_start;
2533 }
2534 } else {
2535 /* Legacy mode FW requires SRIOV to be enabled before
2536 * doing QUERY_DEV_CAP, since max_eq's value is different if
2537 * SRIOV is enabled.
2538 */
2539 memset(dev_cap, 0, sizeof(*dev_cap));
2540 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2541 if (err) {
2542 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2543 goto err_fw;
2544 }
de966c59
MB		 2545
2546 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2547 goto err_fw;
7ae0e400
MB		 2548 }
2549 }
2550
225c7b1f 2551 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2552 if (err) {
2553 if (err == -EACCES) {
2554 /* Not primary Physical function
2555 * Running in slave mode */
ffc39f6d 2556 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 2557 /* We're not a PF */
2558 if (dev->flags & MLX4_FLAG_SRIOV) {
2559 if (!existing_vfs)
2560 pci_disable_sriov(pdev);
2561 if (mlx4_is_master(dev))
2562 atomic_dec(&pf_loading);
2563 dev->flags &= ~MLX4_FLAG_SRIOV;
2564 }
2565 if (!mlx4_is_slave(dev))
2566 mlx4_free_ownership(dev);
ab9c17a0
JM		 2567 dev->flags |= MLX4_FLAG_SLAVE;
2568 dev->flags &= ~MLX4_FLAG_MASTER;
2569 goto slave_start;
2570 } else
a0eacca9 2571 goto err_fw;
ab9c17a0
JM		 2572 }
2573
7ae0e400
MB		 2574 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2575 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, existing_vfs);
2576
2577 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
2578 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
2579 dev->flags = dev_flags;
2580 err = mlx4_cmd_init(dev);
2581 if (err) {
2582 /* Only VHCR is cleaned up, so could still
2583 * send FW commands
2584 */
2585 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
2586 goto err_close;
2587 }
2588 } else {
2589 dev->flags = dev_flags;
2590 }
2591
2592 if (!SRIOV_VALID_STATE(dev->flags)) {
2593 mlx4_err(dev, "Invalid SRIOV state\n");
2594 goto err_close;
2595 }
2596 }
2597
b912b2f8
EP		 2598 /* check if the device is functioning at its maximum possible speed.
2599 * No return code for this call, just warn the user in case of PCI
2600 * express device capabilities are under-satisfied by the bus.
2601 */
83d3459a
EP		 2602 if (!mlx4_is_slave(dev))
2603 mlx4_check_pcie_caps(dev);
b912b2f8 2604
ab9c17a0
JM		 2605 /* In master functions, the communication channel must be initialized
2606 * after obtaining its address from fw */
2607 if (mlx4_is_master(dev)) {
e1c00e10
MD		 2608 int ib_ports = 0;
2609
2610 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2611 ib_ports++;
2612
2613 if (ib_ports &&
2614 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2615 mlx4_err(dev,
2616 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2617 err = -EINVAL;
2618 goto err_close;
2619 }
2620 if (dev->caps.num_ports < 2 &&
2621 num_vfs_argc > 1) {
2622 err = -EINVAL;
2623 mlx4_err(dev,
2624 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2625 dev->caps.num_ports);
ab9c17a0
JM		 2626 goto err_close;
2627 }
e1c00e10 2628 memcpy(dev->nvfs, nvfs, sizeof(dev->nvfs));
dd41cc3b 2629
e1c00e10
MD		 2630 for (i = 0; i < sizeof(dev->nvfs)/sizeof(dev->nvfs[0]); i++) {
2631 unsigned j;
2632
2633 for (j = 0; j < dev->nvfs[i]; ++sum, ++j) {
2634 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
2635 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2636 dev->caps.num_ports;
1ab95d37
MB		 2637 }
2638 }
e1c00e10
MD		 2639
2640 /* In master functions, the communication channel
2641 * must be initialized after obtaining its address from fw
2642 */
2643 err = mlx4_multi_func_init(dev);
2644 if (err) {
2645 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
2646 goto err_close;
2647 }
ab9c17a0 2648 }
225c7b1f 2649
b8dd786f
YP		 2650 err = mlx4_alloc_eq_table(dev);
2651 if (err)
ab9c17a0 2652 goto err_master_mfunc;
b8dd786f 2653
0b7ca5a9 2654 priv->msix_ctl.pool_bm = 0;
730c41d5 2655 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2656
08fb1055 2657 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2658 if ((mlx4_is_mfunc(dev)) &&
2659 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2660 err = -ENOSYS;
1a91de28 2661 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 2662 goto err_free_eq;
ab9c17a0
JM		 2663 }
2664
2665 if (!mlx4_is_slave(dev)) {
2666 err = mlx4_init_steering(dev);
2667 if (err)
e1c00e10 2668 goto err_disable_msix;
ab9c17a0 2669 }
b12d93d6 2670
225c7b1f 2671 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2672 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2673 !mlx4_is_mfunc(dev)) {
08fb1055 2674 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2675 dev->caps.num_comp_vectors = 1;
2676 dev->caps.comp_pool = 0;
08fb1055
MT		 2677 pci_disable_msix(pdev);
2678 err = mlx4_setup_hca(dev);
2679 }
2680
225c7b1f 2681 if (err)
b12d93d6 2682 goto err_steer;
225c7b1f 2683
5a0d0a61
JM		 2684 mlx4_init_quotas(dev);
2685
7ff93f8b
YP		 2686 for (port = 1; port <= dev->caps.num_ports; port++) {
2687 err = mlx4_init_port_info(dev, port);
2688 if (err)
2689 goto err_port;
2690 }
2a2336f8 2691
225c7b1f
RD		 2692 err = mlx4_register_device(dev);
2693 if (err)
7ff93f8b 2694 goto err_port;
225c7b1f 2695
b046ffe5
EP		 2696 mlx4_request_modules(dev);
2697
27bf91d6
YP		 2698 mlx4_sense_init(dev);
2699 mlx4_start_sense(dev);
2700
befdf897 2701 priv->removed = 0;
225c7b1f 2702
e1a5ddc5
AV		 2703 if (mlx4_is_master(dev) && dev->num_vfs)
2704 atomic_dec(&pf_loading);
2705
225c7b1f
RD		 2706 return 0;
2707
7ff93f8b 2708err_port:
b4f77264 2709 for (--port; port >= 1; --port)
7ff93f8b
YP		 2710 mlx4_cleanup_port_info(&priv->port[port]);
2711
f2a3f6a3 2712 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2713 mlx4_cleanup_qp_table(dev);
2714 mlx4_cleanup_srq_table(dev);
2715 mlx4_cleanup_cq_table(dev);
2716 mlx4_cmd_use_polling(dev);
2717 mlx4_cleanup_eq_table(dev);
fe6f700d 2718 mlx4_cleanup_mcg_table(dev);
225c7b1f 2719 mlx4_cleanup_mr_table(dev);
012a8ff5 2720 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2721 mlx4_cleanup_pd_table(dev);
2722 mlx4_cleanup_uar_table(dev);
2723
b12d93d6 2724err_steer:
ab9c17a0
JM		 2725 if (!mlx4_is_slave(dev))
2726 mlx4_clear_steering(dev);
b12d93d6 2727
e1c00e10
MD		 2728err_disable_msix:
2729 if (dev->flags & MLX4_FLAG_MSI_X)
2730 pci_disable_msix(pdev);
2731
b8dd786f
YP		 2732err_free_eq:
2733 mlx4_free_eq_table(dev);
2734
ab9c17a0
JM		 2735err_master_mfunc:
2736 if (mlx4_is_master(dev))
2737 mlx4_multi_func_cleanup(dev);
2738
b38f2879 2739 if (mlx4_is_slave(dev)) {
99ec41d0 2740 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2741 kfree(dev->caps.qp0_tunnel);
2742 kfree(dev->caps.qp0_proxy);
2743 kfree(dev->caps.qp1_tunnel);
2744 kfree(dev->caps.qp1_proxy);
2745 }
2746
225c7b1f
RD		 2747err_close:
2748 mlx4_close_hca(dev);
2749
a0eacca9
MB		 2750err_fw:
2751 mlx4_close_fw(dev);
2752
ab9c17a0
JM		 2753err_mfunc:
2754 if (mlx4_is_slave(dev))
2755 mlx4_multi_func_cleanup(dev);
2756
225c7b1f 2757err_cmd:
ffc39f6d 2758 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 2759
ab9c17a0 2760err_sriov:
bbb07af4 2761 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs)
ab9c17a0
JM		 2762 pci_disable_sriov(pdev);
2763
e1a5ddc5
AV		 2764 if (mlx4_is_master(dev) && dev->num_vfs)
2765 atomic_dec(&pf_loading);
2766
1ab95d37
MB		 2767 kfree(priv->dev.dev_vfs);
2768
e1c00e10
MD		 2769 if (!mlx4_is_slave(dev))
2770 mlx4_free_ownership(dev);
2771
7ae0e400 2772 kfree(dev_cap);
e1c00e10
MD		 2773 return err;
2774}
2775
2776static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
2777 struct mlx4_priv *priv)
2778{
2779 int err;
2780 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2781 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2782 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2783 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2784 unsigned total_vfs = 0;
2785 unsigned int i;
2786
2787 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2788
2789 err = pci_enable_device(pdev);
2790 if (err) {
2791 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
2792 return err;
2793 }
2794
2795 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2796 * per port, we must limit the number of VFs to 63 (since their are
2797 * 128 MACs)
2798 */
2799 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2800 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2801 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
2802 if (nvfs[i] < 0) {
2803 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2804 err = -EINVAL;
2805 goto err_disable_pdev;
2806 }
2807 }
2808 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2809 i++) {
2810 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
2811 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2812 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2813 err = -EINVAL;
2814 goto err_disable_pdev;
2815 }
2816 }
2817 if (total_vfs >= MLX4_MAX_NUM_VF) {
2818 dev_err(&pdev->dev,
2819 "Requested more VF's (%d) than allowed (%d)\n",
2820 total_vfs, MLX4_MAX_NUM_VF - 1);
2821 err = -EINVAL;
2822 goto err_disable_pdev;
2823 }
2824
2825 for (i = 0; i < MLX4_MAX_PORTS; i++) {
2826 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2827 dev_err(&pdev->dev,
2828 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2829 nvfs[i] + nvfs[2], i + 1,
2830 MLX4_MAX_NUM_VF_P_PORT - 1);
2831 err = -EINVAL;
2832 goto err_disable_pdev;
2833 }
2834 }
2835
2836 /* Check for BARs. */
2837 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2838 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2839 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2840 pci_dev_data, pci_resource_flags(pdev, 0));
2841 err = -ENODEV;
2842 goto err_disable_pdev;
2843 }
2844 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2845 dev_err(&pdev->dev, "Missing UAR, aborting\n");
2846 err = -ENODEV;
2847 goto err_disable_pdev;
2848 }
2849
2850 err = pci_request_regions(pdev, DRV_NAME);
2851 if (err) {
2852 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2853 goto err_disable_pdev;
2854 }
2855
2856 pci_set_master(pdev);
2857
2858 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2859 if (err) {
2860 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
2861 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2862 if (err) {
2863 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
2864 goto err_release_regions;
2865 }
2866 }
2867 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2868 if (err) {
2869 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
2870 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2871 if (err) {
2872 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
2873 goto err_release_regions;
2874 }
2875 }
2876
2877 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2878 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2879 /* Detect if this device is a virtual function */
2880 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2881 /* When acting as pf, we normally skip vfs unless explicitly
2882 * requested to probe them.
2883 */
2884 if (total_vfs) {
2885 unsigned vfs_offset = 0;
2886
2887 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
2888 vfs_offset + nvfs[i] < extended_func_num(pdev);
2889 vfs_offset += nvfs[i], i++)
2890 ;
2891 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
2892 err = -ENODEV;
2893 goto err_release_regions;
2894 }
2895 if ((extended_func_num(pdev) - vfs_offset)
2896 > prb_vf[i]) {
2897 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
2898 extended_func_num(pdev));
2899 err = -ENODEV;
2900 goto err_release_regions;
2901 }
2902 }
2903 }
2904
2905 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
2906 if (err)
2907 goto err_release_regions;
2908 return 0;
225c7b1f 2909
a01df0fe
RD		 2910err_release_regions:
2911 pci_release_regions(pdev);
225c7b1f
RD		 2912
2913err_disable_pdev:
2914 pci_disable_device(pdev);
2915 pci_set_drvdata(pdev, NULL);
2916 return err;
2917}
2918
1dd06ae8 2919static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 2920{
befdf897
WY		 2921 struct mlx4_priv *priv;
2922 struct mlx4_dev *dev;
e1c00e10 2923 int ret;
befdf897 2924
0a645e80 2925 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2926
befdf897
WY		 2927 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2928 if (!priv)
2929 return -ENOMEM;
2930
2931 dev = &priv->dev;
e1c00e10 2932 dev->pdev = pdev;
befdf897
WY		 2933 pci_set_drvdata(pdev, dev);
2934 priv->pci_dev_data = id->driver_data;
2935
e1c00e10
MD		 2936 ret = __mlx4_init_one(pdev, id->driver_data, priv);
2937 if (ret)
2938 kfree(priv);
2939
2940 return ret;
3d73c288
RD		 2941}
2942
e1c00e10 2943static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f
RD		 2944{
2945 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2946 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 2947 int pci_dev_data;
225c7b1f 2948 int p;
bbb07af4 2949 int active_vfs = 0;
225c7b1f 2950
befdf897
WY		 2951 if (priv->removed)
2952 return;
225c7b1f 2953
befdf897 2954 pci_dev_data = priv->pci_dev_data;
225c7b1f 2955
bbb07af4
JM		 2956 /* Disabling SR-IOV is not allowed while there are active vf's */
2957 if (mlx4_is_master(dev)) {
2958 active_vfs = mlx4_how_many_lives_vf(dev);
2959 if (active_vfs) {
2960 pr_warn("Removing PF when there are active VF's !!\n");
2961 pr_warn("Will not disable SR-IOV.\n");
2962 }
2963 }
befdf897
WY		 2964 mlx4_stop_sense(dev);
2965 mlx4_unregister_device(dev);
225c7b1f 2966
befdf897
WY		 2967 for (p = 1; p <= dev->caps.num_ports; p++) {
2968 mlx4_cleanup_port_info(&priv->port[p]);
2969 mlx4_CLOSE_PORT(dev, p);
2970 }
2971
2972 if (mlx4_is_master(dev))
2973 mlx4_free_resource_tracker(dev,
2974 RES_TR_FREE_SLAVES_ONLY);
2975
2976 mlx4_cleanup_counters_table(dev);
2977 mlx4_cleanup_qp_table(dev);
2978 mlx4_cleanup_srq_table(dev);
2979 mlx4_cleanup_cq_table(dev);
2980 mlx4_cmd_use_polling(dev);
2981 mlx4_cleanup_eq_table(dev);
2982 mlx4_cleanup_mcg_table(dev);
2983 mlx4_cleanup_mr_table(dev);
2984 mlx4_cleanup_xrcd_table(dev);
2985 mlx4_cleanup_pd_table(dev);
225c7b1f 2986
befdf897
WY		 2987 if (mlx4_is_master(dev))
2988 mlx4_free_resource_tracker(dev,
2989 RES_TR_FREE_STRUCTS_ONLY);
47605df9 2990
befdf897
WY		 2991 iounmap(priv->kar);
2992 mlx4_uar_free(dev, &priv->driver_uar);
2993 mlx4_cleanup_uar_table(dev);
2994 if (!mlx4_is_slave(dev))
2995 mlx4_clear_steering(dev);
2996 mlx4_free_eq_table(dev);
2997 if (mlx4_is_master(dev))
2998 mlx4_multi_func_cleanup(dev);
2999 mlx4_close_hca(dev);
a0eacca9 3000 mlx4_close_fw(dev);
befdf897
WY		 3001 if (mlx4_is_slave(dev))
3002 mlx4_multi_func_cleanup(dev);
ffc39f6d 3003 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 3004
befdf897
WY		 3005 if (dev->flags & MLX4_FLAG_MSI_X)
3006 pci_disable_msix(pdev);
bbb07af4 3007 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
befdf897
WY		 3008 mlx4_warn(dev, "Disabling SR-IOV\n");
3009 pci_disable_sriov(pdev);
a0eacca9 3010 dev->flags &= ~MLX4_FLAG_SRIOV;
e1a5ddc5 3011 dev->num_vfs = 0;
225c7b1f 3012 }
befdf897
WY		 3013
3014 if (!mlx4_is_slave(dev))
3015 mlx4_free_ownership(dev);
3016
99ec41d0 3017 kfree(dev->caps.qp0_qkey);
befdf897
WY		 3018 kfree(dev->caps.qp0_tunnel);
3019 kfree(dev->caps.qp0_proxy);
3020 kfree(dev->caps.qp1_tunnel);
3021 kfree(dev->caps.qp1_proxy);
3022 kfree(dev->dev_vfs);
3023
befdf897
WY		 3024 memset(priv, 0, sizeof(*priv));
3025 priv->pci_dev_data = pci_dev_data;
3026 priv->removed = 1;
3027}
3028
3029static void mlx4_remove_one(struct pci_dev *pdev)
3030{
3031 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3032 struct mlx4_priv *priv = mlx4_priv(dev);
3033
e1c00e10
MD		 3034 mlx4_unload_one(pdev);
3035 pci_release_regions(pdev);
3036 pci_disable_device(pdev);
befdf897
WY		 3037 kfree(priv);
3038 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 3039}
3040
ee49bd93
JM		 3041int mlx4_restart_one(struct pci_dev *pdev)
3042{
839f1243
RD		 3043 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3044 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 3045 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3046 int pci_dev_data, err, total_vfs;
839f1243
RD		 3047
3048 pci_dev_data = priv->pci_dev_data;
e1c00e10
MD		 3049 total_vfs = dev->num_vfs;
3050 memcpy(nvfs, dev->nvfs, sizeof(dev->nvfs));
3051
3052 mlx4_unload_one(pdev);
3053 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
3054 if (err) {
3055 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3056 __func__, pci_name(pdev), err);
3057 return err;
3058 }
3059
3060 return err;
ee49bd93
JM		 3061}
3062
9baa3c34 3063static const struct pci_device_id mlx4_pci_table[] = {
ab9c17a0 3064 /* MT25408 "Hermon" SDR */
ca3e57a5 3065 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3066 /* MT25408 "Hermon" DDR */
ca3e57a5 3067 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3068 /* MT25408 "Hermon" QDR */
ca3e57a5 3069 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3070 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 3071 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3072 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 3073 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3074 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 3075 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3076 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 3077 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3078 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 3079 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3080 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 3081 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3082 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 3083 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3084 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 3085 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3086 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 3087 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3088 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 3089 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3090 /* MT27500 Family [ConnectX-3] */
3091 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3092 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 3093 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3094 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3095 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3096 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3097 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3098 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3099 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3100 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3101 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3102 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3103 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3104 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3105 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 3106 { 0, }
3107};
3108
3109MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3110
57dbf29a
KSS		 3111static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3112 pci_channel_state_t state)
3113{
e1c00e10 3114 mlx4_unload_one(pdev);
57dbf29a
KSS		 3115
3116 return state == pci_channel_io_perm_failure ?
3117 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
3118}
3119
3120static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3121{
befdf897
WY		 3122 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3123 struct mlx4_priv *priv = mlx4_priv(dev);
3124 int ret;
97a5221f 3125
e1c00e10 3126 ret = __mlx4_init_one(pdev, priv->pci_dev_data, priv);
57dbf29a
KSS		 3127
3128 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3129}
3130
3646f0e5 3131static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 3132 .error_detected = mlx4_pci_err_detected,
3133 .slot_reset = mlx4_pci_slot_reset,
3134};
3135
225c7b1f
RD		 3136static struct pci_driver mlx4_driver = {
3137 .name = DRV_NAME,
3138 .id_table = mlx4_pci_table,
3139 .probe = mlx4_init_one,
e1c00e10 3140 .shutdown = mlx4_unload_one,
f57e6848 3141 .remove = mlx4_remove_one,
57dbf29a 3142 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 3143};
3144
7ff93f8b
YP		 3145static int __init mlx4_verify_params(void)
3146{
3147 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 3148 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 3149 return -1;
3150 }
3151
cb29688a 3152 if (log_num_vlan != 0)
c20862c8
AV		 3153 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3154 MLX4_LOG_NUM_VLANS);
7ff93f8b 3155
ecc8fb11
AV		 3156 if (use_prio != 0)
3157 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 3158
0498628f 3159 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 3160 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3161 log_mtts_per_seg);
ab6bf42e
EC		 3162 return -1;
3163 }
3164
ab9c17a0
JM		 3165 /* Check if module param for ports type has legal combination */
3166 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 3167 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 3168 port_type_array[0] = true;
3169 }
3170
3c439b55
JM		 3171 if (mlx4_log_num_mgm_entry_size != -1 &&
3172 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3173 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
1a91de28
JP		 3174 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n",
3175 mlx4_log_num_mgm_entry_size,
3176 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3177 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 3178 return -1;
3179 }
3180
7ff93f8b
YP		 3181 return 0;
3182}
3183
225c7b1f
RD		 3184static int __init mlx4_init(void)
3185{
3186 int ret;
3187
7ff93f8b
YP		 3188 if (mlx4_verify_params())
3189 return -EINVAL;
3190
27bf91d6
YP		 3191 mlx4_catas_init();
3192
3193 mlx4_wq = create_singlethread_workqueue("mlx4");
3194 if (!mlx4_wq)
3195 return -ENOMEM;
ee49bd93 3196
225c7b1f 3197 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 3198 if (ret < 0)
3199 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3200 return ret < 0 ? ret : 0;
3201}
3202
3203static void __exit mlx4_cleanup(void)
3204{
3205 pci_unregister_driver(&mlx4_driver);
27bf91d6 3206 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3207}
3208
3209module_init(mlx4_init);
3210module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)