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mlx4: Replacing pool_lock with mutex
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
225c7b1f
RD		 44
45#include <linux/mlx4/device.h>
46#include <linux/mlx4/doorbell.h>
47
48#include "mlx4.h"
49#include "fw.h"
50#include "icm.h"
51
52MODULE_AUTHOR("Roland Dreier");
53MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
54MODULE_LICENSE("Dual BSD/GPL");
55MODULE_VERSION(DRV_VERSION);
56
27bf91d6
YP		 57struct workqueue_struct *mlx4_wq;
58
225c7b1f
RD		 59#ifdef CONFIG_MLX4_DEBUG
60
61int mlx4_debug_level = 0;
62module_param_named(debug_level, mlx4_debug_level, int, 0644);
63MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
64
65#endif /* CONFIG_MLX4_DEBUG */
66
67#ifdef CONFIG_PCI_MSI
68
08fb1055 69static int msi_x = 1;
225c7b1f
RD		 70module_param(msi_x, int, 0444);
71MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
72
73#else /* CONFIG_PCI_MSI */
74
75#define msi_x (0)
76
77#endif /* CONFIG_PCI_MSI */
78
ab9c17a0
JM		 79static int num_vfs;
80module_param(num_vfs, int, 0444);
81MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
82
83static int probe_vf;
84module_param(probe_vf, int, 0644);
85MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
86
0ec2c0f8
EE		 87int mlx4_log_num_mgm_entry_size = 10;
88module_param_named(log_num_mgm_entry_size,
89 mlx4_log_num_mgm_entry_size, int, 0444);
90MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
91 " of qp per mcg, for example:"
92 " 10 gives 248.range: 9<="
93 " log_num_mgm_entry_size <= 12");
94
ab9c17a0
JM		 95#define MLX4_VF (1 << 0)
96
97#define HCA_GLOBAL_CAP_MASK 0
98#define PF_CONTEXT_BEHAVIOUR_MASK 0
99
f33afc26 100static char mlx4_version[] __devinitdata =
225c7b1f
RD		 101 DRV_NAME ": Mellanox ConnectX core driver v"
102 DRV_VERSION " (" DRV_RELDATE ")\n";
103
104static struct mlx4_profile default_profile = {
ab9c17a0 105 .num_qp = 1 << 18,
225c7b1f 106 .num_srq = 1 << 16,
c9f2ba5e 107 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 108 .num_cq = 1 << 16,
109 .num_mcg = 1 << 13,
ab9c17a0 110 .num_mpt = 1 << 19,
9fd7a1e1 111 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 112};
113
ab9c17a0 114static int log_num_mac = 7;
93fc9e1b
YP		 115module_param_named(log_num_mac, log_num_mac, int, 0444);
116MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
117
118static int log_num_vlan;
119module_param_named(log_num_vlan, log_num_vlan, int, 0444);
120MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 121/* Log2 max number of VLANs per ETH port (0-7) */
122#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 123
eb939922 124static bool use_prio;
93fc9e1b
YP		 125module_param_named(use_prio, use_prio, bool, 0444);
126MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
127 "(0/1, default 0)");
128
2b8fb286 129int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 130module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 131MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 132
8d0fc7b6 133static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 134static int arr_argc = 2;
135module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 136MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
137 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 138
139struct mlx4_port_config {
140 struct list_head list;
141 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
142 struct pci_dev *pdev;
143};
144
145static inline int mlx4_master_get_num_eqs(struct mlx4_dev *dev)
146{
147 return dev->caps.reserved_eqs +
148 MLX4_MFUNC_EQ_NUM * (dev->num_slaves + 1);
149}
150
27bf91d6
YP		 151int mlx4_check_port_params(struct mlx4_dev *dev,
152 enum mlx4_port_type *port_type)
7ff93f8b
YP		 153{
154 int i;
155
156 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 157 if (port_type[i] != port_type[i + 1]) {
158 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
159 mlx4_err(dev, "Only same port types supported "
160 "on this HCA, aborting.\n");
161 return -EINVAL;
162 }
163 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
164 port_type[i + 1] == MLX4_PORT_TYPE_IB)
165 return -EINVAL;
7ff93f8b
YP		 166 }
167 }
7ff93f8b
YP		 168
169 for (i = 0; i < dev->caps.num_ports; i++) {
170 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
171 mlx4_err(dev, "Requested port type for port %d is not "
172 "supported on this HCA\n", i + 1);
173 return -EINVAL;
174 }
175 }
176 return 0;
177}
178
179static void mlx4_set_port_mask(struct mlx4_dev *dev)
180{
181 int i;
182
7ff93f8b 183 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 184 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 185}
f2a3f6a3 186
3d73c288 187static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 188{
189 int err;
5ae2a7a8 190 int i;
225c7b1f
RD		 191
192 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
193 if (err) {
194 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
195 return err;
196 }
197
198 if (dev_cap->min_page_sz > PAGE_SIZE) {
199 mlx4_err(dev, "HCA minimum page size of %d bigger than "
200 "kernel PAGE_SIZE of %ld, aborting.\n",
201 dev_cap->min_page_sz, PAGE_SIZE);
202 return -ENODEV;
203 }
204 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
205 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
206 "aborting.\n",
207 dev_cap->num_ports, MLX4_MAX_PORTS);
208 return -ENODEV;
209 }
210
211 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
212 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
213 "PCI resource 2 size of 0x%llx, aborting.\n",
214 dev_cap->uar_size,
215 (unsigned long long) pci_resource_len(dev->pdev, 2));
216 return -ENODEV;
217 }
218
219 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 220 for (i = 1; i <= dev->caps.num_ports; ++i) {
221 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 222 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
5ae2a7a8
RD		 223 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
224 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
225 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 226 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
227 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 228 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 229 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
230 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 231 dev->caps.trans_type[i] = dev_cap->trans_type[i];
232 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
233 dev->caps.wavelength[i] = dev_cap->wavelength[i];
234 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 235 }
236
ab9c17a0 237 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 238 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 239 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
240 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
241 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
242 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
243 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
244 dev->caps.max_wqes = dev_cap->max_qp_sz;
245 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 246 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
247 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
248 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
249 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
250 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
0ec2c0f8 251 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
225c7b1f
RD		 252 /*
253 * Subtract 1 from the limit because we need to allocate a
254 * spare CQE so the HCA HW can tell the difference between an
255 * empty CQ and a full CQ.
256 */
257 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
258 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
259 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 260 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 261 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 262
263 /* The first 128 UARs are used for EQ doorbells */
264 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 265 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 266 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
267 dev_cap->reserved_xrcds : 0;
268 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
269 dev_cap->max_xrcds : 0;
2b8fb286
MA		 270 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
271
149983af 272 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 273 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
274 dev->caps.flags = dev_cap->flags;
95d04f07
RD		 275 dev->caps.bmme_flags = dev_cap->bmme_flags;
276 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 277 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 278 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
225c7b1f 279
58a60168
YP		 280 /* Sense port always allowed on supported devices for ConnectX1 and 2 */
281 if (dev->pdev->device != 0x1003)
282 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
283
93fc9e1b 284 dev->caps.log_num_macs = log_num_mac;
cb29688a 285 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 286 dev->caps.log_num_prios = use_prio ? 3 : 0;
287
288 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 289 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
290 if (dev->caps.supported_type[i]) {
291 /* if only ETH is supported - assign ETH */
292 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
293 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
294 /* if only IB is supported,
295 * assign IB only if SRIOV is off*/
296 else if (dev->caps.supported_type[i] ==
297 MLX4_PORT_TYPE_IB) {
298 if (dev->flags & MLX4_FLAG_SRIOV)
299 dev->caps.port_type[i] =
300 MLX4_PORT_TYPE_NONE;
301 else
302 dev->caps.port_type[i] =
303 MLX4_PORT_TYPE_IB;
304 /* if IB and ETH are supported,
305 * first of all check if SRIOV is on */
306 } else if (dev->flags & MLX4_FLAG_SRIOV)
307 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
ab9c17a0 308 else {
8d0fc7b6
YP		 309 /* In non-SRIOV mode, we set the port type
310 * according to user selection of port type,
311 * if usere selected none, take the FW hint */
312 if (port_type_array[i-1] == MLX4_PORT_TYPE_NONE)
313 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
314 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 315 else
8d0fc7b6 316 dev->caps.port_type[i] = port_type_array[i-1];
ab9c17a0
JM		 317 }
318 }
8d0fc7b6
YP		 319 /*
320 * Link sensing is allowed on the port if 3 conditions are true:
321 * 1. Both protocols are supported on the port.
322 * 2. Different types are supported on the port
323 * 3. FW declared that it supports link sensing
324 */
27bf91d6 325 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 326 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 327 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 328 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 329
8d0fc7b6
YP		 330 /*
331 * If "default_sense" bit is set, we move the port to "AUTO" mode
332 * and perform sense_port FW command to try and set the correct
333 * port type from beginning
334 */
46c46747 335 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 336 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
337 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
338 mlx4_SENSE_PORT(dev, i, &sensed_port);
339 if (sensed_port != MLX4_PORT_TYPE_NONE)
340 dev->caps.port_type[i] = sensed_port;
341 } else {
342 dev->caps.possible_type[i] = dev->caps.port_type[i];
343 }
344
93fc9e1b
YP		 345 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
346 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
347 mlx4_warn(dev, "Requested number of MACs is too much "
348 "for port %d, reducing to %d.\n",
349 i, 1 << dev->caps.log_num_macs);
350 }
351 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
352 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
353 mlx4_warn(dev, "Requested number of VLANs is too much "
354 "for port %d, reducing to %d.\n",
355 i, 1 << dev->caps.log_num_vlans);
356 }
357 }
358
f2a3f6a3
OG		 359 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
360
93fc9e1b
YP		 361 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
362 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
363 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
364 (1 << dev->caps.log_num_macs) *
365 (1 << dev->caps.log_num_vlans) *
366 (1 << dev->caps.log_num_prios) *
367 dev->caps.num_ports;
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
369
370 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
371 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
372 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
373 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
374
225c7b1f
RD		 375 return 0;
376}
ab9c17a0
JM		 377/*The function checks if there are live vf, return the num of them*/
378static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
379{
380 struct mlx4_priv *priv = mlx4_priv(dev);
381 struct mlx4_slave_state *s_state;
382 int i;
383 int ret = 0;
384
385 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
386 s_state = &priv->mfunc.master.slave_state[i];
387 if (s_state->active && s_state->last_cmd !=
388 MLX4_COMM_CMD_RESET) {
389 mlx4_warn(dev, "%s: slave: %d is still active\n",
390 __func__, i);
391 ret++;
392 }
393 }
394 return ret;
395}
396
397static int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
398{
399 struct mlx4_priv *priv = mlx4_priv(dev);
400 struct mlx4_slave_state *s_slave;
401
402 if (!mlx4_is_master(dev))
403 return 0;
404
405 s_slave = &priv->mfunc.master.slave_state[slave];
406 return !!s_slave->active;
407}
408EXPORT_SYMBOL(mlx4_is_slave_active);
409
410static int mlx4_slave_cap(struct mlx4_dev *dev)
411{
412 int err;
413 u32 page_size;
414 struct mlx4_dev_cap dev_cap;
415 struct mlx4_func_cap func_cap;
416 struct mlx4_init_hca_param hca_param;
417 int i;
418
419 memset(&hca_param, 0, sizeof(hca_param));
420 err = mlx4_QUERY_HCA(dev, &hca_param);
421 if (err) {
422 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
423 return err;
424 }
425
426 /*fail if the hca has an unknown capability */
427 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
428 HCA_GLOBAL_CAP_MASK) {
429 mlx4_err(dev, "Unknown hca global capabilities\n");
430 return -ENOSYS;
431 }
432
433 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
434
435 memset(&dev_cap, 0, sizeof(dev_cap));
436 err = mlx4_dev_cap(dev, &dev_cap);
437 if (err) {
438 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
439 return err;
440 }
441
442 page_size = ~dev->caps.page_size_cap + 1;
443 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
444 if (page_size > PAGE_SIZE) {
445 mlx4_err(dev, "HCA minimum page size of %d bigger than "
446 "kernel PAGE_SIZE of %ld, aborting.\n",
447 page_size, PAGE_SIZE);
448 return -ENODEV;
449 }
450
451 /* slave gets uar page size from QUERY_HCA fw command */
452 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
453
454 /* TODO: relax this assumption */
455 if (dev->caps.uar_page_size != PAGE_SIZE) {
456 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
457 dev->caps.uar_page_size, PAGE_SIZE);
458 return -ENODEV;
459 }
460
461 memset(&func_cap, 0, sizeof(func_cap));
462 err = mlx4_QUERY_FUNC_CAP(dev, &func_cap);
463 if (err) {
464 mlx4_err(dev, "QUERY_FUNC_CAP command failed, aborting.\n");
465 return err;
466 }
467
468 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
469 PF_CONTEXT_BEHAVIOUR_MASK) {
470 mlx4_err(dev, "Unknown pf context behaviour\n");
471 return -ENOSYS;
472 }
473
ab9c17a0
JM		 474 dev->caps.num_ports = func_cap.num_ports;
475 dev->caps.num_qps = func_cap.qp_quota;
476 dev->caps.num_srqs = func_cap.srq_quota;
477 dev->caps.num_cqs = func_cap.cq_quota;
478 dev->caps.num_eqs = func_cap.max_eq;
479 dev->caps.reserved_eqs = func_cap.reserved_eq;
480 dev->caps.num_mpts = func_cap.mpt_quota;
481 dev->caps.num_mtts = func_cap.mtt_quota;
482 dev->caps.num_pds = MLX4_NUM_PDS;
483 dev->caps.num_mgms = 0;
484 dev->caps.num_amgms = 0;
485
486 for (i = 1; i <= dev->caps.num_ports; ++i)
487 dev->caps.port_mask[i] = dev->caps.port_type[i];
488
489 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
490 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
491 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
492 return -ENODEV;
493 }
494
495 if (dev->caps.uar_page_size * (dev->caps.num_uars -
496 dev->caps.reserved_uars) >
497 pci_resource_len(dev->pdev, 2)) {
498 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
499 "PCI resource 2 size of 0x%llx, aborting.\n",
500 dev->caps.uar_page_size * dev->caps.num_uars,
501 (unsigned long long) pci_resource_len(dev->pdev, 2));
502 return -ENODEV;
503 }
504
505#if 0
506 mlx4_warn(dev, "sqp_demux:%d\n", dev->caps.sqp_demux);
507 mlx4_warn(dev, "num_uars:%d reserved_uars:%d uar region:0x%x bar2:0x%llx\n",
508 dev->caps.num_uars, dev->caps.reserved_uars,
509 dev->caps.uar_page_size * dev->caps.num_uars,
510 pci_resource_len(dev->pdev, 2));
511 mlx4_warn(dev, "num_eqs:%d reserved_eqs:%d\n", dev->caps.num_eqs,
512 dev->caps.reserved_eqs);
513 mlx4_warn(dev, "num_pds:%d reserved_pds:%d slave_pd_shift:%d pd_base:%d\n",
514 dev->caps.num_pds, dev->caps.reserved_pds,
515 dev->caps.slave_pd_shift, dev->caps.pd_base);
516#endif
517 return 0;
518}
225c7b1f 519
7ff93f8b
YP		 520/*
521 * Change the port configuration of the device.
522 * Every user of this function must hold the port mutex.
523 */
27bf91d6
YP		 524int mlx4_change_port_types(struct mlx4_dev *dev,
525 enum mlx4_port_type *port_types)
7ff93f8b
YP		 526{
527 int err = 0;
528 int change = 0;
529 int port;
530
531 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 532 /* Change the port type only if the new type is different
533 * from the current, and not set to Auto */
7ff93f8b
YP		 534 if (port_types[port] != dev->caps.port_type[port + 1]) {
535 change = 1;
536 dev->caps.port_type[port + 1] = port_types[port];
537 }
538 }
539 if (change) {
540 mlx4_unregister_device(dev);
541 for (port = 1; port <= dev->caps.num_ports; port++) {
542 mlx4_CLOSE_PORT(dev, port);
543 err = mlx4_SET_PORT(dev, port);
544 if (err) {
545 mlx4_err(dev, "Failed to set port %d, "
546 "aborting\n", port);
547 goto out;
548 }
549 }
550 mlx4_set_port_mask(dev);
551 err = mlx4_register_device(dev);
552 }
553
554out:
555 return err;
556}
557
558static ssize_t show_port_type(struct device *dev,
559 struct device_attribute *attr,
560 char *buf)
561{
562 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
563 port_attr);
564 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 565 char type[8];
566
567 sprintf(type, "%s",
568 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
569 "ib" : "eth");
570 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
571 sprintf(buf, "auto (%s)\n", type);
572 else
573 sprintf(buf, "%s\n", type);
7ff93f8b 574
27bf91d6 575 return strlen(buf);
7ff93f8b
YP		 576}
577
578static ssize_t set_port_type(struct device *dev,
579 struct device_attribute *attr,
580 const char *buf, size_t count)
581{
582 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
583 port_attr);
584 struct mlx4_dev *mdev = info->dev;
585 struct mlx4_priv *priv = mlx4_priv(mdev);
586 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 587 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 588 int i;
589 int err = 0;
590
591 if (!strcmp(buf, "ib\n"))
592 info->tmp_type = MLX4_PORT_TYPE_IB;
593 else if (!strcmp(buf, "eth\n"))
594 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 595 else if (!strcmp(buf, "auto\n"))
596 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 597 else {
598 mlx4_err(mdev, "%s is not supported port type\n", buf);
599 return -EINVAL;
600 }
601
27bf91d6 602 mlx4_stop_sense(mdev);
7ff93f8b 603 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 604 /* Possible type is always the one that was delivered */
605 mdev->caps.possible_type[info->port] = info->tmp_type;
606
607 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 608 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 609 mdev->caps.possible_type[i+1];
610 if (types[i] == MLX4_PORT_TYPE_AUTO)
611 types[i] = mdev->caps.port_type[i+1];
612 }
7ff93f8b 613
58a60168
YP		 614 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
615 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 616 for (i = 1; i <= mdev->caps.num_ports; i++) {
617 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
618 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
619 err = -EINVAL;
620 }
621 }
622 }
623 if (err) {
624 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
625 "Set only 'eth' or 'ib' for both ports "
626 "(should be the same)\n");
627 goto out;
628 }
629
630 mlx4_do_sense_ports(mdev, new_types, types);
631
632 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 633 if (err)
634 goto out;
635
27bf91d6
YP		 636 /* We are about to apply the changes after the configuration
637 * was verified, no need to remember the temporary types
638 * any more */
639 for (i = 0; i < mdev->caps.num_ports; i++)
640 priv->port[i + 1].tmp_type = 0;
7ff93f8b 641
27bf91d6 642 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 643
644out:
27bf91d6 645 mlx4_start_sense(mdev);
7ff93f8b
YP		 646 mutex_unlock(&priv->port_mutex);
647 return err ? err : count;
648}
649
e8f9b2ed 650static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 651{
652 struct mlx4_priv *priv = mlx4_priv(dev);
653 int err;
654
655 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 656 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 657 if (!priv->fw.fw_icm) {
658 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
659 return -ENOMEM;
660 }
661
662 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
663 if (err) {
664 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
665 goto err_free;
666 }
667
668 err = mlx4_RUN_FW(dev);
669 if (err) {
670 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
671 goto err_unmap_fa;
672 }
673
674 return 0;
675
676err_unmap_fa:
677 mlx4_UNMAP_FA(dev);
678
679err_free:
5b0bf5e2 680 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 681 return err;
682}
683
e8f9b2ed
RD		 684static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
685 int cmpt_entry_sz)
225c7b1f
RD		 686{
687 struct mlx4_priv *priv = mlx4_priv(dev);
688 int err;
ab9c17a0 689 int num_eqs;
225c7b1f
RD		 690
691 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
692 cmpt_base +
693 ((u64) (MLX4_CMPT_TYPE_QP *
694 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
695 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 696 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
697 0, 0);
225c7b1f
RD		 698 if (err)
699 goto err;
700
701 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
702 cmpt_base +
703 ((u64) (MLX4_CMPT_TYPE_SRQ *
704 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
705 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 706 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 707 if (err)
708 goto err_qp;
709
710 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
711 cmpt_base +
712 ((u64) (MLX4_CMPT_TYPE_CQ *
713 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
714 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 715 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 716 if (err)
717 goto err_srq;
718
ab9c17a0
JM		 719 num_eqs = (mlx4_is_master(dev)) ?
720 roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) :
721 dev->caps.num_eqs;
225c7b1f
RD		 722 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
723 cmpt_base +
724 ((u64) (MLX4_CMPT_TYPE_EQ *
725 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 726 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 727 if (err)
728 goto err_cq;
729
730 return 0;
731
732err_cq:
733 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
734
735err_srq:
736 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
737
738err_qp:
739 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
740
741err:
742 return err;
743}
744
3d73c288
RD		 745static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
746 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 747{
748 struct mlx4_priv *priv = mlx4_priv(dev);
749 u64 aux_pages;
ab9c17a0 750 int num_eqs;
225c7b1f
RD		 751 int err;
752
753 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
754 if (err) {
755 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
756 return err;
757 }
758
759 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
760 (unsigned long long) icm_size >> 10,
761 (unsigned long long) aux_pages << 2);
762
763 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 764 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 765 if (!priv->fw.aux_icm) {
766 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
767 return -ENOMEM;
768 }
769
770 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
771 if (err) {
772 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
773 goto err_free_aux;
774 }
775
776 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
777 if (err) {
778 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
779 goto err_unmap_aux;
780 }
781
ab9c17a0
JM		 782
783 num_eqs = (mlx4_is_master(dev)) ?
784 roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) :
785 dev->caps.num_eqs;
fa0681d2
RD		 786 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
787 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 788 num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 789 if (err) {
790 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
791 goto err_unmap_cmpt;
792 }
793
d7bb58fb
JM		 794 /*
795 * Reserved MTT entries must be aligned up to a cacheline
796 * boundary, since the FW will write to them, while the driver
797 * writes to all other MTT entries. (The variable
798 * dev->caps.mtt_entry_sz below is really the MTT segment
799 * size, not the raw entry size)
800 */
801 dev->caps.reserved_mtts =
802 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
803 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
804
225c7b1f
RD		 805 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
806 init_hca->mtt_base,
807 dev->caps.mtt_entry_sz,
2b8fb286 808 dev->caps.num_mtts,
5b0bf5e2 809 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 810 if (err) {
811 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
812 goto err_unmap_eq;
813 }
814
815 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
816 init_hca->dmpt_base,
817 dev_cap->dmpt_entry_sz,
818 dev->caps.num_mpts,
5b0bf5e2 819 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 820 if (err) {
821 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
822 goto err_unmap_mtt;
823 }
824
825 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
826 init_hca->qpc_base,
827 dev_cap->qpc_entry_sz,
828 dev->caps.num_qps,
93fc9e1b
YP		 829 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
830 0, 0);
225c7b1f
RD		 831 if (err) {
832 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
833 goto err_unmap_dmpt;
834 }
835
836 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
837 init_hca->auxc_base,
838 dev_cap->aux_entry_sz,
839 dev->caps.num_qps,
93fc9e1b
YP		 840 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
841 0, 0);
225c7b1f
RD		 842 if (err) {
843 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
844 goto err_unmap_qp;
845 }
846
847 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
848 init_hca->altc_base,
849 dev_cap->altc_entry_sz,
850 dev->caps.num_qps,
93fc9e1b
YP		 851 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
852 0, 0);
225c7b1f
RD		 853 if (err) {
854 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
855 goto err_unmap_auxc;
856 }
857
858 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
859 init_hca->rdmarc_base,
860 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
861 dev->caps.num_qps,
93fc9e1b
YP		 862 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
863 0, 0);
225c7b1f
RD		 864 if (err) {
865 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
866 goto err_unmap_altc;
867 }
868
869 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
870 init_hca->cqc_base,
871 dev_cap->cqc_entry_sz,
872 dev->caps.num_cqs,
5b0bf5e2 873 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 874 if (err) {
875 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
876 goto err_unmap_rdmarc;
877 }
878
879 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
880 init_hca->srqc_base,
881 dev_cap->srq_entry_sz,
882 dev->caps.num_srqs,
5b0bf5e2 883 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 884 if (err) {
885 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
886 goto err_unmap_cq;
887 }
888
889 /*
890 * It's not strictly required, but for simplicity just map the
891 * whole multicast group table now. The table isn't very big
892 * and it's a lot easier than trying to track ref counts.
893 */
894 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 895 init_hca->mc_base,
896 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 897 dev->caps.num_mgms + dev->caps.num_amgms,
898 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 899 0, 0);
225c7b1f
RD		 900 if (err) {
901 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
902 goto err_unmap_srq;
903 }
904
905 return 0;
906
907err_unmap_srq:
908 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
909
910err_unmap_cq:
911 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
912
913err_unmap_rdmarc:
914 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
915
916err_unmap_altc:
917 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
918
919err_unmap_auxc:
920 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
921
922err_unmap_qp:
923 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
924
925err_unmap_dmpt:
926 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
927
928err_unmap_mtt:
929 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
930
931err_unmap_eq:
fa0681d2 932 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 933
934err_unmap_cmpt:
935 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
936 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
937 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
938 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
939
940err_unmap_aux:
941 mlx4_UNMAP_ICM_AUX(dev);
942
943err_free_aux:
5b0bf5e2 944 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 945
946 return err;
947}
948
949static void mlx4_free_icms(struct mlx4_dev *dev)
950{
951 struct mlx4_priv *priv = mlx4_priv(dev);
952
953 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
954 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
955 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
956 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
957 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
958 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
959 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
960 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
961 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 962 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 963 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
964 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
965 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
966 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 967
968 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 969 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 970}
971
ab9c17a0
JM		 972static void mlx4_slave_exit(struct mlx4_dev *dev)
973{
974 struct mlx4_priv *priv = mlx4_priv(dev);
975
976 down(&priv->cmd.slave_sem);
977 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
978 mlx4_warn(dev, "Failed to close slave function.\n");
979 up(&priv->cmd.slave_sem);
980}
981
c1b43dca
EC		 982static int map_bf_area(struct mlx4_dev *dev)
983{
984 struct mlx4_priv *priv = mlx4_priv(dev);
985 resource_size_t bf_start;
986 resource_size_t bf_len;
987 int err = 0;
988
3d747473
JM		 989 if (!dev->caps.bf_reg_size)
990 return -ENXIO;
991
ab9c17a0
JM		 992 bf_start = pci_resource_start(dev->pdev, 2) +
993 (dev->caps.num_uars << PAGE_SHIFT);
994 bf_len = pci_resource_len(dev->pdev, 2) -
995 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 996 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
997 if (!priv->bf_mapping)
998 err = -ENOMEM;
999
1000 return err;
1001}
1002
1003static void unmap_bf_area(struct mlx4_dev *dev)
1004{
1005 if (mlx4_priv(dev)->bf_mapping)
1006 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1007}
1008
225c7b1f
RD		 1009static void mlx4_close_hca(struct mlx4_dev *dev)
1010{
c1b43dca 1011 unmap_bf_area(dev);
ab9c17a0
JM		 1012 if (mlx4_is_slave(dev))
1013 mlx4_slave_exit(dev);
1014 else {
1015 mlx4_CLOSE_HCA(dev, 0);
1016 mlx4_free_icms(dev);
1017 mlx4_UNMAP_FA(dev);
1018 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1019 }
1020}
1021
1022static int mlx4_init_slave(struct mlx4_dev *dev)
1023{
1024 struct mlx4_priv *priv = mlx4_priv(dev);
1025 u64 dma = (u64) priv->mfunc.vhcr_dma;
1026 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1027 int ret_from_reset = 0;
1028 u32 slave_read;
1029 u32 cmd_channel_ver;
1030
1031 down(&priv->cmd.slave_sem);
1032 priv->cmd.max_cmds = 1;
1033 mlx4_warn(dev, "Sending reset\n");
1034 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1035 MLX4_COMM_TIME);
1036 /* if we are in the middle of flr the slave will try
1037 * NUM_OF_RESET_RETRIES times before leaving.*/
1038 if (ret_from_reset) {
1039 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1040 msleep(SLEEP_TIME_IN_RESET);
1041 while (ret_from_reset && num_of_reset_retries) {
1042 mlx4_warn(dev, "slave is currently in the"
1043 "middle of FLR. retrying..."
1044 "(try num:%d)\n",
1045 (NUM_OF_RESET_RETRIES -
1046 num_of_reset_retries + 1));
1047 ret_from_reset =
1048 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1049 0, MLX4_COMM_TIME);
1050 num_of_reset_retries = num_of_reset_retries - 1;
1051 }
1052 } else
1053 goto err;
1054 }
1055
1056 /* check the driver version - the slave I/F revision
1057 * must match the master's */
1058 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1059 cmd_channel_ver = mlx4_comm_get_version();
1060
1061 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1062 MLX4_COMM_GET_IF_REV(slave_read)) {
1063 mlx4_err(dev, "slave driver version is not supported"
1064 " by the master\n");
1065 goto err;
1066 }
1067
1068 mlx4_warn(dev, "Sending vhcr0\n");
1069 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1070 MLX4_COMM_TIME))
1071 goto err;
1072 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1073 MLX4_COMM_TIME))
1074 goto err;
1075 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1076 MLX4_COMM_TIME))
1077 goto err;
1078 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1079 goto err;
1080 up(&priv->cmd.slave_sem);
1081 return 0;
1082
1083err:
1084 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1085 up(&priv->cmd.slave_sem);
1086 return -EIO;
225c7b1f
RD		 1087}
1088
3d73c288 1089static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1090{
1091 struct mlx4_priv *priv = mlx4_priv(dev);
1092 struct mlx4_adapter adapter;
1093 struct mlx4_dev_cap dev_cap;
2d928651 1094 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1095 struct mlx4_profile profile;
1096 struct mlx4_init_hca_param init_hca;
1097 u64 icm_size;
1098 int err;
1099
ab9c17a0
JM		 1100 if (!mlx4_is_slave(dev)) {
1101 err = mlx4_QUERY_FW(dev);
1102 if (err) {
1103 if (err == -EACCES)
1104 mlx4_info(dev, "non-primary physical function, skipping.\n");
1105 else
1106 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1107 goto unmap_bf;
1108 }
225c7b1f 1109
ab9c17a0
JM		 1110 err = mlx4_load_fw(dev);
1111 if (err) {
1112 mlx4_err(dev, "Failed to start FW, aborting.\n");
1113 goto unmap_bf;
1114 }
225c7b1f 1115
ab9c17a0
JM		 1116 mlx4_cfg.log_pg_sz_m = 1;
1117 mlx4_cfg.log_pg_sz = 0;
1118 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1119 if (err)
1120 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1121
ab9c17a0
JM		 1122 err = mlx4_dev_cap(dev, &dev_cap);
1123 if (err) {
1124 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1125 goto err_stop_fw;
1126 }
225c7b1f 1127
ab9c17a0 1128 profile = default_profile;
225c7b1f 1129
ab9c17a0
JM		 1130 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1131 &init_hca);
1132 if ((long long) icm_size < 0) {
1133 err = icm_size;
1134 goto err_stop_fw;
1135 }
225c7b1f 1136
ab9c17a0
JM		 1137 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1138 init_hca.uar_page_sz = PAGE_SHIFT - 12;
c1b43dca 1139
ab9c17a0
JM		 1140 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1141 if (err)
1142 goto err_stop_fw;
225c7b1f 1143
ab9c17a0
JM		 1144 err = mlx4_INIT_HCA(dev, &init_hca);
1145 if (err) {
1146 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1147 goto err_free_icm;
1148 }
1149 } else {
1150 err = mlx4_init_slave(dev);
1151 if (err) {
1152 mlx4_err(dev, "Failed to initialize slave\n");
1153 goto unmap_bf;
1154 }
225c7b1f 1155
ab9c17a0
JM		 1156 err = mlx4_slave_cap(dev);
1157 if (err) {
1158 mlx4_err(dev, "Failed to obtain slave caps\n");
1159 goto err_close;
1160 }
225c7b1f
RD		 1161 }
1162
ab9c17a0
JM		 1163 if (map_bf_area(dev))
1164 mlx4_dbg(dev, "Failed to map blue flame area\n");
1165
1166 /*Only the master set the ports, all the rest got it from it.*/
1167 if (!mlx4_is_slave(dev))
1168 mlx4_set_port_mask(dev);
1169
225c7b1f
RD		 1170 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1171 if (err) {
1172 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1173 goto err_close;
1174 }
1175
1176 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1177 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1178
1179 return 0;
1180
1181err_close:
ab9c17a0 1182 mlx4_close_hca(dev);
225c7b1f
RD		 1183
1184err_free_icm:
ab9c17a0
JM		 1185 if (!mlx4_is_slave(dev))
1186 mlx4_free_icms(dev);
225c7b1f
RD		 1187
1188err_stop_fw:
ab9c17a0
JM		 1189 if (!mlx4_is_slave(dev)) {
1190 mlx4_UNMAP_FA(dev);
1191 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1192 }
1193unmap_bf:
c1b43dca 1194 unmap_bf_area(dev);
225c7b1f
RD		 1195 return err;
1196}
1197
f2a3f6a3
OG		 1198static int mlx4_init_counters_table(struct mlx4_dev *dev)
1199{
1200 struct mlx4_priv *priv = mlx4_priv(dev);
1201 int nent;
1202
1203 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1204 return -ENOENT;
1205
1206 nent = dev->caps.max_counters;
1207 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1208}
1209
1210static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1211{
1212 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1213}
1214
1215int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1216{
1217 struct mlx4_priv *priv = mlx4_priv(dev);
1218
1219 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1220 return -ENOENT;
1221
1222 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1223 if (*idx == -1)
1224 return -ENOMEM;
1225
1226 return 0;
1227}
1228EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1229
1230void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1231{
1232 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1233 return;
1234}
1235EXPORT_SYMBOL_GPL(mlx4_counter_free);
1236
3d73c288 1237static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1238{
1239 struct mlx4_priv *priv = mlx4_priv(dev);
1240 int err;
7ff93f8b 1241 int port;
9a5aa622 1242 __be32 ib_port_default_caps;
225c7b1f 1243
225c7b1f
RD		 1244 err = mlx4_init_uar_table(dev);
1245 if (err) {
1246 mlx4_err(dev, "Failed to initialize "
1247 "user access region table, aborting.\n");
1248 return err;
1249 }
1250
1251 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1252 if (err) {
1253 mlx4_err(dev, "Failed to allocate driver access region, "
1254 "aborting.\n");
1255 goto err_uar_table_free;
1256 }
1257
4979d18f 1258 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f
RD		 1259 if (!priv->kar) {
1260 mlx4_err(dev, "Couldn't map kernel access region, "
1261 "aborting.\n");
1262 err = -ENOMEM;
1263 goto err_uar_free;
1264 }
1265
1266 err = mlx4_init_pd_table(dev);
1267 if (err) {
1268 mlx4_err(dev, "Failed to initialize "
1269 "protection domain table, aborting.\n");
1270 goto err_kar_unmap;
1271 }
1272
012a8ff5
SH		 1273 err = mlx4_init_xrcd_table(dev);
1274 if (err) {
1275 mlx4_err(dev, "Failed to initialize "
1276 "reliable connection domain table, aborting.\n");
1277 goto err_pd_table_free;
1278 }
1279
225c7b1f
RD		 1280 err = mlx4_init_mr_table(dev);
1281 if (err) {
1282 mlx4_err(dev, "Failed to initialize "
1283 "memory region table, aborting.\n");
012a8ff5 1284 goto err_xrcd_table_free;
225c7b1f
RD		 1285 }
1286
225c7b1f
RD		 1287 err = mlx4_init_eq_table(dev);
1288 if (err) {
1289 mlx4_err(dev, "Failed to initialize "
1290 "event queue table, aborting.\n");
ee49bd93 1291 goto err_mr_table_free;
225c7b1f
RD		 1292 }
1293
1294 err = mlx4_cmd_use_events(dev);
1295 if (err) {
1296 mlx4_err(dev, "Failed to switch to event-driven "
1297 "firmware commands, aborting.\n");
1298 goto err_eq_table_free;
1299 }
1300
1301 err = mlx4_NOP(dev);
1302 if (err) {
08fb1055
MT		 1303 if (dev->flags & MLX4_FLAG_MSI_X) {
1304 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1305 "interrupt IRQ %d).\n",
b8dd786f 1306 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 1307 mlx4_warn(dev, "Trying again without MSI-X.\n");
1308 } else {
1309 mlx4_err(dev, "NOP command failed to generate interrupt "
1310 "(IRQ %d), aborting.\n",
b8dd786f 1311 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1312 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1313 }
225c7b1f
RD		 1314
1315 goto err_cmd_poll;
1316 }
1317
1318 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1319
1320 err = mlx4_init_cq_table(dev);
1321 if (err) {
1322 mlx4_err(dev, "Failed to initialize "
1323 "completion queue table, aborting.\n");
1324 goto err_cmd_poll;
1325 }
1326
1327 err = mlx4_init_srq_table(dev);
1328 if (err) {
1329 mlx4_err(dev, "Failed to initialize "
1330 "shared receive queue table, aborting.\n");
1331 goto err_cq_table_free;
1332 }
1333
1334 err = mlx4_init_qp_table(dev);
1335 if (err) {
1336 mlx4_err(dev, "Failed to initialize "
1337 "queue pair table, aborting.\n");
1338 goto err_srq_table_free;
1339 }
1340
ab9c17a0
JM		 1341 if (!mlx4_is_slave(dev)) {
1342 err = mlx4_init_mcg_table(dev);
1343 if (err) {
1344 mlx4_err(dev, "Failed to initialize "
1345 "multicast group table, aborting.\n");
1346 goto err_qp_table_free;
1347 }
225c7b1f
RD		 1348 }
1349
f2a3f6a3
OG		 1350 err = mlx4_init_counters_table(dev);
1351 if (err && err != -ENOENT) {
1352 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
ab9c17a0 1353 goto err_mcg_table_free;
f2a3f6a3
OG		 1354 }
1355
ab9c17a0
JM		 1356 if (!mlx4_is_slave(dev)) {
1357 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1358 ib_port_default_caps = 0;
1359 err = mlx4_get_port_ib_caps(dev, port,
1360 &ib_port_default_caps);
1361 if (err)
1362 mlx4_warn(dev, "failed to get port %d default "
1363 "ib capabilities (%d). Continuing "
1364 "with caps = 0\n", port, err);
1365 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1366
1367 err = mlx4_check_ext_port_caps(dev, port);
1368 if (err)
1369 mlx4_warn(dev, "failed to get port %d extended "
1370 "port capabilities support info (%d)."
1371 " Assuming not supported\n",
1372 port, err);
97285b78 1373
ab9c17a0
JM		 1374 err = mlx4_SET_PORT(dev, port);
1375 if (err) {
1376 mlx4_err(dev, "Failed to set port %d, aborting\n",
1377 port);
1378 goto err_counters_table_free;
1379 }
7ff93f8b
YP		 1380 }
1381 }
1382
225c7b1f
RD		 1383 return 0;
1384
f2a3f6a3
OG		 1385err_counters_table_free:
1386 mlx4_cleanup_counters_table(dev);
1387
ab9c17a0
JM		 1388err_mcg_table_free:
1389 mlx4_cleanup_mcg_table(dev);
1390
225c7b1f
RD		 1391err_qp_table_free:
1392 mlx4_cleanup_qp_table(dev);
1393
1394err_srq_table_free:
1395 mlx4_cleanup_srq_table(dev);
1396
1397err_cq_table_free:
1398 mlx4_cleanup_cq_table(dev);
1399
1400err_cmd_poll:
1401 mlx4_cmd_use_polling(dev);
1402
1403err_eq_table_free:
1404 mlx4_cleanup_eq_table(dev);
1405
ee49bd93 1406err_mr_table_free:
225c7b1f
RD		 1407 mlx4_cleanup_mr_table(dev);
1408
012a8ff5
SH		 1409err_xrcd_table_free:
1410 mlx4_cleanup_xrcd_table(dev);
1411
225c7b1f
RD		 1412err_pd_table_free:
1413 mlx4_cleanup_pd_table(dev);
1414
1415err_kar_unmap:
1416 iounmap(priv->kar);
1417
1418err_uar_free:
1419 mlx4_uar_free(dev, &priv->driver_uar);
1420
1421err_uar_table_free:
1422 mlx4_cleanup_uar_table(dev);
1423 return err;
1424}
1425
e8f9b2ed 1426static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 1427{
1428 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 1429 struct msix_entry *entries;
0b7ca5a9
YP		 1430 int nreq = min_t(int, dev->caps.num_ports *
1431 min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT)
1432 + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 1433 int err;
1434 int i;
1435
1436 if (msi_x) {
ab9c17a0
JM		 1437 /* In multifunction mode each function gets 2 msi-X vectors
1438 * one for data path completions anf the other for asynch events
1439 * or command completions */
1440 if (mlx4_is_mfunc(dev)) {
1441 nreq = 2;
1442 } else {
1443 nreq = min_t(int, dev->caps.num_eqs -
1444 dev->caps.reserved_eqs, nreq);
1445 }
1446
b8dd786f
YP		 1447 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1448 if (!entries)
1449 goto no_msi;
1450
1451 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1452 entries[i].entry = i;
1453
b8dd786f
YP		 1454 retry:
1455 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 1456 if (err) {
b8dd786f
YP		 1457 /* Try again if at least 2 vectors are available */
1458 if (err > 1) {
1459 mlx4_info(dev, "Requested %d vectors, "
1460 "but only %d MSI-X vectors available, "
1461 "trying again\n", nreq, err);
1462 nreq = err;
1463 goto retry;
1464 }
5bf0da7d 1465 kfree(entries);
225c7b1f
RD		 1466 goto no_msi;
1467 }
1468
0b7ca5a9
YP		 1469 if (nreq <
1470 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1471 /*Working in legacy mode , all EQ's shared*/
1472 dev->caps.comp_pool = 0;
1473 dev->caps.num_comp_vectors = nreq - 1;
1474 } else {
1475 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1476 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1477 }
b8dd786f 1478 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1479 priv->eq_table.eq[i].irq = entries[i].vector;
1480
1481 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 1482
1483 kfree(entries);
225c7b1f
RD		 1484 return;
1485 }
1486
1487no_msi:
b8dd786f 1488 dev->caps.num_comp_vectors = 1;
0b7ca5a9 1489 dev->caps.comp_pool = 0;
b8dd786f
YP		 1490
1491 for (i = 0; i < 2; ++i)
225c7b1f
RD		 1492 priv->eq_table.eq[i].irq = dev->pdev->irq;
1493}
1494
7ff93f8b 1495static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 1496{
1497 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 1498 int err = 0;
2a2336f8
YP		 1499
1500 info->dev = dev;
1501 info->port = port;
ab9c17a0
JM		 1502 if (!mlx4_is_slave(dev)) {
1503 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL);
1504 mlx4_init_mac_table(dev, &info->mac_table);
1505 mlx4_init_vlan_table(dev, &info->vlan_table);
1506 info->base_qpn =
1507 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
06fa0a88 1508 (port - 1) * (1 << log_num_mac);
ab9c17a0 1509 }
7ff93f8b
YP		 1510
1511 sprintf(info->dev_name, "mlx4_port%d", port);
1512 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 1513 if (mlx4_is_mfunc(dev))
1514 info->port_attr.attr.mode = S_IRUGO;
1515 else {
1516 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1517 info->port_attr.store = set_port_type;
1518 }
7ff93f8b 1519 info->port_attr.show = show_port_type;
3691c964 1520 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 1521
1522 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1523 if (err) {
1524 mlx4_err(dev, "Failed to create file for port %d\n", port);
1525 info->port = -1;
1526 }
1527
1528 return err;
1529}
1530
1531static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1532{
1533 if (info->port < 0)
1534 return;
1535
1536 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2a2336f8
YP		 1537}
1538
b12d93d6
YP		 1539static int mlx4_init_steering(struct mlx4_dev *dev)
1540{
1541 struct mlx4_priv *priv = mlx4_priv(dev);
1542 int num_entries = dev->caps.num_ports;
1543 int i, j;
1544
1545 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1546 if (!priv->steer)
1547 return -ENOMEM;
1548
1549 for (i = 0; i < num_entries; i++) {
1550 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1551 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1552 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1553 }
1554 INIT_LIST_HEAD(&priv->steer[i].high_prios);
1555 }
1556 return 0;
1557}
1558
1559static void mlx4_clear_steering(struct mlx4_dev *dev)
1560{
1561 struct mlx4_priv *priv = mlx4_priv(dev);
1562 struct mlx4_steer_index *entry, *tmp_entry;
1563 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1564 int num_entries = dev->caps.num_ports;
1565 int i, j;
1566
1567 for (i = 0; i < num_entries; i++) {
1568 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1569 list_for_each_entry_safe(pqp, tmp_pqp,
1570 &priv->steer[i].promisc_qps[j],
1571 list) {
1572 list_del(&pqp->list);
1573 kfree(pqp);
1574 }
1575 list_for_each_entry_safe(entry, tmp_entry,
1576 &priv->steer[i].steer_entries[j],
1577 list) {
1578 list_del(&entry->list);
1579 list_for_each_entry_safe(pqp, tmp_pqp,
1580 &entry->duplicates,
1581 list) {
1582 list_del(&pqp->list);
1583 kfree(pqp);
1584 }
1585 kfree(entry);
1586 }
1587 }
1588 }
1589 kfree(priv->steer);
1590}
1591
ab9c17a0
JM		 1592static int extended_func_num(struct pci_dev *pdev)
1593{
1594 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
1595}
1596
1597#define MLX4_OWNER_BASE 0x8069c
1598#define MLX4_OWNER_SIZE 4
1599
1600static int mlx4_get_ownership(struct mlx4_dev *dev)
1601{
1602 void __iomem *owner;
1603 u32 ret;
1604
1605 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1606 MLX4_OWNER_SIZE);
1607 if (!owner) {
1608 mlx4_err(dev, "Failed to obtain ownership bit\n");
1609 return -ENOMEM;
1610 }
1611
1612 ret = readl(owner);
1613 iounmap(owner);
1614 return (int) !!ret;
1615}
1616
1617static void mlx4_free_ownership(struct mlx4_dev *dev)
1618{
1619 void __iomem *owner;
1620
1621 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1622 MLX4_OWNER_SIZE);
1623 if (!owner) {
1624 mlx4_err(dev, "Failed to obtain ownership bit\n");
1625 return;
1626 }
1627 writel(0, owner);
1628 msleep(1000);
1629 iounmap(owner);
1630}
1631
3d73c288 1632static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
225c7b1f 1633{
225c7b1f
RD		 1634 struct mlx4_priv *priv;
1635 struct mlx4_dev *dev;
1636 int err;
2a2336f8 1637 int port;
225c7b1f 1638
0a645e80 1639 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 1640
1641 err = pci_enable_device(pdev);
1642 if (err) {
1643 dev_err(&pdev->dev, "Cannot enable PCI device, "
1644 "aborting.\n");
1645 return err;
1646 }
ab9c17a0
JM		 1647 if (num_vfs > MLX4_MAX_NUM_VF) {
1648 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
1649 num_vfs, MLX4_MAX_NUM_VF);
1650 return -EINVAL;
1651 }
225c7b1f 1652 /*
ab9c17a0 1653 * Check for BARs.
225c7b1f 1654 */
ab9c17a0
JM		 1655 if (((id == NULL) || !(id->driver_data & MLX4_VF)) &&
1656 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1657 dev_err(&pdev->dev, "Missing DCS, aborting."
1658 "(id == 0X%p, id->driver_data: 0x%lx,"
1659 " pci_resource_flags(pdev, 0):0x%lx)\n", id,
1660 id ? id->driver_data : 0, pci_resource_flags(pdev, 0));
225c7b1f
RD		 1661 err = -ENODEV;
1662 goto err_disable_pdev;
1663 }
1664 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1665 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1666 err = -ENODEV;
1667 goto err_disable_pdev;
1668 }
1669
a01df0fe 1670 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 1671 if (err) {
a01df0fe 1672 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 1673 goto err_disable_pdev;
1674 }
1675
225c7b1f
RD		 1676 pci_set_master(pdev);
1677
6a35528a 1678 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1679 if (err) {
1680 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 1681 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1682 if (err) {
1683 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 1684 goto err_release_regions;
225c7b1f
RD		 1685 }
1686 }
6a35528a 1687 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1688 if (err) {
1689 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1690 "consistent PCI DMA mask.\n");
284901a9 1691 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1692 if (err) {
1693 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1694 "aborting.\n");
a01df0fe 1695 goto err_release_regions;
225c7b1f
RD		 1696 }
1697 }
1698
7f9e5c48
DD		 1699 /* Allow large DMA segments, up to the firmware limit of 1 GB */
1700 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1701
225c7b1f
RD		 1702 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1703 if (!priv) {
1704 dev_err(&pdev->dev, "Device struct alloc failed, "
1705 "aborting.\n");
1706 err = -ENOMEM;
a01df0fe 1707 goto err_release_regions;
225c7b1f
RD		 1708 }
1709
1710 dev = &priv->dev;
1711 dev->pdev = pdev;
b581401e
RD		 1712 INIT_LIST_HEAD(&priv->ctx_list);
1713 spin_lock_init(&priv->ctx_lock);
225c7b1f 1714
7ff93f8b
YP		 1715 mutex_init(&priv->port_mutex);
1716
6296883c
YP		 1717 INIT_LIST_HEAD(&priv->pgdir_list);
1718 mutex_init(&priv->pgdir_mutex);
1719
c1b43dca
EC		 1720 INIT_LIST_HEAD(&priv->bf_list);
1721 mutex_init(&priv->bf_mutex);
1722
aca7a3ac 1723 dev->rev_id = pdev->revision;
ab9c17a0
JM		 1724 /* Detect if this device is a virtual function */
1725 if (id && id->driver_data & MLX4_VF) {
1726 /* When acting as pf, we normally skip vfs unless explicitly
1727 * requested to probe them. */
1728 if (num_vfs && extended_func_num(pdev) > probe_vf) {
1729 mlx4_warn(dev, "Skipping virtual function:%d\n",
1730 extended_func_num(pdev));
1731 err = -ENODEV;
1732 goto err_free_dev;
1733 }
1734 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
1735 dev->flags |= MLX4_FLAG_SLAVE;
1736 } else {
1737 /* We reset the device and enable SRIOV only for physical
1738 * devices. Try to claim ownership on the device;
1739 * if already taken, skip -- do not allow multiple PFs */
1740 err = mlx4_get_ownership(dev);
1741 if (err) {
1742 if (err < 0)
1743 goto err_free_dev;
1744 else {
1745 mlx4_warn(dev, "Multiple PFs not yet supported."
1746 " Skipping PF.\n");
1747 err = -EINVAL;
1748 goto err_free_dev;
1749 }
1750 }
aca7a3ac 1751
ab9c17a0
JM		 1752 if (num_vfs) {
1753 mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs);
1754 err = pci_enable_sriov(pdev, num_vfs);
1755 if (err) {
1756 mlx4_err(dev, "Failed to enable sriov,"
1757 "continuing without sriov enabled"
1758 " (err = %d).\n", err);
1759 num_vfs = 0;
1760 err = 0;
1761 } else {
1762 mlx4_warn(dev, "Running in master mode\n");
1763 dev->flags |= MLX4_FLAG_SRIOV |
1764 MLX4_FLAG_MASTER;
1765 dev->num_vfs = num_vfs;
1766 }
1767 }
1768
1769 /*
1770 * Now reset the HCA before we touch the PCI capabilities or
1771 * attempt a firmware command, since a boot ROM may have left
1772 * the HCA in an undefined state.
1773 */
1774 err = mlx4_reset(dev);
1775 if (err) {
1776 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1777 goto err_rel_own;
1778 }
225c7b1f
RD		 1779 }
1780
ab9c17a0 1781slave_start:
225c7b1f
RD		 1782 if (mlx4_cmd_init(dev)) {
1783 mlx4_err(dev, "Failed to init command interface, aborting.\n");
ab9c17a0
JM		 1784 goto err_sriov;
1785 }
1786
1787 /* In slave functions, the communication channel must be initialized
1788 * before posting commands. Also, init num_slaves before calling
1789 * mlx4_init_hca */
1790 if (mlx4_is_mfunc(dev)) {
1791 if (mlx4_is_master(dev))
1792 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
1793 else {
1794 dev->num_slaves = 0;
1795 if (mlx4_multi_func_init(dev)) {
1796 mlx4_err(dev, "Failed to init slave mfunc"
1797 " interface, aborting.\n");
1798 goto err_cmd;
1799 }
1800 }
225c7b1f
RD		 1801 }
1802
1803 err = mlx4_init_hca(dev);
ab9c17a0
JM		 1804 if (err) {
1805 if (err == -EACCES) {
1806 /* Not primary Physical function
1807 * Running in slave mode */
1808 mlx4_cmd_cleanup(dev);
1809 dev->flags |= MLX4_FLAG_SLAVE;
1810 dev->flags &= ~MLX4_FLAG_MASTER;
1811 goto slave_start;
1812 } else
1813 goto err_mfunc;
1814 }
1815
1816 /* In master functions, the communication channel must be initialized
1817 * after obtaining its address from fw */
1818 if (mlx4_is_master(dev)) {
1819 if (mlx4_multi_func_init(dev)) {
1820 mlx4_err(dev, "Failed to init master mfunc"
1821 "interface, aborting.\n");
1822 goto err_close;
1823 }
1824 }
225c7b1f 1825
b8dd786f
YP		 1826 err = mlx4_alloc_eq_table(dev);
1827 if (err)
ab9c17a0 1828 goto err_master_mfunc;
b8dd786f 1829
0b7ca5a9 1830 priv->msix_ctl.pool_bm = 0;
730c41d5 1831 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 1832
08fb1055 1833 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 1834 if ((mlx4_is_mfunc(dev)) &&
1835 !(dev->flags & MLX4_FLAG_MSI_X)) {
1836 mlx4_err(dev, "INTx is not supported in multi-function mode."
1837 " aborting.\n");
b12d93d6 1838 goto err_free_eq;
ab9c17a0
JM		 1839 }
1840
1841 if (!mlx4_is_slave(dev)) {
1842 err = mlx4_init_steering(dev);
1843 if (err)
1844 goto err_free_eq;
1845 }
b12d93d6 1846
225c7b1f 1847 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 1848 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
1849 !mlx4_is_mfunc(dev)) {
08fb1055
MT		 1850 dev->flags &= ~MLX4_FLAG_MSI_X;
1851 pci_disable_msix(pdev);
1852 err = mlx4_setup_hca(dev);
1853 }
1854
225c7b1f 1855 if (err)
b12d93d6 1856 goto err_steer;
225c7b1f 1857
7ff93f8b
YP		 1858 for (port = 1; port <= dev->caps.num_ports; port++) {
1859 err = mlx4_init_port_info(dev, port);
1860 if (err)
1861 goto err_port;
1862 }
2a2336f8 1863
225c7b1f
RD		 1864 err = mlx4_register_device(dev);
1865 if (err)
7ff93f8b 1866 goto err_port;
225c7b1f 1867
27bf91d6
YP		 1868 mlx4_sense_init(dev);
1869 mlx4_start_sense(dev);
1870
225c7b1f
RD		 1871 pci_set_drvdata(pdev, dev);
1872
1873 return 0;
1874
7ff93f8b 1875err_port:
b4f77264 1876 for (--port; port >= 1; --port)
7ff93f8b
YP		 1877 mlx4_cleanup_port_info(&priv->port[port]);
1878
f2a3f6a3 1879 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 1880 mlx4_cleanup_mcg_table(dev);
1881 mlx4_cleanup_qp_table(dev);
1882 mlx4_cleanup_srq_table(dev);
1883 mlx4_cleanup_cq_table(dev);
1884 mlx4_cmd_use_polling(dev);
1885 mlx4_cleanup_eq_table(dev);
225c7b1f 1886 mlx4_cleanup_mr_table(dev);
012a8ff5 1887 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 1888 mlx4_cleanup_pd_table(dev);
1889 mlx4_cleanup_uar_table(dev);
1890
b12d93d6 1891err_steer:
ab9c17a0
JM		 1892 if (!mlx4_is_slave(dev))
1893 mlx4_clear_steering(dev);
b12d93d6 1894
b8dd786f
YP		 1895err_free_eq:
1896 mlx4_free_eq_table(dev);
1897
ab9c17a0
JM		 1898err_master_mfunc:
1899 if (mlx4_is_master(dev))
1900 mlx4_multi_func_cleanup(dev);
1901
225c7b1f 1902err_close:
08fb1055
MT		 1903 if (dev->flags & MLX4_FLAG_MSI_X)
1904 pci_disable_msix(pdev);
1905
225c7b1f
RD		 1906 mlx4_close_hca(dev);
1907
ab9c17a0
JM		 1908err_mfunc:
1909 if (mlx4_is_slave(dev))
1910 mlx4_multi_func_cleanup(dev);
1911
225c7b1f
RD		 1912err_cmd:
1913 mlx4_cmd_cleanup(dev);
1914
ab9c17a0
JM		 1915err_sriov:
1916 if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV))
1917 pci_disable_sriov(pdev);
1918
1919err_rel_own:
1920 if (!mlx4_is_slave(dev))
1921 mlx4_free_ownership(dev);
1922
225c7b1f 1923err_free_dev:
225c7b1f
RD		 1924 kfree(priv);
1925
a01df0fe
RD		 1926err_release_regions:
1927 pci_release_regions(pdev);
225c7b1f
RD		 1928
1929err_disable_pdev:
1930 pci_disable_device(pdev);
1931 pci_set_drvdata(pdev, NULL);
1932 return err;
1933}
1934
3d73c288
RD		 1935static int __devinit mlx4_init_one(struct pci_dev *pdev,
1936 const struct pci_device_id *id)
1937{
0a645e80 1938 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 1939
b027cacd 1940 return __mlx4_init_one(pdev, id);
3d73c288
RD		 1941}
1942
1943static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 1944{
1945 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1946 struct mlx4_priv *priv = mlx4_priv(dev);
1947 int p;
1948
1949 if (dev) {
ab9c17a0
JM		 1950 /* in SRIOV it is not allowed to unload the pf's
1951 * driver while there are alive vf's */
1952 if (mlx4_is_master(dev)) {
1953 if (mlx4_how_many_lives_vf(dev))
1954 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
1955 }
27bf91d6 1956 mlx4_stop_sense(dev);
225c7b1f
RD		 1957 mlx4_unregister_device(dev);
1958
7ff93f8b
YP		 1959 for (p = 1; p <= dev->caps.num_ports; p++) {
1960 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 1961 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 1962 }
225c7b1f 1963
f2a3f6a3 1964 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 1965 mlx4_cleanup_mcg_table(dev);
1966 mlx4_cleanup_qp_table(dev);
1967 mlx4_cleanup_srq_table(dev);
1968 mlx4_cleanup_cq_table(dev);
1969 mlx4_cmd_use_polling(dev);
1970 mlx4_cleanup_eq_table(dev);
225c7b1f 1971 mlx4_cleanup_mr_table(dev);
012a8ff5 1972 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 1973 mlx4_cleanup_pd_table(dev);
1974
ab9c17a0
JM		 1975 if (mlx4_is_master(dev))
1976 mlx4_free_resource_tracker(dev);
1977
225c7b1f
RD		 1978 iounmap(priv->kar);
1979 mlx4_uar_free(dev, &priv->driver_uar);
1980 mlx4_cleanup_uar_table(dev);
ab9c17a0
JM		 1981 if (!mlx4_is_slave(dev))
1982 mlx4_clear_steering(dev);
b8dd786f 1983 mlx4_free_eq_table(dev);
ab9c17a0
JM		 1984 if (mlx4_is_master(dev))
1985 mlx4_multi_func_cleanup(dev);
225c7b1f 1986 mlx4_close_hca(dev);
ab9c17a0
JM		 1987 if (mlx4_is_slave(dev))
1988 mlx4_multi_func_cleanup(dev);
225c7b1f
RD		 1989 mlx4_cmd_cleanup(dev);
1990
1991 if (dev->flags & MLX4_FLAG_MSI_X)
1992 pci_disable_msix(pdev);
ab9c17a0
JM		 1993 if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV)) {
1994 mlx4_warn(dev, "Disabling sriov\n");
1995 pci_disable_sriov(pdev);
1996 }
225c7b1f 1997
ab9c17a0
JM		 1998 if (!mlx4_is_slave(dev))
1999 mlx4_free_ownership(dev);
225c7b1f 2000 kfree(priv);
a01df0fe 2001 pci_release_regions(pdev);
225c7b1f
RD		 2002 pci_disable_device(pdev);
2003 pci_set_drvdata(pdev, NULL);
2004 }
2005}
2006
ee49bd93
JM		 2007int mlx4_restart_one(struct pci_dev *pdev)
2008{
2009 mlx4_remove_one(pdev);
3d73c288 2010 return __mlx4_init_one(pdev, NULL);
ee49bd93
JM		 2011}
2012
a3aa1884 2013static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0
JM		 2014 /* MT25408 "Hermon" SDR */
2015 { PCI_VDEVICE(MELLANOX, 0x6340), 0 },
2016 /* MT25408 "Hermon" DDR */
2017 { PCI_VDEVICE(MELLANOX, 0x634a), 0 },
2018 /* MT25408 "Hermon" QDR */
2019 { PCI_VDEVICE(MELLANOX, 0x6354), 0 },
2020 /* MT25408 "Hermon" DDR PCIe gen2 */
2021 { PCI_VDEVICE(MELLANOX, 0x6732), 0 },
2022 /* MT25408 "Hermon" QDR PCIe gen2 */
2023 { PCI_VDEVICE(MELLANOX, 0x673c), 0 },
2024 /* MT25408 "Hermon" EN 10GigE */
2025 { PCI_VDEVICE(MELLANOX, 0x6368), 0 },
2026 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2027 { PCI_VDEVICE(MELLANOX, 0x6750), 0 },
2028 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2029 { PCI_VDEVICE(MELLANOX, 0x6372), 0 },
2030 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2031 { PCI_VDEVICE(MELLANOX, 0x675a), 0 },
2032 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2033 { PCI_VDEVICE(MELLANOX, 0x6764), 0 },
2034 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2035 { PCI_VDEVICE(MELLANOX, 0x6746), 0 },
2036 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2037 { PCI_VDEVICE(MELLANOX, 0x676e), 0 },
2038 /* MT25400 Family [ConnectX-2 Virtual Function] */
2039 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_VF },
2040 /* MT27500 Family [ConnectX-3] */
2041 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2042 /* MT27500 Family [ConnectX-3 Virtual Function] */
2043 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_VF },
2044 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2045 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2046 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2047 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2048 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2049 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2050 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2051 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2052 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2053 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2054 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2055 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2056 { 0, }
2057};
2058
2059MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2060
2061static struct pci_driver mlx4_driver = {
2062 .name = DRV_NAME,
2063 .id_table = mlx4_pci_table,
2064 .probe = mlx4_init_one,
2065 .remove = __devexit_p(mlx4_remove_one)
2066};
2067
7ff93f8b
YP		 2068static int __init mlx4_verify_params(void)
2069{
2070 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2071 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2072 return -1;
2073 }
2074
cb29688a
OG		 2075 if (log_num_vlan != 0)
2076 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2077 MLX4_LOG_NUM_VLANS);
7ff93f8b 2078
0498628f 2079 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2080 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2081 return -1;
2082 }
2083
ab9c17a0
JM		 2084 /* Check if module param for ports type has legal combination */
2085 if (port_type_array[0] == false && port_type_array[1] == true) {
2086 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2087 port_type_array[0] = true;
2088 }
2089
7ff93f8b
YP		 2090 return 0;
2091}
2092
225c7b1f
RD		 2093static int __init mlx4_init(void)
2094{
2095 int ret;
2096
7ff93f8b
YP		 2097 if (mlx4_verify_params())
2098 return -EINVAL;
2099
27bf91d6
YP		 2100 mlx4_catas_init();
2101
2102 mlx4_wq = create_singlethread_workqueue("mlx4");
2103 if (!mlx4_wq)
2104 return -ENOMEM;
ee49bd93 2105
225c7b1f
RD		 2106 ret = pci_register_driver(&mlx4_driver);
2107 return ret < 0 ? ret : 0;
2108}
2109
2110static void __exit mlx4_cleanup(void)
2111{
2112 pci_unregister_driver(&mlx4_driver);
27bf91d6 2113 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2114}
2115
2116module_init(mlx4_init);
2117module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)