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net/mlx4: mlx4_config_dev_retrieval() - Initialize struct config_dev before using
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
dd41cc3b 80static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 81static int num_vfs_argc;
dd41cc3b
MB		 82module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 87static int probe_vfs_argc;
dd41cc3b
MB		 88module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
ab9c17a0 91
3c439b55 92int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 93module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
3c439b55 97 " 10 gives 248.range: 7 <="
0ff1fb65 98 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 99 " To activate device managed"
100 " flow steering when available, set to -1");
0ec2c0f8 101
be902ab1 102static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 103module_param(enable_64b_cqe_eqe, bool, 0444);
104MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 106
77507aa2 107#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
7d077cd3
MB		 108 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
109 MLX4_FUNC_CAP_DMFS_A0_STATIC)
ab9c17a0 110
55ad3592
YH		 111#define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV)
112
f57e6848 113static char mlx4_version[] =
225c7b1f
RD		 114 DRV_NAME ": Mellanox ConnectX core driver v"
115 DRV_VERSION " (" DRV_RELDATE ")\n";
116
117static struct mlx4_profile default_profile = {
ab9c17a0 118 .num_qp = 1 << 18,
225c7b1f 119 .num_srq = 1 << 16,
c9f2ba5e 120 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 121 .num_cq = 1 << 16,
122 .num_mcg = 1 << 13,
ab9c17a0 123 .num_mpt = 1 << 19,
9fd7a1e1 124 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 125};
126
2599d858
AV		 127static struct mlx4_profile low_mem_profile = {
128 .num_qp = 1 << 17,
129 .num_srq = 1 << 6,
130 .rdmarc_per_qp = 1 << 4,
131 .num_cq = 1 << 8,
132 .num_mcg = 1 << 8,
133 .num_mpt = 1 << 9,
134 .num_mtt = 1 << 7,
135};
136
ab9c17a0 137static int log_num_mac = 7;
93fc9e1b
YP		 138module_param_named(log_num_mac, log_num_mac, int, 0444);
139MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
140
141static int log_num_vlan;
142module_param_named(log_num_vlan, log_num_vlan, int, 0444);
143MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 144/* Log2 max number of VLANs per ETH port (0-7) */
145#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 146#define MLX4_MIN_LOG_NUM_VLANS 0
147#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 148
eb939922 149static bool use_prio;
93fc9e1b 150module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 151MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 152
2b8fb286 153int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 154module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 155MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 156
8d0fc7b6 157static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 158static int arr_argc = 2;
159module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 160MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
161 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 162
163struct mlx4_port_config {
164 struct list_head list;
165 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
166 struct pci_dev *pdev;
167};
168
97989356
AV		 169static atomic_t pf_loading = ATOMIC_INIT(0);
170
27bf91d6
YP		 171int mlx4_check_port_params(struct mlx4_dev *dev,
172 enum mlx4_port_type *port_type)
7ff93f8b
YP		 173{
174 int i;
175
0b997657
YS		 176 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
177 for (i = 0; i < dev->caps.num_ports - 1; i++) {
178 if (port_type[i] != port_type[i + 1]) {
1a91de28 179 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 180 return -EINVAL;
181 }
7ff93f8b
YP		 182 }
183 }
7ff93f8b
YP		 184
185 for (i = 0; i < dev->caps.num_ports; i++) {
186 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 187 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
188 i + 1);
7ff93f8b
YP		 189 return -EINVAL;
190 }
191 }
192 return 0;
193}
194
195static void mlx4_set_port_mask(struct mlx4_dev *dev)
196{
197 int i;
198
7ff93f8b 199 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 200 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 201}
f2a3f6a3 202
7ae0e400
MB		 203enum {
204 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
205};
206
207static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
208{
209 int err = 0;
210 struct mlx4_func func;
211
212 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
213 err = mlx4_QUERY_FUNC(dev, &func, 0);
214 if (err) {
215 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
216 return err;
217 }
218 dev_cap->max_eqs = func.max_eq;
219 dev_cap->reserved_eqs = func.rsvd_eqs;
220 dev_cap->reserved_uars = func.rsvd_uars;
221 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
222 }
223 return err;
224}
225
77507aa2
IS		 226static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
227{
228 struct mlx4_caps *dev_cap = &dev->caps;
229
230 /* FW not supporting or cancelled by user */
231 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
232 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
233 return;
234
235 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
236 * When FW has NCSI it may decide not to report 64B CQE/EQEs
237 */
238 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
239 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
240 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
241 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
242 return;
243 }
244
245 if (cache_line_size() == 128 || cache_line_size() == 256) {
246 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
247 /* Changing the real data inside CQE size to 32B */
248 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
249 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
250
251 if (mlx4_is_master(dev))
252 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
253 } else {
254 mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n");
255 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
256 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
257 }
258}
259
431df8c7
MB		 260static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
261 struct mlx4_port_cap *port_cap)
262{
263 dev->caps.vl_cap[port] = port_cap->max_vl;
264 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
265 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
266 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
267 /* set gid and pkey table operating lengths by default
268 * to non-sriov values
269 */
270 dev->caps.gid_table_len[port] = port_cap->max_gids;
271 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
272 dev->caps.port_width_cap[port] = port_cap->max_port_width;
273 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
274 dev->caps.def_mac[port] = port_cap->def_mac;
275 dev->caps.supported_type[port] = port_cap->supported_port_types;
276 dev->caps.suggested_type[port] = port_cap->suggested_type;
277 dev->caps.default_sense[port] = port_cap->default_sense;
278 dev->caps.trans_type[port] = port_cap->trans_type;
279 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
280 dev->caps.wavelength[port] = port_cap->wavelength;
281 dev->caps.trans_code[port] = port_cap->trans_code;
282
283 return 0;
284}
285
286static int mlx4_dev_port(struct mlx4_dev *dev, int port,
287 struct mlx4_port_cap *port_cap)
288{
289 int err = 0;
290
291 err = mlx4_QUERY_PORT(dev, port, port_cap);
292
293 if (err)
294 mlx4_err(dev, "QUERY_PORT command failed.\n");
295
296 return err;
297}
298
299#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 300static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 301{
302 int err;
5ae2a7a8 303 int i;
225c7b1f
RD		 304
305 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
306 if (err) {
1a91de28 307 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 308 return err;
309 }
c78e25ed 310 mlx4_dev_cap_dump(dev, dev_cap);
225c7b1f
RD		 311
312 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 313 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 314 dev_cap->min_page_sz, PAGE_SIZE);
315 return -ENODEV;
316 }
317 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 318 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 319 dev_cap->num_ports, MLX4_MAX_PORTS);
320 return -ENODEV;
321 }
322
872bf2fb 323 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
1a91de28 324 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f 325 dev_cap->uar_size,
872bf2fb
YH		 326 (unsigned long long)
327 pci_resource_len(dev->persist->pdev, 2));
225c7b1f
RD		 328 return -ENODEV;
329 }
330
331 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 332 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
333 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
334 dev->caps.num_sys_eqs :
335 MLX4_MAX_EQ_NUM;
5ae2a7a8 336 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 337 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
338 if (err) {
339 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
340 return err;
341 }
5ae2a7a8
RD		 342 }
343
ab9c17a0 344 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 345 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 346 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
347 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
348 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
349 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
350 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
351 dev->caps.max_wqes = dev_cap->max_qp_sz;
352 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 353 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
354 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
355 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
356 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
357 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 358 /*
359 * Subtract 1 from the limit because we need to allocate a
360 * spare CQE so the HCA HW can tell the difference between an
361 * empty CQ and a full CQ.
362 */
363 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
364 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
365 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 366 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 367 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 368
369 /* The first 128 UARs are used for EQ doorbells */
370 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 371 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 372 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
373 dev_cap->reserved_xrcds : 0;
374 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
375 dev_cap->max_xrcds : 0;
2b8fb286
MA		 376 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
377
149983af 378 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 379 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
380 dev->caps.flags = dev_cap->flags;
b3416f44 381 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 382 dev->caps.bmme_flags = dev_cap->bmme_flags;
383 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 384 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 385 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 386 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 387
ca3e57a5
RD		 388 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
389 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 390 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 391 /* Don't do sense port on multifunction devices (for now at least) */
392 if (mlx4_is_mfunc(dev))
393 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 394
2599d858
AV		 395 if (mlx4_low_memory_profile()) {
396 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
397 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
398 } else {
399 dev->caps.log_num_macs = log_num_mac;
400 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
401 }
93fc9e1b
YP		 402
403 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 404 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
405 if (dev->caps.supported_type[i]) {
406 /* if only ETH is supported - assign ETH */
407 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
408 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 409 /* if only IB is supported, assign IB */
ab9c17a0 410 else if (dev->caps.supported_type[i] ==
105c320f
JM		 411 MLX4_PORT_TYPE_IB)
412 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 413 else {
105c320f
JM		 414 /* if IB and ETH are supported, we set the port
415 * type according to user selection of port type;
416 * if user selected none, take the FW hint */
417 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 418 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
419 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 420 else
105c320f 421 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 422 }
423 }
8d0fc7b6
YP		 424 /*
425 * Link sensing is allowed on the port if 3 conditions are true:
426 * 1. Both protocols are supported on the port.
427 * 2. Different types are supported on the port
428 * 3. FW declared that it supports link sensing
429 */
27bf91d6 430 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 431 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 432 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 433 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 434
8d0fc7b6
YP		 435 /*
436 * If "default_sense" bit is set, we move the port to "AUTO" mode
437 * and perform sense_port FW command to try and set the correct
438 * port type from beginning
439 */
46c46747 440 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 441 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
442 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
443 mlx4_SENSE_PORT(dev, i, &sensed_port);
444 if (sensed_port != MLX4_PORT_TYPE_NONE)
445 dev->caps.port_type[i] = sensed_port;
446 } else {
447 dev->caps.possible_type[i] = dev->caps.port_type[i];
448 }
449
431df8c7
MB		 450 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
451 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 452 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 453 i, 1 << dev->caps.log_num_macs);
454 }
431df8c7
MB		 455 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
456 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 457 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 458 i, 1 << dev->caps.log_num_vlans);
459 }
460 }
461
f2a3f6a3
OG		 462 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
463
93fc9e1b
YP		 464 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
465 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
466 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
467 (1 << dev->caps.log_num_macs) *
468 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 469 dev->caps.num_ports;
470 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
7d077cd3
MB		 471
472 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
473 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
474 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
475 else
476 dev->caps.dmfs_high_rate_qpn_base =
477 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
478
479 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
480 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
481 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
482 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
483 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
484 } else {
485 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
486 dev->caps.dmfs_high_rate_qpn_base =
487 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
488 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
489 }
490
d57febe1 491 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
7d077cd3 492 dev->caps.dmfs_high_rate_qpn_range;
93fc9e1b
YP		 493
494 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
495 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
496 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
497 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
498
e2c76824 499 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 500
b3051320 501 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 502 if (dev_cap->flags &
503 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
504 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
505 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
506 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
507 }
77507aa2
IS		 508
509 if (dev_cap->flags2 &
510 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
511 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
512 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
513 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
514 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
515 }
08ff3235
OG		 516 }
517
f97b4b5d 518 if ((dev->caps.flags &
08ff3235
OG		 519 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
520 mlx4_is_master(dev))
521 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
522
ddae0349 523 if (!mlx4_is_slave(dev)) {
77507aa2 524 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 525 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 526 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
527 MLX4_RESERVE_A0_QP;
ddae0349
EE		 528 } else {
529 dev->caps.alloc_res_qp_mask = 0;
530 }
77507aa2 531
225c7b1f
RD		 532 return 0;
533}
b912b2f8
EP		 534
535static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
536 enum pci_bus_speed *speed,
537 enum pcie_link_width *width)
538{
539 u32 lnkcap1, lnkcap2;
540 int err1, err2;
541
542#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
543
544 *speed = PCI_SPEED_UNKNOWN;
545 *width = PCIE_LNK_WIDTH_UNKNOWN;
546
872bf2fb
YH		 547 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
548 &lnkcap1);
549 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
550 &lnkcap2);
b912b2f8
EP		 551 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
552 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
553 *speed = PCIE_SPEED_8_0GT;
554 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
555 *speed = PCIE_SPEED_5_0GT;
556 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
557 *speed = PCIE_SPEED_2_5GT;
558 }
559 if (!err1) {
560 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
561 if (!lnkcap2) { /* pre-r3.0 */
562 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
563 *speed = PCIE_SPEED_5_0GT;
564 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
565 *speed = PCIE_SPEED_2_5GT;
566 }
567 }
568
569 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
570 return err1 ? err1 :
571 err2 ? err2 : -EINVAL;
572 }
573 return 0;
574}
575
576static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
577{
578 enum pcie_link_width width, width_cap;
579 enum pci_bus_speed speed, speed_cap;
580 int err;
581
582#define PCIE_SPEED_STR(speed) \
583 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
584 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
585 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
586 "Unknown")
587
588 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
589 if (err) {
590 mlx4_warn(dev,
591 "Unable to determine PCIe device BW capabilities\n");
592 return;
593 }
594
872bf2fb 595 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
b912b2f8
EP		 596 if (err || speed == PCI_SPEED_UNKNOWN ||
597 width == PCIE_LNK_WIDTH_UNKNOWN) {
598 mlx4_warn(dev,
599 "Unable to determine PCI device chain minimum BW\n");
600 return;
601 }
602
603 if (width != width_cap || speed != speed_cap)
604 mlx4_warn(dev,
605 "PCIe BW is different than device's capability\n");
606
607 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
608 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
609 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
610 width, width_cap);
611 return;
612}
613
ab9c17a0
JM		 614/*The function checks if there are live vf, return the num of them*/
615static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
616{
617 struct mlx4_priv *priv = mlx4_priv(dev);
618 struct mlx4_slave_state *s_state;
619 int i;
620 int ret = 0;
621
622 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
623 s_state = &priv->mfunc.master.slave_state[i];
624 if (s_state->active && s_state->last_cmd !=
625 MLX4_COMM_CMD_RESET) {
626 mlx4_warn(dev, "%s: slave: %d is still active\n",
627 __func__, i);
628 ret++;
629 }
630 }
631 return ret;
632}
633
396f2feb
JM		 634int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
635{
636 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 637
638 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
639 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 640 return -EINVAL;
641
47605df9 642 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 643 /* tunnel qp */
47605df9 644 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 645 else
47605df9 646 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 647 *qkey = qk;
648 return 0;
649}
650EXPORT_SYMBOL(mlx4_get_parav_qkey);
651
54679e14
JM		 652void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
653{
654 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
655
656 if (!mlx4_is_master(dev))
657 return;
658
659 priv->virt2phys_pkey[slave][port - 1][i] = val;
660}
661EXPORT_SYMBOL(mlx4_sync_pkey_table);
662
afa8fd1d
JM		 663void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
664{
665 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
666
667 if (!mlx4_is_master(dev))
668 return;
669
670 priv->slave_node_guids[slave] = guid;
671}
672EXPORT_SYMBOL(mlx4_put_slave_node_guid);
673
674__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
675{
676 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
677
678 if (!mlx4_is_master(dev))
679 return 0;
680
681 return priv->slave_node_guids[slave];
682}
683EXPORT_SYMBOL(mlx4_get_slave_node_guid);
684
e10903b0 685int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 686{
687 struct mlx4_priv *priv = mlx4_priv(dev);
688 struct mlx4_slave_state *s_slave;
689
690 if (!mlx4_is_master(dev))
691 return 0;
692
693 s_slave = &priv->mfunc.master.slave_state[slave];
694 return !!s_slave->active;
695}
696EXPORT_SYMBOL(mlx4_is_slave_active);
697
7b8157be
JM		 698static void slave_adjust_steering_mode(struct mlx4_dev *dev,
699 struct mlx4_dev_cap *dev_cap,
700 struct mlx4_init_hca_param *hca_param)
701{
702 dev->caps.steering_mode = hca_param->steering_mode;
703 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
704 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
705 dev->caps.fs_log_max_ucast_qp_range_size =
706 dev_cap->fs_log_max_ucast_qp_range_size;
707 } else
708 dev->caps.num_qp_per_mgm =
709 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
710
711 mlx4_dbg(dev, "Steering mode is: %s\n",
712 mlx4_steering_mode_str(dev->caps.steering_mode));
713}
714
ab9c17a0
JM		 715static int mlx4_slave_cap(struct mlx4_dev *dev)
716{
717 int err;
718 u32 page_size;
719 struct mlx4_dev_cap dev_cap;
720 struct mlx4_func_cap func_cap;
721 struct mlx4_init_hca_param hca_param;
225c6c8c 722 u8 i;
ab9c17a0
JM		 723
724 memset(&hca_param, 0, sizeof(hca_param));
725 err = mlx4_QUERY_HCA(dev, &hca_param);
726 if (err) {
1a91de28 727 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
ab9c17a0
JM		 728 return err;
729 }
730
483e0132
EP		 731 /* fail if the hca has an unknown global capability
732 * at this time global_caps should be always zeroed
733 */
734 if (hca_param.global_caps) {
ab9c17a0
JM		 735 mlx4_err(dev, "Unknown hca global capabilities\n");
736 return -ENOSYS;
737 }
738
739 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
740
ddd8a6c1
EE		 741 dev->caps.hca_core_clock = hca_param.hca_core_clock;
742
ab9c17a0 743 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 744 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 745 err = mlx4_dev_cap(dev, &dev_cap);
746 if (err) {
1a91de28 747 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 748 return err;
749 }
750
b91cb3eb
JM		 751 err = mlx4_QUERY_FW(dev);
752 if (err)
1a91de28 753 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 754
ab9c17a0
JM		 755 page_size = ~dev->caps.page_size_cap + 1;
756 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
757 if (page_size > PAGE_SIZE) {
1a91de28 758 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0
JM		 759 page_size, PAGE_SIZE);
760 return -ENODEV;
761 }
762
763 /* slave gets uar page size from QUERY_HCA fw command */
764 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
765
766 /* TODO: relax this assumption */
767 if (dev->caps.uar_page_size != PAGE_SIZE) {
768 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
769 dev->caps.uar_page_size, PAGE_SIZE);
770 return -ENODEV;
771 }
772
773 memset(&func_cap, 0, sizeof(func_cap));
47605df9 774 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 775 if (err) {
1a91de28
JP		 776 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
777 err);
ab9c17a0
JM		 778 return err;
779 }
780
781 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
782 PF_CONTEXT_BEHAVIOUR_MASK) {
7d077cd3
MB		 783 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
784 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
ab9c17a0
JM		 785 return -ENOSYS;
786 }
787
ab9c17a0 788 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 789 dev->quotas.qp = func_cap.qp_quota;
790 dev->quotas.srq = func_cap.srq_quota;
791 dev->quotas.cq = func_cap.cq_quota;
792 dev->quotas.mpt = func_cap.mpt_quota;
793 dev->quotas.mtt = func_cap.mtt_quota;
794 dev->caps.num_qps = 1 << hca_param.log_num_qps;
795 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
796 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
797 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
798 dev->caps.num_eqs = func_cap.max_eq;
799 dev->caps.reserved_eqs = func_cap.reserved_eq;
f0ce0615 800 dev->caps.reserved_lkey = func_cap.reserved_lkey;
ab9c17a0
JM		 801 dev->caps.num_pds = MLX4_NUM_PDS;
802 dev->caps.num_mgms = 0;
803 dev->caps.num_amgms = 0;
804
ab9c17a0 805 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 806 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
807 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 808 return -ENODEV;
809 }
810
99ec41d0 811 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
47605df9
JM		 812 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
813 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
814 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
815 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
816
817 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
99ec41d0
JM		 818 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
819 !dev->caps.qp0_qkey) {
47605df9
JM		 820 err = -ENOMEM;
821 goto err_mem;
822 }
823
6634961c 824 for (i = 1; i <= dev->caps.num_ports; ++i) {
225c6c8c 825 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
47605df9 826 if (err) {
1a91de28
JP		 827 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
828 i, err);
47605df9
JM		 829 goto err_mem;
830 }
99ec41d0 831 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
47605df9
JM		 832 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
833 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
834 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
835 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 836 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 837 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 838 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
839 &dev->caps.gid_table_len[i],
840 &dev->caps.pkey_table_len[i]))
47605df9 841 goto err_mem;
6634961c 842 }
6230bb23 843
ab9c17a0
JM		 844 if (dev->caps.uar_page_size * (dev->caps.num_uars -
845 dev->caps.reserved_uars) >
872bf2fb
YH		 846 pci_resource_len(dev->persist->pdev,
847 2)) {
1a91de28 848 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0 849 dev->caps.uar_page_size * dev->caps.num_uars,
872bf2fb
YH		 850 (unsigned long long)
851 pci_resource_len(dev->persist->pdev, 2));
47605df9 852 goto err_mem;
ab9c17a0
JM		 853 }
854
08ff3235
OG		 855 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
856 dev->caps.eqe_size = 64;
857 dev->caps.eqe_factor = 1;
858 } else {
859 dev->caps.eqe_size = 32;
860 dev->caps.eqe_factor = 0;
861 }
862
863 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
864 dev->caps.cqe_size = 64;
77507aa2 865 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 866 } else {
867 dev->caps.cqe_size = 32;
868 }
869
77507aa2
IS		 870 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
871 dev->caps.eqe_size = hca_param.eqe_size;
872 dev->caps.eqe_factor = 0;
873 }
874
875 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
876 dev->caps.cqe_size = hca_param.cqe_size;
877 /* User still need to know when CQE > 32B */
878 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
879 }
880
f9bd2d7f 881 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 882 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 883
7b8157be
JM		 884 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
885
ddae0349
EE		 886 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
887 dev->caps.bf_reg_size)
888 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
889
d57febe1
MB		 890 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
891 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
892
ab9c17a0 893 return 0;
47605df9
JM		 894
895err_mem:
99ec41d0 896 kfree(dev->caps.qp0_qkey);
47605df9
JM		 897 kfree(dev->caps.qp0_tunnel);
898 kfree(dev->caps.qp0_proxy);
899 kfree(dev->caps.qp1_tunnel);
900 kfree(dev->caps.qp1_proxy);
99ec41d0
JM		 901 dev->caps.qp0_qkey = NULL;
902 dev->caps.qp0_tunnel = NULL;
903 dev->caps.qp0_proxy = NULL;
904 dev->caps.qp1_tunnel = NULL;
905 dev->caps.qp1_proxy = NULL;
47605df9
JM		 906
907 return err;
ab9c17a0 908}
225c7b1f 909
b046ffe5
EP		 910static void mlx4_request_modules(struct mlx4_dev *dev)
911{
912 int port;
913 int has_ib_port = false;
914 int has_eth_port = false;
915#define EN_DRV_NAME "mlx4_en"
916#define IB_DRV_NAME "mlx4_ib"
917
918 for (port = 1; port <= dev->caps.num_ports; port++) {
919 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
920 has_ib_port = true;
921 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
922 has_eth_port = true;
923 }
924
b046ffe5
EP		 925 if (has_eth_port)
926 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 927 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
928 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 929}
930
7ff93f8b
YP		 931/*
932 * Change the port configuration of the device.
933 * Every user of this function must hold the port mutex.
934 */
27bf91d6
YP		 935int mlx4_change_port_types(struct mlx4_dev *dev,
936 enum mlx4_port_type *port_types)
7ff93f8b
YP		 937{
938 int err = 0;
939 int change = 0;
940 int port;
941
942 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 943 /* Change the port type only if the new type is different
944 * from the current, and not set to Auto */
3d8f9308 945 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 946 change = 1;
7ff93f8b
YP		 947 }
948 if (change) {
949 mlx4_unregister_device(dev);
950 for (port = 1; port <= dev->caps.num_ports; port++) {
951 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 952 dev->caps.port_type[port] = port_types[port - 1];
6634961c 953 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 954 if (err) {
1a91de28
JP		 955 mlx4_err(dev, "Failed to set port %d, aborting\n",
956 port);
7ff93f8b
YP		 957 goto out;
958 }
959 }
960 mlx4_set_port_mask(dev);
961 err = mlx4_register_device(dev);
b046ffe5
EP		 962 if (err) {
963 mlx4_err(dev, "Failed to register device\n");
964 goto out;
965 }
966 mlx4_request_modules(dev);
7ff93f8b
YP		 967 }
968
969out:
970 return err;
971}
972
973static ssize_t show_port_type(struct device *dev,
974 struct device_attribute *attr,
975 char *buf)
976{
977 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
978 port_attr);
979 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 980 char type[8];
981
982 sprintf(type, "%s",
983 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
984 "ib" : "eth");
985 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
986 sprintf(buf, "auto (%s)\n", type);
987 else
988 sprintf(buf, "%s\n", type);
7ff93f8b 989
27bf91d6 990 return strlen(buf);
7ff93f8b
YP		 991}
992
993static ssize_t set_port_type(struct device *dev,
994 struct device_attribute *attr,
995 const char *buf, size_t count)
996{
997 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
998 port_attr);
999 struct mlx4_dev *mdev = info->dev;
1000 struct mlx4_priv *priv = mlx4_priv(mdev);
1001 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 1002 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
0a984556 1003 static DEFINE_MUTEX(set_port_type_mutex);
7ff93f8b
YP		 1004 int i;
1005 int err = 0;
1006
0a984556
AV		 1007 mutex_lock(&set_port_type_mutex);
1008
7ff93f8b
YP		 1009 if (!strcmp(buf, "ib\n"))
1010 info->tmp_type = MLX4_PORT_TYPE_IB;
1011 else if (!strcmp(buf, "eth\n"))
1012 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 1013 else if (!strcmp(buf, "auto\n"))
1014 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 1015 else {
1016 mlx4_err(mdev, "%s is not supported port type\n", buf);
0a984556
AV		 1017 err = -EINVAL;
1018 goto err_out;
7ff93f8b
YP		 1019 }
1020
27bf91d6 1021 mlx4_stop_sense(mdev);
7ff93f8b 1022 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 1023 /* Possible type is always the one that was delivered */
1024 mdev->caps.possible_type[info->port] = info->tmp_type;
1025
1026 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 1027 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 1028 mdev->caps.possible_type[i+1];
1029 if (types[i] == MLX4_PORT_TYPE_AUTO)
1030 types[i] = mdev->caps.port_type[i+1];
1031 }
7ff93f8b 1032
58a60168
YP		 1033 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1034 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1035 for (i = 1; i <= mdev->caps.num_ports; i++) {
1036 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1037 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1038 err = -EINVAL;
1039 }
1040 }
1041 }
1042 if (err) {
1a91de28 1043 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1044 goto out;
1045 }
1046
1047 mlx4_do_sense_ports(mdev, new_types, types);
1048
1049 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1050 if (err)
1051 goto out;
1052
27bf91d6
YP		 1053 /* We are about to apply the changes after the configuration
1054 * was verified, no need to remember the temporary types
1055 * any more */
1056 for (i = 0; i < mdev->caps.num_ports; i++)
1057 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1058
27bf91d6 1059 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1060
1061out:
27bf91d6 1062 mlx4_start_sense(mdev);
7ff93f8b 1063 mutex_unlock(&priv->port_mutex);
0a984556
AV		 1064err_out:
1065 mutex_unlock(&set_port_type_mutex);
1066
7ff93f8b
YP		 1067 return err ? err : count;
1068}
1069
096335b3
OG		 1070enum ibta_mtu {
1071 IB_MTU_256 = 1,
1072 IB_MTU_512 = 2,
1073 IB_MTU_1024 = 3,
1074 IB_MTU_2048 = 4,
1075 IB_MTU_4096 = 5
1076};
1077
1078static inline int int_to_ibta_mtu(int mtu)
1079{
1080 switch (mtu) {
1081 case 256: return IB_MTU_256;
1082 case 512: return IB_MTU_512;
1083 case 1024: return IB_MTU_1024;
1084 case 2048: return IB_MTU_2048;
1085 case 4096: return IB_MTU_4096;
1086 default: return -1;
1087 }
1088}
1089
1090static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1091{
1092 switch (mtu) {
1093 case IB_MTU_256: return 256;
1094 case IB_MTU_512: return 512;
1095 case IB_MTU_1024: return 1024;
1096 case IB_MTU_2048: return 2048;
1097 case IB_MTU_4096: return 4096;
1098 default: return -1;
1099 }
1100}
1101
1102static ssize_t show_port_ib_mtu(struct device *dev,
1103 struct device_attribute *attr,
1104 char *buf)
1105{
1106 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1107 port_mtu_attr);
1108 struct mlx4_dev *mdev = info->dev;
1109
1110 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1111 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1112
1113 sprintf(buf, "%d\n",
1114 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1115 return strlen(buf);
1116}
1117
1118static ssize_t set_port_ib_mtu(struct device *dev,
1119 struct device_attribute *attr,
1120 const char *buf, size_t count)
1121{
1122 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1123 port_mtu_attr);
1124 struct mlx4_dev *mdev = info->dev;
1125 struct mlx4_priv *priv = mlx4_priv(mdev);
1126 int err, port, mtu, ibta_mtu = -1;
1127
1128 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1129 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1130 return -EINVAL;
1131 }
1132
618fad95
DB		 1133 err = kstrtoint(buf, 0, &mtu);
1134 if (!err)
096335b3
OG		 1135 ibta_mtu = int_to_ibta_mtu(mtu);
1136
618fad95 1137 if (err || ibta_mtu < 0) {
096335b3
OG		 1138 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1139 return -EINVAL;
1140 }
1141
1142 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1143
1144 mlx4_stop_sense(mdev);
1145 mutex_lock(&priv->port_mutex);
1146 mlx4_unregister_device(mdev);
1147 for (port = 1; port <= mdev->caps.num_ports; port++) {
1148 mlx4_CLOSE_PORT(mdev, port);
6634961c 1149 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1150 if (err) {
1a91de28
JP		 1151 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1152 port);
096335b3
OG		 1153 goto err_set_port;
1154 }
1155 }
1156 err = mlx4_register_device(mdev);
1157err_set_port:
1158 mutex_unlock(&priv->port_mutex);
1159 mlx4_start_sense(mdev);
1160 return err ? err : count;
1161}
1162
53f33ae2
MS		 1163int mlx4_bond(struct mlx4_dev *dev)
1164{
1165 int ret = 0;
1166 struct mlx4_priv *priv = mlx4_priv(dev);
1167
1168 mutex_lock(&priv->bond_mutex);
1169
1170 if (!mlx4_is_bonded(dev))
1171 ret = mlx4_do_bond(dev, true);
1172 else
1173 ret = 0;
1174
1175 mutex_unlock(&priv->bond_mutex);
1176 if (ret)
1177 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1178 else
1179 mlx4_dbg(dev, "Device is bonded\n");
1180 return ret;
1181}
1182EXPORT_SYMBOL_GPL(mlx4_bond);
1183
1184int mlx4_unbond(struct mlx4_dev *dev)
1185{
1186 int ret = 0;
1187 struct mlx4_priv *priv = mlx4_priv(dev);
1188
1189 mutex_lock(&priv->bond_mutex);
1190
1191 if (mlx4_is_bonded(dev))
1192 ret = mlx4_do_bond(dev, false);
1193
1194 mutex_unlock(&priv->bond_mutex);
1195 if (ret)
1196 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1197 else
1198 mlx4_dbg(dev, "Device is unbonded\n");
1199 return ret;
1200}
1201EXPORT_SYMBOL_GPL(mlx4_unbond);
1202
1203
1204int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1205{
1206 u8 port1 = v2p->port1;
1207 u8 port2 = v2p->port2;
1208 struct mlx4_priv *priv = mlx4_priv(dev);
1209 int err;
1210
1211 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1212 return -ENOTSUPP;
1213
1214 mutex_lock(&priv->bond_mutex);
1215
1216 /* zero means keep current mapping for this port */
1217 if (port1 == 0)
1218 port1 = priv->v2p.port1;
1219 if (port2 == 0)
1220 port2 = priv->v2p.port2;
1221
1222 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1223 (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1224 (port1 == 2 && port2 == 1)) {
1225 /* besides boundary checks cross mapping makes
1226 * no sense and therefore not allowed */
1227 err = -EINVAL;
1228 } else if ((port1 == priv->v2p.port1) &&
1229 (port2 == priv->v2p.port2)) {
1230 err = 0;
1231 } else {
1232 err = mlx4_virt2phy_port_map(dev, port1, port2);
1233 if (!err) {
1234 mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1235 port1, port2);
1236 priv->v2p.port1 = port1;
1237 priv->v2p.port2 = port2;
1238 } else {
1239 mlx4_err(dev, "Failed to change port mape: %d\n", err);
1240 }
1241 }
1242
1243 mutex_unlock(&priv->bond_mutex);
1244 return err;
1245}
1246EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1247
e8f9b2ed 1248static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1249{
1250 struct mlx4_priv *priv = mlx4_priv(dev);
1251 int err;
1252
1253 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1254 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1255 if (!priv->fw.fw_icm) {
1a91de28 1256 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1257 return -ENOMEM;
1258 }
1259
1260 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1261 if (err) {
1a91de28 1262 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1263 goto err_free;
1264 }
1265
1266 err = mlx4_RUN_FW(dev);
1267 if (err) {
1a91de28 1268 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1269 goto err_unmap_fa;
1270 }
1271
1272 return 0;
1273
1274err_unmap_fa:
1275 mlx4_UNMAP_FA(dev);
1276
1277err_free:
5b0bf5e2 1278 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1279 return err;
1280}
1281
e8f9b2ed
RD		 1282static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1283 int cmpt_entry_sz)
225c7b1f
RD		 1284{
1285 struct mlx4_priv *priv = mlx4_priv(dev);
1286 int err;
ab9c17a0 1287 int num_eqs;
225c7b1f
RD		 1288
1289 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1290 cmpt_base +
1291 ((u64) (MLX4_CMPT_TYPE_QP *
1292 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1293 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1294 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1295 0, 0);
225c7b1f
RD		 1296 if (err)
1297 goto err;
1298
1299 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1300 cmpt_base +
1301 ((u64) (MLX4_CMPT_TYPE_SRQ *
1302 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1303 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1304 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1305 if (err)
1306 goto err_qp;
1307
1308 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1309 cmpt_base +
1310 ((u64) (MLX4_CMPT_TYPE_CQ *
1311 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1312 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1313 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1314 if (err)
1315 goto err_srq;
1316
7ae0e400 1317 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1318 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1319 cmpt_base +
1320 ((u64) (MLX4_CMPT_TYPE_EQ *
1321 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1322 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1323 if (err)
1324 goto err_cq;
1325
1326 return 0;
1327
1328err_cq:
1329 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1330
1331err_srq:
1332 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1333
1334err_qp:
1335 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1336
1337err:
1338 return err;
1339}
1340
3d73c288
RD		 1341static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1342 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1343{
1344 struct mlx4_priv *priv = mlx4_priv(dev);
1345 u64 aux_pages;
ab9c17a0 1346 int num_eqs;
225c7b1f
RD		 1347 int err;
1348
1349 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1350 if (err) {
1a91de28 1351 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1352 return err;
1353 }
1354
1a91de28 1355 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1356 (unsigned long long) icm_size >> 10,
1357 (unsigned long long) aux_pages << 2);
1358
1359 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1360 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1361 if (!priv->fw.aux_icm) {
1a91de28 1362 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1363 return -ENOMEM;
1364 }
1365
1366 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1367 if (err) {
1a91de28 1368 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1369 goto err_free_aux;
1370 }
1371
1372 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1373 if (err) {
1a91de28 1374 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1375 goto err_unmap_aux;
1376 }
1377
ab9c17a0 1378
7ae0e400 1379 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1380 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1381 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1382 num_eqs, num_eqs, 0, 0);
225c7b1f 1383 if (err) {
1a91de28 1384 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1385 goto err_unmap_cmpt;
1386 }
1387
d7bb58fb
JM		 1388 /*
1389 * Reserved MTT entries must be aligned up to a cacheline
1390 * boundary, since the FW will write to them, while the driver
1391 * writes to all other MTT entries. (The variable
1392 * dev->caps.mtt_entry_sz below is really the MTT segment
1393 * size, not the raw entry size)
1394 */
1395 dev->caps.reserved_mtts =
1396 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1397 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1398
225c7b1f
RD		 1399 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1400 init_hca->mtt_base,
1401 dev->caps.mtt_entry_sz,
2b8fb286 1402 dev->caps.num_mtts,
5b0bf5e2 1403 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1404 if (err) {
1a91de28 1405 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1406 goto err_unmap_eq;
1407 }
1408
1409 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1410 init_hca->dmpt_base,
1411 dev_cap->dmpt_entry_sz,
1412 dev->caps.num_mpts,
5b0bf5e2 1413 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1414 if (err) {
1a91de28 1415 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1416 goto err_unmap_mtt;
1417 }
1418
1419 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1420 init_hca->qpc_base,
1421 dev_cap->qpc_entry_sz,
1422 dev->caps.num_qps,
93fc9e1b
YP		 1423 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1424 0, 0);
225c7b1f 1425 if (err) {
1a91de28 1426 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1427 goto err_unmap_dmpt;
1428 }
1429
1430 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1431 init_hca->auxc_base,
1432 dev_cap->aux_entry_sz,
1433 dev->caps.num_qps,
93fc9e1b
YP		 1434 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1435 0, 0);
225c7b1f 1436 if (err) {
1a91de28 1437 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1438 goto err_unmap_qp;
1439 }
1440
1441 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1442 init_hca->altc_base,
1443 dev_cap->altc_entry_sz,
1444 dev->caps.num_qps,
93fc9e1b
YP		 1445 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1446 0, 0);
225c7b1f 1447 if (err) {
1a91de28 1448 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1449 goto err_unmap_auxc;
1450 }
1451
1452 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1453 init_hca->rdmarc_base,
1454 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1455 dev->caps.num_qps,
93fc9e1b
YP		 1456 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1457 0, 0);
225c7b1f
RD		 1458 if (err) {
1459 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1460 goto err_unmap_altc;
1461 }
1462
1463 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1464 init_hca->cqc_base,
1465 dev_cap->cqc_entry_sz,
1466 dev->caps.num_cqs,
5b0bf5e2 1467 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1468 if (err) {
1a91de28 1469 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1470 goto err_unmap_rdmarc;
1471 }
1472
1473 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1474 init_hca->srqc_base,
1475 dev_cap->srq_entry_sz,
1476 dev->caps.num_srqs,
5b0bf5e2 1477 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1478 if (err) {
1a91de28 1479 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1480 goto err_unmap_cq;
1481 }
1482
1483 /*
0ff1fb65
HHZ		 1484 * For flow steering device managed mode it is required to use
1485 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1486 * required, but for simplicity just map the whole multicast
1487 * group table now. The table isn't very big and it's a lot
1488 * easier than trying to track ref counts.
225c7b1f
RD		 1489 */
1490 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1491 init_hca->mc_base,
1492 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1493 dev->caps.num_mgms + dev->caps.num_amgms,
1494 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1495 0, 0);
225c7b1f 1496 if (err) {
1a91de28 1497 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1498 goto err_unmap_srq;
1499 }
1500
1501 return 0;
1502
1503err_unmap_srq:
1504 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1505
1506err_unmap_cq:
1507 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1508
1509err_unmap_rdmarc:
1510 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1511
1512err_unmap_altc:
1513 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1514
1515err_unmap_auxc:
1516 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1517
1518err_unmap_qp:
1519 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1520
1521err_unmap_dmpt:
1522 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1523
1524err_unmap_mtt:
1525 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1526
1527err_unmap_eq:
fa0681d2 1528 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1529
1530err_unmap_cmpt:
1531 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1532 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1533 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1534 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1535
1536err_unmap_aux:
1537 mlx4_UNMAP_ICM_AUX(dev);
1538
1539err_free_aux:
5b0bf5e2 1540 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1541
1542 return err;
1543}
1544
1545static void mlx4_free_icms(struct mlx4_dev *dev)
1546{
1547 struct mlx4_priv *priv = mlx4_priv(dev);
1548
1549 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1550 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1551 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1552 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1553 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1554 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1555 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1556 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1557 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1558 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1559 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1560 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1561 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1562 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1563
1564 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1565 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1566}
1567
ab9c17a0
JM		 1568static void mlx4_slave_exit(struct mlx4_dev *dev)
1569{
1570 struct mlx4_priv *priv = mlx4_priv(dev);
1571
f3d4c89e 1572 mutex_lock(&priv->cmd.slave_cmd_mutex);
0cd93027
YH		 1573 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1574 MLX4_COMM_TIME))
1a91de28 1575 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1576 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1577}
1578
c1b43dca
EC		 1579static int map_bf_area(struct mlx4_dev *dev)
1580{
1581 struct mlx4_priv *priv = mlx4_priv(dev);
1582 resource_size_t bf_start;
1583 resource_size_t bf_len;
1584 int err = 0;
1585
3d747473
JM		 1586 if (!dev->caps.bf_reg_size)
1587 return -ENXIO;
1588
872bf2fb 1589 bf_start = pci_resource_start(dev->persist->pdev, 2) +
ab9c17a0 1590 (dev->caps.num_uars << PAGE_SHIFT);
872bf2fb 1591 bf_len = pci_resource_len(dev->persist->pdev, 2) -
ab9c17a0 1592 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1593 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1594 if (!priv->bf_mapping)
1595 err = -ENOMEM;
1596
1597 return err;
1598}
1599
1600static void unmap_bf_area(struct mlx4_dev *dev)
1601{
1602 if (mlx4_priv(dev)->bf_mapping)
1603 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1604}
1605
ec693d47
AV		 1606cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1607{
1608 u32 clockhi, clocklo, clockhi1;
1609 cycle_t cycles;
1610 int i;
1611 struct mlx4_priv *priv = mlx4_priv(dev);
1612
1613 for (i = 0; i < 10; i++) {
1614 clockhi = swab32(readl(priv->clock_mapping));
1615 clocklo = swab32(readl(priv->clock_mapping + 4));
1616 clockhi1 = swab32(readl(priv->clock_mapping));
1617 if (clockhi == clockhi1)
1618 break;
1619 }
1620
1621 cycles = (u64) clockhi << 32 | (u64) clocklo;
1622
1623 return cycles;
1624}
1625EXPORT_SYMBOL_GPL(mlx4_read_clock);
1626
1627
ddd8a6c1
EE		 1628static int map_internal_clock(struct mlx4_dev *dev)
1629{
1630 struct mlx4_priv *priv = mlx4_priv(dev);
1631
1632 priv->clock_mapping =
872bf2fb
YH		 1633 ioremap(pci_resource_start(dev->persist->pdev,
1634 priv->fw.clock_bar) +
ddd8a6c1
EE		 1635 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1636
1637 if (!priv->clock_mapping)
1638 return -ENOMEM;
1639
1640 return 0;
1641}
1642
1643static void unmap_internal_clock(struct mlx4_dev *dev)
1644{
1645 struct mlx4_priv *priv = mlx4_priv(dev);
1646
1647 if (priv->clock_mapping)
1648 iounmap(priv->clock_mapping);
1649}
1650
225c7b1f
RD		 1651static void mlx4_close_hca(struct mlx4_dev *dev)
1652{
ddd8a6c1 1653 unmap_internal_clock(dev);
c1b43dca 1654 unmap_bf_area(dev);
ab9c17a0
JM		 1655 if (mlx4_is_slave(dev))
1656 mlx4_slave_exit(dev);
1657 else {
1658 mlx4_CLOSE_HCA(dev, 0);
1659 mlx4_free_icms(dev);
a0eacca9
MB		 1660 }
1661}
1662
1663static void mlx4_close_fw(struct mlx4_dev *dev)
1664{
1665 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1666 mlx4_UNMAP_FA(dev);
1667 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1668 }
1669}
1670
55ad3592
YH		 1671static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1672{
1673#define COMM_CHAN_OFFLINE_OFFSET 0x09
1674
1675 u32 comm_flags;
1676 u32 offline_bit;
1677 unsigned long end;
1678 struct mlx4_priv *priv = mlx4_priv(dev);
1679
1680 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1681 while (time_before(jiffies, end)) {
1682 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1683 MLX4_COMM_CHAN_FLAGS));
1684 offline_bit = (comm_flags &
1685 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1686 if (!offline_bit)
1687 return 0;
1688 /* There are cases as part of AER/Reset flow that PF needs
1689 * around 100 msec to load. We therefore sleep for 100 msec
1690 * to allow other tasks to make use of that CPU during this
1691 * time interval.
1692 */
1693 msleep(100);
1694 }
1695 mlx4_err(dev, "Communication channel is offline.\n");
1696 return -EIO;
1697}
1698
1699static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1700{
1701#define COMM_CHAN_RST_OFFSET 0x1e
1702
1703 struct mlx4_priv *priv = mlx4_priv(dev);
1704 u32 comm_rst;
1705 u32 comm_caps;
1706
1707 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1708 MLX4_COMM_CHAN_CAPS));
1709 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1710
1711 if (comm_rst)
1712 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1713}
1714
ab9c17a0
JM		 1715static int mlx4_init_slave(struct mlx4_dev *dev)
1716{
1717 struct mlx4_priv *priv = mlx4_priv(dev);
1718 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1719 int ret_from_reset = 0;
1720 u32 slave_read;
1721 u32 cmd_channel_ver;
1722
97989356 1723 if (atomic_read(&pf_loading)) {
1a91de28 1724 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 1725 return -EPROBE_DEFER;
1726 }
1727
f3d4c89e 1728 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1729 priv->cmd.max_cmds = 1;
55ad3592
YH		 1730 if (mlx4_comm_check_offline(dev)) {
1731 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1732 goto err_offline;
1733 }
1734
1735 mlx4_reset_vf_support(dev);
ab9c17a0
JM		 1736 mlx4_warn(dev, "Sending reset\n");
1737 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
0cd93027 1738 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
ab9c17a0
JM		 1739 /* if we are in the middle of flr the slave will try
1740 * NUM_OF_RESET_RETRIES times before leaving.*/
1741 if (ret_from_reset) {
1742 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 1743 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 1744 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1745 return -EPROBE_DEFER;
ab9c17a0
JM		 1746 } else
1747 goto err;
1748 }
1749
1750 /* check the driver version - the slave I/F revision
1751 * must match the master's */
1752 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1753 cmd_channel_ver = mlx4_comm_get_version();
1754
1755 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1756 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 1757 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 1758 goto err;
1759 }
1760
1761 mlx4_warn(dev, "Sending vhcr0\n");
1762 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
0cd93027 1763 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 1764 goto err;
1765 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
0cd93027 1766 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 1767 goto err;
1768 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
0cd93027 1769 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 1770 goto err;
0cd93027
YH		 1771 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1772 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 1773 goto err;
f3d4c89e
RD		 1774
1775 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1776 return 0;
1777
1778err:
0cd93027 1779 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
55ad3592 1780err_offline:
f3d4c89e 1781 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1782 return -EIO;
225c7b1f
RD		 1783}
1784
6634961c
JM		 1785static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1786{
1787 int i;
1788
1789 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1790 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1791 dev->caps.gid_table_len[i] =
449fc488 1792 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1793 else
1794 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1795 dev->caps.pkey_table_len[i] =
1796 dev->phys_caps.pkey_phys_table_len[i] - 1;
1797 }
1798}
1799
3c439b55
JM		 1800static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1801{
1802 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1803
1804 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1805 i++) {
1806 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1807 break;
1808 }
1809
1810 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1811}
1812
7d077cd3
MB		 1813static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
1814{
1815 switch (dmfs_high_steer_mode) {
1816 case MLX4_STEERING_DMFS_A0_DEFAULT:
1817 return "default performance";
1818
1819 case MLX4_STEERING_DMFS_A0_DYNAMIC:
1820 return "dynamic hybrid mode";
1821
1822 case MLX4_STEERING_DMFS_A0_STATIC:
1823 return "performance optimized for limited rule configuration (static)";
1824
1825 case MLX4_STEERING_DMFS_A0_DISABLE:
1826 return "disabled performance optimized steering";
1827
1828 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
1829 return "performance optimized steering not supported";
1830
1831 default:
1832 return "Unrecognized mode";
1833 }
1834}
1835
1836#define MLX4_DMFS_A0_STEERING (1UL << 2)
1837
7b8157be
JM		 1838static void choose_steering_mode(struct mlx4_dev *dev,
1839 struct mlx4_dev_cap *dev_cap)
1840{
7d077cd3
MB		 1841 if (mlx4_log_num_mgm_entry_size <= 0) {
1842 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
1843 if (dev->caps.dmfs_high_steer_mode ==
1844 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1845 mlx4_err(dev, "DMFS high rate mode not supported\n");
1846 else
1847 dev->caps.dmfs_high_steer_mode =
1848 MLX4_STEERING_DMFS_A0_STATIC;
1849 }
1850 }
1851
1852 if (mlx4_log_num_mgm_entry_size <= 0 &&
3c439b55 1853 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1854 (!mlx4_is_mfunc(dev) ||
872bf2fb
YH		 1855 (dev_cap->fs_max_num_qp_per_entry >=
1856 (dev->persist->num_vfs + 1))) &&
3c439b55
JM		 1857 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1858 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1859 dev->oper_log_mgm_entry_size =
1860 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1861 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1862 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1863 dev->caps.fs_log_max_ucast_qp_range_size =
1864 dev_cap->fs_log_max_ucast_qp_range_size;
1865 } else {
7d077cd3
MB		 1866 if (dev->caps.dmfs_high_steer_mode !=
1867 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1868 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
7b8157be
JM		 1869 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1870 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1871 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1872 else {
1873 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1874
1875 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1876 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 1877 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 1878 }
3c439b55
JM		 1879 dev->oper_log_mgm_entry_size =
1880 mlx4_log_num_mgm_entry_size > 0 ?
1881 mlx4_log_num_mgm_entry_size :
1882 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1883 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1884 }
1a91de28 1885 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 1886 mlx4_steering_mode_str(dev->caps.steering_mode),
1887 dev->oper_log_mgm_entry_size,
1888 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1889}
1890
7ffdf726
OG		 1891static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1892 struct mlx4_dev_cap *dev_cap)
1893{
1894 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
5eff6dad 1895 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
7ffdf726
OG		 1896 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1897 else
1898 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1899
1900 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1901 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1902}
1903
7d077cd3
MB		 1904static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
1905{
1906 int i;
1907 struct mlx4_port_cap port_cap;
1908
1909 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1910 return -EINVAL;
1911
1912 for (i = 1; i <= dev->caps.num_ports; i++) {
1913 if (mlx4_dev_port(dev, i, &port_cap)) {
1914 mlx4_err(dev,
1915 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
1916 } else if ((dev->caps.dmfs_high_steer_mode !=
1917 MLX4_STEERING_DMFS_A0_DEFAULT) &&
1918 (port_cap.dmfs_optimized_state ==
1919 !!(dev->caps.dmfs_high_steer_mode ==
1920 MLX4_STEERING_DMFS_A0_DISABLE))) {
1921 mlx4_err(dev,
1922 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
1923 dmfs_high_rate_steering_mode_str(
1924 dev->caps.dmfs_high_steer_mode),
1925 (port_cap.dmfs_optimized_state ?
1926 "enabled" : "disabled"));
1927 }
1928 }
1929
1930 return 0;
1931}
1932
a0eacca9 1933static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 1934{
2d928651 1935 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 1936 int err = 0;
225c7b1f 1937
ab9c17a0
JM		 1938 if (!mlx4_is_slave(dev)) {
1939 err = mlx4_QUERY_FW(dev);
1940 if (err) {
1941 if (err == -EACCES)
1a91de28 1942 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 1943 else
1a91de28 1944 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 1945 return err;
ab9c17a0 1946 }
225c7b1f 1947
ab9c17a0
JM		 1948 err = mlx4_load_fw(dev);
1949 if (err) {
1a91de28 1950 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 1951 return err;
ab9c17a0 1952 }
225c7b1f 1953
ab9c17a0
JM		 1954 mlx4_cfg.log_pg_sz_m = 1;
1955 mlx4_cfg.log_pg_sz = 0;
1956 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1957 if (err)
1958 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 1959 }
2d928651 1960
a0eacca9
MB		 1961 return err;
1962}
1963
1964static int mlx4_init_hca(struct mlx4_dev *dev)
1965{
1966 struct mlx4_priv *priv = mlx4_priv(dev);
1967 struct mlx4_adapter adapter;
1968 struct mlx4_dev_cap dev_cap;
1969 struct mlx4_profile profile;
1970 struct mlx4_init_hca_param init_hca;
1971 u64 icm_size;
1972 struct mlx4_config_dev_params params;
1973 int err;
1974
1975 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1976 err = mlx4_dev_cap(dev, &dev_cap);
1977 if (err) {
1a91de28 1978 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
d0d01250 1979 return err;
ab9c17a0 1980 }
225c7b1f 1981
7b8157be 1982 choose_steering_mode(dev, &dev_cap);
7ffdf726 1983 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1984
7d077cd3
MB		 1985 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
1986 mlx4_is_master(dev))
1987 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
1988
8e1a28e8
HHZ		 1989 err = mlx4_get_phys_port_id(dev);
1990 if (err)
1991 mlx4_err(dev, "Fail to get physical port id\n");
1992
6634961c
JM		 1993 if (mlx4_is_master(dev))
1994 mlx4_parav_master_pf_caps(dev);
1995
2599d858
AV		 1996 if (mlx4_low_memory_profile()) {
1997 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
1998 profile = low_mem_profile;
1999 } else {
2000 profile = default_profile;
2001 }
0ff1fb65
HHZ		 2002 if (dev->caps.steering_mode ==
2003 MLX4_STEERING_MODE_DEVICE_MANAGED)
2004 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 2005
ab9c17a0
JM		 2006 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2007 &init_hca);
2008 if ((long long) icm_size < 0) {
2009 err = icm_size;
d0d01250 2010 return err;
ab9c17a0 2011 }
225c7b1f 2012
a5bbe892
EC		 2013 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2014
ab9c17a0
JM		 2015 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2016 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 2017 init_hca.mw_enabled = 0;
2018 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2019 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2020 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 2021
ab9c17a0
JM		 2022 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2023 if (err)
d0d01250 2024 return err;
225c7b1f 2025
ab9c17a0
JM		 2026 err = mlx4_INIT_HCA(dev, &init_hca);
2027 if (err) {
1a91de28 2028 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 2029 goto err_free_icm;
2030 }
7ae0e400
MB		 2031
2032 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2033 err = mlx4_query_func(dev, &dev_cap);
2034 if (err < 0) {
2035 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
d0d01250 2036 goto err_close;
7ae0e400
MB		 2037 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2038 dev->caps.num_eqs = dev_cap.max_eqs;
2039 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2040 dev->caps.reserved_uars = dev_cap.reserved_uars;
2041 }
2042 }
2043
ddd8a6c1
EE		 2044 /*
2045 * If TS is supported by FW
2046 * read HCA frequency by QUERY_HCA command
2047 */
2048 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2049 memset(&init_hca, 0, sizeof(init_hca));
2050 err = mlx4_QUERY_HCA(dev, &init_hca);
2051 if (err) {
1a91de28 2052 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 2053 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2054 } else {
2055 dev->caps.hca_core_clock =
2056 init_hca.hca_core_clock;
2057 }
2058
2059 /* In case we got HCA frequency 0 - disable timestamping
2060 * to avoid dividing by zero
2061 */
2062 if (!dev->caps.hca_core_clock) {
2063 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2064 mlx4_err(dev,
1a91de28 2065 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 2066 } else if (map_internal_clock(dev)) {
2067 /*
2068 * Map internal clock,
2069 * in case of failure disable timestamping
2070 */
2071 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 2072 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 2073 }
2074 }
7d077cd3
MB		 2075
2076 if (dev->caps.dmfs_high_steer_mode !=
2077 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2078 if (mlx4_validate_optimized_steering(dev))
2079 mlx4_warn(dev, "Optimized steering validation failed\n");
2080
2081 if (dev->caps.dmfs_high_steer_mode ==
2082 MLX4_STEERING_DMFS_A0_DISABLE) {
2083 dev->caps.dmfs_high_rate_qpn_base =
2084 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2085 dev->caps.dmfs_high_rate_qpn_range =
2086 MLX4_A0_STEERING_TABLE_SIZE;
2087 }
2088
2089 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2090 dmfs_high_rate_steering_mode_str(
2091 dev->caps.dmfs_high_steer_mode));
2092 }
ab9c17a0
JM		 2093 } else {
2094 err = mlx4_init_slave(dev);
2095 if (err) {
5efe5355
JM		 2096 if (err != -EPROBE_DEFER)
2097 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 2098 return err;
ab9c17a0 2099 }
225c7b1f 2100
ab9c17a0
JM		 2101 err = mlx4_slave_cap(dev);
2102 if (err) {
2103 mlx4_err(dev, "Failed to obtain slave caps\n");
2104 goto err_close;
2105 }
225c7b1f
RD		 2106 }
2107
ab9c17a0
JM		 2108 if (map_bf_area(dev))
2109 mlx4_dbg(dev, "Failed to map blue flame area\n");
2110
2111 /*Only the master set the ports, all the rest got it from it.*/
2112 if (!mlx4_is_slave(dev))
2113 mlx4_set_port_mask(dev);
2114
225c7b1f
RD		 2115 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2116 if (err) {
1a91de28 2117 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 2118 goto unmap_bf;
225c7b1f
RD		 2119 }
2120
f8c6455b
SM		 2121 /* Query CONFIG_DEV parameters */
2122 err = mlx4_config_dev_retrieval(dev, &params);
2123 if (err && err != -ENOTSUPP) {
2124 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2125 } else if (!err) {
2126 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2127 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2128 }
225c7b1f 2129 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 2130 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 2131
2132 return 0;
2133
bef772eb 2134unmap_bf:
ddd8a6c1 2135 unmap_internal_clock(dev);
bef772eb
AY		 2136 unmap_bf_area(dev);
2137
b38f2879 2138 if (mlx4_is_slave(dev)) {
99ec41d0 2139 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2140 kfree(dev->caps.qp0_tunnel);
2141 kfree(dev->caps.qp0_proxy);
2142 kfree(dev->caps.qp1_tunnel);
2143 kfree(dev->caps.qp1_proxy);
2144 }
2145
225c7b1f 2146err_close:
41929ed2
DB		 2147 if (mlx4_is_slave(dev))
2148 mlx4_slave_exit(dev);
2149 else
2150 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 2151
2152err_free_icm:
ab9c17a0
JM		 2153 if (!mlx4_is_slave(dev))
2154 mlx4_free_icms(dev);
225c7b1f 2155
225c7b1f
RD		 2156 return err;
2157}
2158
f2a3f6a3
OG		 2159static int mlx4_init_counters_table(struct mlx4_dev *dev)
2160{
2161 struct mlx4_priv *priv = mlx4_priv(dev);
2162 int nent;
2163
2164 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2165 return -ENOENT;
2166
2167 nent = dev->caps.max_counters;
2168 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
2169}
2170
2171static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2172{
2173 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2174}
2175
ba062d52 2176int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 2177{
2178 struct mlx4_priv *priv = mlx4_priv(dev);
2179
2180 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2181 return -ENOENT;
2182
2183 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2184 if (*idx == -1)
2185 return -ENOMEM;
2186
2187 return 0;
2188}
ba062d52
JM		 2189
2190int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2191{
2192 u64 out_param;
2193 int err;
2194
2195 if (mlx4_is_mfunc(dev)) {
2196 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2197 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2198 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2199 if (!err)
2200 *idx = get_param_l(&out_param);
2201
2202 return err;
2203 }
2204 return __mlx4_counter_alloc(dev, idx);
2205}
f2a3f6a3
OG		 2206EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2207
ba062d52 2208void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 2209{
7c6d74d2 2210 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 2211 return;
2212}
ba062d52
JM		 2213
2214void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2215{
e7dbeba8 2216 u64 in_param = 0;
ba062d52
JM		 2217
2218 if (mlx4_is_mfunc(dev)) {
2219 set_param_l(&in_param, idx);
2220 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2221 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2222 MLX4_CMD_WRAPPED);
2223 return;
2224 }
2225 __mlx4_counter_free(dev, idx);
2226}
f2a3f6a3
OG		 2227EXPORT_SYMBOL_GPL(mlx4_counter_free);
2228
3d73c288 2229static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 2230{
2231 struct mlx4_priv *priv = mlx4_priv(dev);
2232 int err;
7ff93f8b 2233 int port;
9a5aa622 2234 __be32 ib_port_default_caps;
225c7b1f 2235
225c7b1f
RD		 2236 err = mlx4_init_uar_table(dev);
2237 if (err) {
1a91de28
JP		 2238 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2239 return err;
225c7b1f
RD		 2240 }
2241
2242 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2243 if (err) {
1a91de28 2244 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 2245 goto err_uar_table_free;
2246 }
2247
4979d18f 2248 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 2249 if (!priv->kar) {
1a91de28 2250 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 2251 err = -ENOMEM;
2252 goto err_uar_free;
2253 }
2254
2255 err = mlx4_init_pd_table(dev);
2256 if (err) {
1a91de28 2257 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2258 goto err_kar_unmap;
2259 }
2260
012a8ff5
SH		 2261 err = mlx4_init_xrcd_table(dev);
2262 if (err) {
1a91de28 2263 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2264 goto err_pd_table_free;
2265 }
2266
225c7b1f
RD		 2267 err = mlx4_init_mr_table(dev);
2268 if (err) {
1a91de28 2269 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2270 goto err_xrcd_table_free;
225c7b1f
RD		 2271 }
2272
fe6f700d
YP		 2273 if (!mlx4_is_slave(dev)) {
2274 err = mlx4_init_mcg_table(dev);
2275 if (err) {
1a91de28 2276 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2277 goto err_mr_table_free;
2278 }
114840c3
JM		 2279 err = mlx4_config_mad_demux(dev);
2280 if (err) {
2281 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2282 goto err_mcg_table_free;
2283 }
fe6f700d
YP		 2284 }
2285
225c7b1f
RD		 2286 err = mlx4_init_eq_table(dev);
2287 if (err) {
1a91de28 2288 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2289 goto err_mcg_table_free;
225c7b1f
RD		 2290 }
2291
2292 err = mlx4_cmd_use_events(dev);
2293 if (err) {
1a91de28 2294 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2295 goto err_eq_table_free;
2296 }
2297
2298 err = mlx4_NOP(dev);
2299 if (err) {
08fb1055 2300 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2301 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
b8dd786f 2302 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1a91de28 2303 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2304 } else {
1a91de28 2305 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
b8dd786f 2306 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 2307 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2308 }
225c7b1f
RD		 2309
2310 goto err_cmd_poll;
2311 }
2312
2313 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2314
2315 err = mlx4_init_cq_table(dev);
2316 if (err) {
1a91de28 2317 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2318 goto err_cmd_poll;
2319 }
2320
2321 err = mlx4_init_srq_table(dev);
2322 if (err) {
1a91de28 2323 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2324 goto err_cq_table_free;
2325 }
2326
2327 err = mlx4_init_qp_table(dev);
2328 if (err) {
1a91de28 2329 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2330 goto err_srq_table_free;
2331 }
2332
f2a3f6a3
OG		 2333 err = mlx4_init_counters_table(dev);
2334 if (err && err != -ENOENT) {
1a91de28 2335 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
fe6f700d 2336 goto err_qp_table_free;
f2a3f6a3
OG		 2337 }
2338
ab9c17a0
JM		 2339 if (!mlx4_is_slave(dev)) {
2340 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2341 ib_port_default_caps = 0;
2342 err = mlx4_get_port_ib_caps(dev, port,
2343 &ib_port_default_caps);
2344 if (err)
1a91de28
JP		 2345 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2346 port, err);
ab9c17a0
JM		 2347 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2348
2aca1172
JM		 2349 /* initialize per-slave default ib port capabilities */
2350 if (mlx4_is_master(dev)) {
2351 int i;
2352 for (i = 0; i < dev->num_slaves; i++) {
2353 if (i == mlx4_master_func_num(dev))
2354 continue;
2355 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2356 ib_port_default_caps;
2aca1172
JM		 2357 }
2358 }
2359
096335b3
OG		 2360 if (mlx4_is_mfunc(dev))
2361 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2362 else
2363 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2364
6634961c
JM		 2365 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2366 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2367 if (err) {
2368 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2369 port);
ab9c17a0
JM		 2370 goto err_counters_table_free;
2371 }
7ff93f8b
YP		 2372 }
2373 }
2374
225c7b1f
RD		 2375 return 0;
2376
f2a3f6a3
OG		 2377err_counters_table_free:
2378 mlx4_cleanup_counters_table(dev);
2379
225c7b1f
RD		 2380err_qp_table_free:
2381 mlx4_cleanup_qp_table(dev);
2382
2383err_srq_table_free:
2384 mlx4_cleanup_srq_table(dev);
2385
2386err_cq_table_free:
2387 mlx4_cleanup_cq_table(dev);
2388
2389err_cmd_poll:
2390 mlx4_cmd_use_polling(dev);
2391
2392err_eq_table_free:
2393 mlx4_cleanup_eq_table(dev);
2394
fe6f700d
YP		 2395err_mcg_table_free:
2396 if (!mlx4_is_slave(dev))
2397 mlx4_cleanup_mcg_table(dev);
2398
ee49bd93 2399err_mr_table_free:
225c7b1f
RD		 2400 mlx4_cleanup_mr_table(dev);
2401
012a8ff5
SH		 2402err_xrcd_table_free:
2403 mlx4_cleanup_xrcd_table(dev);
2404
225c7b1f
RD		 2405err_pd_table_free:
2406 mlx4_cleanup_pd_table(dev);
2407
2408err_kar_unmap:
2409 iounmap(priv->kar);
2410
2411err_uar_free:
2412 mlx4_uar_free(dev, &priv->driver_uar);
2413
2414err_uar_table_free:
2415 mlx4_cleanup_uar_table(dev);
2416 return err;
2417}
2418
e8f9b2ed 2419static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2420{
2421 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2422 struct msix_entry *entries;
225c7b1f
RD		 2423 int i;
2424
2425 if (msi_x) {
7ae0e400
MB		 2426 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ;
2427
ca4c7b35
OG		 2428 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2429 nreq);
ab9c17a0 2430
b8dd786f
YP		 2431 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2432 if (!entries)
2433 goto no_msi;
2434
2435 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2436 entries[i].entry = i;
2437
872bf2fb
YH		 2438 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2439 nreq);
66e2f9c1
AG		 2440
2441 if (nreq < 0) {
5bf0da7d 2442 kfree(entries);
225c7b1f 2443 goto no_msi;
66e2f9c1 2444 } else if (nreq < MSIX_LEGACY_SZ +
1a91de28 2445 dev->caps.num_ports * MIN_MSIX_P_PORT) {
0b7ca5a9
YP		 2446 /*Working in legacy mode , all EQ's shared*/
2447 dev->caps.comp_pool = 0;
2448 dev->caps.num_comp_vectors = nreq - 1;
2449 } else {
2450 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2451 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2452 }
b8dd786f 2453 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2454 priv->eq_table.eq[i].irq = entries[i].vector;
2455
2456 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2457
2458 kfree(entries);
225c7b1f
RD		 2459 return;
2460 }
2461
2462no_msi:
b8dd786f 2463 dev->caps.num_comp_vectors = 1;
0b7ca5a9 2464 dev->caps.comp_pool = 0;
b8dd786f
YP		 2465
2466 for (i = 0; i < 2; ++i)
872bf2fb 2467 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
225c7b1f
RD		 2468}
2469
7ff93f8b 2470static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2471{
2472 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2473 int err = 0;
2a2336f8
YP		 2474
2475 info->dev = dev;
2476 info->port = port;
ab9c17a0 2477 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2478 mlx4_init_mac_table(dev, &info->mac_table);
2479 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2480 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2481 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2482 }
7ff93f8b
YP		 2483
2484 sprintf(info->dev_name, "mlx4_port%d", port);
2485 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2486 if (mlx4_is_mfunc(dev))
2487 info->port_attr.attr.mode = S_IRUGO;
2488 else {
2489 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2490 info->port_attr.store = set_port_type;
2491 }
7ff93f8b 2492 info->port_attr.show = show_port_type;
3691c964 2493 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b 2494
872bf2fb 2495 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
7ff93f8b
YP		 2496 if (err) {
2497 mlx4_err(dev, "Failed to create file for port %d\n", port);
2498 info->port = -1;
2499 }
2500
096335b3
OG		 2501 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2502 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2503 if (mlx4_is_mfunc(dev))
2504 info->port_mtu_attr.attr.mode = S_IRUGO;
2505 else {
2506 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2507 info->port_mtu_attr.store = set_port_ib_mtu;
2508 }
2509 info->port_mtu_attr.show = show_port_ib_mtu;
2510 sysfs_attr_init(&info->port_mtu_attr.attr);
2511
872bf2fb
YH		 2512 err = device_create_file(&dev->persist->pdev->dev,
2513 &info->port_mtu_attr);
096335b3
OG		 2514 if (err) {
2515 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
872bf2fb
YH		 2516 device_remove_file(&info->dev->persist->pdev->dev,
2517 &info->port_attr);
096335b3
OG		 2518 info->port = -1;
2519 }
2520
7ff93f8b
YP		 2521 return err;
2522}
2523
2524static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2525{
2526 if (info->port < 0)
2527 return;
2528
872bf2fb
YH		 2529 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2530 device_remove_file(&info->dev->persist->pdev->dev,
2531 &info->port_mtu_attr);
2a2336f8
YP		 2532}
2533
b12d93d6
YP		 2534static int mlx4_init_steering(struct mlx4_dev *dev)
2535{
2536 struct mlx4_priv *priv = mlx4_priv(dev);
2537 int num_entries = dev->caps.num_ports;
2538 int i, j;
2539
2540 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2541 if (!priv->steer)
2542 return -ENOMEM;
2543
45b51365 2544 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2545 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2546 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2547 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2548 }
b12d93d6
YP		 2549 return 0;
2550}
2551
2552static void mlx4_clear_steering(struct mlx4_dev *dev)
2553{
2554 struct mlx4_priv *priv = mlx4_priv(dev);
2555 struct mlx4_steer_index *entry, *tmp_entry;
2556 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2557 int num_entries = dev->caps.num_ports;
2558 int i, j;
2559
2560 for (i = 0; i < num_entries; i++) {
2561 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2562 list_for_each_entry_safe(pqp, tmp_pqp,
2563 &priv->steer[i].promisc_qps[j],
2564 list) {
2565 list_del(&pqp->list);
2566 kfree(pqp);
2567 }
2568 list_for_each_entry_safe(entry, tmp_entry,
2569 &priv->steer[i].steer_entries[j],
2570 list) {
2571 list_del(&entry->list);
2572 list_for_each_entry_safe(pqp, tmp_pqp,
2573 &entry->duplicates,
2574 list) {
2575 list_del(&pqp->list);
2576 kfree(pqp);
2577 }
2578 kfree(entry);
2579 }
2580 }
2581 }
2582 kfree(priv->steer);
2583}
2584
ab9c17a0
JM		 2585static int extended_func_num(struct pci_dev *pdev)
2586{
2587 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2588}
2589
2590#define MLX4_OWNER_BASE 0x8069c
2591#define MLX4_OWNER_SIZE 4
2592
2593static int mlx4_get_ownership(struct mlx4_dev *dev)
2594{
2595 void __iomem *owner;
2596 u32 ret;
2597
872bf2fb 2598 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 2599 return -EIO;
2600
872bf2fb
YH		 2601 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2602 MLX4_OWNER_BASE,
ab9c17a0
JM		 2603 MLX4_OWNER_SIZE);
2604 if (!owner) {
2605 mlx4_err(dev, "Failed to obtain ownership bit\n");
2606 return -ENOMEM;
2607 }
2608
2609 ret = readl(owner);
2610 iounmap(owner);
2611 return (int) !!ret;
2612}
2613
2614static void mlx4_free_ownership(struct mlx4_dev *dev)
2615{
2616 void __iomem *owner;
2617
872bf2fb 2618 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 2619 return;
2620
872bf2fb
YH		 2621 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2622 MLX4_OWNER_BASE,
ab9c17a0
JM		 2623 MLX4_OWNER_SIZE);
2624 if (!owner) {
2625 mlx4_err(dev, "Failed to obtain ownership bit\n");
2626 return;
2627 }
2628 writel(0, owner);
2629 msleep(1000);
2630 iounmap(owner);
2631}
2632
a0eacca9
MB		 2633#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2634 !!((flags) & MLX4_FLAG_MASTER))
2635
2636static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
55ad3592 2637 u8 total_vfs, int existing_vfs, int reset_flow)
a0eacca9
MB		 2638{
2639 u64 dev_flags = dev->flags;
da315679 2640 int err = 0;
a0eacca9 2641
55ad3592
YH		 2642 if (reset_flow) {
2643 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
2644 GFP_KERNEL);
2645 if (!dev->dev_vfs)
2646 goto free_mem;
2647 return dev_flags;
2648 }
2649
da315679
MB		 2650 atomic_inc(&pf_loading);
2651 if (dev->flags & MLX4_FLAG_SRIOV) {
2652 if (existing_vfs != total_vfs) {
2653 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2654 existing_vfs, total_vfs);
2655 total_vfs = existing_vfs;
2656 }
2657 }
2658
2659 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
a0eacca9
MB		 2660 if (NULL == dev->dev_vfs) {
2661 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2662 goto disable_sriov;
da315679
MB		 2663 }
2664
2665 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
2666 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2667 err = pci_enable_sriov(pdev, total_vfs);
2668 }
2669 if (err) {
2670 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2671 err);
2672 goto disable_sriov;
2673 } else {
2674 mlx4_warn(dev, "Running in master mode\n");
2675 dev_flags |= MLX4_FLAG_SRIOV |
2676 MLX4_FLAG_MASTER;
2677 dev_flags &= ~MLX4_FLAG_SLAVE;
872bf2fb 2678 dev->persist->num_vfs = total_vfs;
a0eacca9
MB		 2679 }
2680 return dev_flags;
2681
2682disable_sriov:
da315679 2683 atomic_dec(&pf_loading);
55ad3592 2684free_mem:
872bf2fb 2685 dev->persist->num_vfs = 0;
a0eacca9
MB		 2686 kfree(dev->dev_vfs);
2687 return dev_flags & ~MLX4_FLAG_MASTER;
2688}
2689
de966c59
MB		 2690enum {
2691 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2692};
2693
2694static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
2695 int *nvfs)
2696{
2697 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
2698 /* Checking for 64 VFs as a limitation of CX2 */
2699 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
2700 requested_vfs >= 64) {
2701 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
2702 requested_vfs);
2703 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
2704 }
2705 return 0;
2706}
2707
e1c00e10 2708static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
55ad3592
YH		 2709 int total_vfs, int *nvfs, struct mlx4_priv *priv,
2710 int reset_flow)
225c7b1f 2711{
225c7b1f 2712 struct mlx4_dev *dev;
e1c00e10 2713 unsigned sum = 0;
225c7b1f 2714 int err;
2a2336f8 2715 int port;
e1c00e10 2716 int i;
7ae0e400 2717 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 2718 int existing_vfs = 0;
225c7b1f 2719
e1c00e10 2720 dev = &priv->dev;
225c7b1f 2721
b581401e
RD		 2722 INIT_LIST_HEAD(&priv->ctx_list);
2723 spin_lock_init(&priv->ctx_lock);
225c7b1f 2724
7ff93f8b 2725 mutex_init(&priv->port_mutex);
53f33ae2 2726 mutex_init(&priv->bond_mutex);
7ff93f8b 2727
6296883c
YP		 2728 INIT_LIST_HEAD(&priv->pgdir_list);
2729 mutex_init(&priv->pgdir_mutex);
2730
c1b43dca
EC		 2731 INIT_LIST_HEAD(&priv->bf_list);
2732 mutex_init(&priv->bf_mutex);
2733
aca7a3ac 2734 dev->rev_id = pdev->revision;
6e7136ed 2735 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 2736
ab9c17a0 2737 /* Detect if this device is a virtual function */
839f1243 2738 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2739 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2740 dev->flags |= MLX4_FLAG_SLAVE;
2741 } else {
2742 /* We reset the device and enable SRIOV only for physical
2743 * devices. Try to claim ownership on the device;
2744 * if already taken, skip -- do not allow multiple PFs */
2745 err = mlx4_get_ownership(dev);
2746 if (err) {
2747 if (err < 0)
e1c00e10 2748 return err;
ab9c17a0 2749 else {
1a91de28 2750 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 2751 return -EINVAL;
ab9c17a0
JM		 2752 }
2753 }
aca7a3ac 2754
fe6f700d
YP		 2755 atomic_set(&priv->opreq_count, 0);
2756 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2757
ab9c17a0
JM		 2758 /*
2759 * Now reset the HCA before we touch the PCI capabilities or
2760 * attempt a firmware command, since a boot ROM may have left
2761 * the HCA in an undefined state.
2762 */
2763 err = mlx4_reset(dev);
2764 if (err) {
1a91de28 2765 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 2766 goto err_sriov;
ab9c17a0 2767 }
7ae0e400
MB		 2768
2769 if (total_vfs) {
7ae0e400 2770 dev->flags = MLX4_FLAG_MASTER;
da315679
MB		 2771 existing_vfs = pci_num_vf(pdev);
2772 if (existing_vfs)
2773 dev->flags |= MLX4_FLAG_SRIOV;
872bf2fb 2774 dev->persist->num_vfs = total_vfs;
7ae0e400 2775 }
225c7b1f
RD		 2776 }
2777
f6bc11e4
YH		 2778 /* on load remove any previous indication of internal error,
2779 * device is up.
2780 */
2781 dev->persist->state = MLX4_DEVICE_STATE_UP;
2782
ab9c17a0 2783slave_start:
521130d1
EE		 2784 err = mlx4_cmd_init(dev);
2785 if (err) {
1a91de28 2786 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 2787 goto err_sriov;
2788 }
2789
2790 /* In slave functions, the communication channel must be initialized
2791 * before posting commands. Also, init num_slaves before calling
2792 * mlx4_init_hca */
2793 if (mlx4_is_mfunc(dev)) {
7ae0e400 2794 if (mlx4_is_master(dev)) {
ab9c17a0 2795 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 2796
2797 } else {
ab9c17a0 2798 dev->num_slaves = 0;
f356fcbe
JM		 2799 err = mlx4_multi_func_init(dev);
2800 if (err) {
1a91de28 2801 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 2802 goto err_cmd;
2803 }
2804 }
225c7b1f
RD		 2805 }
2806
a0eacca9
MB		 2807 err = mlx4_init_fw(dev);
2808 if (err) {
2809 mlx4_err(dev, "Failed to init fw, aborting.\n");
2810 goto err_mfunc;
2811 }
2812
7ae0e400 2813 if (mlx4_is_master(dev)) {
da315679 2814 /* when we hit the goto slave_start below, dev_cap already initialized */
7ae0e400
MB		 2815 if (!dev_cap) {
2816 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
2817
2818 if (!dev_cap) {
2819 err = -ENOMEM;
2820 goto err_fw;
2821 }
2822
2823 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2824 if (err) {
2825 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2826 goto err_fw;
2827 }
2828
de966c59
MB		 2829 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2830 goto err_fw;
2831
7ae0e400 2832 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 2833 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
2834 total_vfs,
2835 existing_vfs,
2836 reset_flow);
7ae0e400
MB		 2837
2838 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2839 dev->flags = dev_flags;
2840 if (!SRIOV_VALID_STATE(dev->flags)) {
2841 mlx4_err(dev, "Invalid SRIOV state\n");
2842 goto err_sriov;
2843 }
2844 err = mlx4_reset(dev);
2845 if (err) {
2846 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2847 goto err_sriov;
2848 }
2849 goto slave_start;
2850 }
2851 } else {
2852 /* Legacy mode FW requires SRIOV to be enabled before
2853 * doing QUERY_DEV_CAP, since max_eq's value is different if
2854 * SRIOV is enabled.
2855 */
2856 memset(dev_cap, 0, sizeof(*dev_cap));
2857 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2858 if (err) {
2859 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2860 goto err_fw;
2861 }
de966c59
MB		 2862
2863 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2864 goto err_fw;
7ae0e400
MB		 2865 }
2866 }
2867
225c7b1f 2868 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2869 if (err) {
2870 if (err == -EACCES) {
2871 /* Not primary Physical function
2872 * Running in slave mode */
ffc39f6d 2873 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 2874 /* We're not a PF */
2875 if (dev->flags & MLX4_FLAG_SRIOV) {
2876 if (!existing_vfs)
2877 pci_disable_sriov(pdev);
55ad3592 2878 if (mlx4_is_master(dev) && !reset_flow)
a0eacca9
MB		 2879 atomic_dec(&pf_loading);
2880 dev->flags &= ~MLX4_FLAG_SRIOV;
2881 }
2882 if (!mlx4_is_slave(dev))
2883 mlx4_free_ownership(dev);
ab9c17a0
JM		 2884 dev->flags |= MLX4_FLAG_SLAVE;
2885 dev->flags &= ~MLX4_FLAG_MASTER;
2886 goto slave_start;
2887 } else
a0eacca9 2888 goto err_fw;
ab9c17a0
JM		 2889 }
2890
7ae0e400 2891 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 2892 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
2893 existing_vfs, reset_flow);
7ae0e400
MB		 2894
2895 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
2896 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
2897 dev->flags = dev_flags;
2898 err = mlx4_cmd_init(dev);
2899 if (err) {
2900 /* Only VHCR is cleaned up, so could still
2901 * send FW commands
2902 */
2903 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
2904 goto err_close;
2905 }
2906 } else {
2907 dev->flags = dev_flags;
2908 }
2909
2910 if (!SRIOV_VALID_STATE(dev->flags)) {
2911 mlx4_err(dev, "Invalid SRIOV state\n");
2912 goto err_close;
2913 }
2914 }
2915
b912b2f8
EP		 2916 /* check if the device is functioning at its maximum possible speed.
2917 * No return code for this call, just warn the user in case of PCI
2918 * express device capabilities are under-satisfied by the bus.
2919 */
83d3459a
EP		 2920 if (!mlx4_is_slave(dev))
2921 mlx4_check_pcie_caps(dev);
b912b2f8 2922
ab9c17a0
JM		 2923 /* In master functions, the communication channel must be initialized
2924 * after obtaining its address from fw */
2925 if (mlx4_is_master(dev)) {
e1c00e10
MD		 2926 int ib_ports = 0;
2927
2928 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2929 ib_ports++;
2930
2931 if (ib_ports &&
2932 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2933 mlx4_err(dev,
2934 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2935 err = -EINVAL;
2936 goto err_close;
2937 }
2938 if (dev->caps.num_ports < 2 &&
2939 num_vfs_argc > 1) {
2940 err = -EINVAL;
2941 mlx4_err(dev,
2942 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2943 dev->caps.num_ports);
ab9c17a0
JM		 2944 goto err_close;
2945 }
872bf2fb 2946 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
dd41cc3b 2947
872bf2fb
YH		 2948 for (i = 0;
2949 i < sizeof(dev->persist->nvfs)/
2950 sizeof(dev->persist->nvfs[0]); i++) {
e1c00e10
MD		 2951 unsigned j;
2952
872bf2fb 2953 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
e1c00e10
MD		 2954 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
2955 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2956 dev->caps.num_ports;
1ab95d37
MB		 2957 }
2958 }
e1c00e10
MD		 2959
2960 /* In master functions, the communication channel
2961 * must be initialized after obtaining its address from fw
2962 */
2963 err = mlx4_multi_func_init(dev);
2964 if (err) {
2965 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
2966 goto err_close;
2967 }
ab9c17a0 2968 }
225c7b1f 2969
b8dd786f
YP		 2970 err = mlx4_alloc_eq_table(dev);
2971 if (err)
ab9c17a0 2972 goto err_master_mfunc;
b8dd786f 2973
0b7ca5a9 2974 priv->msix_ctl.pool_bm = 0;
730c41d5 2975 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2976
08fb1055 2977 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2978 if ((mlx4_is_mfunc(dev)) &&
2979 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2980 err = -ENOSYS;
1a91de28 2981 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 2982 goto err_free_eq;
ab9c17a0
JM		 2983 }
2984
2985 if (!mlx4_is_slave(dev)) {
2986 err = mlx4_init_steering(dev);
2987 if (err)
e1c00e10 2988 goto err_disable_msix;
ab9c17a0 2989 }
b12d93d6 2990
225c7b1f 2991 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2992 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2993 !mlx4_is_mfunc(dev)) {
08fb1055 2994 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2995 dev->caps.num_comp_vectors = 1;
2996 dev->caps.comp_pool = 0;
08fb1055
MT		 2997 pci_disable_msix(pdev);
2998 err = mlx4_setup_hca(dev);
2999 }
3000
225c7b1f 3001 if (err)
b12d93d6 3002 goto err_steer;
225c7b1f 3003
5a0d0a61 3004 mlx4_init_quotas(dev);
55ad3592
YH		 3005 /* When PF resources are ready arm its comm channel to enable
3006 * getting commands
3007 */
3008 if (mlx4_is_master(dev)) {
3009 err = mlx4_ARM_COMM_CHANNEL(dev);
3010 if (err) {
3011 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3012 err);
3013 goto err_steer;
3014 }
3015 }
5a0d0a61 3016
7ff93f8b
YP		 3017 for (port = 1; port <= dev->caps.num_ports; port++) {
3018 err = mlx4_init_port_info(dev, port);
3019 if (err)
3020 goto err_port;
3021 }
2a2336f8 3022
53f33ae2
MS		 3023 priv->v2p.port1 = 1;
3024 priv->v2p.port2 = 2;
3025
225c7b1f
RD		 3026 err = mlx4_register_device(dev);
3027 if (err)
7ff93f8b 3028 goto err_port;
225c7b1f 3029
b046ffe5
EP		 3030 mlx4_request_modules(dev);
3031
27bf91d6
YP		 3032 mlx4_sense_init(dev);
3033 mlx4_start_sense(dev);
3034
befdf897 3035 priv->removed = 0;
225c7b1f 3036
55ad3592 3037 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3038 atomic_dec(&pf_loading);
3039
da315679 3040 kfree(dev_cap);
225c7b1f
RD		 3041 return 0;
3042
7ff93f8b 3043err_port:
b4f77264 3044 for (--port; port >= 1; --port)
7ff93f8b
YP		 3045 mlx4_cleanup_port_info(&priv->port[port]);
3046
f2a3f6a3 3047 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 3048 mlx4_cleanup_qp_table(dev);
3049 mlx4_cleanup_srq_table(dev);
3050 mlx4_cleanup_cq_table(dev);
3051 mlx4_cmd_use_polling(dev);
3052 mlx4_cleanup_eq_table(dev);
fe6f700d 3053 mlx4_cleanup_mcg_table(dev);
225c7b1f 3054 mlx4_cleanup_mr_table(dev);
012a8ff5 3055 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 3056 mlx4_cleanup_pd_table(dev);
3057 mlx4_cleanup_uar_table(dev);
3058
b12d93d6 3059err_steer:
ab9c17a0
JM		 3060 if (!mlx4_is_slave(dev))
3061 mlx4_clear_steering(dev);
b12d93d6 3062
e1c00e10
MD		 3063err_disable_msix:
3064 if (dev->flags & MLX4_FLAG_MSI_X)
3065 pci_disable_msix(pdev);
3066
b8dd786f
YP		 3067err_free_eq:
3068 mlx4_free_eq_table(dev);
3069
ab9c17a0 3070err_master_mfunc:
772103e6
JM		 3071 if (mlx4_is_master(dev)) {
3072 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 3073 mlx4_multi_func_cleanup(dev);
772103e6 3074 }
ab9c17a0 3075
b38f2879 3076 if (mlx4_is_slave(dev)) {
99ec41d0 3077 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 3078 kfree(dev->caps.qp0_tunnel);
3079 kfree(dev->caps.qp0_proxy);
3080 kfree(dev->caps.qp1_tunnel);
3081 kfree(dev->caps.qp1_proxy);
3082 }
3083
225c7b1f
RD		 3084err_close:
3085 mlx4_close_hca(dev);
3086
a0eacca9
MB		 3087err_fw:
3088 mlx4_close_fw(dev);
3089
ab9c17a0
JM		 3090err_mfunc:
3091 if (mlx4_is_slave(dev))
3092 mlx4_multi_func_cleanup(dev);
3093
225c7b1f 3094err_cmd:
ffc39f6d 3095 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 3096
ab9c17a0 3097err_sriov:
55ad3592 3098 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
ab9c17a0 3099 pci_disable_sriov(pdev);
55ad3592
YH		 3100 dev->flags &= ~MLX4_FLAG_SRIOV;
3101 }
ab9c17a0 3102
55ad3592 3103 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3104 atomic_dec(&pf_loading);
3105
1ab95d37
MB		 3106 kfree(priv->dev.dev_vfs);
3107
e1c00e10
MD		 3108 if (!mlx4_is_slave(dev))
3109 mlx4_free_ownership(dev);
3110
7ae0e400 3111 kfree(dev_cap);
e1c00e10
MD		 3112 return err;
3113}
3114
3115static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3116 struct mlx4_priv *priv)
3117{
3118 int err;
3119 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3120 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3121 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3122 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3123 unsigned total_vfs = 0;
3124 unsigned int i;
3125
3126 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3127
3128 err = pci_enable_device(pdev);
3129 if (err) {
3130 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3131 return err;
3132 }
3133
3134 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3135 * per port, we must limit the number of VFs to 63 (since their are
3136 * 128 MACs)
3137 */
3138 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3139 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3140 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3141 if (nvfs[i] < 0) {
3142 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3143 err = -EINVAL;
3144 goto err_disable_pdev;
3145 }
3146 }
3147 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3148 i++) {
3149 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3150 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3151 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3152 err = -EINVAL;
3153 goto err_disable_pdev;
3154 }
3155 }
3156 if (total_vfs >= MLX4_MAX_NUM_VF) {
3157 dev_err(&pdev->dev,
3158 "Requested more VF's (%d) than allowed (%d)\n",
3159 total_vfs, MLX4_MAX_NUM_VF - 1);
3160 err = -EINVAL;
3161 goto err_disable_pdev;
3162 }
3163
3164 for (i = 0; i < MLX4_MAX_PORTS; i++) {
3165 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
3166 dev_err(&pdev->dev,
3167 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
3168 nvfs[i] + nvfs[2], i + 1,
3169 MLX4_MAX_NUM_VF_P_PORT - 1);
3170 err = -EINVAL;
3171 goto err_disable_pdev;
3172 }
3173 }
3174
3175 /* Check for BARs. */
3176 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3177 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3178 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3179 pci_dev_data, pci_resource_flags(pdev, 0));
3180 err = -ENODEV;
3181 goto err_disable_pdev;
3182 }
3183 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3184 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3185 err = -ENODEV;
3186 goto err_disable_pdev;
3187 }
3188
3189 err = pci_request_regions(pdev, DRV_NAME);
3190 if (err) {
3191 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3192 goto err_disable_pdev;
3193 }
3194
3195 pci_set_master(pdev);
3196
3197 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3198 if (err) {
3199 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3200 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3201 if (err) {
3202 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3203 goto err_release_regions;
3204 }
3205 }
3206 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3207 if (err) {
3208 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3209 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3210 if (err) {
3211 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3212 goto err_release_regions;
3213 }
3214 }
3215
3216 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3217 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3218 /* Detect if this device is a virtual function */
3219 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3220 /* When acting as pf, we normally skip vfs unless explicitly
3221 * requested to probe them.
3222 */
3223 if (total_vfs) {
3224 unsigned vfs_offset = 0;
3225
3226 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3227 vfs_offset + nvfs[i] < extended_func_num(pdev);
3228 vfs_offset += nvfs[i], i++)
3229 ;
3230 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3231 err = -ENODEV;
3232 goto err_release_regions;
3233 }
3234 if ((extended_func_num(pdev) - vfs_offset)
3235 > prb_vf[i]) {
3236 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3237 extended_func_num(pdev));
3238 err = -ENODEV;
3239 goto err_release_regions;
3240 }
3241 }
3242 }
3243
ad9a0bf0 3244 err = mlx4_catas_init(&priv->dev);
e1c00e10
MD		 3245 if (err)
3246 goto err_release_regions;
ad9a0bf0 3247
55ad3592 3248 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
ad9a0bf0
YH		 3249 if (err)
3250 goto err_catas;
3251
e1c00e10 3252 return 0;
225c7b1f 3253
ad9a0bf0
YH		 3254err_catas:
3255 mlx4_catas_end(&priv->dev);
3256
a01df0fe
RD		 3257err_release_regions:
3258 pci_release_regions(pdev);
225c7b1f
RD		 3259
3260err_disable_pdev:
3261 pci_disable_device(pdev);
3262 pci_set_drvdata(pdev, NULL);
3263 return err;
3264}
3265
1dd06ae8 3266static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 3267{
befdf897
WY		 3268 struct mlx4_priv *priv;
3269 struct mlx4_dev *dev;
e1c00e10 3270 int ret;
befdf897 3271
0a645e80 3272 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 3273
befdf897
WY		 3274 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
3275 if (!priv)
3276 return -ENOMEM;
3277
3278 dev = &priv->dev;
872bf2fb
YH		 3279 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3280 if (!dev->persist) {
3281 kfree(priv);
3282 return -ENOMEM;
3283 }
3284 dev->persist->pdev = pdev;
3285 dev->persist->dev = dev;
3286 pci_set_drvdata(pdev, dev->persist);
befdf897 3287 priv->pci_dev_data = id->driver_data;
f6bc11e4 3288 mutex_init(&dev->persist->device_state_mutex);
c69453e2 3289 mutex_init(&dev->persist->interface_state_mutex);
befdf897 3290
e1c00e10 3291 ret = __mlx4_init_one(pdev, id->driver_data, priv);
872bf2fb
YH		 3292 if (ret) {
3293 kfree(dev->persist);
e1c00e10 3294 kfree(priv);
2ba5fbd6
YH		 3295 } else {
3296 pci_save_state(pdev);
872bf2fb 3297 }
2ba5fbd6 3298
e1c00e10 3299 return ret;
3d73c288
RD		 3300}
3301
dd0eefe3
YH		 3302static void mlx4_clean_dev(struct mlx4_dev *dev)
3303{
3304 struct mlx4_dev_persistent *persist = dev->persist;
3305 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 3306 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
dd0eefe3
YH		 3307
3308 memset(priv, 0, sizeof(*priv));
3309 priv->dev.persist = persist;
55ad3592 3310 priv->dev.flags = flags;
dd0eefe3
YH		 3311}
3312
e1c00e10 3313static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f 3314{
872bf2fb
YH		 3315 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3316 struct mlx4_dev *dev = persist->dev;
225c7b1f 3317 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 3318 int pci_dev_data;
dd0eefe3 3319 int p, i;
225c7b1f 3320
befdf897
WY		 3321 if (priv->removed)
3322 return;
225c7b1f 3323
dd0eefe3
YH		 3324 /* saving current ports type for further use */
3325 for (i = 0; i < dev->caps.num_ports; i++) {
3326 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3327 dev->persist->curr_port_poss_type[i] = dev->caps.
3328 possible_type[i + 1];
3329 }
3330
befdf897 3331 pci_dev_data = priv->pci_dev_data;
225c7b1f 3332
befdf897
WY		 3333 mlx4_stop_sense(dev);
3334 mlx4_unregister_device(dev);
225c7b1f 3335
befdf897
WY		 3336 for (p = 1; p <= dev->caps.num_ports; p++) {
3337 mlx4_cleanup_port_info(&priv->port[p]);
3338 mlx4_CLOSE_PORT(dev, p);
3339 }
3340
3341 if (mlx4_is_master(dev))
3342 mlx4_free_resource_tracker(dev,
3343 RES_TR_FREE_SLAVES_ONLY);
3344
3345 mlx4_cleanup_counters_table(dev);
3346 mlx4_cleanup_qp_table(dev);
3347 mlx4_cleanup_srq_table(dev);
3348 mlx4_cleanup_cq_table(dev);
3349 mlx4_cmd_use_polling(dev);
3350 mlx4_cleanup_eq_table(dev);
3351 mlx4_cleanup_mcg_table(dev);
3352 mlx4_cleanup_mr_table(dev);
3353 mlx4_cleanup_xrcd_table(dev);
3354 mlx4_cleanup_pd_table(dev);
225c7b1f 3355
befdf897
WY		 3356 if (mlx4_is_master(dev))
3357 mlx4_free_resource_tracker(dev,
3358 RES_TR_FREE_STRUCTS_ONLY);
47605df9 3359
befdf897
WY		 3360 iounmap(priv->kar);
3361 mlx4_uar_free(dev, &priv->driver_uar);
3362 mlx4_cleanup_uar_table(dev);
3363 if (!mlx4_is_slave(dev))
3364 mlx4_clear_steering(dev);
3365 mlx4_free_eq_table(dev);
3366 if (mlx4_is_master(dev))
3367 mlx4_multi_func_cleanup(dev);
3368 mlx4_close_hca(dev);
a0eacca9 3369 mlx4_close_fw(dev);
befdf897
WY		 3370 if (mlx4_is_slave(dev))
3371 mlx4_multi_func_cleanup(dev);
ffc39f6d 3372 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 3373
befdf897
WY		 3374 if (dev->flags & MLX4_FLAG_MSI_X)
3375 pci_disable_msix(pdev);
befdf897
WY		 3376
3377 if (!mlx4_is_slave(dev))
3378 mlx4_free_ownership(dev);
3379
99ec41d0 3380 kfree(dev->caps.qp0_qkey);
befdf897
WY		 3381 kfree(dev->caps.qp0_tunnel);
3382 kfree(dev->caps.qp0_proxy);
3383 kfree(dev->caps.qp1_tunnel);
3384 kfree(dev->caps.qp1_proxy);
3385 kfree(dev->dev_vfs);
3386
dd0eefe3 3387 mlx4_clean_dev(dev);
befdf897
WY		 3388 priv->pci_dev_data = pci_dev_data;
3389 priv->removed = 1;
3390}
3391
3392static void mlx4_remove_one(struct pci_dev *pdev)
3393{
872bf2fb
YH		 3394 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3395 struct mlx4_dev *dev = persist->dev;
befdf897 3396 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 3397 int active_vfs = 0;
befdf897 3398
c69453e2
YH		 3399 mutex_lock(&persist->interface_state_mutex);
3400 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3401 mutex_unlock(&persist->interface_state_mutex);
3402
55ad3592
YH		 3403 /* Disabling SR-IOV is not allowed while there are active vf's */
3404 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3405 active_vfs = mlx4_how_many_lives_vf(dev);
3406 if (active_vfs) {
3407 pr_warn("Removing PF when there are active VF's !!\n");
3408 pr_warn("Will not disable SR-IOV.\n");
3409 }
3410 }
3411
c69453e2
YH		 3412 /* device marked to be under deletion running now without the lock
3413 * letting other tasks to be terminated
3414 */
3415 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3416 mlx4_unload_one(pdev);
3417 else
3418 mlx4_info(dev, "%s: interface is down\n", __func__);
ad9a0bf0 3419 mlx4_catas_end(dev);
55ad3592
YH		 3420 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3421 mlx4_warn(dev, "Disabling SR-IOV\n");
3422 pci_disable_sriov(pdev);
3423 }
3424
e1c00e10
MD		 3425 pci_release_regions(pdev);
3426 pci_disable_device(pdev);
872bf2fb 3427 kfree(dev->persist);
befdf897
WY		 3428 kfree(priv);
3429 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 3430}
3431
dd0eefe3
YH		 3432static int restore_current_port_types(struct mlx4_dev *dev,
3433 enum mlx4_port_type *types,
3434 enum mlx4_port_type *poss_types)
3435{
3436 struct mlx4_priv *priv = mlx4_priv(dev);
3437 int err, i;
3438
3439 mlx4_stop_sense(dev);
3440
3441 mutex_lock(&priv->port_mutex);
3442 for (i = 0; i < dev->caps.num_ports; i++)
3443 dev->caps.possible_type[i + 1] = poss_types[i];
3444 err = mlx4_change_port_types(dev, types);
3445 mlx4_start_sense(dev);
3446 mutex_unlock(&priv->port_mutex);
3447
3448 return err;
3449}
3450
ee49bd93
JM		 3451int mlx4_restart_one(struct pci_dev *pdev)
3452{
872bf2fb
YH		 3453 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3454 struct mlx4_dev *dev = persist->dev;
839f1243 3455 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 3456 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3457 int pci_dev_data, err, total_vfs;
839f1243
RD		 3458
3459 pci_dev_data = priv->pci_dev_data;
872bf2fb
YH		 3460 total_vfs = dev->persist->num_vfs;
3461 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
e1c00e10
MD		 3462
3463 mlx4_unload_one(pdev);
55ad3592 3464 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
e1c00e10
MD		 3465 if (err) {
3466 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3467 __func__, pci_name(pdev), err);
3468 return err;
3469 }
3470
dd0eefe3
YH		 3471 err = restore_current_port_types(dev, dev->persist->curr_port_type,
3472 dev->persist->curr_port_poss_type);
3473 if (err)
3474 mlx4_err(dev, "could not restore original port types (%d)\n",
3475 err);
3476
e1c00e10 3477 return err;
ee49bd93
JM		 3478}
3479
9baa3c34 3480static const struct pci_device_id mlx4_pci_table[] = {
ab9c17a0 3481 /* MT25408 "Hermon" SDR */
ca3e57a5 3482 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3483 /* MT25408 "Hermon" DDR */
ca3e57a5 3484 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3485 /* MT25408 "Hermon" QDR */
ca3e57a5 3486 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3487 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 3488 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3489 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 3490 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3491 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 3492 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3493 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 3494 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3495 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 3496 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3497 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 3498 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3499 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 3500 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3501 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 3502 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3503 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 3504 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3505 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 3506 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3507 /* MT27500 Family [ConnectX-3] */
3508 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3509 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 3510 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3511 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3512 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3513 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3514 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3515 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3516 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3517 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3518 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3519 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3520 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3521 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3522 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 3523 { 0, }
3524};
3525
3526MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3527
57dbf29a
KSS		 3528static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3529 pci_channel_state_t state)
3530{
2ba5fbd6
YH		 3531 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3532
3533 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
3534 mlx4_enter_error_state(persist);
57dbf29a 3535
2ba5fbd6
YH		 3536 mutex_lock(&persist->interface_state_mutex);
3537 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3538 mlx4_unload_one(pdev);
3539
3540 mutex_unlock(&persist->interface_state_mutex);
3541 if (state == pci_channel_io_perm_failure)
3542 return PCI_ERS_RESULT_DISCONNECT;
3543
3544 pci_disable_device(pdev);
3545 return PCI_ERS_RESULT_NEED_RESET;
57dbf29a
KSS		 3546}
3547
3548static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3549{
2ba5fbd6
YH		 3550 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3551 struct mlx4_dev *dev = persist->dev;
befdf897
WY		 3552 struct mlx4_priv *priv = mlx4_priv(dev);
3553 int ret;
2ba5fbd6
YH		 3554 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3555 int total_vfs;
97a5221f 3556
2ba5fbd6
YH		 3557 mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
3558 ret = pci_enable_device(pdev);
3559 if (ret) {
3560 mlx4_err(dev, "Can not re-enable device, ret=%d\n", ret);
3561 return PCI_ERS_RESULT_DISCONNECT;
3562 }
3563
3564 pci_set_master(pdev);
3565 pci_restore_state(pdev);
3566 pci_save_state(pdev);
3567
3568 total_vfs = dev->persist->num_vfs;
3569 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3570
3571 mutex_lock(&persist->interface_state_mutex);
3572 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
3573 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
55ad3592 3574 priv, 1);
2ba5fbd6
YH		 3575 if (ret) {
3576 mlx4_err(dev, "%s: mlx4_load_one failed, ret=%d\n",
3577 __func__, ret);
3578 goto end;
3579 }
3580
3581 ret = restore_current_port_types(dev, dev->persist->
3582 curr_port_type, dev->persist->
3583 curr_port_poss_type);
3584 if (ret)
3585 mlx4_err(dev, "could not restore original port types (%d)\n", ret);
3586 }
3587end:
3588 mutex_unlock(&persist->interface_state_mutex);
57dbf29a
KSS		 3589
3590 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3591}
3592
2ba5fbd6
YH		 3593static void mlx4_shutdown(struct pci_dev *pdev)
3594{
3595 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3596
3597 mlx4_info(persist->dev, "mlx4_shutdown was called\n");
3598 mutex_lock(&persist->interface_state_mutex);
3599 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3600 mlx4_unload_one(pdev);
3601 mutex_unlock(&persist->interface_state_mutex);
3602}
3603
3646f0e5 3604static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 3605 .error_detected = mlx4_pci_err_detected,
3606 .slot_reset = mlx4_pci_slot_reset,
3607};
3608
225c7b1f
RD		 3609static struct pci_driver mlx4_driver = {
3610 .name = DRV_NAME,
3611 .id_table = mlx4_pci_table,
3612 .probe = mlx4_init_one,
2ba5fbd6 3613 .shutdown = mlx4_shutdown,
f57e6848 3614 .remove = mlx4_remove_one,
57dbf29a 3615 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 3616};
3617
7ff93f8b
YP		 3618static int __init mlx4_verify_params(void)
3619{
3620 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 3621 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 3622 return -1;
3623 }
3624
cb29688a 3625 if (log_num_vlan != 0)
c20862c8
AV		 3626 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3627 MLX4_LOG_NUM_VLANS);
7ff93f8b 3628
ecc8fb11
AV		 3629 if (use_prio != 0)
3630 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 3631
0498628f 3632 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 3633 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3634 log_mtts_per_seg);
ab6bf42e
EC		 3635 return -1;
3636 }
3637
ab9c17a0
JM		 3638 /* Check if module param for ports type has legal combination */
3639 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 3640 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 3641 port_type_array[0] = true;
3642 }
3643
7d077cd3
MB		 3644 if (mlx4_log_num_mgm_entry_size < -7 ||
3645 (mlx4_log_num_mgm_entry_size > 0 &&
3646 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3647 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
3648 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
1a91de28
JP		 3649 mlx4_log_num_mgm_entry_size,
3650 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3651 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 3652 return -1;
3653 }
3654
7ff93f8b
YP		 3655 return 0;
3656}
3657
225c7b1f
RD		 3658static int __init mlx4_init(void)
3659{
3660 int ret;
3661
7ff93f8b
YP		 3662 if (mlx4_verify_params())
3663 return -EINVAL;
3664
27bf91d6
YP		 3665
3666 mlx4_wq = create_singlethread_workqueue("mlx4");
3667 if (!mlx4_wq)
3668 return -ENOMEM;
ee49bd93 3669
225c7b1f 3670 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 3671 if (ret < 0)
3672 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3673 return ret < 0 ? ret : 0;
3674}
3675
3676static void __exit mlx4_cleanup(void)
3677{
3678 pci_unregister_driver(&mlx4_driver);
27bf91d6 3679 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3680}
3681
3682module_init(mlx4_init);
3683module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)