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net/mlx4_core: Enable device recovery flow with SRIOV
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
dd41cc3b 80static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 81static int num_vfs_argc;
dd41cc3b
MB		 82module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 87static int probe_vfs_argc;
dd41cc3b
MB		 88module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
ab9c17a0 91
3c439b55 92int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 93module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
3c439b55 97 " 10 gives 248.range: 7 <="
0ff1fb65 98 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 99 " To activate device managed"
100 " flow steering when available, set to -1");
0ec2c0f8 101
be902ab1 102static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 103module_param(enable_64b_cqe_eqe, bool, 0444);
104MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 106
77507aa2 107#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
7d077cd3
MB		 108 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
109 MLX4_FUNC_CAP_DMFS_A0_STATIC)
ab9c17a0 110
55ad3592
YH		 111#define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV)
112
f57e6848 113static char mlx4_version[] =
225c7b1f
RD		 114 DRV_NAME ": Mellanox ConnectX core driver v"
115 DRV_VERSION " (" DRV_RELDATE ")\n";
116
117static struct mlx4_profile default_profile = {
ab9c17a0 118 .num_qp = 1 << 18,
225c7b1f 119 .num_srq = 1 << 16,
c9f2ba5e 120 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 121 .num_cq = 1 << 16,
122 .num_mcg = 1 << 13,
ab9c17a0 123 .num_mpt = 1 << 19,
9fd7a1e1 124 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 125};
126
2599d858
AV		 127static struct mlx4_profile low_mem_profile = {
128 .num_qp = 1 << 17,
129 .num_srq = 1 << 6,
130 .rdmarc_per_qp = 1 << 4,
131 .num_cq = 1 << 8,
132 .num_mcg = 1 << 8,
133 .num_mpt = 1 << 9,
134 .num_mtt = 1 << 7,
135};
136
ab9c17a0 137static int log_num_mac = 7;
93fc9e1b
YP		 138module_param_named(log_num_mac, log_num_mac, int, 0444);
139MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
140
141static int log_num_vlan;
142module_param_named(log_num_vlan, log_num_vlan, int, 0444);
143MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 144/* Log2 max number of VLANs per ETH port (0-7) */
145#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 146#define MLX4_MIN_LOG_NUM_VLANS 0
147#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 148
eb939922 149static bool use_prio;
93fc9e1b 150module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 151MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 152
2b8fb286 153int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 154module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 155MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 156
8d0fc7b6 157static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 158static int arr_argc = 2;
159module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 160MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
161 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 162
163struct mlx4_port_config {
164 struct list_head list;
165 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
166 struct pci_dev *pdev;
167};
168
97989356
AV		 169static atomic_t pf_loading = ATOMIC_INIT(0);
170
27bf91d6
YP		 171int mlx4_check_port_params(struct mlx4_dev *dev,
172 enum mlx4_port_type *port_type)
7ff93f8b
YP		 173{
174 int i;
175
0b997657
YS		 176 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
177 for (i = 0; i < dev->caps.num_ports - 1; i++) {
178 if (port_type[i] != port_type[i + 1]) {
1a91de28 179 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 180 return -EINVAL;
181 }
7ff93f8b
YP		 182 }
183 }
7ff93f8b
YP		 184
185 for (i = 0; i < dev->caps.num_ports; i++) {
186 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 187 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
188 i + 1);
7ff93f8b
YP		 189 return -EINVAL;
190 }
191 }
192 return 0;
193}
194
195static void mlx4_set_port_mask(struct mlx4_dev *dev)
196{
197 int i;
198
7ff93f8b 199 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 200 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 201}
f2a3f6a3 202
7ae0e400
MB		 203enum {
204 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
205};
206
207static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
208{
209 int err = 0;
210 struct mlx4_func func;
211
212 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
213 err = mlx4_QUERY_FUNC(dev, &func, 0);
214 if (err) {
215 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
216 return err;
217 }
218 dev_cap->max_eqs = func.max_eq;
219 dev_cap->reserved_eqs = func.rsvd_eqs;
220 dev_cap->reserved_uars = func.rsvd_uars;
221 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
222 }
223 return err;
224}
225
77507aa2
IS		 226static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
227{
228 struct mlx4_caps *dev_cap = &dev->caps;
229
230 /* FW not supporting or cancelled by user */
231 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
232 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
233 return;
234
235 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
236 * When FW has NCSI it may decide not to report 64B CQE/EQEs
237 */
238 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
239 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
240 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
241 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
242 return;
243 }
244
245 if (cache_line_size() == 128 || cache_line_size() == 256) {
246 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
247 /* Changing the real data inside CQE size to 32B */
248 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
249 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
250
251 if (mlx4_is_master(dev))
252 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
253 } else {
254 mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n");
255 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
256 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
257 }
258}
259
431df8c7
MB		 260static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
261 struct mlx4_port_cap *port_cap)
262{
263 dev->caps.vl_cap[port] = port_cap->max_vl;
264 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
265 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
266 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
267 /* set gid and pkey table operating lengths by default
268 * to non-sriov values
269 */
270 dev->caps.gid_table_len[port] = port_cap->max_gids;
271 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
272 dev->caps.port_width_cap[port] = port_cap->max_port_width;
273 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
274 dev->caps.def_mac[port] = port_cap->def_mac;
275 dev->caps.supported_type[port] = port_cap->supported_port_types;
276 dev->caps.suggested_type[port] = port_cap->suggested_type;
277 dev->caps.default_sense[port] = port_cap->default_sense;
278 dev->caps.trans_type[port] = port_cap->trans_type;
279 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
280 dev->caps.wavelength[port] = port_cap->wavelength;
281 dev->caps.trans_code[port] = port_cap->trans_code;
282
283 return 0;
284}
285
286static int mlx4_dev_port(struct mlx4_dev *dev, int port,
287 struct mlx4_port_cap *port_cap)
288{
289 int err = 0;
290
291 err = mlx4_QUERY_PORT(dev, port, port_cap);
292
293 if (err)
294 mlx4_err(dev, "QUERY_PORT command failed.\n");
295
296 return err;
297}
298
299#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 300static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 301{
302 int err;
5ae2a7a8 303 int i;
225c7b1f
RD		 304
305 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
306 if (err) {
1a91de28 307 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 308 return err;
309 }
c78e25ed 310 mlx4_dev_cap_dump(dev, dev_cap);
225c7b1f
RD		 311
312 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 313 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 314 dev_cap->min_page_sz, PAGE_SIZE);
315 return -ENODEV;
316 }
317 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 318 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 319 dev_cap->num_ports, MLX4_MAX_PORTS);
320 return -ENODEV;
321 }
322
872bf2fb 323 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
1a91de28 324 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f 325 dev_cap->uar_size,
872bf2fb
YH		 326 (unsigned long long)
327 pci_resource_len(dev->persist->pdev, 2));
225c7b1f
RD		 328 return -ENODEV;
329 }
330
331 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 332 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
333 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
334 dev->caps.num_sys_eqs :
335 MLX4_MAX_EQ_NUM;
5ae2a7a8 336 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 337 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
338 if (err) {
339 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
340 return err;
341 }
5ae2a7a8
RD		 342 }
343
ab9c17a0 344 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 345 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 346 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
347 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
348 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
349 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
350 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
351 dev->caps.max_wqes = dev_cap->max_qp_sz;
352 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 353 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
354 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
355 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
356 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
357 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 358 /*
359 * Subtract 1 from the limit because we need to allocate a
360 * spare CQE so the HCA HW can tell the difference between an
361 * empty CQ and a full CQ.
362 */
363 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
364 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
365 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 366 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 367 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 368
369 /* The first 128 UARs are used for EQ doorbells */
370 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 371 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 372 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
373 dev_cap->reserved_xrcds : 0;
374 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
375 dev_cap->max_xrcds : 0;
2b8fb286
MA		 376 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
377
149983af 378 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 379 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
380 dev->caps.flags = dev_cap->flags;
b3416f44 381 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 382 dev->caps.bmme_flags = dev_cap->bmme_flags;
383 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 384 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 385 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 386 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 387
ca3e57a5
RD		 388 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
389 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 390 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 391 /* Don't do sense port on multifunction devices (for now at least) */
392 if (mlx4_is_mfunc(dev))
393 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 394
2599d858
AV		 395 if (mlx4_low_memory_profile()) {
396 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
397 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
398 } else {
399 dev->caps.log_num_macs = log_num_mac;
400 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
401 }
93fc9e1b
YP		 402
403 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 404 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
405 if (dev->caps.supported_type[i]) {
406 /* if only ETH is supported - assign ETH */
407 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
408 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 409 /* if only IB is supported, assign IB */
ab9c17a0 410 else if (dev->caps.supported_type[i] ==
105c320f
JM		 411 MLX4_PORT_TYPE_IB)
412 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 413 else {
105c320f
JM		 414 /* if IB and ETH are supported, we set the port
415 * type according to user selection of port type;
416 * if user selected none, take the FW hint */
417 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 418 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
419 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 420 else
105c320f 421 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 422 }
423 }
8d0fc7b6
YP		 424 /*
425 * Link sensing is allowed on the port if 3 conditions are true:
426 * 1. Both protocols are supported on the port.
427 * 2. Different types are supported on the port
428 * 3. FW declared that it supports link sensing
429 */
27bf91d6 430 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 431 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 432 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 433 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 434
8d0fc7b6
YP		 435 /*
436 * If "default_sense" bit is set, we move the port to "AUTO" mode
437 * and perform sense_port FW command to try and set the correct
438 * port type from beginning
439 */
46c46747 440 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 441 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
442 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
443 mlx4_SENSE_PORT(dev, i, &sensed_port);
444 if (sensed_port != MLX4_PORT_TYPE_NONE)
445 dev->caps.port_type[i] = sensed_port;
446 } else {
447 dev->caps.possible_type[i] = dev->caps.port_type[i];
448 }
449
431df8c7
MB		 450 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
451 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 452 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 453 i, 1 << dev->caps.log_num_macs);
454 }
431df8c7
MB		 455 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
456 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 457 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 458 i, 1 << dev->caps.log_num_vlans);
459 }
460 }
461
f2a3f6a3
OG		 462 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
463
93fc9e1b
YP		 464 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
465 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
466 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
467 (1 << dev->caps.log_num_macs) *
468 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 469 dev->caps.num_ports;
470 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
7d077cd3
MB		 471
472 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
473 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
474 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
475 else
476 dev->caps.dmfs_high_rate_qpn_base =
477 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
478
479 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
480 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
481 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
482 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
483 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
484 } else {
485 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
486 dev->caps.dmfs_high_rate_qpn_base =
487 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
488 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
489 }
490
d57febe1 491 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
7d077cd3 492 dev->caps.dmfs_high_rate_qpn_range;
93fc9e1b
YP		 493
494 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
495 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
496 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
497 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
498
e2c76824 499 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 500
b3051320 501 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 502 if (dev_cap->flags &
503 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
504 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
505 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
506 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
507 }
77507aa2
IS		 508
509 if (dev_cap->flags2 &
510 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
511 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
512 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
513 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
514 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
515 }
08ff3235
OG		 516 }
517
f97b4b5d 518 if ((dev->caps.flags &
08ff3235
OG		 519 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
520 mlx4_is_master(dev))
521 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
522
ddae0349 523 if (!mlx4_is_slave(dev)) {
77507aa2 524 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 525 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 526 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
527 MLX4_RESERVE_A0_QP;
ddae0349
EE		 528 } else {
529 dev->caps.alloc_res_qp_mask = 0;
530 }
77507aa2 531
225c7b1f
RD		 532 return 0;
533}
b912b2f8
EP		 534
535static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
536 enum pci_bus_speed *speed,
537 enum pcie_link_width *width)
538{
539 u32 lnkcap1, lnkcap2;
540 int err1, err2;
541
542#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
543
544 *speed = PCI_SPEED_UNKNOWN;
545 *width = PCIE_LNK_WIDTH_UNKNOWN;
546
872bf2fb
YH		 547 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
548 &lnkcap1);
549 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
550 &lnkcap2);
b912b2f8
EP		 551 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
552 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
553 *speed = PCIE_SPEED_8_0GT;
554 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
555 *speed = PCIE_SPEED_5_0GT;
556 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
557 *speed = PCIE_SPEED_2_5GT;
558 }
559 if (!err1) {
560 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
561 if (!lnkcap2) { /* pre-r3.0 */
562 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
563 *speed = PCIE_SPEED_5_0GT;
564 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
565 *speed = PCIE_SPEED_2_5GT;
566 }
567 }
568
569 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
570 return err1 ? err1 :
571 err2 ? err2 : -EINVAL;
572 }
573 return 0;
574}
575
576static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
577{
578 enum pcie_link_width width, width_cap;
579 enum pci_bus_speed speed, speed_cap;
580 int err;
581
582#define PCIE_SPEED_STR(speed) \
583 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
584 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
585 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
586 "Unknown")
587
588 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
589 if (err) {
590 mlx4_warn(dev,
591 "Unable to determine PCIe device BW capabilities\n");
592 return;
593 }
594
872bf2fb 595 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
b912b2f8
EP		 596 if (err || speed == PCI_SPEED_UNKNOWN ||
597 width == PCIE_LNK_WIDTH_UNKNOWN) {
598 mlx4_warn(dev,
599 "Unable to determine PCI device chain minimum BW\n");
600 return;
601 }
602
603 if (width != width_cap || speed != speed_cap)
604 mlx4_warn(dev,
605 "PCIe BW is different than device's capability\n");
606
607 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
608 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
609 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
610 width, width_cap);
611 return;
612}
613
ab9c17a0
JM		 614/*The function checks if there are live vf, return the num of them*/
615static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
616{
617 struct mlx4_priv *priv = mlx4_priv(dev);
618 struct mlx4_slave_state *s_state;
619 int i;
620 int ret = 0;
621
622 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
623 s_state = &priv->mfunc.master.slave_state[i];
624 if (s_state->active && s_state->last_cmd !=
625 MLX4_COMM_CMD_RESET) {
626 mlx4_warn(dev, "%s: slave: %d is still active\n",
627 __func__, i);
628 ret++;
629 }
630 }
631 return ret;
632}
633
396f2feb
JM		 634int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
635{
636 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 637
638 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
639 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 640 return -EINVAL;
641
47605df9 642 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 643 /* tunnel qp */
47605df9 644 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 645 else
47605df9 646 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 647 *qkey = qk;
648 return 0;
649}
650EXPORT_SYMBOL(mlx4_get_parav_qkey);
651
54679e14
JM		 652void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
653{
654 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
655
656 if (!mlx4_is_master(dev))
657 return;
658
659 priv->virt2phys_pkey[slave][port - 1][i] = val;
660}
661EXPORT_SYMBOL(mlx4_sync_pkey_table);
662
afa8fd1d
JM		 663void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
664{
665 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
666
667 if (!mlx4_is_master(dev))
668 return;
669
670 priv->slave_node_guids[slave] = guid;
671}
672EXPORT_SYMBOL(mlx4_put_slave_node_guid);
673
674__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
675{
676 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
677
678 if (!mlx4_is_master(dev))
679 return 0;
680
681 return priv->slave_node_guids[slave];
682}
683EXPORT_SYMBOL(mlx4_get_slave_node_guid);
684
e10903b0 685int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 686{
687 struct mlx4_priv *priv = mlx4_priv(dev);
688 struct mlx4_slave_state *s_slave;
689
690 if (!mlx4_is_master(dev))
691 return 0;
692
693 s_slave = &priv->mfunc.master.slave_state[slave];
694 return !!s_slave->active;
695}
696EXPORT_SYMBOL(mlx4_is_slave_active);
697
7b8157be
JM		 698static void slave_adjust_steering_mode(struct mlx4_dev *dev,
699 struct mlx4_dev_cap *dev_cap,
700 struct mlx4_init_hca_param *hca_param)
701{
702 dev->caps.steering_mode = hca_param->steering_mode;
703 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
704 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
705 dev->caps.fs_log_max_ucast_qp_range_size =
706 dev_cap->fs_log_max_ucast_qp_range_size;
707 } else
708 dev->caps.num_qp_per_mgm =
709 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
710
711 mlx4_dbg(dev, "Steering mode is: %s\n",
712 mlx4_steering_mode_str(dev->caps.steering_mode));
713}
714
ab9c17a0
JM		 715static int mlx4_slave_cap(struct mlx4_dev *dev)
716{
717 int err;
718 u32 page_size;
719 struct mlx4_dev_cap dev_cap;
720 struct mlx4_func_cap func_cap;
721 struct mlx4_init_hca_param hca_param;
225c6c8c 722 u8 i;
ab9c17a0
JM		 723
724 memset(&hca_param, 0, sizeof(hca_param));
725 err = mlx4_QUERY_HCA(dev, &hca_param);
726 if (err) {
1a91de28 727 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
ab9c17a0
JM		 728 return err;
729 }
730
483e0132
EP		 731 /* fail if the hca has an unknown global capability
732 * at this time global_caps should be always zeroed
733 */
734 if (hca_param.global_caps) {
ab9c17a0
JM		 735 mlx4_err(dev, "Unknown hca global capabilities\n");
736 return -ENOSYS;
737 }
738
739 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
740
ddd8a6c1
EE		 741 dev->caps.hca_core_clock = hca_param.hca_core_clock;
742
ab9c17a0 743 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 744 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 745 err = mlx4_dev_cap(dev, &dev_cap);
746 if (err) {
1a91de28 747 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 748 return err;
749 }
750
b91cb3eb
JM		 751 err = mlx4_QUERY_FW(dev);
752 if (err)
1a91de28 753 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 754
ab9c17a0
JM		 755 page_size = ~dev->caps.page_size_cap + 1;
756 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
757 if (page_size > PAGE_SIZE) {
1a91de28 758 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0
JM		 759 page_size, PAGE_SIZE);
760 return -ENODEV;
761 }
762
763 /* slave gets uar page size from QUERY_HCA fw command */
764 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
765
766 /* TODO: relax this assumption */
767 if (dev->caps.uar_page_size != PAGE_SIZE) {
768 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
769 dev->caps.uar_page_size, PAGE_SIZE);
770 return -ENODEV;
771 }
772
773 memset(&func_cap, 0, sizeof(func_cap));
47605df9 774 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 775 if (err) {
1a91de28
JP		 776 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
777 err);
ab9c17a0
JM		 778 return err;
779 }
780
781 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
782 PF_CONTEXT_BEHAVIOUR_MASK) {
7d077cd3
MB		 783 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
784 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
ab9c17a0
JM		 785 return -ENOSYS;
786 }
787
ab9c17a0 788 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 789 dev->quotas.qp = func_cap.qp_quota;
790 dev->quotas.srq = func_cap.srq_quota;
791 dev->quotas.cq = func_cap.cq_quota;
792 dev->quotas.mpt = func_cap.mpt_quota;
793 dev->quotas.mtt = func_cap.mtt_quota;
794 dev->caps.num_qps = 1 << hca_param.log_num_qps;
795 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
796 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
797 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
798 dev->caps.num_eqs = func_cap.max_eq;
799 dev->caps.reserved_eqs = func_cap.reserved_eq;
ab9c17a0
JM		 800 dev->caps.num_pds = MLX4_NUM_PDS;
801 dev->caps.num_mgms = 0;
802 dev->caps.num_amgms = 0;
803
ab9c17a0 804 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 805 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
806 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 807 return -ENODEV;
808 }
809
99ec41d0 810 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
47605df9
JM		 811 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
812 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
813 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
814 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
815
816 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
99ec41d0
JM		 817 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
818 !dev->caps.qp0_qkey) {
47605df9
JM		 819 err = -ENOMEM;
820 goto err_mem;
821 }
822
6634961c 823 for (i = 1; i <= dev->caps.num_ports; ++i) {
225c6c8c 824 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
47605df9 825 if (err) {
1a91de28
JP		 826 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
827 i, err);
47605df9
JM		 828 goto err_mem;
829 }
99ec41d0 830 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
47605df9
JM		 831 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
832 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
833 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
834 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 835 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 836 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 837 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
838 &dev->caps.gid_table_len[i],
839 &dev->caps.pkey_table_len[i]))
47605df9 840 goto err_mem;
6634961c 841 }
6230bb23 842
ab9c17a0
JM		 843 if (dev->caps.uar_page_size * (dev->caps.num_uars -
844 dev->caps.reserved_uars) >
872bf2fb
YH		 845 pci_resource_len(dev->persist->pdev,
846 2)) {
1a91de28 847 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0 848 dev->caps.uar_page_size * dev->caps.num_uars,
872bf2fb
YH		 849 (unsigned long long)
850 pci_resource_len(dev->persist->pdev, 2));
47605df9 851 goto err_mem;
ab9c17a0
JM		 852 }
853
08ff3235
OG		 854 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
855 dev->caps.eqe_size = 64;
856 dev->caps.eqe_factor = 1;
857 } else {
858 dev->caps.eqe_size = 32;
859 dev->caps.eqe_factor = 0;
860 }
861
862 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
863 dev->caps.cqe_size = 64;
77507aa2 864 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 865 } else {
866 dev->caps.cqe_size = 32;
867 }
868
77507aa2
IS		 869 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
870 dev->caps.eqe_size = hca_param.eqe_size;
871 dev->caps.eqe_factor = 0;
872 }
873
874 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
875 dev->caps.cqe_size = hca_param.cqe_size;
876 /* User still need to know when CQE > 32B */
877 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
878 }
879
f9bd2d7f 880 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 881 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 882
7b8157be
JM		 883 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
884
ddae0349
EE		 885 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
886 dev->caps.bf_reg_size)
887 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
888
d57febe1
MB		 889 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
890 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
891
ab9c17a0 892 return 0;
47605df9
JM		 893
894err_mem:
99ec41d0 895 kfree(dev->caps.qp0_qkey);
47605df9
JM		 896 kfree(dev->caps.qp0_tunnel);
897 kfree(dev->caps.qp0_proxy);
898 kfree(dev->caps.qp1_tunnel);
899 kfree(dev->caps.qp1_proxy);
99ec41d0
JM		 900 dev->caps.qp0_qkey = NULL;
901 dev->caps.qp0_tunnel = NULL;
902 dev->caps.qp0_proxy = NULL;
903 dev->caps.qp1_tunnel = NULL;
904 dev->caps.qp1_proxy = NULL;
47605df9
JM		 905
906 return err;
ab9c17a0 907}
225c7b1f 908
b046ffe5
EP		 909static void mlx4_request_modules(struct mlx4_dev *dev)
910{
911 int port;
912 int has_ib_port = false;
913 int has_eth_port = false;
914#define EN_DRV_NAME "mlx4_en"
915#define IB_DRV_NAME "mlx4_ib"
916
917 for (port = 1; port <= dev->caps.num_ports; port++) {
918 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
919 has_ib_port = true;
920 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
921 has_eth_port = true;
922 }
923
b046ffe5
EP		 924 if (has_eth_port)
925 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 926 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
927 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 928}
929
7ff93f8b
YP		 930/*
931 * Change the port configuration of the device.
932 * Every user of this function must hold the port mutex.
933 */
27bf91d6
YP		 934int mlx4_change_port_types(struct mlx4_dev *dev,
935 enum mlx4_port_type *port_types)
7ff93f8b
YP		 936{
937 int err = 0;
938 int change = 0;
939 int port;
940
941 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 942 /* Change the port type only if the new type is different
943 * from the current, and not set to Auto */
3d8f9308 944 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 945 change = 1;
7ff93f8b
YP		 946 }
947 if (change) {
948 mlx4_unregister_device(dev);
949 for (port = 1; port <= dev->caps.num_ports; port++) {
950 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 951 dev->caps.port_type[port] = port_types[port - 1];
6634961c 952 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 953 if (err) {
1a91de28
JP		 954 mlx4_err(dev, "Failed to set port %d, aborting\n",
955 port);
7ff93f8b
YP		 956 goto out;
957 }
958 }
959 mlx4_set_port_mask(dev);
960 err = mlx4_register_device(dev);
b046ffe5
EP		 961 if (err) {
962 mlx4_err(dev, "Failed to register device\n");
963 goto out;
964 }
965 mlx4_request_modules(dev);
7ff93f8b
YP		 966 }
967
968out:
969 return err;
970}
971
972static ssize_t show_port_type(struct device *dev,
973 struct device_attribute *attr,
974 char *buf)
975{
976 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
977 port_attr);
978 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 979 char type[8];
980
981 sprintf(type, "%s",
982 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
983 "ib" : "eth");
984 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
985 sprintf(buf, "auto (%s)\n", type);
986 else
987 sprintf(buf, "%s\n", type);
7ff93f8b 988
27bf91d6 989 return strlen(buf);
7ff93f8b
YP		 990}
991
992static ssize_t set_port_type(struct device *dev,
993 struct device_attribute *attr,
994 const char *buf, size_t count)
995{
996 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
997 port_attr);
998 struct mlx4_dev *mdev = info->dev;
999 struct mlx4_priv *priv = mlx4_priv(mdev);
1000 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 1001 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
0a984556 1002 static DEFINE_MUTEX(set_port_type_mutex);
7ff93f8b
YP		 1003 int i;
1004 int err = 0;
1005
0a984556
AV		 1006 mutex_lock(&set_port_type_mutex);
1007
7ff93f8b
YP		 1008 if (!strcmp(buf, "ib\n"))
1009 info->tmp_type = MLX4_PORT_TYPE_IB;
1010 else if (!strcmp(buf, "eth\n"))
1011 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 1012 else if (!strcmp(buf, "auto\n"))
1013 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 1014 else {
1015 mlx4_err(mdev, "%s is not supported port type\n", buf);
0a984556
AV		 1016 err = -EINVAL;
1017 goto err_out;
7ff93f8b
YP		 1018 }
1019
27bf91d6 1020 mlx4_stop_sense(mdev);
7ff93f8b 1021 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 1022 /* Possible type is always the one that was delivered */
1023 mdev->caps.possible_type[info->port] = info->tmp_type;
1024
1025 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 1026 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 1027 mdev->caps.possible_type[i+1];
1028 if (types[i] == MLX4_PORT_TYPE_AUTO)
1029 types[i] = mdev->caps.port_type[i+1];
1030 }
7ff93f8b 1031
58a60168
YP		 1032 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1033 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1034 for (i = 1; i <= mdev->caps.num_ports; i++) {
1035 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1036 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1037 err = -EINVAL;
1038 }
1039 }
1040 }
1041 if (err) {
1a91de28 1042 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1043 goto out;
1044 }
1045
1046 mlx4_do_sense_ports(mdev, new_types, types);
1047
1048 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1049 if (err)
1050 goto out;
1051
27bf91d6
YP		 1052 /* We are about to apply the changes after the configuration
1053 * was verified, no need to remember the temporary types
1054 * any more */
1055 for (i = 0; i < mdev->caps.num_ports; i++)
1056 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1057
27bf91d6 1058 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1059
1060out:
27bf91d6 1061 mlx4_start_sense(mdev);
7ff93f8b 1062 mutex_unlock(&priv->port_mutex);
0a984556
AV		 1063err_out:
1064 mutex_unlock(&set_port_type_mutex);
1065
7ff93f8b
YP		 1066 return err ? err : count;
1067}
1068
096335b3
OG		 1069enum ibta_mtu {
1070 IB_MTU_256 = 1,
1071 IB_MTU_512 = 2,
1072 IB_MTU_1024 = 3,
1073 IB_MTU_2048 = 4,
1074 IB_MTU_4096 = 5
1075};
1076
1077static inline int int_to_ibta_mtu(int mtu)
1078{
1079 switch (mtu) {
1080 case 256: return IB_MTU_256;
1081 case 512: return IB_MTU_512;
1082 case 1024: return IB_MTU_1024;
1083 case 2048: return IB_MTU_2048;
1084 case 4096: return IB_MTU_4096;
1085 default: return -1;
1086 }
1087}
1088
1089static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1090{
1091 switch (mtu) {
1092 case IB_MTU_256: return 256;
1093 case IB_MTU_512: return 512;
1094 case IB_MTU_1024: return 1024;
1095 case IB_MTU_2048: return 2048;
1096 case IB_MTU_4096: return 4096;
1097 default: return -1;
1098 }
1099}
1100
1101static ssize_t show_port_ib_mtu(struct device *dev,
1102 struct device_attribute *attr,
1103 char *buf)
1104{
1105 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1106 port_mtu_attr);
1107 struct mlx4_dev *mdev = info->dev;
1108
1109 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1110 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1111
1112 sprintf(buf, "%d\n",
1113 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1114 return strlen(buf);
1115}
1116
1117static ssize_t set_port_ib_mtu(struct device *dev,
1118 struct device_attribute *attr,
1119 const char *buf, size_t count)
1120{
1121 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1122 port_mtu_attr);
1123 struct mlx4_dev *mdev = info->dev;
1124 struct mlx4_priv *priv = mlx4_priv(mdev);
1125 int err, port, mtu, ibta_mtu = -1;
1126
1127 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1128 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1129 return -EINVAL;
1130 }
1131
618fad95
DB		 1132 err = kstrtoint(buf, 0, &mtu);
1133 if (!err)
096335b3
OG		 1134 ibta_mtu = int_to_ibta_mtu(mtu);
1135
618fad95 1136 if (err || ibta_mtu < 0) {
096335b3
OG		 1137 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1138 return -EINVAL;
1139 }
1140
1141 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1142
1143 mlx4_stop_sense(mdev);
1144 mutex_lock(&priv->port_mutex);
1145 mlx4_unregister_device(mdev);
1146 for (port = 1; port <= mdev->caps.num_ports; port++) {
1147 mlx4_CLOSE_PORT(mdev, port);
6634961c 1148 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1149 if (err) {
1a91de28
JP		 1150 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1151 port);
096335b3
OG		 1152 goto err_set_port;
1153 }
1154 }
1155 err = mlx4_register_device(mdev);
1156err_set_port:
1157 mutex_unlock(&priv->port_mutex);
1158 mlx4_start_sense(mdev);
1159 return err ? err : count;
1160}
1161
e8f9b2ed 1162static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1163{
1164 struct mlx4_priv *priv = mlx4_priv(dev);
1165 int err;
1166
1167 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1168 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1169 if (!priv->fw.fw_icm) {
1a91de28 1170 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1171 return -ENOMEM;
1172 }
1173
1174 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1175 if (err) {
1a91de28 1176 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1177 goto err_free;
1178 }
1179
1180 err = mlx4_RUN_FW(dev);
1181 if (err) {
1a91de28 1182 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1183 goto err_unmap_fa;
1184 }
1185
1186 return 0;
1187
1188err_unmap_fa:
1189 mlx4_UNMAP_FA(dev);
1190
1191err_free:
5b0bf5e2 1192 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1193 return err;
1194}
1195
e8f9b2ed
RD		 1196static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1197 int cmpt_entry_sz)
225c7b1f
RD		 1198{
1199 struct mlx4_priv *priv = mlx4_priv(dev);
1200 int err;
ab9c17a0 1201 int num_eqs;
225c7b1f
RD		 1202
1203 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1204 cmpt_base +
1205 ((u64) (MLX4_CMPT_TYPE_QP *
1206 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1207 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1208 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1209 0, 0);
225c7b1f
RD		 1210 if (err)
1211 goto err;
1212
1213 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1214 cmpt_base +
1215 ((u64) (MLX4_CMPT_TYPE_SRQ *
1216 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1217 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1218 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1219 if (err)
1220 goto err_qp;
1221
1222 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1223 cmpt_base +
1224 ((u64) (MLX4_CMPT_TYPE_CQ *
1225 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1226 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1227 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1228 if (err)
1229 goto err_srq;
1230
7ae0e400 1231 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1232 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1233 cmpt_base +
1234 ((u64) (MLX4_CMPT_TYPE_EQ *
1235 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1236 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1237 if (err)
1238 goto err_cq;
1239
1240 return 0;
1241
1242err_cq:
1243 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1244
1245err_srq:
1246 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1247
1248err_qp:
1249 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1250
1251err:
1252 return err;
1253}
1254
3d73c288
RD		 1255static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1256 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1257{
1258 struct mlx4_priv *priv = mlx4_priv(dev);
1259 u64 aux_pages;
ab9c17a0 1260 int num_eqs;
225c7b1f
RD		 1261 int err;
1262
1263 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1264 if (err) {
1a91de28 1265 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1266 return err;
1267 }
1268
1a91de28 1269 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1270 (unsigned long long) icm_size >> 10,
1271 (unsigned long long) aux_pages << 2);
1272
1273 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1274 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1275 if (!priv->fw.aux_icm) {
1a91de28 1276 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1277 return -ENOMEM;
1278 }
1279
1280 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1281 if (err) {
1a91de28 1282 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1283 goto err_free_aux;
1284 }
1285
1286 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1287 if (err) {
1a91de28 1288 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1289 goto err_unmap_aux;
1290 }
1291
ab9c17a0 1292
7ae0e400 1293 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1294 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1295 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1296 num_eqs, num_eqs, 0, 0);
225c7b1f 1297 if (err) {
1a91de28 1298 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1299 goto err_unmap_cmpt;
1300 }
1301
d7bb58fb
JM		 1302 /*
1303 * Reserved MTT entries must be aligned up to a cacheline
1304 * boundary, since the FW will write to them, while the driver
1305 * writes to all other MTT entries. (The variable
1306 * dev->caps.mtt_entry_sz below is really the MTT segment
1307 * size, not the raw entry size)
1308 */
1309 dev->caps.reserved_mtts =
1310 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1311 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1312
225c7b1f
RD		 1313 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1314 init_hca->mtt_base,
1315 dev->caps.mtt_entry_sz,
2b8fb286 1316 dev->caps.num_mtts,
5b0bf5e2 1317 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1318 if (err) {
1a91de28 1319 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1320 goto err_unmap_eq;
1321 }
1322
1323 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1324 init_hca->dmpt_base,
1325 dev_cap->dmpt_entry_sz,
1326 dev->caps.num_mpts,
5b0bf5e2 1327 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1328 if (err) {
1a91de28 1329 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1330 goto err_unmap_mtt;
1331 }
1332
1333 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1334 init_hca->qpc_base,
1335 dev_cap->qpc_entry_sz,
1336 dev->caps.num_qps,
93fc9e1b
YP		 1337 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1338 0, 0);
225c7b1f 1339 if (err) {
1a91de28 1340 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1341 goto err_unmap_dmpt;
1342 }
1343
1344 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1345 init_hca->auxc_base,
1346 dev_cap->aux_entry_sz,
1347 dev->caps.num_qps,
93fc9e1b
YP		 1348 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1349 0, 0);
225c7b1f 1350 if (err) {
1a91de28 1351 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1352 goto err_unmap_qp;
1353 }
1354
1355 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1356 init_hca->altc_base,
1357 dev_cap->altc_entry_sz,
1358 dev->caps.num_qps,
93fc9e1b
YP		 1359 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1360 0, 0);
225c7b1f 1361 if (err) {
1a91de28 1362 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1363 goto err_unmap_auxc;
1364 }
1365
1366 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1367 init_hca->rdmarc_base,
1368 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1369 dev->caps.num_qps,
93fc9e1b
YP		 1370 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1371 0, 0);
225c7b1f
RD		 1372 if (err) {
1373 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1374 goto err_unmap_altc;
1375 }
1376
1377 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1378 init_hca->cqc_base,
1379 dev_cap->cqc_entry_sz,
1380 dev->caps.num_cqs,
5b0bf5e2 1381 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1382 if (err) {
1a91de28 1383 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1384 goto err_unmap_rdmarc;
1385 }
1386
1387 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1388 init_hca->srqc_base,
1389 dev_cap->srq_entry_sz,
1390 dev->caps.num_srqs,
5b0bf5e2 1391 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1392 if (err) {
1a91de28 1393 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1394 goto err_unmap_cq;
1395 }
1396
1397 /*
0ff1fb65
HHZ		 1398 * For flow steering device managed mode it is required to use
1399 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1400 * required, but for simplicity just map the whole multicast
1401 * group table now. The table isn't very big and it's a lot
1402 * easier than trying to track ref counts.
225c7b1f
RD		 1403 */
1404 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1405 init_hca->mc_base,
1406 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1407 dev->caps.num_mgms + dev->caps.num_amgms,
1408 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1409 0, 0);
225c7b1f 1410 if (err) {
1a91de28 1411 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1412 goto err_unmap_srq;
1413 }
1414
1415 return 0;
1416
1417err_unmap_srq:
1418 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1419
1420err_unmap_cq:
1421 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1422
1423err_unmap_rdmarc:
1424 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1425
1426err_unmap_altc:
1427 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1428
1429err_unmap_auxc:
1430 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1431
1432err_unmap_qp:
1433 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1434
1435err_unmap_dmpt:
1436 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1437
1438err_unmap_mtt:
1439 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1440
1441err_unmap_eq:
fa0681d2 1442 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1443
1444err_unmap_cmpt:
1445 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1446 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1447 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1448 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1449
1450err_unmap_aux:
1451 mlx4_UNMAP_ICM_AUX(dev);
1452
1453err_free_aux:
5b0bf5e2 1454 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1455
1456 return err;
1457}
1458
1459static void mlx4_free_icms(struct mlx4_dev *dev)
1460{
1461 struct mlx4_priv *priv = mlx4_priv(dev);
1462
1463 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1464 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1465 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1466 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1467 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1468 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1469 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1470 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1471 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1472 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1473 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1474 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1475 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1476 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1477
1478 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1479 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1480}
1481
ab9c17a0
JM		 1482static void mlx4_slave_exit(struct mlx4_dev *dev)
1483{
1484 struct mlx4_priv *priv = mlx4_priv(dev);
1485
f3d4c89e 1486 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1487 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1a91de28 1488 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1489 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1490}
1491
c1b43dca
EC		 1492static int map_bf_area(struct mlx4_dev *dev)
1493{
1494 struct mlx4_priv *priv = mlx4_priv(dev);
1495 resource_size_t bf_start;
1496 resource_size_t bf_len;
1497 int err = 0;
1498
3d747473
JM		 1499 if (!dev->caps.bf_reg_size)
1500 return -ENXIO;
1501
872bf2fb 1502 bf_start = pci_resource_start(dev->persist->pdev, 2) +
ab9c17a0 1503 (dev->caps.num_uars << PAGE_SHIFT);
872bf2fb 1504 bf_len = pci_resource_len(dev->persist->pdev, 2) -
ab9c17a0 1505 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1506 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1507 if (!priv->bf_mapping)
1508 err = -ENOMEM;
1509
1510 return err;
1511}
1512
1513static void unmap_bf_area(struct mlx4_dev *dev)
1514{
1515 if (mlx4_priv(dev)->bf_mapping)
1516 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1517}
1518
ec693d47
AV		 1519cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1520{
1521 u32 clockhi, clocklo, clockhi1;
1522 cycle_t cycles;
1523 int i;
1524 struct mlx4_priv *priv = mlx4_priv(dev);
1525
1526 for (i = 0; i < 10; i++) {
1527 clockhi = swab32(readl(priv->clock_mapping));
1528 clocklo = swab32(readl(priv->clock_mapping + 4));
1529 clockhi1 = swab32(readl(priv->clock_mapping));
1530 if (clockhi == clockhi1)
1531 break;
1532 }
1533
1534 cycles = (u64) clockhi << 32 | (u64) clocklo;
1535
1536 return cycles;
1537}
1538EXPORT_SYMBOL_GPL(mlx4_read_clock);
1539
1540
ddd8a6c1
EE		 1541static int map_internal_clock(struct mlx4_dev *dev)
1542{
1543 struct mlx4_priv *priv = mlx4_priv(dev);
1544
1545 priv->clock_mapping =
872bf2fb
YH		 1546 ioremap(pci_resource_start(dev->persist->pdev,
1547 priv->fw.clock_bar) +
ddd8a6c1
EE		 1548 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1549
1550 if (!priv->clock_mapping)
1551 return -ENOMEM;
1552
1553 return 0;
1554}
1555
1556static void unmap_internal_clock(struct mlx4_dev *dev)
1557{
1558 struct mlx4_priv *priv = mlx4_priv(dev);
1559
1560 if (priv->clock_mapping)
1561 iounmap(priv->clock_mapping);
1562}
1563
225c7b1f
RD		 1564static void mlx4_close_hca(struct mlx4_dev *dev)
1565{
ddd8a6c1 1566 unmap_internal_clock(dev);
c1b43dca 1567 unmap_bf_area(dev);
ab9c17a0
JM		 1568 if (mlx4_is_slave(dev))
1569 mlx4_slave_exit(dev);
1570 else {
1571 mlx4_CLOSE_HCA(dev, 0);
1572 mlx4_free_icms(dev);
a0eacca9
MB		 1573 }
1574}
1575
1576static void mlx4_close_fw(struct mlx4_dev *dev)
1577{
1578 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1579 mlx4_UNMAP_FA(dev);
1580 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1581 }
1582}
1583
55ad3592
YH		 1584static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1585{
1586#define COMM_CHAN_OFFLINE_OFFSET 0x09
1587
1588 u32 comm_flags;
1589 u32 offline_bit;
1590 unsigned long end;
1591 struct mlx4_priv *priv = mlx4_priv(dev);
1592
1593 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1594 while (time_before(jiffies, end)) {
1595 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1596 MLX4_COMM_CHAN_FLAGS));
1597 offline_bit = (comm_flags &
1598 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1599 if (!offline_bit)
1600 return 0;
1601 /* There are cases as part of AER/Reset flow that PF needs
1602 * around 100 msec to load. We therefore sleep for 100 msec
1603 * to allow other tasks to make use of that CPU during this
1604 * time interval.
1605 */
1606 msleep(100);
1607 }
1608 mlx4_err(dev, "Communication channel is offline.\n");
1609 return -EIO;
1610}
1611
1612static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1613{
1614#define COMM_CHAN_RST_OFFSET 0x1e
1615
1616 struct mlx4_priv *priv = mlx4_priv(dev);
1617 u32 comm_rst;
1618 u32 comm_caps;
1619
1620 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1621 MLX4_COMM_CHAN_CAPS));
1622 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1623
1624 if (comm_rst)
1625 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1626}
1627
ab9c17a0
JM		 1628static int mlx4_init_slave(struct mlx4_dev *dev)
1629{
1630 struct mlx4_priv *priv = mlx4_priv(dev);
1631 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1632 int ret_from_reset = 0;
1633 u32 slave_read;
1634 u32 cmd_channel_ver;
1635
97989356 1636 if (atomic_read(&pf_loading)) {
1a91de28 1637 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 1638 return -EPROBE_DEFER;
1639 }
1640
f3d4c89e 1641 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1642 priv->cmd.max_cmds = 1;
55ad3592
YH		 1643 if (mlx4_comm_check_offline(dev)) {
1644 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1645 goto err_offline;
1646 }
1647
1648 mlx4_reset_vf_support(dev);
ab9c17a0
JM		 1649 mlx4_warn(dev, "Sending reset\n");
1650 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1651 MLX4_COMM_TIME);
1652 /* if we are in the middle of flr the slave will try
1653 * NUM_OF_RESET_RETRIES times before leaving.*/
1654 if (ret_from_reset) {
1655 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 1656 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 1657 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1658 return -EPROBE_DEFER;
ab9c17a0
JM		 1659 } else
1660 goto err;
1661 }
1662
1663 /* check the driver version - the slave I/F revision
1664 * must match the master's */
1665 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1666 cmd_channel_ver = mlx4_comm_get_version();
1667
1668 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1669 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 1670 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 1671 goto err;
1672 }
1673
1674 mlx4_warn(dev, "Sending vhcr0\n");
1675 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1676 MLX4_COMM_TIME))
1677 goto err;
1678 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1679 MLX4_COMM_TIME))
1680 goto err;
1681 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1682 MLX4_COMM_TIME))
1683 goto err;
1684 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1685 goto err;
f3d4c89e
RD		 1686
1687 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1688 return 0;
1689
1690err:
1691 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
55ad3592 1692err_offline:
f3d4c89e 1693 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1694 return -EIO;
225c7b1f
RD		 1695}
1696
6634961c
JM		 1697static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1698{
1699 int i;
1700
1701 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1702 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1703 dev->caps.gid_table_len[i] =
449fc488 1704 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1705 else
1706 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1707 dev->caps.pkey_table_len[i] =
1708 dev->phys_caps.pkey_phys_table_len[i] - 1;
1709 }
1710}
1711
3c439b55
JM		 1712static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1713{
1714 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1715
1716 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1717 i++) {
1718 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1719 break;
1720 }
1721
1722 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1723}
1724
7d077cd3
MB		 1725static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
1726{
1727 switch (dmfs_high_steer_mode) {
1728 case MLX4_STEERING_DMFS_A0_DEFAULT:
1729 return "default performance";
1730
1731 case MLX4_STEERING_DMFS_A0_DYNAMIC:
1732 return "dynamic hybrid mode";
1733
1734 case MLX4_STEERING_DMFS_A0_STATIC:
1735 return "performance optimized for limited rule configuration (static)";
1736
1737 case MLX4_STEERING_DMFS_A0_DISABLE:
1738 return "disabled performance optimized steering";
1739
1740 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
1741 return "performance optimized steering not supported";
1742
1743 default:
1744 return "Unrecognized mode";
1745 }
1746}
1747
1748#define MLX4_DMFS_A0_STEERING (1UL << 2)
1749
7b8157be
JM		 1750static void choose_steering_mode(struct mlx4_dev *dev,
1751 struct mlx4_dev_cap *dev_cap)
1752{
7d077cd3
MB		 1753 if (mlx4_log_num_mgm_entry_size <= 0) {
1754 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
1755 if (dev->caps.dmfs_high_steer_mode ==
1756 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1757 mlx4_err(dev, "DMFS high rate mode not supported\n");
1758 else
1759 dev->caps.dmfs_high_steer_mode =
1760 MLX4_STEERING_DMFS_A0_STATIC;
1761 }
1762 }
1763
1764 if (mlx4_log_num_mgm_entry_size <= 0 &&
3c439b55 1765 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1766 (!mlx4_is_mfunc(dev) ||
872bf2fb
YH		 1767 (dev_cap->fs_max_num_qp_per_entry >=
1768 (dev->persist->num_vfs + 1))) &&
3c439b55
JM		 1769 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1770 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1771 dev->oper_log_mgm_entry_size =
1772 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1773 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1774 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1775 dev->caps.fs_log_max_ucast_qp_range_size =
1776 dev_cap->fs_log_max_ucast_qp_range_size;
1777 } else {
7d077cd3
MB		 1778 if (dev->caps.dmfs_high_steer_mode !=
1779 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1780 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
7b8157be
JM		 1781 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1782 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1783 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1784 else {
1785 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1786
1787 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1788 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 1789 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 1790 }
3c439b55
JM		 1791 dev->oper_log_mgm_entry_size =
1792 mlx4_log_num_mgm_entry_size > 0 ?
1793 mlx4_log_num_mgm_entry_size :
1794 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1795 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1796 }
1a91de28 1797 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 1798 mlx4_steering_mode_str(dev->caps.steering_mode),
1799 dev->oper_log_mgm_entry_size,
1800 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1801}
1802
7ffdf726
OG		 1803static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1804 struct mlx4_dev_cap *dev_cap)
1805{
1806 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
7d077cd3
MB		 1807 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS &&
1808 dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
7ffdf726
OG		 1809 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1810 else
1811 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1812
1813 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1814 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1815}
1816
7d077cd3
MB		 1817static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
1818{
1819 int i;
1820 struct mlx4_port_cap port_cap;
1821
1822 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1823 return -EINVAL;
1824
1825 for (i = 1; i <= dev->caps.num_ports; i++) {
1826 if (mlx4_dev_port(dev, i, &port_cap)) {
1827 mlx4_err(dev,
1828 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
1829 } else if ((dev->caps.dmfs_high_steer_mode !=
1830 MLX4_STEERING_DMFS_A0_DEFAULT) &&
1831 (port_cap.dmfs_optimized_state ==
1832 !!(dev->caps.dmfs_high_steer_mode ==
1833 MLX4_STEERING_DMFS_A0_DISABLE))) {
1834 mlx4_err(dev,
1835 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
1836 dmfs_high_rate_steering_mode_str(
1837 dev->caps.dmfs_high_steer_mode),
1838 (port_cap.dmfs_optimized_state ?
1839 "enabled" : "disabled"));
1840 }
1841 }
1842
1843 return 0;
1844}
1845
a0eacca9 1846static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 1847{
2d928651 1848 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 1849 int err = 0;
225c7b1f 1850
ab9c17a0
JM		 1851 if (!mlx4_is_slave(dev)) {
1852 err = mlx4_QUERY_FW(dev);
1853 if (err) {
1854 if (err == -EACCES)
1a91de28 1855 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 1856 else
1a91de28 1857 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 1858 return err;
ab9c17a0 1859 }
225c7b1f 1860
ab9c17a0
JM		 1861 err = mlx4_load_fw(dev);
1862 if (err) {
1a91de28 1863 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 1864 return err;
ab9c17a0 1865 }
225c7b1f 1866
ab9c17a0
JM		 1867 mlx4_cfg.log_pg_sz_m = 1;
1868 mlx4_cfg.log_pg_sz = 0;
1869 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1870 if (err)
1871 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 1872 }
2d928651 1873
a0eacca9
MB		 1874 return err;
1875}
1876
1877static int mlx4_init_hca(struct mlx4_dev *dev)
1878{
1879 struct mlx4_priv *priv = mlx4_priv(dev);
1880 struct mlx4_adapter adapter;
1881 struct mlx4_dev_cap dev_cap;
1882 struct mlx4_profile profile;
1883 struct mlx4_init_hca_param init_hca;
1884 u64 icm_size;
1885 struct mlx4_config_dev_params params;
1886 int err;
1887
1888 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1889 err = mlx4_dev_cap(dev, &dev_cap);
1890 if (err) {
1a91de28 1891 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
d0d01250 1892 return err;
ab9c17a0 1893 }
225c7b1f 1894
7b8157be 1895 choose_steering_mode(dev, &dev_cap);
7ffdf726 1896 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1897
7d077cd3
MB		 1898 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
1899 mlx4_is_master(dev))
1900 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
1901
8e1a28e8
HHZ		 1902 err = mlx4_get_phys_port_id(dev);
1903 if (err)
1904 mlx4_err(dev, "Fail to get physical port id\n");
1905
6634961c
JM		 1906 if (mlx4_is_master(dev))
1907 mlx4_parav_master_pf_caps(dev);
1908
2599d858
AV		 1909 if (mlx4_low_memory_profile()) {
1910 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
1911 profile = low_mem_profile;
1912 } else {
1913 profile = default_profile;
1914 }
0ff1fb65
HHZ		 1915 if (dev->caps.steering_mode ==
1916 MLX4_STEERING_MODE_DEVICE_MANAGED)
1917 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1918
ab9c17a0
JM		 1919 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1920 &init_hca);
1921 if ((long long) icm_size < 0) {
1922 err = icm_size;
d0d01250 1923 return err;
ab9c17a0 1924 }
225c7b1f 1925
a5bbe892
EC		 1926 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1927
ab9c17a0
JM		 1928 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1929 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1930 init_hca.mw_enabled = 0;
1931 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1932 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1933 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1934
ab9c17a0
JM		 1935 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1936 if (err)
d0d01250 1937 return err;
225c7b1f 1938
ab9c17a0
JM		 1939 err = mlx4_INIT_HCA(dev, &init_hca);
1940 if (err) {
1a91de28 1941 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 1942 goto err_free_icm;
1943 }
7ae0e400
MB		 1944
1945 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
1946 err = mlx4_query_func(dev, &dev_cap);
1947 if (err < 0) {
1948 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
d0d01250 1949 goto err_close;
7ae0e400
MB		 1950 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
1951 dev->caps.num_eqs = dev_cap.max_eqs;
1952 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
1953 dev->caps.reserved_uars = dev_cap.reserved_uars;
1954 }
1955 }
1956
ddd8a6c1
EE		 1957 /*
1958 * If TS is supported by FW
1959 * read HCA frequency by QUERY_HCA command
1960 */
1961 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1962 memset(&init_hca, 0, sizeof(init_hca));
1963 err = mlx4_QUERY_HCA(dev, &init_hca);
1964 if (err) {
1a91de28 1965 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 1966 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1967 } else {
1968 dev->caps.hca_core_clock =
1969 init_hca.hca_core_clock;
1970 }
1971
1972 /* In case we got HCA frequency 0 - disable timestamping
1973 * to avoid dividing by zero
1974 */
1975 if (!dev->caps.hca_core_clock) {
1976 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1977 mlx4_err(dev,
1a91de28 1978 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 1979 } else if (map_internal_clock(dev)) {
1980 /*
1981 * Map internal clock,
1982 * in case of failure disable timestamping
1983 */
1984 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1985 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 1986 }
1987 }
7d077cd3
MB		 1988
1989 if (dev->caps.dmfs_high_steer_mode !=
1990 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
1991 if (mlx4_validate_optimized_steering(dev))
1992 mlx4_warn(dev, "Optimized steering validation failed\n");
1993
1994 if (dev->caps.dmfs_high_steer_mode ==
1995 MLX4_STEERING_DMFS_A0_DISABLE) {
1996 dev->caps.dmfs_high_rate_qpn_base =
1997 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1998 dev->caps.dmfs_high_rate_qpn_range =
1999 MLX4_A0_STEERING_TABLE_SIZE;
2000 }
2001
2002 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2003 dmfs_high_rate_steering_mode_str(
2004 dev->caps.dmfs_high_steer_mode));
2005 }
ab9c17a0
JM		 2006 } else {
2007 err = mlx4_init_slave(dev);
2008 if (err) {
5efe5355
JM		 2009 if (err != -EPROBE_DEFER)
2010 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 2011 return err;
ab9c17a0 2012 }
225c7b1f 2013
ab9c17a0
JM		 2014 err = mlx4_slave_cap(dev);
2015 if (err) {
2016 mlx4_err(dev, "Failed to obtain slave caps\n");
2017 goto err_close;
2018 }
225c7b1f
RD		 2019 }
2020
ab9c17a0
JM		 2021 if (map_bf_area(dev))
2022 mlx4_dbg(dev, "Failed to map blue flame area\n");
2023
2024 /*Only the master set the ports, all the rest got it from it.*/
2025 if (!mlx4_is_slave(dev))
2026 mlx4_set_port_mask(dev);
2027
225c7b1f
RD		 2028 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2029 if (err) {
1a91de28 2030 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 2031 goto unmap_bf;
225c7b1f
RD		 2032 }
2033
f8c6455b
SM		 2034 /* Query CONFIG_DEV parameters */
2035 err = mlx4_config_dev_retrieval(dev, &params);
2036 if (err && err != -ENOTSUPP) {
2037 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2038 } else if (!err) {
2039 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2040 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2041 }
225c7b1f 2042 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 2043 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 2044
2045 return 0;
2046
bef772eb 2047unmap_bf:
ddd8a6c1 2048 unmap_internal_clock(dev);
bef772eb
AY		 2049 unmap_bf_area(dev);
2050
b38f2879 2051 if (mlx4_is_slave(dev)) {
99ec41d0 2052 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2053 kfree(dev->caps.qp0_tunnel);
2054 kfree(dev->caps.qp0_proxy);
2055 kfree(dev->caps.qp1_tunnel);
2056 kfree(dev->caps.qp1_proxy);
2057 }
2058
225c7b1f 2059err_close:
41929ed2
DB		 2060 if (mlx4_is_slave(dev))
2061 mlx4_slave_exit(dev);
2062 else
2063 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 2064
2065err_free_icm:
ab9c17a0
JM		 2066 if (!mlx4_is_slave(dev))
2067 mlx4_free_icms(dev);
225c7b1f 2068
225c7b1f
RD		 2069 return err;
2070}
2071
f2a3f6a3
OG		 2072static int mlx4_init_counters_table(struct mlx4_dev *dev)
2073{
2074 struct mlx4_priv *priv = mlx4_priv(dev);
2075 int nent;
2076
2077 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2078 return -ENOENT;
2079
2080 nent = dev->caps.max_counters;
2081 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
2082}
2083
2084static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2085{
2086 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2087}
2088
ba062d52 2089int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 2090{
2091 struct mlx4_priv *priv = mlx4_priv(dev);
2092
2093 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2094 return -ENOENT;
2095
2096 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2097 if (*idx == -1)
2098 return -ENOMEM;
2099
2100 return 0;
2101}
ba062d52
JM		 2102
2103int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2104{
2105 u64 out_param;
2106 int err;
2107
2108 if (mlx4_is_mfunc(dev)) {
2109 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2110 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2111 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2112 if (!err)
2113 *idx = get_param_l(&out_param);
2114
2115 return err;
2116 }
2117 return __mlx4_counter_alloc(dev, idx);
2118}
f2a3f6a3
OG		 2119EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2120
ba062d52 2121void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 2122{
7c6d74d2 2123 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 2124 return;
2125}
ba062d52
JM		 2126
2127void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2128{
e7dbeba8 2129 u64 in_param = 0;
ba062d52
JM		 2130
2131 if (mlx4_is_mfunc(dev)) {
2132 set_param_l(&in_param, idx);
2133 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2134 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2135 MLX4_CMD_WRAPPED);
2136 return;
2137 }
2138 __mlx4_counter_free(dev, idx);
2139}
f2a3f6a3
OG		 2140EXPORT_SYMBOL_GPL(mlx4_counter_free);
2141
3d73c288 2142static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 2143{
2144 struct mlx4_priv *priv = mlx4_priv(dev);
2145 int err;
7ff93f8b 2146 int port;
9a5aa622 2147 __be32 ib_port_default_caps;
225c7b1f 2148
225c7b1f
RD		 2149 err = mlx4_init_uar_table(dev);
2150 if (err) {
1a91de28
JP		 2151 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2152 return err;
225c7b1f
RD		 2153 }
2154
2155 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2156 if (err) {
1a91de28 2157 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 2158 goto err_uar_table_free;
2159 }
2160
4979d18f 2161 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 2162 if (!priv->kar) {
1a91de28 2163 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 2164 err = -ENOMEM;
2165 goto err_uar_free;
2166 }
2167
2168 err = mlx4_init_pd_table(dev);
2169 if (err) {
1a91de28 2170 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2171 goto err_kar_unmap;
2172 }
2173
012a8ff5
SH		 2174 err = mlx4_init_xrcd_table(dev);
2175 if (err) {
1a91de28 2176 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2177 goto err_pd_table_free;
2178 }
2179
225c7b1f
RD		 2180 err = mlx4_init_mr_table(dev);
2181 if (err) {
1a91de28 2182 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2183 goto err_xrcd_table_free;
225c7b1f
RD		 2184 }
2185
fe6f700d
YP		 2186 if (!mlx4_is_slave(dev)) {
2187 err = mlx4_init_mcg_table(dev);
2188 if (err) {
1a91de28 2189 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2190 goto err_mr_table_free;
2191 }
114840c3
JM		 2192 err = mlx4_config_mad_demux(dev);
2193 if (err) {
2194 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2195 goto err_mcg_table_free;
2196 }
fe6f700d
YP		 2197 }
2198
225c7b1f
RD		 2199 err = mlx4_init_eq_table(dev);
2200 if (err) {
1a91de28 2201 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2202 goto err_mcg_table_free;
225c7b1f
RD		 2203 }
2204
2205 err = mlx4_cmd_use_events(dev);
2206 if (err) {
1a91de28 2207 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2208 goto err_eq_table_free;
2209 }
2210
2211 err = mlx4_NOP(dev);
2212 if (err) {
08fb1055 2213 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2214 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
b8dd786f 2215 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1a91de28 2216 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2217 } else {
1a91de28 2218 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
b8dd786f 2219 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 2220 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2221 }
225c7b1f
RD		 2222
2223 goto err_cmd_poll;
2224 }
2225
2226 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2227
2228 err = mlx4_init_cq_table(dev);
2229 if (err) {
1a91de28 2230 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2231 goto err_cmd_poll;
2232 }
2233
2234 err = mlx4_init_srq_table(dev);
2235 if (err) {
1a91de28 2236 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2237 goto err_cq_table_free;
2238 }
2239
2240 err = mlx4_init_qp_table(dev);
2241 if (err) {
1a91de28 2242 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2243 goto err_srq_table_free;
2244 }
2245
f2a3f6a3
OG		 2246 err = mlx4_init_counters_table(dev);
2247 if (err && err != -ENOENT) {
1a91de28 2248 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
fe6f700d 2249 goto err_qp_table_free;
f2a3f6a3
OG		 2250 }
2251
ab9c17a0
JM		 2252 if (!mlx4_is_slave(dev)) {
2253 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2254 ib_port_default_caps = 0;
2255 err = mlx4_get_port_ib_caps(dev, port,
2256 &ib_port_default_caps);
2257 if (err)
1a91de28
JP		 2258 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2259 port, err);
ab9c17a0
JM		 2260 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2261
2aca1172
JM		 2262 /* initialize per-slave default ib port capabilities */
2263 if (mlx4_is_master(dev)) {
2264 int i;
2265 for (i = 0; i < dev->num_slaves; i++) {
2266 if (i == mlx4_master_func_num(dev))
2267 continue;
2268 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2269 ib_port_default_caps;
2aca1172
JM		 2270 }
2271 }
2272
096335b3
OG		 2273 if (mlx4_is_mfunc(dev))
2274 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2275 else
2276 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2277
6634961c
JM		 2278 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2279 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2280 if (err) {
2281 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2282 port);
ab9c17a0
JM		 2283 goto err_counters_table_free;
2284 }
7ff93f8b
YP		 2285 }
2286 }
2287
225c7b1f
RD		 2288 return 0;
2289
f2a3f6a3
OG		 2290err_counters_table_free:
2291 mlx4_cleanup_counters_table(dev);
2292
225c7b1f
RD		 2293err_qp_table_free:
2294 mlx4_cleanup_qp_table(dev);
2295
2296err_srq_table_free:
2297 mlx4_cleanup_srq_table(dev);
2298
2299err_cq_table_free:
2300 mlx4_cleanup_cq_table(dev);
2301
2302err_cmd_poll:
2303 mlx4_cmd_use_polling(dev);
2304
2305err_eq_table_free:
2306 mlx4_cleanup_eq_table(dev);
2307
fe6f700d
YP		 2308err_mcg_table_free:
2309 if (!mlx4_is_slave(dev))
2310 mlx4_cleanup_mcg_table(dev);
2311
ee49bd93 2312err_mr_table_free:
225c7b1f
RD		 2313 mlx4_cleanup_mr_table(dev);
2314
012a8ff5
SH		 2315err_xrcd_table_free:
2316 mlx4_cleanup_xrcd_table(dev);
2317
225c7b1f
RD		 2318err_pd_table_free:
2319 mlx4_cleanup_pd_table(dev);
2320
2321err_kar_unmap:
2322 iounmap(priv->kar);
2323
2324err_uar_free:
2325 mlx4_uar_free(dev, &priv->driver_uar);
2326
2327err_uar_table_free:
2328 mlx4_cleanup_uar_table(dev);
2329 return err;
2330}
2331
e8f9b2ed 2332static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2333{
2334 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2335 struct msix_entry *entries;
225c7b1f
RD		 2336 int i;
2337
2338 if (msi_x) {
7ae0e400
MB		 2339 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ;
2340
ca4c7b35
OG		 2341 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2342 nreq);
ab9c17a0 2343
b8dd786f
YP		 2344 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2345 if (!entries)
2346 goto no_msi;
2347
2348 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2349 entries[i].entry = i;
2350
872bf2fb
YH		 2351 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2352 nreq);
66e2f9c1
AG		 2353
2354 if (nreq < 0) {
5bf0da7d 2355 kfree(entries);
225c7b1f 2356 goto no_msi;
66e2f9c1 2357 } else if (nreq < MSIX_LEGACY_SZ +
1a91de28 2358 dev->caps.num_ports * MIN_MSIX_P_PORT) {
0b7ca5a9
YP		 2359 /*Working in legacy mode , all EQ's shared*/
2360 dev->caps.comp_pool = 0;
2361 dev->caps.num_comp_vectors = nreq - 1;
2362 } else {
2363 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2364 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2365 }
b8dd786f 2366 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2367 priv->eq_table.eq[i].irq = entries[i].vector;
2368
2369 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2370
2371 kfree(entries);
225c7b1f
RD		 2372 return;
2373 }
2374
2375no_msi:
b8dd786f 2376 dev->caps.num_comp_vectors = 1;
0b7ca5a9 2377 dev->caps.comp_pool = 0;
b8dd786f
YP		 2378
2379 for (i = 0; i < 2; ++i)
872bf2fb 2380 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
225c7b1f
RD		 2381}
2382
7ff93f8b 2383static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2384{
2385 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2386 int err = 0;
2a2336f8
YP		 2387
2388 info->dev = dev;
2389 info->port = port;
ab9c17a0 2390 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2391 mlx4_init_mac_table(dev, &info->mac_table);
2392 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2393 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2394 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2395 }
7ff93f8b
YP		 2396
2397 sprintf(info->dev_name, "mlx4_port%d", port);
2398 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2399 if (mlx4_is_mfunc(dev))
2400 info->port_attr.attr.mode = S_IRUGO;
2401 else {
2402 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2403 info->port_attr.store = set_port_type;
2404 }
7ff93f8b 2405 info->port_attr.show = show_port_type;
3691c964 2406 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b 2407
872bf2fb 2408 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
7ff93f8b
YP		 2409 if (err) {
2410 mlx4_err(dev, "Failed to create file for port %d\n", port);
2411 info->port = -1;
2412 }
2413
096335b3
OG		 2414 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2415 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2416 if (mlx4_is_mfunc(dev))
2417 info->port_mtu_attr.attr.mode = S_IRUGO;
2418 else {
2419 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2420 info->port_mtu_attr.store = set_port_ib_mtu;
2421 }
2422 info->port_mtu_attr.show = show_port_ib_mtu;
2423 sysfs_attr_init(&info->port_mtu_attr.attr);
2424
872bf2fb
YH		 2425 err = device_create_file(&dev->persist->pdev->dev,
2426 &info->port_mtu_attr);
096335b3
OG		 2427 if (err) {
2428 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
872bf2fb
YH		 2429 device_remove_file(&info->dev->persist->pdev->dev,
2430 &info->port_attr);
096335b3
OG		 2431 info->port = -1;
2432 }
2433
7ff93f8b
YP		 2434 return err;
2435}
2436
2437static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2438{
2439 if (info->port < 0)
2440 return;
2441
872bf2fb
YH		 2442 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2443 device_remove_file(&info->dev->persist->pdev->dev,
2444 &info->port_mtu_attr);
2a2336f8
YP		 2445}
2446
b12d93d6
YP		 2447static int mlx4_init_steering(struct mlx4_dev *dev)
2448{
2449 struct mlx4_priv *priv = mlx4_priv(dev);
2450 int num_entries = dev->caps.num_ports;
2451 int i, j;
2452
2453 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2454 if (!priv->steer)
2455 return -ENOMEM;
2456
45b51365 2457 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2458 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2459 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2460 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2461 }
b12d93d6
YP		 2462 return 0;
2463}
2464
2465static void mlx4_clear_steering(struct mlx4_dev *dev)
2466{
2467 struct mlx4_priv *priv = mlx4_priv(dev);
2468 struct mlx4_steer_index *entry, *tmp_entry;
2469 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2470 int num_entries = dev->caps.num_ports;
2471 int i, j;
2472
2473 for (i = 0; i < num_entries; i++) {
2474 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2475 list_for_each_entry_safe(pqp, tmp_pqp,
2476 &priv->steer[i].promisc_qps[j],
2477 list) {
2478 list_del(&pqp->list);
2479 kfree(pqp);
2480 }
2481 list_for_each_entry_safe(entry, tmp_entry,
2482 &priv->steer[i].steer_entries[j],
2483 list) {
2484 list_del(&entry->list);
2485 list_for_each_entry_safe(pqp, tmp_pqp,
2486 &entry->duplicates,
2487 list) {
2488 list_del(&pqp->list);
2489 kfree(pqp);
2490 }
2491 kfree(entry);
2492 }
2493 }
2494 }
2495 kfree(priv->steer);
2496}
2497
ab9c17a0
JM		 2498static int extended_func_num(struct pci_dev *pdev)
2499{
2500 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2501}
2502
2503#define MLX4_OWNER_BASE 0x8069c
2504#define MLX4_OWNER_SIZE 4
2505
2506static int mlx4_get_ownership(struct mlx4_dev *dev)
2507{
2508 void __iomem *owner;
2509 u32 ret;
2510
872bf2fb 2511 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 2512 return -EIO;
2513
872bf2fb
YH		 2514 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2515 MLX4_OWNER_BASE,
ab9c17a0
JM		 2516 MLX4_OWNER_SIZE);
2517 if (!owner) {
2518 mlx4_err(dev, "Failed to obtain ownership bit\n");
2519 return -ENOMEM;
2520 }
2521
2522 ret = readl(owner);
2523 iounmap(owner);
2524 return (int) !!ret;
2525}
2526
2527static void mlx4_free_ownership(struct mlx4_dev *dev)
2528{
2529 void __iomem *owner;
2530
872bf2fb 2531 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 2532 return;
2533
872bf2fb
YH		 2534 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2535 MLX4_OWNER_BASE,
ab9c17a0
JM		 2536 MLX4_OWNER_SIZE);
2537 if (!owner) {
2538 mlx4_err(dev, "Failed to obtain ownership bit\n");
2539 return;
2540 }
2541 writel(0, owner);
2542 msleep(1000);
2543 iounmap(owner);
2544}
2545
a0eacca9
MB		 2546#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2547 !!((flags) & MLX4_FLAG_MASTER))
2548
2549static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
55ad3592 2550 u8 total_vfs, int existing_vfs, int reset_flow)
a0eacca9
MB		 2551{
2552 u64 dev_flags = dev->flags;
da315679 2553 int err = 0;
a0eacca9 2554
55ad3592
YH		 2555 if (reset_flow) {
2556 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
2557 GFP_KERNEL);
2558 if (!dev->dev_vfs)
2559 goto free_mem;
2560 return dev_flags;
2561 }
2562
da315679
MB		 2563 atomic_inc(&pf_loading);
2564 if (dev->flags & MLX4_FLAG_SRIOV) {
2565 if (existing_vfs != total_vfs) {
2566 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2567 existing_vfs, total_vfs);
2568 total_vfs = existing_vfs;
2569 }
2570 }
2571
2572 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
a0eacca9
MB		 2573 if (NULL == dev->dev_vfs) {
2574 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2575 goto disable_sriov;
da315679
MB		 2576 }
2577
2578 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
2579 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2580 err = pci_enable_sriov(pdev, total_vfs);
2581 }
2582 if (err) {
2583 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2584 err);
2585 goto disable_sriov;
2586 } else {
2587 mlx4_warn(dev, "Running in master mode\n");
2588 dev_flags |= MLX4_FLAG_SRIOV |
2589 MLX4_FLAG_MASTER;
2590 dev_flags &= ~MLX4_FLAG_SLAVE;
872bf2fb 2591 dev->persist->num_vfs = total_vfs;
a0eacca9
MB		 2592 }
2593 return dev_flags;
2594
2595disable_sriov:
da315679 2596 atomic_dec(&pf_loading);
55ad3592 2597free_mem:
872bf2fb 2598 dev->persist->num_vfs = 0;
a0eacca9
MB		 2599 kfree(dev->dev_vfs);
2600 return dev_flags & ~MLX4_FLAG_MASTER;
2601}
2602
de966c59
MB		 2603enum {
2604 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2605};
2606
2607static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
2608 int *nvfs)
2609{
2610 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
2611 /* Checking for 64 VFs as a limitation of CX2 */
2612 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
2613 requested_vfs >= 64) {
2614 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
2615 requested_vfs);
2616 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
2617 }
2618 return 0;
2619}
2620
e1c00e10 2621static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
55ad3592
YH		 2622 int total_vfs, int *nvfs, struct mlx4_priv *priv,
2623 int reset_flow)
225c7b1f 2624{
225c7b1f 2625 struct mlx4_dev *dev;
e1c00e10 2626 unsigned sum = 0;
225c7b1f 2627 int err;
2a2336f8 2628 int port;
e1c00e10 2629 int i;
7ae0e400 2630 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 2631 int existing_vfs = 0;
225c7b1f 2632
e1c00e10 2633 dev = &priv->dev;
225c7b1f 2634
b581401e
RD		 2635 INIT_LIST_HEAD(&priv->ctx_list);
2636 spin_lock_init(&priv->ctx_lock);
225c7b1f 2637
7ff93f8b
YP		 2638 mutex_init(&priv->port_mutex);
2639
6296883c
YP		 2640 INIT_LIST_HEAD(&priv->pgdir_list);
2641 mutex_init(&priv->pgdir_mutex);
2642
c1b43dca
EC		 2643 INIT_LIST_HEAD(&priv->bf_list);
2644 mutex_init(&priv->bf_mutex);
2645
aca7a3ac 2646 dev->rev_id = pdev->revision;
6e7136ed 2647 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 2648
ab9c17a0 2649 /* Detect if this device is a virtual function */
839f1243 2650 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2651 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2652 dev->flags |= MLX4_FLAG_SLAVE;
2653 } else {
2654 /* We reset the device and enable SRIOV only for physical
2655 * devices. Try to claim ownership on the device;
2656 * if already taken, skip -- do not allow multiple PFs */
2657 err = mlx4_get_ownership(dev);
2658 if (err) {
2659 if (err < 0)
e1c00e10 2660 return err;
ab9c17a0 2661 else {
1a91de28 2662 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 2663 return -EINVAL;
ab9c17a0
JM		 2664 }
2665 }
aca7a3ac 2666
fe6f700d
YP		 2667 atomic_set(&priv->opreq_count, 0);
2668 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2669
ab9c17a0
JM		 2670 /*
2671 * Now reset the HCA before we touch the PCI capabilities or
2672 * attempt a firmware command, since a boot ROM may have left
2673 * the HCA in an undefined state.
2674 */
2675 err = mlx4_reset(dev);
2676 if (err) {
1a91de28 2677 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 2678 goto err_sriov;
ab9c17a0 2679 }
7ae0e400
MB		 2680
2681 if (total_vfs) {
7ae0e400 2682 dev->flags = MLX4_FLAG_MASTER;
da315679
MB		 2683 existing_vfs = pci_num_vf(pdev);
2684 if (existing_vfs)
2685 dev->flags |= MLX4_FLAG_SRIOV;
872bf2fb 2686 dev->persist->num_vfs = total_vfs;
7ae0e400 2687 }
225c7b1f
RD		 2688 }
2689
f6bc11e4
YH		 2690 /* on load remove any previous indication of internal error,
2691 * device is up.
2692 */
2693 dev->persist->state = MLX4_DEVICE_STATE_UP;
2694
ab9c17a0 2695slave_start:
521130d1
EE		 2696 err = mlx4_cmd_init(dev);
2697 if (err) {
1a91de28 2698 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 2699 goto err_sriov;
2700 }
2701
2702 /* In slave functions, the communication channel must be initialized
2703 * before posting commands. Also, init num_slaves before calling
2704 * mlx4_init_hca */
2705 if (mlx4_is_mfunc(dev)) {
7ae0e400 2706 if (mlx4_is_master(dev)) {
ab9c17a0 2707 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 2708
2709 } else {
ab9c17a0 2710 dev->num_slaves = 0;
f356fcbe
JM		 2711 err = mlx4_multi_func_init(dev);
2712 if (err) {
1a91de28 2713 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 2714 goto err_cmd;
2715 }
2716 }
225c7b1f
RD		 2717 }
2718
a0eacca9
MB		 2719 err = mlx4_init_fw(dev);
2720 if (err) {
2721 mlx4_err(dev, "Failed to init fw, aborting.\n");
2722 goto err_mfunc;
2723 }
2724
7ae0e400 2725 if (mlx4_is_master(dev)) {
da315679 2726 /* when we hit the goto slave_start below, dev_cap already initialized */
7ae0e400
MB		 2727 if (!dev_cap) {
2728 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
2729
2730 if (!dev_cap) {
2731 err = -ENOMEM;
2732 goto err_fw;
2733 }
2734
2735 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2736 if (err) {
2737 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2738 goto err_fw;
2739 }
2740
de966c59
MB		 2741 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2742 goto err_fw;
2743
7ae0e400 2744 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 2745 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
2746 total_vfs,
2747 existing_vfs,
2748 reset_flow);
7ae0e400
MB		 2749
2750 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2751 dev->flags = dev_flags;
2752 if (!SRIOV_VALID_STATE(dev->flags)) {
2753 mlx4_err(dev, "Invalid SRIOV state\n");
2754 goto err_sriov;
2755 }
2756 err = mlx4_reset(dev);
2757 if (err) {
2758 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2759 goto err_sriov;
2760 }
2761 goto slave_start;
2762 }
2763 } else {
2764 /* Legacy mode FW requires SRIOV to be enabled before
2765 * doing QUERY_DEV_CAP, since max_eq's value is different if
2766 * SRIOV is enabled.
2767 */
2768 memset(dev_cap, 0, sizeof(*dev_cap));
2769 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2770 if (err) {
2771 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2772 goto err_fw;
2773 }
de966c59
MB		 2774
2775 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2776 goto err_fw;
7ae0e400
MB		 2777 }
2778 }
2779
225c7b1f 2780 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2781 if (err) {
2782 if (err == -EACCES) {
2783 /* Not primary Physical function
2784 * Running in slave mode */
ffc39f6d 2785 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 2786 /* We're not a PF */
2787 if (dev->flags & MLX4_FLAG_SRIOV) {
2788 if (!existing_vfs)
2789 pci_disable_sriov(pdev);
55ad3592 2790 if (mlx4_is_master(dev) && !reset_flow)
a0eacca9
MB		 2791 atomic_dec(&pf_loading);
2792 dev->flags &= ~MLX4_FLAG_SRIOV;
2793 }
2794 if (!mlx4_is_slave(dev))
2795 mlx4_free_ownership(dev);
ab9c17a0
JM		 2796 dev->flags |= MLX4_FLAG_SLAVE;
2797 dev->flags &= ~MLX4_FLAG_MASTER;
2798 goto slave_start;
2799 } else
a0eacca9 2800 goto err_fw;
ab9c17a0
JM		 2801 }
2802
7ae0e400 2803 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 2804 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
2805 existing_vfs, reset_flow);
7ae0e400
MB		 2806
2807 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
2808 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
2809 dev->flags = dev_flags;
2810 err = mlx4_cmd_init(dev);
2811 if (err) {
2812 /* Only VHCR is cleaned up, so could still
2813 * send FW commands
2814 */
2815 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
2816 goto err_close;
2817 }
2818 } else {
2819 dev->flags = dev_flags;
2820 }
2821
2822 if (!SRIOV_VALID_STATE(dev->flags)) {
2823 mlx4_err(dev, "Invalid SRIOV state\n");
2824 goto err_close;
2825 }
2826 }
2827
b912b2f8
EP		 2828 /* check if the device is functioning at its maximum possible speed.
2829 * No return code for this call, just warn the user in case of PCI
2830 * express device capabilities are under-satisfied by the bus.
2831 */
83d3459a
EP		 2832 if (!mlx4_is_slave(dev))
2833 mlx4_check_pcie_caps(dev);
b912b2f8 2834
ab9c17a0
JM		 2835 /* In master functions, the communication channel must be initialized
2836 * after obtaining its address from fw */
2837 if (mlx4_is_master(dev)) {
e1c00e10
MD		 2838 int ib_ports = 0;
2839
2840 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2841 ib_ports++;
2842
2843 if (ib_ports &&
2844 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2845 mlx4_err(dev,
2846 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2847 err = -EINVAL;
2848 goto err_close;
2849 }
2850 if (dev->caps.num_ports < 2 &&
2851 num_vfs_argc > 1) {
2852 err = -EINVAL;
2853 mlx4_err(dev,
2854 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2855 dev->caps.num_ports);
ab9c17a0
JM		 2856 goto err_close;
2857 }
872bf2fb 2858 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
dd41cc3b 2859
872bf2fb
YH		 2860 for (i = 0;
2861 i < sizeof(dev->persist->nvfs)/
2862 sizeof(dev->persist->nvfs[0]); i++) {
e1c00e10
MD		 2863 unsigned j;
2864
872bf2fb 2865 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
e1c00e10
MD		 2866 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
2867 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2868 dev->caps.num_ports;
1ab95d37
MB		 2869 }
2870 }
e1c00e10
MD		 2871
2872 /* In master functions, the communication channel
2873 * must be initialized after obtaining its address from fw
2874 */
2875 err = mlx4_multi_func_init(dev);
2876 if (err) {
2877 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
2878 goto err_close;
2879 }
ab9c17a0 2880 }
225c7b1f 2881
b8dd786f
YP		 2882 err = mlx4_alloc_eq_table(dev);
2883 if (err)
ab9c17a0 2884 goto err_master_mfunc;
b8dd786f 2885
0b7ca5a9 2886 priv->msix_ctl.pool_bm = 0;
730c41d5 2887 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2888
08fb1055 2889 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2890 if ((mlx4_is_mfunc(dev)) &&
2891 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2892 err = -ENOSYS;
1a91de28 2893 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 2894 goto err_free_eq;
ab9c17a0
JM		 2895 }
2896
2897 if (!mlx4_is_slave(dev)) {
2898 err = mlx4_init_steering(dev);
2899 if (err)
e1c00e10 2900 goto err_disable_msix;
ab9c17a0 2901 }
b12d93d6 2902
225c7b1f 2903 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2904 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2905 !mlx4_is_mfunc(dev)) {
08fb1055 2906 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2907 dev->caps.num_comp_vectors = 1;
2908 dev->caps.comp_pool = 0;
08fb1055
MT		 2909 pci_disable_msix(pdev);
2910 err = mlx4_setup_hca(dev);
2911 }
2912
225c7b1f 2913 if (err)
b12d93d6 2914 goto err_steer;
225c7b1f 2915
5a0d0a61 2916 mlx4_init_quotas(dev);
55ad3592
YH		 2917 /* When PF resources are ready arm its comm channel to enable
2918 * getting commands
2919 */
2920 if (mlx4_is_master(dev)) {
2921 err = mlx4_ARM_COMM_CHANNEL(dev);
2922 if (err) {
2923 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
2924 err);
2925 goto err_steer;
2926 }
2927 }
5a0d0a61 2928
7ff93f8b
YP		 2929 for (port = 1; port <= dev->caps.num_ports; port++) {
2930 err = mlx4_init_port_info(dev, port);
2931 if (err)
2932 goto err_port;
2933 }
2a2336f8 2934
225c7b1f
RD		 2935 err = mlx4_register_device(dev);
2936 if (err)
7ff93f8b 2937 goto err_port;
225c7b1f 2938
b046ffe5
EP		 2939 mlx4_request_modules(dev);
2940
27bf91d6
YP		 2941 mlx4_sense_init(dev);
2942 mlx4_start_sense(dev);
2943
befdf897 2944 priv->removed = 0;
225c7b1f 2945
55ad3592 2946 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 2947 atomic_dec(&pf_loading);
2948
da315679 2949 kfree(dev_cap);
225c7b1f
RD		 2950 return 0;
2951
7ff93f8b 2952err_port:
b4f77264 2953 for (--port; port >= 1; --port)
7ff93f8b
YP		 2954 mlx4_cleanup_port_info(&priv->port[port]);
2955
f2a3f6a3 2956 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2957 mlx4_cleanup_qp_table(dev);
2958 mlx4_cleanup_srq_table(dev);
2959 mlx4_cleanup_cq_table(dev);
2960 mlx4_cmd_use_polling(dev);
2961 mlx4_cleanup_eq_table(dev);
fe6f700d 2962 mlx4_cleanup_mcg_table(dev);
225c7b1f 2963 mlx4_cleanup_mr_table(dev);
012a8ff5 2964 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2965 mlx4_cleanup_pd_table(dev);
2966 mlx4_cleanup_uar_table(dev);
2967
b12d93d6 2968err_steer:
ab9c17a0
JM		 2969 if (!mlx4_is_slave(dev))
2970 mlx4_clear_steering(dev);
b12d93d6 2971
e1c00e10
MD		 2972err_disable_msix:
2973 if (dev->flags & MLX4_FLAG_MSI_X)
2974 pci_disable_msix(pdev);
2975
b8dd786f
YP		 2976err_free_eq:
2977 mlx4_free_eq_table(dev);
2978
ab9c17a0
JM		 2979err_master_mfunc:
2980 if (mlx4_is_master(dev))
2981 mlx4_multi_func_cleanup(dev);
2982
b38f2879 2983 if (mlx4_is_slave(dev)) {
99ec41d0 2984 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2985 kfree(dev->caps.qp0_tunnel);
2986 kfree(dev->caps.qp0_proxy);
2987 kfree(dev->caps.qp1_tunnel);
2988 kfree(dev->caps.qp1_proxy);
2989 }
2990
225c7b1f
RD		 2991err_close:
2992 mlx4_close_hca(dev);
2993
a0eacca9
MB		 2994err_fw:
2995 mlx4_close_fw(dev);
2996
ab9c17a0
JM		 2997err_mfunc:
2998 if (mlx4_is_slave(dev))
2999 mlx4_multi_func_cleanup(dev);
3000
225c7b1f 3001err_cmd:
ffc39f6d 3002 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 3003
ab9c17a0 3004err_sriov:
55ad3592 3005 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
ab9c17a0 3006 pci_disable_sriov(pdev);
55ad3592
YH		 3007 dev->flags &= ~MLX4_FLAG_SRIOV;
3008 }
ab9c17a0 3009
55ad3592 3010 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3011 atomic_dec(&pf_loading);
3012
1ab95d37
MB		 3013 kfree(priv->dev.dev_vfs);
3014
e1c00e10
MD		 3015 if (!mlx4_is_slave(dev))
3016 mlx4_free_ownership(dev);
3017
7ae0e400 3018 kfree(dev_cap);
e1c00e10
MD		 3019 return err;
3020}
3021
3022static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3023 struct mlx4_priv *priv)
3024{
3025 int err;
3026 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3027 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3028 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3029 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3030 unsigned total_vfs = 0;
3031 unsigned int i;
3032
3033 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3034
3035 err = pci_enable_device(pdev);
3036 if (err) {
3037 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3038 return err;
3039 }
3040
3041 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3042 * per port, we must limit the number of VFs to 63 (since their are
3043 * 128 MACs)
3044 */
3045 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3046 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3047 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3048 if (nvfs[i] < 0) {
3049 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3050 err = -EINVAL;
3051 goto err_disable_pdev;
3052 }
3053 }
3054 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3055 i++) {
3056 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3057 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3058 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3059 err = -EINVAL;
3060 goto err_disable_pdev;
3061 }
3062 }
3063 if (total_vfs >= MLX4_MAX_NUM_VF) {
3064 dev_err(&pdev->dev,
3065 "Requested more VF's (%d) than allowed (%d)\n",
3066 total_vfs, MLX4_MAX_NUM_VF - 1);
3067 err = -EINVAL;
3068 goto err_disable_pdev;
3069 }
3070
3071 for (i = 0; i < MLX4_MAX_PORTS; i++) {
3072 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
3073 dev_err(&pdev->dev,
3074 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
3075 nvfs[i] + nvfs[2], i + 1,
3076 MLX4_MAX_NUM_VF_P_PORT - 1);
3077 err = -EINVAL;
3078 goto err_disable_pdev;
3079 }
3080 }
3081
3082 /* Check for BARs. */
3083 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3084 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3085 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3086 pci_dev_data, pci_resource_flags(pdev, 0));
3087 err = -ENODEV;
3088 goto err_disable_pdev;
3089 }
3090 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3091 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3092 err = -ENODEV;
3093 goto err_disable_pdev;
3094 }
3095
3096 err = pci_request_regions(pdev, DRV_NAME);
3097 if (err) {
3098 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3099 goto err_disable_pdev;
3100 }
3101
3102 pci_set_master(pdev);
3103
3104 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3105 if (err) {
3106 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3107 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3108 if (err) {
3109 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3110 goto err_release_regions;
3111 }
3112 }
3113 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3114 if (err) {
3115 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3116 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3117 if (err) {
3118 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3119 goto err_release_regions;
3120 }
3121 }
3122
3123 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3124 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3125 /* Detect if this device is a virtual function */
3126 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3127 /* When acting as pf, we normally skip vfs unless explicitly
3128 * requested to probe them.
3129 */
3130 if (total_vfs) {
3131 unsigned vfs_offset = 0;
3132
3133 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3134 vfs_offset + nvfs[i] < extended_func_num(pdev);
3135 vfs_offset += nvfs[i], i++)
3136 ;
3137 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3138 err = -ENODEV;
3139 goto err_release_regions;
3140 }
3141 if ((extended_func_num(pdev) - vfs_offset)
3142 > prb_vf[i]) {
3143 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3144 extended_func_num(pdev));
3145 err = -ENODEV;
3146 goto err_release_regions;
3147 }
3148 }
3149 }
3150
ad9a0bf0 3151 err = mlx4_catas_init(&priv->dev);
e1c00e10
MD		 3152 if (err)
3153 goto err_release_regions;
ad9a0bf0 3154
55ad3592 3155 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
ad9a0bf0
YH		 3156 if (err)
3157 goto err_catas;
3158
e1c00e10 3159 return 0;
225c7b1f 3160
ad9a0bf0
YH		 3161err_catas:
3162 mlx4_catas_end(&priv->dev);
3163
a01df0fe
RD		 3164err_release_regions:
3165 pci_release_regions(pdev);
225c7b1f
RD		 3166
3167err_disable_pdev:
3168 pci_disable_device(pdev);
3169 pci_set_drvdata(pdev, NULL);
3170 return err;
3171}
3172
1dd06ae8 3173static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 3174{
befdf897
WY		 3175 struct mlx4_priv *priv;
3176 struct mlx4_dev *dev;
e1c00e10 3177 int ret;
befdf897 3178
0a645e80 3179 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 3180
befdf897
WY		 3181 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
3182 if (!priv)
3183 return -ENOMEM;
3184
3185 dev = &priv->dev;
872bf2fb
YH		 3186 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3187 if (!dev->persist) {
3188 kfree(priv);
3189 return -ENOMEM;
3190 }
3191 dev->persist->pdev = pdev;
3192 dev->persist->dev = dev;
3193 pci_set_drvdata(pdev, dev->persist);
befdf897 3194 priv->pci_dev_data = id->driver_data;
f6bc11e4 3195 mutex_init(&dev->persist->device_state_mutex);
c69453e2 3196 mutex_init(&dev->persist->interface_state_mutex);
befdf897 3197
e1c00e10 3198 ret = __mlx4_init_one(pdev, id->driver_data, priv);
872bf2fb
YH		 3199 if (ret) {
3200 kfree(dev->persist);
e1c00e10 3201 kfree(priv);
2ba5fbd6
YH		 3202 } else {
3203 pci_save_state(pdev);
872bf2fb 3204 }
2ba5fbd6 3205
e1c00e10 3206 return ret;
3d73c288
RD		 3207}
3208
dd0eefe3
YH		 3209static void mlx4_clean_dev(struct mlx4_dev *dev)
3210{
3211 struct mlx4_dev_persistent *persist = dev->persist;
3212 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 3213 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
dd0eefe3
YH		 3214
3215 memset(priv, 0, sizeof(*priv));
3216 priv->dev.persist = persist;
55ad3592 3217 priv->dev.flags = flags;
dd0eefe3
YH		 3218}
3219
e1c00e10 3220static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f 3221{
872bf2fb
YH		 3222 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3223 struct mlx4_dev *dev = persist->dev;
225c7b1f 3224 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 3225 int pci_dev_data;
dd0eefe3 3226 int p, i;
225c7b1f 3227
befdf897
WY		 3228 if (priv->removed)
3229 return;
225c7b1f 3230
dd0eefe3
YH		 3231 /* saving current ports type for further use */
3232 for (i = 0; i < dev->caps.num_ports; i++) {
3233 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3234 dev->persist->curr_port_poss_type[i] = dev->caps.
3235 possible_type[i + 1];
3236 }
3237
befdf897 3238 pci_dev_data = priv->pci_dev_data;
225c7b1f 3239
befdf897
WY		 3240 mlx4_stop_sense(dev);
3241 mlx4_unregister_device(dev);
225c7b1f 3242
befdf897
WY		 3243 for (p = 1; p <= dev->caps.num_ports; p++) {
3244 mlx4_cleanup_port_info(&priv->port[p]);
3245 mlx4_CLOSE_PORT(dev, p);
3246 }
3247
3248 if (mlx4_is_master(dev))
3249 mlx4_free_resource_tracker(dev,
3250 RES_TR_FREE_SLAVES_ONLY);
3251
3252 mlx4_cleanup_counters_table(dev);
3253 mlx4_cleanup_qp_table(dev);
3254 mlx4_cleanup_srq_table(dev);
3255 mlx4_cleanup_cq_table(dev);
3256 mlx4_cmd_use_polling(dev);
3257 mlx4_cleanup_eq_table(dev);
3258 mlx4_cleanup_mcg_table(dev);
3259 mlx4_cleanup_mr_table(dev);
3260 mlx4_cleanup_xrcd_table(dev);
3261 mlx4_cleanup_pd_table(dev);
225c7b1f 3262
befdf897
WY		 3263 if (mlx4_is_master(dev))
3264 mlx4_free_resource_tracker(dev,
3265 RES_TR_FREE_STRUCTS_ONLY);
47605df9 3266
befdf897
WY		 3267 iounmap(priv->kar);
3268 mlx4_uar_free(dev, &priv->driver_uar);
3269 mlx4_cleanup_uar_table(dev);
3270 if (!mlx4_is_slave(dev))
3271 mlx4_clear_steering(dev);
3272 mlx4_free_eq_table(dev);
3273 if (mlx4_is_master(dev))
3274 mlx4_multi_func_cleanup(dev);
3275 mlx4_close_hca(dev);
a0eacca9 3276 mlx4_close_fw(dev);
befdf897
WY		 3277 if (mlx4_is_slave(dev))
3278 mlx4_multi_func_cleanup(dev);
ffc39f6d 3279 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 3280
befdf897
WY		 3281 if (dev->flags & MLX4_FLAG_MSI_X)
3282 pci_disable_msix(pdev);
befdf897
WY		 3283
3284 if (!mlx4_is_slave(dev))
3285 mlx4_free_ownership(dev);
3286
99ec41d0 3287 kfree(dev->caps.qp0_qkey);
befdf897
WY		 3288 kfree(dev->caps.qp0_tunnel);
3289 kfree(dev->caps.qp0_proxy);
3290 kfree(dev->caps.qp1_tunnel);
3291 kfree(dev->caps.qp1_proxy);
3292 kfree(dev->dev_vfs);
3293
dd0eefe3 3294 mlx4_clean_dev(dev);
befdf897
WY		 3295 priv->pci_dev_data = pci_dev_data;
3296 priv->removed = 1;
3297}
3298
3299static void mlx4_remove_one(struct pci_dev *pdev)
3300{
872bf2fb
YH		 3301 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3302 struct mlx4_dev *dev = persist->dev;
befdf897 3303 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 3304 int active_vfs = 0;
befdf897 3305
c69453e2
YH		 3306 mutex_lock(&persist->interface_state_mutex);
3307 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3308 mutex_unlock(&persist->interface_state_mutex);
3309
55ad3592
YH		 3310 /* Disabling SR-IOV is not allowed while there are active vf's */
3311 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3312 active_vfs = mlx4_how_many_lives_vf(dev);
3313 if (active_vfs) {
3314 pr_warn("Removing PF when there are active VF's !!\n");
3315 pr_warn("Will not disable SR-IOV.\n");
3316 }
3317 }
3318
c69453e2
YH		 3319 /* device marked to be under deletion running now without the lock
3320 * letting other tasks to be terminated
3321 */
3322 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3323 mlx4_unload_one(pdev);
3324 else
3325 mlx4_info(dev, "%s: interface is down\n", __func__);
ad9a0bf0 3326 mlx4_catas_end(dev);
55ad3592
YH		 3327 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3328 mlx4_warn(dev, "Disabling SR-IOV\n");
3329 pci_disable_sriov(pdev);
3330 }
3331
e1c00e10
MD		 3332 pci_release_regions(pdev);
3333 pci_disable_device(pdev);
872bf2fb 3334 kfree(dev->persist);
befdf897
WY		 3335 kfree(priv);
3336 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 3337}
3338
dd0eefe3
YH		 3339static int restore_current_port_types(struct mlx4_dev *dev,
3340 enum mlx4_port_type *types,
3341 enum mlx4_port_type *poss_types)
3342{
3343 struct mlx4_priv *priv = mlx4_priv(dev);
3344 int err, i;
3345
3346 mlx4_stop_sense(dev);
3347
3348 mutex_lock(&priv->port_mutex);
3349 for (i = 0; i < dev->caps.num_ports; i++)
3350 dev->caps.possible_type[i + 1] = poss_types[i];
3351 err = mlx4_change_port_types(dev, types);
3352 mlx4_start_sense(dev);
3353 mutex_unlock(&priv->port_mutex);
3354
3355 return err;
3356}
3357
ee49bd93
JM		 3358int mlx4_restart_one(struct pci_dev *pdev)
3359{
872bf2fb
YH		 3360 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3361 struct mlx4_dev *dev = persist->dev;
839f1243 3362 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 3363 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3364 int pci_dev_data, err, total_vfs;
839f1243
RD		 3365
3366 pci_dev_data = priv->pci_dev_data;
872bf2fb
YH		 3367 total_vfs = dev->persist->num_vfs;
3368 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
e1c00e10
MD		 3369
3370 mlx4_unload_one(pdev);
55ad3592 3371 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
e1c00e10
MD		 3372 if (err) {
3373 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3374 __func__, pci_name(pdev), err);
3375 return err;
3376 }
3377
dd0eefe3
YH		 3378 err = restore_current_port_types(dev, dev->persist->curr_port_type,
3379 dev->persist->curr_port_poss_type);
3380 if (err)
3381 mlx4_err(dev, "could not restore original port types (%d)\n",
3382 err);
3383
e1c00e10 3384 return err;
ee49bd93
JM		 3385}
3386
9baa3c34 3387static const struct pci_device_id mlx4_pci_table[] = {
ab9c17a0 3388 /* MT25408 "Hermon" SDR */
ca3e57a5 3389 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3390 /* MT25408 "Hermon" DDR */
ca3e57a5 3391 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3392 /* MT25408 "Hermon" QDR */
ca3e57a5 3393 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3394 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 3395 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3396 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 3397 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3398 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 3399 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3400 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 3401 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3402 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 3403 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3404 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 3405 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3406 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 3407 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3408 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 3409 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3410 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 3411 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3412 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 3413 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3414 /* MT27500 Family [ConnectX-3] */
3415 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3416 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 3417 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3418 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3419 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3420 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3421 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3422 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3423 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3424 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3425 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3426 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3427 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3428 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3429 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 3430 { 0, }
3431};
3432
3433MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3434
57dbf29a
KSS		 3435static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3436 pci_channel_state_t state)
3437{
2ba5fbd6
YH		 3438 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3439
3440 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
3441 mlx4_enter_error_state(persist);
57dbf29a 3442
2ba5fbd6
YH		 3443 mutex_lock(&persist->interface_state_mutex);
3444 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3445 mlx4_unload_one(pdev);
3446
3447 mutex_unlock(&persist->interface_state_mutex);
3448 if (state == pci_channel_io_perm_failure)
3449 return PCI_ERS_RESULT_DISCONNECT;
3450
3451 pci_disable_device(pdev);
3452 return PCI_ERS_RESULT_NEED_RESET;
57dbf29a
KSS		 3453}
3454
3455static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3456{
2ba5fbd6
YH		 3457 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3458 struct mlx4_dev *dev = persist->dev;
befdf897
WY		 3459 struct mlx4_priv *priv = mlx4_priv(dev);
3460 int ret;
2ba5fbd6
YH		 3461 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3462 int total_vfs;
97a5221f 3463
2ba5fbd6
YH		 3464 mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
3465 ret = pci_enable_device(pdev);
3466 if (ret) {
3467 mlx4_err(dev, "Can not re-enable device, ret=%d\n", ret);
3468 return PCI_ERS_RESULT_DISCONNECT;
3469 }
3470
3471 pci_set_master(pdev);
3472 pci_restore_state(pdev);
3473 pci_save_state(pdev);
3474
3475 total_vfs = dev->persist->num_vfs;
3476 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3477
3478 mutex_lock(&persist->interface_state_mutex);
3479 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
3480 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
55ad3592 3481 priv, 1);
2ba5fbd6
YH		 3482 if (ret) {
3483 mlx4_err(dev, "%s: mlx4_load_one failed, ret=%d\n",
3484 __func__, ret);
3485 goto end;
3486 }
3487
3488 ret = restore_current_port_types(dev, dev->persist->
3489 curr_port_type, dev->persist->
3490 curr_port_poss_type);
3491 if (ret)
3492 mlx4_err(dev, "could not restore original port types (%d)\n", ret);
3493 }
3494end:
3495 mutex_unlock(&persist->interface_state_mutex);
57dbf29a
KSS		 3496
3497 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3498}
3499
2ba5fbd6
YH		 3500static void mlx4_shutdown(struct pci_dev *pdev)
3501{
3502 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3503
3504 mlx4_info(persist->dev, "mlx4_shutdown was called\n");
3505 mutex_lock(&persist->interface_state_mutex);
3506 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3507 mlx4_unload_one(pdev);
3508 mutex_unlock(&persist->interface_state_mutex);
3509}
3510
3646f0e5 3511static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 3512 .error_detected = mlx4_pci_err_detected,
3513 .slot_reset = mlx4_pci_slot_reset,
3514};
3515
225c7b1f
RD		 3516static struct pci_driver mlx4_driver = {
3517 .name = DRV_NAME,
3518 .id_table = mlx4_pci_table,
3519 .probe = mlx4_init_one,
2ba5fbd6 3520 .shutdown = mlx4_shutdown,
f57e6848 3521 .remove = mlx4_remove_one,
57dbf29a 3522 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 3523};
3524
7ff93f8b
YP		 3525static int __init mlx4_verify_params(void)
3526{
3527 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 3528 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 3529 return -1;
3530 }
3531
cb29688a 3532 if (log_num_vlan != 0)
c20862c8
AV		 3533 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3534 MLX4_LOG_NUM_VLANS);
7ff93f8b 3535
ecc8fb11
AV		 3536 if (use_prio != 0)
3537 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 3538
0498628f 3539 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 3540 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3541 log_mtts_per_seg);
ab6bf42e
EC		 3542 return -1;
3543 }
3544
ab9c17a0
JM		 3545 /* Check if module param for ports type has legal combination */
3546 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 3547 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 3548 port_type_array[0] = true;
3549 }
3550
7d077cd3
MB		 3551 if (mlx4_log_num_mgm_entry_size < -7 ||
3552 (mlx4_log_num_mgm_entry_size > 0 &&
3553 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3554 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
3555 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
1a91de28
JP		 3556 mlx4_log_num_mgm_entry_size,
3557 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3558 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 3559 return -1;
3560 }
3561
7ff93f8b
YP		 3562 return 0;
3563}
3564
225c7b1f
RD		 3565static int __init mlx4_init(void)
3566{
3567 int ret;
3568
7ff93f8b
YP		 3569 if (mlx4_verify_params())
3570 return -EINVAL;
3571
27bf91d6
YP		 3572
3573 mlx4_wq = create_singlethread_workqueue("mlx4");
3574 if (!mlx4_wq)
3575 return -ENOMEM;
ee49bd93 3576
225c7b1f 3577 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 3578 if (ret < 0)
3579 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3580 return ret < 0 ? ret : 0;
3581}
3582
3583static void __exit mlx4_cleanup(void)
3584{
3585 pci_unregister_driver(&mlx4_driver);
27bf91d6 3586 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3587}
3588
3589module_init(mlx4_init);
3590module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)