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IB/mlx4: Set bad_wr for invalid send opcode
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
225c7b1f
RD		 44
45#include <linux/mlx4/device.h>
46#include <linux/mlx4/doorbell.h>
47
48#include "mlx4.h"
49#include "fw.h"
50#include "icm.h"
51
52MODULE_AUTHOR("Roland Dreier");
53MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
54MODULE_LICENSE("Dual BSD/GPL");
55MODULE_VERSION(DRV_VERSION);
56
27bf91d6
YP		 57struct workqueue_struct *mlx4_wq;
58
225c7b1f
RD		 59#ifdef CONFIG_MLX4_DEBUG
60
61int mlx4_debug_level = 0;
62module_param_named(debug_level, mlx4_debug_level, int, 0644);
63MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
64
65#endif /* CONFIG_MLX4_DEBUG */
66
67#ifdef CONFIG_PCI_MSI
68
08fb1055 69static int msi_x = 1;
225c7b1f
RD		 70module_param(msi_x, int, 0444);
71MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
72
73#else /* CONFIG_PCI_MSI */
74
75#define msi_x (0)
76
77#endif /* CONFIG_PCI_MSI */
78
ab9c17a0
JM		 79static int num_vfs;
80module_param(num_vfs, int, 0444);
81MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
82
83static int probe_vf;
84module_param(probe_vf, int, 0644);
85MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
86
0ec2c0f8
EE		 87int mlx4_log_num_mgm_entry_size = 10;
88module_param_named(log_num_mgm_entry_size,
89 mlx4_log_num_mgm_entry_size, int, 0444);
90MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
91 " of qp per mcg, for example:"
92 " 10 gives 248.range: 9<="
93 " log_num_mgm_entry_size <= 12");
94
ab9c17a0
JM		 95#define MLX4_VF (1 << 0)
96
97#define HCA_GLOBAL_CAP_MASK 0
98#define PF_CONTEXT_BEHAVIOUR_MASK 0
99
f33afc26 100static char mlx4_version[] __devinitdata =
225c7b1f
RD		 101 DRV_NAME ": Mellanox ConnectX core driver v"
102 DRV_VERSION " (" DRV_RELDATE ")\n";
103
104static struct mlx4_profile default_profile = {
ab9c17a0 105 .num_qp = 1 << 18,
225c7b1f 106 .num_srq = 1 << 16,
c9f2ba5e 107 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 108 .num_cq = 1 << 16,
109 .num_mcg = 1 << 13,
ab9c17a0 110 .num_mpt = 1 << 19,
9fd7a1e1 111 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 112};
113
ab9c17a0 114static int log_num_mac = 7;
93fc9e1b
YP		 115module_param_named(log_num_mac, log_num_mac, int, 0444);
116MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
117
118static int log_num_vlan;
119module_param_named(log_num_vlan, log_num_vlan, int, 0444);
120MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 121/* Log2 max number of VLANs per ETH port (0-7) */
122#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 123
eb939922 124static bool use_prio;
93fc9e1b
YP		 125module_param_named(use_prio, use_prio, bool, 0444);
126MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
127 "(0/1, default 0)");
128
2b8fb286 129int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 130module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 131MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 132
8d0fc7b6 133static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 134static int arr_argc = 2;
135module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 136MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
137 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 138
139struct mlx4_port_config {
140 struct list_head list;
141 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
142 struct pci_dev *pdev;
143};
144
145static inline int mlx4_master_get_num_eqs(struct mlx4_dev *dev)
146{
147 return dev->caps.reserved_eqs +
148 MLX4_MFUNC_EQ_NUM * (dev->num_slaves + 1);
149}
150
27bf91d6
YP		 151int mlx4_check_port_params(struct mlx4_dev *dev,
152 enum mlx4_port_type *port_type)
7ff93f8b
YP		 153{
154 int i;
155
156 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 157 if (port_type[i] != port_type[i + 1]) {
158 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
159 mlx4_err(dev, "Only same port types supported "
160 "on this HCA, aborting.\n");
161 return -EINVAL;
162 }
163 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
164 port_type[i + 1] == MLX4_PORT_TYPE_IB)
165 return -EINVAL;
7ff93f8b
YP		 166 }
167 }
7ff93f8b
YP		 168
169 for (i = 0; i < dev->caps.num_ports; i++) {
170 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
171 mlx4_err(dev, "Requested port type for port %d is not "
172 "supported on this HCA\n", i + 1);
173 return -EINVAL;
174 }
175 }
176 return 0;
177}
178
179static void mlx4_set_port_mask(struct mlx4_dev *dev)
180{
181 int i;
182
7ff93f8b 183 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 184 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 185}
f2a3f6a3 186
3d73c288 187static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 188{
189 int err;
5ae2a7a8 190 int i;
225c7b1f
RD		 191
192 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
193 if (err) {
194 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
195 return err;
196 }
197
198 if (dev_cap->min_page_sz > PAGE_SIZE) {
199 mlx4_err(dev, "HCA minimum page size of %d bigger than "
200 "kernel PAGE_SIZE of %ld, aborting.\n",
201 dev_cap->min_page_sz, PAGE_SIZE);
202 return -ENODEV;
203 }
204 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
205 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
206 "aborting.\n",
207 dev_cap->num_ports, MLX4_MAX_PORTS);
208 return -ENODEV;
209 }
210
211 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
212 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
213 "PCI resource 2 size of 0x%llx, aborting.\n",
214 dev_cap->uar_size,
215 (unsigned long long) pci_resource_len(dev->pdev, 2));
216 return -ENODEV;
217 }
218
219 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 220 for (i = 1; i <= dev->caps.num_ports; ++i) {
221 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 222 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
5ae2a7a8
RD		 223 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
224 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
225 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 226 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
227 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 228 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 229 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
230 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 231 dev->caps.trans_type[i] = dev_cap->trans_type[i];
232 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
233 dev->caps.wavelength[i] = dev_cap->wavelength[i];
234 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 235 }
236
ab9c17a0 237 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 238 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 239 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
240 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
241 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
242 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
243 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
244 dev->caps.max_wqes = dev_cap->max_qp_sz;
245 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 246 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
247 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
248 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
249 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
250 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
0ec2c0f8 251 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
225c7b1f
RD		 252 /*
253 * Subtract 1 from the limit because we need to allocate a
254 * spare CQE so the HCA HW can tell the difference between an
255 * empty CQ and a full CQ.
256 */
257 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
258 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
259 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 260 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 261 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 262
263 /* The first 128 UARs are used for EQ doorbells */
264 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 265 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 266 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
267 dev_cap->reserved_xrcds : 0;
268 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
269 dev_cap->max_xrcds : 0;
2b8fb286
MA		 270 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
271
149983af 272 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 273 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
274 dev->caps.flags = dev_cap->flags;
95d04f07
RD		 275 dev->caps.bmme_flags = dev_cap->bmme_flags;
276 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 277 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 278 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
225c7b1f 279
58a60168
YP		 280 /* Sense port always allowed on supported devices for ConnectX1 and 2 */
281 if (dev->pdev->device != 0x1003)
282 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
283
93fc9e1b 284 dev->caps.log_num_macs = log_num_mac;
cb29688a 285 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 286 dev->caps.log_num_prios = use_prio ? 3 : 0;
287
288 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 289 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
290 if (dev->caps.supported_type[i]) {
291 /* if only ETH is supported - assign ETH */
292 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
293 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
294 /* if only IB is supported,
295 * assign IB only if SRIOV is off*/
296 else if (dev->caps.supported_type[i] ==
297 MLX4_PORT_TYPE_IB) {
298 if (dev->flags & MLX4_FLAG_SRIOV)
299 dev->caps.port_type[i] =
300 MLX4_PORT_TYPE_NONE;
301 else
302 dev->caps.port_type[i] =
303 MLX4_PORT_TYPE_IB;
304 /* if IB and ETH are supported,
305 * first of all check if SRIOV is on */
306 } else if (dev->flags & MLX4_FLAG_SRIOV)
307 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
ab9c17a0 308 else {
8d0fc7b6
YP		 309 /* In non-SRIOV mode, we set the port type
310 * according to user selection of port type,
311 * if usere selected none, take the FW hint */
312 if (port_type_array[i-1] == MLX4_PORT_TYPE_NONE)
313 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
314 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 315 else
8d0fc7b6 316 dev->caps.port_type[i] = port_type_array[i-1];
ab9c17a0
JM		 317 }
318 }
8d0fc7b6
YP		 319 /*
320 * Link sensing is allowed on the port if 3 conditions are true:
321 * 1. Both protocols are supported on the port.
322 * 2. Different types are supported on the port
323 * 3. FW declared that it supports link sensing
324 */
27bf91d6 325 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 326 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 327 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 328 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 329
8d0fc7b6
YP		 330 /*
331 * If "default_sense" bit is set, we move the port to "AUTO" mode
332 * and perform sense_port FW command to try and set the correct
333 * port type from beginning
334 */
46c46747 335 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 336 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
337 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
338 mlx4_SENSE_PORT(dev, i, &sensed_port);
339 if (sensed_port != MLX4_PORT_TYPE_NONE)
340 dev->caps.port_type[i] = sensed_port;
341 } else {
342 dev->caps.possible_type[i] = dev->caps.port_type[i];
343 }
344
93fc9e1b
YP		 345 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
346 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
347 mlx4_warn(dev, "Requested number of MACs is too much "
348 "for port %d, reducing to %d.\n",
349 i, 1 << dev->caps.log_num_macs);
350 }
351 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
352 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
353 mlx4_warn(dev, "Requested number of VLANs is too much "
354 "for port %d, reducing to %d.\n",
355 i, 1 << dev->caps.log_num_vlans);
356 }
357 }
358
f2a3f6a3
OG		 359 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
360
93fc9e1b
YP		 361 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
362 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
363 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
364 (1 << dev->caps.log_num_macs) *
365 (1 << dev->caps.log_num_vlans) *
366 (1 << dev->caps.log_num_prios) *
367 dev->caps.num_ports;
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
369
370 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
371 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
372 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
373 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
374
225c7b1f
RD		 375 return 0;
376}
ab9c17a0
JM		 377/*The function checks if there are live vf, return the num of them*/
378static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
379{
380 struct mlx4_priv *priv = mlx4_priv(dev);
381 struct mlx4_slave_state *s_state;
382 int i;
383 int ret = 0;
384
385 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
386 s_state = &priv->mfunc.master.slave_state[i];
387 if (s_state->active && s_state->last_cmd !=
388 MLX4_COMM_CMD_RESET) {
389 mlx4_warn(dev, "%s: slave: %d is still active\n",
390 __func__, i);
391 ret++;
392 }
393 }
394 return ret;
395}
396
397static int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
398{
399 struct mlx4_priv *priv = mlx4_priv(dev);
400 struct mlx4_slave_state *s_slave;
401
402 if (!mlx4_is_master(dev))
403 return 0;
404
405 s_slave = &priv->mfunc.master.slave_state[slave];
406 return !!s_slave->active;
407}
408EXPORT_SYMBOL(mlx4_is_slave_active);
409
410static int mlx4_slave_cap(struct mlx4_dev *dev)
411{
412 int err;
413 u32 page_size;
414 struct mlx4_dev_cap dev_cap;
415 struct mlx4_func_cap func_cap;
416 struct mlx4_init_hca_param hca_param;
417 int i;
418
419 memset(&hca_param, 0, sizeof(hca_param));
420 err = mlx4_QUERY_HCA(dev, &hca_param);
421 if (err) {
422 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
423 return err;
424 }
425
426 /*fail if the hca has an unknown capability */
427 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
428 HCA_GLOBAL_CAP_MASK) {
429 mlx4_err(dev, "Unknown hca global capabilities\n");
430 return -ENOSYS;
431 }
432
433 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
434
435 memset(&dev_cap, 0, sizeof(dev_cap));
436 err = mlx4_dev_cap(dev, &dev_cap);
437 if (err) {
438 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
439 return err;
440 }
441
442 page_size = ~dev->caps.page_size_cap + 1;
443 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
444 if (page_size > PAGE_SIZE) {
445 mlx4_err(dev, "HCA minimum page size of %d bigger than "
446 "kernel PAGE_SIZE of %ld, aborting.\n",
447 page_size, PAGE_SIZE);
448 return -ENODEV;
449 }
450
451 /* slave gets uar page size from QUERY_HCA fw command */
452 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
453
454 /* TODO: relax this assumption */
455 if (dev->caps.uar_page_size != PAGE_SIZE) {
456 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
457 dev->caps.uar_page_size, PAGE_SIZE);
458 return -ENODEV;
459 }
460
461 memset(&func_cap, 0, sizeof(func_cap));
462 err = mlx4_QUERY_FUNC_CAP(dev, &func_cap);
463 if (err) {
464 mlx4_err(dev, "QUERY_FUNC_CAP command failed, aborting.\n");
465 return err;
466 }
467
468 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
469 PF_CONTEXT_BEHAVIOUR_MASK) {
470 mlx4_err(dev, "Unknown pf context behaviour\n");
471 return -ENOSYS;
472 }
473
ab9c17a0
JM		 474 dev->caps.num_ports = func_cap.num_ports;
475 dev->caps.num_qps = func_cap.qp_quota;
476 dev->caps.num_srqs = func_cap.srq_quota;
477 dev->caps.num_cqs = func_cap.cq_quota;
478 dev->caps.num_eqs = func_cap.max_eq;
479 dev->caps.reserved_eqs = func_cap.reserved_eq;
480 dev->caps.num_mpts = func_cap.mpt_quota;
481 dev->caps.num_mtts = func_cap.mtt_quota;
482 dev->caps.num_pds = MLX4_NUM_PDS;
483 dev->caps.num_mgms = 0;
484 dev->caps.num_amgms = 0;
485
486 for (i = 1; i <= dev->caps.num_ports; ++i)
487 dev->caps.port_mask[i] = dev->caps.port_type[i];
488
489 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
490 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
491 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
492 return -ENODEV;
493 }
494
495 if (dev->caps.uar_page_size * (dev->caps.num_uars -
496 dev->caps.reserved_uars) >
497 pci_resource_len(dev->pdev, 2)) {
498 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
499 "PCI resource 2 size of 0x%llx, aborting.\n",
500 dev->caps.uar_page_size * dev->caps.num_uars,
501 (unsigned long long) pci_resource_len(dev->pdev, 2));
502 return -ENODEV;
503 }
504
505#if 0
506 mlx4_warn(dev, "sqp_demux:%d\n", dev->caps.sqp_demux);
507 mlx4_warn(dev, "num_uars:%d reserved_uars:%d uar region:0x%x bar2:0x%llx\n",
508 dev->caps.num_uars, dev->caps.reserved_uars,
509 dev->caps.uar_page_size * dev->caps.num_uars,
510 pci_resource_len(dev->pdev, 2));
511 mlx4_warn(dev, "num_eqs:%d reserved_eqs:%d\n", dev->caps.num_eqs,
512 dev->caps.reserved_eqs);
513 mlx4_warn(dev, "num_pds:%d reserved_pds:%d slave_pd_shift:%d pd_base:%d\n",
514 dev->caps.num_pds, dev->caps.reserved_pds,
515 dev->caps.slave_pd_shift, dev->caps.pd_base);
516#endif
517 return 0;
518}
225c7b1f 519
7ff93f8b
YP		 520/*
521 * Change the port configuration of the device.
522 * Every user of this function must hold the port mutex.
523 */
27bf91d6
YP		 524int mlx4_change_port_types(struct mlx4_dev *dev,
525 enum mlx4_port_type *port_types)
7ff93f8b
YP		 526{
527 int err = 0;
528 int change = 0;
529 int port;
530
531 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 532 /* Change the port type only if the new type is different
533 * from the current, and not set to Auto */
7ff93f8b
YP		 534 if (port_types[port] != dev->caps.port_type[port + 1]) {
535 change = 1;
536 dev->caps.port_type[port + 1] = port_types[port];
537 }
538 }
539 if (change) {
540 mlx4_unregister_device(dev);
541 for (port = 1; port <= dev->caps.num_ports; port++) {
542 mlx4_CLOSE_PORT(dev, port);
543 err = mlx4_SET_PORT(dev, port);
544 if (err) {
545 mlx4_err(dev, "Failed to set port %d, "
546 "aborting\n", port);
547 goto out;
548 }
549 }
550 mlx4_set_port_mask(dev);
551 err = mlx4_register_device(dev);
552 }
553
554out:
555 return err;
556}
557
558static ssize_t show_port_type(struct device *dev,
559 struct device_attribute *attr,
560 char *buf)
561{
562 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
563 port_attr);
564 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 565 char type[8];
566
567 sprintf(type, "%s",
568 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
569 "ib" : "eth");
570 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
571 sprintf(buf, "auto (%s)\n", type);
572 else
573 sprintf(buf, "%s\n", type);
7ff93f8b 574
27bf91d6 575 return strlen(buf);
7ff93f8b
YP		 576}
577
578static ssize_t set_port_type(struct device *dev,
579 struct device_attribute *attr,
580 const char *buf, size_t count)
581{
582 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
583 port_attr);
584 struct mlx4_dev *mdev = info->dev;
585 struct mlx4_priv *priv = mlx4_priv(mdev);
586 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 587 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 588 int i;
589 int err = 0;
590
591 if (!strcmp(buf, "ib\n"))
592 info->tmp_type = MLX4_PORT_TYPE_IB;
593 else if (!strcmp(buf, "eth\n"))
594 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 595 else if (!strcmp(buf, "auto\n"))
596 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 597 else {
598 mlx4_err(mdev, "%s is not supported port type\n", buf);
599 return -EINVAL;
600 }
601
27bf91d6 602 mlx4_stop_sense(mdev);
7ff93f8b 603 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 604 /* Possible type is always the one that was delivered */
605 mdev->caps.possible_type[info->port] = info->tmp_type;
606
607 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 608 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 609 mdev->caps.possible_type[i+1];
610 if (types[i] == MLX4_PORT_TYPE_AUTO)
611 types[i] = mdev->caps.port_type[i+1];
612 }
7ff93f8b 613
58a60168
YP		 614 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
615 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 616 for (i = 1; i <= mdev->caps.num_ports; i++) {
617 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
618 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
619 err = -EINVAL;
620 }
621 }
622 }
623 if (err) {
624 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
625 "Set only 'eth' or 'ib' for both ports "
626 "(should be the same)\n");
627 goto out;
628 }
629
630 mlx4_do_sense_ports(mdev, new_types, types);
631
632 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 633 if (err)
634 goto out;
635
27bf91d6
YP		 636 /* We are about to apply the changes after the configuration
637 * was verified, no need to remember the temporary types
638 * any more */
639 for (i = 0; i < mdev->caps.num_ports; i++)
640 priv->port[i + 1].tmp_type = 0;
7ff93f8b 641
27bf91d6 642 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 643
644out:
27bf91d6 645 mlx4_start_sense(mdev);
7ff93f8b
YP		 646 mutex_unlock(&priv->port_mutex);
647 return err ? err : count;
648}
649
e8f9b2ed 650static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 651{
652 struct mlx4_priv *priv = mlx4_priv(dev);
653 int err;
654
655 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 656 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 657 if (!priv->fw.fw_icm) {
658 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
659 return -ENOMEM;
660 }
661
662 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
663 if (err) {
664 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
665 goto err_free;
666 }
667
668 err = mlx4_RUN_FW(dev);
669 if (err) {
670 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
671 goto err_unmap_fa;
672 }
673
674 return 0;
675
676err_unmap_fa:
677 mlx4_UNMAP_FA(dev);
678
679err_free:
5b0bf5e2 680 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 681 return err;
682}
683
e8f9b2ed
RD		 684static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
685 int cmpt_entry_sz)
225c7b1f
RD		 686{
687 struct mlx4_priv *priv = mlx4_priv(dev);
688 int err;
ab9c17a0 689 int num_eqs;
225c7b1f
RD		 690
691 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
692 cmpt_base +
693 ((u64) (MLX4_CMPT_TYPE_QP *
694 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
695 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 696 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
697 0, 0);
225c7b1f
RD		 698 if (err)
699 goto err;
700
701 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
702 cmpt_base +
703 ((u64) (MLX4_CMPT_TYPE_SRQ *
704 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
705 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 706 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 707 if (err)
708 goto err_qp;
709
710 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
711 cmpt_base +
712 ((u64) (MLX4_CMPT_TYPE_CQ *
713 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
714 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 715 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 716 if (err)
717 goto err_srq;
718
ab9c17a0
JM		 719 num_eqs = (mlx4_is_master(dev)) ?
720 roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) :
721 dev->caps.num_eqs;
225c7b1f
RD		 722 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
723 cmpt_base +
724 ((u64) (MLX4_CMPT_TYPE_EQ *
725 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 726 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 727 if (err)
728 goto err_cq;
729
730 return 0;
731
732err_cq:
733 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
734
735err_srq:
736 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
737
738err_qp:
739 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
740
741err:
742 return err;
743}
744
3d73c288
RD		 745static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
746 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 747{
748 struct mlx4_priv *priv = mlx4_priv(dev);
749 u64 aux_pages;
ab9c17a0 750 int num_eqs;
225c7b1f
RD		 751 int err;
752
753 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
754 if (err) {
755 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
756 return err;
757 }
758
759 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
760 (unsigned long long) icm_size >> 10,
761 (unsigned long long) aux_pages << 2);
762
763 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 764 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 765 if (!priv->fw.aux_icm) {
766 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
767 return -ENOMEM;
768 }
769
770 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
771 if (err) {
772 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
773 goto err_free_aux;
774 }
775
776 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
777 if (err) {
778 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
779 goto err_unmap_aux;
780 }
781
ab9c17a0
JM		 782
783 num_eqs = (mlx4_is_master(dev)) ?
784 roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) :
785 dev->caps.num_eqs;
fa0681d2
RD		 786 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
787 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 788 num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 789 if (err) {
790 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
791 goto err_unmap_cmpt;
792 }
793
d7bb58fb
JM		 794 /*
795 * Reserved MTT entries must be aligned up to a cacheline
796 * boundary, since the FW will write to them, while the driver
797 * writes to all other MTT entries. (The variable
798 * dev->caps.mtt_entry_sz below is really the MTT segment
799 * size, not the raw entry size)
800 */
801 dev->caps.reserved_mtts =
802 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
803 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
804
225c7b1f
RD		 805 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
806 init_hca->mtt_base,
807 dev->caps.mtt_entry_sz,
2b8fb286 808 dev->caps.num_mtts,
5b0bf5e2 809 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 810 if (err) {
811 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
812 goto err_unmap_eq;
813 }
814
815 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
816 init_hca->dmpt_base,
817 dev_cap->dmpt_entry_sz,
818 dev->caps.num_mpts,
5b0bf5e2 819 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 820 if (err) {
821 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
822 goto err_unmap_mtt;
823 }
824
825 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
826 init_hca->qpc_base,
827 dev_cap->qpc_entry_sz,
828 dev->caps.num_qps,
93fc9e1b
YP		 829 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
830 0, 0);
225c7b1f
RD		 831 if (err) {
832 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
833 goto err_unmap_dmpt;
834 }
835
836 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
837 init_hca->auxc_base,
838 dev_cap->aux_entry_sz,
839 dev->caps.num_qps,
93fc9e1b
YP		 840 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
841 0, 0);
225c7b1f
RD		 842 if (err) {
843 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
844 goto err_unmap_qp;
845 }
846
847 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
848 init_hca->altc_base,
849 dev_cap->altc_entry_sz,
850 dev->caps.num_qps,
93fc9e1b
YP		 851 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
852 0, 0);
225c7b1f
RD		 853 if (err) {
854 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
855 goto err_unmap_auxc;
856 }
857
858 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
859 init_hca->rdmarc_base,
860 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
861 dev->caps.num_qps,
93fc9e1b
YP		 862 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
863 0, 0);
225c7b1f
RD		 864 if (err) {
865 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
866 goto err_unmap_altc;
867 }
868
869 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
870 init_hca->cqc_base,
871 dev_cap->cqc_entry_sz,
872 dev->caps.num_cqs,
5b0bf5e2 873 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 874 if (err) {
875 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
876 goto err_unmap_rdmarc;
877 }
878
879 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
880 init_hca->srqc_base,
881 dev_cap->srq_entry_sz,
882 dev->caps.num_srqs,
5b0bf5e2 883 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 884 if (err) {
885 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
886 goto err_unmap_cq;
887 }
888
889 /*
890 * It's not strictly required, but for simplicity just map the
891 * whole multicast group table now. The table isn't very big
892 * and it's a lot easier than trying to track ref counts.
893 */
894 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 895 init_hca->mc_base,
896 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 897 dev->caps.num_mgms + dev->caps.num_amgms,
898 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 899 0, 0);
225c7b1f
RD		 900 if (err) {
901 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
902 goto err_unmap_srq;
903 }
904
905 return 0;
906
907err_unmap_srq:
908 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
909
910err_unmap_cq:
911 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
912
913err_unmap_rdmarc:
914 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
915
916err_unmap_altc:
917 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
918
919err_unmap_auxc:
920 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
921
922err_unmap_qp:
923 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
924
925err_unmap_dmpt:
926 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
927
928err_unmap_mtt:
929 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
930
931err_unmap_eq:
fa0681d2 932 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 933
934err_unmap_cmpt:
935 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
936 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
937 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
938 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
939
940err_unmap_aux:
941 mlx4_UNMAP_ICM_AUX(dev);
942
943err_free_aux:
5b0bf5e2 944 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 945
946 return err;
947}
948
949static void mlx4_free_icms(struct mlx4_dev *dev)
950{
951 struct mlx4_priv *priv = mlx4_priv(dev);
952
953 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
954 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
955 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
956 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
957 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
958 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
959 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
960 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
961 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 962 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 963 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
964 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
965 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
966 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 967
968 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 969 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 970}
971
ab9c17a0
JM		 972static void mlx4_slave_exit(struct mlx4_dev *dev)
973{
974 struct mlx4_priv *priv = mlx4_priv(dev);
975
976 down(&priv->cmd.slave_sem);
977 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
978 mlx4_warn(dev, "Failed to close slave function.\n");
979 up(&priv->cmd.slave_sem);
980}
981
c1b43dca
EC		 982static int map_bf_area(struct mlx4_dev *dev)
983{
984 struct mlx4_priv *priv = mlx4_priv(dev);
985 resource_size_t bf_start;
986 resource_size_t bf_len;
987 int err = 0;
988
ab9c17a0
JM		 989 bf_start = pci_resource_start(dev->pdev, 2) +
990 (dev->caps.num_uars << PAGE_SHIFT);
991 bf_len = pci_resource_len(dev->pdev, 2) -
992 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 993 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
994 if (!priv->bf_mapping)
995 err = -ENOMEM;
996
997 return err;
998}
999
1000static void unmap_bf_area(struct mlx4_dev *dev)
1001{
1002 if (mlx4_priv(dev)->bf_mapping)
1003 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1004}
1005
225c7b1f
RD		 1006static void mlx4_close_hca(struct mlx4_dev *dev)
1007{
c1b43dca 1008 unmap_bf_area(dev);
ab9c17a0
JM		 1009 if (mlx4_is_slave(dev))
1010 mlx4_slave_exit(dev);
1011 else {
1012 mlx4_CLOSE_HCA(dev, 0);
1013 mlx4_free_icms(dev);
1014 mlx4_UNMAP_FA(dev);
1015 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1016 }
1017}
1018
1019static int mlx4_init_slave(struct mlx4_dev *dev)
1020{
1021 struct mlx4_priv *priv = mlx4_priv(dev);
1022 u64 dma = (u64) priv->mfunc.vhcr_dma;
1023 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1024 int ret_from_reset = 0;
1025 u32 slave_read;
1026 u32 cmd_channel_ver;
1027
1028 down(&priv->cmd.slave_sem);
1029 priv->cmd.max_cmds = 1;
1030 mlx4_warn(dev, "Sending reset\n");
1031 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1032 MLX4_COMM_TIME);
1033 /* if we are in the middle of flr the slave will try
1034 * NUM_OF_RESET_RETRIES times before leaving.*/
1035 if (ret_from_reset) {
1036 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1037 msleep(SLEEP_TIME_IN_RESET);
1038 while (ret_from_reset && num_of_reset_retries) {
1039 mlx4_warn(dev, "slave is currently in the"
1040 "middle of FLR. retrying..."
1041 "(try num:%d)\n",
1042 (NUM_OF_RESET_RETRIES -
1043 num_of_reset_retries + 1));
1044 ret_from_reset =
1045 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1046 0, MLX4_COMM_TIME);
1047 num_of_reset_retries = num_of_reset_retries - 1;
1048 }
1049 } else
1050 goto err;
1051 }
1052
1053 /* check the driver version - the slave I/F revision
1054 * must match the master's */
1055 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1056 cmd_channel_ver = mlx4_comm_get_version();
1057
1058 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1059 MLX4_COMM_GET_IF_REV(slave_read)) {
1060 mlx4_err(dev, "slave driver version is not supported"
1061 " by the master\n");
1062 goto err;
1063 }
1064
1065 mlx4_warn(dev, "Sending vhcr0\n");
1066 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1067 MLX4_COMM_TIME))
1068 goto err;
1069 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1070 MLX4_COMM_TIME))
1071 goto err;
1072 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1073 MLX4_COMM_TIME))
1074 goto err;
1075 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1076 goto err;
1077 up(&priv->cmd.slave_sem);
1078 return 0;
1079
1080err:
1081 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1082 up(&priv->cmd.slave_sem);
1083 return -EIO;
225c7b1f
RD		 1084}
1085
3d73c288 1086static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1087{
1088 struct mlx4_priv *priv = mlx4_priv(dev);
1089 struct mlx4_adapter adapter;
1090 struct mlx4_dev_cap dev_cap;
2d928651 1091 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1092 struct mlx4_profile profile;
1093 struct mlx4_init_hca_param init_hca;
1094 u64 icm_size;
1095 int err;
1096
ab9c17a0
JM		 1097 if (!mlx4_is_slave(dev)) {
1098 err = mlx4_QUERY_FW(dev);
1099 if (err) {
1100 if (err == -EACCES)
1101 mlx4_info(dev, "non-primary physical function, skipping.\n");
1102 else
1103 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1104 goto unmap_bf;
1105 }
225c7b1f 1106
ab9c17a0
JM		 1107 err = mlx4_load_fw(dev);
1108 if (err) {
1109 mlx4_err(dev, "Failed to start FW, aborting.\n");
1110 goto unmap_bf;
1111 }
225c7b1f 1112
ab9c17a0
JM		 1113 mlx4_cfg.log_pg_sz_m = 1;
1114 mlx4_cfg.log_pg_sz = 0;
1115 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1116 if (err)
1117 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1118
ab9c17a0
JM		 1119 err = mlx4_dev_cap(dev, &dev_cap);
1120 if (err) {
1121 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1122 goto err_stop_fw;
1123 }
225c7b1f 1124
ab9c17a0 1125 profile = default_profile;
225c7b1f 1126
ab9c17a0
JM		 1127 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1128 &init_hca);
1129 if ((long long) icm_size < 0) {
1130 err = icm_size;
1131 goto err_stop_fw;
1132 }
225c7b1f 1133
ab9c17a0
JM		 1134 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1135 init_hca.uar_page_sz = PAGE_SHIFT - 12;
c1b43dca 1136
ab9c17a0
JM		 1137 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1138 if (err)
1139 goto err_stop_fw;
225c7b1f 1140
ab9c17a0
JM		 1141 err = mlx4_INIT_HCA(dev, &init_hca);
1142 if (err) {
1143 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1144 goto err_free_icm;
1145 }
1146 } else {
1147 err = mlx4_init_slave(dev);
1148 if (err) {
1149 mlx4_err(dev, "Failed to initialize slave\n");
1150 goto unmap_bf;
1151 }
225c7b1f 1152
ab9c17a0
JM		 1153 err = mlx4_slave_cap(dev);
1154 if (err) {
1155 mlx4_err(dev, "Failed to obtain slave caps\n");
1156 goto err_close;
1157 }
225c7b1f
RD		 1158 }
1159
ab9c17a0
JM		 1160 if (map_bf_area(dev))
1161 mlx4_dbg(dev, "Failed to map blue flame area\n");
1162
1163 /*Only the master set the ports, all the rest got it from it.*/
1164 if (!mlx4_is_slave(dev))
1165 mlx4_set_port_mask(dev);
1166
225c7b1f
RD		 1167 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1168 if (err) {
1169 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1170 goto err_close;
1171 }
1172
1173 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1174 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1175
1176 return 0;
1177
1178err_close:
ab9c17a0 1179 mlx4_close_hca(dev);
225c7b1f
RD		 1180
1181err_free_icm:
ab9c17a0
JM		 1182 if (!mlx4_is_slave(dev))
1183 mlx4_free_icms(dev);
225c7b1f
RD		 1184
1185err_stop_fw:
ab9c17a0
JM		 1186 if (!mlx4_is_slave(dev)) {
1187 mlx4_UNMAP_FA(dev);
1188 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1189 }
1190unmap_bf:
c1b43dca 1191 unmap_bf_area(dev);
225c7b1f
RD		 1192 return err;
1193}
1194
f2a3f6a3
OG		 1195static int mlx4_init_counters_table(struct mlx4_dev *dev)
1196{
1197 struct mlx4_priv *priv = mlx4_priv(dev);
1198 int nent;
1199
1200 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1201 return -ENOENT;
1202
1203 nent = dev->caps.max_counters;
1204 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1205}
1206
1207static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1208{
1209 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1210}
1211
1212int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1213{
1214 struct mlx4_priv *priv = mlx4_priv(dev);
1215
1216 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1217 return -ENOENT;
1218
1219 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1220 if (*idx == -1)
1221 return -ENOMEM;
1222
1223 return 0;
1224}
1225EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1226
1227void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1228{
1229 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1230 return;
1231}
1232EXPORT_SYMBOL_GPL(mlx4_counter_free);
1233
3d73c288 1234static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1235{
1236 struct mlx4_priv *priv = mlx4_priv(dev);
1237 int err;
7ff93f8b 1238 int port;
9a5aa622 1239 __be32 ib_port_default_caps;
225c7b1f 1240
225c7b1f
RD		 1241 err = mlx4_init_uar_table(dev);
1242 if (err) {
1243 mlx4_err(dev, "Failed to initialize "
1244 "user access region table, aborting.\n");
1245 return err;
1246 }
1247
1248 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1249 if (err) {
1250 mlx4_err(dev, "Failed to allocate driver access region, "
1251 "aborting.\n");
1252 goto err_uar_table_free;
1253 }
1254
4979d18f 1255 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f
RD		 1256 if (!priv->kar) {
1257 mlx4_err(dev, "Couldn't map kernel access region, "
1258 "aborting.\n");
1259 err = -ENOMEM;
1260 goto err_uar_free;
1261 }
1262
1263 err = mlx4_init_pd_table(dev);
1264 if (err) {
1265 mlx4_err(dev, "Failed to initialize "
1266 "protection domain table, aborting.\n");
1267 goto err_kar_unmap;
1268 }
1269
012a8ff5
SH		 1270 err = mlx4_init_xrcd_table(dev);
1271 if (err) {
1272 mlx4_err(dev, "Failed to initialize "
1273 "reliable connection domain table, aborting.\n");
1274 goto err_pd_table_free;
1275 }
1276
225c7b1f
RD		 1277 err = mlx4_init_mr_table(dev);
1278 if (err) {
1279 mlx4_err(dev, "Failed to initialize "
1280 "memory region table, aborting.\n");
012a8ff5 1281 goto err_xrcd_table_free;
225c7b1f
RD		 1282 }
1283
225c7b1f
RD		 1284 err = mlx4_init_eq_table(dev);
1285 if (err) {
1286 mlx4_err(dev, "Failed to initialize "
1287 "event queue table, aborting.\n");
ee49bd93 1288 goto err_mr_table_free;
225c7b1f
RD		 1289 }
1290
1291 err = mlx4_cmd_use_events(dev);
1292 if (err) {
1293 mlx4_err(dev, "Failed to switch to event-driven "
1294 "firmware commands, aborting.\n");
1295 goto err_eq_table_free;
1296 }
1297
1298 err = mlx4_NOP(dev);
1299 if (err) {
08fb1055
MT		 1300 if (dev->flags & MLX4_FLAG_MSI_X) {
1301 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1302 "interrupt IRQ %d).\n",
b8dd786f 1303 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 1304 mlx4_warn(dev, "Trying again without MSI-X.\n");
1305 } else {
1306 mlx4_err(dev, "NOP command failed to generate interrupt "
1307 "(IRQ %d), aborting.\n",
b8dd786f 1308 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1309 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1310 }
225c7b1f
RD		 1311
1312 goto err_cmd_poll;
1313 }
1314
1315 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1316
1317 err = mlx4_init_cq_table(dev);
1318 if (err) {
1319 mlx4_err(dev, "Failed to initialize "
1320 "completion queue table, aborting.\n");
1321 goto err_cmd_poll;
1322 }
1323
1324 err = mlx4_init_srq_table(dev);
1325 if (err) {
1326 mlx4_err(dev, "Failed to initialize "
1327 "shared receive queue table, aborting.\n");
1328 goto err_cq_table_free;
1329 }
1330
1331 err = mlx4_init_qp_table(dev);
1332 if (err) {
1333 mlx4_err(dev, "Failed to initialize "
1334 "queue pair table, aborting.\n");
1335 goto err_srq_table_free;
1336 }
1337
ab9c17a0
JM		 1338 if (!mlx4_is_slave(dev)) {
1339 err = mlx4_init_mcg_table(dev);
1340 if (err) {
1341 mlx4_err(dev, "Failed to initialize "
1342 "multicast group table, aborting.\n");
1343 goto err_qp_table_free;
1344 }
225c7b1f
RD		 1345 }
1346
f2a3f6a3
OG		 1347 err = mlx4_init_counters_table(dev);
1348 if (err && err != -ENOENT) {
1349 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
ab9c17a0 1350 goto err_mcg_table_free;
f2a3f6a3
OG		 1351 }
1352
ab9c17a0
JM		 1353 if (!mlx4_is_slave(dev)) {
1354 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1355 ib_port_default_caps = 0;
1356 err = mlx4_get_port_ib_caps(dev, port,
1357 &ib_port_default_caps);
1358 if (err)
1359 mlx4_warn(dev, "failed to get port %d default "
1360 "ib capabilities (%d). Continuing "
1361 "with caps = 0\n", port, err);
1362 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1363
1364 err = mlx4_check_ext_port_caps(dev, port);
1365 if (err)
1366 mlx4_warn(dev, "failed to get port %d extended "
1367 "port capabilities support info (%d)."
1368 " Assuming not supported\n",
1369 port, err);
97285b78 1370
ab9c17a0
JM		 1371 err = mlx4_SET_PORT(dev, port);
1372 if (err) {
1373 mlx4_err(dev, "Failed to set port %d, aborting\n",
1374 port);
1375 goto err_counters_table_free;
1376 }
7ff93f8b
YP		 1377 }
1378 }
1379
225c7b1f
RD		 1380 return 0;
1381
f2a3f6a3
OG		 1382err_counters_table_free:
1383 mlx4_cleanup_counters_table(dev);
1384
ab9c17a0
JM		 1385err_mcg_table_free:
1386 mlx4_cleanup_mcg_table(dev);
1387
225c7b1f
RD		 1388err_qp_table_free:
1389 mlx4_cleanup_qp_table(dev);
1390
1391err_srq_table_free:
1392 mlx4_cleanup_srq_table(dev);
1393
1394err_cq_table_free:
1395 mlx4_cleanup_cq_table(dev);
1396
1397err_cmd_poll:
1398 mlx4_cmd_use_polling(dev);
1399
1400err_eq_table_free:
1401 mlx4_cleanup_eq_table(dev);
1402
ee49bd93 1403err_mr_table_free:
225c7b1f
RD		 1404 mlx4_cleanup_mr_table(dev);
1405
012a8ff5
SH		 1406err_xrcd_table_free:
1407 mlx4_cleanup_xrcd_table(dev);
1408
225c7b1f
RD		 1409err_pd_table_free:
1410 mlx4_cleanup_pd_table(dev);
1411
1412err_kar_unmap:
1413 iounmap(priv->kar);
1414
1415err_uar_free:
1416 mlx4_uar_free(dev, &priv->driver_uar);
1417
1418err_uar_table_free:
1419 mlx4_cleanup_uar_table(dev);
1420 return err;
1421}
1422
e8f9b2ed 1423static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 1424{
1425 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 1426 struct msix_entry *entries;
0b7ca5a9
YP		 1427 int nreq = min_t(int, dev->caps.num_ports *
1428 min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT)
1429 + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 1430 int err;
1431 int i;
1432
1433 if (msi_x) {
ab9c17a0
JM		 1434 /* In multifunction mode each function gets 2 msi-X vectors
1435 * one for data path completions anf the other for asynch events
1436 * or command completions */
1437 if (mlx4_is_mfunc(dev)) {
1438 nreq = 2;
1439 } else {
1440 nreq = min_t(int, dev->caps.num_eqs -
1441 dev->caps.reserved_eqs, nreq);
1442 }
1443
b8dd786f
YP		 1444 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1445 if (!entries)
1446 goto no_msi;
1447
1448 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1449 entries[i].entry = i;
1450
b8dd786f
YP		 1451 retry:
1452 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 1453 if (err) {
b8dd786f
YP		 1454 /* Try again if at least 2 vectors are available */
1455 if (err > 1) {
1456 mlx4_info(dev, "Requested %d vectors, "
1457 "but only %d MSI-X vectors available, "
1458 "trying again\n", nreq, err);
1459 nreq = err;
1460 goto retry;
1461 }
5bf0da7d 1462 kfree(entries);
225c7b1f
RD		 1463 goto no_msi;
1464 }
1465
0b7ca5a9
YP		 1466 if (nreq <
1467 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1468 /*Working in legacy mode , all EQ's shared*/
1469 dev->caps.comp_pool = 0;
1470 dev->caps.num_comp_vectors = nreq - 1;
1471 } else {
1472 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1473 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1474 }
b8dd786f 1475 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1476 priv->eq_table.eq[i].irq = entries[i].vector;
1477
1478 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 1479
1480 kfree(entries);
225c7b1f
RD		 1481 return;
1482 }
1483
1484no_msi:
b8dd786f 1485 dev->caps.num_comp_vectors = 1;
0b7ca5a9 1486 dev->caps.comp_pool = 0;
b8dd786f
YP		 1487
1488 for (i = 0; i < 2; ++i)
225c7b1f
RD		 1489 priv->eq_table.eq[i].irq = dev->pdev->irq;
1490}
1491
7ff93f8b 1492static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 1493{
1494 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 1495 int err = 0;
2a2336f8
YP		 1496
1497 info->dev = dev;
1498 info->port = port;
ab9c17a0
JM		 1499 if (!mlx4_is_slave(dev)) {
1500 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL);
1501 mlx4_init_mac_table(dev, &info->mac_table);
1502 mlx4_init_vlan_table(dev, &info->vlan_table);
1503 info->base_qpn =
1504 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
06fa0a88 1505 (port - 1) * (1 << log_num_mac);
ab9c17a0 1506 }
7ff93f8b
YP		 1507
1508 sprintf(info->dev_name, "mlx4_port%d", port);
1509 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 1510 if (mlx4_is_mfunc(dev))
1511 info->port_attr.attr.mode = S_IRUGO;
1512 else {
1513 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1514 info->port_attr.store = set_port_type;
1515 }
7ff93f8b 1516 info->port_attr.show = show_port_type;
3691c964 1517 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 1518
1519 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1520 if (err) {
1521 mlx4_err(dev, "Failed to create file for port %d\n", port);
1522 info->port = -1;
1523 }
1524
1525 return err;
1526}
1527
1528static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1529{
1530 if (info->port < 0)
1531 return;
1532
1533 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2a2336f8
YP		 1534}
1535
b12d93d6
YP		 1536static int mlx4_init_steering(struct mlx4_dev *dev)
1537{
1538 struct mlx4_priv *priv = mlx4_priv(dev);
1539 int num_entries = dev->caps.num_ports;
1540 int i, j;
1541
1542 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1543 if (!priv->steer)
1544 return -ENOMEM;
1545
1546 for (i = 0; i < num_entries; i++) {
1547 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1548 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1549 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1550 }
1551 INIT_LIST_HEAD(&priv->steer[i].high_prios);
1552 }
1553 return 0;
1554}
1555
1556static void mlx4_clear_steering(struct mlx4_dev *dev)
1557{
1558 struct mlx4_priv *priv = mlx4_priv(dev);
1559 struct mlx4_steer_index *entry, *tmp_entry;
1560 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1561 int num_entries = dev->caps.num_ports;
1562 int i, j;
1563
1564 for (i = 0; i < num_entries; i++) {
1565 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1566 list_for_each_entry_safe(pqp, tmp_pqp,
1567 &priv->steer[i].promisc_qps[j],
1568 list) {
1569 list_del(&pqp->list);
1570 kfree(pqp);
1571 }
1572 list_for_each_entry_safe(entry, tmp_entry,
1573 &priv->steer[i].steer_entries[j],
1574 list) {
1575 list_del(&entry->list);
1576 list_for_each_entry_safe(pqp, tmp_pqp,
1577 &entry->duplicates,
1578 list) {
1579 list_del(&pqp->list);
1580 kfree(pqp);
1581 }
1582 kfree(entry);
1583 }
1584 }
1585 }
1586 kfree(priv->steer);
1587}
1588
ab9c17a0
JM		 1589static int extended_func_num(struct pci_dev *pdev)
1590{
1591 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
1592}
1593
1594#define MLX4_OWNER_BASE 0x8069c
1595#define MLX4_OWNER_SIZE 4
1596
1597static int mlx4_get_ownership(struct mlx4_dev *dev)
1598{
1599 void __iomem *owner;
1600 u32 ret;
1601
1602 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1603 MLX4_OWNER_SIZE);
1604 if (!owner) {
1605 mlx4_err(dev, "Failed to obtain ownership bit\n");
1606 return -ENOMEM;
1607 }
1608
1609 ret = readl(owner);
1610 iounmap(owner);
1611 return (int) !!ret;
1612}
1613
1614static void mlx4_free_ownership(struct mlx4_dev *dev)
1615{
1616 void __iomem *owner;
1617
1618 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1619 MLX4_OWNER_SIZE);
1620 if (!owner) {
1621 mlx4_err(dev, "Failed to obtain ownership bit\n");
1622 return;
1623 }
1624 writel(0, owner);
1625 msleep(1000);
1626 iounmap(owner);
1627}
1628
3d73c288 1629static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
225c7b1f 1630{
225c7b1f
RD		 1631 struct mlx4_priv *priv;
1632 struct mlx4_dev *dev;
1633 int err;
2a2336f8 1634 int port;
225c7b1f 1635
0a645e80 1636 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 1637
1638 err = pci_enable_device(pdev);
1639 if (err) {
1640 dev_err(&pdev->dev, "Cannot enable PCI device, "
1641 "aborting.\n");
1642 return err;
1643 }
ab9c17a0
JM		 1644 if (num_vfs > MLX4_MAX_NUM_VF) {
1645 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
1646 num_vfs, MLX4_MAX_NUM_VF);
1647 return -EINVAL;
1648 }
225c7b1f 1649 /*
ab9c17a0 1650 * Check for BARs.
225c7b1f 1651 */
ab9c17a0
JM		 1652 if (((id == NULL) || !(id->driver_data & MLX4_VF)) &&
1653 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1654 dev_err(&pdev->dev, "Missing DCS, aborting."
1655 "(id == 0X%p, id->driver_data: 0x%lx,"
1656 " pci_resource_flags(pdev, 0):0x%lx)\n", id,
1657 id ? id->driver_data : 0, pci_resource_flags(pdev, 0));
225c7b1f
RD		 1658 err = -ENODEV;
1659 goto err_disable_pdev;
1660 }
1661 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1662 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1663 err = -ENODEV;
1664 goto err_disable_pdev;
1665 }
1666
a01df0fe 1667 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 1668 if (err) {
a01df0fe 1669 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 1670 goto err_disable_pdev;
1671 }
1672
225c7b1f
RD		 1673 pci_set_master(pdev);
1674
6a35528a 1675 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1676 if (err) {
1677 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 1678 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1679 if (err) {
1680 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 1681 goto err_release_regions;
225c7b1f
RD		 1682 }
1683 }
6a35528a 1684 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1685 if (err) {
1686 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1687 "consistent PCI DMA mask.\n");
284901a9 1688 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1689 if (err) {
1690 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1691 "aborting.\n");
a01df0fe 1692 goto err_release_regions;
225c7b1f
RD		 1693 }
1694 }
1695
7f9e5c48
DD		 1696 /* Allow large DMA segments, up to the firmware limit of 1 GB */
1697 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1698
225c7b1f
RD		 1699 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1700 if (!priv) {
1701 dev_err(&pdev->dev, "Device struct alloc failed, "
1702 "aborting.\n");
1703 err = -ENOMEM;
a01df0fe 1704 goto err_release_regions;
225c7b1f
RD		 1705 }
1706
1707 dev = &priv->dev;
1708 dev->pdev = pdev;
b581401e
RD		 1709 INIT_LIST_HEAD(&priv->ctx_list);
1710 spin_lock_init(&priv->ctx_lock);
225c7b1f 1711
7ff93f8b
YP		 1712 mutex_init(&priv->port_mutex);
1713
6296883c
YP		 1714 INIT_LIST_HEAD(&priv->pgdir_list);
1715 mutex_init(&priv->pgdir_mutex);
1716
c1b43dca
EC		 1717 INIT_LIST_HEAD(&priv->bf_list);
1718 mutex_init(&priv->bf_mutex);
1719
aca7a3ac 1720 dev->rev_id = pdev->revision;
ab9c17a0
JM		 1721 /* Detect if this device is a virtual function */
1722 if (id && id->driver_data & MLX4_VF) {
1723 /* When acting as pf, we normally skip vfs unless explicitly
1724 * requested to probe them. */
1725 if (num_vfs && extended_func_num(pdev) > probe_vf) {
1726 mlx4_warn(dev, "Skipping virtual function:%d\n",
1727 extended_func_num(pdev));
1728 err = -ENODEV;
1729 goto err_free_dev;
1730 }
1731 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
1732 dev->flags |= MLX4_FLAG_SLAVE;
1733 } else {
1734 /* We reset the device and enable SRIOV only for physical
1735 * devices. Try to claim ownership on the device;
1736 * if already taken, skip -- do not allow multiple PFs */
1737 err = mlx4_get_ownership(dev);
1738 if (err) {
1739 if (err < 0)
1740 goto err_free_dev;
1741 else {
1742 mlx4_warn(dev, "Multiple PFs not yet supported."
1743 " Skipping PF.\n");
1744 err = -EINVAL;
1745 goto err_free_dev;
1746 }
1747 }
aca7a3ac 1748
ab9c17a0
JM		 1749 if (num_vfs) {
1750 mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs);
1751 err = pci_enable_sriov(pdev, num_vfs);
1752 if (err) {
1753 mlx4_err(dev, "Failed to enable sriov,"
1754 "continuing without sriov enabled"
1755 " (err = %d).\n", err);
1756 num_vfs = 0;
1757 err = 0;
1758 } else {
1759 mlx4_warn(dev, "Running in master mode\n");
1760 dev->flags |= MLX4_FLAG_SRIOV |
1761 MLX4_FLAG_MASTER;
1762 dev->num_vfs = num_vfs;
1763 }
1764 }
1765
1766 /*
1767 * Now reset the HCA before we touch the PCI capabilities or
1768 * attempt a firmware command, since a boot ROM may have left
1769 * the HCA in an undefined state.
1770 */
1771 err = mlx4_reset(dev);
1772 if (err) {
1773 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1774 goto err_rel_own;
1775 }
225c7b1f
RD		 1776 }
1777
ab9c17a0 1778slave_start:
225c7b1f
RD		 1779 if (mlx4_cmd_init(dev)) {
1780 mlx4_err(dev, "Failed to init command interface, aborting.\n");
ab9c17a0
JM		 1781 goto err_sriov;
1782 }
1783
1784 /* In slave functions, the communication channel must be initialized
1785 * before posting commands. Also, init num_slaves before calling
1786 * mlx4_init_hca */
1787 if (mlx4_is_mfunc(dev)) {
1788 if (mlx4_is_master(dev))
1789 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
1790 else {
1791 dev->num_slaves = 0;
1792 if (mlx4_multi_func_init(dev)) {
1793 mlx4_err(dev, "Failed to init slave mfunc"
1794 " interface, aborting.\n");
1795 goto err_cmd;
1796 }
1797 }
225c7b1f
RD		 1798 }
1799
1800 err = mlx4_init_hca(dev);
ab9c17a0
JM		 1801 if (err) {
1802 if (err == -EACCES) {
1803 /* Not primary Physical function
1804 * Running in slave mode */
1805 mlx4_cmd_cleanup(dev);
1806 dev->flags |= MLX4_FLAG_SLAVE;
1807 dev->flags &= ~MLX4_FLAG_MASTER;
1808 goto slave_start;
1809 } else
1810 goto err_mfunc;
1811 }
1812
1813 /* In master functions, the communication channel must be initialized
1814 * after obtaining its address from fw */
1815 if (mlx4_is_master(dev)) {
1816 if (mlx4_multi_func_init(dev)) {
1817 mlx4_err(dev, "Failed to init master mfunc"
1818 "interface, aborting.\n");
1819 goto err_close;
1820 }
1821 }
225c7b1f 1822
b8dd786f
YP		 1823 err = mlx4_alloc_eq_table(dev);
1824 if (err)
ab9c17a0 1825 goto err_master_mfunc;
b8dd786f 1826
0b7ca5a9
YP		 1827 priv->msix_ctl.pool_bm = 0;
1828 spin_lock_init(&priv->msix_ctl.pool_lock);
1829
08fb1055 1830 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 1831 if ((mlx4_is_mfunc(dev)) &&
1832 !(dev->flags & MLX4_FLAG_MSI_X)) {
1833 mlx4_err(dev, "INTx is not supported in multi-function mode."
1834 " aborting.\n");
b12d93d6 1835 goto err_free_eq;
ab9c17a0
JM		 1836 }
1837
1838 if (!mlx4_is_slave(dev)) {
1839 err = mlx4_init_steering(dev);
1840 if (err)
1841 goto err_free_eq;
1842 }
b12d93d6 1843
225c7b1f 1844 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 1845 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
1846 !mlx4_is_mfunc(dev)) {
08fb1055
MT		 1847 dev->flags &= ~MLX4_FLAG_MSI_X;
1848 pci_disable_msix(pdev);
1849 err = mlx4_setup_hca(dev);
1850 }
1851
225c7b1f 1852 if (err)
b12d93d6 1853 goto err_steer;
225c7b1f 1854
7ff93f8b
YP		 1855 for (port = 1; port <= dev->caps.num_ports; port++) {
1856 err = mlx4_init_port_info(dev, port);
1857 if (err)
1858 goto err_port;
1859 }
2a2336f8 1860
225c7b1f
RD		 1861 err = mlx4_register_device(dev);
1862 if (err)
7ff93f8b 1863 goto err_port;
225c7b1f 1864
27bf91d6
YP		 1865 mlx4_sense_init(dev);
1866 mlx4_start_sense(dev);
1867
225c7b1f
RD		 1868 pci_set_drvdata(pdev, dev);
1869
1870 return 0;
1871
7ff93f8b 1872err_port:
b4f77264 1873 for (--port; port >= 1; --port)
7ff93f8b
YP		 1874 mlx4_cleanup_port_info(&priv->port[port]);
1875
f2a3f6a3 1876 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 1877 mlx4_cleanup_mcg_table(dev);
1878 mlx4_cleanup_qp_table(dev);
1879 mlx4_cleanup_srq_table(dev);
1880 mlx4_cleanup_cq_table(dev);
1881 mlx4_cmd_use_polling(dev);
1882 mlx4_cleanup_eq_table(dev);
225c7b1f 1883 mlx4_cleanup_mr_table(dev);
012a8ff5 1884 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 1885 mlx4_cleanup_pd_table(dev);
1886 mlx4_cleanup_uar_table(dev);
1887
b12d93d6 1888err_steer:
ab9c17a0
JM		 1889 if (!mlx4_is_slave(dev))
1890 mlx4_clear_steering(dev);
b12d93d6 1891
b8dd786f
YP		 1892err_free_eq:
1893 mlx4_free_eq_table(dev);
1894
ab9c17a0
JM		 1895err_master_mfunc:
1896 if (mlx4_is_master(dev))
1897 mlx4_multi_func_cleanup(dev);
1898
225c7b1f 1899err_close:
08fb1055
MT		 1900 if (dev->flags & MLX4_FLAG_MSI_X)
1901 pci_disable_msix(pdev);
1902
225c7b1f
RD		 1903 mlx4_close_hca(dev);
1904
ab9c17a0
JM		 1905err_mfunc:
1906 if (mlx4_is_slave(dev))
1907 mlx4_multi_func_cleanup(dev);
1908
225c7b1f
RD		 1909err_cmd:
1910 mlx4_cmd_cleanup(dev);
1911
ab9c17a0
JM		 1912err_sriov:
1913 if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV))
1914 pci_disable_sriov(pdev);
1915
1916err_rel_own:
1917 if (!mlx4_is_slave(dev))
1918 mlx4_free_ownership(dev);
1919
225c7b1f 1920err_free_dev:
225c7b1f
RD		 1921 kfree(priv);
1922
a01df0fe
RD		 1923err_release_regions:
1924 pci_release_regions(pdev);
225c7b1f
RD		 1925
1926err_disable_pdev:
1927 pci_disable_device(pdev);
1928 pci_set_drvdata(pdev, NULL);
1929 return err;
1930}
1931
3d73c288
RD		 1932static int __devinit mlx4_init_one(struct pci_dev *pdev,
1933 const struct pci_device_id *id)
1934{
0a645e80 1935 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 1936
b027cacd 1937 return __mlx4_init_one(pdev, id);
3d73c288
RD		 1938}
1939
1940static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 1941{
1942 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1943 struct mlx4_priv *priv = mlx4_priv(dev);
1944 int p;
1945
1946 if (dev) {
ab9c17a0
JM		 1947 /* in SRIOV it is not allowed to unload the pf's
1948 * driver while there are alive vf's */
1949 if (mlx4_is_master(dev)) {
1950 if (mlx4_how_many_lives_vf(dev))
1951 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
1952 }
27bf91d6 1953 mlx4_stop_sense(dev);
225c7b1f
RD		 1954 mlx4_unregister_device(dev);
1955
7ff93f8b
YP		 1956 for (p = 1; p <= dev->caps.num_ports; p++) {
1957 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 1958 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 1959 }
225c7b1f 1960
f2a3f6a3 1961 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 1962 mlx4_cleanup_mcg_table(dev);
1963 mlx4_cleanup_qp_table(dev);
1964 mlx4_cleanup_srq_table(dev);
1965 mlx4_cleanup_cq_table(dev);
1966 mlx4_cmd_use_polling(dev);
1967 mlx4_cleanup_eq_table(dev);
225c7b1f 1968 mlx4_cleanup_mr_table(dev);
012a8ff5 1969 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 1970 mlx4_cleanup_pd_table(dev);
1971
ab9c17a0
JM		 1972 if (mlx4_is_master(dev))
1973 mlx4_free_resource_tracker(dev);
1974
225c7b1f
RD		 1975 iounmap(priv->kar);
1976 mlx4_uar_free(dev, &priv->driver_uar);
1977 mlx4_cleanup_uar_table(dev);
ab9c17a0
JM		 1978 if (!mlx4_is_slave(dev))
1979 mlx4_clear_steering(dev);
b8dd786f 1980 mlx4_free_eq_table(dev);
ab9c17a0
JM		 1981 if (mlx4_is_master(dev))
1982 mlx4_multi_func_cleanup(dev);
225c7b1f 1983 mlx4_close_hca(dev);
ab9c17a0
JM		 1984 if (mlx4_is_slave(dev))
1985 mlx4_multi_func_cleanup(dev);
225c7b1f
RD		 1986 mlx4_cmd_cleanup(dev);
1987
1988 if (dev->flags & MLX4_FLAG_MSI_X)
1989 pci_disable_msix(pdev);
ab9c17a0
JM		 1990 if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV)) {
1991 mlx4_warn(dev, "Disabling sriov\n");
1992 pci_disable_sriov(pdev);
1993 }
225c7b1f 1994
ab9c17a0
JM		 1995 if (!mlx4_is_slave(dev))
1996 mlx4_free_ownership(dev);
225c7b1f 1997 kfree(priv);
a01df0fe 1998 pci_release_regions(pdev);
225c7b1f
RD		 1999 pci_disable_device(pdev);
2000 pci_set_drvdata(pdev, NULL);
2001 }
2002}
2003
ee49bd93
JM		 2004int mlx4_restart_one(struct pci_dev *pdev)
2005{
2006 mlx4_remove_one(pdev);
3d73c288 2007 return __mlx4_init_one(pdev, NULL);
ee49bd93
JM		 2008}
2009
a3aa1884 2010static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0
JM		 2011 /* MT25408 "Hermon" SDR */
2012 { PCI_VDEVICE(MELLANOX, 0x6340), 0 },
2013 /* MT25408 "Hermon" DDR */
2014 { PCI_VDEVICE(MELLANOX, 0x634a), 0 },
2015 /* MT25408 "Hermon" QDR */
2016 { PCI_VDEVICE(MELLANOX, 0x6354), 0 },
2017 /* MT25408 "Hermon" DDR PCIe gen2 */
2018 { PCI_VDEVICE(MELLANOX, 0x6732), 0 },
2019 /* MT25408 "Hermon" QDR PCIe gen2 */
2020 { PCI_VDEVICE(MELLANOX, 0x673c), 0 },
2021 /* MT25408 "Hermon" EN 10GigE */
2022 { PCI_VDEVICE(MELLANOX, 0x6368), 0 },
2023 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2024 { PCI_VDEVICE(MELLANOX, 0x6750), 0 },
2025 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2026 { PCI_VDEVICE(MELLANOX, 0x6372), 0 },
2027 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2028 { PCI_VDEVICE(MELLANOX, 0x675a), 0 },
2029 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2030 { PCI_VDEVICE(MELLANOX, 0x6764), 0 },
2031 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2032 { PCI_VDEVICE(MELLANOX, 0x6746), 0 },
2033 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2034 { PCI_VDEVICE(MELLANOX, 0x676e), 0 },
2035 /* MT25400 Family [ConnectX-2 Virtual Function] */
2036 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_VF },
2037 /* MT27500 Family [ConnectX-3] */
2038 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2039 /* MT27500 Family [ConnectX-3 Virtual Function] */
2040 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_VF },
2041 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2042 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2043 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2044 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2045 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2046 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2047 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2048 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2049 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2050 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2051 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2052 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2053 { 0, }
2054};
2055
2056MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2057
2058static struct pci_driver mlx4_driver = {
2059 .name = DRV_NAME,
2060 .id_table = mlx4_pci_table,
2061 .probe = mlx4_init_one,
2062 .remove = __devexit_p(mlx4_remove_one)
2063};
2064
7ff93f8b
YP		 2065static int __init mlx4_verify_params(void)
2066{
2067 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2068 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2069 return -1;
2070 }
2071
cb29688a
OG		 2072 if (log_num_vlan != 0)
2073 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2074 MLX4_LOG_NUM_VLANS);
7ff93f8b 2075
0498628f 2076 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2077 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2078 return -1;
2079 }
2080
ab9c17a0
JM		 2081 /* Check if module param for ports type has legal combination */
2082 if (port_type_array[0] == false && port_type_array[1] == true) {
2083 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2084 port_type_array[0] = true;
2085 }
2086
7ff93f8b
YP		 2087 return 0;
2088}
2089
225c7b1f
RD		 2090static int __init mlx4_init(void)
2091{
2092 int ret;
2093
7ff93f8b
YP		 2094 if (mlx4_verify_params())
2095 return -EINVAL;
2096
27bf91d6
YP		 2097 mlx4_catas_init();
2098
2099 mlx4_wq = create_singlethread_workqueue("mlx4");
2100 if (!mlx4_wq)
2101 return -ENOMEM;
ee49bd93 2102
225c7b1f
RD		 2103 ret = pci_register_driver(&mlx4_driver);
2104 return ret < 0 ? ret : 0;
2105}
2106
2107static void __exit mlx4_cleanup(void)
2108{
2109 pci_unregister_driver(&mlx4_driver);
27bf91d6 2110 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2111}
2112
2113module_init(mlx4_init);
2114module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)