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net/mlx4: Refactor QUERY_PORT
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
dd41cc3b 80static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 81static int num_vfs_argc;
dd41cc3b
MB		 82module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 87static int probe_vfs_argc;
dd41cc3b
MB		 88module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
ab9c17a0 91
3c439b55 92int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 93module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
3c439b55 97 " 10 gives 248.range: 7 <="
0ff1fb65 98 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 99 " To activate device managed"
100 " flow steering when available, set to -1");
0ec2c0f8 101
be902ab1 102static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 103module_param(enable_64b_cqe_eqe, bool, 0444);
104MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 106
77507aa2
IS		 107#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
108 MLX4_FUNC_CAP_EQE_CQE_STRIDE)
ab9c17a0 109
f57e6848 110static char mlx4_version[] =
225c7b1f
RD		 111 DRV_NAME ": Mellanox ConnectX core driver v"
112 DRV_VERSION " (" DRV_RELDATE ")\n";
113
114static struct mlx4_profile default_profile = {
ab9c17a0 115 .num_qp = 1 << 18,
225c7b1f 116 .num_srq = 1 << 16,
c9f2ba5e 117 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 118 .num_cq = 1 << 16,
119 .num_mcg = 1 << 13,
ab9c17a0 120 .num_mpt = 1 << 19,
9fd7a1e1 121 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 122};
123
2599d858
AV		 124static struct mlx4_profile low_mem_profile = {
125 .num_qp = 1 << 17,
126 .num_srq = 1 << 6,
127 .rdmarc_per_qp = 1 << 4,
128 .num_cq = 1 << 8,
129 .num_mcg = 1 << 8,
130 .num_mpt = 1 << 9,
131 .num_mtt = 1 << 7,
132};
133
ab9c17a0 134static int log_num_mac = 7;
93fc9e1b
YP		 135module_param_named(log_num_mac, log_num_mac, int, 0444);
136MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
137
138static int log_num_vlan;
139module_param_named(log_num_vlan, log_num_vlan, int, 0444);
140MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 141/* Log2 max number of VLANs per ETH port (0-7) */
142#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 143#define MLX4_MIN_LOG_NUM_VLANS 0
144#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 145
eb939922 146static bool use_prio;
93fc9e1b 147module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 148MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 149
2b8fb286 150int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 151module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 152MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 153
8d0fc7b6 154static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 155static int arr_argc = 2;
156module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 157MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
158 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 159
160struct mlx4_port_config {
161 struct list_head list;
162 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
163 struct pci_dev *pdev;
164};
165
97989356
AV		 166static atomic_t pf_loading = ATOMIC_INIT(0);
167
27bf91d6
YP		 168int mlx4_check_port_params(struct mlx4_dev *dev,
169 enum mlx4_port_type *port_type)
7ff93f8b
YP		 170{
171 int i;
172
173 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 174 if (port_type[i] != port_type[i + 1]) {
175 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
1a91de28 176 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 177 return -EINVAL;
178 }
7ff93f8b
YP		 179 }
180 }
7ff93f8b
YP		 181
182 for (i = 0; i < dev->caps.num_ports; i++) {
183 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 184 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
185 i + 1);
7ff93f8b
YP		 186 return -EINVAL;
187 }
188 }
189 return 0;
190}
191
192static void mlx4_set_port_mask(struct mlx4_dev *dev)
193{
194 int i;
195
7ff93f8b 196 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 197 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 198}
f2a3f6a3 199
7ae0e400
MB		 200enum {
201 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
202};
203
204static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
205{
206 int err = 0;
207 struct mlx4_func func;
208
209 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
210 err = mlx4_QUERY_FUNC(dev, &func, 0);
211 if (err) {
212 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
213 return err;
214 }
215 dev_cap->max_eqs = func.max_eq;
216 dev_cap->reserved_eqs = func.rsvd_eqs;
217 dev_cap->reserved_uars = func.rsvd_uars;
218 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
219 }
220 return err;
221}
222
77507aa2
IS		 223static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
224{
225 struct mlx4_caps *dev_cap = &dev->caps;
226
227 /* FW not supporting or cancelled by user */
228 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
229 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
230 return;
231
232 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
233 * When FW has NCSI it may decide not to report 64B CQE/EQEs
234 */
235 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
236 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
237 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
238 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
239 return;
240 }
241
242 if (cache_line_size() == 128 || cache_line_size() == 256) {
243 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
244 /* Changing the real data inside CQE size to 32B */
245 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
246 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
247
248 if (mlx4_is_master(dev))
249 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
250 } else {
251 mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n");
252 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
253 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
254 }
255}
256
431df8c7
MB		 257static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
258 struct mlx4_port_cap *port_cap)
259{
260 dev->caps.vl_cap[port] = port_cap->max_vl;
261 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
262 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
263 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
264 /* set gid and pkey table operating lengths by default
265 * to non-sriov values
266 */
267 dev->caps.gid_table_len[port] = port_cap->max_gids;
268 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
269 dev->caps.port_width_cap[port] = port_cap->max_port_width;
270 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
271 dev->caps.def_mac[port] = port_cap->def_mac;
272 dev->caps.supported_type[port] = port_cap->supported_port_types;
273 dev->caps.suggested_type[port] = port_cap->suggested_type;
274 dev->caps.default_sense[port] = port_cap->default_sense;
275 dev->caps.trans_type[port] = port_cap->trans_type;
276 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
277 dev->caps.wavelength[port] = port_cap->wavelength;
278 dev->caps.trans_code[port] = port_cap->trans_code;
279
280 return 0;
281}
282
283static int mlx4_dev_port(struct mlx4_dev *dev, int port,
284 struct mlx4_port_cap *port_cap)
285{
286 int err = 0;
287
288 err = mlx4_QUERY_PORT(dev, port, port_cap);
289
290 if (err)
291 mlx4_err(dev, "QUERY_PORT command failed.\n");
292
293 return err;
294}
295
296#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 297static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 298{
299 int err;
5ae2a7a8 300 int i;
225c7b1f
RD		 301
302 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
303 if (err) {
1a91de28 304 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 305 return err;
306 }
307
308 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 309 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 310 dev_cap->min_page_sz, PAGE_SIZE);
311 return -ENODEV;
312 }
313 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 314 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 315 dev_cap->num_ports, MLX4_MAX_PORTS);
316 return -ENODEV;
317 }
318
319 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
1a91de28 320 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f
RD		 321 dev_cap->uar_size,
322 (unsigned long long) pci_resource_len(dev->pdev, 2));
323 return -ENODEV;
324 }
325
326 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 327 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
328 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
329 dev->caps.num_sys_eqs :
330 MLX4_MAX_EQ_NUM;
5ae2a7a8 331 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 332 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
333 if (err) {
334 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
335 return err;
336 }
5ae2a7a8
RD		 337 }
338
ab9c17a0 339 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 340 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 341 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
342 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
343 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
344 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
345 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
346 dev->caps.max_wqes = dev_cap->max_qp_sz;
347 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 348 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
349 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
350 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
351 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
352 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 353 /*
354 * Subtract 1 from the limit because we need to allocate a
355 * spare CQE so the HCA HW can tell the difference between an
356 * empty CQ and a full CQ.
357 */
358 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
359 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
360 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 361 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 362 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 363
364 /* The first 128 UARs are used for EQ doorbells */
365 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 366 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 367 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
368 dev_cap->reserved_xrcds : 0;
369 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
370 dev_cap->max_xrcds : 0;
2b8fb286
MA		 371 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
372
149983af 373 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 374 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
375 dev->caps.flags = dev_cap->flags;
b3416f44 376 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 377 dev->caps.bmme_flags = dev_cap->bmme_flags;
378 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 379 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 380 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 381 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 382
ca3e57a5
RD		 383 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
384 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 385 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 386 /* Don't do sense port on multifunction devices (for now at least) */
387 if (mlx4_is_mfunc(dev))
388 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 389
2599d858
AV		 390 if (mlx4_low_memory_profile()) {
391 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
392 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
393 } else {
394 dev->caps.log_num_macs = log_num_mac;
395 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
396 }
93fc9e1b
YP		 397
398 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 399 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
400 if (dev->caps.supported_type[i]) {
401 /* if only ETH is supported - assign ETH */
402 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
403 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 404 /* if only IB is supported, assign IB */
ab9c17a0 405 else if (dev->caps.supported_type[i] ==
105c320f
JM		 406 MLX4_PORT_TYPE_IB)
407 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 408 else {
105c320f
JM		 409 /* if IB and ETH are supported, we set the port
410 * type according to user selection of port type;
411 * if user selected none, take the FW hint */
412 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 413 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
414 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 415 else
105c320f 416 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 417 }
418 }
8d0fc7b6
YP		 419 /*
420 * Link sensing is allowed on the port if 3 conditions are true:
421 * 1. Both protocols are supported on the port.
422 * 2. Different types are supported on the port
423 * 3. FW declared that it supports link sensing
424 */
27bf91d6 425 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 426 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 427 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 428 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 429
8d0fc7b6
YP		 430 /*
431 * If "default_sense" bit is set, we move the port to "AUTO" mode
432 * and perform sense_port FW command to try and set the correct
433 * port type from beginning
434 */
46c46747 435 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 436 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
437 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
438 mlx4_SENSE_PORT(dev, i, &sensed_port);
439 if (sensed_port != MLX4_PORT_TYPE_NONE)
440 dev->caps.port_type[i] = sensed_port;
441 } else {
442 dev->caps.possible_type[i] = dev->caps.port_type[i];
443 }
444
431df8c7
MB		 445 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
446 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 447 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 448 i, 1 << dev->caps.log_num_macs);
449 }
431df8c7
MB		 450 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
451 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 452 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 453 i, 1 << dev->caps.log_num_vlans);
454 }
455 }
456
f2a3f6a3
OG		 457 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
458
93fc9e1b
YP		 459 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
460 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
461 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
462 (1 << dev->caps.log_num_macs) *
463 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 464 dev->caps.num_ports;
465 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
d57febe1
MB		 466 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
467 MLX4_A0_STEERING_TABLE_SIZE;
93fc9e1b
YP		 468
469 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
470 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
471 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
472 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
473
e2c76824 474 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 475
b3051320 476 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 477 if (dev_cap->flags &
478 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
479 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
480 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
481 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
482 }
77507aa2
IS		 483
484 if (dev_cap->flags2 &
485 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
486 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
487 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
488 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
489 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
490 }
08ff3235
OG		 491 }
492
f97b4b5d 493 if ((dev->caps.flags &
08ff3235
OG		 494 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
495 mlx4_is_master(dev))
496 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
497
ddae0349 498 if (!mlx4_is_slave(dev)) {
77507aa2 499 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 500 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 501 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
502 MLX4_RESERVE_A0_QP;
ddae0349
EE		 503 } else {
504 dev->caps.alloc_res_qp_mask = 0;
505 }
77507aa2 506
225c7b1f
RD		 507 return 0;
508}
b912b2f8
EP		 509
510static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
511 enum pci_bus_speed *speed,
512 enum pcie_link_width *width)
513{
514 u32 lnkcap1, lnkcap2;
515 int err1, err2;
516
517#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
518
519 *speed = PCI_SPEED_UNKNOWN;
520 *width = PCIE_LNK_WIDTH_UNKNOWN;
521
522 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
523 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
524 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
525 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
526 *speed = PCIE_SPEED_8_0GT;
527 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
528 *speed = PCIE_SPEED_5_0GT;
529 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
530 *speed = PCIE_SPEED_2_5GT;
531 }
532 if (!err1) {
533 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
534 if (!lnkcap2) { /* pre-r3.0 */
535 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
536 *speed = PCIE_SPEED_5_0GT;
537 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
538 *speed = PCIE_SPEED_2_5GT;
539 }
540 }
541
542 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
543 return err1 ? err1 :
544 err2 ? err2 : -EINVAL;
545 }
546 return 0;
547}
548
549static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
550{
551 enum pcie_link_width width, width_cap;
552 enum pci_bus_speed speed, speed_cap;
553 int err;
554
555#define PCIE_SPEED_STR(speed) \
556 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
557 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
558 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
559 "Unknown")
560
561 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
562 if (err) {
563 mlx4_warn(dev,
564 "Unable to determine PCIe device BW capabilities\n");
565 return;
566 }
567
568 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
569 if (err || speed == PCI_SPEED_UNKNOWN ||
570 width == PCIE_LNK_WIDTH_UNKNOWN) {
571 mlx4_warn(dev,
572 "Unable to determine PCI device chain minimum BW\n");
573 return;
574 }
575
576 if (width != width_cap || speed != speed_cap)
577 mlx4_warn(dev,
578 "PCIe BW is different than device's capability\n");
579
580 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
581 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
582 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
583 width, width_cap);
584 return;
585}
586
ab9c17a0
JM		 587/*The function checks if there are live vf, return the num of them*/
588static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
589{
590 struct mlx4_priv *priv = mlx4_priv(dev);
591 struct mlx4_slave_state *s_state;
592 int i;
593 int ret = 0;
594
595 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
596 s_state = &priv->mfunc.master.slave_state[i];
597 if (s_state->active && s_state->last_cmd !=
598 MLX4_COMM_CMD_RESET) {
599 mlx4_warn(dev, "%s: slave: %d is still active\n",
600 __func__, i);
601 ret++;
602 }
603 }
604 return ret;
605}
606
396f2feb
JM		 607int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
608{
609 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 610
611 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
612 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 613 return -EINVAL;
614
47605df9 615 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 616 /* tunnel qp */
47605df9 617 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 618 else
47605df9 619 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 620 *qkey = qk;
621 return 0;
622}
623EXPORT_SYMBOL(mlx4_get_parav_qkey);
624
54679e14
JM		 625void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
626{
627 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
628
629 if (!mlx4_is_master(dev))
630 return;
631
632 priv->virt2phys_pkey[slave][port - 1][i] = val;
633}
634EXPORT_SYMBOL(mlx4_sync_pkey_table);
635
afa8fd1d
JM		 636void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
637{
638 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
639
640 if (!mlx4_is_master(dev))
641 return;
642
643 priv->slave_node_guids[slave] = guid;
644}
645EXPORT_SYMBOL(mlx4_put_slave_node_guid);
646
647__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
648{
649 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
650
651 if (!mlx4_is_master(dev))
652 return 0;
653
654 return priv->slave_node_guids[slave];
655}
656EXPORT_SYMBOL(mlx4_get_slave_node_guid);
657
e10903b0 658int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 659{
660 struct mlx4_priv *priv = mlx4_priv(dev);
661 struct mlx4_slave_state *s_slave;
662
663 if (!mlx4_is_master(dev))
664 return 0;
665
666 s_slave = &priv->mfunc.master.slave_state[slave];
667 return !!s_slave->active;
668}
669EXPORT_SYMBOL(mlx4_is_slave_active);
670
7b8157be
JM		 671static void slave_adjust_steering_mode(struct mlx4_dev *dev,
672 struct mlx4_dev_cap *dev_cap,
673 struct mlx4_init_hca_param *hca_param)
674{
675 dev->caps.steering_mode = hca_param->steering_mode;
676 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
677 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
678 dev->caps.fs_log_max_ucast_qp_range_size =
679 dev_cap->fs_log_max_ucast_qp_range_size;
680 } else
681 dev->caps.num_qp_per_mgm =
682 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
683
684 mlx4_dbg(dev, "Steering mode is: %s\n",
685 mlx4_steering_mode_str(dev->caps.steering_mode));
686}
687
ab9c17a0
JM		 688static int mlx4_slave_cap(struct mlx4_dev *dev)
689{
690 int err;
691 u32 page_size;
692 struct mlx4_dev_cap dev_cap;
693 struct mlx4_func_cap func_cap;
694 struct mlx4_init_hca_param hca_param;
225c6c8c 695 u8 i;
ab9c17a0
JM		 696
697 memset(&hca_param, 0, sizeof(hca_param));
698 err = mlx4_QUERY_HCA(dev, &hca_param);
699 if (err) {
1a91de28 700 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
ab9c17a0
JM		 701 return err;
702 }
703
483e0132
EP		 704 /* fail if the hca has an unknown global capability
705 * at this time global_caps should be always zeroed
706 */
707 if (hca_param.global_caps) {
ab9c17a0
JM		 708 mlx4_err(dev, "Unknown hca global capabilities\n");
709 return -ENOSYS;
710 }
711
712 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
713
ddd8a6c1
EE		 714 dev->caps.hca_core_clock = hca_param.hca_core_clock;
715
ab9c17a0 716 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 717 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 718 err = mlx4_dev_cap(dev, &dev_cap);
719 if (err) {
1a91de28 720 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 721 return err;
722 }
723
b91cb3eb
JM		 724 err = mlx4_QUERY_FW(dev);
725 if (err)
1a91de28 726 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 727
ab9c17a0
JM		 728 page_size = ~dev->caps.page_size_cap + 1;
729 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
730 if (page_size > PAGE_SIZE) {
1a91de28 731 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0
JM		 732 page_size, PAGE_SIZE);
733 return -ENODEV;
734 }
735
736 /* slave gets uar page size from QUERY_HCA fw command */
737 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
738
739 /* TODO: relax this assumption */
740 if (dev->caps.uar_page_size != PAGE_SIZE) {
741 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
742 dev->caps.uar_page_size, PAGE_SIZE);
743 return -ENODEV;
744 }
745
746 memset(&func_cap, 0, sizeof(func_cap));
47605df9 747 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 748 if (err) {
1a91de28
JP		 749 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
750 err);
ab9c17a0
JM		 751 return err;
752 }
753
754 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
755 PF_CONTEXT_BEHAVIOUR_MASK) {
756 mlx4_err(dev, "Unknown pf context behaviour\n");
757 return -ENOSYS;
758 }
759
ab9c17a0 760 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 761 dev->quotas.qp = func_cap.qp_quota;
762 dev->quotas.srq = func_cap.srq_quota;
763 dev->quotas.cq = func_cap.cq_quota;
764 dev->quotas.mpt = func_cap.mpt_quota;
765 dev->quotas.mtt = func_cap.mtt_quota;
766 dev->caps.num_qps = 1 << hca_param.log_num_qps;
767 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
768 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
769 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
770 dev->caps.num_eqs = func_cap.max_eq;
771 dev->caps.reserved_eqs = func_cap.reserved_eq;
ab9c17a0
JM		 772 dev->caps.num_pds = MLX4_NUM_PDS;
773 dev->caps.num_mgms = 0;
774 dev->caps.num_amgms = 0;
775
ab9c17a0 776 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 777 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
778 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 779 return -ENODEV;
780 }
781
99ec41d0 782 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
47605df9
JM		 783 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
784 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
785 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
786 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
787
788 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
99ec41d0
JM		 789 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
790 !dev->caps.qp0_qkey) {
47605df9
JM		 791 err = -ENOMEM;
792 goto err_mem;
793 }
794
6634961c 795 for (i = 1; i <= dev->caps.num_ports; ++i) {
225c6c8c 796 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
47605df9 797 if (err) {
1a91de28
JP		 798 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
799 i, err);
47605df9
JM		 800 goto err_mem;
801 }
99ec41d0 802 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
47605df9
JM		 803 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
804 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
805 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
806 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 807 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 808 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 809 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
810 &dev->caps.gid_table_len[i],
811 &dev->caps.pkey_table_len[i]))
47605df9 812 goto err_mem;
6634961c 813 }
6230bb23 814
ab9c17a0
JM		 815 if (dev->caps.uar_page_size * (dev->caps.num_uars -
816 dev->caps.reserved_uars) >
817 pci_resource_len(dev->pdev, 2)) {
1a91de28 818 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0
JM		 819 dev->caps.uar_page_size * dev->caps.num_uars,
820 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 821 goto err_mem;
ab9c17a0
JM		 822 }
823
08ff3235
OG		 824 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
825 dev->caps.eqe_size = 64;
826 dev->caps.eqe_factor = 1;
827 } else {
828 dev->caps.eqe_size = 32;
829 dev->caps.eqe_factor = 0;
830 }
831
832 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
833 dev->caps.cqe_size = 64;
77507aa2 834 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 835 } else {
836 dev->caps.cqe_size = 32;
837 }
838
77507aa2
IS		 839 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
840 dev->caps.eqe_size = hca_param.eqe_size;
841 dev->caps.eqe_factor = 0;
842 }
843
844 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
845 dev->caps.cqe_size = hca_param.cqe_size;
846 /* User still need to know when CQE > 32B */
847 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
848 }
849
f9bd2d7f 850 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 851 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 852
7b8157be
JM		 853 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
854
ddae0349
EE		 855 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
856 dev->caps.bf_reg_size)
857 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
858
d57febe1
MB		 859 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
860 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
861
ab9c17a0 862 return 0;
47605df9
JM		 863
864err_mem:
99ec41d0 865 kfree(dev->caps.qp0_qkey);
47605df9
JM		 866 kfree(dev->caps.qp0_tunnel);
867 kfree(dev->caps.qp0_proxy);
868 kfree(dev->caps.qp1_tunnel);
869 kfree(dev->caps.qp1_proxy);
99ec41d0
JM		 870 dev->caps.qp0_qkey = NULL;
871 dev->caps.qp0_tunnel = NULL;
872 dev->caps.qp0_proxy = NULL;
873 dev->caps.qp1_tunnel = NULL;
874 dev->caps.qp1_proxy = NULL;
47605df9
JM		 875
876 return err;
ab9c17a0 877}
225c7b1f 878
b046ffe5
EP		 879static void mlx4_request_modules(struct mlx4_dev *dev)
880{
881 int port;
882 int has_ib_port = false;
883 int has_eth_port = false;
884#define EN_DRV_NAME "mlx4_en"
885#define IB_DRV_NAME "mlx4_ib"
886
887 for (port = 1; port <= dev->caps.num_ports; port++) {
888 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
889 has_ib_port = true;
890 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
891 has_eth_port = true;
892 }
893
b046ffe5
EP		 894 if (has_eth_port)
895 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 896 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
897 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 898}
899
7ff93f8b
YP		 900/*
901 * Change the port configuration of the device.
902 * Every user of this function must hold the port mutex.
903 */
27bf91d6
YP		 904int mlx4_change_port_types(struct mlx4_dev *dev,
905 enum mlx4_port_type *port_types)
7ff93f8b
YP		 906{
907 int err = 0;
908 int change = 0;
909 int port;
910
911 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 912 /* Change the port type only if the new type is different
913 * from the current, and not set to Auto */
3d8f9308 914 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 915 change = 1;
7ff93f8b
YP		 916 }
917 if (change) {
918 mlx4_unregister_device(dev);
919 for (port = 1; port <= dev->caps.num_ports; port++) {
920 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 921 dev->caps.port_type[port] = port_types[port - 1];
6634961c 922 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 923 if (err) {
1a91de28
JP		 924 mlx4_err(dev, "Failed to set port %d, aborting\n",
925 port);
7ff93f8b
YP		 926 goto out;
927 }
928 }
929 mlx4_set_port_mask(dev);
930 err = mlx4_register_device(dev);
b046ffe5
EP		 931 if (err) {
932 mlx4_err(dev, "Failed to register device\n");
933 goto out;
934 }
935 mlx4_request_modules(dev);
7ff93f8b
YP		 936 }
937
938out:
939 return err;
940}
941
942static ssize_t show_port_type(struct device *dev,
943 struct device_attribute *attr,
944 char *buf)
945{
946 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
947 port_attr);
948 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 949 char type[8];
950
951 sprintf(type, "%s",
952 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
953 "ib" : "eth");
954 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
955 sprintf(buf, "auto (%s)\n", type);
956 else
957 sprintf(buf, "%s\n", type);
7ff93f8b 958
27bf91d6 959 return strlen(buf);
7ff93f8b
YP		 960}
961
962static ssize_t set_port_type(struct device *dev,
963 struct device_attribute *attr,
964 const char *buf, size_t count)
965{
966 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
967 port_attr);
968 struct mlx4_dev *mdev = info->dev;
969 struct mlx4_priv *priv = mlx4_priv(mdev);
970 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 971 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
0a984556 972 static DEFINE_MUTEX(set_port_type_mutex);
7ff93f8b
YP		 973 int i;
974 int err = 0;
975
0a984556
AV		 976 mutex_lock(&set_port_type_mutex);
977
7ff93f8b
YP		 978 if (!strcmp(buf, "ib\n"))
979 info->tmp_type = MLX4_PORT_TYPE_IB;
980 else if (!strcmp(buf, "eth\n"))
981 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 982 else if (!strcmp(buf, "auto\n"))
983 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 984 else {
985 mlx4_err(mdev, "%s is not supported port type\n", buf);
0a984556
AV		 986 err = -EINVAL;
987 goto err_out;
7ff93f8b
YP		 988 }
989
27bf91d6 990 mlx4_stop_sense(mdev);
7ff93f8b 991 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 992 /* Possible type is always the one that was delivered */
993 mdev->caps.possible_type[info->port] = info->tmp_type;
994
995 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 996 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 997 mdev->caps.possible_type[i+1];
998 if (types[i] == MLX4_PORT_TYPE_AUTO)
999 types[i] = mdev->caps.port_type[i+1];
1000 }
7ff93f8b 1001
58a60168
YP		 1002 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1003 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1004 for (i = 1; i <= mdev->caps.num_ports; i++) {
1005 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1006 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1007 err = -EINVAL;
1008 }
1009 }
1010 }
1011 if (err) {
1a91de28 1012 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1013 goto out;
1014 }
1015
1016 mlx4_do_sense_ports(mdev, new_types, types);
1017
1018 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1019 if (err)
1020 goto out;
1021
27bf91d6
YP		 1022 /* We are about to apply the changes after the configuration
1023 * was verified, no need to remember the temporary types
1024 * any more */
1025 for (i = 0; i < mdev->caps.num_ports; i++)
1026 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1027
27bf91d6 1028 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1029
1030out:
27bf91d6 1031 mlx4_start_sense(mdev);
7ff93f8b 1032 mutex_unlock(&priv->port_mutex);
0a984556
AV		 1033err_out:
1034 mutex_unlock(&set_port_type_mutex);
1035
7ff93f8b
YP		 1036 return err ? err : count;
1037}
1038
096335b3
OG		 1039enum ibta_mtu {
1040 IB_MTU_256 = 1,
1041 IB_MTU_512 = 2,
1042 IB_MTU_1024 = 3,
1043 IB_MTU_2048 = 4,
1044 IB_MTU_4096 = 5
1045};
1046
1047static inline int int_to_ibta_mtu(int mtu)
1048{
1049 switch (mtu) {
1050 case 256: return IB_MTU_256;
1051 case 512: return IB_MTU_512;
1052 case 1024: return IB_MTU_1024;
1053 case 2048: return IB_MTU_2048;
1054 case 4096: return IB_MTU_4096;
1055 default: return -1;
1056 }
1057}
1058
1059static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1060{
1061 switch (mtu) {
1062 case IB_MTU_256: return 256;
1063 case IB_MTU_512: return 512;
1064 case IB_MTU_1024: return 1024;
1065 case IB_MTU_2048: return 2048;
1066 case IB_MTU_4096: return 4096;
1067 default: return -1;
1068 }
1069}
1070
1071static ssize_t show_port_ib_mtu(struct device *dev,
1072 struct device_attribute *attr,
1073 char *buf)
1074{
1075 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1076 port_mtu_attr);
1077 struct mlx4_dev *mdev = info->dev;
1078
1079 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1080 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1081
1082 sprintf(buf, "%d\n",
1083 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1084 return strlen(buf);
1085}
1086
1087static ssize_t set_port_ib_mtu(struct device *dev,
1088 struct device_attribute *attr,
1089 const char *buf, size_t count)
1090{
1091 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1092 port_mtu_attr);
1093 struct mlx4_dev *mdev = info->dev;
1094 struct mlx4_priv *priv = mlx4_priv(mdev);
1095 int err, port, mtu, ibta_mtu = -1;
1096
1097 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1098 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1099 return -EINVAL;
1100 }
1101
618fad95
DB		 1102 err = kstrtoint(buf, 0, &mtu);
1103 if (!err)
096335b3
OG		 1104 ibta_mtu = int_to_ibta_mtu(mtu);
1105
618fad95 1106 if (err || ibta_mtu < 0) {
096335b3
OG		 1107 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1108 return -EINVAL;
1109 }
1110
1111 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1112
1113 mlx4_stop_sense(mdev);
1114 mutex_lock(&priv->port_mutex);
1115 mlx4_unregister_device(mdev);
1116 for (port = 1; port <= mdev->caps.num_ports; port++) {
1117 mlx4_CLOSE_PORT(mdev, port);
6634961c 1118 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1119 if (err) {
1a91de28
JP		 1120 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1121 port);
096335b3
OG		 1122 goto err_set_port;
1123 }
1124 }
1125 err = mlx4_register_device(mdev);
1126err_set_port:
1127 mutex_unlock(&priv->port_mutex);
1128 mlx4_start_sense(mdev);
1129 return err ? err : count;
1130}
1131
e8f9b2ed 1132static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1133{
1134 struct mlx4_priv *priv = mlx4_priv(dev);
1135 int err;
1136
1137 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1138 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1139 if (!priv->fw.fw_icm) {
1a91de28 1140 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1141 return -ENOMEM;
1142 }
1143
1144 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1145 if (err) {
1a91de28 1146 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1147 goto err_free;
1148 }
1149
1150 err = mlx4_RUN_FW(dev);
1151 if (err) {
1a91de28 1152 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1153 goto err_unmap_fa;
1154 }
1155
1156 return 0;
1157
1158err_unmap_fa:
1159 mlx4_UNMAP_FA(dev);
1160
1161err_free:
5b0bf5e2 1162 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1163 return err;
1164}
1165
e8f9b2ed
RD		 1166static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1167 int cmpt_entry_sz)
225c7b1f
RD		 1168{
1169 struct mlx4_priv *priv = mlx4_priv(dev);
1170 int err;
ab9c17a0 1171 int num_eqs;
225c7b1f
RD		 1172
1173 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1174 cmpt_base +
1175 ((u64) (MLX4_CMPT_TYPE_QP *
1176 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1177 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1178 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1179 0, 0);
225c7b1f
RD		 1180 if (err)
1181 goto err;
1182
1183 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1184 cmpt_base +
1185 ((u64) (MLX4_CMPT_TYPE_SRQ *
1186 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1187 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1188 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1189 if (err)
1190 goto err_qp;
1191
1192 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1193 cmpt_base +
1194 ((u64) (MLX4_CMPT_TYPE_CQ *
1195 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1196 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1197 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1198 if (err)
1199 goto err_srq;
1200
7ae0e400 1201 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1202 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1203 cmpt_base +
1204 ((u64) (MLX4_CMPT_TYPE_EQ *
1205 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1206 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1207 if (err)
1208 goto err_cq;
1209
1210 return 0;
1211
1212err_cq:
1213 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1214
1215err_srq:
1216 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1217
1218err_qp:
1219 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1220
1221err:
1222 return err;
1223}
1224
3d73c288
RD		 1225static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1226 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1227{
1228 struct mlx4_priv *priv = mlx4_priv(dev);
1229 u64 aux_pages;
ab9c17a0 1230 int num_eqs;
225c7b1f
RD		 1231 int err;
1232
1233 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1234 if (err) {
1a91de28 1235 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1236 return err;
1237 }
1238
1a91de28 1239 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1240 (unsigned long long) icm_size >> 10,
1241 (unsigned long long) aux_pages << 2);
1242
1243 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1244 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1245 if (!priv->fw.aux_icm) {
1a91de28 1246 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1247 return -ENOMEM;
1248 }
1249
1250 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1251 if (err) {
1a91de28 1252 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1253 goto err_free_aux;
1254 }
1255
1256 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1257 if (err) {
1a91de28 1258 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1259 goto err_unmap_aux;
1260 }
1261
ab9c17a0 1262
7ae0e400 1263 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1264 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1265 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1266 num_eqs, num_eqs, 0, 0);
225c7b1f 1267 if (err) {
1a91de28 1268 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1269 goto err_unmap_cmpt;
1270 }
1271
d7bb58fb
JM		 1272 /*
1273 * Reserved MTT entries must be aligned up to a cacheline
1274 * boundary, since the FW will write to them, while the driver
1275 * writes to all other MTT entries. (The variable
1276 * dev->caps.mtt_entry_sz below is really the MTT segment
1277 * size, not the raw entry size)
1278 */
1279 dev->caps.reserved_mtts =
1280 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1281 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1282
225c7b1f
RD		 1283 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1284 init_hca->mtt_base,
1285 dev->caps.mtt_entry_sz,
2b8fb286 1286 dev->caps.num_mtts,
5b0bf5e2 1287 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1288 if (err) {
1a91de28 1289 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1290 goto err_unmap_eq;
1291 }
1292
1293 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1294 init_hca->dmpt_base,
1295 dev_cap->dmpt_entry_sz,
1296 dev->caps.num_mpts,
5b0bf5e2 1297 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1298 if (err) {
1a91de28 1299 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1300 goto err_unmap_mtt;
1301 }
1302
1303 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1304 init_hca->qpc_base,
1305 dev_cap->qpc_entry_sz,
1306 dev->caps.num_qps,
93fc9e1b
YP		 1307 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1308 0, 0);
225c7b1f 1309 if (err) {
1a91de28 1310 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1311 goto err_unmap_dmpt;
1312 }
1313
1314 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1315 init_hca->auxc_base,
1316 dev_cap->aux_entry_sz,
1317 dev->caps.num_qps,
93fc9e1b
YP		 1318 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1319 0, 0);
225c7b1f 1320 if (err) {
1a91de28 1321 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1322 goto err_unmap_qp;
1323 }
1324
1325 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1326 init_hca->altc_base,
1327 dev_cap->altc_entry_sz,
1328 dev->caps.num_qps,
93fc9e1b
YP		 1329 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1330 0, 0);
225c7b1f 1331 if (err) {
1a91de28 1332 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1333 goto err_unmap_auxc;
1334 }
1335
1336 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1337 init_hca->rdmarc_base,
1338 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1339 dev->caps.num_qps,
93fc9e1b
YP		 1340 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1341 0, 0);
225c7b1f
RD		 1342 if (err) {
1343 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1344 goto err_unmap_altc;
1345 }
1346
1347 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1348 init_hca->cqc_base,
1349 dev_cap->cqc_entry_sz,
1350 dev->caps.num_cqs,
5b0bf5e2 1351 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1352 if (err) {
1a91de28 1353 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1354 goto err_unmap_rdmarc;
1355 }
1356
1357 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1358 init_hca->srqc_base,
1359 dev_cap->srq_entry_sz,
1360 dev->caps.num_srqs,
5b0bf5e2 1361 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1362 if (err) {
1a91de28 1363 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1364 goto err_unmap_cq;
1365 }
1366
1367 /*
0ff1fb65
HHZ		 1368 * For flow steering device managed mode it is required to use
1369 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1370 * required, but for simplicity just map the whole multicast
1371 * group table now. The table isn't very big and it's a lot
1372 * easier than trying to track ref counts.
225c7b1f
RD		 1373 */
1374 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1375 init_hca->mc_base,
1376 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1377 dev->caps.num_mgms + dev->caps.num_amgms,
1378 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1379 0, 0);
225c7b1f 1380 if (err) {
1a91de28 1381 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1382 goto err_unmap_srq;
1383 }
1384
1385 return 0;
1386
1387err_unmap_srq:
1388 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1389
1390err_unmap_cq:
1391 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1392
1393err_unmap_rdmarc:
1394 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1395
1396err_unmap_altc:
1397 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1398
1399err_unmap_auxc:
1400 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1401
1402err_unmap_qp:
1403 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1404
1405err_unmap_dmpt:
1406 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1407
1408err_unmap_mtt:
1409 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1410
1411err_unmap_eq:
fa0681d2 1412 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1413
1414err_unmap_cmpt:
1415 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1416 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1417 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1418 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1419
1420err_unmap_aux:
1421 mlx4_UNMAP_ICM_AUX(dev);
1422
1423err_free_aux:
5b0bf5e2 1424 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1425
1426 return err;
1427}
1428
1429static void mlx4_free_icms(struct mlx4_dev *dev)
1430{
1431 struct mlx4_priv *priv = mlx4_priv(dev);
1432
1433 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1434 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1435 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1436 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1437 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1438 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1439 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1440 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1441 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1442 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1443 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1444 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1445 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1446 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1447
1448 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1449 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1450}
1451
ab9c17a0
JM		 1452static void mlx4_slave_exit(struct mlx4_dev *dev)
1453{
1454 struct mlx4_priv *priv = mlx4_priv(dev);
1455
f3d4c89e 1456 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1457 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1a91de28 1458 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1459 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1460}
1461
c1b43dca
EC		 1462static int map_bf_area(struct mlx4_dev *dev)
1463{
1464 struct mlx4_priv *priv = mlx4_priv(dev);
1465 resource_size_t bf_start;
1466 resource_size_t bf_len;
1467 int err = 0;
1468
3d747473
JM		 1469 if (!dev->caps.bf_reg_size)
1470 return -ENXIO;
1471
ab9c17a0
JM		 1472 bf_start = pci_resource_start(dev->pdev, 2) +
1473 (dev->caps.num_uars << PAGE_SHIFT);
1474 bf_len = pci_resource_len(dev->pdev, 2) -
1475 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1476 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1477 if (!priv->bf_mapping)
1478 err = -ENOMEM;
1479
1480 return err;
1481}
1482
1483static void unmap_bf_area(struct mlx4_dev *dev)
1484{
1485 if (mlx4_priv(dev)->bf_mapping)
1486 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1487}
1488
ec693d47
AV		 1489cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1490{
1491 u32 clockhi, clocklo, clockhi1;
1492 cycle_t cycles;
1493 int i;
1494 struct mlx4_priv *priv = mlx4_priv(dev);
1495
1496 for (i = 0; i < 10; i++) {
1497 clockhi = swab32(readl(priv->clock_mapping));
1498 clocklo = swab32(readl(priv->clock_mapping + 4));
1499 clockhi1 = swab32(readl(priv->clock_mapping));
1500 if (clockhi == clockhi1)
1501 break;
1502 }
1503
1504 cycles = (u64) clockhi << 32 | (u64) clocklo;
1505
1506 return cycles;
1507}
1508EXPORT_SYMBOL_GPL(mlx4_read_clock);
1509
1510
ddd8a6c1
EE		 1511static int map_internal_clock(struct mlx4_dev *dev)
1512{
1513 struct mlx4_priv *priv = mlx4_priv(dev);
1514
1515 priv->clock_mapping =
1516 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1517 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1518
1519 if (!priv->clock_mapping)
1520 return -ENOMEM;
1521
1522 return 0;
1523}
1524
1525static void unmap_internal_clock(struct mlx4_dev *dev)
1526{
1527 struct mlx4_priv *priv = mlx4_priv(dev);
1528
1529 if (priv->clock_mapping)
1530 iounmap(priv->clock_mapping);
1531}
1532
225c7b1f
RD		 1533static void mlx4_close_hca(struct mlx4_dev *dev)
1534{
ddd8a6c1 1535 unmap_internal_clock(dev);
c1b43dca 1536 unmap_bf_area(dev);
ab9c17a0
JM		 1537 if (mlx4_is_slave(dev))
1538 mlx4_slave_exit(dev);
1539 else {
1540 mlx4_CLOSE_HCA(dev, 0);
1541 mlx4_free_icms(dev);
a0eacca9
MB		 1542 }
1543}
1544
1545static void mlx4_close_fw(struct mlx4_dev *dev)
1546{
1547 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1548 mlx4_UNMAP_FA(dev);
1549 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1550 }
1551}
1552
1553static int mlx4_init_slave(struct mlx4_dev *dev)
1554{
1555 struct mlx4_priv *priv = mlx4_priv(dev);
1556 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1557 int ret_from_reset = 0;
1558 u32 slave_read;
1559 u32 cmd_channel_ver;
1560
97989356 1561 if (atomic_read(&pf_loading)) {
1a91de28 1562 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 1563 return -EPROBE_DEFER;
1564 }
1565
f3d4c89e 1566 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1567 priv->cmd.max_cmds = 1;
1568 mlx4_warn(dev, "Sending reset\n");
1569 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1570 MLX4_COMM_TIME);
1571 /* if we are in the middle of flr the slave will try
1572 * NUM_OF_RESET_RETRIES times before leaving.*/
1573 if (ret_from_reset) {
1574 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 1575 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 1576 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1577 return -EPROBE_DEFER;
ab9c17a0
JM		 1578 } else
1579 goto err;
1580 }
1581
1582 /* check the driver version - the slave I/F revision
1583 * must match the master's */
1584 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1585 cmd_channel_ver = mlx4_comm_get_version();
1586
1587 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1588 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 1589 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 1590 goto err;
1591 }
1592
1593 mlx4_warn(dev, "Sending vhcr0\n");
1594 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1595 MLX4_COMM_TIME))
1596 goto err;
1597 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1598 MLX4_COMM_TIME))
1599 goto err;
1600 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1601 MLX4_COMM_TIME))
1602 goto err;
1603 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1604 goto err;
f3d4c89e
RD		 1605
1606 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1607 return 0;
1608
1609err:
1610 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1611 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1612 return -EIO;
225c7b1f
RD		 1613}
1614
6634961c
JM		 1615static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1616{
1617 int i;
1618
1619 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1620 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1621 dev->caps.gid_table_len[i] =
449fc488 1622 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1623 else
1624 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1625 dev->caps.pkey_table_len[i] =
1626 dev->phys_caps.pkey_phys_table_len[i] - 1;
1627 }
1628}
1629
3c439b55
JM		 1630static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1631{
1632 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1633
1634 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1635 i++) {
1636 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1637 break;
1638 }
1639
1640 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1641}
1642
7b8157be
JM		 1643static void choose_steering_mode(struct mlx4_dev *dev,
1644 struct mlx4_dev_cap *dev_cap)
1645{
3c439b55
JM		 1646 if (mlx4_log_num_mgm_entry_size == -1 &&
1647 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1648 (!mlx4_is_mfunc(dev) ||
449fc488 1649 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) &&
3c439b55
JM		 1650 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1651 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1652 dev->oper_log_mgm_entry_size =
1653 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1654 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1655 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1656 dev->caps.fs_log_max_ucast_qp_range_size =
1657 dev_cap->fs_log_max_ucast_qp_range_size;
1658 } else {
1659 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1660 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1661 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1662 else {
1663 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1664
1665 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1666 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 1667 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 1668 }
3c439b55
JM		 1669 dev->oper_log_mgm_entry_size =
1670 mlx4_log_num_mgm_entry_size > 0 ?
1671 mlx4_log_num_mgm_entry_size :
1672 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1673 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1674 }
1a91de28 1675 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 1676 mlx4_steering_mode_str(dev->caps.steering_mode),
1677 dev->oper_log_mgm_entry_size,
1678 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1679}
1680
7ffdf726
OG		 1681static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1682 struct mlx4_dev_cap *dev_cap)
1683{
1684 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1685 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1686 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1687 else
1688 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1689
1690 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1691 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1692}
1693
a0eacca9 1694static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 1695{
2d928651 1696 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 1697 int err = 0;
225c7b1f 1698
ab9c17a0
JM		 1699 if (!mlx4_is_slave(dev)) {
1700 err = mlx4_QUERY_FW(dev);
1701 if (err) {
1702 if (err == -EACCES)
1a91de28 1703 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 1704 else
1a91de28 1705 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 1706 return err;
ab9c17a0 1707 }
225c7b1f 1708
ab9c17a0
JM		 1709 err = mlx4_load_fw(dev);
1710 if (err) {
1a91de28 1711 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 1712 return err;
ab9c17a0 1713 }
225c7b1f 1714
ab9c17a0
JM		 1715 mlx4_cfg.log_pg_sz_m = 1;
1716 mlx4_cfg.log_pg_sz = 0;
1717 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1718 if (err)
1719 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 1720 }
2d928651 1721
a0eacca9
MB		 1722 return err;
1723}
1724
1725static int mlx4_init_hca(struct mlx4_dev *dev)
1726{
1727 struct mlx4_priv *priv = mlx4_priv(dev);
1728 struct mlx4_adapter adapter;
1729 struct mlx4_dev_cap dev_cap;
1730 struct mlx4_profile profile;
1731 struct mlx4_init_hca_param init_hca;
1732 u64 icm_size;
1733 struct mlx4_config_dev_params params;
1734 int err;
1735
1736 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1737 err = mlx4_dev_cap(dev, &dev_cap);
1738 if (err) {
1a91de28 1739 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 1740 goto err_stop_fw;
1741 }
225c7b1f 1742
7b8157be 1743 choose_steering_mode(dev, &dev_cap);
7ffdf726 1744 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1745
8e1a28e8
HHZ		 1746 err = mlx4_get_phys_port_id(dev);
1747 if (err)
1748 mlx4_err(dev, "Fail to get physical port id\n");
1749
6634961c
JM		 1750 if (mlx4_is_master(dev))
1751 mlx4_parav_master_pf_caps(dev);
1752
2599d858
AV		 1753 if (mlx4_low_memory_profile()) {
1754 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
1755 profile = low_mem_profile;
1756 } else {
1757 profile = default_profile;
1758 }
0ff1fb65
HHZ		 1759 if (dev->caps.steering_mode ==
1760 MLX4_STEERING_MODE_DEVICE_MANAGED)
1761 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1762
ab9c17a0
JM		 1763 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1764 &init_hca);
1765 if ((long long) icm_size < 0) {
1766 err = icm_size;
1767 goto err_stop_fw;
1768 }
225c7b1f 1769
a5bbe892
EC		 1770 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1771
ab9c17a0
JM		 1772 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1773 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1774 init_hca.mw_enabled = 0;
1775 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1776 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1777 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1778
ab9c17a0
JM		 1779 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1780 if (err)
1781 goto err_stop_fw;
225c7b1f 1782
ab9c17a0
JM		 1783 err = mlx4_INIT_HCA(dev, &init_hca);
1784 if (err) {
1a91de28 1785 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 1786 goto err_free_icm;
1787 }
7ae0e400
MB		 1788
1789 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
1790 err = mlx4_query_func(dev, &dev_cap);
1791 if (err < 0) {
1792 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
1793 goto err_stop_fw;
1794 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
1795 dev->caps.num_eqs = dev_cap.max_eqs;
1796 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
1797 dev->caps.reserved_uars = dev_cap.reserved_uars;
1798 }
1799 }
1800
ddd8a6c1
EE		 1801 /*
1802 * If TS is supported by FW
1803 * read HCA frequency by QUERY_HCA command
1804 */
1805 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1806 memset(&init_hca, 0, sizeof(init_hca));
1807 err = mlx4_QUERY_HCA(dev, &init_hca);
1808 if (err) {
1a91de28 1809 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 1810 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1811 } else {
1812 dev->caps.hca_core_clock =
1813 init_hca.hca_core_clock;
1814 }
1815
1816 /* In case we got HCA frequency 0 - disable timestamping
1817 * to avoid dividing by zero
1818 */
1819 if (!dev->caps.hca_core_clock) {
1820 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1821 mlx4_err(dev,
1a91de28 1822 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 1823 } else if (map_internal_clock(dev)) {
1824 /*
1825 * Map internal clock,
1826 * in case of failure disable timestamping
1827 */
1828 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1829 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 1830 }
1831 }
ab9c17a0
JM		 1832 } else {
1833 err = mlx4_init_slave(dev);
1834 if (err) {
5efe5355
JM		 1835 if (err != -EPROBE_DEFER)
1836 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1837 return err;
ab9c17a0 1838 }
225c7b1f 1839
ab9c17a0
JM		 1840 err = mlx4_slave_cap(dev);
1841 if (err) {
1842 mlx4_err(dev, "Failed to obtain slave caps\n");
1843 goto err_close;
1844 }
225c7b1f
RD		 1845 }
1846
ab9c17a0
JM		 1847 if (map_bf_area(dev))
1848 mlx4_dbg(dev, "Failed to map blue flame area\n");
1849
1850 /*Only the master set the ports, all the rest got it from it.*/
1851 if (!mlx4_is_slave(dev))
1852 mlx4_set_port_mask(dev);
1853
225c7b1f
RD		 1854 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1855 if (err) {
1a91de28 1856 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 1857 goto unmap_bf;
225c7b1f
RD		 1858 }
1859
f8c6455b
SM		 1860 /* Query CONFIG_DEV parameters */
1861 err = mlx4_config_dev_retrieval(dev, &params);
1862 if (err && err != -ENOTSUPP) {
1863 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
1864 } else if (!err) {
1865 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
1866 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
1867 }
225c7b1f 1868 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1869 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1870
1871 return 0;
1872
bef772eb 1873unmap_bf:
ddd8a6c1 1874 unmap_internal_clock(dev);
bef772eb
AY		 1875 unmap_bf_area(dev);
1876
b38f2879 1877 if (mlx4_is_slave(dev)) {
99ec41d0 1878 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 1879 kfree(dev->caps.qp0_tunnel);
1880 kfree(dev->caps.qp0_proxy);
1881 kfree(dev->caps.qp1_tunnel);
1882 kfree(dev->caps.qp1_proxy);
1883 }
1884
225c7b1f 1885err_close:
41929ed2
DB		 1886 if (mlx4_is_slave(dev))
1887 mlx4_slave_exit(dev);
1888 else
1889 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 1890
1891err_free_icm:
ab9c17a0
JM		 1892 if (!mlx4_is_slave(dev))
1893 mlx4_free_icms(dev);
225c7b1f
RD		 1894
1895err_stop_fw:
ab9c17a0
JM		 1896 if (!mlx4_is_slave(dev)) {
1897 mlx4_UNMAP_FA(dev);
1898 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1899 }
225c7b1f
RD		 1900 return err;
1901}
1902
f2a3f6a3
OG		 1903static int mlx4_init_counters_table(struct mlx4_dev *dev)
1904{
1905 struct mlx4_priv *priv = mlx4_priv(dev);
1906 int nent;
1907
1908 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1909 return -ENOENT;
1910
1911 nent = dev->caps.max_counters;
1912 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1913}
1914
1915static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1916{
1917 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1918}
1919
ba062d52 1920int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1921{
1922 struct mlx4_priv *priv = mlx4_priv(dev);
1923
1924 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1925 return -ENOENT;
1926
1927 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1928 if (*idx == -1)
1929 return -ENOMEM;
1930
1931 return 0;
1932}
ba062d52
JM		 1933
1934int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1935{
1936 u64 out_param;
1937 int err;
1938
1939 if (mlx4_is_mfunc(dev)) {
1940 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1941 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1942 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1943 if (!err)
1944 *idx = get_param_l(&out_param);
1945
1946 return err;
1947 }
1948 return __mlx4_counter_alloc(dev, idx);
1949}
f2a3f6a3
OG		 1950EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1951
ba062d52 1952void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 1953{
7c6d74d2 1954 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 1955 return;
1956}
ba062d52
JM		 1957
1958void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1959{
e7dbeba8 1960 u64 in_param = 0;
ba062d52
JM		 1961
1962 if (mlx4_is_mfunc(dev)) {
1963 set_param_l(&in_param, idx);
1964 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1965 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1966 MLX4_CMD_WRAPPED);
1967 return;
1968 }
1969 __mlx4_counter_free(dev, idx);
1970}
f2a3f6a3
OG		 1971EXPORT_SYMBOL_GPL(mlx4_counter_free);
1972
3d73c288 1973static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1974{
1975 struct mlx4_priv *priv = mlx4_priv(dev);
1976 int err;
7ff93f8b 1977 int port;
9a5aa622 1978 __be32 ib_port_default_caps;
225c7b1f 1979
225c7b1f
RD		 1980 err = mlx4_init_uar_table(dev);
1981 if (err) {
1a91de28
JP		 1982 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
1983 return err;
225c7b1f
RD		 1984 }
1985
1986 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1987 if (err) {
1a91de28 1988 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 1989 goto err_uar_table_free;
1990 }
1991
4979d18f 1992 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 1993 if (!priv->kar) {
1a91de28 1994 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 1995 err = -ENOMEM;
1996 goto err_uar_free;
1997 }
1998
1999 err = mlx4_init_pd_table(dev);
2000 if (err) {
1a91de28 2001 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2002 goto err_kar_unmap;
2003 }
2004
012a8ff5
SH		 2005 err = mlx4_init_xrcd_table(dev);
2006 if (err) {
1a91de28 2007 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2008 goto err_pd_table_free;
2009 }
2010
225c7b1f
RD		 2011 err = mlx4_init_mr_table(dev);
2012 if (err) {
1a91de28 2013 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2014 goto err_xrcd_table_free;
225c7b1f
RD		 2015 }
2016
fe6f700d
YP		 2017 if (!mlx4_is_slave(dev)) {
2018 err = mlx4_init_mcg_table(dev);
2019 if (err) {
1a91de28 2020 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2021 goto err_mr_table_free;
2022 }
114840c3
JM		 2023 err = mlx4_config_mad_demux(dev);
2024 if (err) {
2025 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2026 goto err_mcg_table_free;
2027 }
fe6f700d
YP		 2028 }
2029
225c7b1f
RD		 2030 err = mlx4_init_eq_table(dev);
2031 if (err) {
1a91de28 2032 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2033 goto err_mcg_table_free;
225c7b1f
RD		 2034 }
2035
2036 err = mlx4_cmd_use_events(dev);
2037 if (err) {
1a91de28 2038 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2039 goto err_eq_table_free;
2040 }
2041
2042 err = mlx4_NOP(dev);
2043 if (err) {
08fb1055 2044 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2045 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
b8dd786f 2046 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1a91de28 2047 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2048 } else {
1a91de28 2049 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
b8dd786f 2050 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 2051 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2052 }
225c7b1f
RD		 2053
2054 goto err_cmd_poll;
2055 }
2056
2057 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2058
2059 err = mlx4_init_cq_table(dev);
2060 if (err) {
1a91de28 2061 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2062 goto err_cmd_poll;
2063 }
2064
2065 err = mlx4_init_srq_table(dev);
2066 if (err) {
1a91de28 2067 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2068 goto err_cq_table_free;
2069 }
2070
2071 err = mlx4_init_qp_table(dev);
2072 if (err) {
1a91de28 2073 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2074 goto err_srq_table_free;
2075 }
2076
f2a3f6a3
OG		 2077 err = mlx4_init_counters_table(dev);
2078 if (err && err != -ENOENT) {
1a91de28 2079 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
fe6f700d 2080 goto err_qp_table_free;
f2a3f6a3
OG		 2081 }
2082
ab9c17a0
JM		 2083 if (!mlx4_is_slave(dev)) {
2084 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2085 ib_port_default_caps = 0;
2086 err = mlx4_get_port_ib_caps(dev, port,
2087 &ib_port_default_caps);
2088 if (err)
1a91de28
JP		 2089 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2090 port, err);
ab9c17a0
JM		 2091 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2092
2aca1172
JM		 2093 /* initialize per-slave default ib port capabilities */
2094 if (mlx4_is_master(dev)) {
2095 int i;
2096 for (i = 0; i < dev->num_slaves; i++) {
2097 if (i == mlx4_master_func_num(dev))
2098 continue;
2099 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2100 ib_port_default_caps;
2aca1172
JM		 2101 }
2102 }
2103
096335b3
OG		 2104 if (mlx4_is_mfunc(dev))
2105 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2106 else
2107 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2108
6634961c
JM		 2109 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2110 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2111 if (err) {
2112 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2113 port);
ab9c17a0
JM		 2114 goto err_counters_table_free;
2115 }
7ff93f8b
YP		 2116 }
2117 }
2118
225c7b1f
RD		 2119 return 0;
2120
f2a3f6a3
OG		 2121err_counters_table_free:
2122 mlx4_cleanup_counters_table(dev);
2123
225c7b1f
RD		 2124err_qp_table_free:
2125 mlx4_cleanup_qp_table(dev);
2126
2127err_srq_table_free:
2128 mlx4_cleanup_srq_table(dev);
2129
2130err_cq_table_free:
2131 mlx4_cleanup_cq_table(dev);
2132
2133err_cmd_poll:
2134 mlx4_cmd_use_polling(dev);
2135
2136err_eq_table_free:
2137 mlx4_cleanup_eq_table(dev);
2138
fe6f700d
YP		 2139err_mcg_table_free:
2140 if (!mlx4_is_slave(dev))
2141 mlx4_cleanup_mcg_table(dev);
2142
ee49bd93 2143err_mr_table_free:
225c7b1f
RD		 2144 mlx4_cleanup_mr_table(dev);
2145
012a8ff5
SH		 2146err_xrcd_table_free:
2147 mlx4_cleanup_xrcd_table(dev);
2148
225c7b1f
RD		 2149err_pd_table_free:
2150 mlx4_cleanup_pd_table(dev);
2151
2152err_kar_unmap:
2153 iounmap(priv->kar);
2154
2155err_uar_free:
2156 mlx4_uar_free(dev, &priv->driver_uar);
2157
2158err_uar_table_free:
2159 mlx4_cleanup_uar_table(dev);
2160 return err;
2161}
2162
e8f9b2ed 2163static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2164{
2165 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2166 struct msix_entry *entries;
225c7b1f
RD		 2167 int i;
2168
2169 if (msi_x) {
7ae0e400
MB		 2170 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ;
2171
ca4c7b35
OG		 2172 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2173 nreq);
ab9c17a0 2174
b8dd786f
YP		 2175 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2176 if (!entries)
2177 goto no_msi;
2178
2179 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2180 entries[i].entry = i;
2181
66e2f9c1
AG		 2182 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
2183
2184 if (nreq < 0) {
5bf0da7d 2185 kfree(entries);
225c7b1f 2186 goto no_msi;
66e2f9c1 2187 } else if (nreq < MSIX_LEGACY_SZ +
1a91de28 2188 dev->caps.num_ports * MIN_MSIX_P_PORT) {
0b7ca5a9
YP		 2189 /*Working in legacy mode , all EQ's shared*/
2190 dev->caps.comp_pool = 0;
2191 dev->caps.num_comp_vectors = nreq - 1;
2192 } else {
2193 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2194 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2195 }
b8dd786f 2196 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2197 priv->eq_table.eq[i].irq = entries[i].vector;
2198
2199 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2200
2201 kfree(entries);
225c7b1f
RD		 2202 return;
2203 }
2204
2205no_msi:
b8dd786f 2206 dev->caps.num_comp_vectors = 1;
0b7ca5a9 2207 dev->caps.comp_pool = 0;
b8dd786f
YP		 2208
2209 for (i = 0; i < 2; ++i)
225c7b1f
RD		 2210 priv->eq_table.eq[i].irq = dev->pdev->irq;
2211}
2212
7ff93f8b 2213static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2214{
2215 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2216 int err = 0;
2a2336f8
YP		 2217
2218 info->dev = dev;
2219 info->port = port;
ab9c17a0 2220 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2221 mlx4_init_mac_table(dev, &info->mac_table);
2222 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2223 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2224 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2225 }
7ff93f8b
YP		 2226
2227 sprintf(info->dev_name, "mlx4_port%d", port);
2228 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2229 if (mlx4_is_mfunc(dev))
2230 info->port_attr.attr.mode = S_IRUGO;
2231 else {
2232 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2233 info->port_attr.store = set_port_type;
2234 }
7ff93f8b 2235 info->port_attr.show = show_port_type;
3691c964 2236 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 2237
2238 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2239 if (err) {
2240 mlx4_err(dev, "Failed to create file for port %d\n", port);
2241 info->port = -1;
2242 }
2243
096335b3
OG		 2244 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2245 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2246 if (mlx4_is_mfunc(dev))
2247 info->port_mtu_attr.attr.mode = S_IRUGO;
2248 else {
2249 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2250 info->port_mtu_attr.store = set_port_ib_mtu;
2251 }
2252 info->port_mtu_attr.show = show_port_ib_mtu;
2253 sysfs_attr_init(&info->port_mtu_attr.attr);
2254
2255 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2256 if (err) {
2257 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2258 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2259 info->port = -1;
2260 }
2261
7ff93f8b
YP		 2262 return err;
2263}
2264
2265static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2266{
2267 if (info->port < 0)
2268 return;
2269
2270 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 2271 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 2272}
2273
b12d93d6
YP		 2274static int mlx4_init_steering(struct mlx4_dev *dev)
2275{
2276 struct mlx4_priv *priv = mlx4_priv(dev);
2277 int num_entries = dev->caps.num_ports;
2278 int i, j;
2279
2280 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2281 if (!priv->steer)
2282 return -ENOMEM;
2283
45b51365 2284 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2285 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2286 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2287 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2288 }
b12d93d6
YP		 2289 return 0;
2290}
2291
2292static void mlx4_clear_steering(struct mlx4_dev *dev)
2293{
2294 struct mlx4_priv *priv = mlx4_priv(dev);
2295 struct mlx4_steer_index *entry, *tmp_entry;
2296 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2297 int num_entries = dev->caps.num_ports;
2298 int i, j;
2299
2300 for (i = 0; i < num_entries; i++) {
2301 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2302 list_for_each_entry_safe(pqp, tmp_pqp,
2303 &priv->steer[i].promisc_qps[j],
2304 list) {
2305 list_del(&pqp->list);
2306 kfree(pqp);
2307 }
2308 list_for_each_entry_safe(entry, tmp_entry,
2309 &priv->steer[i].steer_entries[j],
2310 list) {
2311 list_del(&entry->list);
2312 list_for_each_entry_safe(pqp, tmp_pqp,
2313 &entry->duplicates,
2314 list) {
2315 list_del(&pqp->list);
2316 kfree(pqp);
2317 }
2318 kfree(entry);
2319 }
2320 }
2321 }
2322 kfree(priv->steer);
2323}
2324
ab9c17a0
JM		 2325static int extended_func_num(struct pci_dev *pdev)
2326{
2327 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2328}
2329
2330#define MLX4_OWNER_BASE 0x8069c
2331#define MLX4_OWNER_SIZE 4
2332
2333static int mlx4_get_ownership(struct mlx4_dev *dev)
2334{
2335 void __iomem *owner;
2336 u32 ret;
2337
57dbf29a
KSS		 2338 if (pci_channel_offline(dev->pdev))
2339 return -EIO;
2340
ab9c17a0
JM		 2341 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2342 MLX4_OWNER_SIZE);
2343 if (!owner) {
2344 mlx4_err(dev, "Failed to obtain ownership bit\n");
2345 return -ENOMEM;
2346 }
2347
2348 ret = readl(owner);
2349 iounmap(owner);
2350 return (int) !!ret;
2351}
2352
2353static void mlx4_free_ownership(struct mlx4_dev *dev)
2354{
2355 void __iomem *owner;
2356
57dbf29a
KSS		 2357 if (pci_channel_offline(dev->pdev))
2358 return;
2359
ab9c17a0
JM		 2360 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2361 MLX4_OWNER_SIZE);
2362 if (!owner) {
2363 mlx4_err(dev, "Failed to obtain ownership bit\n");
2364 return;
2365 }
2366 writel(0, owner);
2367 msleep(1000);
2368 iounmap(owner);
2369}
2370
a0eacca9
MB		 2371#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2372 !!((flags) & MLX4_FLAG_MASTER))
2373
2374static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
2375 u8 total_vfs, int existing_vfs)
2376{
2377 u64 dev_flags = dev->flags;
2378
2379 dev->dev_vfs = kzalloc(
2380 total_vfs * sizeof(*dev->dev_vfs),
2381 GFP_KERNEL);
2382 if (NULL == dev->dev_vfs) {
2383 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2384 goto disable_sriov;
2385 } else if (!(dev->flags & MLX4_FLAG_SRIOV)) {
2386 int err = 0;
2387
2388 atomic_inc(&pf_loading);
2389 if (existing_vfs) {
2390 if (existing_vfs != total_vfs)
2391 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2392 existing_vfs, total_vfs);
2393 } else {
2394 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2395 err = pci_enable_sriov(pdev, total_vfs);
2396 }
2397 if (err) {
2398 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2399 err);
2400 atomic_dec(&pf_loading);
2401 goto disable_sriov;
2402 } else {
2403 mlx4_warn(dev, "Running in master mode\n");
2404 dev_flags |= MLX4_FLAG_SRIOV |
2405 MLX4_FLAG_MASTER;
2406 dev_flags &= ~MLX4_FLAG_SLAVE;
2407 dev->num_vfs = total_vfs;
2408 }
2409 }
2410 return dev_flags;
2411
2412disable_sriov:
2413 dev->num_vfs = 0;
2414 kfree(dev->dev_vfs);
2415 return dev_flags & ~MLX4_FLAG_MASTER;
2416}
2417
de966c59
MB		 2418enum {
2419 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2420};
2421
2422static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
2423 int *nvfs)
2424{
2425 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
2426 /* Checking for 64 VFs as a limitation of CX2 */
2427 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
2428 requested_vfs >= 64) {
2429 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
2430 requested_vfs);
2431 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
2432 }
2433 return 0;
2434}
2435
e1c00e10
MD		 2436static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
2437 int total_vfs, int *nvfs, struct mlx4_priv *priv)
225c7b1f 2438{
225c7b1f 2439 struct mlx4_dev *dev;
e1c00e10 2440 unsigned sum = 0;
225c7b1f 2441 int err;
2a2336f8 2442 int port;
e1c00e10 2443 int i;
7ae0e400 2444 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 2445 int existing_vfs = 0;
225c7b1f 2446
e1c00e10 2447 dev = &priv->dev;
225c7b1f 2448
b581401e
RD		 2449 INIT_LIST_HEAD(&priv->ctx_list);
2450 spin_lock_init(&priv->ctx_lock);
225c7b1f 2451
7ff93f8b
YP		 2452 mutex_init(&priv->port_mutex);
2453
6296883c
YP		 2454 INIT_LIST_HEAD(&priv->pgdir_list);
2455 mutex_init(&priv->pgdir_mutex);
2456
c1b43dca
EC		 2457 INIT_LIST_HEAD(&priv->bf_list);
2458 mutex_init(&priv->bf_mutex);
2459
aca7a3ac 2460 dev->rev_id = pdev->revision;
6e7136ed 2461 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 2462
ab9c17a0 2463 /* Detect if this device is a virtual function */
839f1243 2464 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2465 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2466 dev->flags |= MLX4_FLAG_SLAVE;
2467 } else {
2468 /* We reset the device and enable SRIOV only for physical
2469 * devices. Try to claim ownership on the device;
2470 * if already taken, skip -- do not allow multiple PFs */
2471 err = mlx4_get_ownership(dev);
2472 if (err) {
2473 if (err < 0)
e1c00e10 2474 return err;
ab9c17a0 2475 else {
1a91de28 2476 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 2477 return -EINVAL;
ab9c17a0
JM		 2478 }
2479 }
aca7a3ac 2480
fe6f700d
YP		 2481 atomic_set(&priv->opreq_count, 0);
2482 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2483
ab9c17a0
JM		 2484 /*
2485 * Now reset the HCA before we touch the PCI capabilities or
2486 * attempt a firmware command, since a boot ROM may have left
2487 * the HCA in an undefined state.
2488 */
2489 err = mlx4_reset(dev);
2490 if (err) {
1a91de28 2491 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 2492 goto err_sriov;
ab9c17a0 2493 }
7ae0e400
MB		 2494
2495 if (total_vfs) {
2496 existing_vfs = pci_num_vf(pdev);
2497 dev->flags = MLX4_FLAG_MASTER;
2498 dev->num_vfs = total_vfs;
2499 }
225c7b1f
RD		 2500 }
2501
ab9c17a0 2502slave_start:
521130d1
EE		 2503 err = mlx4_cmd_init(dev);
2504 if (err) {
1a91de28 2505 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 2506 goto err_sriov;
2507 }
2508
2509 /* In slave functions, the communication channel must be initialized
2510 * before posting commands. Also, init num_slaves before calling
2511 * mlx4_init_hca */
2512 if (mlx4_is_mfunc(dev)) {
7ae0e400 2513 if (mlx4_is_master(dev)) {
ab9c17a0 2514 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 2515
2516 } else {
ab9c17a0 2517 dev->num_slaves = 0;
f356fcbe
JM		 2518 err = mlx4_multi_func_init(dev);
2519 if (err) {
1a91de28 2520 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 2521 goto err_cmd;
2522 }
2523 }
225c7b1f
RD		 2524 }
2525
a0eacca9
MB		 2526 err = mlx4_init_fw(dev);
2527 if (err) {
2528 mlx4_err(dev, "Failed to init fw, aborting.\n");
2529 goto err_mfunc;
2530 }
2531
7ae0e400
MB		 2532 if (mlx4_is_master(dev)) {
2533 if (!dev_cap) {
2534 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
2535
2536 if (!dev_cap) {
2537 err = -ENOMEM;
2538 goto err_fw;
2539 }
2540
2541 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2542 if (err) {
2543 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2544 goto err_fw;
2545 }
2546
de966c59
MB		 2547 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2548 goto err_fw;
2549
7ae0e400
MB		 2550 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2551 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
2552 existing_vfs);
2553
2554 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2555 dev->flags = dev_flags;
2556 if (!SRIOV_VALID_STATE(dev->flags)) {
2557 mlx4_err(dev, "Invalid SRIOV state\n");
2558 goto err_sriov;
2559 }
2560 err = mlx4_reset(dev);
2561 if (err) {
2562 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2563 goto err_sriov;
2564 }
2565 goto slave_start;
2566 }
2567 } else {
2568 /* Legacy mode FW requires SRIOV to be enabled before
2569 * doing QUERY_DEV_CAP, since max_eq's value is different if
2570 * SRIOV is enabled.
2571 */
2572 memset(dev_cap, 0, sizeof(*dev_cap));
2573 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2574 if (err) {
2575 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2576 goto err_fw;
2577 }
de966c59
MB		 2578
2579 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2580 goto err_fw;
7ae0e400
MB		 2581 }
2582 }
2583
225c7b1f 2584 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2585 if (err) {
2586 if (err == -EACCES) {
2587 /* Not primary Physical function
2588 * Running in slave mode */
ffc39f6d 2589 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 2590 /* We're not a PF */
2591 if (dev->flags & MLX4_FLAG_SRIOV) {
2592 if (!existing_vfs)
2593 pci_disable_sriov(pdev);
2594 if (mlx4_is_master(dev))
2595 atomic_dec(&pf_loading);
2596 dev->flags &= ~MLX4_FLAG_SRIOV;
2597 }
2598 if (!mlx4_is_slave(dev))
2599 mlx4_free_ownership(dev);
ab9c17a0
JM		 2600 dev->flags |= MLX4_FLAG_SLAVE;
2601 dev->flags &= ~MLX4_FLAG_MASTER;
2602 goto slave_start;
2603 } else
a0eacca9 2604 goto err_fw;
ab9c17a0
JM		 2605 }
2606
7ae0e400
MB		 2607 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2608 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, existing_vfs);
2609
2610 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
2611 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
2612 dev->flags = dev_flags;
2613 err = mlx4_cmd_init(dev);
2614 if (err) {
2615 /* Only VHCR is cleaned up, so could still
2616 * send FW commands
2617 */
2618 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
2619 goto err_close;
2620 }
2621 } else {
2622 dev->flags = dev_flags;
2623 }
2624
2625 if (!SRIOV_VALID_STATE(dev->flags)) {
2626 mlx4_err(dev, "Invalid SRIOV state\n");
2627 goto err_close;
2628 }
2629 }
2630
b912b2f8
EP		 2631 /* check if the device is functioning at its maximum possible speed.
2632 * No return code for this call, just warn the user in case of PCI
2633 * express device capabilities are under-satisfied by the bus.
2634 */
83d3459a
EP		 2635 if (!mlx4_is_slave(dev))
2636 mlx4_check_pcie_caps(dev);
b912b2f8 2637
ab9c17a0
JM		 2638 /* In master functions, the communication channel must be initialized
2639 * after obtaining its address from fw */
2640 if (mlx4_is_master(dev)) {
e1c00e10
MD		 2641 int ib_ports = 0;
2642
2643 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2644 ib_ports++;
2645
2646 if (ib_ports &&
2647 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2648 mlx4_err(dev,
2649 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2650 err = -EINVAL;
2651 goto err_close;
2652 }
2653 if (dev->caps.num_ports < 2 &&
2654 num_vfs_argc > 1) {
2655 err = -EINVAL;
2656 mlx4_err(dev,
2657 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2658 dev->caps.num_ports);
ab9c17a0
JM		 2659 goto err_close;
2660 }
e1c00e10 2661 memcpy(dev->nvfs, nvfs, sizeof(dev->nvfs));
dd41cc3b 2662
e1c00e10
MD		 2663 for (i = 0; i < sizeof(dev->nvfs)/sizeof(dev->nvfs[0]); i++) {
2664 unsigned j;
2665
2666 for (j = 0; j < dev->nvfs[i]; ++sum, ++j) {
2667 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
2668 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2669 dev->caps.num_ports;
1ab95d37
MB		 2670 }
2671 }
e1c00e10
MD		 2672
2673 /* In master functions, the communication channel
2674 * must be initialized after obtaining its address from fw
2675 */
2676 err = mlx4_multi_func_init(dev);
2677 if (err) {
2678 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
2679 goto err_close;
2680 }
ab9c17a0 2681 }
225c7b1f 2682
b8dd786f
YP		 2683 err = mlx4_alloc_eq_table(dev);
2684 if (err)
ab9c17a0 2685 goto err_master_mfunc;
b8dd786f 2686
0b7ca5a9 2687 priv->msix_ctl.pool_bm = 0;
730c41d5 2688 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2689
08fb1055 2690 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2691 if ((mlx4_is_mfunc(dev)) &&
2692 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2693 err = -ENOSYS;
1a91de28 2694 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 2695 goto err_free_eq;
ab9c17a0
JM		 2696 }
2697
2698 if (!mlx4_is_slave(dev)) {
2699 err = mlx4_init_steering(dev);
2700 if (err)
e1c00e10 2701 goto err_disable_msix;
ab9c17a0 2702 }
b12d93d6 2703
225c7b1f 2704 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2705 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2706 !mlx4_is_mfunc(dev)) {
08fb1055 2707 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2708 dev->caps.num_comp_vectors = 1;
2709 dev->caps.comp_pool = 0;
08fb1055
MT		 2710 pci_disable_msix(pdev);
2711 err = mlx4_setup_hca(dev);
2712 }
2713
225c7b1f 2714 if (err)
b12d93d6 2715 goto err_steer;
225c7b1f 2716
5a0d0a61
JM		 2717 mlx4_init_quotas(dev);
2718
7ff93f8b
YP		 2719 for (port = 1; port <= dev->caps.num_ports; port++) {
2720 err = mlx4_init_port_info(dev, port);
2721 if (err)
2722 goto err_port;
2723 }
2a2336f8 2724
225c7b1f
RD		 2725 err = mlx4_register_device(dev);
2726 if (err)
7ff93f8b 2727 goto err_port;
225c7b1f 2728
b046ffe5
EP		 2729 mlx4_request_modules(dev);
2730
27bf91d6
YP		 2731 mlx4_sense_init(dev);
2732 mlx4_start_sense(dev);
2733
befdf897 2734 priv->removed = 0;
225c7b1f 2735
e1a5ddc5
AV		 2736 if (mlx4_is_master(dev) && dev->num_vfs)
2737 atomic_dec(&pf_loading);
2738
225c7b1f
RD		 2739 return 0;
2740
7ff93f8b 2741err_port:
b4f77264 2742 for (--port; port >= 1; --port)
7ff93f8b
YP		 2743 mlx4_cleanup_port_info(&priv->port[port]);
2744
f2a3f6a3 2745 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2746 mlx4_cleanup_qp_table(dev);
2747 mlx4_cleanup_srq_table(dev);
2748 mlx4_cleanup_cq_table(dev);
2749 mlx4_cmd_use_polling(dev);
2750 mlx4_cleanup_eq_table(dev);
fe6f700d 2751 mlx4_cleanup_mcg_table(dev);
225c7b1f 2752 mlx4_cleanup_mr_table(dev);
012a8ff5 2753 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2754 mlx4_cleanup_pd_table(dev);
2755 mlx4_cleanup_uar_table(dev);
2756
b12d93d6 2757err_steer:
ab9c17a0
JM		 2758 if (!mlx4_is_slave(dev))
2759 mlx4_clear_steering(dev);
b12d93d6 2760
e1c00e10
MD		 2761err_disable_msix:
2762 if (dev->flags & MLX4_FLAG_MSI_X)
2763 pci_disable_msix(pdev);
2764
b8dd786f
YP		 2765err_free_eq:
2766 mlx4_free_eq_table(dev);
2767
ab9c17a0
JM		 2768err_master_mfunc:
2769 if (mlx4_is_master(dev))
2770 mlx4_multi_func_cleanup(dev);
2771
b38f2879 2772 if (mlx4_is_slave(dev)) {
99ec41d0 2773 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2774 kfree(dev->caps.qp0_tunnel);
2775 kfree(dev->caps.qp0_proxy);
2776 kfree(dev->caps.qp1_tunnel);
2777 kfree(dev->caps.qp1_proxy);
2778 }
2779
225c7b1f
RD		 2780err_close:
2781 mlx4_close_hca(dev);
2782
a0eacca9
MB		 2783err_fw:
2784 mlx4_close_fw(dev);
2785
ab9c17a0
JM		 2786err_mfunc:
2787 if (mlx4_is_slave(dev))
2788 mlx4_multi_func_cleanup(dev);
2789
225c7b1f 2790err_cmd:
ffc39f6d 2791 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 2792
ab9c17a0 2793err_sriov:
bbb07af4 2794 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs)
ab9c17a0
JM		 2795 pci_disable_sriov(pdev);
2796
e1a5ddc5
AV		 2797 if (mlx4_is_master(dev) && dev->num_vfs)
2798 atomic_dec(&pf_loading);
2799
1ab95d37
MB		 2800 kfree(priv->dev.dev_vfs);
2801
e1c00e10
MD		 2802 if (!mlx4_is_slave(dev))
2803 mlx4_free_ownership(dev);
2804
7ae0e400 2805 kfree(dev_cap);
e1c00e10
MD		 2806 return err;
2807}
2808
2809static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
2810 struct mlx4_priv *priv)
2811{
2812 int err;
2813 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2814 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2815 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2816 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2817 unsigned total_vfs = 0;
2818 unsigned int i;
2819
2820 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2821
2822 err = pci_enable_device(pdev);
2823 if (err) {
2824 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
2825 return err;
2826 }
2827
2828 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2829 * per port, we must limit the number of VFs to 63 (since their are
2830 * 128 MACs)
2831 */
2832 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2833 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2834 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
2835 if (nvfs[i] < 0) {
2836 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2837 err = -EINVAL;
2838 goto err_disable_pdev;
2839 }
2840 }
2841 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2842 i++) {
2843 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
2844 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2845 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2846 err = -EINVAL;
2847 goto err_disable_pdev;
2848 }
2849 }
2850 if (total_vfs >= MLX4_MAX_NUM_VF) {
2851 dev_err(&pdev->dev,
2852 "Requested more VF's (%d) than allowed (%d)\n",
2853 total_vfs, MLX4_MAX_NUM_VF - 1);
2854 err = -EINVAL;
2855 goto err_disable_pdev;
2856 }
2857
2858 for (i = 0; i < MLX4_MAX_PORTS; i++) {
2859 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2860 dev_err(&pdev->dev,
2861 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2862 nvfs[i] + nvfs[2], i + 1,
2863 MLX4_MAX_NUM_VF_P_PORT - 1);
2864 err = -EINVAL;
2865 goto err_disable_pdev;
2866 }
2867 }
2868
2869 /* Check for BARs. */
2870 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2871 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2872 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2873 pci_dev_data, pci_resource_flags(pdev, 0));
2874 err = -ENODEV;
2875 goto err_disable_pdev;
2876 }
2877 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2878 dev_err(&pdev->dev, "Missing UAR, aborting\n");
2879 err = -ENODEV;
2880 goto err_disable_pdev;
2881 }
2882
2883 err = pci_request_regions(pdev, DRV_NAME);
2884 if (err) {
2885 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2886 goto err_disable_pdev;
2887 }
2888
2889 pci_set_master(pdev);
2890
2891 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2892 if (err) {
2893 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
2894 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2895 if (err) {
2896 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
2897 goto err_release_regions;
2898 }
2899 }
2900 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2901 if (err) {
2902 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
2903 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2904 if (err) {
2905 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
2906 goto err_release_regions;
2907 }
2908 }
2909
2910 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2911 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2912 /* Detect if this device is a virtual function */
2913 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2914 /* When acting as pf, we normally skip vfs unless explicitly
2915 * requested to probe them.
2916 */
2917 if (total_vfs) {
2918 unsigned vfs_offset = 0;
2919
2920 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
2921 vfs_offset + nvfs[i] < extended_func_num(pdev);
2922 vfs_offset += nvfs[i], i++)
2923 ;
2924 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
2925 err = -ENODEV;
2926 goto err_release_regions;
2927 }
2928 if ((extended_func_num(pdev) - vfs_offset)
2929 > prb_vf[i]) {
2930 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
2931 extended_func_num(pdev));
2932 err = -ENODEV;
2933 goto err_release_regions;
2934 }
2935 }
2936 }
2937
2938 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
2939 if (err)
2940 goto err_release_regions;
2941 return 0;
225c7b1f 2942
a01df0fe
RD		 2943err_release_regions:
2944 pci_release_regions(pdev);
225c7b1f
RD		 2945
2946err_disable_pdev:
2947 pci_disable_device(pdev);
2948 pci_set_drvdata(pdev, NULL);
2949 return err;
2950}
2951
1dd06ae8 2952static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 2953{
befdf897
WY		 2954 struct mlx4_priv *priv;
2955 struct mlx4_dev *dev;
e1c00e10 2956 int ret;
befdf897 2957
0a645e80 2958 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2959
befdf897
WY		 2960 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2961 if (!priv)
2962 return -ENOMEM;
2963
2964 dev = &priv->dev;
e1c00e10 2965 dev->pdev = pdev;
befdf897
WY		 2966 pci_set_drvdata(pdev, dev);
2967 priv->pci_dev_data = id->driver_data;
2968
e1c00e10
MD		 2969 ret = __mlx4_init_one(pdev, id->driver_data, priv);
2970 if (ret)
2971 kfree(priv);
2972
2973 return ret;
3d73c288
RD		 2974}
2975
e1c00e10 2976static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f
RD		 2977{
2978 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2979 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 2980 int pci_dev_data;
225c7b1f 2981 int p;
bbb07af4 2982 int active_vfs = 0;
225c7b1f 2983
befdf897
WY		 2984 if (priv->removed)
2985 return;
225c7b1f 2986
befdf897 2987 pci_dev_data = priv->pci_dev_data;
225c7b1f 2988
bbb07af4
JM		 2989 /* Disabling SR-IOV is not allowed while there are active vf's */
2990 if (mlx4_is_master(dev)) {
2991 active_vfs = mlx4_how_many_lives_vf(dev);
2992 if (active_vfs) {
2993 pr_warn("Removing PF when there are active VF's !!\n");
2994 pr_warn("Will not disable SR-IOV.\n");
2995 }
2996 }
befdf897
WY		 2997 mlx4_stop_sense(dev);
2998 mlx4_unregister_device(dev);
225c7b1f 2999
befdf897
WY		 3000 for (p = 1; p <= dev->caps.num_ports; p++) {
3001 mlx4_cleanup_port_info(&priv->port[p]);
3002 mlx4_CLOSE_PORT(dev, p);
3003 }
3004
3005 if (mlx4_is_master(dev))
3006 mlx4_free_resource_tracker(dev,
3007 RES_TR_FREE_SLAVES_ONLY);
3008
3009 mlx4_cleanup_counters_table(dev);
3010 mlx4_cleanup_qp_table(dev);
3011 mlx4_cleanup_srq_table(dev);
3012 mlx4_cleanup_cq_table(dev);
3013 mlx4_cmd_use_polling(dev);
3014 mlx4_cleanup_eq_table(dev);
3015 mlx4_cleanup_mcg_table(dev);
3016 mlx4_cleanup_mr_table(dev);
3017 mlx4_cleanup_xrcd_table(dev);
3018 mlx4_cleanup_pd_table(dev);
225c7b1f 3019
befdf897
WY		 3020 if (mlx4_is_master(dev))
3021 mlx4_free_resource_tracker(dev,
3022 RES_TR_FREE_STRUCTS_ONLY);
47605df9 3023
befdf897
WY		 3024 iounmap(priv->kar);
3025 mlx4_uar_free(dev, &priv->driver_uar);
3026 mlx4_cleanup_uar_table(dev);
3027 if (!mlx4_is_slave(dev))
3028 mlx4_clear_steering(dev);
3029 mlx4_free_eq_table(dev);
3030 if (mlx4_is_master(dev))
3031 mlx4_multi_func_cleanup(dev);
3032 mlx4_close_hca(dev);
a0eacca9 3033 mlx4_close_fw(dev);
befdf897
WY		 3034 if (mlx4_is_slave(dev))
3035 mlx4_multi_func_cleanup(dev);
ffc39f6d 3036 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 3037
befdf897
WY		 3038 if (dev->flags & MLX4_FLAG_MSI_X)
3039 pci_disable_msix(pdev);
bbb07af4 3040 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
befdf897
WY		 3041 mlx4_warn(dev, "Disabling SR-IOV\n");
3042 pci_disable_sriov(pdev);
a0eacca9 3043 dev->flags &= ~MLX4_FLAG_SRIOV;
e1a5ddc5 3044 dev->num_vfs = 0;
225c7b1f 3045 }
befdf897
WY		 3046
3047 if (!mlx4_is_slave(dev))
3048 mlx4_free_ownership(dev);
3049
99ec41d0 3050 kfree(dev->caps.qp0_qkey);
befdf897
WY		 3051 kfree(dev->caps.qp0_tunnel);
3052 kfree(dev->caps.qp0_proxy);
3053 kfree(dev->caps.qp1_tunnel);
3054 kfree(dev->caps.qp1_proxy);
3055 kfree(dev->dev_vfs);
3056
befdf897
WY		 3057 memset(priv, 0, sizeof(*priv));
3058 priv->pci_dev_data = pci_dev_data;
3059 priv->removed = 1;
3060}
3061
3062static void mlx4_remove_one(struct pci_dev *pdev)
3063{
3064 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3065 struct mlx4_priv *priv = mlx4_priv(dev);
3066
e1c00e10
MD		 3067 mlx4_unload_one(pdev);
3068 pci_release_regions(pdev);
3069 pci_disable_device(pdev);
befdf897
WY		 3070 kfree(priv);
3071 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 3072}
3073
ee49bd93
JM		 3074int mlx4_restart_one(struct pci_dev *pdev)
3075{
839f1243
RD		 3076 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3077 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 3078 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3079 int pci_dev_data, err, total_vfs;
839f1243
RD		 3080
3081 pci_dev_data = priv->pci_dev_data;
e1c00e10
MD		 3082 total_vfs = dev->num_vfs;
3083 memcpy(nvfs, dev->nvfs, sizeof(dev->nvfs));
3084
3085 mlx4_unload_one(pdev);
3086 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
3087 if (err) {
3088 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3089 __func__, pci_name(pdev), err);
3090 return err;
3091 }
3092
3093 return err;
ee49bd93
JM		 3094}
3095
9baa3c34 3096static const struct pci_device_id mlx4_pci_table[] = {
ab9c17a0 3097 /* MT25408 "Hermon" SDR */
ca3e57a5 3098 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3099 /* MT25408 "Hermon" DDR */
ca3e57a5 3100 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3101 /* MT25408 "Hermon" QDR */
ca3e57a5 3102 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3103 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 3104 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3105 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 3106 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3107 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 3108 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3109 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 3110 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3111 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 3112 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3113 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 3114 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3115 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 3116 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3117 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 3118 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3119 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 3120 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 3121 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 3122 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3123 /* MT27500 Family [ConnectX-3] */
3124 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3125 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 3126 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 3127 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3128 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3129 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3130 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3131 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3132 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3133 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3134 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3135 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3136 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3137 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3138 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 3139 { 0, }
3140};
3141
3142MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3143
57dbf29a
KSS		 3144static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3145 pci_channel_state_t state)
3146{
e1c00e10 3147 mlx4_unload_one(pdev);
57dbf29a
KSS		 3148
3149 return state == pci_channel_io_perm_failure ?
3150 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
3151}
3152
3153static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3154{
befdf897
WY		 3155 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3156 struct mlx4_priv *priv = mlx4_priv(dev);
3157 int ret;
97a5221f 3158
e1c00e10 3159 ret = __mlx4_init_one(pdev, priv->pci_dev_data, priv);
57dbf29a
KSS		 3160
3161 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3162}
3163
3646f0e5 3164static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 3165 .error_detected = mlx4_pci_err_detected,
3166 .slot_reset = mlx4_pci_slot_reset,
3167};
3168
225c7b1f
RD		 3169static struct pci_driver mlx4_driver = {
3170 .name = DRV_NAME,
3171 .id_table = mlx4_pci_table,
3172 .probe = mlx4_init_one,
e1c00e10 3173 .shutdown = mlx4_unload_one,
f57e6848 3174 .remove = mlx4_remove_one,
57dbf29a 3175 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 3176};
3177
7ff93f8b
YP		 3178static int __init mlx4_verify_params(void)
3179{
3180 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 3181 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 3182 return -1;
3183 }
3184
cb29688a 3185 if (log_num_vlan != 0)
c20862c8
AV		 3186 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3187 MLX4_LOG_NUM_VLANS);
7ff93f8b 3188
ecc8fb11
AV		 3189 if (use_prio != 0)
3190 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 3191
0498628f 3192 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 3193 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3194 log_mtts_per_seg);
ab6bf42e
EC		 3195 return -1;
3196 }
3197
ab9c17a0
JM		 3198 /* Check if module param for ports type has legal combination */
3199 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 3200 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 3201 port_type_array[0] = true;
3202 }
3203
3c439b55
JM		 3204 if (mlx4_log_num_mgm_entry_size != -1 &&
3205 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3206 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
1a91de28
JP		 3207 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n",
3208 mlx4_log_num_mgm_entry_size,
3209 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3210 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 3211 return -1;
3212 }
3213
7ff93f8b
YP		 3214 return 0;
3215}
3216
225c7b1f
RD		 3217static int __init mlx4_init(void)
3218{
3219 int ret;
3220
7ff93f8b
YP		 3221 if (mlx4_verify_params())
3222 return -EINVAL;
3223
27bf91d6
YP		 3224 mlx4_catas_init();
3225
3226 mlx4_wq = create_singlethread_workqueue("mlx4");
3227 if (!mlx4_wq)
3228 return -ENOMEM;
ee49bd93 3229
225c7b1f 3230 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 3231 if (ret < 0)
3232 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3233 return ret < 0 ? ret : 0;
3234}
3235
3236static void __exit mlx4_cleanup(void)
3237{
3238 pci_unregister_driver(&mlx4_driver);
27bf91d6 3239 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 3240}
3241
3242module_init(mlx4_init);
3243module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)